Pixel driving circuit and driving method thereof, and display panel

Abstract

The pixel driving circuit (10) includes a current control circuit (100) configured to receive a display data signal and control the magnitude of a driving current flowing through the current control circuit (100) based on the display data signal, and a time control circuit (200) configured to receive the driving current, a time data signal, a first light-emitting control signal, and a second light-emitting control signal and control the passage time of the driving current based on the time data signal, the first light-emitting control signal, and the second light-emitting control signal. The pixel driving circuit (10) realizes binary unit time length control when scanning multiple times, and increases the flexibility of time length control, thereby achieving gray scale brightness correction and improving the display effect of the display panel.

Description

[Technical field]

[0001] The embodiments of the present disclosure relate to a pixel driving circuit, a driving method thereof, and a display panel. [Background technology]

[0002] Micro light emitting diode (micro LED, also abbreviated as mLED or μLED) display devices have gradually attracted widespread attention because the length of light emitting diode (LED) can be reduced to 1% of the conventional length (e.g., 100 micrometers or less, e.g., 10 micrometers to 20 micrometers) and has advantages such as higher luminance, luminous efficiency, and lower operating power consumption compared to organic light emitting diode (OLED) display devices. Due to these characteristics, micro LEDs may be applied to devices with display functions such as mobile phones, displays, notebook computers, digital cameras, instruments, and meters.

[0003] Micro LED technology, i.e. LED micro and matrix technology, can fabricate micro LEDs on an array substrate to display three colors of red, green and blue at the micrometer level. Currently, micro LED technology is based on conventional gallium nitride (GaN) LED technology. Each micro LED on the array substrate is regarded as a single pixel unit, i.e. it can be driven to light up independently, which allows the display device to display a more sensitive and contrast-rich image. Summary of the Invention

[0004] At least one embodiment of the present invention provides a pixel drive circuit comprising: a current control circuit configured to receive a display data signal and control a magnitude of a drive current flowing through the current control circuit based on the display data signal; and a time control circuit configured to receive the drive current, and to receive a time data signal, a first light-emitting control signal, and a second light-emitting control signal, and to control a passing time of the drive current based on the time data signal, the first light-emitting control signal, and the second light-emitting control signal.

[0005] For example, in a pixel driving circuit provided in an embodiment of the present disclosure, the time control circuit includes: a switching circuit having a control end and a first end, and configured to determine whether to allow the driving current to pass through the switching circuit by controlling whether the switching circuit is conductive in response to the time data signal; a time data writing circuit connected to the control end of the switching circuit and configured to write the time data signal to the control end of the switching circuit in response to a first scanning signal; a first storage circuit connected to the control end of the switching circuit and configured to store the time data signal written by the time data writing circuit; a first light-emitting control circuit connected to the first end of the switching circuit and configured to apply the driving current to the first end of the switching circuit in response to the first light-emitting control signal; and a second light-emitting control circuit connected in parallel with the first light-emitting control circuit, also connected to the first end of the switching circuit, and configured to apply the driving current to the first end of the switching circuit in response to the second light-emitting control signal.

[0006] For example, in a pixel driving circuit provided in one embodiment of the present disclosure, the time control circuit is connected to a light-emitting element, a time for driving the light-emitting element to emit light by applying the driving current to the light-emitting element via the first light-emitting control circuit and the switching circuit is a first time, a time for driving the light-emitting element to emit light by applying the driving current to the light-emitting element via the second light-emitting control circuit and the switching circuit is a compensation time, and the passing time is the sum of the first time and the correction time.

[0007] For example, in a pixel driving circuit provided in one embodiment of the present disclosure, the switching circuit includes a first transistor, a gate of the first transistor is a control end of the switching circuit, a first pole of the first transistor is a first end of the switching circuit, and a second pole of the first transistor is connected to a light-emitting element.

[0008] For example, in a pixel driving circuit provided in one embodiment of the present disclosure, the time data writing circuit includes a second transistor, a gate of the second transistor is connected to a first scan line and configured to receive the first scan signal, a first pole of the second transistor is connected to a time data line and configured to receive the time data signal, and a second pole of the second transistor is connected to a control end of the switching circuit.

[0009] For example, in a pixel driving circuit provided in one embodiment of the present disclosure, the first memory circuit includes a first capacitance, a first pole of the first capacitance is configured to be connected to a control end of the switching circuit, and a second pole of the first capacitance is connected to a first voltage end and configured to receive a first voltage.

[0010] For example, in a pixel driving circuit provided in one embodiment of the present disclosure, the first light-emitting control circuit includes a third transistor, a gate of the third transistor is connected to a first light-emitting control line and configured to receive the first light-emitting control signal, a first pole of the third transistor is configured to be connected to the current control circuit, and a second pole of the third transistor is configured to be connected to a first end of the switching circuit.

[0011] For example, in the pixel driving circuit provided in one embodiment of the present disclosure, the second light-emitting control circuit includes a fourth transistor, a gate of the fourth transistor is connected to a second light-emitting control line and configured to receive the second light-emitting control signal, a first pole of the fourth transistor is configured to be connected to the current control circuit, and a second pole of the fourth transistor is configured to be connected to a first end of the switching circuit.

[0012] For example, in a pixel driving circuit provided in one embodiment of the present disclosure, the current control circuit includes a driving circuit, a display data writing circuit, and a second memory circuit, the driving circuit includes a control end, a first end, and a second end, and is configured to control a magnitude of the driving current based on the display data signal, the display data writing circuit is connected to the first end or the control end of the driving circuit, and is configured to write the display data signal to the first end or the control end of the driving circuit in response to a second scanning signal, and the second memory circuit is connected to the control end of the driving circuit, and is configured to store the display data signal written by the display data writing circuit.

[0013] For example, in a pixel driving circuit provided in one embodiment of the present disclosure, the current control circuit further includes a compensation circuit, a third emission control circuit, and a reset circuit, the compensation circuit is connected to the control end and the second end of the driving circuit, and is configured to compensate the driving circuit in response to the second scanning signal and the display data signal written to the first end of the driving circuit, the third emission control circuit is connected to the first end of the driving circuit, and is configured to apply a second voltage of a second voltage end to the first end of the driving circuit in response to a third emission control signal, and the reset circuit is connected to the control end of the driving circuit, and applies a reset voltage of a reset voltage end to the control end of the driving circuit in response to a reset signal.

[0014] For example, in a pixel driving circuit provided in one embodiment of the present disclosure, the driving circuit includes a fifth transistor, and is configured to connect a gate of the fifth transistor as a control end of the driving circuit, a first pole of the fifth transistor as a first end of the driving circuit, and a second pole of the fifth transistor as a second end of the driving circuit to the time control circuit.

[0015] For example, in a pixel driving circuit provided in one embodiment of the present disclosure, the display data writing circuit includes a sixth transistor, a gate of the sixth transistor is connected to a second scan line and configured to receive the second scan signal, a first pole of the sixth transistor is connected to a display data line and configured to receive the display data signal, and a second pole of the sixth transistor is connected to a first end or a control end of the driving circuit.

[0016] For example, in a pixel driving circuit provided in one embodiment of the present disclosure, the second memory circuit includes a second capacitance, a first pole of the second capacitance is configured to be connected to a control end of the driving circuit, and a second pole of the second capacitance is configured to be connected to a second voltage end to receive a second voltage.

[0017] For example, in a pixel driving circuit provided in one embodiment of the present disclosure, the compensation circuit includes a seventh transistor, a gate of the seventh transistor is connected to a second scan line and configured to receive the second scanning signal, a first pole of the seventh transistor is configured to be connected to a control end of the driving circuit, and a second pole of the seventh transistor is configured to be connected to a second end of the driving circuit.

[0018] For example, in a pixel driving circuit provided in one embodiment of the present disclosure, the third light-emitting control circuit includes an eighth transistor, a gate of the eighth transistor is connected to a third light-emitting control line and configured to receive the third light-emitting control signal, a first pole of the eighth transistor is configured to be connected to the second voltage terminal, and a second pole of the eighth transistor is configured to be connected to a first terminal of the driving circuit.

[0019] For example, in a pixel driving circuit provided in one embodiment of the present disclosure, the reset circuit includes a ninth transistor, a gate of the ninth transistor is connected to a reset signal line and configured to receive the reset signal, a first pole of the ninth transistor is configured to be connected to a control end of the driving circuit, and a second pole of the ninth transistor is configured to be connected to the reset voltage end.

[0020] At least one embodiment of the present disclosure further provides a display panel including a plurality of pixel units arranged in an array, the pixel units including a pixel driving circuit according to any one of the embodiments of the present disclosure and a light-emitting element connected to the pixel driving circuit.

[0021] For example, a display panel provided in one embodiment of the present disclosure further includes at least two gate driving circuits, and the first light-emitting control signal and the second light-emitting control signal are respectively provided by different gate driving circuits among the at least two gate driving circuits.

[0022] For example, in a display panel provided in one embodiment of the present disclosure, the light emitting element comprises a light emitting diode.

[0023] At least one embodiment of the present disclosure provides a driving method for a pixel driving circuit described in any of the embodiments of the present disclosure, comprising a step of inputting the display data signal, the time data signal, the first light-emitting control signal, and the second light-emitting control signal, such that the current control circuit controls a magnitude of a driving current flowing through the current control circuit based on the display data signal, and the time control circuit receives the driving current and controls a passing time of the driving current based on the time data signal, the first light-emitting control signal, and the second light-emitting control signal.

[0024] For example, in the driving method for a pixel driving circuit provided in an embodiment of the present disclosure, the passing time includes a plurality of time lengths corresponding to different display gray scales, and the plurality of time lengths are time lengths in binary units. [Brief description of the drawings]

[0025] In order to more clearly explain the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments are briefly described below. It is apparent that the drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure. [Figure 1A] FIG. 1A is a schematic diagram of a pixel driving circuit. [Figure 1B] FIG. 1B is a signal timing diagram of the pixel driving circuit. [Diagram 2] FIG. 2 is a schematic block diagram of a pixel driving circuit provided in some embodiments of the present disclosure. [Diagram 3] FIG. 3 is a schematic block diagram of a time control circuit of a pixel driving circuit provided in some embodiments of the present disclosure. [Figure 4] FIG. 4 is a schematic block diagram of a current control circuit of a pixel driving circuit provided in some embodiments of the present disclosure. [Diagram 5]FIG. 5 is a schematic block diagram of a current control circuit of another pixel driving circuit provided in some embodiments of the present disclosure. [Figure 6] FIG. 6 is a schematic block diagram of another pixel driving circuit provided in some embodiments of the present disclosure. [Figure 7] FIG. 7 is a circuit diagram showing a specific implementation of the pixel driving circuit shown in FIG. [Figure 8] FIG. 8 is a circuit diagram showing a specific implementation of the pixel driving circuit shown in FIG. [Figure 9] FIG. 9 is a signal timing diagram of a pixel driving circuit provided in some embodiments of the present disclosure. [Figure 10] FIG. 10 is a schematic diagram of a shift register unit. [Figure 11] FIG. 11 is a schematic diagram of another shift register unit. [Figure 12] FIG. 12 is a signal timing diagram of the shift register unit. [Figure 13] FIG. 13 is a signal timing diagram of another shift register unit. [Figure 14] FIG. 14 is a schematic block diagram of a display panel provided in some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is clear that the described embodiments are not all the embodiments, but are some of the embodiments of the present disclosure. All other embodiments obtained based on the described embodiments of the present disclosure without requiring creative labor by those skilled in the art belong to the scope of protection of the present disclosure.

[0027] Unless otherwise defined, technical or scientific terms used herein should have the ordinary meaning understood by a person of ordinary skill in the field to which this disclosure belongs. The terms "first", "second" and similar terms used in this disclosure do not denote any order, quantity or importance, but are used only to distinguish different components. Similarly, similar terms such as "comprise" or "include" mean that the element or part appearing before this term covers the elements or parts listed after it and the like, but do not exclude other elements or parts. Similar terms such as "connect" and "connect" are not limited to physical or mechanical connections, but include electrical connections, which may be direct or indirect. Terms such as "upper", "lower", "left", "right" and the like are used only to indicate relative positional relationships, and when the absolute position of the objects being described changes, the relative positional relationships may change accordingly.

[0028] As a self-emitting device, the luminous efficiency of micro LEDs at low current density decreases with decreasing current density, and the color coordinates also change with the change in current density. Therefore, micro LEDs need to realize grayscale display at high current density to avoid large changes in luminous efficiency and color coordinates.

[0029] A typical pixel driving circuit applied to a micro LED adopts an 8T2C circuit, that is, it uses eight thin film transistors (TFTs) and two capacitances to realize the basic function of driving a micro LED to emit light. As shown in FIG. 1A, the pixel driving circuit is an 8T2C circuit including a current control sub-circuit 01 and a time length control sub-circuit 02. The pixel driving circuit jointly adjusts the gray scale by the magnitude of the current and the emission time. For example, the current control sub-circuit 01 includes first to fifth transistors M1-M5 and a first capacitance P1, the fourth transistor M4 is a driving transistor, and the remaining transistors are switching transistors. These transistors and the first capacitance P1 jointly function to control the magnitude of the current (i.e., the driving current) flowing through the light emitting element L0 (i.e., the micro LED). For example, a uniform current output may be realized by compensating the threshold voltage of the fourth transistor M4. For example, the time length control subcircuit 02 includes the sixth to eighth transistors M6-M8 and the second capacitor P2, and these transistors and the second capacitor P2 function together to control the light emitting time of the light emitting element L0. The screen of each frame may be composed of two or more sub-screens superimposed on each other, for which the screen of each frame needs to perform two or more operations of writing the time data signal by the time length control subcircuit 02. This method can make the micro LED operate in a high efficiency region in full gray scale, and the color coordinate drift of the micro LED in the high efficiency region is small.

[0030] The pixel driving circuit shown in Fig. 1A is driven, for example, with the signal timing shown in Fig. 1B. For example, the time length control sub-circuit 02 scans the emission control signal EM' multiple times in one frame (i.e., multiple effective levels), and employs a time data signal Vdata_t (not shown) to control the conduction or blocking of the eighth transistor M8, thereby realizing a gray scale display of multiple bits.

[0031] For example, the emission control signal EM' is generally generated by a plurality of cascaded shift register units in the gate driving circuit of the display panel. The shift register unit generally adopts, for example, a 10T3C shift register circuit. The emission control signal EM' needs to be matched with signals such as a gate scanning signal for driving the gate line and a reset signal for resetting, that is, when at least the gate scanning signal and the reset signal are at an effective level, the emission control signal EM' needs to be held at an ineffective level to prevent the light-emitting element from emitting light when it should not. Here, the effective level pulse width of the gate scanning signal of the pixel driving circuit provided in the embodiment of the present disclosure, such as the Gate1 signal or the Gate2 signal in FIG. 1B, is defined as one unit of time length and is denoted as H. In the shift register circuit that outputs the light emission control signal EM', when the two clock signals CK and CB, which have the same frequency, have a period of 2H, an effective level pulse width of 0.5H, and a duty ratio of 25%, since there are multiple shift registers having a cascade connection relationship (the output of the current row is the input of the next row), the minimum control time length of the invalid level of the light emission control signal EM' for each stage is 3H. According to the circuit characteristics of the shift register, the minimum control time length of the invalid level that can be output is equal to the minimum control time length of the effective level that can be output, so the minimum control time length of the effective level of the light emission control signal EM' for each stage is also 3H. By adjusting the duty ratio of the input signal or the start trigger signal, it is possible to output the light emission control signal EM' with an effective level pulse width of different lengths, and according to the characteristics of the 10T3C shift register circuit, it can be seen that the effective level time length of the light emission control signal EM' may be 3H+m*2H, where m is an integer equal to or greater than 0. This shows that the interval of the effective level pulse width of the signal that the shift register circuit can realize (that is, the minimum unit of increase or decrease) is 2H.

[0032] In order to accurately display each gray scale, the effective level time lengths s1, s2, s3, etc. in each scan of the light emission control signal EM' must be binary unit time lengths, i.e., s2=s1 / 2, s3=s1 / 2 2For example, the time length in binary units required for gray scale display and the effective level pulse width output by the shift register circuit are shown in the table below.

[0033] [Table 1]

[0034] As can be seen from the above table, when the signal output from the shift register circuit is used as the light emission control signal EM', the signal output from the shift register circuit can only be close to the binary unit time length at best, and cannot completely match the binary unit time length, resulting in poor gray scale brightness display on the display panel using micro LEDs. In order to improve the display quality, it is necessary to compensate the signal output from the shift register circuit for a time length of 1H, thereby realizing the binary unit time length and accurately displaying each gray scale.

[0035] At least one embodiment of the present disclosure provides a pixel driving circuit and a driving method thereof, and a display panel, which realizes binary time length control during multiple scanning, and improves the flexibility of the time length control to realize compensation for gray scale luminance and improve the display effect of the display panel.

[0036] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings, in which it should be noted that the same reference numerals in different drawings are used to refer to the same elements that have already been described.

[0037] At least one embodiment of the present disclosure provides a pixel drive circuit including a current control circuit configured to receive a display data signal and control a magnitude of a drive current flowing through the current control circuit based on the display data signal, and a time control circuit configured to receive the drive current, a time data signal, a first light-emitting control signal, and a second light-emitting control signal, and to control a passing time of the drive current based on the time data signal, the first light-emitting control signal, and the second light-emitting control signal.

[0038] The pixel driving circuit provided in the above embodiment controls the passing time of the driving current by comprehensively considering the time data signal, the first emission control signal and the second emission control signal, thereby realizing the control of the time length in binary units when multiple scans are performed, and increasing the flexibility of the time length control, thereby realizing the compensation for gray scale luminance and improving the display effect of the display panel.

[0039] 2 is a schematic block diagram of a pixel driving circuit provided in some embodiments of the present disclosure. As shown in FIG. 2, the pixel driving circuit 10 includes a current control circuit 100 and a time control circuit 200. The pixel driving circuit 10 is used, for example, in a sub-pixel or pixel unit of a micro LED display device. The time control circuit 200 is connected, for example, to a light-emitting element 300.

[0040] The current control circuit 100 is configured to receive a display data signal and control the magnitude of a driving current flowing through the current control circuit 100 based on the display data signal. For example, the current control circuit 100 is connected to a display data line (display data terminal Vdata_d), a time control circuit 200, and a separately provided high voltage terminal (not shown), receives a display data signal provided at the display data terminal Vdata_d and a high level signal provided at the high voltage terminal, and provides a driving current to the time control circuit 200. For example, the current control circuit 100 may provide a driving current to the light emitting element 300 via the time control circuit 200 during operation, so that the light emitting element 300 emits light according to the magnitude of the driving current.

[0041] The time control circuit 200 is configured to receive the driving current, receive the time data signal, the first light-emitting control signal, and the second light-emitting control signal, and control the passing time of the driving current according to the time data signal, the first light-emitting control signal, and the second light-emitting control signal. For example, the time control circuit 200 is connected to the time data line (time data terminal Vdata_t), the first light-emitting control line (first light-emitting control terminal EM1), the second light-emitting control line (second light-emitting control terminal EM2), the current control circuit 100, and the light-emitting element 300, respectively, and receives the time data signal provided at the time data terminal Vdata_t, the first light-emitting control signal provided at the first light-emitting control terminal EM1, and the second light-emitting control signal provided at the second light-emitting control terminal EM2, and provides the driving current from the current control circuit 100 to the light-emitting element 300. For example, the time control circuit 200 may control the passing time of the driving current during operation so that the light emitting element 300 receives the driving current within the corresponding time and emits light according to the magnitude of the driving current, and does not emit light during other times because it cannot receive the driving current. For example, by combining the first light emitting control signal, the second light emitting control signal, and the time data signal, there are multiple selectable values ​​for the magnitude of the passing time of the driving current, which can further increase the adjustment range of the light emitting element 300 and improve the contrast.

[0042] The light emitting device 300 is configured to receive a driving current and emit light according to the magnitude and passing time of the driving current. For example, the light emitting device 300 is connected to the time control circuit 200 and a separately provided low voltage end (not shown), and receives the driving current from the time control circuit 200 and a low level signal from the low voltage end. For example, when the time control circuit 200 is turned on to provide the driving current from the current control circuit 100 to the light emitting device 300, the light emitting device 300 emits light according to the magnitude of the driving current, and when the time control circuit 200 is turned off, the light emitting device 300 does not emit light. For example, the light emitting device 300 may adopt a light emitting diode such as a micro LED. The above operation method may jointly control the emission of the light emitting device 300 according to the magnitude of the current and the emission time to realize a corresponding gray scale, thereby improving the contrast, and may operate the light emitting device 300 in a region with high luminous efficiency in a complete gray scale, and may have little color coordinate drift.

[0043] In this embodiment, by adopting two emission control signals, i.e., the first emission control signal and the second emission control signal, the emission time of the light emitting element 300 can be compensated compared with the case of adopting only one emission control signal. For example, the time length that the first emission control signal of the first emission control end EM1 can realize is the above-mentioned 3H+m*2H, and the time length that the second emission control signal of the second emission control end EM2 can realize is H. Thus, the time length of 3H+m*2H can be realized by the cooperation of the first emission control signal and the second emission control signal, and the time length of 3H+m*2H+H can also be realized. Therefore, the above-mentioned binary unit time length (for example, 48H, 24H, 12H, 6H, 3H, etc.) can be realized. Thus, when the pixel driving circuit 10 is scanned multiple times, the control of the time length in binary units is realized, and the flexibility of the time length control is increased, so that the compensation for the gray scale luminance can be realized, and the display effect of the display panel can be improved.

[0044] For example, the first emission control signal of the first emission control terminal EM1 and the second emission control signal of the second emission control terminal EM2 are provided by different gate driving circuits, so that the effective level pulse width (i.e., time length 3H+m*2H) of the first emission control signal and the effective level pulse width (i.e., time length H) of the second emission control signal can be adjusted independently. Therefore, the effective level pulse width of the second emission control signal can be adjusted more flexibly, the adjustment range of the emission time of the light emitting device 300 can be increased, and the adjustment precision of the emission time of the light emitting device 300 can be improved, thereby realizing the control of the time length in binary units and the compensation for gray scale luminance.

[0045] In some embodiments of the present disclosure, the current control circuit 100, the time control circuit 200, and the light emitting element 300 are connected between a high voltage end and a low voltage end provided separately, and are used to provide a current path for the driving current. Therefore, the order in which the current control circuit 100, the time control circuit 200, and the light emitting element 300 are connected between the high voltage end and the low voltage end is not limited, and may be any order, as long as a current path from the high voltage end to the low voltage end is provided.

[0046] For example, the display data terminal Vdata_d and the time data terminal Vdata_t may be connected to the same signal line and configured to receive the display data signal and the time data signal at different times, thereby reducing the number of signal lines. Of course, the embodiment of the present disclosure is not limited thereto. The display data terminal Vdata_d and the time data terminal Vdata_t may be connected to different signal lines, thereby allowing the display data signal and the time data signal to be received simultaneously and without affecting each other.

[0047] 3 is a schematic block diagram of a time control circuit of a pixel driving circuit provided in some embodiments of the present disclosure. As shown in FIG. 3, the time control circuit 200 includes a switching circuit 210, a time data writing circuit 220, a first memory circuit 230, a first light emission control circuit 240, and a second light emission control circuit 250.

[0048] The switching circuit 210 includes a control end 211 and a first end 212, and is configured to determine whether or not the driving current is allowed to pass through the switching circuit 210 by controlling whether the switching circuit 210 is conductive in response to the time data signal. For example, the switching circuit 210 is connected to a first node N1 and a second node N2, and is also connected to the light-emitting element 300, receives the time data signal written to the first node N1, and provides the driving current from the second node N2 to the light-emitting element 300. For example, the switching circuit 210 may be turned on under the control of the time data signal in operation to provide the driving current to the light-emitting element 300, and may be cut off under the control of the time data signal to prevent the driving current from being provided to the light-emitting element 300.

[0049] The time data writing circuit 220 is connected to the control end 211 of the switching circuit 210, and configured to write a time data signal to the control end 211 of the switching circuit 210 in response to a first scanning signal. For example, the time data writing circuit 220 is respectively connected to a time data line (time data end Vdata_t), a first node N1, and a first scanning line (first scanning end Gate1), and receives a time data signal provided at the time data end Vdata_t and a first scanning signal provided at the first scanning end Gate1, respectively. For example, the time data writing circuit 220 can be turned on in response to the first scanning signal, write a time data signal to the control end 211 (first node N1) of the switching circuit 210, and store the time data signal in the first storage circuit 230.

[0050] The first storage circuit 230 is connected to the control end 211 of the switching circuit 210 and configured to store the time data signal written by the time data writing circuit 220. For example, the first storage circuit 230 may be connected to the first node N1, store the time data signal written to the first node N1, and use the stored time data signal to control the switching circuit 210. For example, the first storage circuit 230 may also be connected to a voltage end (e.g., a first voltage end Vcom described below) provided separately to realize a voltage storage function.

[0051] The first light-emitting control circuit 240 is connected to the first end 212 of the switching circuit 210 and configured to apply a driving current to the first end 212 of the switching circuit 210 in response to a first light-emitting control signal. For example, the first light-emitting control circuit 240 is respectively connected to the first light-emitting control line (first light-emitting control end EM1) and the first end 212 (second node N2) of the switching circuit 210, and is also connected to the current control circuit 100 to respectively receive the first light-emitting control signal of the first light-emitting control end EM1 and the driving current provided by the current control circuit 100. For example, the first light-emitting control circuit 240 may be turned on in response to the first light-emitting control signal, electrically connect the current control circuit 100 and the second node N2, and apply the driving current to the second node N2.

[0052] The second light-emitting control circuit 250 is connected in parallel to the first light-emitting control circuit 240, and is also connected to the first end 212 of the switching circuit 210, and is configured to apply a driving current to the first end 212 of the switching circuit 210 in response to a second light-emitting control signal. For example, the second light-emitting control circuit 250 is respectively connected to the second light-emitting control line (second light-emitting control end EM2) and the first end 212 (second node N2) of the switching circuit 210, and is also connected to the current control circuit 100 to respectively receive the second light-emitting control signal at the second light-emitting control end EM2 and the driving current provided by the current control circuit 100. For example, the second light-emitting control circuit 250 may be turned on in response to the second light-emitting control signal, electrically connect the current control circuit 100 and the second node N2, and apply the driving current to the second node N2.

[0053] For example, the first light-emitting control circuit 240 and the second light-emitting control circuit 250 are turned on at different times, and thus respectively apply the driving current from the current control circuit 100 to the second node N2 at these different times. When the switching circuit 210 is also turned on, the driving current is further applied to the light-emitting element 300 to drive the light-emitting element 300 to emit light. For example, the time during which the driving current is applied to the light-emitting element 300 via the first light-emitting control circuit 240 and the switching circuit 210 to drive the light-emitting element 300 to emit light is a first time (e.g., 0 or 3H+m*2H), the time during which the driving current is applied to the light-emitting element 300 via the second light-emitting control circuit 250 and the switching circuit 210 to drive the light-emitting element 300 to emit light is a compensation time (e.g., 0 or H), and the light-emitting time of the light-emitting element 300 (i.e., the passing time described above) is the sum of the first time and the compensation time. This method makes it possible to realize a time length of 3H+m*2H or 3H+m*2H+H, and to realize control of the time length in binary units.

[0054] In addition, in some embodiments of the present disclosure, the time control circuit 200 is not limited to the above-mentioned switching circuit 210, the time data writing circuit 220, the first memory circuit 230, the first light-emitting control circuit 240, and the second light-emitting control circuit 250, and may include any applicable circuit or module as long as it can achieve the appropriate function.

[0055] 4 is a schematic block diagram of a current control circuit of a pixel driving circuit provided in some embodiments of the present disclosure. As shown in FIG. 4, the current control circuit 100 includes a driving circuit 110, a display data writing circuit 120, and a second storage circuit 130.

[0056] The driving circuit 110 includes a first end 111, a second end 112, and a control end 113, and is configured to control the magnitude of the driving current according to a display data signal. For example, the control end 113 of the driving circuit 110 is connected to the second storage circuit 130, the first end 111 of the driving circuit 110 is connected to a second voltage end VDD, and the second end 112 of the driving circuit 110 is connected to the time control circuit 200. For example, the second voltage end VDD is configured to hold the input of a DC high level signal, and the DC high level is called a second voltage, which is the same in each of the following embodiments and will not be described repeatedly. For example, the driving circuit 110 may provide a driving current to the light-emitting element 300 through the time control circuit 200 (for example, the switching circuit 210 and the first light-emitting control circuit 240 or the second light-emitting control circuit 250 in the time control circuit 200) to drive the light-emitting element 300 to emit light, and may drive the light-emitting element 300 to emit light according to a required gray level (or gray scale).

[0057] The display data writing circuit 120 is connected to the first end 111 of the driving circuit 110, and configured to write a display data signal to the first end 111 of the driving circuit 110 in response to a second scanning signal. For example, the display data writing circuit 120 is respectively connected to a display data line (display data end Vdata_d), the first end 111 of the driving circuit 110 (third node N3), and a second scanning line (second scanning end Gate2). For example, the second scanning signal from the second scanning end Gate2 is applied to the display data writing circuit 120 to control whether the display data writing circuit 120 is on or off. For example, the display data writing circuit 120 may be turned on in response to the second scanning signal, and write the display data signal provided at the display data end Vdata_d to the first end 111 of the driving circuit 110 (third node N3). The display data signal may then be stored in the second storage circuit 130 via the drive circuit 110, and a drive current for driving the light emitting element 300 to emit light may be generated based on the display data signal.

[0058] It should be noted that, in the embodiments of the present disclosure, there is no limitation on the specific connection manner between the display data writing circuit 120 and the driving circuit 110. For example, in some embodiments, the display data writing circuit 120 may be connected to the control end 113 of the driving circuit 110, write a display data signal to the control end 113 of the driving circuit 110, and store it in the second storage circuit 130.

[0059] The second storage circuit 130 is connected to the control end 113 of the driving circuit 110, and is configured to store the display data signal written by the display data writing circuit 120. For example, the second storage circuit 130 may store the display data signal and use the stored display data signal to control the driving circuit 110. For example, the second storage circuit 130 may be connected to a second voltage end VDD or a high voltage end provided separately to realize a voltage storage function.

[0060] 5 is a schematic block diagram of a current control circuit of another pixel driving circuit provided in some embodiments of the present disclosure. As shown in FIG. 5, the current control circuit 100 may further include a compensation circuit 140, a third light emission control circuit 150, and a reset circuit 160, and other configurations are basically the same as the current control circuit 100 shown in FIG. 4.

[0061] The compensation circuit 140 is connected to the control end 113 and the second end 112 of the driving circuit 110, and is configured to compensate the driving circuit 110 in response to a second scanning signal and a display data signal written to the first end 111 of the driving circuit 110. For example, the compensation circuit 140 is connected to a second scanning line (second scanning end Gate2), a fourth node N4, and a fifth node N5. For example, the second scanning signal from the second scanning end Gate2 is applied to the compensation circuit 140 to control the on / off of the compensation circuit 140. For example, the compensation circuit 140 may turn on in response to a second scanning signal, electrically connect the control end 113 (fourth node N4) and the second end 112 (fifth node N5) of the driving circuit 110, and store both the threshold voltage information of the driving circuit 110 and the display data signal written by the display data writing circuit 120 in the second memory circuit 130, thereby controlling the driving circuit 110 so that its output is corrected using a voltage value including the stored display data signal and threshold voltage information.

[0062] The third light-emitting control circuit 150 is connected to the first end 111 of the driving circuit 110, and is configured to apply a second voltage at the second voltage end VDD to the first end 111 of the driving circuit 110 in response to a third light-emitting control signal. For example, the third light-emitting control circuit 150 is respectively connected to the third light-emitting control line (third light-emitting control end EM3), the second voltage end VDD, and the third node N3. For example, the third light-emitting control circuit 150 may be turned on in response to a third light-emitting control signal provided at the third light-emitting control end EM3, and apply a second voltage to the first end 111 (third node N3) of the driving circuit 110. When the driving circuit 110 and the time control circuit 200 are both on, the driving circuit 110 applies the second voltage to the light-emitting element 300 via the time control circuit 200, thereby providing a driving voltage and driving the light-emitting element 300 to emit light. In order to reduce the number of signal lines, the third light-emitting control signal may be the same as the first light-emitting control signal, or may be an independent signal different from the first light-emitting control signal, but this is not limited in the embodiment of the present disclosure.

[0063] The reset circuit 160 is connected to the control end 113 of the driving circuit 110, and configured to apply a reset voltage at a reset voltage end Vint to the control end 113 of the driving circuit 110 in response to a reset signal. For example, the reset circuit 160 is connected to a fourth node N4, a reset voltage end Vint, and a reset signal line (reset signal end RST), respectively. For example, the reset circuit 160 turns on in response to a reset signal provided at the reset signal end RST, and applies a reset voltage provided at the reset voltage end Vint to the control end 113 (fourth node N4) of the driving circuit 110, thereby performing a reset operation on the driving circuit 110 and the second memory circuit 130, thereby eliminating the influence of the previous light-emitting stage. In addition, the reset voltage applied by the reset circuit 160 may be stored in the second memory circuit 130. This allows the driving circuit 110 to remain on, and when the next display data signal is to be written, the display data signal is easily written to the second storage circuit 130 via the driving circuit 110 and the compensation circuit 140.

[0064] FIG. 6 is a schematic block diagram of another pixel driving circuit provided in some embodiments of the present disclosure. As shown in FIG. 6, the current control circuit 100 of the pixel driving circuit 10 is basically the same as the current control circuit 100 shown in FIG. 5, and the time control circuit 200 of the pixel driving circuit 10 is basically the same as the time control circuit 200 shown in FIG. 3. The specific connection relationship and related description of the pixel driving circuit 10 can be referred to above, and will not be repeated here. It should be noted that the pixel driving circuit 10 provided in the embodiments of the present disclosure may further include other circuit configurations, such as a circuit configuration having other compensation functions. The compensation function may be realized by voltage compensation and current compensation, or a combination of compensation. This is not limited in the embodiments of the present disclosure.

[0065] In addition, in some embodiments of the present disclosure, the pixel driving circuit 10 may be obtained by combining the time control circuit 200 with any other pixel driving circuit having a control function for the magnitude of the driving current, and is not limited to the above configuration. It is sufficient that the pixel driving circuit 10 provided in the embodiments of the present disclosure can commonly control the gray scale by the magnitude of the current and the light emission time, and can be commonly controlled by the first light emission control signal and the second light emission control signal to realize the time length in binary units.

[0066] FIG. 7 is a circuit diagram showing a specific implementation of the pixel driving circuit shown in FIG. 6. As shown in FIG. 7, the pixel driving circuit 10 includes first to ninth transistors T1-T9, and includes a first capacitance C1 and a second capacitance C2. The pixel driving circuit 10 is also connected to a light-emitting element L1. For example, the fifth transistor T5 is used as a driving transistor, and the other transistors are used as switching transistors. For example, the light-emitting element L1 may be various kinds of micro LEDs that emit red, green, blue, or white light, etc. This is not limited in the embodiments of the present disclosure.

[0067] For example, the switching circuit 210 may be realized as a first transistor T1. A gate of the first transistor T1 is connected to a first node N1 as a control end 211 of the switching circuit 210, a first pole of the first transistor T1 is connected to a second node N2 as a first end 212 of the switching circuit 210, and a second pole of the first transistor T1 is connected to the light-emitting element L1 (e.g., connected to the anode of the light-emitting element L1). Note that the embodiment of the present disclosure is not limited thereto, and the switching circuit 210 may be a circuit formed by other means.

[0068] The time data writing circuit 220 may be realized as a second transistor T2. The gate of the second transistor T2 is connected to the first scanning line (first scanning end Gate1) and configured to receive the first scanning signal, the first pole of the second transistor T2 is connected to the time data line (time data end Vdata_t) and configured to receive the time data signal, and the second pole of the second transistor T2 is connected to the control end 211 (first node N1) of the switching circuit 210. Note that the embodiment of the present disclosure is not limited to this, and the time data writing circuit 220 may be a circuit composed of other means.

[0069] The first storage circuit 230 may be realized as a first capacitance C1. A first pole of the first capacitance C1 is configured to be connected to the control end 211 (first node N1) of the switching circuit 210, and a second pole of the first capacitance C1 is configured to be connected to the first voltage end Vcom to receive a first voltage. For example, the first voltage end Vcom is configured to hold an input of a DC low level signal, for example, to hold ground, and the DC low level is called a first voltage, which is the same in each of the following embodiments and will not be described again here. Note that the embodiments of the present disclosure are not limited to this, and the first storage circuit 230 may be a circuit composed of other means.

[0070] The first light emission control circuit 240 may be realized as a third transistor T3. The gate of the third transistor T3 is configured to be connected to the first light emission control line (first light emission control end EM1), the first pole of the third transistor T3 is configured to be connected to the current control circuit 100 to receive the driving current, and the second pole of the third transistor T3 is configured to be connected to the first end 212 (second node N2) of the switching circuit 210. Note that the embodiment of the present disclosure is not limited to this, and the first light emission control circuit 240 may be a circuit composed of other means.

[0071] The second light emission control circuit 250 may be realized as a fourth transistor T4. The gate of the fourth transistor T4 is configured to be connected to the second light emission control line (second light emission control end EM2), the first pole of the fourth transistor T4 is configured to be connected to the current control circuit 100 to receive the driving current, and the second pole of the fourth transistor T4 is configured to be connected to the first end 212 (second node N2) of the switching circuit 210. Note that the embodiment of the present disclosure is not limited to this, and the second light emission control circuit 250 may be a circuit composed of other means.

[0072] The driving circuit 110 may be realized as a fifth transistor T5. The fifth transistor T5 is configured such that the gate of the fifth transistor T5 is connected to the fourth node N4 as the control end 113 of the driving circuit 110, the first pole of the fifth transistor T5 is connected to the third node N3 as the first end 111 of the driving circuit 110, the second pole of the fifth transistor T5 is connected to the fifth node N5 as the second end 112 of the driving circuit 110, and is connected to the time control circuit 200 (e.g., connected to the first pole of the third transistor T3 and the first pole of the fourth transistor T4). Note that the embodiment of the present disclosure is not limited to this, and the driving circuit 110 may be a circuit composed of other means. For example, the driving circuit 110 may have two driving transistors that can be switched according to specific situations.

[0073] The display data writing circuit 120 may be realized as a sixth transistor T6. The gate of the sixth transistor T6 is connected to the second scanning line (second scanning end Gate2) and configured to receive the second scanning signal, the first pole of the sixth transistor T6 is connected to the display data line (display data end Vdata_d) and configured to receive the display data signal, and the second pole of the sixth transistor T6 is connected to the first end 111 (third node N3) of the driving circuit 110. Note that, in the embodiment of the present disclosure, there is no limitation on the connection relationship between the sixth transistor T6 and the fifth transistor T5. For example, in some other embodiments, when the compensation circuit 140 is not provided, the second pole of the sixth transistor T6 may be connected to the gate of the fifth transistor T5 to write the display data signal to the gate of the fifth transistor T5. The display data writing circuit 120 may be a circuit composed of other means, and this is not limited in the embodiment of the present disclosure.

[0074] The second storage circuit 130 may be realized as a second capacitance C2. A first pole of the second capacitance C2 is configured to be connected to the control end 113 (fourth node N4) of the drive circuit 110, and a second pole of the second capacitance C2 is configured to be connected to the second voltage end VDD to receive the second voltage. Note that the embodiment of the present disclosure is not limited to this, and the second storage circuit 130 may be a circuit composed of other means. For example, the second storage circuit 130 may include two capacitances connected in parallel / series to each other.

[0075] The compensation circuit 140 may be realized as a seventh transistor T7. The gate of the seventh transistor T7 is configured to be connected to the second scanning line (second scanning end Gate2) to receive the second scanning signal, the first pole of the seventh transistor T7 is configured to be connected to the control end 113 (fourth node N4) of the driving circuit 110, and the second pole of the seventh transistor T7 is configured to be connected to the second end 112 (fifth node N5) of the driving circuit 110. Note that the embodiment of the present disclosure is not limited to this, and the compensation circuit 140 may be a circuit composed of other means.

[0076] The third light emission control circuit 150 may be realized as an eighth transistor T8. The gate of the eighth transistor T8 is connected to a third light emission control line (third light emission control terminal EM3) and configured to receive a third light emission control signal, the first pole of the eighth transistor T8 is configured to be connected to a second voltage terminal VDD, and the second pole of the eighth transistor T8 is configured to be connected to a first terminal 111 (third node N3) of the drive circuit 110. Note that the embodiment of the present disclosure is not limited to this, and the third light emission control circuit 150 may be a circuit composed of other means.

[0077] The reset circuit 160 may be realized as a ninth transistor T9. The gate of the ninth transistor T9 is connected to a reset signal line (reset signal terminal RST) and configured to receive a reset signal, the first pole of the ninth transistor T9 is connected to a control terminal 113 (fourth node N4) of the driving circuit 110, and the second pole of the ninth transistor T9 is connected to a reset voltage terminal Vint and configured to receive a reset voltage. Note that the embodiment of the present disclosure is not limited to this, and the reset circuit 160 may be a circuit composed of other means.

[0078] The light-emitting element 300 may be realized as a light-emitting element L1 (e.g., a micro LED). A first end (here, an anode) of the light-emitting element L1 is connected to the second pole of the first transistor T1, and a second end (here, a cathode) of the light-emitting element L1 is connected to a third voltage end VSS to receive a third voltage. For example, the third voltage end VSS is configured to hold an input of a DC low level signal, for example, to hold ground, and the DC low level is called a third voltage, which is the same in each embodiment below and will not be described again here. For example, in some embodiments, the third voltage end VSS may be connected to the same voltage end as the first voltage end Vcom. For example, when the pixel driving circuits 10 are arranged in an array in one display panel, the cathodes of the light-emitting element L1 may be electrically connected to the same voltage end, that is, a common cathode connection method is adopted.

[0079] For example, in the embodiment, the third transistor T3 and the fourth transistor T4 are connected in parallel between the fifth node N5 and the second node N2, so that the driving current can be transmitted between the fifth node N5 and the second node N2 through either the third transistor T3 or the fourth transistor T4. For example, the eighth transistor T8, the fifth transistor T5, the first transistor T1, the light-emitting element L1, or either the third transistor T3 or the fourth transistor T4 is connected between the second voltage end VDD and the third voltage end VSS to provide a current path for the driving current, so that the light-emitting element L1 emits light when driven by the driving current. Note that, in some embodiments of the present disclosure, the connection order of the eighth transistor T8, the fifth transistor T5, the first transistor T1, the light-emitting element L1, the third transistor T3, and the fourth transistor T4 is not limited to the situation shown in the figure, and may be any appropriate connection order. It is only necessary to provide a current path for the driving current, and the third transistor T3 and the fourth transistor T4 are connected in parallel to the current path.

[0080] Fig. 8 is a circuit diagram showing a specific implementation of the pixel driving circuit shown in Fig. 2. As shown in Fig. 8, the pixel driving circuit 10 includes the first to fourth transistors T1-T4, the tenth transistor T10, the eleventh transistor T11, the first capacitance C1, and the third capacitance C3. The pixel driving circuit 10 is also connected to the light-emitting element L1. The connection method of the first to fourth transistors T1-T4, the first capacitance C1, and the light-emitting element L1 is basically the same as that of the pixel driving circuit 10 shown in Fig. 7, and will not be described again here.

[0081] In this embodiment, the current control circuit 100 only includes the driving circuit 110, the display data writing circuit 120, and the second storage circuit 130, and the current control circuit 100 may be realized as a basic 2T1C circuit. For example, as shown in FIG. 8, the driving circuit 110 may be realized as a tenth transistor T10. The gate of the tenth transistor T10 is configured to be connected to the display data writing circuit 120, the first pole of the tenth transistor T10 is configured to be connected to the second voltage terminal VDD, and the second pole of the tenth transistor T10 is configured to be connected to the first pole of the third transistor T3. The display data writing circuit 120 may be realized as an eleventh transistor T11. The gate of the eleventh transistor T11 is configured to be connected to the second scan line (second scan end Gate2) to receive the second scan signal, the first electrode of the eleventh transistor T11 is configured to be connected to the display data line (display data end Vdata_d) to receive the display data signal, and the second electrode of the eleventh transistor T11 is configured to be connected to the gate of the tenth transistor T10. The second storage circuit 130 may be realized as a third capacitance C3. The first electrode of the third capacitance C3 is configured to be connected to the gate of the tenth transistor T10, and the second electrode of the third capacitance C3 is configured to be connected to the second voltage end VDD.

[0082] In addition, in some embodiments of the present disclosure, the current control circuit 100 in the pixel driving circuit 10 may be realized as a pixel driving circuit of any ordinary configuration, such as 2T1C, 4T1C, 4T2C, etc. Accordingly, there is no restriction on the connection order between the transistors (e.g., the first transistor T1, the third transistor T3, and the fourth transistor T4) that provide the current path of the driving current in the time control circuit 200 and the driving transistors in the circuits such as 2T1C, 4T1C, and 4T2C, and for example, in some other embodiments, the tenth transistor T10 may be connected between the first transistor T1 and the light-emitting element L1.

[0083] In addition, in the description of each embodiment of the present disclosure, the first node N1, the second node N2, the third node N3, the fourth node N4, and the fifth node N5 indicate the junctions of related electrical connections in the circuit diagram, rather than actual components.

[0084] The transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics, and the embodiments of the present disclosure will be described using thin film transistors as an example. The source and drain of the transistors used here may be structurally symmetrical, and therefore the source and drain may not be structurally distinct. In the embodiments of the present disclosure, in order to distinguish between the two poles of the transistor other than the gate, one of them is directly described as a first pole and the other as a second pole.

[0085] In addition, the transistors in the embodiments of the present disclosure are all described as P-type transistors, in which case the first pole of the transistor is the source and the second pole is the drain. However, the present disclosure includes but is not limited to the above situation. For example, one or more transistors in the pixel driving circuit 10 provided in the embodiments of the present disclosure may adopt N-type transistors. In this case, the first pole of the transistor is the drain and the second pole is the source. Each pole of the selected type of transistor may be respectively connected with reference to each pole of the corresponding transistor in the embodiments of the present disclosure, and the corresponding voltage terminal and signal terminal may provide a corresponding high level signal or low level signal. When N-type transistors are adopted, indium gallium zinc oxide (IGZO) may be adopted as the active layer of the thin film transistor. Compared with the case where low temperature polysilicon (LTPS) or amorphous silicon (e.g., hydrogenated amorphous silicon) is adopted as the active layer of the thin film transistor, the size of the transistor can be effectively reduced and current leakage can also be prevented. When P-type transistors are employed, low temperature polycrystalline silicon (LTPS) or amorphous silicon (eg, hydrogenated amorphous silicon) may be employed as the active layer of the thin film transistor.

[0086] 9 is a signal timing diagram of a pixel driving circuit provided in some embodiments of the present disclosure. The operation principle of the pixel driving circuit 10 shown in FIG. 7 will be described below with reference to the signal timing diagram shown in FIG. 9. Here, each transistor is taken as an example for description. That is, the gate of each transistor is conductive when connected to a low level, and is cut off when connected to a high level, but the embodiments of the present disclosure are not limited thereto.

[0087] In Fig. 9 and the following description, RST, Gate1, Gate2, EM1, EM2, EM3, Vdata_d, Vdata_t, etc. are used to represent corresponding signal ends and corresponding signals. In the first to thirteenth steps 1-13 shown in Fig. 9, the pixel driving circuit 10 may respectively perform the following operations:

[0088] In the first phase 1, the reset signal terminal RST provides a low level signal, the ninth transistor T9 is turned on, and the low level signal (not shown) of the reset voltage terminal Vint is input to the fourth node N4. The gate of the fifth transistor T5 and the second capacitor C2 are reset by the low level of the fourth node N4. In addition, the fifth transistor T5 is turned on by the low level of the fourth node N4 so as to write the display data signal in the next phase, and the conductive state is maintained until the next phase.

[0089] In the second stage 2, the second scanning end Gate2 and the display data end Vdata_d provide a low level signal, and the sixth transistor T6 and the seventh transistor T7 are both conductive. The fifth transistor T5 is maintained conductive. Thus, the display data signal provided at the display data end Vdata_d is written to the fourth node N4 through the path formed by the sixth transistor T6, the fifth transistor T5, and the seventh transistor T7, and is stored in the second capacitor C2. It can be easily understood that the potential of the third node N3 is maintained at Vdata_d, and the fifth transistor T5 is cut off and the charging process is terminated when the potential of the fourth node N4 becomes Vdata_d+Vth due to the characteristics of the fifth transistor T5 itself. Here, Vth represents the threshold voltage of the fifth transistor T5. In this embodiment, the fifth transistor T5 is a P-type transistor, so the threshold voltage Vth here may be a negative value. Because the potential of the fourth node N4 is Vdata_d+Vth, the display data signal Vdata_d and related information including the threshold voltage Vth are stored in the second capacitor C2, and are used to provide display data in the later light-emitting stage and compensate for the threshold voltage Vth of the fifth transistor T5 itself.

[0090] In the third stage 3, the third light-emitting control terminal EM3 provides a low-level signal, and the eighth transistor T8 is turned on. At this time, the potential of the fourth node N4 is Vdata_d+Vth, and the potential of the third node N3 is VDD, so that the fifth transistor T5 is turned on. The first scanning terminal Gate1 and the time data terminal Vdata_t provide low-level signals, and the second transistor T2 is turned on, so that the time data signal provided by the time data terminal Vdata_t is written to the first node N1 and stored in the first capacitor C1. The first transistor T1 is turned on by the low level of the first node N1. The first light-emitting control terminal EM1 and the second light-emitting control terminal EM2 provide high-level signals, so that the third transistor T3 and the fourth transistor T4 are both cut off, and the light-emitting element L1 does not emit light in this stage. However, in another example, in this case, the time data edge Vdata_t may provide a high level signal, in response to which the first transistor T1 is turned off.

[0091] In the fourth stage 4, the eighth transistor T8, the fifth transistor T5, and the first transistor T1 are kept conductive. The first light-emitting control terminal EM1 provides a low-level signal, and the third transistor T3 is turned on. The second voltage terminal VDD, the eighth transistor T8, the fifth transistor T5, the third transistor T3, the first transistor T1, the light-emitting element L1, and the third voltage terminal VSS form one current path, so that the light-emitting element L1 is driven by the driving current to emit light. At this time, the magnitude of the driving current is determined by the display data signal Vdata_d written in the second stage 2, and whether or not the light-emitting element L1 emits light is determined by the time data signal Vdata_t written in the third stage 3. In addition, when the light-emitting element emits light, the light-emitting time is the same as the effective level pulse width t1 of the first light-emitting control signal EM1 in that stage. However, in some other embodiments, if a high level signal is provided at the time data end Vdata_t in the third stage 3, the first transistor T1 is kept turned off and the light emitting element L1 does not emit light in this stage.

[0092] For example, the driving current I L1 The value of can be obtained by the following formula:

number

[0093] In the above formula, Vth represents the threshold voltage of the fifth transistor T5, and V GS represents the voltage between the gate and source (here, the first pole) of the fifth transistor T5, and K is a constant value related to the fifth transistor T5 itself. As can be seen from the above formula, the driving current I L1 Since the threshold voltage Vth of the fifth transistor T5 is no longer related to the threshold voltage Vth of the fifth transistor T5, the compensation of the pixel driving circuit 10 can be realized, and the driving transistor (e.g., the fifth transistor T5) solves the problem of threshold voltage drift due to the manufacturing process and long-term operation, and the driving current I L1 By eliminating the influence on the pixel driving circuit 10, the display effect of the display device using the pixel driving circuit 10 can be improved.

[0094] In the fifth stage 5, the eighth transistor T8, the fifth transistor T5, and the first transistor T1 are kept conductive. The second light-emitting control terminal EM2 provides a low-level signal. The fourth transistor T4 is made conductive. Since one current path is formed by the second voltage terminal VDD, the eighth transistor T8, the fifth transistor T5, the fourth transistor T4, the first transistor T1, the light-emitting element L1, and the third voltage terminal VSS, the light-emitting element L1 is driven by the driving current and continues to emit light. At this time, the magnitude of the driving current is determined by the display data signal Vdata_d written in the second stage 2, and is also the same as the magnitude of the driving current in the fourth stage 4. Whether or not to emit light is determined by the time data signal Vdata_t written in the third stage 3, and when emitting light, the light-emitting time is the same as the effective level pulse width x1 of the second light-emitting control signal EM2 in that stage. However, in some other embodiments, if a high level signal is provided at the time data end Vdata_t in the third stage 3, the first transistor T1 is kept turned off and the light emitting element L1 does not emit light in this stage.

[0095] In the sixth stage 6, the first light-emitting control end EM1 and the second light-emitting control end EM2 both provide high-level signals, and the third transistor T3 and the fourth transistor T4 are both turned off, so that the current path of the driving current is cut off and the light-emitting element L1 does not emit light.

[0096] In the seventh stage 7, the eighth transistor T8 and the fifth transistor T5 are kept conductive. The first scanning end Gate1 and the time data end Vdata_t provide low level signals, the second transistor T2 is conductive, and the time data signal provided at the time data end Vdata_t is written to the first node N1 and stored in the first capacitor C1. The first transistor T1 is conductive under the effect of the low level of the first node N1. Since the first light-emitting control end EM1 and the second light-emitting control end EM2 provide high level signals, the third transistor T3 and the fourth transistor T4 are both cut off, and the light-emitting element L1 does not emit light in this stage. It should be noted that in some other embodiments, the time data end Vdata_t may provide a high level signal in this case, and the first transistor T1 is cut off accordingly.

[0097] In the eighth stage 8, the eighth transistor T8, the fifth transistor T5, and the first transistor T1 are kept conductive. The first light-emitting control terminal EM1 provides a low-level signal, and the third transistor T3 is turned on. A current path is formed by the second voltage terminal VDD, the eighth transistor T8, the fifth transistor T5, the third transistor T3, the first transistor T1, the light-emitting element L1, and the third voltage terminal VSS, so that the light-emitting element L1 is driven by the driving current to emit light. At this time, the magnitude of the driving current is determined by the display data signal Vdata_d written in the second stage 2 as it is, and whether or not to emit light is determined by the time data signal Vdata_t written in the seventh stage 7. When emitting light, the light-emitting time is the same as the effective level pulse width t2 of the first light-emitting control signal EM1 in this stage. However, in some other embodiments, if a high level signal is provided at the time data edge Vdata_t in the seventh stage 7, the first transistor T1 is kept turned off and the light emitting element L1 does not emit light in this stage.

[0098] In the ninth stage 9, the eighth transistor T8, the fifth transistor T5, and the first transistor T1 are kept conductive. The second light-emitting control terminal EM2 provides a low-level signal, and the fourth transistor T4 is made conductive. Since one current path is formed by the second voltage terminal VDD, the eighth transistor T8, the fifth transistor T5, the fourth transistor T4, the first transistor T1, the light-emitting element L1, and the third voltage terminal VSS, the light-emitting element L1 is driven by the driving current and continues to emit light. In this case, the magnitude of the driving current is determined as it is by the display data signal Vdata_d written in the second stage 2, and whether or not to emit light is determined by the time data signal Vdata_t written in the seventh stage 7, and when emitting light, the light-emitting time is the same as the effective level pulse width x2 of the second light-emitting control signal EM2 in that stage. However, in some other embodiments, if a high level signal is provided at the time data edge Vdata_t in the seventh stage 7, the first transistor T1 is kept turned off and the light emitting element L1 does not emit light in this stage.

[0099] In the tenth stage 10, the first light-emitting control end EM1 and the second light-emitting control end EM2 both provide high-level signals, and the third transistor T3 and the fourth transistor T4 are both turned off, so that the current path of the driving current is cut off and the light-emitting element L1 does not emit light.

[0100] In the eleventh stage 11, the eighth transistor T8 and the fifth transistor T5 are kept conductive. The first scanning end Gate1 and the time data end Vdata_t provide low level signals, the second transistor T2 is conductive, and the time data signal provided at the time data end Vdata_t is written to the first node N1 and stored in the first capacitor C1. The first transistor T1 is conductive under the effect of the low level of the first node N1. Since the first light-emitting control end EM1 and the second light-emitting control end EM2 provide high level signals, the third transistor T3 and the fourth transistor T4 are both cut off, and the light-emitting element L1 does not emit light in this stage. It should be noted that in some other embodiments, the time data end Vdata_t may provide a high level signal in this case, and the first transistor T1 is cut off accordingly.

[0101] In the twelfth stage 12, the eighth transistor T8, the fifth transistor T5, and the first transistor T1 are kept conductive. The first light-emitting control terminal EM1 provides a low-level signal, and the third transistor T3 is turned on. The second voltage terminal VDD, the eighth transistor T8, the fifth transistor T5, the third transistor T3, the first transistor T1, the light-emitting element L1, and the third voltage terminal VSS form one current path, so that the light-emitting element L1 is driven by the driving current to emit light. At this time, the magnitude of the driving current is determined as it is by the display data signal Vdata_d written in the second stage 2, and whether or not to emit light is determined by the time data signal Vdata_t written in the eleventh stage 11, and when emitting light, the light-emitting time is the same as the effective level pulse width t3 of the first light-emitting control signal EM1 in this stage. However, in some other embodiments, if a high level signal is provided at the time data end Vdata_t in the eleventh stage 11, the first transistor T1 is kept turned off and the light emitting element L1 does not emit light in this stage.

[0102] In the thirteenth stage 13, the eighth transistor T8, the fifth transistor T5 and the first transistor T1 are kept conductive. The second light-emitting control terminal EM2 provides a low-level signal, and the fourth transistor T4 is made conductive. Since one current path is formed by the second voltage terminal VDD, the eighth transistor T8, the fifth transistor T5, the fourth transistor T4, the first transistor T1, the light-emitting element L1 and the third voltage terminal VSS, the light-emitting element L1 is driven by the driving current and continues to emit light. At this time, the magnitude of the driving current is determined as it is by the display data signal Vdata_d written in the second stage 2, and whether or not to emit light is determined by the time data signal Vdata_t written in the eleventh stage 11, and when emitting light, the light-emitting time is the same as the effective level pulse width x3 of the second light-emitting control signal EM2 in that stage. However, in some other embodiments, if a high level signal is provided at the time data end Vdata_t in the eleventh stage 11, the first transistor T1 is kept turned off and the light emitting element L1 does not emit light in this stage.

[0103] For example, in the display process, the screen for each frame is formed by overlapping the screens displayed in one or more periods of the fourth stage 4 (t1 period), the fifth stage 5 (x1 period), the eighth stage 8 (t2 period), the ninth stage 9 (x2 period), the twelfth stage 12 (t3 period) and the thirteenth stage 13 (x3 period). For example, in the screen for each frame, the pixel driving circuit 10 scans multiple times so that the time data signal Vdata_t is written multiple times, and the light emission times corresponding to the multiple scans are t1+x1, t2+x2, and t3+x3, respectively. For example, the times of t1+x1, t2+x2, and t3+x3 are different from each other, and t1+x1, t2+x2, and t3+x3 may be the time lengths in binary units as described above. For example, in one example, t1+x1=48H, t2+x2=24H, t3+x3=12H. t1, t2, t3 are, for example, the time length 3H+m*2H described above, and t1, t2, t3 can be different. x1, x2, x3 are, for example, the time length H described above, and the three can be, for example, the same. In the above embodiment, the first light-emitting control signal EM1 controls the light-emitting times t1, t2, t3, and the second light-emitting control signal EM2 controls the light-emitting times x1, x2, x3 to compensate for the difference between t1, t2, t3 and the time length in binary units, thereby achieving compensation for grayscale luminance. In this way, when scanning multiple times, the control of the time length in binary units can be achieved, and the flexibility of the time length control can be increased, thereby improving the display effect of the display panel.

[0104] In the above embodiment, the t1 period and the x1 period are continuous and do not overlap each other, but in some embodiments, the t1 period and the x1 period may be continuous and partially overlap each other, and in some embodiments, the t1 period and the x1 period may not be continuous with each other. The total length in the time domain of t1+x1 only needs to satisfy the requirement. For example, t1+x1=48H as above. Similarly, the t2 period and the x2 period are continuous and do not overlap each other, but in some embodiments, the t2 period and the x2 period may be continuous and partially overlap each other, and in some embodiments, the t2 period and the x2 period may not be continuous with each other. The total length in the time domain of t2+x2 only needs to satisfy the requirement. For example, t2+x2=24H as above. Similarly, the t3 period and the x3 period are consecutive and do not overlap each other, but in some embodiments, the t3 period and the x3 period may be consecutive and partially overlap each other, and in some embodiments, the t3 period and the x3 period may not be consecutive each other. It is only necessary that the total length in the time domain of t3+x3 meets the requirement. For example, t3+x3=12H as above.

[0105] For example, the time data signal Vdata_t written in the third step 3 is Vdata1, the time data signal Vdata_t written in the seventh step 7 is Vdata2, and the time data signal Vdata_t written in the eleventh step 11 is Vdata3. The three time data signals Vdata1, Vdata2, and Vdata3 may be set to high or low levels as required (i.e., may be set to logic "1" or logic "0"). When Vdata1, Vdata2, and Vdata3 are "0", "0", and "0", respectively, that is, as shown in FIG. 9, the light-emitting element L1 emits light in periods t1, x1, t2, x2, t3, and x3, and the frame screen is formed by overlapping the corresponding screens. For example, in another example, when Vdata1, Vdata2, and Vdata3 are "1", "1", and "0", respectively, the light-emitting element L1 emits light only in periods t3 and x3, and the frame screen is formed by overlapping the corresponding screens. It should be noted that Vdata1, Vdata2 and Vdata3 can be set as necessary and are not limited to the setting methods described in the above example. Therefore, the screen for each frame has various overlapping methods to meet the gray level requirements and improve the contrast.

[0106] In some embodiments of the present disclosure, the time data signals Vdata1, Vdata2 and Vdata3 determine whether the light-emitting element L1 emits light in the corresponding period, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 determine the light-emitting time of the light-emitting element L1 in the corresponding period, and the display data signal Vdata_d determines the magnitude of the driving current, thereby jointly controlling the screen for each display frame with the above parameters.

[0107] In addition, while the embodiment has been described using an example of performing three scans (i.e., writing of time data signals three times) within one frame, this does not constitute a limitation on the embodiments of the present disclosure, and the number of scans may be any number, such as four or five, depending on actual needs.

[0108] It should be noted that in some embodiments of the present disclosure, the specific time lengths of t1, t2, t3, x1, x2, and x3 are not limited, and the specific time lengths of t1+x1, t2+x2, and t3+x3 are not limited, and may be determined according to actual needs, and are not limited to the manner described in the above example. In addition, the specific time lengths of x1, x2, and x3 may be the same or different. This may be determined according to actual needs, and is not limited in the embodiments of the present disclosure.

[0109] In this embodiment, the third light-emitting control signal EM3 is different from the first light-emitting control signal EM1. However, in some other embodiments of the present disclosure, the third light-emitting control signal EM3 may be the same signal as the first light-emitting control signal EM1, thereby reducing the number of signal lines. The third light-emitting control signal EM3 may be another signal having a waveform different from that shown in FIG. 9. It is sufficient that the effective level section of the third light-emitting control signal EM3 includes the effective level section of the first light-emitting control signal or is the same as the effective level section of the first light-emitting control signal. This is not a limitation in the embodiments of the present disclosure.

[0110] For example, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 may be provided by a cascaded shift register unit in a conventional gate driving circuit. For example, they may be provided by an 8T2C circuit as shown in FIG. 10, or a 10T3C circuit as shown in FIG. 11, or other suitable circuits, which are not limited in the embodiments of the present disclosure. The operation principles of the 8T2C circuit shown in FIG. 10 and the 10T3C circuit shown in FIG. 11 may refer to the conventional design and will not be described here. Next, the output signal of the 8T2C circuit shown in FIG. 10 will be briefly described in conjunction with the signal timing shown in FIG. 12.

[0111] For example, the first scanning signal Gate1, the second scanning signal Gate2, the first light-emitting control signal EM1, and the second light-emitting control signal EM2 are provided by 8T2C circuits, that is, four 8T2C circuits are adopted to provide the above four signals. In FIG. 12, G1_STV, G1_CK, and G1_CB signals correspond to the GSTV, GCK, and GCB signals in the 8T2C circuit providing the first scanning signal Gate1. G2_STV, G2_CK, and G2_CB signals correspond to the GSTV, GCK, and GCB signals in the 8T2C circuit providing the second scanning signal Gate2. ESTV1, ECK1, and ECB1 signals correspond to the GSTV, GCK, and GCB signals in the 8T2C circuit providing the first light-emitting control signal EM1. ESTV2, ECK2, and ECB2 signals correspond to the GSTV, GCK, and GCB signals in the 8T2C circuit providing the second light-emitting control signal EM2. For example, the effective level pulse width of the ECK1 and ECB1 signals is 0.5H, and the duty ratio is 25%. Figure 12 also shows signals corresponding to two adjacent rows of pixel units. Gate1(1), Gate2(1), EM1(1), EM2(1), Vdata_d(1) and Vdata_t(1) correspond to the first scanning signal Gate1, the second scanning signal Gate2, the first emission control signal EM1, the second emission control signal EM2, the display data signal Vdata_d and the time data signal Vdata_t of the pixel unit in the first row. Gate1(2), Gate2(2), EM1(2), EM2(2), Vdata_d(2), and Vdata_t(2) correspond to the first scanning signal Gate1, the second scanning signal Gate2, the first emission control signal EM1, the second emission control signal EM2, the display data signal Vdata_d, and the time data signal Vdata_t of the pixel unit in the second row.

[0112] As can be seen from FIG. 12, the first scanning signal Gate1 and the second scanning signal Gate2 both have an effective level pulse width of 1H, and the effective level pulse width of the reset signal RST is also 1H. For example, the second scanning signal Gate2 of the adjacent previous row may be multiplexed with the reset signal RST of the current row. In this embodiment, the display data signal Vdata_d and the time data signal Vdata_t for the first scanning are written in the same period for each row of pixel units, so that more time is left for subsequent operations and the light-emitting element L1 has a longer light-emitting time. During the effective level pulse width period (e.g., t1 period or t2 period) of the first light-emitting control signal EM1, the light-emitting element L1 emits light. After the first light-emitting control signal EM1 becomes an inactive level, the second light-emitting control signal EM2 becomes an effective level (e.g., x1 period or x2 period), and the light-emitting element L1 continues to emit light, thereby achieving compensation of the light-emitting time, and the light-emitting time of the light-emitting element L1 becomes a binary unit time length.

[0113] Similarly, the 10T3C circuit shown in FIG. 11 may adopt the signal timing as shown in FIG. 13. The signal timing is basically the same as the signal timing shown in FIG. 12, and will not be described again here. In addition, in some embodiments of the present disclosure, the circuit configuration of the shift register unit for providing the first light-emitting control signal EM1 and the second light-emitting control signal EM2 is not limited, and accordingly, the signal timing and operation method of the shift register unit are not limited, as long as it can provide the first light-emitting control signal EM1 and the second light-emitting control signal EM2 that meet the requirements. For example, the shift register unit for providing the first light-emitting control signal EM1 may have the same circuit configuration as or different from the shift register unit for providing the second light-emitting control signal EM2. In the embodiments of the present disclosure, this is not limited.

[0114] At least one embodiment of the present disclosure further provides a display panel including a plurality of pixel units arranged in an array, the pixel units including a pixel driving circuit according to any one embodiment of the present disclosure and a light emitting element connected to the pixel driving circuit, the display panel can realize binary time length control during multiple scanning, and can improve the flexibility of the time length control to realize correction for gray scale luminance and improve the display effect of the display panel.

[0115] 14 is a schematic block diagram of a display panel provided in some embodiments of the present disclosure. As shown in FIG. 14, a display panel 2000 is installed in a display device 20, and is electrically connected to gate drivers 2011, 2012 and a data driver 2030. The display device 20 further includes a timing controller 2020. The display panel 2000 includes pixel units P defined by the intersections of a plurality of scan lines GL and a plurality of data lines DL. The gate driver 2011 is used to drive a plurality of scan lines GL1. The gate driver 2012 is used to drive a plurality of scan lines GL2. The data driver 2030 is used to drive a plurality of data lines DL. The timing controller 2020 processes image data RGB input from outside the display device 20, provides the processed image data RGB to the data driver 2030, and outputs scan control signals GCS and data control signals DCS to the gate drivers 2011, 2012 and the data driver 2030 to control the gate drivers 2011, 2012 and the data driver 2030.

[0116] For example, the display panel 2000 includes a plurality of pixel units P. The pixel units P include a pixel driving circuit 10 provided in any one of the above embodiments. For example, the pixel unit P includes a pixel driving circuit 10 as shown in FIG. 7 or FIG. 8. The pixel unit P further includes a light-emitting element, for example a light-emitting diode (for example a micro LED), connected to the pixel driving circuit 10. As shown in FIG. 14, the display panel 2000 further includes a plurality of scan lines GL1, GL2 and a plurality of data lines DL. For example, the pixel unit P is disposed in an intersection area of ​​the scan lines GL1, GL2 and the data lines DL. For example, each pixel unit P is connected to five scanning lines GL1 (providing a first scanning signal, a second scanning signal, a reset signal, a first light emission control signal, and a third light emission control signal), one scanning line GL2 (providing a second light emission control signal), two data lines DL (providing a display data signal and a time data signal, respectively), a first voltage line for providing a first voltage, a second voltage line for providing a second voltage, and a third voltage line for providing a third voltage. For example, the first voltage line, the second voltage line, or the third voltage line may be replaced with a corresponding plate-shaped common electrode (e.g., a common anode or a common cathode). Note that only some pixel units P, scanning lines GL1, GL2, and data lines DL are shown in FIG. 14.

[0117] For example, the display panel 2000 includes at least two gate driving circuits. For example, the display panel 2000 includes at least a gate driver 2011 and a gate driver 2012, and the first light-emitting control signal and the second light-emitting control signal are provided by different gate driving circuits among the two gate driving circuits. For example, the first light-emitting control signal is provided by the gate driver 2011, and the second light-emitting control signal is provided by the gate driver 2012. The second light-emitting control signal is provided by a single gate driver 2012 and does not need to be matched with other signals, so that the time length H can be realized. For example, the gate driver 2011 may further include multiple gate driving sub-circuits for respectively providing a first scanning signal, a second scanning signal, a reset signal, a first light-emitting control signal, a third light-emitting control signal, etc. For example, the gate drivers 2011 and 2012 may be fabricated on an array substrate to configure a GOA (Gate-driver On Array).

[0118] For example, the gate drivers 2011, 2012 provide a plurality of selection signals to the plurality of scan lines GL1, GL2 through a plurality of scan control signals GCS from the timing controller 2020. The plurality of selection signals include a first scan signal, a second scan signal, a reset signal, a first light-emitting control signal, a second light-emitting control signal, and a third light-emitting control signal, etc. These signals are provided to each pixel unit P through the plurality of scan lines GL1, GL2.

[0119] For example, the data driver 2030 converts the digital image data RGB input from the timing controller 2020 into a display data signal and a time data signal by a plurality of data control signals DCS from the timing controller 2020 using the reference gamma voltage. The data driver 2030 provides the converted display data signal and time data signal to a plurality of data lines DL. For example, the data driver 2030 may be connected to a plurality of first voltage lines, a plurality of second voltage lines and a plurality of third voltage lines to provide a first voltage, a second voltage and a third voltage, respectively.

[0120] For example, the timing controller 2020 processes externally inputted graphic data RGB to match the size and resolution of the display panel 2000, and provides the processed graphic data to the data driver 2030. The timing controller 2020 generates a plurality of scan control signals GCS and a plurality of data control signals DCS using synchronization signals (e.g., a dot clock DCLK, a data enable signal DE, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync) inputted from the outside of the display device 20. The timing controller 2020 provides the generated scan control signals GCS and data control signals DCS to the gate drivers 2011, 2012 and the data driver 2030, respectively, for controlling the gate drivers 2011, 2012 and the data driver 2030.

[0121] For example, the gate drivers 2011, 2012 and the data driver 2030 may be implemented as semiconductor chips. The display device 20 may further include other components, such as a signal decoding circuit, a voltage conversion circuit, etc. These components may be, for example, existing conventional components, and will not be described in detail herein.

[0122] For example, the display panel 2000 may be applied to any product or component with a display function, such as an e-book, a mobile phone, a tablet, a television, a display, a notebook computer, a digital photo frame, a navigation system, etc. For example, the display panel 2000 may be a micro LED display panel.

[0123] At least one embodiment of the present disclosure further provides a driving method for the pixel driving circuit according to any one embodiment of the present disclosure, which can realize binary unit time length control during multiple scanning, and improve the flexibility of time length control to realize correction for gray scale luminance and improve the display effect of the display panel.

[0124] For example, in one embodiment, the driving method of the pixel driving circuit 10 includes the following operations.

[0125] By inputting the display data signal, the time data signal, the first light-emitting control signal, and the second light-emitting control signal, the current control circuit 100 controls the magnitude of the drive current flowing through the current control circuit 100 based on the display data signal, and the time control circuit 200 receives the drive current and controls the passing time of the drive current based on the time data signal, the first light-emitting control signal, and the second light-emitting control signal.

[0126] For example, in one example, the passing time of the driving current includes a plurality of time lengths corresponding to different display gray scales, and the plurality of time lengths are time lengths in binary units (e.g., 48H, 24H, 12H, 6H, 3H, etc., as mentioned above). For example, the pixel driving circuit 10 is connected to the light emitting element 300, and the light emitting element 300 receives the driving current and is driven by the driving current, and emits light according to the current magnitude and passing time of the driving current.

[0127] For a detailed description of the driving method, reference may be made to the operation principle of the pixel driving circuit 10 and the display panel 2000 in the embodiment of the present disclosure, and the description will not be repeated here.

[0128] A few points need to be explained:

[0129] (1) The drawings of the embodiments of the present disclosure relate only to configurations of some of the embodiments of the present disclosure, and other configurations may refer to the general design.

[0130] (2) Where no conflict exists, the embodiments and features of the embodiments of the present disclosure may be combined with each other to obtain new embodiments.

[0131] Although what has been described above are only specific embodiments of the present disclosure, the scope of protection of the present disclosure is not limited thereto, and the scope of protection of the present disclosure should be in accordance with the scope of protection of the claims described herein.

Claims

1. a current control circuit configured to receive a display data signal and control a current magnitude of a drive current flowing through the current control circuit based on the display data signal; a time control circuit configured to receive the driving current, and to receive a time data signal, a first light-emitting control signal, and a second light-emitting control signal, and to control a passing time of the driving current based on the time data signal, the first light-emitting control signal, and the second light-emitting control signal; In a pixel driving circuit comprising: The time control circuit includes: a switching circuit having a control end and a first end, and configured to determine whether to allow the driving current to pass through the switching circuit by controlling whether the switching circuit is conductive or not in response to the time data signal; a time data writing circuit connected to a control end of the switching circuit and configured to write the time data signal into the control end of the switching circuit in response to a first scanning signal; a first storage circuit connected to a control end of the switching circuit and configured to store the time data signal written by the time data writing circuit; a first light emission control circuit coupled to a first end of the switching circuit and configured to apply the drive current to the first end of the switching circuit in response to the first light emission control signal; a second emission control circuit connected in parallel with the first emission control circuit, and thereby also connected to a first end of the switching circuit, and configured to apply the drive current to the first end of the switching circuit in response to the second emission control signal; It is equipped with the time control circuit is connected to the light emitting device; a time period during which the light-emitting element is driven to emit light by applying the drive current to the light-emitting element via the first light-emitting control circuit and the switching circuit; a time for driving the light-emitting element by applying the driving current to the light-emitting element via the second light-emitting control circuit and the switching circuit so that the light-emitting element emits light is a compensation time that compensates for a difference between the first time and a time length in binary units; a transit time of the drive current is a sum of the first time and the compensation time.

2. the switching circuit comprises a first transistor; 2. The pixel driving circuit according to claim 1, wherein a gate of the first transistor is a control end of the switching circuit, a first pole of the first transistor is a first end of the switching circuit, and a second pole of the first transistor is connected to a light-emitting element.

3. the time data writing circuit comprises a second transistor; 3. The pixel driving circuit according to claim 1, wherein a gate of the second transistor is connected to a first scan line and configured to receive the first scan signal, a first pole of the second transistor is connected to a time data line and configured to receive the time data signal, and a second pole of the second transistor is connected to a control end of the switching circuit.

4. the first storage circuit includes a first capacitance; 4. The pixel drive circuit of claim 1, wherein a first pole of the first capacitance is configured to be connected to a control end of the switching circuit, and a second pole of the first capacitance is connected to a first voltage end to receive a first voltage.

5. the first light emission control circuit includes a third transistor; 5. The pixel driving circuit according to claim 1, wherein a gate of the third transistor is connected to a first light emission control line and configured to receive the first light emission control signal, a first pole of the third transistor is configured to be connected to the current control circuit, and a second pole of the third transistor is configured to be connected to a first end of the switching circuit.

6. the second light emission control circuit includes a fourth transistor; 6. The pixel driving circuit according to claim 1, wherein a gate of the fourth transistor is connected to a second light emission control line and configured to receive the second light emission control signal, a first pole of the fourth transistor is configured to be connected to the current control circuit, and a second pole of the fourth transistor is configured to be connected to a first end of the switching circuit.

7. the current control circuit includes a drive circuit, a display data writing circuit, and a second memory circuit; the driving circuit has a control end, a first end and a second end, and is configured to control a current magnitude of the driving current based on the display data signal; the display data writing circuit is connected to a first end or a control end of the driving circuit, and configured to write the display data signal to the first end or the control end of the driving circuit in response to a second scanning signal; 7. The pixel driving circuit according to claim 1, wherein the second storage circuit is connected to a control end of the driving circuit and configured to store the display data signal written by the display data writing circuit.

8. the current control circuit further includes a compensation circuit, a third light emission control circuit, and a reset circuit; the compensation circuit is connected to a control end and a second end of the driving circuit, and is configured to compensate the driving circuit in response to the second scanning signal and the display data signal written to the first end of the driving circuit; the third light emission control circuit is connected to the first end of the drive circuit and configured to apply a second voltage of a second voltage end to the first end of the drive circuit in response to a third light emission control signal; 8. The pixel driving circuit according to claim 7, wherein the reset circuit is connected to a control end of the driving circuit and configured to apply a reset voltage at a reset voltage end to the control end of the driving circuit in response to a reset signal.

9. the drive circuit comprises a fifth transistor; 9. The pixel driving circuit according to claim 7 or 8, wherein a gate of the fifth transistor is connected to the control end of the driving circuit, a first pole of the fifth transistor is connected to the first end of the driving circuit, and a second pole of the fifth transistor is connected to the time control circuit as the second end of the driving circuit.

10. the display data writing circuit includes a sixth transistor; 10. The pixel driving circuit according to claim 7, wherein a gate of the sixth transistor is connected to a second scan line and configured to receive the second scan signal, a first pole of the sixth transistor is connected to a display data line and configured to receive the display data signal, and a second pole of the sixth transistor is connected to a first end or a control end of the driving circuit.

11. the second storage circuit includes a second capacitance; 11. The pixel drive circuit of claim 7, wherein a first pole of the second capacitance is configured to be connected to a control end of the drive circuit, and a second pole of the second capacitance is connected to a second voltage end to receive a second voltage.

12. the compensation circuit comprises a seventh transistor; 9. The pixel driving circuit of claim 8, wherein a gate of the seventh transistor is connected to a second scan line to receive the second scan signal, a first pole of the seventh transistor is connected to a control end of the driving circuit, and a second pole of the seventh transistor is connected to a second end of the driving circuit.

13. the third light emission control circuit includes an eighth transistor; 13. The pixel driving circuit of claim 8 or 12, wherein a gate of the eighth transistor is connected to a third light emission control line and configured to receive the third light emission control signal, a first pole of the eighth transistor is configured to be connected to the second voltage terminal, and a second pole of the eighth transistor is configured to be connected to a first terminal of the driving circuit.

14. the reset circuit comprises a ninth transistor; 14. The pixel driving circuit of claim 8, wherein a gate of the ninth transistor is connected to a reset signal line to receive the reset signal, a first pole of the ninth transistor is configured to be connected to a control terminal of the driving circuit, and a second pole of the ninth transistor is configured to be connected to the reset voltage terminal.

15. A display panel comprising a plurality of pixel units arranged in an array, the pixel units comprising the pixel drive circuit according to claim 1 and a light emitting element connected to the pixel drive circuit.

16. Further comprising at least two gate drive circuits; The display panel of claim 15 , wherein the first light-emitting control signal and the second light-emitting control signal are provided by different gate drive circuits among the at least two gate drive circuits.

17. 17. The display panel according to claim 15, wherein the light emitting element comprises a light emitting diode.

18. 15. A method for driving a pixel drive circuit according to claim 1, comprising a step of inputting the display data signal, the time data signal, the first light-emitting control signal, and the second light-emitting control signal, so that the current control circuit controls a magnitude of the drive current flowing through the current control circuit based on the display data signal, and the time control circuit receives the drive current and controls a passing time of the drive current based on the time data signal, the first light-emitting control signal, and the second light-emitting control signal.

19. 20. The driving method of a pixel driving circuit according to claim 18, wherein the passing time includes a plurality of time lengths corresponding to different display gray scales, and the plurality of time lengths are time lengths in binary units.

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