Driving circuit and display device using same

Abstract

To reduce the generation of luminance difference at a time point of a refresh rate change, to prevent viewers from perceiving the variation of the refresh rate.SOLUTION: A display device comprises an electroluminescent element comprising a pixel electrode and a cathode electrode, a pixel comprising a pixel circuit configured to drive the electroluminescent element, and a driver configured to generate a signal for driving the pixel circuit. An electroluminescent display device uses a variable refresh rate (VRR) mode in which the pixel is driven through a refresh frame period and a hold frame period.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] [CROSS REFERENCE TO RELATED APPLICATIONS] This application claims the benefit of Korean Patent Application No. 10-2020-0103392, filed on August 18, 2020, the entire contents of which are hereby incorporated by reference for all purposes as if fully set forth herein. [Background technology]

[0002] The present disclosure relates to electroluminescent display devices using a variable refresh rate (VRR) mode, which is designed to reduce the occurrence of luminance differences when the refresh rate changes.

[0003] Electroluminescent display devices using electroluminescent elements such as organic light emitting diodes can be driven at a variety of driving frequencies.

[0004] Recently, variable refresh rate (VRR) has become one of the many features required for display devices. VRR is a technology that drives a display device at a constant frequency, increases the refresh rate to activate pixels when high-speed driving is required, and reduces the refresh rate to drive pixels when power consumption needs to be reduced or low-speed driving is required.

[0005] If the refresh rate at which the data voltage is updated according to the VRR changes, the viewer may perceive the change in refresh rate as unnatural. Therefore, it is necessary to prevent the viewer from perceiving the change in refresh rate. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2016-118664 A Summary of the Invention [Problem to be solved by the invention]

[0007] The present disclosure relates to an electroluminescent display device using a variable refresh rate (VRR) mode, and an objective of the present disclosure is to reduce the occurrence of luminance differences when the refresh rate changes, thereby preventing the viewer from perceiving the change in refresh rate.

[0008] The present disclosure provides a means for solving the above problems, and has the following embodiments. [Means for solving the problem]

[0009] One embodiment discloses a display device including a pixel including an electroluminescent element including a pixel electrode and a cathode electrode, and a pixel circuit configured to drive the electroluminescent element, and a driver configured to generate a signal for driving the pixel circuit. The pixel is driven through a refresh frame period and a hold frame period. The pixel circuit includes a drive transistor having a source electrode, a drain electrode, and a gate electrode and providing a drive current to the electroluminescent element, a compensation transistor configured to connect the drain electrode and the gate electrode of the drive transistor according to a first scan signal provided by the driver, a first bias transistor configured to apply a first bias voltage to the drain electrode of the drive transistor according to a second scan signal provided by the driver, and a second bias transistor configured to apply a second bias voltage to the pixel electrode of the electroluminescent element according to the second scan signal provided by the driver. The first bias voltage has a first voltage and a second voltage higher than the first voltage. When the compensation transistor performs an off operation, the second voltage is applied to the drain electrode of the drive transistor, and the first and second bias transistors perform an on operation. Before and after switching from a first refresh rate to a second refresh rate lower than the first refresh rate, the second voltage of the first bias voltage or the second bias voltage is dynamically controlled.

[0010] Another embodiment discloses a display device including an electroluminescent element, a drive transistor configured to provide a drive current to the electroluminescent element, and a drive driver to dynamically control a first bias voltage and a second bias voltage before and after switching from a first refresh rate to a second refresh rate, where the first bias voltage is applied to the drive transistor and the second bias voltage is applied to the electroluminescent element.

[0011] Yet another embodiment discloses a display driver for driving a pixel circuit connected to an electroluminescent element including a pixel electrode and a cathode electrode. The display driver is configured to generate a signal for driving the pixel circuit to switch between a first refresh rate and a second refresh rate lower than the first refresh rate. The pixel is driven through a refresh frame period and a hold frame period. The pixel circuit includes a drive transistor having a source electrode, a drain electrode, and a gate electrode and providing a drive current to the electroluminescent element, a compensation transistor configured to connect the drain electrode and the gate electrode of the drive transistor according to a first scan signal provided by the driver, a first bias transistor configured to apply a first bias voltage to the drain electrode of the drive transistor according to a second scan signal provided by the driver, and a second bias transistor configured to apply a second bias voltage to the pixel electrode of the electroluminescent element according to the second scan signal provided by the driver. The first bias voltage has a first voltage and a second voltage higher than the first voltage in an on-bias stress phase. In the on-bias stress phase, the compensation transistor performs an off operation, and the first and second bias transistors perform an on operation. Before and after switching from the first refresh rate to the second refresh rate, the second voltage of the first bias voltage or the second bias voltage is dynamically controlled.

[0012] Another embodiment discloses a display driver. A frame is divided into a refresh period in which a data voltage is written and a hold period in which the data voltage written in the refresh period is maintained. The frame dynamically controls a first bias voltage and a second bias voltage before and after switching from a first refresh rate to a second refresh rate. The first bias voltage is applied to a drain electrode of a driving transistor. The second bias voltage is applied to a pixel electrode of an electroluminescent element.

[0013] The second voltage of the first bias voltage is controlled to a voltage higher by a first level in a first refresh frame period after switching to the second refresh rate.

[0014] The second voltage of the first bias voltage is controlled to a voltage higher by a second level lower than the first level in a refresh period following the first refresh frame period after switching to the second refresh rate.

[0015] The second bias voltage is controlled to a voltage lower by a first level in a first refresh frame period after switching to the second refresh rate.

[0016] The second voltage of the first bias voltage is controlled to a voltage lower by a first level in the hold frame period after switching to the second refresh rate.

[0017] The second bias voltage is controlled to a voltage higher by the first level in the hold frame period after switching to the second refresh rate.

[0018] The second bias voltage is controlled to a voltage higher by the first level in the hold frame period immediately before switching to the second refresh rate.

[0019] After switching to the second refresh rate, the second voltage of the first bias voltage is controlled to a voltage higher by a first level in the refresh frame period and to a voltage lower by the first level in the hold frame period.

[0020] The second voltage of the first bias voltage is controlled to a voltage higher by a first level in the hold frame period immediately before switching to the second refresh rate.

[0021] The drawings, which are provided to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and explain the principles of the invention with reference to the accompanying drawings, in which: [Brief description of the drawings]

[0022] [Figure 1] 1 is a block diagram illustrating an electroluminescent display device according to an embodiment of the present invention; [Figure 2A] 1 is a circuit diagram of a pixel circuit of an electroluminescence display device according to an embodiment of the present invention; [Figure 2B] 1 is a circuit diagram of a pixel circuit of an electroluminescence display device according to an embodiment of the present invention; [Figure 2C] 1 is a circuit diagram of a pixel circuit of an electroluminescence display device according to an embodiment of the present invention; [Figure 3A] 2A to 2C. FIG. 2B is a diagram for explaining driving of an electroluminescence element and a refresh frame in a pixel circuit of the display device shown in FIGS. 2A to 2C. [Figure 3B] 2A to 2C. FIG. 2B is a diagram for explaining driving of an electroluminescence element and a refresh frame in a pixel circuit of the display device shown in FIGS. 2A to 2C. [Figure 3C] 2A to 2C. FIG. 2B is a diagram for explaining driving of an electroluminescence element and a refresh frame in a pixel circuit of the display device shown in FIGS. 2A to 2C. [Figure 3D] 2A to 2C. FIG. 2B is a diagram for explaining driving of an electroluminescence element and a refresh frame in a pixel circuit of the display device shown in FIGS. 2A to 2C. [Figure 3E] 2A to 2C. FIG. 2B is a diagram for explaining driving of an electroluminescence element and a refresh frame in a pixel circuit of the display device shown in FIGS. 2A to 2C. [Figure 3F] 2A to 2C. FIG. 2B is a diagram for explaining driving of an electroluminescence element and a refresh frame in a pixel circuit of the display device shown in FIGS. 2A to 2C. [Figure 3G] 2A to 2C. FIG. 2B is a diagram for explaining driving of an electroluminescence element and a refresh frame in a pixel circuit of the display device shown in FIGS. 2A to 2C. [Figure 3H] 2A to 2C. FIG. 2B is a diagram for explaining driving of an electroluminescence element and a refresh frame in a pixel circuit of the display device shown in FIGS. 2A to 2C. [Figure 3I] 2A to 2C. FIG. 2B is a diagram for explaining driving of an electroluminescence element and a refresh frame in a pixel circuit of the display device shown in FIGS. 2A to 2C. [Figure 3J] 2A to 2C. FIG. 2B is a diagram for explaining driving of an electroluminescence element and a refresh frame in a pixel circuit of the display device shown in FIGS. 2A to 2C. [Figure 3K] 2A to 2C. FIG. 2B is a diagram for explaining driving of an electroluminescence element and a refresh frame in a pixel circuit of the display device shown in FIGS. 2A to 2C. [Figure 4A] 2C。 FIG. 2C is a diagram for explaining the driving of an electroluminescence element and a hold frame pixel circuit in the pixel circuit of the display device shown in FIG. 2A to FIG. 2C. [Figure 4B] 2C。 FIG. 2C is a diagram for explaining the driving of an electroluminescence element and a hold frame pixel circuit in the pixel circuit of the display device shown in FIG. 2A to FIG. 2C. [Figure 4C]2C。 FIG. 2C is a diagram for explaining the driving of an electroluminescence element and a hold frame pixel circuit in the pixel circuit of the display device shown in FIG. 2A to FIG. 2C. [Diagram 5] FIG. 5 is a diagram illustrating the problem of luminance difference occurring when the refresh rate is switched from 60 Hz to 1 Hz using the VRR mode. [Figure 6] FIG. 6 is a diagram for explaining a first method of brightness deviation compensation driving. [Figure 7] FIG. 7 is a diagram illustrating a second method of brightness deviation compensation driving. [Figure 8] FIG. 8 is a diagram for explaining a third method of brightness deviation compensation driving. [Figure 9] FIG. 9 is a diagram for explaining a fourth method of brightness deviation compensation driving. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] The following detailed description will be given with reference to the embodiments and drawings, which will make clear the features, advantages and methods of achieving the present invention. However, the present invention is not limited to the embodiments disclosed below, and may be implemented in various different forms. The embodiments are provided only for the purpose of providing a complete disclosure of the present invention and enabling those skilled in the art to fully understand the scope of the present invention. The present invention is defined only by the claims. In the present disclosure, the same elements are designated by the same reference numerals.

[0024] A reference to a component being "connected" or "coupled" to another component includes both the case where the component is directly connected or coupled to the other component and the case where there are additional intervening components therebetween, whereas a reference to a component being "directly connected" or "directly coupled" to another component means that there are no additional intervening components therebetween. The term "and / or" includes each of the listed items and all combinations of one or more of them.

[0025] The terms used in this specification are provided to describe only certain embodiments of the present invention and are not intended to limit the present invention. In the present specification, the singular form includes the plural form unless otherwise specified. The term "comprises" used in this specification is intended to specify the characteristics, numbers, steps, operations, components, parts, or any combination thereof described in this specification, and is not intended to exclude the presence or addition of at least one of other characteristics, numbers, steps, operations, components, parts, or any combination thereof.

[0026] Terms such as first, second, etc. may be used to describe various components, but the components are not limited by the above terms. These terms are used only to distinguish one component from another component.

[0027] Therefore, the first component described below may be the second component in the sense of the present invention. Unless otherwise defined, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by those skilled in the art to which the present invention belongs. In addition, commonly used terms defined in the dictionary should not be interpreted as ideal or angular unless clearly and specifically defined in this application.

[0028] The term "module" or "part" as used herein may refer to a software component or a hardware component such as a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC). A "part" or "module" performs a specific function. However, a "part" or "module" is not limited to software or hardware. A "part" or "module" may be arranged on an addressable storage medium or configured to restore one or more processors. Thus, a "part" or "module" may include components such as software components, object-oriented software components, class components, and task components, and may include processes, functions, attributes, procedures, subroutines, program code segments, drivers, firmware, circuits, data, databases, data structures, tables, arrays, and variables. The components and functions provided in a "part" or "module" may be combined into a small number of components and "parts" or "modules" or may be divided into additional components and "parts" or "modules".

[0029] The method or algorithm steps described with respect to some embodiments of the present disclosure may be directly implemented by hardware and software modules executed by a processor, or by a combination thereof. The software modules may reside on a RAM, a flash memory, a ROM, an EPROM, an EEPROM, a register, a hard disk, a removable disk, a CD-ROM, or other types of recording media known to those skilled in the art. An exemplary recording medium is coupled to the processor, and the processor can read information from the recording medium and can record information on the recording medium. Alternatively, the recording medium may be formed integrally with the processor. The processor and the recording medium may reside in an application specific integrated circuit (ASIC). The ASIC may reside in a user terminal.

[0030] Fig. 1 is a block diagram showing an electroluminescent display device according to an embodiment of the present invention. Referring to Fig. 1, the electroluminescent display device 100 includes a display panel 110 including a plurality of pixels, a gate driver 130 for supplying gate signals to each of the plurality of pixels, a data driver 140 for supplying data signals to each of the plurality of pixels, a light emission signal generating device 150 for supplying light emission signals to each of the plurality of pixels, and a timing control device 120.

[0031] The timing control device 120 appropriately processes the image data RGB input from the outside according to the size and resolution of the display panel 110, and provides it to the data driver 140. The timing control device 120 generates a plurality of gate control signals GCS, a plurality of data control signals DCS, and a plurality of light emission control signals ECS using a synchronization signal SYNC input from the outside, such as a dot clock signal CLK, a data enable signal DE, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync. The timing control device 120 controls the gate driver 130, the data driver 140, and the light emission signal generating device 150 by providing the generated plurality of gate control signals GCS, a plurality of data control signals DCS, and a plurality of light emission control signals ECS to the gate driver 130, the data driver 140, and the light emission signal generating device 150, respectively.

[0032] The timing control device 120 may be coupled to various processors, e.g., microprocessors, mobile processors, application processors, etc., depending on the device to which it is attached. The timing control device 120 generates signals to drive the pixels at various refresh rates. That is, the timing control device 120 generates signals for driving the pixels to drive them in a variable refresh rate VRR mode or to drive them switchably between a first refresh rate and a second refresh rate. For example, the timing control device 120 simply changes the speed of a clock signal, generates synchronization signals to generate horizontal or vertical blanks, or drives gate drivers in a masked manner to drive the pixels at various refresh rates.

[0033] Also, the timing control device 120 generates various signals for driving the pixel driving circuit at a first refresh rate. In particular, when the pixel driving circuit is driven at the first refresh rate, the timing control device 120 generates a light emission control signal ECS to cause the light emission signal generating device 150 to generate a light emission signal EM having a first duty ratio. Next, the timing control device 120 operates to drive the pixel driving circuit at a second refresh rate, and to this end, generates various signals for driving at the second refresh rate. In particular, when the pixel driving circuit is driven at the second refresh rate, the light emission signal generating device 150 generates a light emission control signal ECS to cause the light emission signal generating device 150 to generate a light emission signal EM having a second duty ratio different from the first duty ratio.

[0034] The gate driver 130 provides a scan signal SC to the gate line GL according to a gate control signal GCS provided from the timing control device 120. In Fig. 1, the gate driver 130 is disposed at a distance from one side of the display panel 110. However, the number and arrangement of the gate drivers 130 are not limited thereto. That is, the gate drivers 130 may be disposed on one or both sides of the display panel 110 in a gate-in-panel (GIP) manner.

[0035] The data driver 140 converts the image data RGB into a data voltage Vdata in accordance with a data control signal DCS provided by the timing control device 120, and supplies the converted data voltage Vdata to the pixels via the data lines DL.

[0036] In the display panel 110, a plurality of gate lines GL, a plurality of emission lines EL, and a plurality of data lines DL cross each other, and a plurality of pixels are respectively connected to the gate lines GL, the emission lines EL, and the data lines DL. Specifically, one pixel receives a gate signal from the gate driver 130 through the gate lines GL, receives a data signal from the data driver 140 through the data lines DL, receives an emission signal EM through the emission lines EL, and receives various powers through the power supply lines. Here, the gate lines GL provide the scanning signals SC, the emission lines EL provide the emission signals EM, and the data lines DL supply the data voltages Vdata. However, according to various embodiments, the gate lines GL may include a plurality of scanning signal lines, and the data lines DL may further include a plurality of power supply lines VL. The emission lines EL may also include a plurality of emission signal lines. Also, one pixel receives a high potential voltage ELVDD and a low potential voltage ELVSS. Also, one pixel may receive a first bias voltage V1 and a second bias voltage V2 through a plurality of power supply lines VL.

[0037] Further, each pixel includes an electroluminescent element and a pixel driving circuit for controlling the driving of the electroluminescent element. Here, the electroluminescent element includes an anode, a cathode, and an organic light-emitting layer between the anode and the cathode. The pixel driving circuit includes a plurality of switching elements, a driving switching element, and a capacitor. Here, the switching element may be composed of a TFT. In the pixel driving circuit, the driving TFT controls the amount of current supplied to the electroluminescent element according to the difference between a reference voltage and a data voltage charged in the capacitor, and controls the amount of light emitted by the electroluminescent element. In addition, the plurality of switching TFTs receive a scanning signal SC supplied via a gate line GL and a light-emitting signal EM supplied via a light-emitting line EL, and charge a data voltage Vdata in the capacitor.

[0038] The electroluminescence display device 100 according to the embodiment of the present invention includes a gate driver 130, a data driver 140, and a light emission signal generating device 150 for driving a display panel 110 including a plurality of pixels, and a timing control device 120 for controlling them. Here, the light emission signal generating device 150 is configured to be able to control the duty ratio of the light emission signal EM. For example, the light emission signal generating device 150 may include a shift register, a latch, or the like for controlling the duty ratio of the light emission signal EM. The light emission signal generating device 150 may be configured to generate a light emission signal having a first duty ratio and provide it to the pixel driving circuit when the pixel driving circuit is driven at a first refresh rate according to the light emission control signal ECS generated by the timing control device 120, and may be configured to generate a light emission signal having a second duty ratio different from the first duty ratio and provide it to the pixel driving circuit when the pixel driving circuit is driven at a second refresh rate.

[0039] 2A to 2C are circuit diagrams of a pixel circuit of an electroluminescent display device according to an embodiment of the present invention. FIG. 2A to FIG. 2C exemplarily show a pixel driving circuit for the purpose of explanation, and the pixel driving circuit is not limited thereto as long as it has a structure capable of controlling the emission of the electroluminescent element ELD by providing an emission signal EM. For example, the pixel driving circuit may include an additional scanning signal, a switching TFT connected to the scanning signal, and a switching TFT to which an additional initialization voltage is applied. In addition, the connection relationship between the switching elements or the connection position of the capacitor may be variously arranged. That is, since the emission of the electroluminescent element ELD is controlled according to the change in the duty ratio of the emission signal EM, pixel driving circuits having various structures may be used as long as the emission can be controlled according to the refresh rate. For example, various pixel driving circuits such as 3T1C, 4T1C, 6T1C, 7T1C, and 7T2C may be used. Hereinafter, for convenience of explanation, an electroluminescent display device having a 7T1C pixel driving circuit in FIG. 2 will be described.

[0040] Referring to FIG. 2A, each of the plurality of pixels P may include a pixel circuit PC having a driving transistor DT, and an electroluminescent element ELD connected to the pixel circuit PC.

[0041] The pixel circuit PC may drive the electroluminescent element ELD by controlling a driving current ID flowing through the electroluminescent element ELD. The pixel circuit PC may include a driving transistor DT, a first transistor T1 to a sixth transistor T6, and a storage capacitor Cst. Each of the transistors DT and T1 to T6 may include a first electrode, a second electrode, and a gate electrode. One of the first electrode and the second electrode may be a source electrode, and the other of the first electrode and the second electrode may be a drain electrode.

[0042] The transistors DT and T1-T6 may be PMOS or NMOS transistors. In the embodiment of Figures 2A and 2B, the first transistor T1 is an NMOS transistor, and the other transistors DT and T2-T6 are PMOS transistors. Furthermore, in the embodiment of Figure 2C, the first transistor T1 is also composed of a PMOS transistor.

[0043] In the following, an example will be described in which the first transistor T1 is an NMOS transistor and the other transistors DT and T2 to T6 are PMOS transistors. Therefore, the first transistor T1 is turned on by applying a high voltage, and the other transistors DT and T2 to T6 are turned on by applying a low voltage.

[0044] According to an embodiment, the first transistor T1 constituting the pixel circuit PC may function as a compensation transistor, the second transistor T2 may function as a data supply transistor, the third transistor T3 and the fourth transistor T4 may function as light-emitting control transistors, and the fifth transistor T5 and the sixth transistor T6 may function as bias transistors.

[0045] The electroluminescent element ELD may include a pixel electrode (or an anode electrode) and a cathode electrode. The pixel electrode of the electroluminescent element ELD may be connected to the fifth node N5, and the cathode electrode may be connected to the second power supply voltage ELVSS.

[0046] The driving transistor DT may include a first electrode connected to the second node N2, a second electrode connected to the third node N3, and a gate electrode connected to the first node N1. The driving transistor DT may provide a driving current Id to the electroluminescent element ELD based on the voltage of the first node N1 (or a data voltage stored in a capacitor Cst, which will be described later).

[0047] The first transistor T1 may include a first electrode coupled to the first node N1, a second electrode coupled to the third node N3, and a gate electrode receiving the first scanning signal SC1. The first transistor T1 may be turned on in response to the first scanning signal SC1 and may transmit a data signal Vdata to the first node N1. The first transistor T1 samples a threshold voltage Vth of the driving transistor DT by being diode-connected between the first node N1 and the third node N3. The first transistor T1 may be a compensation transistor.

[0048] The capacitor Cst may be connected or formed between the first node N1 and the fourth node N4. The capacitor Cst may store or maintain the provided data signal Vdata.

[0049] The second transistor T2 may include a first electrode connected to the data line DL (or receiving a data signal Vdata), a second electrode connected to the second node N2, and a gate electrode receiving a third scan signal SC3. The second transistor T2 may be turned on in response to the third scan signal SC3 and may transmit the data signal Vdata to the second node N2. The second transistor T2 may be a data supply transistor.

[0050] The third transistor T3 and the fourth transistor T4 (or the first and second light-emitting control transistors) may be connected between the first power supply voltage ELVDD and the electroluminescent element ELD, and the electroluminescent element ELD may form a current transfer path through which the drive current Id generated by the drive transistor DT transfers.

[0051] The third transistor T3 may include a first electrode connected to a fourth node N4 and receiving a first power supply voltage ELVDD, a second electrode connected to a second node N2, and a gate electrode receiving an emission signal EM.

[0052] Similarly, the fourth transistor T4 may include a first electrode coupled to the third node N3, a second electrode coupled to a fifth node N5 (or a pixel electrode of the electroluminescent element ELD), and a gate electrode receiving a light emission signal EM.

[0053] The third transistor T3 and the fourth transistor T4 are turned on in response to the light emission signal EM. In this case, the driving current Id is supplied to the electroluminescence element ELD, and the electroluminescence element ELD can emit light with a luminance corresponding to the driving current Id.

[0054] The fifth transistor T5 may include a first electrode coupled to the third node N3, a second electrode receiving the first bias voltage, and a gate electrode receiving the second scan signal SC2.

[0055] The sixth transistor T6 may include a first electrode connected to the fifth node N5, a second electrode receiving the second bias voltage V2, and a gate electrode receiving the second scan signal SC2. In Fig. 2A, the gate electrodes of the fifth transistor T5 and the sixth transistor T6 are configured to commonly receive the second scan signal SC2. However, the present invention is not limited thereto, and as shown in Figs. 2B and 2C, the gate electrodes of the fifth transistor T5 and the sixth transistor T6 may be configured to receive separate scan signals and be controlled independently.

[0056] The sixth transistor T6 may include a first electrode connected to the fifth node N5, a second electrode connected to the second bias voltage V2, and a gate electrode receiving the second scan signal SC2. Before the electroluminescent element ELD emits light (or after the electroluminescent element ELD emits light), the sixth transistor T6 may be turned on in response to the second scan signal SC2 and may initialize the pixel electrode (or the anode electrode) of the electroluminescent element ELD using the second bias voltage V2. The electroluminescent element ELD may have a parasitic capacitor formed between the pixel electrode and the cathode electrode. Also, while the electroluminescent element ELD emits light, the parasitic capacitor is charged so that the pixel electrode of the electroluminescent element ELD can have a specific voltage. Therefore, the amount of charge stored in the electroluminescent element ELD can be initialized by applying the second bias voltage V2 to the pixel electrode of the electroluminescent element ELD via the sixth transistor T6.

[0057] The present disclosure relates to an electroluminescent display device using variable refresh rate (VRR), which is a technique for driving a display device at a constant frequency, activating pixels by increasing the refresh rate at which the data voltage Vdata is updated when high-speed driving is required, and driving pixels by decreasing the refresh rate when power consumption needs to be reduced or when low-speed driving is required.

[0058] Each of the pixels P may be driven through a combination of a refresh rate and a hold frame within one second. In this specification, one set is defined as a repetition of refresh frames in which the data voltage Vdata is updated. Also, one set period is a repetition of refresh frames in which the data voltage Vdata is updated.

[0059] When a display device is driven at a refresh rate of 120Hz, the display device can only be driven with refresh frames, i.e., the refresh frames can be driven 120 times within one second. One refresh frame period is 1 / 120=8.33 milliseconds, and one set period is also 8.33 milliseconds.

[0060] When the display device is driven at a refresh rate of 60 Hz, the refresh frame and the hold frame may be driven alternately. That is, the refresh frame and the hold frame can be driven alternately 60 times within one second. One refresh frame period and one hold frame period are 0.5 / 60=8.33 milliseconds, respectively, and one set period is 16.66 milliseconds.

[0061] When a display device operates at a refresh rate of 1 Hz, it may operate with one refresh frame per second, and then operate with 119 hold frames after one refresh frame. One refresh frame period and one hold frame period are 1 / 120=8.33 milliseconds, respectively, and one set period is 1 second.

[0062] Figures 3A to 3K are diagrams for explaining driving of an electroluminescent element in the pixel circuit of the display device shown in Figures 2A to 2C and the pixel circuit in a refresh frame. Figures 4A to 4C are diagrams for explaining driving of an electroluminescent element in the pixel circuit of the display device shown in Figures 2A to 2C and the pixel circuit in a hold frame.

[0063] Meanwhile, in the refresh frame, a new data signal Vdata is charged and applied to the gate electrode of the driving transistor DT, and in the hold frame, the data signal Vdata of the previous frame is maintained and used, while the hold frame is also called a skip frame because the process of applying a new data signal Vdata to the gate electrode of the driving transistor DT is omitted.

[0064] Each of the pixels P may initialize the voltage charged or remaining in the pixel circuit PC during the refresh period. Specifically, each of the pixels P may remove the influence of the driving voltage VDD and the data voltage Vdata stored in the previous frame in the refresh frame. Therefore, each of the pixels P may display an image corresponding to the new data voltage Vdata in the hold period.

[0065] Each of the plurality of pixels P may display an image by providing a driving current Id corresponding to a data voltage Vdata to the electroluminescent element ELD during a hold frame period, and may maintain the electroluminescent element ELD in an on state.

[0066] First, the driving of the electroluminescent element and the pixel circuit in a refresh frame will be described with reference to Figures 3A to 3K. The refresh frame may include at least one bias section, an initialization section, a sampling section, and a light emission section. However, this is merely an embodiment, and the order is not necessarily limited to this.

[0067] 3A-3C show the first bias section. In FIG. 3A, the section in which the first bias voltage V1 changes from the first voltage to the second voltage is illustrated. The state of the light emission signal EM is a high voltage, and the third transistor T3 and the fourth transistor T4 are turned off. The first voltage is represented as V1_L, and the second voltage is represented as V1_H. V1_H is preferably higher than V1_L, and V1_H is also higher than the data voltage Vdata. The first scanning signal SC1 is a low voltage, and the first transistor T1 is turned off. The second scanning signal SC2 and the third scanning signal SC3 are a high voltage, and the second transistor T2, the fifth transistor T5, and the sixth transistor T6 are turned off. The voltage of the gate electrode of the driving transistor DT connected to the first node N1 is Vdata(n-1)-|Vth|, i.e., the difference between the data voltage Vdata(n-1) of the previous frame n-1 and the threshold voltage Vth of the driving transistor DT.

[0068] In FIG. 3B, the state of the second scanning signal SC2 is a low voltage, and the fifth transistor T5 and the sixth transistor T6 are turned on. When the fifth transistor T5 is turned on, a first bias voltage V1 (V1_H) is applied to the first electrode of the driving transistor DT connected to the second node N2. The voltage of the first electrode of the driving transistor DT connected to the second node N2 rises to a voltage V1_H. The driving transistor DT may be a PMOS transistor, in which case the first electrode may be a source electrode. Here, the electrode Vgs between the gate and source of the driving transistor DT is Vgs=Vdata(n-1)-|Vth|-V1_H.

[0069] Here, the first bias voltage V1=V1(V1_H) is supplied to the third node N3, which is the drain electrode of the driving transistor DT, so that the charging time or charging delay of the voltage of the fifth node N5, which is the anode electrode of the electroluminescent element ELD, can be reduced in the light-emitting section. The driving transistor DT maintains a stronger saturation state. For example, when the first bias voltage V1=V1(V1_H) increases, the voltage of the third node N3, which is the drain electrode of the driving transistor DT, can increase, and the gate-source voltage or drain-source voltage of the driving transistor DT can decrease. Therefore, it is preferable that the first bias voltage V1_H is at least higher than the data voltage Vdata. Here, the magnitude of the drain-source current Id passing through the driving transistor DT can decrease, and the stress of the driving transistor DT in the positive bias stress situation can be reduced, thereby eliminating the charging delay of the voltage of the third node N3. In other words, the Vgs of the drive transistor DT is biased to Vdata before the threshold voltage Vth of the drive transistor DT is sampled, thereby reducing the hysteresis of the drive transistor DT. Therefore, on-bias stress can be defined as the operation of directly applying an appropriate bias voltage (e.g., V1=V1_H) to the drive transistor DT during the non-emission period.

[0070] Also, when the sixth transistor T6 is turned on in the first bias section, the pixel electrode (or anode electrode) of the electroluminescent element ELD connected to the fifth node N5 is initialized to the second bias voltage V2. However, the gate electrodes of the fifth transistor T5 and the sixth transistor T6 may be configured to receive separate scanning signals and be controlled independently. That is, in the first bias section, it is not necessarily necessary to simultaneously apply bias voltages to the source electrode of the driving transistor DT and the pixel electrode of the electroluminescent element ELD.

[0071] 3C, a high second scanning signal SC2 is input, and the first bias voltage V1 changes from V1_H to V1_L. When a high second scanning signal SC2 is input, the fifth transistor T5 and the sixth transistor T6 are turned off.

[0072] FIG. 3D shows an initialization period. In the initialization period, the voltage of the gate electrode of the driving transistor DT is initialized. In FIG. 3D, the first scanning signal SC1 represents a high voltage, and the first transistor T1 is turned off. The second scanning signal SC2 represents a low voltage, and the fifth transistor T5 and the sixth transistor T6 are turned on. When the first transistor T1 and the fifth transistor T5 are turned on, the voltage of the gate electrode of the driving transistor DT connected to the first node N1 is initialized to the voltage V1_L. Also, when the sixth transistor T6 is turned on, the pixel electrode (or the anode electrode) of the electroluminescent element ELD is initialized to the second bias voltage V2. However, as described above, the present invention does not need to be limited thereto, and as shown in FIGS. 2B and 2C, the gate electrodes of the fifth transistor T5 and the sixth transistor T6 may be configured to receive separate scanning signals and be controlled independently. That is, in the initialization period, it is not necessarily necessary to simultaneously apply bias voltages to the gate electrode of the driving transistor DT and the pixel electrode of the electroluminescent element ELD.

[0073] 3E to 3G show a sampling period. In the sampling period, the data voltage and the threshold voltage of the driving transistor DT are sampled and stored in the first node N1. In FIG. 3E, a high second scanning signal SC2 is input, and the fifth transistor T5 and the sixth transistor T6 are turned off. The first transistor T1 maintains the on state.

[0074] In FIG. 3F, a low third scan signal SC3 is input, and the second transistor T2 is turned off. When the second transistor T2 is turned on, a voltage of Vdata(n) of the current frame n is applied to the source electrode of the driving transistor DT connected to the second node N2. In addition, the first transistor T1 maintains an on state. Since the driving transistor DT is diode-connected with the first voltage T1 turned on, the voltage of the gate electrode of the driving transistor DT connected to the first node N1 is Vdata(n)-|Vth|. That is, the first transistor T1 samples the threshold voltage Vth of the driving transistor DT by being diode-connected between the first node N1 and the third node N3.

[0075] In FIG. 3G, a high third scan signal SC3 is input, turning off the second transistor T2.

[0076] 3H to 3J show the second bias section. The driving waveform in the second bias section is the same as the driving waveform in the first bias section, so a detailed description will be omitted.

[0077] In FIG. 3H, the first bias voltage V1 changes from V1_L to V1_H. In FIG. 3J, when the fifth transistor T5 is turned on, the voltage of the first electrode of the driving transistor DT connected to the second node N2 rises to the voltage V1_H. Here, the electrode Vgs between the gate and source of the driving transistor is Vgs=Vdata(n)-|Vth|-V1_H. That is, the driving transistor DT maintains a stronger saturated state. Also, when the sixth transistor T6 is turned on, the pixel electrode (or anode electrode) of the electroluminescent element ELD is initialized to the second bias voltage V2. The voltage of the gate electrode of the driving transistor DT connected to the first node N1 maintains Vdata(n)-|Vth|.

[0078] In FIG. 3J, a high second scanning signal SC2 is input, and the first bias voltage V1 changes from V1_H to V1_L. When a high second scanning signal SC2 is input, the fifth transistor T5 and the sixth transistor T6 are turned off. The voltage of the gate electrode of the driving transistor DT connected to the first node N1 is maintained at Vdata(n)-|Vth|.

[0079] 3K shows a light emission period, in which the sampled threshold voltage Vth is cancelled and the electroluminescent element ELD is caused to emit light by a driving current corresponding to the sampled data voltage.

[0080] In FIG. 3K, the state of the light emission signal EM is a low voltage, and the third transistor T3 and the fourth transistor T4 are turned off.

[0081] When the third transistor T3 is turned on, the first power supply voltage ELVDD connected to the fourth node N2 is applied to the source electrode of the drive transistor DT connected to the second node N2 through the third transistor T3. The drive current Id supplied to the electroluminescence element ELD through the fourth transistor T4 by the drive transistor DT becomes independent of the threshold voltage Vth of the drive transistor DT, so that the threshold voltage Vth of the drive transistor is compensated.

[0082] Next, driving of the electroluminescent element and the pixel circuit in a hold frame will be described with reference to Figures 4A to 4C. The hold frame may include at least one bias section and a light emission section.

[0083] As described above, the refresh frame and the hold frame are different in that in the refresh frame, a new data signal Vdata is charged and applied to the gate electrode of the driving transistor DT, while in the hold frame, the data signal Vdata of the previous frame is maintained and used. Thus, unlike the refresh frame, the hold frame does not require an initialization period and a sampling period.

[0084] 4A and 4B show the first and second bias sections, and FIG. 4C shows the light emission section.

[0085] In the operation of the hold frame, one bias section may be sufficient, but in this embodiment, for convenience of the driving circuit, the second scanning signal SC2 is driven in the same manner as the second scanning signal SC2 of the refresh frame, so there are two bias sections.

[0086] The drive signals in the refresh frames described with reference to FIGS. 3A to 3K and the drive signals in the hold frames of FIGS. 4A to 4C differ from each other in the first scanning signal SC1 and the third scanning signal SC3. The hold frames do not require an initialization period and a sampling period. Therefore, unlike the refresh frames, the first scanning signal SC1 is always in a low state and the third scanning signal SC3 is always in a high state. That is, the first transistor T1 and the second transistor T2 are always off.

[0087] FIG. 5 is a diagram illustrating the problem of luminance difference occurring when the refresh rate is switched from 60 Hz to 1 Hz using the VRR mode.

[0088] The case where the refresh rate is 60 Hz is shown in Fig. 5(a), and the case where the refresh rate is 1 Hz is shown in Fig. 5(b). The refresh frame period and the hold frame period in each case are 1 / 120 seconds (=8.33 milliseconds), respectively. When the display device is driven at a refresh rate of 60 Hz, one set period is 1 / 60 seconds (=16.66 milliseconds), and when the display device is driven at a refresh rate of 1 Hz, one set period is 1 second.

[0089] As shown in (a) of Fig. 5, when the pixel is driven at a refresh rate of 60 Hz, the refresh frame and the hold frame may be driven alternately, so that the bias voltage applied to the hold frame may be reset without being stored by the initialization period of the refresh frame.

[0090] However, as shown in FIG. 5(b), when the display device is driven at a refresh rate of 1 Hz, a refresh frame is followed by a hold frame. Therefore, the bias voltage applied to the hold frame is stored as a stress voltage of the drive transistor DT. If the number of times that the bias voltage is applied to the drive transistor DT increases, the charge of the drive transistor DT increases and the drive transistor DT becomes saturated. That is, when the pixel is driven at 60 Hz and 1 Hz, the characteristics of the drive transistor DT change, causing a luminance difference.

[0091] The difference in the characteristics of the driving transistor DT between driving at 60 Hz and driving at 1 Hz is due to the difference in the amount of bias stress within one set. That is, when the display device is driven at a refresh rate of 60 Hz, there is one hold frame in one set, so the bias stress is one time, but when the display device is driven at a refresh rate of 1 Hz, there are 119 hold frames in one set, so the bias stress is 119 times. Therefore, a difference occurs in the amount of bias stress. As a result, the characteristics of the driving transistor DT change, and a brightness difference occurs. In other words, when the display device is driven at a refresh rate changed from a high refresh rate (e.g., 60 Hz) to a low refresh rate (e.g., 1 Hz), a difference occurs in the amount of bias stress of the driving transistor DT, and thus the characteristics of the driving transistor DT change and the magnitude of the driving current Id decreases. As a result, when the display device is driven at a refresh rate changed from a high refresh rate to a low refresh rate, the brightness of the electroluminescent element ELD decreases due to the decrease in the driving current Id. This is perceived by the viewer as flickering at the time when the refresh rate changes.

[0092] In the display device provided by the present disclosure, the pixel circuit may be driven at a first refresh rate, and the pixel circuit may be driven by switching from the first refresh rate to a second refresh rate having a refresh rate lower than the first refresh rate.

[0093] Hereinafter, a method for preventing a luminance difference by controlling the second voltage V1_H of the first bias voltage or the second bias voltage V2 before and after changing the refresh rate will be disclosed.

[0094] First Embodiment 6 is a diagram for explaining a first method of brightness deviation compensation driving. For example, the first refresh rate RR1 may be 60 Hz, and the second refresh rate RR2 may be 1 Hz. In the first refresh rate RR1 section, the flag value of the first refresh rate RR1 may have a value of 1, and the flag value of the second refresh rate RR2 may have a value of 0. In addition, in the second refresh rate RR2 section, the flag value of the first refresh rate RR1 may have a value of 0, and the flag value of the second refresh rate RR2 may have a value of 1.

[0095] The second voltage V1_H of the first bias voltage V1 may be adjusted to a voltage higher than the reference voltage Ref by a first level in a first refresh frame period (one set of frames R0) after switching to the second refresh rate RR2. For example, the first level may have a value of 5% of the reference voltage Ref, but is not limited thereto.

[0096] The adjustment of the second voltage V1_H of the first bias voltage V1 in the first refresh frame period (one set of frames R0) after switching to the second refresh rate RR2 is for compensating for the brightness fluctuation in this period. When the second voltage V1_H of the first bias voltage V1 increases, the voltage of the channel of the driving transistor DT becomes higher than the voltage of the gate, and the driving current Id increases. As a result, the brightness of the electroluminescent element ELD increases to compensate, so that when the refresh rate is changed from a high refresh rate to a low refresh rate to drive the pixel, the problem of flickering occurring when the refresh rate is changed can be solved.

[0097] The second voltage V1_H of the first bias voltage V1 may be adjusted to a voltage higher than the reference voltage Ref by a second level in a refresh frame period (two sets of frames R0) after the first refresh frame period after switching to the second refresh rate RR2. For example, the second level may have a value of 3% of the reference voltage Ref, but is not limited thereto. The characteristics of the driving transistor DT change most immediately after switching to the second refresh rate RR2, and the reduction amount of the driving current Id is also the largest. Therefore, in the refresh frame period after the first refresh frame period, it is necessary to reduce the luminance compensation of the electroluminescent element ELD. Therefore, it is preferable that the second level is lower than the first level.

[0098] The second bias voltage V2 may be adjusted to a voltage lower by a first level in a first refresh frame period after switching to the second refresh rate RR2. For example, the first level may have a value of 5% of the reference voltage Ref, but is not limited thereto. The second bias voltage V2 initializes the pixel electrode of the electroluminescent element ELD. By lowering the initialization voltage, the final luminance of the electroluminescent element ELD is reduced, so that the luminance deviation between the refresh frame and the hold frame can be prevented.

[0099] <Second embodiment> 7 is a diagram for explaining a second method of brightness deviation compensation driving. It has been described above that the difference in the characteristics of the driving transistor DT occurs between driving at the first refresh rate and driving at the second refresh rate. The difference in the characteristics of the driving transistor DT is due to the difference in the amount of bias stress within one set. The second embodiment provides a method for removing the deviation in the amount of bias stress that is the reason for the difference in the characteristics of the driving transistor DT.

[0100] In order to reduce the amount of bias stress in driving at the second refresh rate, it is necessary to lower the second voltage V1_H of the first bias voltage V1 in the hold frame period. Specifically, the second voltage V1_H of the first bias voltage V1 is adjusted to a voltage lower by a first level in the entire hold frame period after switching to the second refresh rate RR2, thereby eliminating the deviation of the amount of bias stress. For example, the first level may have a value of 5% of the reference voltage Ref, but is not limited thereto.

[0101] Meanwhile, since the second voltage V1_H of the first bias voltage V1 is lowered in the hold frame period, a luminance deviation may occur between the refresh frame and the hold frame. Therefore, in order to eliminate the luminance deviation between the refresh frame and the hold frame, it is necessary to correct the luminance by increasing the second bias voltage V2 in the hold frame period. Specifically, the second bias voltage V2 is adjusted to a voltage higher by a first level in the entire hold frame period after switching to the second refresh rate RR2. In addition, the second bias voltage V2 is adjusted to a voltage higher by a first level in the hold frame period H1 immediately before switching to the second refresh rate RR2. For example, the first level may have a value of 5% of the reference voltage Ref, but is not limited thereto.

[0102] <Third embodiment> 8 is a diagram illustrating a third method of brightness deviation compensation driving. Unlike the first and second embodiments, the third embodiment is characterized in that the second bias voltage V2 is not adjusted, and only the second voltage V1_H of the first bias voltage V1 is adjusted for driving.

[0103] First, in order to reduce the amount of bias stress in driving at the second refresh rate RR2, the second voltage V1_H of the first bias voltage V1 in the hold frame period is lowered. Specifically, the second voltage V1_H of the first bias voltage V1 is adjusted to a voltage higher by a first level in the refresh frame period after switching to the second refresh rate RR2.

[0104] Also, in order to eliminate the brightness deviation between the refresh frame and the hold frame, the brightness is corrected by lowering the second voltage V1_H of the first bias voltage V1 in the hold frame period. Specifically, the voltage is adjusted to a voltage lower by a first level in the hold frame period. For example, the first level may have a value of 5% of the reference voltage Ref, but is not limited thereto.

[0105] The third embodiment has the characteristic that the second voltage V1_H of the first bias voltage V1 has three voltage levels, namely a reference voltage Ref, a first change voltage increasing by a first level, and a second change voltage decreasing by the first level.

[0106] <Fourth embodiment> 9 is a diagram illustrating a fourth method of brightness deviation compensation driving. Different from the third embodiment, the fourth embodiment is characterized in that the second voltage V1_H of the first bias voltage V1 has two voltage levels, namely, a reference voltage Ref and a change voltage increased by the first level.

[0107] As described above, the difference in the characteristics of the drive transistor DT occurs between driving at the first refresh rate and driving at the second refresh rate. The difference in the characteristics of the drive transistor DT is due to the difference in the amount of bias stress within one set. The fourth embodiment provides a method for eliminating the deviation in the amount of bias stress that is the reason for the difference in the characteristics of the drive transistor DT. The deviation in the amount of bias stress is eliminated by increasing the second voltage V1_H of the first bias voltage V1 in the hold frame period immediately before switching to the second refresh rate RR2.

[0108] Specifically, the second voltage V1_H of the first bias voltage V1 is adjusted to a voltage higher by a first level in a hold frame period immediately before switching to the second refresh rate RR2. For example, the first level may have a value of 5% of the reference voltage Ref, but is not limited thereto.

[0109] According to the first to fourth methods for brightness deviation compensation driving, it is possible to eliminate the brightness deviation that occurs when driving pixels at a refresh rate that is changed from a high refresh rate (e.g., 60 Hz) to a low refresh rate (e.g., 1 Hz).

[0110] As described above, the present disclosure relates to an electroluminescent display device using a variable refresh rate (VRR). According to the first to fourth methods for brightness deviation compensation driving, it is possible to eliminate the deviation in the bias stress amount of the driving transistor DT that occurs when driving a pixel with a refresh rate changed from a high refresh rate (e.g., 60 Hz) to a low refresh rate (e.g., 1 Hz). As a result, the occurrence of brightness difference when the refresh rate changes is reduced, and the viewer cannot sense the change in the refresh rate.

[0111] While the present disclosure has been described with reference to illustrated embodiments, it will be understood that this is merely an example, and that various modifications and equivalents may be made by those skilled in the art. Accordingly, the true scope of the present disclosure should be determined by the spirit of the appended claims.

Claims

1. a display panel having a plurality of pixels; a gate driver disposed on one or both sides of the display panel; a light emitting signal generator disposed on the other side of the display panel; Each of the plurality of pixels is Electroluminescent devices, and a pixel circuit operable to change a refresh rate of the electroluminescent device to a first refresh rate and a second refresh rate lower than the first refresh rate; the light emission signal generator changes a duty ratio of a light emission signal in response to the refresh rate; The pixel circuit includes: a drive transistor for providing a drive current to the electroluminescent device; a compensation transistor configured to connect the drain electrode and the gate electrode of the drive transistor; a light emission control transistor configured to connect the drain electrode of the driving transistor and a pixel electrode of the electroluminescent device according to a light emission signal provided by the light emission signal generator; a first bias transistor configured to apply a first bias voltage to the drain electrode of the drive transistor, the drain electrode being an electrode of the drive transistor facing the electroluminescent device; a second bias transistor configured to apply a second bias voltage to the pixel electrode of the electroluminescent device; and Including, When the pixel circuit is driven at the second refresh rate, the pixel circuit is driven to include at least one refresh frame period and at least one hold frame period; The refresh frame period is a first bias period for turning the emission control transistor from on to off, turning the first and second bias transistors from off to on, applying a second voltage of the first bias voltage to the drain electrode of the drive transistor, and applying the second bias voltage to the pixel electrode of the electroluminescent device, and then turning the first and second bias transistors from on to off; a second bias period for turning the compensation transistor from on to off, turning the first and second bias transistors from off to on, maintaining the emission control transistor in an off state, applying the second voltage of the first bias voltage to the drain electrode of the drive transistor, and applying the second bias voltage to the pixel electrode of the electroluminescent device, and then turning the first and second bias transistors from on to off; the refresh frame period and the hold frame period each include the first and second bias periods; During the first and second bias periods, a first bias voltage is applied at the first refresh rate and a second bias voltage is applied at the second refresh rate; The display device, wherein the first bias voltage is controlled to a voltage higher by a first level in a first refresh frame period after switching to the second refresh rate.

2. A display panel having a plurality of pixels; a gate driver disposed on one or both sides of the display panel; a light emitting signal generator disposed on the other side of the display panel; Each of the plurality of pixels is Electroluminescent devices, and a pixel circuit operable to change a refresh rate of the electroluminescent device to a first refresh rate and a second refresh rate lower than the first refresh rate; the light emission signal generator changes a duty ratio of a light emission signal in response to the refresh rate; The pixel circuit includes: a drive transistor for providing a drive current to the electroluminescent device; a compensation transistor configured to connect the drain electrode and the gate electrode of the drive transistor; a light emission control transistor configured to connect the drain electrode of the driving transistor and a pixel electrode of the electroluminescent device according to a light emission signal provided by the light emission signal generator; a first bias transistor configured to apply a first bias voltage to the drain electrode of the drive transistor, the drain electrode being an electrode of the drive transistor facing the electroluminescent device; a second bias transistor configured to apply a second bias voltage to the pixel electrode of the electroluminescent device; and Including, When the pixel circuit is driven at the second refresh rate, the pixel circuit is driven to include at least one refresh frame period and at least one hold frame period; The refresh frame period is a first bias period for turning the emission control transistor from on to off, turning the first and second bias transistors from off to on, applying a second voltage of the first bias voltage to the drain electrode of the drive transistor, and applying the second bias voltage to the pixel electrode of the electroluminescent device, and then turning the first and second bias transistors from on to off; a second bias period for turning the compensation transistor from on to off, turning the first and second bias transistors from off to on, maintaining the emission control transistor in an off state, applying the second voltage of the first bias voltage to the drain electrode of the drive transistor, and applying the second bias voltage to the pixel electrode of the electroluminescent device, and then turning the first and second bias transistors from on to off; the refresh frame period and the hold frame period each include the first and second bias periods; During the first and second bias periods, a first bias voltage is applied at the first refresh rate and a second bias voltage is applied at the second refresh rate; The display device, wherein the first bias voltage is controlled to a voltage lower by a first level during the hold frame period after switching to the second refresh rate.

3. A display panel having a plurality of pixels; a gate driver disposed on one or both sides of the display panel; a light emitting signal generator disposed on the other side of the display panel; Each of the plurality of pixels is Electroluminescent devices, and a pixel circuit operable to change a refresh rate of the electroluminescent device to a first refresh rate and a second refresh rate lower than the first refresh rate; the light emission signal generator changes a duty ratio of a light emission signal in response to the refresh rate; The pixel circuit includes: a drive transistor for providing a drive current to the electroluminescent device; a compensation transistor configured to connect the drain electrode and the gate electrode of the drive transistor; a light emission control transistor configured to connect the drain electrode of the driving transistor and a pixel electrode of the electroluminescent device according to a light emission signal provided by the light emission signal generator; a first bias transistor configured to apply a first bias voltage to the drain electrode of the drive transistor, the drain electrode being an electrode of the drive transistor facing the electroluminescent device; a second bias transistor configured to apply a second bias voltage to the pixel electrode of the electroluminescent device; and Including, When the pixel circuit is driven at the second refresh rate, the pixel circuit is driven to include at least one refresh frame period and at least one hold frame period; The refresh frame period is a first bias period for turning the emission control transistor from on to off, turning the first and second bias transistors from off to on, applying a second voltage of the first bias voltage to the drain electrode of the drive transistor, and applying the second bias voltage to the pixel electrode of the electroluminescent device, and then turning the first and second bias transistors from on to off; a second bias period for turning the compensation transistor from on to off, turning the first and second bias transistors from off to on, maintaining the emission control transistor in an off state, applying the second voltage of the first bias voltage to the drain electrode of the drive transistor, and applying the second bias voltage to the pixel electrode of the electroluminescent device, and then turning the first and second bias transistors from on to off; the refresh frame period and the hold frame period each include the first and second bias periods, During the first and second bias periods, a first bias voltage is applied at the first refresh rate and a second bias voltage is applied at the second refresh rate; a display device that, after switching to the second refresh rate, controls the first bias voltage to a voltage higher by a first level during the refresh frame period, and controls the second bias voltage to a voltage lower by the first level during the hold frame period.

4. A display panel having a plurality of pixels; a gate driver disposed on one or both sides of the display panel; a light emitting signal generator disposed on the other side of the display panel; Each of the plurality of pixels is Electroluminescent devices, and a pixel circuit operable to change a refresh rate of the electroluminescent device to a first refresh rate and a second refresh rate lower than the first refresh rate; the light emission signal generator changes a duty ratio of a light emission signal in response to the refresh rate; The pixel circuit includes: a drive transistor for providing a drive current to the electroluminescent device; a compensation transistor configured to connect the drain electrode and the gate electrode of the drive transistor; a light emission control transistor configured to connect the drain electrode of the driving transistor and a pixel electrode of the electroluminescent device according to a light emission signal provided by the light emission signal generator; a first bias transistor configured to apply a first bias voltage to the drain electrode of the drive transistor, the drain electrode being an electrode of the drive transistor facing the electroluminescent device; a second bias transistor configured to apply a second bias voltage to the pixel electrode of the electroluminescent device; and Including, When the pixel circuit is driven at the second refresh rate, the pixel circuit is driven to include at least one refresh frame period and at least one hold frame period; The refresh frame period is a first bias period for turning the emission control transistor from on to off, turning the first and second bias transistors from off to on, applying a second voltage of the first bias voltage to the drain electrode of the drive transistor, and applying the second bias voltage to the pixel electrode of the electroluminescent device, and then turning the first and second bias transistors from on to off; a second bias period for turning the compensation transistor from on to off, turning the first and second bias transistors from off to on, maintaining the emission control transistor in an off state, applying the second voltage of the first bias voltage to the drain electrode of the drive transistor, and applying the second bias voltage to the pixel electrode of the electroluminescent device, and then turning the first and second bias transistors from on to off; the refresh frame period and the hold frame period each include the first and second bias periods; During the first and second bias periods, a first bias voltage is applied at the first refresh rate and a second bias voltage is applied at the second refresh rate; The display device, wherein the first bias voltage is controlled to a voltage higher by a first level during a hold frame period immediately before switching to the second refresh rate.

5. 5. The display device according to claim 1, wherein the light emission signal generator generates a light emission signal having a first duty ratio at the first refresh rate, and generates a light emission signal having a second duty ratio at the second refresh rate.

6. The display device according to any one of claims 1 to 4, wherein the light emission signal generator includes a shift register and a latch.

7. The pixel circuit further includes at least one switching transistor that receives a scanning signal provided through a gate line and the emission signal provided through an emission line and charges a data voltage in a capacitor; the drive transistor is configured to provide a drive current to the electroluminescent device; The display device according to any one of claims 1 to 4, wherein the at least one switching transistor is an NMOS transistor.

8. a driving driver dynamically controls the first bias voltage and the second bias voltage before and after switching from the first refresh rate to the second refresh rate; the first bias voltage is applied to a drain electrode of the drive transistor on the electroluminescent device side; 8. The display device of claim 7, wherein the second bias voltage is applied to a pixel electrode of the electroluminescent device on a side of the drive transistor.

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