Driving circuit, display device and driving method

Abstract

The invention of the present application provides a driving circuit, a display device, and a driving method which achieve a reduction in power consumption.　This driving circuit is provided with: a setting circuit that precharges a video signal line connected to a first transistor for sampling the voltage of the video signal line to a first voltage; and an adjustment circuit that adjusts the voltage of the video signal line by charging or discharging the video signal line precharged to the first voltage during a time corresponding to a second voltage to which the video signal line is set.

Description

[Technical field]

[0001] The present disclosure relates to a drive circuit, a display device, and a drive method. [Background technology]

[0002] A display device, typified by a microdisplay such as an organic electroluminescence display, includes a pixel array that displays an image using a plurality of pixels, a horizontal drive circuit that writes a video signal to each pixel of the pixel array, a vertical drive circuit that selects a video signal line to which the video signal is written, a horizontal logic circuit that controls the horizontal drive circuit, and a vertical logic circuit that controls the vertical drive circuit. The display device further includes an interface that converts an input signal to the display device into an output signal of a logic level, and a controller that controls the operation timing of the vertical drive circuit and the horizontal drive circuit based on the output signal converted by the interface.

[0003] The following Patent Document 1 discloses an example of driving a pixel that improves image quality by constant current PWM driving. In the technology disclosed in the document, first, a voltage according to an input signal voltage is held at the gate of a switching control transistor in a pixel, and then a bias voltage is held at the gate of an organic EL driver transistor. Then, a ramp wave is applied to a node via a capacitance. In response to the application of the ramp wave, the voltage of the node rises, and a constant current is applied to the organic EL light-emitting element until the voltage of the node reaches the threshold voltage of the switching control transistor. Since the pixel requires a ramp wave for PWM control of the organic EL light-emitting element, there are problems such as increased power consumption, horizontal shading, and worsening horizontal crosstalk. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2013-76812 A Summary of the Invention [Problem to be solved by the invention]

[0005] The present disclosure provides a drive circuit, a display device, and a drive method that reduce power consumption. [Means for solving the problem]

[0006] The driving circuit of the present disclosure includes: a setting circuit connected to a first transistor for sampling a voltage of a video signal line, the setting circuit precharging the video signal line to a first voltage; and an adjustment circuit that adjusts the voltage of the video signal line by charging or discharging the video signal line, which has been precharged to the first voltage, for a time period corresponding to a second voltage to be set on the video signal line.

[0007] The setting circuit includes: a first switch that connects the video signal line to the first voltage; The adjustment circuit includes: a current source being a second transistor; a second switch connecting the video signal line and the current source; The present invention may also include:

[0008] The drive circuit includes: a detection circuit having a first terminal connected to the second voltage and a second terminal connected to the video signal line, the detection circuit detecting a difference between the second voltage and a voltage of the video signal line; a holding circuit that holds a voltage corresponding to the difference and supplies the voltage to a control terminal of the current source; The present invention may also include:

[0009] the detection circuit includes an amplifier that generates a current corresponding to a difference between the second voltage and a voltage of the video signal line; The holding circuit may include a capacitance that stores a charge corresponding to the current.

[0010] the drive circuit includes a third switch connecting between the first terminal and the second terminal; The adjustment circuit turns on the third switch for a certain period before the amplifier is operated.

[0011] the detection circuit includes a comparator that detects a timing when the voltage of the video signal line becomes the second voltage, and a phase comparator that detects a difference between the timing and a timing corresponding to the second voltage; a charge pump that generates a current according to the difference; The holding circuit may include a capacitance that stores a charge corresponding to the current.

[0012] the detection circuit includes a conversion circuit that converts the difference between the second voltage and the voltage of the video signal line into a digital signal; The holding circuit may include a digital-to-analog converter that supplies a voltage corresponding to the digital signal to the control terminal.

[0013] The first voltage may be a voltage corresponding to a maximum gray scale or a minimum gray scale.

[0014] The second voltage may be a voltage corresponding to a gray scale to be displayed by a pixel circuit including the first transistor.

[0015] The second voltage may be an offset voltage that corrects a threshold voltage of a second transistor for driving a light emitting element in a pixel circuit including the first transistor.

[0016] the drive circuit includes a scanning circuit that turns on the first transistor and supplies a voltage of the video signal line, which is set to the offset voltage, to a node in the pixel circuit; the setting circuit precharges the video signal line to the first voltage after the offset voltage is supplied to the pixel circuit; the adjustment circuit charges or discharges the video signal line, which has been precharged to the first voltage, for a time period according to a voltage corresponding to a gradation, thereby adjusting the video signal line to a voltage corresponding to the gradation; The scanning circuit may supply a voltage of the video signal line to a node in the pixel circuit by turning on the first transistor.

[0017] The drive circuit includes a plurality of sub-drive circuits each including the setting circuit and the adjustment circuit; A current generating circuit for generating a reference current; the plurality of sub-drive circuits are connected to the plurality of video signal lines, the adjustment circuit of the plurality of sub-drive circuits includes a third transistor that samples a reference current; The adjustment circuits of the plurality of sub-drive circuits may charge or discharge the video signal lines precharged by the setting circuit, using the current sampled by the third transistor.

[0018] The current generating circuit includes: a first capacitance connected to a third voltage; a fourth transistor, which is a current source; a fourth switch connecting between the first capacitance and the current source; a fifth switch connecting both ends of the first capacitance; a detection circuit having a first terminal connected to a fourth voltage and a second terminal connected to the fourth switch, the detection circuit detecting a difference between a voltage at the first terminal and a voltage at the second terminal; a holding circuit that holds a voltage corresponding to the difference and supplies the voltage to a control terminal of the current source; a sixth switch that diode-connects the third transistors of the plurality of sub-drive circuits; a seventh switch connected to the diode-connected third transistors of the plurality of sub-drive circuits and to the current source; The present invention may also include:

[0019] turning on the fourth switch and the fifth switch to precharge the first capacitor; turning off the fifth switch to discharge the first capacitance to generate the reference current; turning off the fourth switch and operating the detection circuit for a certain period of time; The sixth switch and the seventh switch may be turned on to sample the reference current into the sub-driver circuit.

[0020] During a period in which the first transistor is off, the setting circuit may precharge the video signal line to the first voltage, and the adjustment circuit may adjust the video signal line to the second voltage.

[0021] The period during which the first transistor is off may be a blanking period during which a pixel circuit including the first transistor does not emit light.

[0022] The display device of the present disclosure includes a video signal line for supplying a video signal; a pixel circuit including a first transistor connected to the video signal line and configured to sample a voltage of the video signal line; a drive circuit including: a setting circuit that precharges the video signal line to a first voltage; and an adjustment circuit that adjusts a voltage of the video signal line by charging or discharging the video signal line precharged to the first voltage for a time period corresponding to a second voltage to be set for the video signal line; a scanning circuit that controls the on and off of the first transistor; Equipped with.

[0023] The driving method of the present disclosure includes: precharging a video signal line connected to a first transistor for sampling a voltage of the video signal line to a first voltage; The video signal line, which has been precharged to the first voltage, is charged or discharged for a period of time corresponding to a second voltage to be set on the video signal line, thereby adjusting the voltage of the video signal line. [Brief description of the drawings]

[0024] [Figure 1] 1 is a diagram illustrating an example of the configuration of a horizontal drive circuit and a pixel array in a display device according to a first embodiment of the present disclosure. [Diagram 2] FIG. 2 is a diagram showing a driving circuit and pixels in a horizontal driving circuit. [Diagram 3] A block diagram showing the configuration of a pixel and its peripheral circuits. [Figure 4] FIG. 3 is a timing chart of the drive circuit in FIG. [Diagram 5] FIG. 2 is a diagram showing an example of a drive circuit when an output current source is a PMOS transistor. [Figure 6] 6 is a timing chart of the drive circuit of FIG. 5 . [Figure 7] FIG. 13 is a block diagram showing another example of the configuration of the drive circuit. [Figure 8] 8 is a timing chart of the drive circuit of FIG. 7. [Figure 9] FIG. 2 is a diagram showing a configuration example of a drive circuit according to a first specific example. [Figure 10] FIG. 8 is a diagram showing an example of a circuit configuration of an OTA in FIG. 7. [Figure 11] FIG. 1 shows an example of the circuit configuration of an OTA in the case of N-channel drive. [Figure 12] FIG. 11 is a diagram showing a configuration example of a drive circuit according to a second specific example. [Figure 13] FIG. 11 is a diagram showing a configuration example of a drive circuit according to a third specific example. [Figure 14] FIG. 11 is a block diagram showing a pixel and its peripheral circuits according to a second embodiment. [Figure 15] 10 is a timing chart of a drive circuit according to a second embodiment. [Figure 16] FIG. 11 is a block diagram of a drive circuit according to a third embodiment. [Figure 17] FIG. 4 is a diagram showing an example of the configuration of a current generating circuit and a sub-driver circuit. [Figure 18] 18 is a timing chart of the drive circuit of FIG. 17. [Figure 19] 1 shows a schematic configuration of a voltage follower driving system as a horizontal driving circuit in an active matrix display device. [Figure 20] FIG. 2 is a diagram showing a schematic configuration of a horizontal logic circuit and a horizontal drive circuit using a RAMPDAC system. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] Hereinafter, the embodiments of the present disclosure will be described with reference to the drawings. In one or more embodiments shown in the present disclosure, the elements included in each embodiment can be combined with each other, and the combined result also forms part of the embodiment shown in the present disclosure.

[0026] First, the technical background of the embodiments of the present disclosure will be described.

[0027] FIG. 19 shows a schematic configuration of a voltage follower driving system as a horizontal driving circuit in an active matrix display device. A horizontal driving circuit 1002 receives data signals for pixel circuits (hereinafter, pixels) from a horizontal logic circuit 1001, and corrects the data signals to voltages according to gamma characteristics using a level shifter (LS) 1003. The corrected voltage is converted to an analog signal using a DAC circuit (Digital to Analog Converter) 1004. The analog signal is impedance-converted using an operational amplifier (buffer amplifier) ​​1005 to which a predetermined bias voltage is applied. The voltage of the signal after impedance conversion is applied to a video signal line (pixel signal line) of a pixel row selected by an output selector (demultiplexer) 1006 in a pixel array 1007. Of the selected pixel rows, a pixel to which a signal is written is selected by a vertical driving circuit (not shown).

[0028] In the voltage follower method of Fig. 19, the horizontal drive circuit 1002 has one horizontal drive circuit (LS, DAC, operational amplifier, output selector) corresponding to multiple pixel columns, and the output selector 1006 is time-division controlled to suppress increases in power consumption and circuit area. This method has the advantage that image quality degradation is relatively unlikely to occur when high definition is achieved, because the voltage follower buffers the voltage to drive the pixels. However, as the definition is increased, the number of channels (number of pixel columns) increases, and the DC bias power of the voltage follower for each pixel column (channel) increases.

[0029] In contrast to the voltage follower method of FIG. 19, a video signal writing method using a method called a RAMPDAC method is also known.

[0030] 20 shows a schematic configuration of a horizontal logic circuit and a horizontal driving circuit using the RAMPDAC system in an active matrix display device. The horizontal logic circuit includes a shift register 1100, a first latch circuit 1101, and a second latch circuit 1102. The horizontal driving circuit includes a digital comparator 1103, a synchronous counter 1104, a PWM generating circuit 1105, a level shifter 1106, a switch circuit 1107, and a ramp circuit 1108 (analog buffer, RAMPDAC).

[0031] The N+1 latches in the first latch circuit 1101 sample and latch a data signal (digital grayscale data) corresponding to each pixel at the timing when the clocks LATCK[0] to LATCK[N] are input from the shift register 1100 to the CLK terminal.

[0032] The N+1 latches included in the second latch circuit 1102 read and latch the signals held in the N+1 latches in the first latch circuit at the timing when a common line clock (LINECLK) is input to the CLK terminal. The latched data signals are input to the N+1 comparators in the digital comparator 1103.

[0033] The synchronous counter 1104 is reset when the LINECLK is input to the second latch circuit, and starts counting the grayscale clocks provided from the outside. The synchronous counter 1104 counts the grayscale clocks generated during one horizontal scanning period, and outputs the counted value to each comparator.

[0034] Each PWM generating circuit 1105 is provided corresponding to each digital comparator 1103. Each PWM generating circuit 1105 outputs a voltage of a predetermined level as a PWM signal during the time until the data signal (corresponding to the gradation value) input to each comparator matches the count value input to each comparator. Therefore, each PWM generating circuit 1105 outputs a rectangular wave of a length according to the gradation value indicated by the corresponding data signal as a PWM signal.

[0035] Each level shifter 1106 corresponds to a corresponding PWM generating circuit 1105, adjusts the length of the rectangular wave (PWM signal) output from the PWM generating circuit 1105 in accordance with the gamma characteristic, and outputs the adjusted PWM signal.

[0036] The ramp circuit 1108 includes a RAMPDAC that generates a ramp wave, which is a voltage wave in which the voltage changes (rises or falls) at a constant rate from an initial voltage within one horizontal scanning period, and an analog buffer that buffers the ramp wave. The ramp circuit 1108 outputs a ramp wave via the analog buffer in synchronization with the start timing of the output of each level shifter 1106 (or the output of the PWM generation circuit).

[0037] Each switch in the switch circuit 1107 corresponds to each level shifter 1106. Each switch is on while the PWM signal (rectangular wave) is input from the output of each level shifter 1106, and outputs a ramp wave while it is on. When the PWM signal is no longer input, each switch is turned off and stops outputting the ramp wave. As a result, a voltage according to the length of the PWM signal is output to the pixel array 1109 as a voltage (grayscale voltage) representing the corresponding grayscale value. The pixel array 1109 drives the corresponding pixel using a current according to the grayscale voltage via each switch.

[0038] The RAMPDAC method of FIG. 20 requires fewer analog circuits than the voltage follower method of FIG. 19, and therefore consumes less power and is suitable for miniaturization. However, the load capacitance of all pixels becomes the load of the analog buffer, and an operation of writing a waveform that changes transiently like a ramp wave is performed. Therefore, during writing to the pixel, a current is generated according to the pixel load capacitance and the slope of the ramp wave. This current causes image quality problems such as horizontal shading, horizontal crosstalk, and switching noise depending on the resistance of the wiring when the voltage of the RAMP waveform is written. This problem becomes particularly noticeable when the resolution is increased.

[0039] The present disclosure solves the problems of DC bias power and image quality degradation that accompany the trend toward higher resolution display devices.

[0040] (First embodiment) FIG. 1 is a block diagram showing a horizontal driving circuit and a pixel array in an active matrix display device according to a first embodiment of the present disclosure. The horizontal driving circuit includes a shift register 1100, a first latch circuit 1101, a second latch circuit 1102, a synchronous counter 1104, a digital comparator 1103, a PWM generating circuit 1105, a level shifter 1106, and a current driving circuit 101. The blocks 1100 to 1106 have the same configuration as that of FIG. 20. The current driving circuit 101 includes a driving circuit 102 corresponding to each pixel column. As described above, a voltage (PWM signal) having a time width corresponding to a data signal (grayscale) is generated for each pixel by processing the blocks 1100 to 1106, and is supplied to the driving circuit 102 corresponding to each pixel column. Each driving circuit 102 is connected to a video signal line (pixel signal line) corresponding to each pixel column. Each driving circuit 102 generates a voltage (grayscale voltage) corresponding to the PWM signal, and supplies the voltage to the pixel connected to each video signal line as a signal voltage of the video signal. One of the features of this embodiment is that the drive circuit 102 generates a signal voltage with low power consumption and high accuracy.

[0041] FIG. 2 is a diagram showing a portion of the drive circuit 102 that is related to this embodiment, and one pixel 103. As shown in FIG.

[0042] The driving circuit 102 includes a setting circuit 104, an adjustment circuit 105, and an output terminal Vout. The voltage at the output terminal Vout is represented by the same reference symbol Vout as the output terminal. The setting circuit 104 includes a switch PCHG (first switch). The adjustment circuit 105 includes an output current source IA and a switch PWM (second switch). The output current source IA is an NMOS transistor. The output terminal Vout is connected to a video signal line 112. The video signal line 112 is connected to a pixel 103. From the perspective of the driving circuit 102, the pixel 103 appears equivalent to a capacitance. Specifically, this capacitance is the capacitance of the wiring (video signal line) from the driving circuit 102 to the pixel, the parasitic capacitance of a sampling transistor included in the pixel 103, and the like. The sampling transistor is connected to the video signal line 112 and samples the signal voltage of the video signal. This capacitance is represented by Cpix. The capacitance Cpix is ​​called a pixel load capacitance. The pixel load capacitance Cpix will be described in more detail.

[0043] FIG. 3 is a block diagram showing the configuration of a pixel 103 and its peripheral circuits in an active matrix display device according to this embodiment. Although one pixel 103 is shown in FIG. 3, pixels are actually arranged in a matrix in the pixel array. The peripheral circuits include a horizontal drive circuit 10, a drive scanning circuit 20, and a write scanning circuit 60. The drive scanning circuit 20 and the write scanning circuit 60 correspond to a vertical drive circuit. The configuration of the pixel 103 is an example, and various other configurations are possible. A drive circuit 102 is provided for each column of pixels.

[0044] The pixel 103 includes a sampling transistor WSTr, a driving transistor DrTr, a capacitance Cs, and a light-emitting element 30. Each transistor is an NMOS transistor, but may be a PMOS transistor, or transistors of both conductivity types may be mixed. The light-emitting element 30 is a two-terminal organic EL light-emitting element having an anode and a cathode. However, the light-emitting element 30 is not limited to an organic EL light-emitting element, and generally includes any device that emits light by current driving.

[0045] The driving transistor DrTr has a gate connected to a node G, a source connected to a node S, and a drain connected to a driving line 50. The light-emitting element 30 has an anode connected to the node S, and a cathode connected to a common power supply line 70 (having a voltage Vcath) that is commonly wired to all pixels. The sampling transistor WSTr is connected between the video signal line 112 and the node G. The gate of the sampling transistor WSTr is connected to the scanning line 40. The capacitance Cs is connected between the node G and the node S. The driving scanning circuit 20 sets the driving line 50 to a predetermined potential, and while the driving line 50 is set to the predetermined potential, the following operation is performed. First, the writing scanning circuit 60 turns on the sampling transistor WSTr for a certain time. The signal voltage of the video signal line 112 is written to the capacitance Cs via the node G, and the capacitance Cs is set to the signal potential. The driving transistor DrTr passes a current between the drain and source according to the gate voltage applied between the gate and source via the capacitance Cs, and drives the light-emitting element 30 with this current.

[0046] The pixel load capacitance Cpix described in FIG. 2 includes the wiring capacitance present on the video signal line 112 and the parasitic capacitance present on the input side of the sampling transistor WStr.

[0047] The output current source IA in FIG. 2 is connected to a ground voltage and a switch PWM. The output terminal Vout is connected to a video signal line 112. The switch PWM connects the output current source IA and the video signal line 112 via the output terminal Vout. The switch PCHG connects the precharge voltage VPCHG (first voltage) and the video signal line 112 via the output terminal Vout. The setting circuit 104 turns on the PCHG 104 to precharge the video signal line 112 to the precharge voltage VPCHG. The PCHG 104 is turned off, and the switch PWM is turned on for the time length of the PWM signal supplied from the level shifter. The PWM signal is a rectangular voltage waveform having a time width according to the gradation. That is, the switch PWM is turned on for a time period according to the second voltage, which is a desired voltage to be set on the video signal line. This charges or discharges the precharged video signal line 112 (that is, charges or discharges the capacitance Cpix). This adjusts the voltage of the video signal line 112 to a desired voltage, for example, a voltage corresponding to the gradation represented by the PWM signal. After the adjustment, the write scanning circuit 60 turns on the sampling transistor WSTr of the pixel 103 via the scanning line 40, so that the signal voltage is written to the pixel 103.

[0048] Fig. 4 shows a timing chart of the drive circuit 102 of Fig. 2. The timing chart shows an example of an operation in which the drive circuit 102 generates a voltage (second voltage) according to a PWM signal supplied from a level shifter, and sets the generated voltage as a signal voltage to the video signal line 112. The horizontal axis represents time. The operation of Fig. 4 is performed during a period in which the sampling transistor is off. The operation of Fig. 4 may be performed, for example, during a blanking period in which all pixels do not emit light.

[0049] In FIG. 2, first, the switch PCHG is turned on to precharge the video signal line 112 to the precharge voltage VPCHG for a certain period T1. That is, the pixel load capacitance Cpix is ​​precharged to the precharge voltage VPCHG. The voltage VSIG of the video signal line 112 becomes the precharge voltage VPCHG (=V1). Next, the switch PCHG is turned off, and the switch PWM is turned on for a time tPWM according to the PWM signal (grayscale value). This causes the output current source IA to charge or discharge the precharged video signal line 112. The waveform of the voltage VSIG of the video signal line drops from the precharge voltage V1 with a slope of the output current Iout / pixel load capacitance Cpix (a value obtained by dividing the output current Iout by the pixel load capacitance Cpix). After the time tPWM, the switch PWM is turned off. The voltage VSIG of the video signal line 112 at this time becomes the output voltage Vout. This output voltage Vout can be used as a signal voltage according to the grayscale. The output voltage Vout is defined by the following formula. Vout=VPCHG-(Iout×tPWM / Cpix)...Equation (A).

[0050] In this way, by turning on the switch PWM for the time length of the PWM signal, a signal voltage corresponding to the gradation can be generated. After that, by turning on the sampling transistor of the pixel 103 connected to the video signal line 112, the signal voltage is written to the pixel 103. Here, the precharge voltage VPCHG is, for example, a voltage corresponding to the minimum width of the PWM signal (a voltage corresponding to the maximum gradation or the minimum gradation). The current source IA is adjusted so that when the switch PCHG is turned on for the time corresponding to the maximum width of the PWM signal, the precharged video signal line (capacitor Cpix) flows a current that reaches a voltage corresponding to the maximum width of the PWM signal. Note that the voltage corresponding to the maximum gradation may be expressed as VG255, and the voltage corresponding to the minimum gradation may be expressed as VG0.

[0051] In this way, the video signal line precharged to a predetermined precharge voltage is charged or discharged for a period of time according to the PWM signal, so that a voltage according to the gradation can be set to the video signal line with high accuracy. Also, the only circuit that performs analog operation in the drive circuit of Figure 2 is the output current source IA, and a circuit that generates and buffers the RAMP waveform is not required, resulting in low power consumption.

[0052] 2 and 4 show the configuration and operation when the output current source is an NMOS transistor (N-channel drive), but the configuration can be similar when the output current source is a PMOS transistor (P-channel drive).

[0053] FIG. 5 shows an example of the driver circuit 102 when the output current source IA is a PMOS transistor. Figure 6 shows a timing chart of the drive circuit of Figure 5. In this configuration, the output voltage Vout is defined by the following equation. Vout=VPCHG+(Iout×tPWM / Cpix)...Equation (B). The explanation of Figs. 5 and 6 is omitted since it is similar to the explanation of Figs. 2 and 4.

[0054] Fig. 7 is a block diagram showing another example of the configuration of the drive circuit 102. A current correction circuit 106 is added to the drive circuit 102 of Fig. 2. The current correction circuit 106 includes a voltage controlled current source circuit (OTA) 111, a switch CAL, a hold capacitance Ch, and a reference terminal VREF. In this example, the output current source IA is configured by an NMOS transistor. The current correction circuit 106 has the effect of reducing the relative current variation error between the output current sources IA of the drive circuit corresponding to each pixel column.

[0055] The OTA111 has a negative input terminal (first terminal), a positive input terminal (second terminal), and an enable terminal. The OTA111 operates while the OTAEN signal input to the enable terminal is on. The voltage (desired voltage) to be set to the video signal line is supplied to the negative input terminal of the OTA111 as a reference voltage VREF. As an example, a voltage corresponding to the gradation represented by the PWM signal is supplied. When the gradation represented by the PWM signal is the maximum gradation, the reference voltage VREF is a voltage (VG255) corresponding to the maximum gradation. The positive input terminal is connected to the output terminal Vout, and an output voltage Vout (voltage of Cpix) is supplied. The OTA111 is an example of a detection circuit that detects the difference between the voltage supplied to the negative input terminal and the voltage supplied to the positive input terminal. The OTA111 generates a current according to the detected difference. More specifically, the OTA111 calculates the difference ΔVin between the reference voltage VREF and the output voltage Vout, and changes the output current by the current obtained by multiplying the difference ΔVin by the transconductance Gm.

[0056] The switch CAL connects the output of the OTA 111 and one end of the hold capacitance Ch. The other end of the hold capacitance Ch is connected to the ground voltage. One end of the hold capacitance Ch is connected to the control terminal (gate) of the NMOS transistor which is the current source IA. The hold capacitance Ch is an example of a holding circuit which holds a voltage according to the difference and supplies the held voltage to the control terminal of the output current source IA.

[0057] The current generated by the OTA 111 charges or discharges the hold capacitance Ch via the switch CAL. That is, a charge according to the current is accumulated in the hold capacitance Ch. This adjusts the voltage of the hold capacitance Ch. The voltage of the hold capacitance Ch is supplied to the gate of the NOS transistor. The hold capacitance Ch has a role of holding the gate voltage of the output current source IA. The output current range of the OTA 111 is the range of current that can be generated by the current source (see current source 123 in FIG. 10 described later) included in the OTA 111. Specifically, the output current range is expressed by Gm·ΔVin×ton / Ch using the input voltage difference ΔVin of the OTA 111, the time ton for which the switch CAL is on, and the charge amount Ch of the hold capacitance.

[0058] Fig. 8 shows a timing chart of the drive circuit 102 in Fig. 7. The horizontal axis represents time. In the initial state, the switches PCHG, PWM, and CAL are all in the off state.

[0059] (1) First, the switch PCHG is turned on for a certain period T1, and the video signal line 112 is precharged using the precharge voltage VPCHG, that is, the pixel load capacitance Cpix is ​​precharged. The voltage after precharging is represented as V1 (=VPCHG). The voltage V1 corresponds to the voltage to be achieved with the minimum time width of the PWM signal. Note that the minimum time width of the PWM signal may be 0 or may be a time greater than 0.

[0060] (2) The switch PCHG is turned off, and the switch PWM is turned on for a time tPWM according to the PWM signal (grayscale value) input from the level shifter (see FIG. 1). This charges or discharges the video signal line 112 (i.e., charges or discharges the pixel load capacitance Cpix) via the output current source IA. The current of the output current source IA is a constant current determined by the above-mentioned formula A.

[0061] (3) After the time tPWM has elapsed, the switch PWM is turned off. In the example shown in the figure, the output voltage Vout at this time is voltage V1d. The OTAEN signal input to the enable terminal of OTA111 is turned on to put OTA111 into an operating state. Next, the switch CAL is turned on for a certain period of time. OTA111 compares the reference voltage VREF (the voltage to be achieved) with the output voltage Vout (the voltage of the pixel load capacitance Cpix), and outputs a current according to the voltage difference.

[0062] (4) The hold capacitance Ch is charged or discharged by the current output from the OTA 111.

[0063] (5) The CP (Charge Pump) output, which is the voltage of the hold capacitance Ch, changes. The CP output changes within a certain voltage range RA1 according to the charge state of the hold capacitance Ch.

[0064] The operations (1) to (5) may be performed repeatedly. This allows the voltage of the video signal line to be adjusted to the desired voltage with high precision while suppressing variations between each pixel column. However, the operations (1) to (5) may be performed only once. The operations (1) to (5) are performed, for example, during a blanking period in which all pixels do not emit light, during which the sampling transistors of the pixels are off. After the signal voltage is set on the video signal line, when it is time to write to the pixel, the sampling transistor of the pixel is turned on for a certain period of time, and the signal voltage VSIG of the video signal line is written to the pixel.

[0065] The only circuits that perform analog operations in the drive circuit in Figure 7 are the OTA 111 and the output current source IA. The OTA 111 only needs to operate during the period when the gate voltage is adjusted, and the output current source IA only needs to operate during the on-period of the switch PWM. Therefore, with the configuration of the drive circuit in Figure 7, DC bias power is consumed for only the minimum period necessary, achieving the effect of low power consumption.

[0066] [Example 1] Before the OTA 111 starts operating, the negative input terminal and the positive input terminal may be shorted to perform an offset cancellation operation. The offset cancellation operation is performed, for example, between turning on the OTAEN signal and turning on the CAL signal. By performing the offset cancellation operation, it is possible to suppress the variation in the operation of the OTA for each current correction circuit corresponding to multiple pixel columns. Therefore, it is possible to improve the variation accuracy of the output current.

[0067] 9 shows a configuration example of the driver circuit 102 according to specific example 1. A switch INI (third switch) that connects two terminals (- input terminal, + input terminal) of the OTA 111 is added.

[0068] Figures 10(A) and 10(B) show examples of the circuit configuration of the OTA 111 in Figure 9. A specific example of the offset cancellation operation will be explained using Figure 7. Figure 10(A) shows the circuit state during the offset cancellation operation, and Figure 10(B) shows the circuit state during current output operation after the offset cancellation operation.

[0069] 10A, the gate (+ input terminal) of the PMOS transistor 121 is connected to the reference voltage terminal VREF. One end (- input terminal) of the switch CAL is connected to the VFB terminal to which the output voltage Vout (voltage of the pixel load capacitance) is input. The voltage of the VFB terminal is indicated as voltage VFB.

[0070] A current source 123 is commonly connected to the source of the PMOS transistor 121 and the source of the PMOS transistor 122. The drains of the NMOS transistors 124 and 125 are connected to the drain of the PMOS transistor 121 and the drain of the PMOS transistor 122. The sources of the NMOS transistors 124 and 125 are connected to the ground voltage. The gate of the NMOS transistor 125 is connected to the ground voltage via a capacitor 126. The connection node between the drain of the PMOS transistor 122 and the drain of the NMOS transistor 125 is connected to the output terminal OTAOUT. The gate voltage of the PMOS transistor 121 is represented as VINP, and the gate voltage of the PMOS transistor 122 is represented as VINN.

[0071] A switch INI is provided between the other end of the switch CAL and a reference voltage VREF terminal (negative input terminal). A switch 132 is also provided between the capacitor 126 and the drain of the NMOS transistor 125. In the offset cancellation operation, the switches INI and 132 are turned on for a certain period of time to short the negative input terminal and the positive input terminal. Furthermore, by turning on the switch 132, the gate and source of the NMOS transistor 125 are connected. This connection is called a diode connection. As a result, both the voltages VINP and VINN become the same reference voltage VREF (i.e., the input potential difference is 0V), and the output current Ical is generated.

[0072] In this state, as shown in FIG. 10B, the switches INI and 132 are turned off, and the switch CAL is turned on. This causes a current (gm×(VFB−VREF)) obtained by subtracting the output current Ical (load current) from the current corresponding to the potential difference between the reference voltage VREF and the voltage VFB. This operation can cancel the relative variation of the OTA 111 itself. This offset cancellation operation is merely an example, and other offset cancellation methods can also be used. By performing the offset cancellation operation in this manner, it is possible to suppress the variation in the operation of the OTA for each current correction circuit corresponding to multiple pixel columns. This can improve the variation accuracy of the output current.

[0073] Although FIG. 10 shows an example of a circuit configuration for P-channel drive, a circuit configuration for N-channel drive is also possible. Fig. 11 shows an example of the circuit configuration of the OTA 111 in the case of N-channel drive. Elements corresponding to those in Fig. 10 are designated by the same reference numerals with the suffix A added. The explanation of Fig. 11 can be made by appropriately replacing the polarity of the transistors in the explanation of Fig. 10, and therefore a detailed explanation will be omitted.

[0074] [Example 2] Fig. 12 shows a configuration example of the drive circuit 102 according to specific example 2. In Fig. 7 and Fig. 9, the detection circuit in the drive circuit 102 is the OTA 111, but in Fig. 12, the detection circuit includes a comparator 141, a phase comparator 142, and a charge pump 143. Note that pixel load capacitance is not shown in Fig. 12. In the configuration in Fig. 12, it is possible to generate a highly accurate current by the output current source IA without adding a function such as the offset cancellation operation in Fig. 9.

[0075] The comparator 141 has two input terminals, one of which is connected to a reference voltage VREF, which is a voltage (desired voltage) to be set in the video signal, and the other terminal is connected to an output terminal VOUT. The comparator 141 detects the timing at which the output voltage VOUT matches the reference voltage VERF. When the switch PWM is turned on in response to the PWM signal and the voltage of the output terminal VOUT is input to the comparator 141, the comparator 141 detects the timing at which the input voltage matches the reference voltage VERF. The comparator 141 outputs a digital signal CMPOUT indicating the detected timing. An enable signal may be input to the comparator 141 in response to the on timing of the switch PWM, and the comparator 141 may start operating in response to the input of the enable signal.

[0076] The phase comparator 142 has two terminals, one of which receives the digital signal CMPOUT representing the timing detected by the comparator 141. The other terminal receives the digital signal REFPWM representing the timing corresponding to the reference voltage VERF. The phase comparator 142 compares the two digital signals to detect the timing difference between the timing detected by the comparator 141 and the timing corresponding to the reference voltage VERF.

[0077] The charge pump 143 includes an upside switch 146 and a downside switch 147 connected in series. A connection node between the upside switch 146 and the downside switch 147 is connected to a hold capacitance Ch and a gate of an output current source IA (transistor). When the upside switch 146 is turned on, it supplies a current to the hold capacitance Ch. When the downside switch 147 is turned on, it discharges a current from the hold capacitance Ch.

[0078] The phase comparator 142 selectively turns on the upside switch 146 and the downside switch 147 of the charge pump 143 in response to the detected timing difference signal. Specifically, one of the upside switch 146 and the downside switch 147 is selected in response to the sign of the timing difference signal, and the selected switch is turned on for a time length corresponding to the timing difference. This charges or discharges the hold capacitance Ch, and adjusts the gate voltage of the output current source IA.

[0079] [Example 3] FIG. 13 shows a configuration example of the drive circuit 102 according to the specific example 3. In FIGS. 7 and 9, the detection circuit in the drive circuit 102 is an OTA 111, and the holding unit is a hold capacitance. In FIG. 12, the detection circuit is a differential amplifier circuit 151 and a successive approximation circuit 152, and the holding unit is a digital-to-analog converter (DAC: Digital to Analog Converter) 153. An NMOS transistor 154 is connected to the output current source IA as a bias current source. The gate of the NMOS transistor 154 is connected to a bias voltage VB. Note that the pixel load capacitance is not shown in FIG. 12. In the configuration of FIG. 13, it is possible to generate a highly accurate current by the output current source IA without adding a function such as the offset cancel operation of FIG. 9.

[0080] The positive input terminal of the differential amplifier circuit 151 is connected to a reference voltage VREF, which is a voltage (desired voltage) to be set in the video signal. The negative input terminal of the differential amplifier circuit 151 is connected to an output terminal VOUT. The differential amplifier circuit 151 compares the reference voltage VERF with the voltage of the output terminal VOUT, and outputs the difference voltage between the two to the successive comparison circuit 152.

[0081] The successive approximation circuit 152 performs successive approximation based on the difference voltage input from the differential amplifier circuit 151, and calculates the difference voltage with high accuracy. In other words, it outputs a comparison result that approaches the set value of the gate voltage that allows the desired output current to flow. The successive approximation circuit 152 outputs a digital signal according to the calculated difference voltage. The digital signal indicates the set value of the gate voltage that allows the desired output current to flow or a value close to the set value. The successive approximation circuit 152 outputs the digital signal to the DAC 153.

[0082] The DAC 153 converts the digital signal into a DC analog voltage. That is, the DAC 153 holds the digital signal output from the successive approximation circuit 152 and generates a voltage according to a set value represented by the digital signal. The DAC 153 supplies the generated voltage to the gate of the output current source IA.

[0083] In the case of the circuit in Figure 13, after adjusting the gate voltage of the output current source IA, it is no longer necessary to adjust the gate voltage every frame, so further power consumption reduction is expected. In addition, since most of the driving circuit can be realized by logic circuits, the size reduction effect is high when the process generation advances.

[0084] As a circuit for holding the digital signal that is the output of the successive approximation circuit 152, a RAM, a flip-flop circuit, a latch circuit, a FIFO, or the like may be used.

[0085] Second embodiment The configuration of the drive circuit of the second embodiment is the same as that of the first embodiment, but the operation for the pixels is partially different. In the second embodiment, the variation between pixels in the threshold voltage of the drive transistor DrTr is cancelled (called threshold correction). For this purpose, an offset voltage is first set in the video signal line, and the set offset voltage is written to the pixel 103 via the sampling transistor WSTr. Threshold correction is performed based on this offset voltage. After the writing of the offset voltage is completed, a voltage for the gradation is set in the video signal line, and the signal voltage of the video signal is written to the pixel, as in the first embodiment. In this way, the drive circuit of the first embodiment can be used when setting the offset voltage used for threshold correction. This makes it possible to perform high-precision threshold correction while suppressing the variation between pixels. The second embodiment will be described in detail below.

[0086] FIG. 14 is a block diagram showing a pixel and its peripheral circuits in an active matrix display device according to the second embodiment. Although one pixel 103 is shown in FIG. 14, pixels are actually arranged in a matrix in the pixel array. The peripheral circuits include a horizontal drive circuit 10, a drive scanning circuit 20, and a write scanning circuit 60. The drive scanning circuit 20 and the write scanning circuit 60 correspond to a vertical drive circuit. The configuration of the pixel 103 is an example, and various other configurations are possible. The horizontal drive circuit 10 is provided with a drive circuit 102 for each column of pixels.

[0087] The pixel 103 includes a light-emitting element 30 such as an organic EL element. The cathode of the light-emitting element 30 is connected to a common power line 34 that is wired in common to all pixels. The pixel 103 also has a drive transistor DrTr, a sampling transistor WSTr, a light-emitting control transistor 24, a holding capacitor 25, and an auxiliary capacitor 26. In this example, PMOS transistors are used for the drive transistor DrTr, the sampling transistor WSTr, and the light-emitting control transistor 24, but NMOS transistors may also be used, or both conductivity types may be mixed.

[0088] The sampling transistor WSTr samples the signal voltage VSIG supplied from the drive circuit 102 through the video signal line 112, and writes it to the holding capacitor 25. The light emission control transistor 24 is connected between the power supply node of the power supply voltage Vcc and the source of the drive transistor DrTr, and controls the light emission of the light emitting element 30 under the drive of a light emission control signal DS from the drive scanning circuit 20.

[0089] The storage capacitor 25 is connected between the gate and source of the drive transistor DrTr. This storage capacitor 25 stores the signal voltage VSIG written by sampling by the sampling transistor WSTr. The drive transistor DrTr drives the light emitting element 30 by passing a drive current corresponding to the voltage stored in the storage capacitor 25 through the light emitting element 30. The auxiliary capacitor 26 is connected between the source of the drive transistor DrTr and a node of a fixed potential, for example, a power supply node of a power supply voltage Vcc. This auxiliary capacitor 26 suppresses fluctuations in the source potential of the drive transistor DrTr when the signal voltage VSIG is written, and sets the gate-source voltage Vgs of the drive transistor DrTr to the threshold voltage Vth of the drive transistor DrTr. The operation of this circuit will be described below.

[0090] With an offset voltage VOFS set from the drive circuit 102 to the video signal line 112, the potential WS of the scanning line 40 transitions from high to low, turning on the sampling transistor WSTr. The gate potential Vg of the drive transistor DrTr becomes the offset voltage VOFS. At this time, the potential DS of the drive line 50 is in a low potential state, and the light-emitting control transistor 24 is turned on. Therefore, the source potential Vs of the drive transistor DrTr becomes the power supply voltage Vcc. At this time, the gate-source voltage Vgs of the drive transistor DrTr becomes Vgs=VOFS-Vcc.

[0091] Here, in order to perform a threshold correction operation (threshold correction process) described later, it is necessary to make the gate-source voltage Vgs of the drive transistor DrTr larger than the threshold voltage Vth of the drive transistor DrTr. Therefore, each voltage value is set so that |Vgs|=|VOFS-Vcc|>|Vth|.

[0092] In this way, the initialization operation of setting the gate potential Vg of the driving transistor DrTr to the offset voltage VOFS and setting the source potential Vs of the driving transistor DrTr to the power supply voltage Vcc is a preparation (threshold correction preparation) operation before the next threshold correction operation. Therefore, the offset voltage VOFS and the power supply voltage Vcc are the initialization voltages of the gate potential Vg and the source potential Vs of the driving transistor DrTr, respectively.

[0093] The potential DS of the drive line 50 is transitioned from low to high, turning off the light emission control transistor 24. The source potential Vs of the drive transistor DrTr becomes floating, and the threshold correction operation is started in a state where the gate potential Vg of the drive transistor DrTr is kept at the offset voltage VOFS. That is, the source potential Vs of the drive transistor DrTr starts to drop (reduced) toward a potential (Vg-Vth) obtained by subtracting the threshold voltage Vth from the gate potential Vg of the drive transistor DrTr.

[0094] In this way, the threshold correction operation is an operation of changing the source potential Vs of the drive transistor DrTr toward a potential (Vg-Vth) obtained by subtracting the threshold voltage Vth from the voltage VOFS, based on the offset voltage VOFS (initialization voltage) of the gate potential Vg of the drive transistor DrTr. As this threshold correction operation progresses, the gate-source voltage Vgs of the drive transistor DrTr converges to the threshold voltage Vth of the drive transistor DrTr. A voltage equivalent to this threshold voltage Vth is held in the storage capacitor 25.

[0095] The potential WS of the scanning line 40 is transitioned from a low potential to a high potential, and the sampling transistor WSTr is turned off, thereby completing the threshold correction period. After that, the signal voltage VSIG of the video signal is set from the driving circuit 102 to the video signal line 112. As a result, the potential of the video signal line 112 is switched from the offset voltage VOFS to the signal voltage VSIG.

[0096] The potential WS of the scanning line 40 transitions from a high potential to a low potential, the sampling transistor WSTr turns off, and the signal voltage VSIG is sampled and written into the pixel 103. This writing operation of the signal voltage VSIG by the sampling transistor WSTr causes the gate potential Vg of the driving transistor DrTr to become the signal voltage VSIG.

[0097] When the signal voltage VSIG of the video signal is written, the auxiliary capacitance 26 connected between the source of the drive transistor DrTr and the power supply node of the power supply voltage Vcc suppresses fluctuations in the source potential Vs of the drive transistor DrTr. Then, when the drive transistor DrTr is driven by the signal voltage VSIG of the video signal, the threshold voltage Vth of the drive transistor DrTr is offset by the voltage equivalent to the threshold voltage Vth held in the holding capacitance 25.

[0098] The potential WS of the scanning line 40 is transitioned from low to high, and the sampling transistor WSTr is turned off, thereby completing the signal writing. The potential DS of the drive line 50 is transitioned from high to low, and the light emission control transistor 24 is turned on. As a result, a current is supplied from the power supply node of the power supply voltage Vcc to the drive transistor DrTr through the light emission control transistor 24.

[0099] At this time, since the storage capacitor 25 is connected between the gate and source of the driving transistor DrTr, the gate potential Vg also changes in conjunction with the change in the source potential Vs of the driving transistor DrTr. That is, the source potential Vs and gate potential Vg of the driving transistor DrTr rise while retaining the gate-source voltage Vgs retained in the storage capacitor 25. Then, the source potential Vs of the driving transistor DrTr rises to the light-emitting voltage of the light-emitting element 30 according to the saturation current of the transistor. As the drain-source current of the driving transistor DrTr starts to flow to the light-emitting element 30, the anode potential of the light-emitting element 30 rises. Eventually, when the anode potential of the light-emitting element 30 exceeds the threshold voltage of the light-emitting element 30, a driving current starts to flow to the light-emitting element 30, and the light-emitting element 30 starts to emit light.

[0100] Each of the operations of threshold correction preparation, threshold correction, and writing of the signal voltage VSIG (signal writing) described above is performed in, for example, one horizontal period (1H).

[0101] Hereinafter, the operation of the driving circuit 102 according to the second embodiment in a circuit that performs threshold correction by writing an offset voltage before writing a signal voltage as shown in FIG. 14 will be described with reference to FIG.

[0102] 15 is a timing chart of the driving circuit 102 according to the second embodiment. Here, the driving circuit 102 uses the OTA 111 having the offset cancellation function shown in FIG. 9. The horizontal axis represents time. For the sake of explanation, the time axis is divided into a number of sections S1 to S7.

[0103] First, in section S1, the PCHG switch is turned on, and the video signal line 112 (pixel load capacitance) is precharged to a predetermined voltage PCHG (the output terminal VOUT becomes the precharge voltage).

[0104] In section S2, the switch PCHG is turned off, and the switch PWM is turned on for a predetermined time according to VOSF. At this time, an offset voltage VOFS is provided as a reference voltage REF for the OTA 111. The precharged video signal line 112 (pixel load capacitance) is discharged at a constant slope, and when a predetermined time has passed, the switch PWM is turned off. At this time, the voltage of the output terminal VOUT becomes VOSF or a voltage close to this. When the PWM switch is turned off, the enable signal OTAEN of the OTA 111 is turned on.

[0105] While the OTA 111 is on, in section S3, the switch INI is turned on and offset cancellation is performed.

[0106] Next, in section S4, the CAL switch is turned on, and a current is output from the OTA 111. Also, the sampling transistor in the pixel is turned on (WSEN1 signal is on), and the offset voltage VOSF is supplied to the pixel. The above-mentioned threshold correction is performed in the pixel based on the offset voltage VOSF.

[0107] In section S5, the operation of the OTA 111 stops. The voltage of the hold capacitance Ch is applied to the gate of the output current source IA, and the gate voltage (CP output) varies accordingly. After the OTA 111 is turned off, the switch PCHG is turned on, and the video signal line 112 (pixel load capacitance) is precharged again. The output terminal VOUT is set to the precharge voltage.

[0108] In section S6, the switch PCHG is turned on for a time period (a time period corresponding to a desired gradation) corresponding to the PWM signal supplied from the level shifter. The precharged video signal line 112 (pixel load capacitance) is discharged at a constant rate, and when the time period corresponding to the PWM signal has elapsed, the switch PWM is turned off. The voltage of the output terminal VOUT at this time becomes the write signal voltage VSIG.

[0109] In section S7, the sampling transistor in the pixel is turned on (WSEN2 signal is on), and the signal voltage VSIG is written to the pixel via the sampling transistor.

[0110] Thereafter, the operations from S1 to S7 may be repeated one or more times, or may not be repeated. The operations from S1 to S7 may be performed one or more times during a blanking period.

[0111] Third embodiment In the third embodiment, a case where the pixel is a sub-pixel of red (R), blue (G), and green (B) is described. Using the driving circuit of the first embodiment, a capacitance (dummy capacitance) other than the pixel load capacitance is used to adjust the gate voltage of the output current source IA so that a current (reference current) with a constant slope is obtained by discharging the dummy capacitance for a certain period of time. Then, the reference current is copied to the sub-driving circuits for each of the sub-pixels of red (R), blue (G), and green (B) by a current sampling operation. In the sub-driving circuit, the video signal line precharged in advance for each sub-driving circuit is charged or discharged for a time according to the PWM signal using the current copied from the driving circuit. As a result, a signal voltage according to the gradation is set for each video signal line of RGB.

[0112] Fig. 16 is a block diagram of a driving circuit according to a third embodiment. The driving circuit in Fig. 16 includes a current generating circuit 160 and three sub-driving circuits 102R, 102B, and 102G corresponding to R (red), B (blue), and G (green). The output terminals VOUT of the three sub-driving circuits 102R, 102B, and 102G are connected to the sub-pixels 103R, 103B, and 103G via the video signal lines 112R, 112B, and 112G for RBG. The current generating circuit 160 is connected to the sub-driving circuits 102R, 102B, and 102G via the output terminal OUT. The current generating circuit 160 has a VERF terminal to which a predetermined reference voltage VER is input.

[0113] 17 shows an example of the configuration of the current generating circuit 160 and the sub-driving circuit 102R. The configuration of the sub-driving circuits 102B and 102G is the same as that of the sub-driving circuit 102R, and therefore is not shown in the figures.

[0114] The current generating circuit 160 includes an input terminal VCCP, a dummy capacitance Cdum, a switch CS (fourth switch), a switch CALPRCHG (fifth switch), switches WRT_R, WRT_B, WRT_G (seventh switch), and output terminals OUTR, OUTB, and ORTG. The current generating circuit 160 also includes an output current source IA, a hold capacitance Ch, an OTA111, two switches CAL, and a switch INI. Although the switch CAL is connected to the negative input terminal of the OTA111, this switch CAL may be omitted and the switch CAL may be only on the output side of the OTA111. In the configuration of FIG. 9 described above, a switch CAL may be added to the negative input terminal side of the OTA111 to provide two CAL switches. The operations of the output current source IA, the hold capacitance Ch, the OTA111, the two switches CAL, and the switch INI are the same as those of FIG. 9 in the first embodiment, and therefore detailed explanations will be omitted.

[0115] The sub-drive circuit 102R includes a switch WRT_R1 (sixth switch), a switch WRT_R2, a PMOS transistor 161R (third transistor), a capacitor 162R, a switch PWM, a switch PRCG|SIG_VOFS, a precharge input terminal 165, and an output terminal VOUT. The switch PRCG|SIG_VOFS corresponds to a setting circuit 167R that precharges the video signal line 112R connected to the output terminal VOUT based on the voltage applied to the precharge input terminal 165. The transistor 161R, the capacitor 162R, and the switch PWM correspond to an adjustment circuit 168R that adjusts the voltage of the video signal line 112R by charging or discharging the precharged video signal line 112R for a time period according to the PWM signal.

[0116] In the current generating circuit 160, for example, VG0 (voltage corresponding to the minimum gradation) is applied to the input terminal VCCP, and VG255 (voltage corresponding to the maximum gradation) is applied to the VERF terminal as a reference voltage VERF. Using the OTA 111 and the hold capacitance Ch, a current with a slope that reaches from a voltage corresponding to the minimum gradation to a voltage corresponding to the maximum gradation in a certain time (corresponding to a PWM signal with a maximum width) is generated as a reference current. This reference current is copied to the sub-driving circuits 102R, 102B, and 102G by current sampling. In the sub-driving circuits 102R, 102B, and 102G, the copied reference current is used to charge or discharge the video signal lines 112R, 112B, and 112G that have been precharged in advance for a time period corresponding to the PWM signal. This sets a voltage corresponding to the gradation to each of the RGB video signal lines. As in the second embodiment, before setting the video signal, an offset voltage may be set to the video signal line, and threshold correction based on the offset voltage may be performed in each sub-pixel. In the following operation description, a case where threshold correction is performed will be described.

[0117] Figure 18 is a timing chart of the drive circuit in Figure 17. The horizontal axis is time. In this example, we assume that the sub-drive circuits 102R, 102B, and 102G set a voltage (VG0) corresponding to the minimum gradation to the video signal line, that is, set the voltage of the output terminal VOUT of the sub-drive circuit to VG0.

[0118] In sections S1 to S4, the generation of a reference current to be copied in the current generating circuit 160 (setting of the dummy capacitance Cdum) and the setting of an offset voltage for each sub-pixel and threshold correction are performed in parallel. Specifically, first, in section S1, the switches CS and CALPRCHG are turned on to precharge Cdum to VG0. In addition, the switch INI on the input side of the OTA 111 is turned on to perform offset cancellation.

[0119] In section S2, the switch CALPRCHG is turned off to discharge the dummy capacitance Cdum for a certain period of time. The voltage amplitude of the dummy capacitance Cdum becomes VG0 minus VG255 as a result of the discharge. A current (reference current) flows with a certain slope that reaches from the voltage corresponding to the minimum gradation to the voltage corresponding to the maximum gradation or a voltage close to this in a certain period of time (corresponding to the maximum width PWM signal).

[0120] In section S3, the switch CS is turned off and the two CAL switches are turned on to operate the OTA 111. Although not shown in the figure, the enable signal OTAEN that is turned on is also input to the OTA 111. The output voltage of the dummy capacitance Cdum is compared with the VREF voltage (VG255), a current is charged or discharged to the hold capacitance Ch, and the gate voltage of the output current source IA (CP output in the figure) is adjusted. This adjusts the variation of the current source IA between pixels.

[0121] In section S4, the two CAL switches are turned off to terminate the operation of the OTA 111. The switch WRT_R on the current generating circuit 160 side and the two switches WRT_R1 and WRT_R2 on the sub-driving circuit 102R side are turned on to copy the current (reference current) generated by the current generating circuit 160 to the sub-driving circuit 102R. That is, by turning on the switch WRT_R on the current generating circuit 160 side and the two switches WRT_R1 and WRT_R2 on the sub-driving circuit 102R side, the gate and drain of the PMOS transistor 161R are electrically connected to the output terminal OUTR of the current generating circuit 160. The source of the PMOS transistor 161R is connected to the voltage of VG0, and the PMOS transistor 161 is diode-connected. A current with the same gradient as the reference current flows through the source and drain of the PMOS transistor 161 and the output current source IA. In this state, the switch WRT_R on the current generating circuit 160 side and the two switches WRT_R1, WRT_R2 of the sub-drive circuit 102R are turned off. The gate-source capacitor 162R holds a gate-source voltage (output stage VgsR in the figure) required to generate a current with the same slope as the reference current.

[0122] Similarly, the switch WRT_B on the current generation circuit 160 side and the two switches WRT_B1, WRT_B2 on the sub-drive circuit 102B side are turned on to copy the reference current generated by the current generation circuit 160 to the sub-drive circuit 102B. Also, the switch WRT_G on the current generation circuit 160 side and the two switches WRT_G1, WRT_G2 on the sub-drive circuit 102G side are turned on to copy the reference current generated by the current generation circuit 160 to the sub-drive circuit 102G.

[0123] In parallel with the operations of the above-mentioned sections S1 to S4, in each sub-drive circuit, an offset voltage is set for each video signal line, and threshold correction based on the set offset voltage is performed for each sub-pixel. Specifically, in the middle of sections S2 to S4, the switch SIG_VOFS of each sub-drive circuit is turned on with the precharge input terminal 165 connected to the offset voltage VOFS. This causes the video signal lines 112R, 112B, and 112G to be precharged to the offset voltage VOFS. With the video signal lines 112R, 112B, and 112G in a precharged state, the sampling transistor included in each sub-pixel is turned on (WSEN1 signal is turned on), and the offset voltage VOFS is written to each sub-pixel. In each sub-pixel, a threshold correction operation is performed using the offset voltage VOFS.

[0124] When the setting and writing of the offset voltage VOFS for each sub-drive circuit is completed and the copying of the reference current is completed, the switch PRCG in each sub-drive circuit is turned on for a certain period of time to precharge the video signal lines 112R, 112B, and 112G to VG255. That is, the voltages of the video signal lines 112R, 112B, and 112G change from VOFS to VG255. Note that the switch PRCG is the same switch as the switch SIG_VOFS, but because the switching purposes are different, different reference symbols are used for the same switches for convenience.

[0125] In section S5, when the switch PRCG in each sub-drive circuit is turned off, the switch PWM in each sub-drive circuit is turned on for a time length corresponding to the PWM signal. In the figure, only the PWM signal of one of the three sub-pixels (here, the sub-pixel 103R) is shown. In this example, a PWM signal of the maximum time length corresponding to the minimum gradation is shown. While the switch PWM is turned on, a current corresponding to the gate-source voltage held in the capacitance 162R from the transistor 161R, that is, a current having the same slope as the reference current, is supplied to the video signal line via the switch PWM (current sampling). This causes the video signal line precharged to VG255 to be charged or discharged (charging in the example shown). By charging the video signal line, the voltage of the video signal line (the voltage of the pixel load capacitance) is set to or approaches the voltage VG0 corresponding to the minimum gradation.

[0126] When the switch PWM is turned off in the section S6, the sampling transistor of each subpixel is turned on (WSEN2 signal is turned on), and the voltage VSIG of the video signal line is written to each subpixel. In each subpixel, the light-emitting element is driven according to this voltage VSIG, and emits light with a grayscale corresponding to the signal voltage VSIG. Before writing the signal voltage (before turning on the sampling transistor), the sections S1 to S5 may be repeated one or more times. This allows the gate voltage of the output current source IA of the current generating circuit 160 to be adjusted with high precision, and the voltage VSIG can be set to a target voltage (VG0 in the example shown in the figure) with high precision. The figure shows, in schematic form, that the voltage VG0 can be made closer to the voltage by increasing the number of operations from the nth time to the n+1th time.

[0127] 16 and 17, there is no need to provide a drive circuit for each sub-pixel as in the first embodiment, and the current generating circuit can be shared by multiple sub-drive circuits, reducing the circuit area. Also, it is only necessary to supply DC bias power (VERF voltage) from one current generating circuit when adjusting the output current source IA, reducing power consumption.

[0128] The above-described embodiment shows an example for realizing the present disclosure, and the present disclosure can be implemented in various other forms. For example, various modifications, substitutions, omissions, or combinations thereof are possible without departing from the gist of the present disclosure. Such modifications, substitutions, omissions, etc. are also included in the scope of the present disclosure, as well as in the scope of the invention and its equivalents described in the claims.

[0129] Furthermore, the effects of the present disclosure described in this specification are merely examples, and other effects may be available.

[0130] The present disclosure can also be configured as follows. [Item 1] a setting circuit connected to a first transistor for sampling a voltage of a video signal line, the setting circuit precharging the video signal line to a first voltage; an adjustment circuit that adjusts a voltage of the video signal line by charging or discharging the video signal line precharged to the first voltage for a time period corresponding to a second voltage to be set on the video signal line; A drive circuit comprising: [Item 2] The setting circuit includes: a first switch that connects the video signal line to the first voltage; The adjustment circuit includes: a current source being a second transistor; a second switch connecting the video signal line and the current source; 2. The drive circuit according to item 1, comprising: [Item 3] a detection circuit having a first terminal connected to the second voltage and a second terminal connected to the video signal line, the detection circuit detecting a difference between the second voltage and a voltage of the video signal line; a holding circuit that holds a voltage corresponding to the difference and supplies the voltage to a control terminal of the current source; 3. The drive circuit according to item 2, comprising: [Item 4] the detection circuit includes an amplifier that generates a current corresponding to a difference between the second voltage and a voltage of the video signal line; the holding circuit includes a capacitance that stores a charge according to the current; Item 3. The drive circuit according to item 3. [Item 5] a third switch connecting the first terminal and the second terminal; The adjustment circuit turns on the third switch for a certain period before the amplifier is operated. 5. The drive circuit according to item 4. [Item 6] the detection circuit includes a comparator that detects a timing when the voltage of the video signal line becomes the second voltage, and a phase comparator that detects a difference between the timing and a timing corresponding to the second voltage; a charge pump that generates a current according to the difference; the holding circuit includes a capacitance that stores a charge according to the current; Item 3. The drive circuit according to item 3. [Item 7] the detection circuit includes a conversion circuit that converts the difference between the second voltage and the voltage of the video signal line into a digital signal; The holding circuit includes a digital-to-analog converter that supplies a voltage corresponding to the digital signal to the control terminal. Item 3. The drive circuit according to item 3. [Item 8] The first voltage corresponds to a maximum gray scale or a minimum gray scale. The driving circuit according to any one of items 1 to 7. [Item 9] The second voltage is a voltage corresponding to a gray scale to be displayed by a pixel circuit including the first transistor. The driving circuit according to any one of items 1 to 8. [Item 10] The second voltage is an offset voltage that corrects a threshold voltage of a second transistor for driving a light-emitting element in a pixel circuit including the first transistor. 10. The driving circuit according to any one of items 1 to 9. [Item 11] a scanning circuit that turns on the first transistor and supplies a voltage of the video signal line that is set to the offset voltage to a node in the pixel circuit; the setting circuit precharges the video signal line to the first voltage after the offset voltage is supplied to the pixel circuit; the adjustment circuit charges or discharges the video signal line, which has been precharged to the first voltage, for a time period according to a voltage corresponding to a gradation, thereby adjusting the video signal line to a voltage corresponding to the gradation; The scanning circuit supplies a voltage of the video signal line to a node in the pixel circuit by turning on the first transistor. Item 11. The drive circuit according to item 10. [Item 12] a plurality of sub-drive circuits each including the setting circuit and the adjustment circuit; A current generating circuit for generating a reference current; the plurality of sub-drive circuits are connected to the plurality of video signal lines, the adjustment circuit of the plurality of sub-drive circuits includes a third transistor that samples a reference current; The adjustment circuits of the plurality of sub-drive circuits charge or discharge the video signal lines precharged by the setting circuit using the current sampled by the third transistor. The driving circuit according to any one of items 1 to 11. [Item 13] The current generating circuit includes: a first capacitance connected to a third voltage; a fourth transistor, which is a current source; a fourth switch connecting between the first capacitance and the current source; a fifth switch connecting both ends of the first capacitance; a detection circuit having a first terminal connected to a fourth voltage and a second terminal connected to the fourth switch, the detection circuit detecting a difference between a voltage at the first terminal and a voltage at the second terminal; a holding circuit that holds a voltage corresponding to the difference and supplies the voltage to a control terminal of the current source; a sixth switch that diode-connects the third transistors of the plurality of sub-drive circuits; a seventh switch connected to the diode-connected third transistors of the plurality of sub-drive circuits and to the current source; Item 13. The drive circuit according to item 12, comprising: [Item 14] turning on the fourth switch and the fifth switch to precharge the first capacitor; turning off the fifth switch to discharge the first capacitance to generate the reference current; turning off the fourth switch and operating the detection circuit for a certain period of time; The sixth switch and the seventh switch are turned on to sample the reference current to the sub-driver circuit. Item 14. The drive circuit according to item 13. [Item 15] During a period in which the first transistor is off, the setting circuit precharges the video signal line to the first voltage, and the adjustment circuit adjusts the video signal line to the second voltage. The driving circuit according to any one of items 1 to 14. [Item 16] The period during which the first transistor is off is a blanking period during which a pixel circuit including the first transistor does not emit light. Item 16. The drive circuit according to item 15. [Item 17] A video signal line for supplying a video signal; a pixel circuit including a first transistor connected to the video signal line and configured to sample a voltage of the video signal line; a drive circuit including: a setting circuit that precharges the video signal line to a first voltage; and an adjustment circuit that adjusts a voltage of the video signal line by charging or discharging the video signal line precharged to the first voltage for a time period corresponding to a second voltage to be set for the video signal line; a scanning circuit that controls the on and off of the first transistor; A display device comprising: [Item 18] precharging a video signal line connected to a first transistor for sampling a voltage of the video signal line to a first voltage; The video signal line precharged to the first voltage is charged or discharged for a time period corresponding to a second voltage to be set on the video signal line, thereby adjusting the voltage of the video signal line. Drive method. [Explanation of symbols]

[0131] 10: Horizontal drive circuit 20: Drive scanning circuit 24: Light-emitting control transistor 26: Auxiliary capacity 25: Holding capacity 30: Light emitting element 34: Common power line 60: Write scanning circuit 101: Current drive circuit 102: Drive circuit 104: Setting circuit 103: Pixel circuit (pixel) 105: Adjustment circuit 103R, 103B, 103G: Sub-pixels 111: Voltage controlled current source circuit (OTA) 112: Video signal line 121, 122, 124, 125: Transistor 123: Current source 126: Capacity 132: Switch 142: Phase comparator 143: Charge pump 146: Upside Switch 147: Downside switch 151: Differential amplifier circuit 152: Successive approximation circuit 153:DAC 154: Transistor 160:Current generation circuit 102R, 102B, 102G: Sub-drive circuit 103R, 103B, 103G: Sub-pixels 161R: Transistor 162R: Capacity 1100: Shift register 1101: First latch circuit 1102: Second latch circuit 1104: Synchronous counter 1103: Digital comparator 1105:PWM generation circuit 1106: Level shifter Vout: Output terminal, output voltage VREF: Reference terminal, reference voltage IA: Output current source WSTr: Sampling Transistor DrTr: Drive transistor Cs: Capacity Ch: Hold capacitance Cdum: dummy capacitance PWM, PCHG, CAL, INI, CS, CALPRCHG, WRT_R, WRT_B, WRT_G, WRT_R1, WRT_B1, WRT_G1, WRT_R2, WRT_B2, WRT_G2, PROG, SIG_VOFS: Switch

Claims

1. a setting circuit including a first switch for connecting the video signal line connected to a first transistor for sampling a voltage of the video signal line to a first voltage, the setting circuit precharging the video signal line to the first voltage; an adjustment circuit including a current source which is a second transistor and a second switch which connects between the video signal line and the current source, and which adjusts a voltage of the video signal line by charging or discharging the video signal line precharged to the first voltage for a time period corresponding to a rectangular wave signal having a time length according to a gray scale; a detection circuit having a first terminal connected to a second voltage serving as a reference and a second terminal connected to the video signal line, the detection circuit detecting a difference between the second voltage and a voltage of the video signal line; a holding circuit that holds a voltage corresponding to the difference and supplies the voltage to a control terminal of the current source; A drive circuit comprising:

2. (delete)

3. (delete)

4. the detection circuit includes an amplifier that generates a current corresponding to a difference between the second voltage and a voltage of the video signal line; the holding circuit includes a capacitance that stores a charge according to the current; 2. The drive circuit according to claim 1.

5. a third switch connecting the first terminal and the second terminal; The adjustment circuit turns on the third switch for a certain period before the amplifier is operated.

5. The drive circuit according to claim 4.

6. the detection circuit includes a comparator that detects a timing when the voltage of the video signal line becomes the second voltage, and a phase comparator that detects a difference between the timing and a timing corresponding to the second voltage; a charge pump that generates a current according to the difference; the holding circuit includes a capacitance that stores a charge according to the current; 2. The drive circuit according to claim 1.

7. the detection circuit includes a conversion circuit that converts the difference between the second voltage and the voltage of the video signal line into a digital signal; The holding circuit includes a digital-to-analog converter that supplies a voltage corresponding to the digital signal to the control terminal.

2. The drive circuit according to claim 1.

8. The first voltage corresponds to a maximum gray scale or a minimum gray scale.

2. The drive circuit according to claim 1.

9. The second voltage is a voltage corresponding to a gray scale to be displayed by a pixel circuit including the first transistor.

2. The drive circuit according to claim 1.

10. The second voltage is an offset voltage that corrects a threshold voltage of a second transistor for driving a light-emitting element in a pixel circuit including the first transistor.

2. The drive circuit according to claim 1.

11. a scanning circuit that turns on the first transistor and supplies a voltage of the video signal line that is set to the offset voltage to a node in the pixel circuit; the setting circuit precharges the video signal line to the first voltage after the offset voltage is supplied to the pixel circuit; the adjustment circuit charges or discharges the video signal line, which has been precharged to the first voltage, for a time period according to a voltage corresponding to a gradation, thereby adjusting the video signal line to a voltage corresponding to the gradation; The scanning circuit supplies a voltage of the video signal line to a node in the pixel circuit by turning on the first transistor. The drive circuit according to claim 10.

12. a plurality of sub-drive circuits each including the setting circuit and the adjustment circuit; A current generating circuit for generating a reference current; the plurality of sub-drive circuits are connected to the plurality of video signal lines, The adjustment circuit of the plurality of sub-drive circuits includes a third transistor that samples a reference current; The adjustment circuits of the plurality of sub-drive circuits charge or discharge the video signal lines precharged by the setting circuit using the current sampled by the third transistor.

2. The drive circuit according to claim 1.

13. The current generating circuit includes: a first capacitance coupled to a third voltage; a current source being a fourth transistor; a fourth switch connecting between the first capacitance and the current source; a fifth switch connecting both ends of the first capacitance; a detection circuit having a first terminal connected to a fourth voltage and a second terminal connected to the fourth switch, the detection circuit detecting a difference between a voltage at the first terminal and a voltage at the second terminal; a holding circuit that holds a voltage corresponding to the difference and supplies the voltage to a control terminal of the current source; a sixth switch that diode-connects the third transistors of the plurality of sub-drive circuits; a seventh switch connected to the diode-connected third transistors of the plurality of sub-drive circuits and to the current source; The drive circuit of claim 12 comprising:

14. turning on the fourth switch and the fifth switch to precharge the first capacitor; Turning off the fifth switch to discharge the first capacitance to generate the reference current; turning off the fourth switch and operating the detection circuit for a certain period of time; The sixth switch and the seventh switch are turned on to sample the reference current to the sub-driver circuit.

14. A driving circuit according to claim 13.

15. During a period in which the first transistor is off, the setting circuit precharges the video signal line to the first voltage, and the adjustment circuit adjusts the voltage of the video signal line.

2. The drive circuit according to claim 1.

16. During a blanking period in which a pixel circuit including the first transistor does not emit light, the first transistor is off.

16. A drive circuit as claimed in claim 15.

17. A video signal line for supplying a video signal; a pixel circuit including a first transistor connected to the video signal line and configured to sample a voltage of the video signal line; a setting circuit including a first switch that connects the video signal line to a first voltage and that precharges the video signal line to the first voltage; a drive circuit including a current source which is a second transistor, and a second switch which connects between the video signal line and the current source, and an adjustment circuit which adjusts a voltage of the video signal line by charging or discharging the video signal line precharged to the first voltage for a time period corresponding to a rectangular wave signal having a time length according to a gray scale; a detection circuit having a first terminal connected to a second voltage serving as a reference and a second terminal connected to the video signal line, the detection circuit detecting a difference between the second voltage and a voltage of the video signal line; a holding circuit that holds a voltage corresponding to the difference and supplies the voltage to a control terminal of the current source; a scanning circuit that controls the on and off of the first transistor; A display device comprising:

18. precharging a video signal line connected to a first transistor that samples a voltage of the video signal line to a first voltage based on a first switch connected to a first voltage; a current source which is a second transistor and a second switch which connects between the video signal line and the current source, the video signal line which has been precharged to the first voltage is charged or discharged for a time period corresponding to a rectangular wave signal having a time length according to a gray scale, thereby adjusting a voltage of the video signal line; a first terminal receiving a second voltage serving as a reference, a second terminal receiving a voltage of the video signal line, detecting a difference between the second voltage and the voltage of the video signal line, holding a voltage according to the difference, and supplying the voltage to a control terminal of the current source; Drive method.

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