Display panel control circuit and display device

Abstract

This application discloses a control circuit (10) for a display panel (2) and a display device (1), in which the control circuit (10) for the display panel receives a first clock signal, a first level signal, and a second level signal, and based on the first level signal and the second level signal, phase-shifts the first clock signal to obtain a second clock signal, which is output to a gate drive circuit (20), thereby realizing a phase shift for the clock signal, thereby reducing the load of a single clock signal, reducing the number of clock generators in the display panel (2), and reducing the manufacturing cost of the display panel (2).

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to a Chinese patent application filed with the China Patent Office on July 30, 2021, bearing application number 202110876023.9 ​​and entitled "Control circuit and display device for display panel", the entire contents of which are incorporated herein by reference. [Technical field]

[0002] The present application relates to the field of display technology, and more particularly to a control circuit for a display panel and a display device. [Background technology]

[0003] With the rapid development of display technology, display panels are widely applied in various fields such as entertainment, education, and security. GDL (Gate Driver Less, Array Substrate Row Drive) technology directly manufactures gate driver ICs on the array substrate and outputs row drive signals to achieve progressive scanning of the gates. GDL technology can simplify the manufacturing process of display panels, eliminate the chip bonding process in the horizontal scan line direction, and reduce manufacturing costs, while at the same time improving the integration degree of display panels and making display panels thinner.

[0004] A display panel adopting GDL technology needs to use multiple clock signals to control the gate driving circuits to output row driving signals. As the size and resolution of display panels continue to increase, the number of gate driving circuits in each display panel also continues to increase, resulting in the load of a single clock signal being too high, and reducing the operational stability of the display panel. Summary of the Invention [Problem to be solved by the invention]

[0005] One of the objectives of the embodiments of the present application is to provide a control circuit and a display device for a display panel, which solves the problem that the number of gate driving circuits in a display panel adopting conventional GDL technology is increasingly increased, which places too high a load on a single clock signal, thereby reducing the operational stability of the display panel. [Means for solving the problem]

[0006] The technical solutions adopted in the embodiments of the present application are as follows: In a first aspect, a control circuit for a display panel is provided, the control circuit receiving a first clock signal, a first level signal and a second level signal, and phase-shifting the first clock signal according to the first level signal and the second level signal to obtain a second clock signal and output it to a gate driving circuit, where the second clock signal includes a third level signal and a fourth level signal, and the third level signal and the fourth level signal have different level magnitudes; the control circuit includes a first switch unit and a second switch unit, the first switch unit is connected to the second switch unit; the first switch unit is used for receiving the first clock signal, the first level signal and the second level signal, and outputting a third level signal to the gate driving circuit according to the first clock signal, the first level signal and the second level signal; The second switch unit is used for receiving the first clock signal, the first level signal and the second level signal, and outputting a fourth level signal to the gate driving circuit according to the first clock signal, the first level signal and the second level signal.

[0007] In a second aspect, there is provided a display device comprising a display panel and a control unit including the control circuit according to the first aspect. Effect of the Invention

[0008] A first aspect of an embodiment of the present application provides a control circuit for a display panel, which receives a first clock signal, a first level signal and a second level signal, and based on the first level signal and the second level signal, phase-shifts the first clock signal to obtain a second clock signal, which is output to a gate driving circuit, thereby realizing a phase shift for a clock signal, thereby reducing the load of a single clock signal, and reducing the number of clock generators in the display panel, and reducing the manufacturing cost of the display panel.

[0009] As can be understood, the beneficial effects of the second aspect can be referred to the relevant description in the first aspect, and the description will be omitted here. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a structural schematic diagram of a first type of control circuit for a display panel provided in an embodiment of the present application. [Diagram 2] FIG. 2 is a schematic diagram of a second structure of a control circuit for a display panel according to an embodiment of the present application. [Diagram 3] FIG. 3 is a schematic diagram of a third structure of a control circuit for a display panel according to an embodiment of the present application. [Figure 4] FIG. 4 is a schematic diagram of a fourth structure of a control circuit for a display panel according to an embodiment of the present application. [Diagram 5] FIG. 5 is a schematic diagram of a fifth structure of a control circuit for a display panel according to an embodiment of the present application. [Figure 6] FIG. 6 is a timing schematic diagram of a first clock signal, a gate level of a second electronic switch, a drain level of a second electronic switch, a gate level of a fourth electronic switch, a third level signal, a fourth level signal and a second clock signal provided in an embodiment of the present application. [Figure 7] FIG. 7 is a schematic diagram of a sixth structure of a control circuit for a display panel according to an embodiment of the present application. [Figure 8] FIG. 8 is a schematic diagram of a seventh type of structure of a control circuit for a display panel provided in an embodiment of the present application. [Figure 9]FIG. 9 is a schematic diagram of an eighth structural example of a control circuit for a display panel according to an embodiment of the present application. [Figure 10] FIG. 10 is a timing schematic diagram of the first clock signal, the gate level of the tenth electronic switch, the drain level of the tenth electronic switch, the gate level of the twelfth electronic switch, the fifth level signal, the sixth level signal and the second clock signal provided by an embodiment of the present application. [Figure 11] FIG. 11 is a structural schematic diagram of a display device provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] In the following description, for the purposes of explanation and not limitation, specific details such as specific system structures and techniques are provided to provide a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application can be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid obscuring the description of the present application with unnecessary details.

[0012] Furthermore, in the description of the present specification and the appended claims, the terms "first," "second," "third," etc. are used merely for distinguishing and describing purposes, and should not be understood to indicate or imply relative importance.

[0013] References to "one embodiment" or "some embodiments" or the like in the present specification mean that one or more embodiments of the present specification include a particular feature, structure, or characteristic described in connection with that embodiment. Thus, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in further embodiments," etc. appearing in different places in this specification are not necessarily referring to the same embodiment and, unless specifically emphasized otherwise, all mean "one or more, but not all, embodiments." Unless specifically emphasized otherwise, the terms "comprise," "contain," "have," and variations thereof all mean "including but not limited to."

[0014] The embodiments of the present application provide a control circuit for a display panel, which can be applied to a display panel, and the display panel can be a liquid crystal display panel based on TFT-LCD (Thin Film Transistor Liquid Crystal Display) technology, a liquid crystal display panel based on LCD (Liquid Crystal Display) technology, an organic electroluminescent display panel based on OLED (Organic Light-Emitting Diode) technology, a quantum dot light-emitting diode display panel based on QLED (Quantum Dot Light Emitting Diodes) technology, or a curved display panel, etc.

[0015] As shown in Fig. 1 or 2, an embodiment of the present application provides a control circuit 10 for a display panel, which is used to receive a first clock signal, a first level signal and a second level signal, and phase-shift the first clock signal according to the first level signal and the second level signal to obtain a second clock signal, which is output to a gate driving circuit 20. Here, the second clock signal includes a third level signal and a fourth level signal, and the third level signal and the fourth level signal have different levels; The control circuit 10 includes a first switch unit 11 and a second switch unit 12, the first switch unit 11 is connected to the second switch unit 12, the first switch unit 11 is used for receiving the first clock signal, the first level signal and the second level signal, and outputting a third level signal to the gate driving circuit 20 according to the first clock signal, the first level signal and the second level signal; The second switch unit 12 is used to receive the first clock signal, the first level signal and the second level signal, and output a fourth level signal to the gate driving circuit 20 according to the first clock signal, the first level signal and the second level signal.

[0016] Here, Fig. 1 only exemplarily illustrates the connection relationship between the control circuit and the gate driving circuit, the input / output signals of the control circuit, and the input signals of the gate driving circuit. Fig. 2 illustrates, based on Fig. 1, that the control circuit includes a first switch unit and a second switch unit, and the input / output signals of the first switch unit and the second switch unit.

[0017] In application, the control circuit may include electronic components such as a plurality of transistors, comparators, logic gates, resistors, capacitors, or inductances. The first clock signal, the first level signal, and the second level signal are input to the control circuit by a timing controller (Timer Control Register, TCON) or a system on chip (SOC). The control circuit can phase-shift the first clock signal according to the first level signal and the second level signal, and the phase difference between the second clock signal and the first clock signal obtained by the phase shift may range from 0 degrees to 180 degrees, and the phase difference between the second clock signal and the first clock signal is determined according to the timing of the first level signal and the second level signal. Both the first clock signal and the second clock signal can be output to a gate driving circuit, and the gate driving circuit outputs a row driving signal to control the gates of the display panel to perform progressive scanning. Specifically, a display panel can include at least one control circuit, the number of control circuits is determined according to the number of clock signals used by the display panel, each control circuit corresponds to each first clock signal one-to-one, and n control circuits receive the n first clock signals and phase-shift the n first clock signals to obtain n second clock signals corresponding to the n first clock signals. Each control circuit outputs the phase-shifted second clock signals to a gate driving circuit, and the gate driving circuit controls the output of any number of row driving signals according to actual needs to perform progressive scanning on the gates of the display panel.Compared with using n first clock signals to input to the gate drive circuit, by using a control circuit to generate n first clock signals that correspond one-to-one to the n first clock signals, a total of 2n clock signals, which are n first clock signals and n second clock signals, can be input to the gate drive circuit, and a single clock signal can be input to multiple gate drive circuits, so that after the number of clock signals is increased, the number of single clock signals input to the gate drive circuit can be reduced, thereby reducing the load of the single clock signal, and reducing the number of clock generators for generating clock signals, and reducing the manufacturing cost of the display panel. Here, n is an integer greater than 0, and the number of control circuits can be set according to the actual needs of the display panel.

[0018] FIG. 3 is a schematic structural diagram illustrating an example in which a first control circuit 101, a second control circuit 102 to an n-th control circuit 103 are connected to a gate drive circuit 20. As shown in FIG.

[0019] In application, the control circuit can include multiple switch units, and each switch unit can control whether the switch unit outputs a level signal according to the magnitude of the level of the first clock signal; specifically, the control circuit can include a first switch unit and a second switch unit, where the first switch unit is used to control the output of a third level signal according to the first clock signal, and the second switch unit is used to control the output of a fourth level signal according to the first clock signal. For example, when the first clock signal is at a high level, the first switch unit can be controlled to stop outputting the third level signal, and the second switch unit can be controlled to start outputting the fourth level signal. When the first clock signal is at a low level, the first switch unit can be controlled to start outputting the third level signal, and the second switch unit can be controlled to stop outputting the fourth level signal. In addition, after the display panel enters an operating state, the third level signal and the fourth level signal have different levels, specifically, when the third level signal is at a high level, the fourth level signal is at a low level, or when the third level signal is at a low level, the fourth level signal is at a high level. Therefore, by matching the third level signal output from the first switch unit and the fourth level signal output from the second switch unit, a continuous second clock signal can be obtained without interruption.

[0020] In one embodiment, the first level signal is a high level signal and the second level signal is a low level signal.

[0021] In one embodiment, the first switch unit 11 is further used to turn on a third level signal to output to the gate driving circuit 20 according to the first clock signal, the first level signal, and the second level signal when the first clock signal is at a low level, and the third level signal is at a high level. The first switch unit 11 is further used to turn off the third level signal to stop outputting to the gate driving circuit 20 according to the first clock signal, the first level signal, and the second level signal when the first clock signal is at a high level; The second switch unit 12 is further used to turn on a fourth level signal and output it to the gate drive circuit 20 according to the first clock signal, the first level signal, and the second level signal when the first clock signal is at a high level, and the fourth level signal is at a low level. The second switch unit 12 is further used to turn off the fourth level signal and stop outputting it to the gate drive circuit 20 according to the first clock signal, the first level signal, and the second level signal when the first clock signal is at a low level.

[0022] In application, after the control circuit enters into a working state, when the first clock signal is at a low level, the first switch unit turns on to output a third level signal to the gate drive circuit, at this time the third level signal is at a high level, the second switch unit turns off to stop outputting the fourth level signal to the gate drive circuit, at this time the fourth level signal is not output, so the second clock signal is at a high level; when the first clock signal is at a high level, the first switch unit turns off to stop outputting the third level signal to the gate drive circuit, at this time the third level signal is not output, the second switch unit turns on to output a fourth level signal to the gate drive circuit, at this time the fourth level signal is at a low level, so the second clock signal is at a low level, thereby realizing a phase shift with respect to the first clock signal, and the phase difference between the second clock signal and the first clock signal obtained by the phase shift is 90 degrees.

[0023] As shown in FIG. 4, in one embodiment, based on the embodiment corresponding to FIG. 2, the first switch unit 11 includes: a first electronic switch 111, a second electronic switch 112, a third electronic switch 113, a fourth electronic switch 114, a fifth electronic switch 115 and a first capacitor 116; The drain of the first electronic switch 111 is connected to the gate of the second electronic switch 112, and the gate and source of the first electronic switch 111 are used to receive the first clock signal; The drain of the second electronic switch 112 is connected to the source of the fourth electronic switch 114, and the source of the second electronic switch 112 is used to receive the first level signal; The drain of the third electronic switch 113 is respectively connected to the source of the fifth electronic switch 115 and the gate of the fourth electronic switch 114, and the source of the third electronic switch 113 is used to receive the first level signal; The first stage of the first capacitor 116 is respectively connected to the drain of the first electronic switch 111 and the gate of the second electronic switch 112, and the drain of the fifth electronic switch 115 is used to receive the second level signal; The gate of the third electronic switch 113, the drain of the fifth electronic switch 115, the drain of the fourth electronic switch 114 and the second electrode of the first capacitor 116 are respectively electrically connected to the second switch unit.

[0024] In application, the first electronic switch to the fifth electronic switch may be any device or circuit having an electronic switch function, such as a transistor or a metal oxide semiconductor field effect transistor (MOSFET), specifically a thin film field effect transistor (TFT). The first capacitor may be different types of capacitors, such as a ceramic capacitor, an aluminum electrolytic capacitor, a mica capacitor, a paper capacitor, a tantalum niobium electrolytic capacitor, or a thin film capacitor, and the type and capacitance value of the first capacitor may be selected according to actual needs.

[0025] As shown in FIG. 5, in one embodiment, based on the embodiment corresponding to FIG. 4, the second switch unit 12 includes a sixth electronic switch 121, a seventh electronic switch 122 and an eighth electronic switch 123; The drain of the sixth electronic switch 121 is respectively connected to the gate of the third electronic switch and the source of the seventh electronic switch 122, and the gate and source of the sixth electronic switch 121 are used to receive the first level signal; The drain of the seventh electronic switch 122 is respectively connected to the drain of the fifth electronic switch and the source of the eighth electronic switch 123, the gate of the seventh electronic switch 122 is used to receive the first clock signal, and the drain of the seventh electronic switch 122 is used to receive the second level signal; The drain of the eighth electronic switch 123 is respectively connected to the drain of the fifth electronic switch and the second stage of the first capacitor, and the gate of the eighth electronic switch 123 is used for receiving the first clock signal.

[0026] In application, the component types of the sixth electronic switch to the eighth electronic switch are the same as the component types of the first electronic switch to the fifth electronic switch, and therefore the description thereof is omitted here.

[0027] FIG. 6 exemplarily illustrates a timing chart of the first clock signal, the gate level of the second electronic switch, the drain level of the second electronic switch, the gate level of the fourth electronic switch, the third level signal, the fourth level signal, and the second clock signal.

[0028] In application, the first level signal always outputs a high level signal, the second level signal always outputs a low level signal, the first clock signal is a periodic clock signal, and the phase difference between adjacent rising edges and falling edges of the first clock signal is 90 degrees. Before the control circuit enters the working state, it needs to go through a standby state. During the first time period, the control circuit enters the first standby state, and the first clock signal receives a low level, so that the first electronic switch is turned off during the first time period, the drain level of the first electronic switch is a low level, making the gate level of the second electronic switch a low level, and when the second electronic switch is turned off, the drain level of the second electronic switch is a low level, so that the source level of the fourth electronic switch is a low level. The gate and source of the sixth electronic switch both receive the first level signal, the sixth electronic switch is turned on and the drain level is high level, the gate level of the third electronic switch is high level, the third electronic switch is turned on and the source of the third electronic switch receives the first level signal, so the drain level of the third electronic switch is high level, the gate level of the fourth electronic switch is high level, the fourth electronic switch is turned on and the source level of the fourth electronic switch is low level, so the drain level of the fourth electronic switch is low level, and the drain level of the fourth electronic switch is the third level signal, so the third level signal is low level. The first clock signal inputs a low level, so the fifth electronic switch, the seventh electronic switch and the eighth electronic switch are turned off within the first time period, and the eighth electronic switch does not output the fourth level signal. The third level signal is low level, and the fourth level signal is not output, so the second clock signal is low level. In addition, in the first preparation state, the voltage magnitudes of the third level signal and the fourth level signal are different, specifically, the third level signal may be a low level, the low level may be -3 V, -5 V, -6 V, or -8 V, etc., and the voltage of the fourth level signal may be 0 V. The embodiments of the present application do not limit the specific voltage values ​​of the low level and the high level.

[0029] In application, during the second time period, the control circuit enters a second ready state, and the first clock signal changes from the low level of the first time period to input a high level, so that during the second time period, the first electronic switch is turned on and the drain level is at a high level, so that the gate level of the second electronic switch is at a high level, the second electronic switch is turned on and the source of the second electronic switch receives the first level signal, so that the drain level of the second electronic switch is at a high level. The gate of the seventh electronic switch is turned on by receiving the first clock signal of a high level, the high level output by the drain of the sixth electronic switch is released as a second level signal through the seventh electronic switch, causing the gate level of the third electronic switch to drop from a high level to a low level, and the third electronic switch is turned off, and further the gate of the fifth electronic switch is turned on by receiving the first clock signal of a high level, the high level at the source of the fifth electronic switch is released as a second level signal through the fifth electronic switch, in combination with the third electronic switch being turned off, causing the source level of the fifth electronic switch to drop from a high level to a low level, the gate level of the fourth electronic switch to drop from a high level to a low level, the fourth electronic switch is turned off, and the output of the third level signal is stopped. Because the gate of the eighth electronic switch receives the first clock signal at a high level, the eighth electronic switch is turned on, and because the source of the eighth electronic switch receives the second clock signal at a low level, the drain level of the eighth electronic switch is at a low level, therefore the fourth level signal is at a low level, stopping the output of the third level signal and the fourth level signal is at a low level, therefore the second clock signal is at a low level.

[0030] In application, the third time period is the time period when the second clock signal outputs a high level, the control circuit enters the first working state, the first clock signal changes from the input high level of the second time period to the input low level, so that the first electronic switch is turned off within the third time period, but the voltage at the gate of the second electronic switch is in a floating state, so that the current voltage at the gate of the second electronic switch is the first voltage, the gate level of the second electronic switch is still at a high level, the second electronic switch is turned on, the drain level of the second electronic switch is consistent with the drain level of the second electronic switch in the second time period and is at a high level, the on state of the third electronic switch is consistent with the on state of the third electronic switch in the first time period, and the description is omitted here, the first clock signal inputs a low level, the gate level of the fifth electronic switch is at a low level, the fifth electronic switch is turned off, so that the gate level of the fourth electronic switch is at a high level, and the source level of the fourth electronic switch is at a high level, so that the third level signal is at a high level. The first clock signal inputs a low level, the gate levels of the seventh electronic switch and the eighth electronic switch are low, the seventh electronic switch is turned off, the eighth electronic switch is turned off and stops outputting the fourth level signal. The third level signal is high, and stops outputting the fourth level signal, so the second clock signal is high. Meanwhile, the third level signal is high, and the voltage at the gate of the second electronic switch is in a floating state, so the first voltage at the gate of the second electronic switch is increased to a second voltage by the coupling effect of the first capacitor, and the voltage value of the first voltage is determined by the voltage value when the first clock signal inputs a high level, and the voltage value of the second voltage is determined by the voltage value when the first clock signal inputs a high level and the coupling effect of the first capacitor.

[0031] In application, the fourth time period is the time period during which the second clock signal outputs a low level, the control circuit enters the second working state, the first clock signal changes from the input low level of the third time period to the input high level, so that the first electronic switch is turned on during the third time period, the voltage at the gate of the second electronic switch is released from the floating state, the voltage at the gate of the second electronic switch returns from the second voltage to the first voltage, the second electronic switch is turned on, and the drain level of the second electronic switch during the fourth time period is consistent with the drain level of the second electronic switch during the third time period and is a high level. The gate of the seventh electronic switch receives the first clock signal of a high level, so that the seventh electronic switch is turned on, and the high level output from the drain of the sixth electronic switch is released as a second level signal through the seventh electronic switch, in combination with the third electronic switch being turned off, the source level of the fifth electronic switch drops from a high level to a low level, the gate level of the fourth electronic switch drops from a high level to a low level, the fourth electronic switch is turned off, and stops outputting the third level signal. The gate of the eighth electronic switch receives the first clock signal at a high level and is turned on, the source of the eighth electronic switch receives the second level signal at a low level, so that the drain level of the eighth electronic switch is at a low level and the fourth level signal is at a low level, the output of the third level signal is stopped, and since the fourth level signal is at a low level, the second clock signal is at a low level.

[0032] In application, after the control circuit finishes preparation of the first time period and the second time period, the operating state of the control circuit changes with the change in level of the first clock signal, specifically, when the first clock signal is at low level, the operating state of the control circuit is consistent with the first operating state of the third time period, and when the first clock signal is at high level, the operating state of the control circuit is consistent with the second operating state of the fourth time period, so that the phase difference between the second clock signal and the first clock signal output from the control circuit is 90 degrees, which realizes a phase shift with respect to the clock signal, reduces the load of the single clock signal, and reduces the number of clock generators in the display panel, thereby reducing the manufacturing cost of the display panel.

[0033] As shown in FIG. 7, in one embodiment, based on the embodiment corresponding to FIG. 1, the control circuit 10 a third switch unit 13 for receiving the first clock signal, the first level signal and the second level signal, and when the first clock signal is at a high level, the third switch unit 13 is turned on and outputs a fifth level signal to the gate driving circuit 20 according to the first clock signal, the first level signal and the second level signal, and when the fifth level signal is at a high level and the first clock signal is at a low level, the third switch unit 13 is turned on and outputs a fifth level signal to the gate driving circuit 20 according to the first clock signal, the first level signal and the second level signal, and the fifth level signal is at a low level; a fourth switch unit 14 connected to the third switch unit 13 for receiving the first clock signal, the first level signal and the second level signal, the fourth switch unit 14 being turned on to output a sixth level signal to the gate driving circuit 20 based on the first clock signal, the first level signal and the second level signal when the first clock signal is at a high level, and being turned off to stop outputting the sixth level signal based on the first clock signal, the first level signal and the second level signal when the sixth level signal is at a low level and the first clock signal is also at a low level.

[0034] Here, the second clock signal includes a fifth level signal and a sixth level signal.

[0035] In application, after the control circuit enters into the working state, when the first clock signal is at a low level, the third switch unit turns on to output a fifth level signal to the gate drive circuit, in this case the fifth level signal is at a high level, and the fourth switch unit turns off to stop outputting a sixth level signal to the gate drive circuit, in this case the sixth level signal is not output, so that the second clock signal is at a high level; when the first clock signal is at a high level, the third switch unit turns on to output the fifth level signal to the gate drive circuit, in this case the fifth level signal is at a low level, and the fourth switch unit turns on to output a sixth level signal to the gate drive circuit, in this case the sixth level signal is at a low level, so that the second clock signal is at a low level, thereby realizing a phase shift with respect to the first clock signal, and the phase difference between the second clock signal and the first clock signal obtained by the phase shift is 90 degrees.

[0036] As shown in FIG. 8 , in one embodiment, based on the embodiment corresponding to FIG. 7 , the third switch unit 13 includes: a ninth electronic switch 131, a tenth electronic switch 132, an eleventh electronic switch 133, a twelfth electronic switch 134, a thirteenth electronic switch 135, a second capacitor 136 and a third capacitor 137; The drain of the ninth electronic switch 131 is respectively connected to the gate of the tenth electronic switch 132, the source of the thirteenth electronic switch 135 and the first electrode of the second capacitor 136, and the source of the ninth electronic switch 131 is used for receiving a first level signal; The drain of the tenth electronic switch 132 is connected to the second electrode of the second capacitor 136 and the source of the twelfth electronic switch 134, and the source of the tenth electronic switch 132 is used to receive a first level signal; The gate and source of the eleventh electronic switch 133 are used to receive the first clock signal; The gate of the twelfth electronic switch 134 is connected to the first electrode of the third capacitor 137 and the drain of the eleventh electronic switch 133, respectively. a gate of the thirteenth electronic switch 135 is used to receive the first clock signal; The gate of the ninth electronic switch 131, the drain of the twelfth electronic switch 134, the drain of the thirteenth electronic switch 135 and the second electrode of the third capacitor 137 are respectively electrically connected to the fourth switch unit.

[0037] In application, the component types of the ninth electronic switch to the thirteenth electronic switch are consistent with the component types of the first electronic switch to the fifth electronic switch, and the types of the second capacitor and the third capacitor are consistent with the type of the first capacitor, and the description here is omitted, and the capacitance values ​​of the second capacitor and the third capacitor can be set according to actual needs.

[0038] As shown in FIG. 9, in one embodiment, based on the embodiment corresponding to FIG. 8, the fourth switch unit 14 includes a fourteenth electronic switch 141, a fifteenth electronic switch 142 and a sixteenth electronic switch 143; The drain of the fourteenth electronic switch 141 is connected to the gate of the ninth electronic switch and the source of the fifteenth electronic switch 142, and the gate and source of the fourteenth electronic switch 141 are used to receive a first level signal; The drain of the fifteenth electronic switch 142 is respectively connected to the drain of the thirteenth electronic switch and the source of the sixteenth electronic switch 143, the gate of the fifteenth electronic switch 142 is used to receive the first clock signal, and the drain of the fifteenth electronic switch 142 is used to receive the second level signal; The drain of the sixteenth electronic switch 143 is respectively connected to the drain of the twelfth electronic switch and the second electrode of the third capacitor, and the gate of the sixteenth electronic switch 143 is used for receiving the first clock signal.

[0039] In application, the component types of the fourteenth electronic switch to the sixteenth electronic switch are the same as the component types of the first electronic switch to the fifth electronic switch, and therefore, description thereof will be omitted here.

[0040] FIG. 10 exemplarily illustrates a timing chart of the first clock signal, the gate level of the tenth electronic switch, the drain level of the tenth electronic switch, the gate level of the twelfth electronic switch, the fifth level signal, the sixth level signal, and the second clock signal.

[0041] In application, the first level signal always outputs a high level signal, the second level signal always outputs a low level signal, the first clock signal is a periodic clock signal, and the phase difference between adjacent rising edges and falling edges of the first clock signal is 90 degrees. The gate and source of the fourteenth electronic switch always receive the first level signal, so the drain level of the fourteenth electronic switch is always at a high level. Before the control circuit enters the working state, it needs to go through a standby state. Within the fifth time period, the control circuit enters the first standby state, the first clock signal inputs a low level, and the eleventh electronic switch, the thirteenth electronic switch, the fifteenth electronic switch and the sixteenth electronic switch are turned off. The high level of the drain of the fourteenth electronic switch is output to the gate of the ninth electronic switch, turning on the ninth electronic switch, and the source of the ninth electronic switch receives the first level signal, so the drain level of the ninth electronic switch is at a high level, the gate level of the tenth electronic switch is at a high level, the tenth electronic switch is turned on, and the drain level of the tenth electronic switch is at a high level. Since the eleventh electronic switch is turned off, the gate level of the twelfth electronic switch is a low level, the twelfth electronic switch is turned off, and the drain level of the twelfth electronic switch is a fifth level signal, so that the twelfth electronic switch does not output a fifth level signal. The sixteenth electronic switch is turned off, and the sixteenth electronic drain level is a sixth level signal, so that the sixteenth electronic switch does not output a sixth level signal. Neither the fifth level signal nor the sixth level signal is output, so that the second clock signal is a low level.

[0042] In application, during the sixth time period, the control circuit enters the second ready state, the first clock signal changes from the input low level during the fifth time period to the input high level, the gate of the fifteenth electronic switch receives the first clock signal of high level, the fifteenth electronic switch is turned on, the high level output from the drain of the fourteenth electronic switch is emitted by the second level signal through the fifteenth electronic switch, causing the gate level of the ninth electronic switch to drop from high level to low level, the ninth electronic switch is turned off, and the gate of the thirteenth electronic switch receives the first clock signal of high level, the thirteenth electronic switch is turned on, the high level at the source of the thirteenth electronic switch is emitted by the second level signal through the thirteenth electronic switch, combined with the ninth electronic switch being turned off, causing the gate level of the tenth electronic switch to drop from high level to low level, the tenth electronic switch is turned off, and the voltage at the drain of the tenth electronic switch is reduced by the coupling effect of the second capacitor, so the drain level of the tenth electronic switch is low level. The first clock signal is at a high level, the eleventh electronic switch is turned on, the gate level of the twelfth electronic switch is at a high level, the twelfth electronic switch is turned on, and the drain level of the twelfth electronic switch is at a low level, so the fifth level signal is at a low level. The first clock signal is at a high level, the sixteenth electronic switch is turned on, and the source of the sixteenth electronic switch receives the second level signal, so the drain level of the sixteenth electronic switch is at a low level, so the sixth level signal is at a low level. The fifth level signal and the sixth level signal are both at a low level, so the second clock signal is at a low level.

[0043] In application, the seventh time period is the time period when the second clock signal outputs a high level, the control circuit enters the first working state, the first clock signal changes from the input high level of the sixth time period to the input low level, so the fifteenth electronic switch is turned off, the ninth electronic switch is turned on, the gate level of the tenth electronic switch is currently at a high level, the tenth electronic switch is turned on, the source of the tenth electronic switch receives the first level signal, so the drain level of the tenth electronic switch is at a high level, and the voltage at the gate of the tenth electronic switch is further increased due to the coupling effect of the third capacitor, so that the tenth electronic switch is turned on more fully. The first clock signal inputs a low level, so the eleventh electronic switch is turned off, but the voltage at the gate of the twelfth electronic switch is in a floating state, the voltage at the gate of the twelfth electronic switch is currently at the third voltage, so that the gate level of the twelfth electronic switch is still at a high level, the twelfth electronic switch is turned on, so that the drain level of the twelfth electronic switch is at a high level, so that the fifth level signal is at a high level. Since the first clock signal inputs a low level, the thirteenth electronic switch, the fifteenth electronic switch and the sixteenth electronic switch are turned off, and since the sixteenth electronic switch is turned off, the output of the sixth level signal is stopped. Since the fifth level signal is a high level, the output of the sixth level signal is stopped, and the second clock signal is a high level. In addition, since the fifth level signal is a high level and the voltage at the gate of the twelfth electronic switch is in a floating state, the current voltage at the gate of the twelfth electronic switch is a third voltage, and due to the coupling effect of the third capacitor, the voltage at the gate of the twelfth electronic switch rises to a fourth voltage, so that the twelfth electronic switch is turned on more fully, and the voltage value of the third voltage is determined by the voltage value when the first clock signal outputs a high level, and the voltage value of the fourth voltage is determined by the voltage value when the first clock signal outputs a high level, the voltage value of the first level signal and the coupling effect of the third capacitor.

[0044] In application, the eighth time period is the time period when the second clock signal outputs a low level, and the control circuit is in a second working state, which is consistent with the first standby state of the control circuit, and is not described here. The difference is that the first clock signal inputs a high level, so the eleventh electronic switch is turned on, the voltage at the gate of the twelfth electronic switch is released from the floating state, and the voltage at the gate of the twelfth electronic switch returns to the third voltage from the fourth voltage.

[0045] In application, after the control circuit finishes preparation for the fifth and sixth time periods, the circuit state of the control circuit changes with the change in the level of the first clock signal, specifically, when the first clock signal is at low level, the operating state of the control circuit coincides with the first operating state of the seventh time period, and when the first clock signal is at high level, the operating state of the control circuit coincides with the second operating state of the fourth time period, so that the phase difference between the second clock signal and the first clock signal output from the control circuit is 90 degrees. Compared with the control circuit composed of the first switch unit and the second switch unit, the control circuit composed of the third switch unit and the fourth switch unit can more fully turn on the third switch unit in the first operating state, and ensure the stability of the clock signal output obtained by phase shifting.

[0046] The control circuit of the display panel provided in the embodiments of the present application is used to receive a first clock signal, a first level signal and a second level signal, and based on the first level signal and the second level signal, phase-shifts the first clock signal to obtain a second clock signal, which is output to a gate driving circuit, so as to realize a phase shift for the clock signal, thereby reducing the load of a single clock signal, and reducing the number of clock generators in the display panel, and reducing the manufacturing cost of the display panel.

[0047] As shown in FIG. 11, an embodiment of the present application further provides a display device 1, which includes a display panel 2 and a control unit 3, where the control unit 3 includes the above-mentioned control circuits.

[0048] The control unit includes a memory, a processor, and a computer program stored in the memory and executable by the processor, and when the processor executes the computer program, realizes the functions of the control circuit embodiment of each of the display panels.

[0049] In application, the processor may be a Timing Controller (Timer Control Register, TCON) or a System on Chip (SOC), may be a Central Processing Unit (CPU), the processor may further be another general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, etc. The general purpose processor may be a microprocessor or the processor may be any general purpose processor, etc.

[0050] In application, the memory may be an internal storage unit of the terminal device in some embodiments, such as a hard disk or memory of the terminal device. The memory may be an external storage device of the terminal device in other embodiments, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) card, a Flash Card, etc., disposed in the terminal device. In addition, the memory may not only include the internal storage unit of the terminal device, but also include an external storage device. The memory is used to store an operating system, an application program, a boot loader, data, and other programs, such as program code of a computer program, etc. The memory may also be used to temporarily store data that is output or to be output.

[0051] The above embodiments are only for illustrating the technical solutions of the present application, and are not intended to limit the same. Although the present application has been described in detail with reference to the above embodiments, it is still possible to modify the technical solutions described in the above embodiments, or to replace some of the technical features thereof with equivalents, and it should be understood by those skilled in the art that such modifications or replacements do not deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and all of them should be included in the protection scope of the present application.

Claims

1. A control circuit for a display panel, the control circuit receives a first clock signal, a first level signal and a second level signal, and phase-shifts the first clock signal according to the first level signal and the second level signal to obtain a second clock signal, and outputs the second clock signal to a gate driving circuit, wherein the second clock signal includes a third level signal and a fourth level signal, the first level signal and the second level signal have different level magnitudes, the third level signal and the fourth level signal have different level magnitudes, the first level signal and the third level signal have the same level magnitude, and the second level signal and the fourth level signal have the same level magnitude; the control circuit includes a first switch unit and a second switch unit, the first switch unit is connected to the second switch unit; the first switch unit receives the first clock signal, the first level signal and the second level signal, and outputs a third level signal to the gate driving circuit according to the first clock signal, the first level signal and the second level signal; the second switch unit receives the first clock signal, the first level signal and the second level signal, and outputs a fourth level signal to the gate driving circuit according to the first clock signal, the first level signal and the second level signal; the first switch unit includes a first electronic switch, a second electronic switch, a third electronic switch, a fourth electronic switch, a fifth electronic switch and a first capacitor; a drain of the first electronic switch is connected to a gate of the second electronic switch, and a gate and a source of the first electronic switch are used to receive the first clock signal; a drain of the second electronic switch is connected to a source of the fourth electronic switch, and a source of the second electronic switch is used to receive the first level signal; a drain of the third electronic switch is connected to a source of the fifth electronic switch and a gate of the fourth electronic switch, respectively, and a source of the third electronic switch is used for receiving the first level signal; a first electrode of the first capacitor is respectively connected to the drain of the first electronic switch and the gate of the second electronic switch, and a drain of the fifth electronic switch is used for receiving the second level signal; a gate of the third electronic switch, a gate of the fifth electronic switch, a drain of the fourth electronic switch and a second electrode of the first capacitor are respectively electrically connected to the second switch unit; the drain of the fourth electronic switch outputs the third level signal;

2. The second switch unit includes a sixth electronic switch, a seventh electronic switch, and an eighth electronic switch, the drain of the sixth electronic switch is respectively connected to the gate of the third electronic switch and the source of the seventh electronic switch, and the gate and the source of the sixth electronic switch are used to receive the first level signal; a drain of the seventh electronic switch is respectively connected to a drain of the fifth electronic switch and a source of the eighth electronic switch, a gate of the seventh electronic switch is used for receiving the first clock signal, and a drain of the seventh electronic switch is used for receiving the second level signal; a drain of the eighth electronic switch is respectively connected to a drain of the fourth electronic switch and a second electrode of the first capacitor, and a gate of the eighth electronic switch is used for receiving the first clock signal; The control circuit for a display panel according to claim 1 , wherein the fourth level signal is output from a drain of the eighth electronic switch.

3. 2. The control circuit for a display panel according to claim 1, wherein the fourth electronic switch of the first switch unit is further configured to be turned on and output a third level signal of a high level to the gate driving circuit according to the first clock signal, the first level signal and the second level signal when the first clock signal is at a low level.

4. 2. The control circuit for a display panel according to claim 1, wherein the fourth electronic switch of the first switch unit is further turned off and stops outputting the third level signal to the gate driving circuit based on the first clock signal, the first level signal and the second level signal when the first clock signal is at a high level.

5. 3. The control circuit for a display panel according to claim 2, wherein the eighth electronic switch of the second switch unit is further configured to be turned on and output a fourth level signal of a low level to the gate driving circuit according to the first clock signal, the first level signal and the second level signal when the first clock signal is at a high level.

6. 3. The control circuit for a display panel according to claim 2, wherein the eighth electronic switch of the second switch unit is further turned off and stops outputting the fourth level signal to the gate driving circuit according to the first clock signal, the first level signal and the second level signal when the first clock signal is at a low level.

7. A control circuit for a display panel, the control circuit receives a first clock signal, a first level signal and a second level signal, and phase-shifts the first clock signal according to the first level signal and the second level signal to obtain a second clock signal and output it to a gate driving circuit, wherein the second clock signal includes a fifth level signal and a sixth level signal, the first level signal and the second level signal have different level magnitudes, the fifth level signal and the sixth level signal have different level magnitudes, the first level signal and the fifth level signal have the same level magnitude, and the second level signal and the sixth level signal have the same level magnitude; the control circuit includes a third switch unit and a fourth switch unit, the third switch unit is connected to the fourth switch unit; the third switch unit includes a ninth electronic switch, a tenth electronic switch, an eleventh electronic switch, a twelfth electronic switch, a thirteenth electronic switch, a second capacitor and a third capacitor; a drain of the ninth electronic switch is respectively connected to the gate of the tenth electronic switch, the source of the thirteenth electronic switch and the first electrode of the second capacitor, and a source of the ninth electronic switch is used for receiving the first level signal; a drain of the tenth electronic switch is connected to a second electrode of the second capacitor and a source of the twelfth electronic switch, and a source of the tenth electronic switch is used to receive the first level signal; a gate and a source of the eleventh electronic switch are used to receive the first clock signal; a gate of the twelfth electronic switch is connected to a first electrode of the third capacitor and a drain of the eleventh electronic switch, a gate of the thirteenth electronic switch is used to receive the first clock signal; the gate of the ninth electronic switch, the drain of the twelfth electronic switch, the drain of the thirteenth electronic switch and the second electrode of the third capacitor are respectively electrically connected to the fourth switch unit; The fifth level signal is output from a drain of the twelfth electronic switch; the fourth switch unit includes a fourteenth electronic switch, a fifteenth electronic switch and a sixteenth electronic switch; a drain of the fourteenth electronic switch is connected to a gate of the ninth electronic switch and a source of the fifteenth electronic switch, and a gate and a source of the fourteenth electronic switch are used to receive the first level signal; a drain of the fifteenth electronic switch is connected to a drain of the thirteenth electronic switch and a source of the sixteenth electronic switch, a gate of the fifteenth electronic switch is used to receive the first clock signal, and a drain of the fifteenth electronic switch is used to receive the second level signal; a drain of the sixteenth electronic switch is respectively connected to a drain of the twelfth electronic switch and a second electrode of the third capacitor, and a gate of the sixteenth electronic switch is used for receiving the first clock signal; The sixth level signal is output from a drain of the sixteenth electronic switch; the twelfth electronic switch of the third switch unit receives the first clock signal, the first level signal, and the second level signal, and is turned on to output a fifth level signal of a high level to the gate driving circuit according to the first clock signal, the first level signal, and the second level signal when the first clock signal is at a high level, and is turned off to stop outputting the fifth level signal according to the first clock signal, the first level signal, and the second level signal when the first clock signal is at a low level; the sixteenth electronic switch of the fourth switch unit receives the first clock signal, the first level signal, and the second level signal, and is turned on to output a sixth level signal of a low level to the gate driving circuit according to the first clock signal, the first level signal, and the second level signal when the first clock signal is at a high level, and is turned off to stop outputting the sixth level signal according to the first clock signal, the first level signal, and the second level signal when the first clock signal is at a low level.

8. 2. The control circuit for a display panel according to claim 1, wherein the first level signal is a high level signal, and the second level signal is a low level signal.

9. The display panel control circuit according to claim 1 , wherein the second clock signal and the first clock signal have a phase difference of 180 degrees.

10. A display device, comprising: A display panel; A control unit including the control circuit of claim 1; A display device comprising:

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