Reduced border width around holes in display active area

Abstract

The electronic device may include a display having display pixels formed in an active area of ​​the display. The display further includes display driver circuitry for driving gate lines routed across the display. Holes, such as through-holes, optical windows, or other inactive areas, may be formed in the active area of ​​the display. Multiple gate lines carrying the same signal may be merged together before being routed around the hole to help minimize congestion of the routing lines around the hole's boundaries. Dummy circuitry may be coupled to portions of the merged segments to help increase parasitic loading on the merged segments. The holes may have a tapered shape to help maximize the size of the active area. The holes may have an asymmetric shape to accommodate multiple sub-display sensor components.

Description

[Technical field]

[0001] This application claims priority to U.S. Patent Application No. 17 / 145,815, filed January 11, 2021, and U.S. Provisional Patent Application No. 63 / 001,949, filed March 30, 2020, each of which is incorporated by reference in its entirety. [Background technology]

[0002] The present application relates generally to electronic devices, and more particularly, to electronic devices having a display.

[0003] Electronic devices often include a display. Displays are typically driven using display driver circuits and gate driver circuits. The display driver circuits provide data signals via data lines to corresponding display pixels, while the gate driver circuits provide control signals via gate lines to selectively load data signals onto a subset of the display pixels. The display pixels are formed in an area sometimes referred to as an active area. Designing a display with a rectangular, uninterrupted active area is generally straightforward, as the data and gate lines may be routed in a regular grid-like pattern across the display.

[0004] However, some displays may deviate from the conventional active area and have one or more holes or inactive regions within the active area. Routing data and gate lines within such types of displays with holes in the active area can be difficult. If care is not taken, the display border near the holes can become overly crowded, resulting in an increase in border width. Summary of the Invention

[0005] The electronic device may include a display having an array of display pixels formed in an active area of ​​the display. One or more inactive regions may be formed in the active area. The inactive regions may be through-holes, non-through-hole optical windows, or other types of openings in the display that are devoid of pixels. The display may further include a display driver circuit configured to output a control signal to a first row control line coupled to a first row of display pixels and to output a control signal to a second row control line coupled to a second row of display pixels, where the first and second row control lines are merged into a segment (i.e., a merged segment), which is routed by the inactive region. The control signal may be a scan line signal, an emission line signal, an initialization line signal, a reset signal, an enable signal, a data line signal, a reference signal, or other suitable data / control signal that is simultaneously provided to two or more rows of pixels in the active area.

[0006] If desired, a dummy circuit, such as a capacitor circuit, may be coupled to the merged segment and may be configured to increase parasitics on the first and second row control lines. The merged segment may be coupled between a first merge node and a second fan-out / split node. The first node may be connected to the first and second row control lines. The merged segment may be configured to split into at least first and second additional row control lines at the second fan-out node.

[0007] The display driver circuitry may be formed on one side of the display. The display may further include an additional display driver circuitry configured to output additional control signals to a third row control line coupled to the first row of display pixels and to output additional control signals to a fourth row control line coupled to the second row of display pixels. The third and fourth row control lines may be merged into an additional segment routed by the inactive area. If desired, more than two parallel row control lines may be connected to the merged segment.

[0008] In one preferred configuration, the inactive area may have a substantially rounded or circular shape. In another preferred configuration, the inactive area may have a substantially rectangular shape. In yet another preferred configuration, the inactive area may have a symmetric or asymmetric tapered shape optimized to increase the size of the active area.

[0009] Both row lines, which extend horizontally across the face of the display, and column lines, which extend vertically across the face of the display, may extend into a hole boundary region that surrounds the inactive area. The hole boundary region may define a hole boundary width and may not overlap with the active area. In another suitable configuration, only the row lines may extend into the hole boundary region, but the column lines do not extend into the hole boundary region, remaining within the active area when routing around the inactive area. In yet another suitable configuration, only the column lines may extend into the hole boundary region, but the row lines do not extend into the hole boundary region, remaining within the active area when routing around the inactive area. The row / column lines that remain within the active area may overlap one or more display pixels and may be formed using a top metal layer, such as one of the anode layer, source-drain metal routing layer, or touch sensor layer, or using a buried metal layer formed above the substrate layer and below the low-temperature polysilicon layer. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 illustrates an exemplary electronic device having a display, according to one embodiment. [Diagram 2] FIG. 2 is a top view of an exemplary display in an electronic device, according to one embodiment. [Diagram 3] FIG. 1C is a top view of a display circuitry illustrating how a multi-row single-sided gate driver circuit can be configured to drive corresponding gate lines that are merged before being routed around holes in the display active area, according to one embodiment. [Figure 4A] 2 is a side cross-sectional view of an exemplary through-hole that may be formed in a display active area, according to one embodiment. [Figure 4B] 2 is a cross-sectional side view of an exemplary optical window that may be formed in a display active area, according to one embodiment. [Diagram 5] FIG. 13 is a top view illustrating how gate line merging and splitting can occur from both sides of a hole, according to one embodiment. [Figure 6] FIG. 1 is a top view of an exemplary display circuitry illustrating how a multi-row single-sided gate driver circuit can be configured to drive corresponding gate lines that are merged before being routed directly above the optical window, according to one embodiment. [Figure 7] FIG. 13 illustrates how three or more control lines can be connected together at the edge of a hole, according to one embodiment. [Figure 8A] FIG. 13 is a top view illustrating a dummy loading circuit that may be mounted near the smaller hole, according to one embodiment. [Figure 8B] 1A-1C illustrate holes of different sizes and shapes that may be formed in a display active area according to some embodiments. [Figure 8C] 1A-1C illustrate holes of different sizes and shapes that may be formed in a display active area according to some embodiments. [Figure 8D] 1A-1C illustrate holes of different sizes and shapes that may be formed in a display active area according to some embodiments. [Figure 8E] 1A-1C illustrate holes of different sizes and shapes that may be formed in a display active area according to some embodiments. [Figure 8F] 1A-1C illustrate holes of different sizes and shapes that may be formed in a display active area according to some embodiments. [Figure 9A]1 is a top view illustrating a minimum hole boundary envelope associated with a data line routed around a hole, according to one embodiment. [Figure 9B] FIG. 11B is a top view illustrating how the display active area is limited by the minimum hole boundary envelope shown in FIG. 11A according to one embodiment. [Figure 10A] FIG. 13 illustrates how the size of the minimum hole bounding envelope can be reduced by reshaping the hole, according to one embodiment. [Figure 10B] 13A-13C illustrate how a hole can be asymmetrically tapered according to one embodiment. [Figure 11] FIG. 1C is a top view of an example touch sensing circuitry illustrating how multiple rows of single-sided touch sensing circuits may be coupled to corresponding sense lines that are shorted together before being routed around holes in the active area, in accordance with one embodiment. [Figure 12A] FIG. 13 is a top view illustrating row and column lines routed to hole boundary regions outside of the active area, according to one embodiment. [Figure 12B] FIG. 13 is a top view illustrating row lines routed to hole bounding regions and column lines routed inside the active area, according to one embodiment. [Figure 12C] FIG. 13 is a top view illustrating column lines routed to hole bounding regions and row lines routed inside the active area, according to one embodiment. [Figure 13] FIG. 2 is a cross-sectional side view of an exemplary display stackup, according to one embodiment. [Figure 14] FIG. 2 is a cross-sectional side view of an exemplary thin film transistor (TFT) layer, according to one embodiment. [Figure 15] FIG. 2 is a cross-sectional side view illustrating one preferred configuration of a buried metal layer, according to one embodiment. [Figure 16] FIG. 2 is a cross-sectional view illustrating another preferred configuration of a buried metal layer, according to one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Exemplary types of electronic devices that may include a display are shown in Figure 1. The electronic device 10 of Figure 1 may be a tablet computer, a laptop computer, a desktop computer, a monitor with an embedded computer, a monitor without an embedded computer, a display for use with a computer or other equipment external to the display, a mobile phone, a media player, other wearable electronic devices such as a watch-type device or a head-mounted device, or other suitable electronic device.

[0012] As shown in FIG. 1, electronic device 10 may have control circuitry 16. Control circuitry 16 may include storage and processing circuitry to support operation of device 10. The storage and processing circuitry may include storage devices such as hard disk drive storage, non-volatile memory (e.g., flash memory or other electrically programmable read-only memory configured to form a solid-state drive), volatile memory (e.g., static or dynamic random access memory), etc. Processing circuitry in control circuitry 16 may be used to control operation of device 10. The processing circuitry may be based on one or more microprocessors, microcontrollers, digital signal processors, baseband processors, power management units, audio chips, application specific integrated circuits, etc.

[0013] Input / output circuitry within device 10, such as input / output device 12, may be used to enable data to be provided to device 10 and to enable data to be provided from device 10 to external devices. I / O device 12 may include buttons, joysticks, scroll wheels, touch pads, keypads, keyboards, microphones, speakers, sound sources, vibrators, cameras, sensors, light emitting diodes and other status indicators, data ports, and the like. A user may control the operation of device 10 by providing commands through the input resources of I / O device 12 and may receive status information and other output from device 10 via the output resources of I / O device 12.

[0014] Input / output device 12 may include one or more displays, such as display 14. Display 14 may be a touchscreen display that includes touch sensors for collecting touch input from a user, or display 14 may not be touch-sensitive. The touch sensors for display 14 may be based on an array of capacitive touch sensor electrodes, acoustic touch sensor structures, resistive touch components, force-based touch sensor structures, optically-based touch sensors, or other suitable touch sensor devices.

[0015] Control circuitry 16 may be used to execute software on device 10, such as operating system code and applications. During operation of device 10, software executing on control circuitry 16 may use the array of pixels in display 14 to display images on display 14. Display 14 may have a substantially rectangular shape (i.e., display 14 may have a rectangular footprint and a rectangular perimeter extending around the perimeter of the rectangular footprint) or may have other suitable shapes. Display 14 may be flat or may have a curved contour. Display 14 may be an organic light emitting diode display, a liquid crystal display, a liquid crystal on silicon display, a microelectromechanical system (MEM) display, or other suitable type of display.

[0016] It may be desirable to incorporate electrical components into device 10 and / or within or below display 14. For example, components 18 may be audio components (e.g., microphones, speakers, etc.), radio frequency components, tactile components (e.g., piezoelectric structures, vibrators, etc.), capacitive touch sensor components or other touch sensor structures, temperature sensors, pressure / force sensors, magnetic sensors, fingerprint sensors, or other sensors, or any other suitable type of electrical component. In one suitable configuration that may be described herein by way of example, electrical components 18 may be light-based sensor components (e.g., ambient light sensors, proximity sensors, or components that emit and / or detect visible, infrared, and / or ultraviolet light).

[0017] Examples of light-based components 18 that emit light include light-emitting diodes (e.g., organic light-emitting diodes, discrete crystal light-emitting diode dies, etc.), lasers, and lamps. Examples of light-based components that detect light include photodetectors such as photodiodes and phototransistors. Some components may include both light emitters and detectors, as desired. For example, component 18 may emit infrared light and include a photodetector structure for detecting a portion of the emitted light reflected from a nearby object. This type of component may be used to implement a proximity sensor.

[0018] FIG. 2 is a top (layout) view of an exemplary display 14 in an electronic device 10. As shown in FIG. 2, the display 14 can have an array of pixels 22 formed from a substrate structure, such as a substrate 36. The area on the substrate 36 in which the array of pixels 22 is formed may be referred to as the "active area" (AA). The area(s) outside the active area may be referred to as the inactive area or inactive regions. A substrate, such as the substrate 36, may be formed from glass, metal, plastic, ceramic, or other substrate material. The pixels 22 may receive data signals through signal paths, such as data lines D, and may receive one or more control signals through control signal paths, such as gate lines G (which may also be referred to as control lines, scan lines, light emission enable lines, gate signal paths, etc.). There may be any suitable number of rows and columns of pixels 22 in the display 14 (e.g., tens or more, hundreds or more, or thousands or more). The pixels 22 may have different colors (e.g., red, green, and blue), providing the display 14 with the ability to display color images. The pixel circuit of pixel 22 may include a transistor (e.g., a thin film transistor on substrate 36) having a gate controlled by a gate line signal on gate line G. The terms "row" and "column" may be used to refer to any array of display pixels, and are sometimes used interchangeably (e.g., gate lines may also be called column lines and data lines may be called row lines).

[0019] Display driver circuitry 20 may be used to control the operation of pixels 22. Display driver circuitry 20 may be formed from integrated circuits, thin film transistor circuitry, or other suitable circuitry. The thin film transistor circuitry for display driver circuitry 20 and pixels 22 may be formed from polysilicon thin film transistors, semiconductor oxide thin film transistors such as indium gallium zinc oxide (IGZO) transistors, or thin film transistors formed from other semiconductor materials.

[0020] Display driver circuitry 20 may include display driver circuits such as display driver circuitry 20A and gate driver circuitry 20B. Display driver circuitry 20A may include one or more display driver integrated circuits (e.g., a timing controller integrated circuit) and / or display driver circuit 20A-1 formed from thin film transistor circuitry, and may include demultiplexer circuitry 20A-2 (e.g., a demultiplexer formed from thin film transistor circuitry or formed within an integrated circuit). Gate driver circuitry 20B may be formed from thin film transistor circuitry or may be formed within a gate driver integrated circuit.

[0021] Display driver circuitry 20A may include communication circuitry for communicating with system control circuitry, such as control circuitry 16 of FIG. 1, through paths 32. Paths 32 may be formed from traces on a flexible printed circuit or other conductive lines. During normal operation, control circuitry (e.g., control circuitry 16 of FIG. 1) may provide circuitry 20A with information regarding an image to be displayed on display 14. To display an image on display pixels 22, display driver circuitry 20A may provide image data to data lines D while issuing control signals (e.g., clock signals, gate start pulses, etc.) to support display driver circuitry, such as gate driver circuitry 20B, through paths 38. Display driver circuitry 20A may also dynamically adjust demultiplexer circuitry 20A-2 by providing clock signals, select signals, and / or other control signals to demultiplexer circuitry 20A-2. If desired, gate driver circuitry may optionally be formed on more than one side of display 14 (see, for example, gate driver circuitry 20B' formed on opposing edges of substrate 36). In such a configuration, display driver circuitry 20A may also issue control signals to support gate driver circuitry 20B' over path 38'.

[0022] 3 is a plan view of one implementation of display 14, showing how a multi-row single-sided gate driver may be used to drive corresponding gate lines routed around holes in the active area when viewed from in front of the display surface in direction Z toward the XY plane. In one suitable configuration, display 14 may be substantially coplanar with the XY plane (i.e., the display substrate is formed in a single plane). In another suitable configuration, display 14 may instead be curved and protrude out of the XY plane. In general, device 10 (and display 14) may assume any suitable shape.

[0023] 3A, gate driver circuitry 20B is formed only on one edge of the display (i.e., no gate driver circuitry 20B' is formed on the right edge of the display). The gate driver circuitry 20B may include a number of gate drivers 21 configured to drive corresponding gate lines G. Gate driver 21-1 may be configured to drive a first gate line pair coupled to the first and second rows of display pixels 22. Gate driver 21-2 may be configured to drive a second gate line pair coupled to the third and fourth rows of display pixels 22. Gate driver 21-3 may be configured to drive a third gate line pair coupled to the fifth and sixth rows of display pixels 22. In FIG. 3, each individual gate driver circuit 21 may be configured to generate a corresponding row control signal A, but the waveforms output from each circuit 21 may be offset in time with respect to each other. For example, circuit 21-1 may output a control signal A(1), circuit 21-2 may output a control signal A(2), circuit 21-3 may output a control signal A(3), etc.

[0024] In certain embodiments, holes, such as hole 300, may be formed in the display active area. Hole 300 may be at least partially or completely surrounded by the active area. The term "hole" generally refers to an area in the active area that does not include any display pixels, and may be a through-hole (e.g., an opening formed from a top surface of the display substrate through a bottom surface of the display substrate), an optical window (e.g., a portion of a continuous display substrate through which an optical signal can still pass through the substrate), or other inactive area.

[0025] 4A is a side cross-sectional view of an exemplary through-hole that may be formed in a display active area. As shown in FIG. 4A, the display may generally include a substrate layer 400 (which may be equivalent to substrate 36 described in connection with FIG. 2), a thin film transistor (TFT) routing layer 402 formed on the substrate 400, and an encapsulation layer 404 covering the TFT routing layer 402. Display pixel structures and associated routing lines, display driver circuitry, and / or gate driver circuitry may be formed in the TFT routing layer 402. The encapsulation layer 404 may include some combination of organic and inorganic layers configured to help prevent moisture and / or other contaminants from penetrating the TFT routing layer 402.

[0026] In the example of FIG. 4A , the hole 300 may be implemented as a through hole that extends completely through the display substrate layer 400 (i.e., the non-active area 300 may be a hole drilled or cut through the entire thickness of the substrate 400). If desired, one or more components, such as a light sensor 18 of the type described in connection with FIG. 1 , may be positioned directly below the hole 300 such that light or other signals traverse the hole 300 to reach the sensor 18. The hole 300 may be defined by a substrate edge 490. The TFT routing layer 402 must be formed at a minimum distance Δ from the substrate edge 490 so that the encapsulation layer 404 can be properly formed (e.g., so that the encapsulation layer 404 can be tapered). This minimum distance Δ may therefore be referred to as the encapsulation finish margin. The distance Δ thus defines the closest point at which a control line routing segment (formed in the TFT routing layer 402) may be formed relative to the edge of the hole 300.

[0027] 4B is a side cross-sectional view of an exemplary optical window that may be formed in a display active area according to another preferred embodiment. As shown in FIG. 4B, a display may generally include a substrate layer 400, a thin film transistor (TFT) routing layer 402 formed on the substrate 400, and an encapsulation layer 404 covering the TFT routing layer 402. Display pixel structures and associated routing lines, display driver circuitry, and / or gate driver circuitry may be formed in the TFT routing layer 402. The encapsulation layer 404 may include some combination of organic and inorganic layers configured to help prevent moisture and / or other contaminants from penetrating the TFT routing layer 402.

[0028] In the example of Figure 4B, the hole 300 may be implemented as an optical window that allows light or other signals to pass through the substrate 400. Unlike the cut through hole of Figure 4A, the optical window 300 of Figure 4B includes a continuous substrate layer 400 that completely overlaps the window 300 (when viewed from above the front of the display). Because there is no interruption of the substrate 400 in the inactive hole region 300, a sealing layer 404 may also be formed above the hole region 300. The presence of layers 400 and 404 does not prevent light or other desired signals from traversing the optical window 300.

[0029] If desired, one or more components, such as a light sensor 18 of the type described in connection with FIG. 1, may be positioned directly below the optical window 300 so that light or other signals can traverse the window 300 to reach the sensor 18. Because the substrate is not actually cut through in the optical window 300 (i.e., there are no substrate edges within the optical window area), the TFT routing layer 402 is not constrained by encapsulation finishing margins. Thus, the TFT routing layer 402 may be formed all the way up to the edge of the optical window 300. Comparing FIGS. 4A and 4B, it can be seen that the TFT routing layer 402 may be formed closer to the edge of the hole 300 in the optical window configuration of FIG. 4B. In other words, the control line routing segments (formed in the TFT routing layer 402) may be formed closer to the boundary of the hole 300 when the hole 300 is implemented as an optical window, which may help reduce the overall hole boundary width.

[0030] 3, the gate lines formed above and below the inactive area 300 may be straight and coupled to display pixels 22 spaced at regular intervals (see, e.g., gate line G driven by circuits 21-1 and 21-3). In contrast, the gate lines formed in the rows that overlap the holes 300 must be routed around the holes 300 (see, e.g., gate line G driven by circuit 21-2). In conventional displays with multi-row gate driver circuits, the two gate lines in each gate line pair must be routed around the boundaries of the holes 300, resulting in congestion of the routing lines and a dramatic increase in the minimum required border width surrounding the holes 300.

[0031] According to an embodiment, a multi-row driving scheme may have multiple routing lines merged before being routed around the hole 300. As shown in FIG. 3A, each driver circuit 21 may be a multi-row driver circuit configured to generate a control signal A (e.g., a scan line signal, an emission line signal, or other row control signal) that is simultaneously supplied to two adjacent rows of pixels. In other words, the circuit 21 may be configured to output a signal A(n) to rows n and (n+1). For example, the driver circuit 21-2 may be configured to drive a control signal A on a first linear / straight line segment coupled to a third row of pixels located in the active area to the left of the hole 300, and on a second linear / straight line segment coupled to a fourth row of pixels located in the active area to the left of the hole 300. The second linear segment may merge with the first linear segment via a connecting / shorting segment 802 such that the first and second linear (straight) segments combine or merge at a node 804. From this point, a single (merged) routing line or merged segment 805 (sometimes called an intermediate routing segment) may be routed around and along the boundary of hole 300 to reach the active area to the right of hole 300.

[0032] The merged routing segment (which may be curved or have any suitable trajectory depending on the shape of the hole 300) may extend from node 804 to node 806. At node 806, the merged routing segment 805 may be split into a third linear segment and a fourth linear segment using a fan-out segment 808. The third linear segment may be coupled to a third row of pixels located in the active area to the right of the hole 300, while the fourth linear segment may be coupled to a fourth row of pixels located in the active area to the right of the hole 300.

[0033] Although FIG. 3 shows only six pixel rows, a display may generally include any number of gate driver circuits (e.g., hundreds or thousands of individual multi-row gate drivers) formed on the left and / or right edges of the display, each capable of outputting gate line signals or row control signals to two or more rows of display pixels. The example of FIG. 3, in which the hole 300 overlaps approximately two pixel rows and four pixel columns, is merely illustrative and is not intended to limit the present embodiment. In general, the hole 300 may have X and / or Y dimensions that span from 2 to 10 displays, from 10 to 100 pixels, hundreds or thousands of pixels, etc. (e.g., the hole 300 has a Y dimension that spans any suitable number of pixel columns and an X dimension that spans any suitable number of pixel columns). Thus, any intermediate merged segments routed around the hole 300 may potentially represent paths having lengths of several microns to several millimeters that are not interrupted by pixels.

[0034] The merged routing segment 805 connected between nodes 804 and 806 may be completely devoid of pixels 22 (i.e., no pixels connected to intermediate routing segments routed around hole 300). Thus, the number of pixels formed along the entirety of such a gate line may differ from the number of gate lines of a normal pixel row in which pixels are formed at regular uninterrupted intervals (the number of pixels 22 connected to a first gate line feeding a first pixel row is greater than the number of pixels connected to a third gate line feeding a third pixel row, see FIG. 3). To help match the load of the routing lines coupled to the fewer display pixels to the load on the normal gate lines, dummy circuit components such as dummy circuit 850 may be coupled to the pixel-devoid merged routing segment to help mimic the load of the display pixels that would have been formed between the merge node and the split node if hole 300 had not been in the way. Dummy circuit 850 may be a capacitance circuit, a dummy transistor structure, a dummy pixel structure, a passive electrical component, or other suitable load component that occupies a minimum circuit area to help reduce routing congestion around hole 300. Intentionally providing parasitic loads in this manner to balance the load among all row control / routing lines can help reduce undesirable display artifacts.

[0035] The merging of routing lines at one edge of the hole 300 and splitting / fanning out of routing lines at the other edge of the hole 300 described above for the multi-row gate driver circuit 21-2 of FIG. 3 may also be applied to a multiple gate driver 21′ formed along the opposite edge of the display (see, for example, FIG. 5). As shown in FIG. 5, the multiple gate driver 21′ may be configured to output a control signal B to at least two pixel rows in parallel (e.g., the circuit 21′ may be configured to output a signal B(n) to rows n and (n+1). The hole 300 may be at least partially physically interposed between the circuits 21 and 21′. As shown in FIG. 5, merging of the linear gate line segments originating from the circuit 21′ may occur at node 820, while fanning out to multiple linear gate line segments after being routed around the hole 300 may occur at node 822. The merged routing segment 821 coupled between nodes 820 and 822 may help reduce routing line congestion for the gate lines associated with the multiple row driver circuit 21′. Since routing congestion determines the minimum hole border width, merging or shorting multiple row control lines in this manner can dramatically reduce the border width around the hole 300. If desired, dummy circuitry 850 may also be attached to the intermediate routing segments 821 to facilitate load balancing.

[0036] The examples of Figures 3 and 5 in which merged routing lines are routed around the hole 300 are merely illustrative. It may be necessary to route around or around the hole 300 if the hole 300 is implemented as a through hole of the type described in connection with Figure 4A or as another structure that prevents or impedes routing lines from being routed through the inactive hole region. In other suitable configurations, such as when the hole 300 is implemented as an optical window of the type shown in Figure 4B, the merged routing lines may be routed directly over and through the hole region 300, as shown in the top (layout) view of Figure 6. In other words, the control lines that are routed across the hole 300 do not need to be routed along the boundary of the hole 300, but can remain as straight / rectilinear segments. Such routing configurations may be used as long as the hole 300 is not implemented as a cut through hole.

[0037] 3, 5, and 6, in which a multi-row gate driver circuit is configured to drive control signals to pixels arranged along two adjacent rows, are merely illustrative and are not intended to limit the scope of the present embodiment. In general, a single peripheral driver circuit, such as a multi-row driver circuit 21 as shown in FIG. 7, may be configured to simultaneously generate corresponding control signals A (e.g., scan signals, light emission signals, initialization signals, reference signals, reset signals, enable signals, row control signals, column control signals, etc.) to three or more control lines (e.g., three or more row control lines of adjacent / contiguous rows, three or more row control lines of non-adjacent / non-contiguous rows, 4-10 row control signals of adjacent or non-contiguous rows, etc.), where the multiple row control lines carrying the same signal waveform output from the circuit 21 are merged or connected at a shorting node 904, and the merged single routing segment 905 is routed around or directly through the hole 300.

[0038] The embodiment of FIGS. 3-7 in which the display 14 includes one hole 300 is merely illustrative and is not intended to limit the scope of the present embodiment. According to some embodiments, the display may include two or more holes formed in the active area (see, for example, FIG. 8A). As shown in FIG. 8A, the display 14 may include at least a first hole 300-1 and a second hole 300-2 formed in the active area. Each of the holes 300-1 and 300-2 may correspond to a through hole of the type described in connection with FIG. 4A, an optical window of the type described in connection with FIG. 4B, or other inactive area lacking display pixels. The holes 300-1 and 300-2 need not be the same size and shape. In the example of FIG. 8A, the holes 300-1 and 300-2 have different sizes and shapes (e.g., the hole 300-1 may be larger than the hole 300-2, and the hole 300-1 may be circular while the hole 300-2 may be elliptical).

[0039] In such a configuration, potential routing congestion near the boundaries of the large hole 300-1 may be more pronounced than routing congestion near the boundaries of the small hole 300-2, because the space occupied by the small hole 300-2 is necessarily less. As shown in FIG. 8A, a merged routing segment connecting node 804 in the active area to the left of hole 300-1 to node 806 in the active area to the right of hole 300-2 may have more space to route near the small hole 300-2 (e.g., the intermediate routing segment connecting nodes 804 and 806 may have a first serpentine portion that needs to be routed around hole 300-1 and a second straight portion that takes a more direct path to node 806). Because there is more free circuit area around the small hole 300-2, dummy loading circuitry may be physically formed near the small hole. For example, a first dummy loading component 850A coupled to a first merged routing segment 805 carrying control signal A may be formed in the free space above hole 300-2 (when viewed in the Z direction toward the XY plane in front of the display), while a second dummy loading component 850B coupled to a second merged routing segment 821 carrying control signal B may be formed in the free space located below hole 300-2. Thus, in general, it may be desirable to form dummy loading circuitry near, around, or at the boundaries of smaller inactive areas.

[0040] In general, the inactive hole(s) in the active area of ​​the display may have any suitable shape and / or size, and there may be any desired number of holes of the same or different sizes / shapes. FIG. 8B illustrates three or more circular holes 300-1, 300-2, and 300-3 of different sizes that may be formed in the active area of ​​the display. FIG. 8C illustrates two or more rectangular holes 300-1 and 300-2 of different sizes (e.g., holes of a shared shape) that may be formed in the active area of ​​the display. FIG. 8D illustrates how a display may include at least two circular holes 300-1 and 300-2 of the same size and shape, at least a square hole 300-3, and / or a smaller triangular hole 300-4. FIG. 8E illustrates how a display may include at least a larger hole 300-1 with an asymmetric arc and a smaller hole 300-2 with a circular border on one side and a rectangular border on the other side. 8F illustrates yet another preferred embodiment in which holes 300 have asymmetrically tapered boundaries (e.g., a left portion of hole 300 has a more elongated tapered curved boundary and a right portion of hole 300 has a relatively shorter tapered curved boundary). Each hole 300 may have one or more curved edges (e.g., convex or concave boundaries) and / or one or more straight edges.

[0041] The required minimum border width at the edge of the hole 300 can determine how close a display pixel may be formed from the edge of the hole, and therefore can constrain the size of the active area if the border width is too large. FIG. 9A is a plan view showing a minimum hole border envelope 1100 associated with data lines routed around the hole 300. As shown in FIG. 9A, multiple data lines D extending in the Y direction toward the hole 300 may need to be routed around the hole 300 assuming that they cannot be routed directly through the hole 300 as shown in FIG. 4B (e.g., a data line extending from the top of the hole 300 may have a first intermediate segment extending west along the top edge of the hole 300, a second intermediate segment extending south along the left edge of the hole 300, and a third intermediate segment extending east along the bottom edge of the hole 300). Each successive data line may be routed further away from the edge of the hole 300, pushing out the closest point where a display pixel may be formed along the vertical segment of each data line. Thus, the minimum hole boundary envelope 1100 may define where the nearest display pixel may be formed along the data lines relative to the edge of the hole 300 (i.e., display pixels may not be formed within the envelope 1100, but should only be formed outside of the envelope 1100). A similar envelope may also exist for the right half of the hole 300, assuming that the data lines are also routed around the right edge of the hole 300.

[0042] FIG. 9B shows both a minimum boundary envelope 1100 for the left half of the hole 300 and a minimum boundary envelope 1100' for the right half of the hole 300. Both envelopes 1100 and 1100' may be associated with a routing pattern of data lines routed substantially in the Y direction. As shown in FIGS. 2, 3, and 5-8, control lines such as gate lines, scan lines, emission lines, or other row control lines may also be routed substantially in the X direction, and row control lines that overlap the hole 300 may need to be routed around the hole 300. Similar to the data lines shown in FIG. 9A, these row control lines that need to avoid the hole 300 may also have an associated minimum hole boundary envelope 1102 that determines where the nearest display pixel may be formed along the row control line relative to the edge of the hole 300 (i.e., display pixels may not even be formed within the envelope 1102, but should only be formed outside of the envelope 1102).

[0043] In the example of FIG. 9B, the envelope associated with the column-extended data lines (i.e., envelopes 1100 and 1100') may have a larger overall footprint than the envelope associated with the row-extended gate lines (i.e., envelope 1102). Thus, the edge of the active area (AA) depicted by the dotted line 1104 may be limited by the size of the envelopes 1100 and 1100'. This is not necessarily the case. In other configurations, the envelope associated with the row-extended gate lines may have a larger overall footprint than the envelope associated with the column-extended data lines (e.g., the footprint of envelope 1102 is larger than envelopes 1100, 1100'). In such a scenario, the active area may be limited by the size of the envelopes 1100 and 1100'. The techniques described above in connection with Figures 3 and 5-8 for reducing routing congestion at the boundaries of holes 300 can be used to help minimize the size of envelope 1102 so that the active area size is no longer limited by the row line routing pattern, thereby increasing the size of the active area.

[0044] FIG. 10A illustrates how the size of the minimum hole boundary envelope can be reduced by reshaping the hole, according to one embodiment. As shown in FIG. 10A, a hole such as hole 300′ (e.g., a through-hole, optical window, or other inactive display area) can have edges that taper inwardly at an angle α relative to the X-axis. This angle α at which the hole edges are narrowed can be equal to the angle α at which the envelope 1100 extends outwardly from the rectangular hole 300 (see, e.g., FIG. 9B). Tapering hole 300′ in this manner can offset increased congestion of routing lines introduced by successive data lines being routed around hole 300′ (e.g., the narrowed hole shape effectively creates space for data lines to be routed in an area that would otherwise be occupied by the rectangular hole). So configured, the resulting minimum hole boundary envelope 1101 has an overall footprint substantially smaller than the footprint of envelope 1100 / 1100' of FIG. 9B, thereby further increasing the size of the display active area.

[0045] The example of FIG. 10A in which hole 300′ has a symmetrical taper is merely illustrative and is not intended to limit the scope of the present embodiment. FIG. 10B illustrates another suitable configuration in which a hole (e.g., a through-hole, optical window, or other inactive display area) such as hole 300″ has an asymmetrical taper. As shown in FIG. 10B, hole 300″ may have a left portion tapered at an angle α relative to the X-axis and a right portion tapered at an angle θ relative to the X-axis. Such an offset hole shape may be used, for example, to accommodate two or more electrical components from below the display (e.g., a first, larger sensor 18-1 may be formed in the wider opening portion of hole 300″, while a second, smaller sensor 18-2 may be formed in the narrower opening portion of hole 300″). Thus, the asymmetric hole of FIG. 10B may allow signals to pass through multiple sub-display components while simultaneously minimizing the minimum hole boundary envelope associated with vertical routing lines extending in the Y direction, resulting in an overall reduced boundary width around the hole 300'' and a larger overall active area of ​​the display. In general, the holes or inactive areas within the active area of ​​the display may have any suitable size or shape to accommodate any suitable number of sensor components (e.g., the shape of the holes or inactive areas may be optimized to reduce the hole boundary width and thus maximize the display active area coverage).

[0046] If desired, the techniques described in connection with FIGS. 2-10 regarding reducing routing congestion of display control lines routed around holes or inactive areas can also be extended to touch sensor circuitry (see, e.g., FIG. 11). FIG. 11 is a top (layout) view illustrating how multiple rows of touch sensing circuitry 1300 formed on the left edge of an electronic device and 1300′ formed on the right edge of the electronic device may be coupled to corresponding sensing lines that are shorted together before being routed around holes 300 (e.g., through holes, optical windows, or other non-display inactive areas) in the active area. As shown in FIG. 11, multiple touch control lines 1302 may be merged at node 1304 before being routed around the boundary of hole 300. The merged routing line segment, which is a single intermediate routing wire connection connecting node 1304 to node 1306, may be split into multiple parallel lines at fan-out node 1306 to the active area to the right of hole 300. If desired, the methods and circuitry described herein may be extended to any type of signal or power line to be routed around or across a hole with the objective of minimizing routing congestion near the hole.

[0047] FIG. 12A is a top (layout) view showing row and column lines routed to a hole boundary region outside the active area. As shown in FIG. 12A, row lines (e.g., gate lines G, scan lines, emission lines, initialization lines, reset lines, reference lines, and / or other row extension control lines) and column lines (e.g., data lines D, positive power lines, ground power lines, and / or other column extension control lines) near the hole 300 may both be routed to a hole boundary region surrounding the hole 300. The hole boundary region may be defined on one side by the edge of the hole 300 and on the other side by the edge of the active area (as defined by dotted line 1202). Thus defined, the hole boundary region and the active area are non-overlapping regions. Thus, the hole boundary region surrounding the hole 300 may exhibit a hole boundary width 1204. As discussed above in connection with FIG. 9B, techniques for reducing routing congestion at the boundaries of holes 300 can be used to help minimize the hole border area (i.e., to reduce the hole border width), thereby increasing the size of the active area.

[0048] To further maximize the size of the active area, FIG. 12B shows another preferred configuration in which only the row lines are routed within the hole bounding region, and the column lines are routed outside the hole bounding region and inside the active area (see, for example, data line D, which is routed within the active area edge 1212 and does not extend into the hole bounding region). By routing only the row control lines within the hole bounding region, the hole bounding width 1214 can be further reduced. If desired, row lines routed around the hole 300 may be merged, which may also help to further reduce the hole bounding width. To allow for the formation of column lines within the active area, the column lines may be formed in a top metal routing layer above the pixel transistors or in a buried metal layer below the pixel transistors (see the discussion below in connection with FIGS. 13-16). When formed in this manner within the active area, the column lines may be routed directly above or below one or more pixels 22 within the active area. Meanwhile, the portion of the column lines extending within the hole bounding region does not overlap any pixels, since no pixels are formed within the holder bounding region.

[0049] FIG. 12C illustrates yet another preferred arrangement in which only the column lines are routed inside the hole bounding region, and the row control lines are routed outside the hole bounding region and inside the active area (see, for example, gate line G, which is routed inside the active area edge 1222 and does not extend into the hole bounding region). Routing only the column lines within the hole bounding region can further reduce the hole bounding width 1224, thus maximizing the size of the active area. To allow for the formation of row control lines within the active area, the row lines may be formed in a top metal routing layer above the pixel transistors or in a buried metal layer below the pixel transistors (see discussion below in connection with FIGS. 13-16). When formed within the active area in this manner, the row lines may be routed directly above or below one or more pixels 22 within the active area.

[0050] FIG. 13 is a cross-sectional side view of an exemplary display stackup, according to one embodiment. As shown in FIG. 13, the display stack may include a backing film 1300 and a substrate layer, such as a substrate 1302, formed on the backing film 1300. The substrate 1302 may be formed from glass, metal, plastic, ceramic, sapphire, or other suitable substrate material. In some configurations, the substrate 1302 may be an organic substrate formed from (by way of example) polyimide (PI), polyethylene terephthalate (PET), or polyethylene naphthalate (PEN). The surface of the substrate 1302 may optionally be covered with one or more buffer layers (e.g., inorganic buffer layers such as layers of silicon oxide, silicon nitride, etc.).

[0051] A thin film transistor (TFT) layer 1304 may be formed above the substrate 1302. The TFT layer 1304 may include thin film transistor circuitry such as thin film transistors, thin film capacitors, associated routing circuitry, and other thin film structures formed within a plurality of alternating metal routing and dielectric layers. An organic light emitting diode (OLED) layer 1306 may be formed above the TFT layer 1304. The OLED layer 1306 may include a cathode layer, an anode layer, and a light emitting material interposed between the cathode layer and the anode layer.

[0052] The circuitry formed in the TFT layer 1304 and the OLED layer 1306 may be protected by an encapsulation layer 1308. As an example, the encapsulation layer 1308 may include a first inorganic encapsulation layer, an organic encapsulation layer formed on the first inorganic encapsulation layer, and a second inorganic encapsulation layer formed on the organic encapsulation layer. The encapsulation layer 1308 thus formed may help prevent moisture and other potential contaminants from damaging the conductive circuitry covered by the layer 1308.

[0053] One or more polarizer films 1312 may be formed above the encapsulation layer 1308 using an adhesive layer 1310. The adhesive 1310 may be implemented using an optically clear adhesive (OCA) material that provides high light transmission. One or more touch layers 1316 that implement the touch sensor functionality of the touch screen display 14 may be formed above the polarizer film 1312 using an adhesive 1314 (e.g., an OCA material). For example, the touch layer 1316 may include horizontal and vertical touch sensor electrodes that collectively form an array of capacitive touch sensor electrodes. Finally, the display stack may be topped off with a cover glass (CG) layer 1320 formed above the touch layer 1316 using additional adhesive 1318 (e.g., an OCA material). The cover glass 1320 may act as an outer protective layer for the display 14.

[0054] Figure 14 is a cross-sectional side view of an exemplary TFT layer 1304 of a display pixel 22, according to one embodiment. As shown in Figure 14, the TFT layer 1304 may include a buried conductive layer, such as a buried metal layer 1400, formed on a substrate 1302. The buried metal layer 1400 and the substrate 302 may optionally be covered with one or more buffer layers 1401 (e.g., inorganic buffer layers such as layers of silicon oxide, silicon nitride, etc.).

[0055] A polysilicon layer (e.g., a low temperature polysilicon or "LTPS" layer) may be formed on the inorganic buffer layer 1401 and patterned and etched to form an LTPS region 1452. Two opposing ends of the LTPS region 1452 may optionally be doped (e.g., n-doped or p-doped) to form source-drain regions of a silicon transistor (e.g., an LTPS transistor) within a display pixel. In general, a display pixel may include any suitable number of silicon transistors (if any).

[0056] A gate insulator layer 1404 may be formed on the buffer layer 1401 and the silicon region 1452. A first metal layer (e.g., a first gate metal layer "GE1") may be formed above the gate insulator layer 1404. The GE1 metal layer may be patterned and etched to form gate conductors of the silicon transistors. If desired, the first metal layer may also be patterned and etched to form terminals of one or more capacitors within the display pixels.

[0057] A first inter-layer dielectric (ILD1) layer 1406 may be formed above the first gate metal layer GE1 and the silicon transistor. The dielectric layer 1406 may be formed from silicon nitride, silicon oxide, and other suitable insulating materials. A second metal layer (e.g., a second gate metal layer "GE2") may be formed on the ILD1 layer 1406. The second metal layer may optionally be patterned and etched to form another terminal of one or more capacitors in the display pixel.

[0058] A second interlayer dielectric (ILD2) layer 1408 may be formed above the second gate metal layer GE2. The dielectric layer 1408 may be formed of silicon nitride, silicon oxide, and other suitable insulating materials. One or more buffer layers, such as buffer layer 1410 (e.g., inorganic buffer layers, such as silicon oxide layers, silicon nitride layers, etc.), may be formed above the dielectric layer 1408.

[0059] A semiconductor oxide layer (e.g., an indium gallium zinc oxide or "IGZO" layer) may be formed above the buffer layer 1410, which is sometimes referred to as an oxide buffer layer. The semiconductor oxide layer may be patterned and etched to form a semiconductor oxide region 1462. Two opposing ends of the semiconductor oxide region 1462 may optionally be doped (e.g., n-doped or p-doped) to form source-drain regions of a semiconductor oxide transistor within the display pixel. In general, the display pixel 22 may include any suitable number of semiconductor oxide transistors (if any).

[0060] An insulator layer, such as gate insulator layer 1411, may be formed on IGZO region 1462. An oxide (third) gate metal layer "OGE" may be formed on gate insulator layer 1411 to function as a gate conductor for the semiconductor oxide transistor. Another interlayer dielectric (OILD) layer 1412 may be formed on buffer layer 1410 and on the semiconductor oxide transistor. Pixel 22 need not include a semiconductor oxide transistor. In configurations where pixel 22 does not include any semiconductor oxide transistor, one or more of layers, such as oxide buffer layer 1410, semiconductor oxide region 1462, gate liner 1411, OGE layer, and / or oxide ILD layer 2512, may not be formed during fabrication of pixel 22. Layer GE2 and dielectric layer 1408 are also optional if not required to form a capacitor structure.

[0061] A first interconnect layer above the silicon transistors and above the semiconductor oxide transistors may be formed on the dielectric layer 1412. The conductive routing structures formed in the first interconnect layer may be coupled to the source-drain regions of each underlying transistor in pixel 22, and therefore may be referred to as a first source-drain metal layer "SD1."

[0062] A first planarization (PLN1) layer, such as layer 1414, may be formed above the SD1 metal routing layer. A second interconnect layer may be further formed on the first planarization layer 1414. The conductive routing structures formed in the second interconnect layer may be coupled to the SD1 conductors and thus may be referred to as the second source-drain metal layer, "SD2."

[0063] A second planarization (PLN2) layer, such as layer 1416, may be formed over planarization layer 1414 and over the SD2 routing metal lines. Planarization layers 1414 and 1416 may be formed from an organic dielectric material, such as a polymer. In contrast, layers below the organic planarization layers, such as layers 1404, 1406, 1408, 1410, and 1412, are typically formed from inorganic dielectric materials, such as silicon nitride, silicon oxide, etc.

[0064] An anode 1418 (e.g., an anode terminal of an organic light emitting diode in pixel 22) may be formed above the second planarization layer 1416. Additional structures may be formed above the anode 1418. For example, a pixel defining layer, a light emitting diode light emitting material, a cathode, and other pixel structures may also be included in the stackup of display pixel 22. However, these additional structures have been omitted for simplicity.

[0065] As discussed above in connection with FIGS. 12B and 12C, the row and column lines may be optionally routed within the active area using a “top” conductive layer (i.e., a metal layer formed above the silicon and semiconductor oxide transistors). As an example, the data lines D routed inside the active area as shown in FIG. 12B may be formed using the anode layer 1418. As another example, the row / column lines routed inside the active area may be formed using the SD1 or SD2 metal layer. As yet another example, the row / column lines routed inside the active area may be formed using one or more touch sensor layers 1316 (see FIG. 13). These top metal layers may be formed using aluminum, copper, silver, gold, or other suitable materials having high electrical conductivity.

[0066] As discussed above in connection with Figures 12B and 12C, the row and column lines may be optionally routed within the active area using a "buried" conductive layer (i.e., one or more metal layers formed under the pixel silicon transistors). As an example, the gate lines G routed inside the active area as shown in Figure 12C may be formed using a buried metal layer 1400 formed directly on the substrate 1302 as shown in Figure 14. As another example, the row / column lines routed within the active area may be formed using a buried metal layer sandwiched between two inorganic buffer layers (see, for example, Figure 15 where the buried metal layer 1400 is formed between buffer layers 1401-1 and 1401-2). As yet another example, the row / column lines routed within the active area may be formed using a buried metal layer buried or embedded within the substrate (see, for example, Figure 16 where the buried metal layer 1400 is formed on the inorganic buffer layer 1401 and embedded between the first substrate layer 1302-1 and the second substrate layer 1302-2).

[0067] According to one embodiment, there is provided a display circuitry including a first row of display pixels formed in an active area, a second row of display pixels formed in the active area, a non-active region within the active area, and a display driver circuit configured to output control signals to a first row control line coupled to the first row of display pixels and to output control signals to a second row control line coupled to the second row of display pixels, the first and second row control lines being merged into a segment routed by the non-active region.

[0068] According to another embodiment, the inactive area comprises a hole.

[0069] According to another embodiment, the non-active area includes a through hole.

[0070] According to another embodiment, the inactive area includes an optical window.

[0071] According to another embodiment, the merged segments are routed around the boundary of the hole.

[0072] According to another embodiment, the merged segment is routed directly across the hole.

[0073] According to another embodiment, the display driver circuit is further configured to output control signals onto the first and second row control lines simultaneously.

[0074] According to another embodiment, the display circuitry includes dummy circuitry coupled to the merged segment and configured to increase a parasitic load on the first and second row control lines.

[0075] According to another embodiment, the merged segment is coupled between a first node and a second node, the first node being connected to the first and second row control lines, and the merged segment being split into at least first and second additional row control lines at the second node.

[0076] According to another embodiment, the display circuitry includes an additional display driver circuit configured to output an additional control signal to a third row control line coupled to the first row of display pixels and an additional control signal to a fourth control line coupled to the second row of display pixels, the third and fourth row control lines being merged into an additional segment routed by the inactive area.

[0077] According to another embodiment, the inactive area is physically interposed between the display driver circuitry and the further display driver circuitry.

[0078] According to another embodiment, the display circuitry includes a third row of display pixels formed in the active area, and the display driver circuitry is further configured to output a control signal onto a third row control line coupled to the third row of display pixels, the merged segment also being connected to the third row control line.

[0079] According to another embodiment, the inactive area has a tapered shape optimized to increase the size of the active area surrounding the inactive area.

[0080] According to another embodiment, the inactive area is asymmetric.

[0081] According to one embodiment, there is provided a display including display pixels formed in an active area, a non-active area at least partially surrounded by the active area, a first routing segment coupled to a first group of display pixels formed in a first portion of the active area on a first side of the non-active area, and a second routing segment coupled to a second group of display pixels formed in the first portion of the active area on the first side of the non-active area, the first and second routing segments being connected at a node via a shorting segment and including a merged segment routed by the non-active area.

[0082] According to another embodiment, the display includes a third routing segment coupled to a third group of display pixels formed in a second portion of the active area on a side of the inactive area, and a fourth routing segment coupled to a fourth group of display pixels formed in a second portion of the active area on the second side of the inactive area, the third and fourth routing segments connected to a merged segment at a fan-out node.

[0083] According to another embodiment, the first routing segment and the third routing segment are coupled to the same row of display pixels.

[0084] According to another embodiment, the first routing segment is parallel to the second routing segment.

[0085] According to another embodiment, the first group of display pixels and the second group of display pixels correspond to adjacent rows of display pixels in the active area.

[0086] According to another embodiment, the first group of display pixels and the second group of display pixels correspond to non-adjacent rows of display pixels in the active area.

[0087] According to another embodiment, the non-active region has a tapered shape optimized to increase the active area.

[0088] According to one embodiment, there is provided a display including an array of pixels formed in an active area, a non-active area at least partially surrounded by the active area, the non-active area having a border area that does not overlap with the active area, first routing lines extending across the display in a first direction and extending into the border area of ​​the non-active area, and second routing lines extending across the display in a second direction and not extending into the border area of ​​the non-active area.

[0089] According to another embodiment, the second direction is perpendicular to the first direction.

[0090] According to another embodiment, the first routing lines include gate lines and the second routing lines include data lines.

[0091] According to another embodiment, the first routing lines include data lines and the second routing lines include gate lines.

[0092] According to another embodiment, the second routing line is formed using the anode layer.

[0093] According to another embodiment, the second routing line is formed using a source-drain metal routing layer.

[0094] According to another embodiment, the second routing line is formed using the touch sensor layer.

[0095] According to another embodiment, the second routing line is formed using a buried metal layer formed above the substrate layer and below the low temperature polysilicon layer.

[0096] The above is merely illustrative and various modifications may be made to the described embodiments. The above embodiments may be implemented individually or in any combination.

Claims

1. a first row of display pixels formed in the active area; a second row of display pixels formed within the active area; an inactive region within the active area; a display driver circuit configured to output control signals on first row control lines coupled to the first row of display pixels and to output the control signals on second row control lines coupled to the second row of display pixels; an additional display driver circuit configured to output an additional control signal on a third row control line coupled to the first row of display pixels and to output the additional control signal on a fourth row control line coupled to the second row of display pixels; the first and second row control lines are merged across a first side of the inactive area into a segment routed in the inactive area; the third and fourth row control lines cross a second side of the inactive area opposite the first side and merge into an additional segment routed in the inactive area.

2. The display circuitry of claim 1 wherein the inactive areas comprise holes.

3. The display circuitry of claim 2 wherein the non-active areas include through holes.

4. The display circuitry of claim 2 wherein the inactive area comprises an optical window.

5. The display circuitry of claim 2 wherein the merged segment is routed around a boundary of the hole.

6. 3. The display circuitry of claim 2 wherein said inactive area has an optical window and said merged segments are routed directly across said optical window.

7. 2. The display circuitry of claim 1, wherein said display driver circuit is further configured to output said control signals to said first and second row control lines simultaneously.

8. and a dummy circuit coupled to the merged segment and configured to increase a parasitic load on the first and second row control lines.

2. The display circuitry of claim 1.

9. 2. The display circuitry of claim 1, wherein the merged segment is coupled between a first node and a second node, the first node being connected to the first and second row control lines, and the merged segment is split into at least first and second additional row control lines at the second node.

10. 2. The display circuitry of claim 1 , wherein the active area has a first side at a first edge of a substrate and a second side at a second edge of the substrate opposite the first side, the display driver circuitry being disposed at the first edge of the substrate and the additional display driver circuitry being disposed at the second edge of the substrate.

11. 11. The display circuitry of claim 10, wherein the inactive area is physically interposed between the display driver circuitry and the further display driver circuitry.

12. a third row of display pixels formed within the active area, the display driver circuitry further configured to output the control signal to an additional row control line coupled to the third row of display pixels, the merged segment also being connected to the additional row control line.

2. The display circuitry of claim 1.

13. 2. The display circuitry of claim 1 wherein the inactive area has a tapered shape.

14. 2. The display circuitry of claim 1 wherein said inactive areas are asymmetric.

15. A display, Display pixels formed in an active area; a non-active area at least partially surrounded by the active area; an additional inactive area smaller than the inactive area, the additional inactive area being separated from the inactive area and the additional inactive area being at least partially surrounded by the active area; and a first routing segment coupled to a first group of the display pixels formed in a first portion of the active area on a first side of the inactive region; a second routing segment coupled to a second group of the display pixels formed in the first portion of the active area on the first side of the non-active region, the first and second routing segments being connected at a node via a shorting segment; and a merged segment for the first and second routing segments connected to the node and routed across the inactive area and the further inactive area.

16. a third routing segment coupled to a third group of the display pixels formed in a second portion of the active area on a second side of the non-active region; and a fourth routing segment coupled to a fourth group of the display pixels formed in the second portion of the active area on the second side of the non-active region; the third and fourth routing segments are connected to the merged segment at a fan-out node of the third and fourth routing segments, and the first routing segment and the third routing segment are coupled to a same row of the display pixels.

16. A display according to claim 15.

17. the first routing segment is parallel to the second routing segment; the first group of display pixels and the second group of display pixels correspond to adjacent or non-adjacent rows of the display pixels in the active area.

16. A display according to claim 15.

18. A display, an array of pixels formed in the active area; an inactive area at least partially surrounded by the active area, the inactive area having a border area, the border area not overlapping with the active area; a first routing line extending in a first direction across the display and extending into the border area of ​​the inactive area; a second routing line extending in a second direction across the display and having a portion routed outside the boundary area of ​​the inactive area; The second direction is perpendicular to the first direction, and the portions of the second routing lines overlap pixel transistors of one or more pixels in the array of pixels in the active area.

19. 20. The display of claim 18, wherein the second routing lines are formed using a layer selected from the group consisting of an anode layer, a source-drain metal routing layer, a touch sensor layer, and a buried metal layer formed above a substrate layer and below a low temperature polysilicon layer.

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