Display panel drive circuit and drive device

Abstract

This application discloses a driving circuit and driving device for a display panel, the driving circuit (1) of the display panel including a widening module (10), a control module (20), a bootstrap module (30) and an output module (40), the control module (20) being electrically connected to the widening module (10), the bootstrap module (30) and the output module (40), the bootstrap module (30) being electrically connected to the output module (40), the widening signal generated by the widening module (10) allowing the bootstrap module (30) to be charged for a sufficient time, ensuring that the output module (40) reaches or exceeds a predetermined potential when receiving the bootstrap signal, thereby avoiding unstable voltage when outputting gate drive signals and preventing the gate drive signals from prematurely ceasing output, thereby improving the stability of the output gate drive signals, and further improving the refresh rate and resolution of the display panel while also improving the display brightness and stability of the display effect of the display panel.

Description

[Technical field]

[0001] [CROSS REFERENCE TO RELATED APPLICATIONS] This application claims priority to a Chinese patent application filed with the China Patent Office on August 16, 2021, bearing application number 202110935013.8 and entitled "Driving circuit and driving device for display panel", the entire contents of which are incorporated herein by reference.

[0002] The present application relates to the field of display technology, and in particular to a driving circuit and a driving device for a display panel. [Background technology]

[0003] The descriptions herein only provide background information related to the present application and do not necessarily constitute prior art. With the development of display technology, display panels are widely applied in various fields such as entertainment, education, and security. GDL (Gate Driver Less) technology refers to directly manufacturing a gate driver IC on an array substrate to realize a driving method of scanning gates row by row. The GDL technology can simplify the manufacturing process of the display panel, omit the chip bonding process in the horizontal scanning line direction, reduce manufacturing costs, and at the same time improve the integration degree of the display panel and make the display panel thinner.

[0004] Currently, users have higher and higher requirements for the refresh rate and resolution of display panels, which requires the gate scanning frequency to be improved, and therefore the frequency at which the gate driver outputs the gate driving signal must also be improved. As a result, the charging time is reduced every time the gate driver outputs a gate driving signal, and the gate driving signal is prone to have unstable voltage during the output process, which affects the display effect. Summary of the Invention [Problem to be solved by the invention]

[0005] One of the objectives of the embodiments of the present application is to provide a driving circuit and a driving device for a display panel, and to solve the problem that the output of the gate driving signal in the conventional GDL technology is not stable, which affects the display effect. [Means for solving the problem]

[0006] The technical solutions adopted in the embodiments of the present application are as follows: In a first aspect, there is provided a drive circuit including a control module and a bootstrap module, the drive circuit further including a widening module and an output module, the control module being electrically connected to the widening module, the bootstrap module and the output module, respectively, and the bootstrap module being electrically connected to the output module; The widening module is used to receive a first level signal, generate a widening signal based on the first level signal when receiving a first transmission signal, and send the widening signal to a control module, the first transmission signal including at least two time-series different sub-transmission signals, and a time length of the widening signal is determined based on a time length of the first transmission signal; the control module is used to receive the first level signal, and when receiving the widening signal, generate a control signal based on the first level signal, and send the control signal to the output module and the bootstrap module; the bootstrap module is used to receive the control signal and transmit the bootstrap signal to the output module when the control signal is switched to a low level; The output module further receives a clock signal, and when receiving the bootstrap signal, is used to generate a gate driving signal and a second transmission signal based on the clock signal, and transmit the gate driving signal to a sub-pixel of the display panel and transmit the second transmission signal.

[0007] In a second aspect, there is provided a driving device including a clock signal generator 2a and a driving circuit according to the first aspect of the nth embodiment of the present application, The jth clock signal generator is connected to the output module of the j+2kath driver circuit, the first widening unit of the i+2ath driver circuit is connected to the second output unit of the ith driver circuit, the second output unit of the i+2ath driver circuit is connected to the second output unit of the ith driver circuit, and the second widening unit of the i+2ath driver circuit is connected to the second output unit of the i+ath driver circuit; the jth clock signal generator is used to generate a clock signal and send it to the output module of the j+2kath driving circuit, and the phase difference between the clock signal generated by the jth clock signal generator and the clock signal generated by the j+1th clock signal generator is π / 2a; a first widening unit of the (i+2a)th driving circuit is used to send a first sub-widening signal to the control module when receiving a first sub-transmission signal sent from the second output unit of the i-th driving circuit; the second widening unit of the (i+2a)th driving circuit is used to send a second sub-widening signal to the control module when receiving the second sub-transmission signal sent from the second output unit of the (i+a)th driving circuit; The second output unit of the (i+2a)th driver receives the first sub-transmission signal transmitted from the second output unit of the i)th driver, and is used to output the clock signal when the second output unit of the (i+2a)th driver receives a control signal and a clock signal; Here, a is an integer greater than or equal to 1, n is an integer greater than 2a, and i ∈ [1, n-2a], j = 1, 2, ..., 2a, k = 0, 1, 2, ..., [n / 2a], and j+2ka is less than or equal to n. Effect of the Invention

[0008] The driving circuit of the display panel provided in the embodiments of the present application ensures that the bootstrap module can be charged in a sufficient time by the widening signal generated by the widening module, and reaches or exceeds a predetermined potential when the output module receives the bootstrap signal, thereby avoiding the phenomenon of unstable voltage when outputting the gate driving signal and avoiding the phenomenon of the gate driving signal stopping outputting prematurely, thereby improving the stability of outputting the gate driving signal, and further improving the refresh rate and resolution of the display panel, while at the same time improving the display brightness and stability of the display effect of the display panel.

[0009] The display panel driving device provided in the embodiment of the present application is configured by installing driving circuits in a cascade connection and combining them with a clock signal generator. This driving device uses fewer input signals and has a simple structure. The driving device can perform stable cyclic operation and continuously output multiple time series of gate driving signals, and has the advantages of high resistance to external disturbances, low cost, and stable output. In order to more clearly describe the technical solutions in the embodiments of the present application, the following briefly introduces drawings necessary for describing the embodiments or exemplary technologies. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without any creative work. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a schematic structural diagram of a first type of driving circuit for a display panel provided in an embodiment of the present application. [Diagram 2] FIG. 2 is a timing diagram of a first level signal, a first transmission signal, a widening signal, a control signal, a potential of an input port of an output module, a clock signal, a gate driving signal and a second transmission signal provided in an embodiment of the present application. [Diagram 3] FIG. 3 is a schematic diagram of a second structure of a driving circuit of a display panel provided in an embodiment of the present application. [Figure 4]FIG. 4 is a timing diagram of the first level signal, the first sub-transmit signal, the first sub-widening signal, the second sub-transmit signal, the second sub-widening signal, the widening signal and the control signal provided in an embodiment of the present application. [Diagram 5] FIG. 5 is a schematic diagram of a third structure of a driving circuit of a display panel provided in an embodiment of the present application. [Figure 6] FIG. 6 is a schematic diagram of a fourth structure of a driving circuit of a display panel provided in an embodiment of the present application. [Figure 7] FIG. 7 is a schematic diagram of a fifth structure of a driving circuit of a display panel provided in an embodiment of the present application. [Figure 8] FIG. 8 is a timing diagram of the first sub-transmission signal, the second sub-transmission signal, the control signal, the bootstrap signal, the potential of the input port of the output module, the clock signal, the gate driving signal and the second transmission signal provided in an embodiment of the present application. [Figure 9] FIG. 9 is a schematic diagram of a sixth structure of a driving circuit of a display panel provided in an embodiment of the present application. [Figure 10] FIG. 10 is a schematic diagram of a seventh type of structure of a driving circuit for a display panel provided in an embodiment of the present application. [Figure 11] FIG. 11 is a schematic diagram of an eighth structural example of a driving circuit for a display panel according to an embodiment of the present application. [Figure 12] FIG. 12 is a timing diagram of the control signal, the bootstrap signal, the potential of the input port of the output module, and the third transmission signal sent to the reset module when the bootstrap signal is switched to a low level in the embodiment of the present application. [Figure 13] FIG. 13 is a schematic diagram of a ninth type of structure of a driving circuit for a display panel provided in an embodiment of the present application. [Figure 14] FIG. 14 is a schematic diagram of a first type of structure of a driving device for a display panel provided in an embodiment of the present application. [Figure 15] FIG. 15 is a timing chart from the first clock signal generated by the first clock signal generator to the seventh clock signal generated by the seventh clock signal generator when a=3 in an embodiment of the present application. [Figure 16] FIG. 16 is a timing chart of the first level signal, the first sub transmission signal, the first sub widening signal, the second sub transmission signal, the second sub widening signal, the second sub transmission signal, the second sub widening signal, the widening signal, the control signal, the bootstrap signal, the potential of the input port of the output module, the clock signal, the gate driving signal and the second transmission signal of the i+2ath driving circuit provided in an embodiment of the present application. [Figure 17] Figure 17 is a timing chart of the first level signal, the first sub transmission signal, the first sub widening signal, the second sub transmission signal, the second sub widening signal, the second sub transmission signal, the second sub widening signal, the widening signal, the control signal, the bootstrap signal, the potential of the input port of the output module, the clock signal, the gate driving signal and the second transmission signal when the first widening unit of the i+2ath driving circuit provided in an embodiment of the present application receives the first sub transmission signal transmitted from the second output unit of the i+1th driving circuit and the second widening unit of the i+2ath driving circuit receives the second sub transmission signal transmitted from the second output unit of the i+a-1th driving circuit. [Figure 18] FIG. 18 is a timing chart of the control signal, the bootstrap signal, the potential of the input port of the output module, and the third transmission signal of the i+2a-th driving circuit when the reset module of the i+2a-th driving circuit provided in an embodiment of the present application is connected to the second output unit of the i+3a+1-th driving circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be described in more detail below with reference to the drawings and embodiments. It is understood that the specific embodiments described herein are only for the purpose of illustrating the present application, and are not intended to limit the present application.

[0012] In addition, the orientations or positional relationships indicated by the terms "up", "down", "left", "right", etc. are based on the orientations or positional relationships shown in the drawings, and are merely for ease of description, and do not indicate or suggest that a specified device or element must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be understood as limiting the present application, and those skilled in the art can understand the specific meanings of the above terms according to the specific circumstances. The terms "first", "second" are used merely for ease of description, and should not be understood as indicating or implying relative importance or implicitly indicating the quantity of technical features, and "plurality" means two or more, unless otherwise clearly and specifically limited.

[0013] In order to explain the technical solutions provided by the present application, detailed descriptions are given below with reference to specific figures and embodiments.

[0014] In application, the gate driver needs to be charged before outputting the gate driving signal, and the gate driver outputs the gate driving signal after the charging is completed, and the longer the charging time of the gate driver, the higher the stability of the gate driving signal. As users have higher and higher requirements for the refresh rate and resolution of the display panel, if the frequency at which the gate driver outputs the gate driving signal is increased, the charging time of the conventional gate driver is shortened every time it outputs the gate driving signal, and the gate driving signal cannot reach the preset potential, so that the gate driving signal is likely to have a voltage drop phenomenon during the output process, and the stability of the output of the gate driving signal is reduced, resulting in an unstable display brightness of the display panel.

[0015] The embodiments of the present application provide a driving circuit for a display panel, which can be applied to a display panel, and can ensure that the bootstrap module can be charged in a sufficient time by the widening signal generated by the widening module, and reach a preset potential before the output module outputs a gate driving signal, thereby avoiding the unstable voltage when outputting the gate driving signal and avoiding the phenomenon that the gate driving signal stops outputting early, thereby improving the stability of outputting the gate driving signal, and further improving the refresh rate and resolution of the display panel, while at the same time improving the stability of the display brightness and display effect of the display panel.

[0016] In applications, the display panel may be a liquid crystal display panel based on TFT-LCD (Thin Film Transistor Liquid Crystal Display) technology, a liquid crystal display panel based on LCD (Liquid Crystal Display) technology, an organic light-emitting diode display panel based on OLED (Organic Light-Emitting Diode) technology, a quantum dot light-emitting diode display panel based on QLED (Quantum Dot Light Emitting Diodes) technology, or a curved display panel, etc.

[0017] Example 1 As shown in FIG. 1, the driving circuit 1 provided in the first embodiment of the present application includes a widening module 10, a control module 20, a bootstrap module 30 and an output module 40, the control module 20 is electrically connected to the widening module 10, the bootstrap module 30 and the output module 40 respectively, the bootstrap module 30 is electrically connected to the output module 40; The widening module 10 is used to receive a first level signal, generate a widening signal according to the first level signal when receiving a first transmission signal, and send the widening signal to the control module 20, the first transmission signal includes at least two sub-transmission signals of different time series, and the time length of the widening signal is determined according to the time length of the first transmission signal; The control module 20 is used to receive the first level signal, and when receiving the widening signal, generate a control signal according to the first level signal, and send the control signal to the output module 40 and the bootstrap module 30; The bootstrap module 30 is used to receive the control signal and send the bootstrap signal to the output module 40 when the control signal is switched to a low level; The output module 40 further receives a clock signal, and when receiving the bootstrap signal, generates a gate driving signal and a second transmission signal based on the clock signal, and is used to send the gate driving signal to the sub-pixel 210 of the display panel 2 and send the second transmission signal.

[0018] In application, the driving circuit may include multiple electronic components such as transistors, comparators, logic gates, resistors, capacitors or inductances, and the level signal and the clock signal are generated by a timing controller (Timer Control Register, TCON) or a system on chip (SOC) and input to the driving circuit, the level signal may be a high level signal or a low level signal, and the clock signal may be phase shifted by the TCON or SOC according to actual needs to obtain multiple clock signals with phase differences.

[0019] In application, the first transmission signal received by the widening module can be the second transmission signal output by the output module of another driving circuit of the display panel, the first level signal can be a DC high level signal, the widening module is turned on to output the first level signal when receiving the first transmission signal, and is turned off to stop outputting the first level signal when not receiving the first transmission signal, thereby generating a widening signal, and extending the time length of the first transmission signal, thereby extending the time length of the widening signal. Specifically, the first transmission signal can include at least two sub-transmission signals with different time series, and the time length of the widening signal is the same as the time length of the first transmission signal. The widening signal can be sent to the control module to control the on and off of the control module.

[0020] In application, the control module is turned on when receiving the widening signal to output a first level signal, and is turned off when not receiving the widening signal to stop outputting the first level signal, thereby generating and sending a control signal to the output module and the bootstrap module, and the time length of the control signal and the time length of the widening signal may be the same. Specifically, the widening unit can extend the time length of the widening signal, so that the control module extends the on time to realize the extension of the time length of the control signal.

[0021] In application, when the output module receives a high-level control signal, the potential of the input port of the output module is pulled up to a first high potential, but the first high potential is smaller than the predetermined potential, resulting in the gate driving signal output from the output module being unstable.

[0022] In application, the bootstrap module can send a bootstrap signal to the output module when the control signal switches from high level to low level, and the output module can pull up the potential of the input port of the output module to a second high potential when it receives the bootstrap signal, so that the input port of the output module can reach or exceed a predetermined potential. It should be noted that, due to the display characteristics of the display panel, only the gate drive signal sent according to the frequency of the refresh rate can be used to control the deflection of the sub-pixel, so the output module controls the deflection of the sub-pixel by outputting a stable gate drive signal to the sub-pixel according to the frequency of the refresh rate, which is easy to understand, the unstable gate drive signal and the stable gate drive signal have a certain time difference, so the unstable gate drive signal is not used to control the deflection of the sub-pixel, and when the unstable gate drive signal is output before the stable gate drive signal, the unstable gate drive signal is used to pre-charge the sub-pixel.

[0023] Wherein, the predetermined potential is determined according to the voltage magnitude and time length of the gate driving signal actually required by the display panel, and if the input port of the output module can reach the predetermined potential by charging, a complete and stable gate driving signal can be generated. In addition, when the output module receives the bootstrap signal, it can further generate and send a second transmission signal, wherein the clock signal can be switched from low level to high level at the same time when the control signal is switched from high level to low level, and the connection between the control module, the output module and the bootstrap module is the input port of the output module.

[0024] In one embodiment, a bootstrap module is used to receive a control signal and charge when the control signal is at a high level.

[0025] In application, the bootstrap module charges and accumulates charges when the control signal is at a high level, and releases the accumulated charges when the control signal switches from a high level to a low level, thereby generating a bootstrap signal.

[0026] In application, the output module can provide independent signals to different output targets, specifically, when the output target is a sub-pixel of a display panel, the output module can provide a stable gate driving signal, which can charge one or more rows of sub-pixels of the display panel to drive the display panel to display a screen, where a display panel can include at least one driving circuit, and the number of driving circuits is determined according to the number of clock signals used by the display panel, and when the output target is another driving circuit of the display panel, the output module can provide a second transmission signal, which provides a first transmission signal to the widening module of the other driving circuit. By providing independent signals to different output targets, interference between the signals output to different output targets can be avoided, and the stability of the operation of the display panel can be improved. The embodiment of the present invention is not limited by the type and number of output targets of the output module.

[0027] In application, the widening module ensures that the widening signal generated by the widening module can charge the bootstrap module in a sufficient time, and that the bootstrap module reaches or exceeds a predetermined potential when the output module receives the bootstrap signal, so that the output module can be fully turned on when transmitting the gate driving signal and the second transmission signal, and improve the signal transmission efficiency, and prevent the gate driving signal and the second transmission signal from being outputted due to the module being turned off early, thereby improving the stability of the output gate driving signal and the second transmission signal.

[0028] FIG. 2 exemplarily illustrates a timing chart of the first level signal, the first transmission signal, the widening signal, the control signal, the potential of the input port of the output module, the clock signal, the gate driving signal, and the second transmission signal.

[0029] Example 2 As shown in FIG. 3, based on the embodiment 1 corresponding to FIG. 1, the driving circuit 1 of the display panel provided by the embodiment 2 of the present application is as follows: the widening module 10 includes a first widening unit 110 and a second widening unit 120, and the first widening unit 110 and the second widening unit 120 are electrically connected to the control module 20 respectively; The first widening unit 110 is used to receive the first level signal, and when receiving the first sub-transmission signal, generate a first sub-widening signal according to the first level signal, and send the first sub-widening signal to the control module 20; The second widening unit 120 is used to receive the first level signal, and when receiving the second sub-transmission signal, generate a second sub-widening signal according to the first level signal, and send the second sub-widening signal to the control module 20; Here, the widened signal includes a first sub-widened signal and a second sub-widened signal.

[0030] In application, the widening module can include at least two widening units, and the operation principle of each widening unit is consistent with the operation principle of the widening module provided in the above embodiment, with the following distinction: each widening unit obtains a sub-transmission signal through an output module connected to a different driving circuit, and each widening unit can generate a sub-widening signal according to the sub-transmission signal, and it should be noted that the time length of each sub-widening signal can be the same as the time length of the corresponding sub-transmission signal, because the timing of each sub-transmission signal is different, and the widening signal sent by the widening module is composed of all the sub-widening signals, so the time length of the widening signal is determined according to the number and timing of the sub-transmission signals. By extending the time length of the widening signal, the time length of the control signal output from the control module can be extended.

[0031] Specifically, the widening module may include a first widening unit and a second widening unit, and the first widening unit and the second widening unit are respectively connected to output modules of different driving circuits, and in order to distinguish different transmission signals received by different widening units, the transmission signal received by the first widening unit is defined as a first sub-transmission signal, and the transmission signal received by the second widening unit is defined as a second sub-transmission signal.

[0032] FIG. 4 exemplarily shows a timing chart of the first level signal, the first sub-transmission signal, the first sub-widening signal, the second sub-transmission signal, the second sub-widening signal, the widening signal and the control signal. The operating principles of the first widening unit and the second widening unit will be described below with reference to FIG. 4.

[0033] The first widening unit and the second widening unit receive and hold a first level signal, the first widening unit is turned on at time t0 when the first sub transmission signal is received to output a first level signal, and turned off at time t1 when the first sub transmission signal is not received to stop outputting the first level signal, thereby generating a high-level first sub widening signal in a first period t01, the second widening unit is turned on at time t1 when the second sub transmission signal is received to output a first level signal, and turned off at time t2 when the second sub transmission signal is not received to stop outputting the first level signal, thereby generating a second sub widening signal in a second period t12, where the timing of the first sub transmission signal and the timing of the first sub widening signal may be the same, and similarly, the timing of the second sub transmission signal and the timing of the second sub widening signal may be the same, and the timing of the widening signal can be determined by controlling the timing of the first sub transmission signal and the second sub transmission signal, specifically, the first sub transmission signal and the second sub transmission signal may be high-level signals having the same voltage magnitude and a phase difference of 90 degrees, and the widening signal is composed of the first sub widening signal and the second sub widening signal.

[0034] Example 3 As shown in FIG. 5, based on the embodiment 2 corresponding to FIG. 3, the driving circuit 1 of the display panel provided by the embodiment 3 of the present application is as follows: the first widening unit 110 includes a first electronic switch 111, the second widening unit 120 includes a second electronic switch 121, the source of the first electronic switch 111 is connected to the source of the second electronic switch 121, and the drain of the first electronic switch 111 is electrically connected to the drain of the second electronic switch 121 and the control module 20 respectively; The source of the first electronic switch 111 is used to receive a first level signal, and when the gate of the first electronic switch 111 receives a first sub-transmission signal, the drain of the first electronic switch 111 is used to generate a first sub-widened signal according to the first level signal, and send the first sub-widened signal to the control module 20; The source of the second electronic switch 121 is used to receive a first level signal, and when the gate of the second electronic switch 121 receives a second sub-transmission signal, the drain of the second electronic switch 121 is used to generate a second sub-widened signal based on the first level signal, and transmit the second sub-widened signal to the control module 20.

[0035] In application, the first electronic switch and the second electronic switch may be any device or circuit having an electronic switch function, such as a transistor or a metal oxide semiconductor field effect transistor (MOSFET), specifically a thin film field effect transistor (TFT).

[0036] The operation principle of the first electronic switch and the second electronic switch will be described below with reference to the timing chart of FIG. 4 and the structural diagram of FIG.

[0037] The source of the first electronic switch and the source of the second electronic switch are used to receive a first level signal, the gate of the first electronic switch is turned on at time t0 when the first sub transmission signal is received, so that the drain of the first electronic switch outputs the first level signal, the gate of the first electronic switch is turned off at time t1 when the first sub transmission signal is not received, so that the drain of the first electronic switch stops outputting the first level signal, thereby generating a high level first sub widening signal in a first period t01, the gate of the second electronic switch is turned on at time t1 when the second sub transmission signal is received, so that the drain of the second electronic switch outputs the first level signal, and the gate of the second electronic switch is turned off at time t2 when the first sub transmission signal is not received, so that the drain of the second electronic switch stops outputting the first level signal, thereby generating a high level second sub widening signal in a second period t12.

[0038] In application, the first widening unit composed of the first electronic switch and the second widening unit composed of the second electronic switch have the advantages of simple structure, easy control, stable output and low cost, which can improve the stability of the driving circuit and reduce the manufacturing cost of the display panel.

[0039] Example 4 As shown in FIG. 6, based on the third embodiment corresponding to FIG. 5, the driving circuit 1 of the display panel provided by the fourth embodiment of the present application is as follows: the control module 20 includes a third electronic switch 201, the gate of the third electronic switch 201 is respectively connected to the drain of the first electronic switch 111 and the drain of the second electronic switch 121, and the drain of the third electronic switch 201 is respectively electrically connected to the bootstrap module 30 and the output module 40; The source of the third electronic switch 201 is used to receive a first level signal, and when the gate of the third electronic switch 201 receives a widening signal, the drain of the third electronic switch 201 is used to generate a control signal based on the first level signal, and send the control signal to the bootstrap module 30 and the output module 40.

[0040] In application, the type selection of the third electronic switch is consistent with the type selection of the first electronic switch and the second electronic switch, and is not described here.

[0041] The operation principle of the third electronic switch will be described below with reference to the timing chart of FIG.

[0042] The source of the third electronic switch is used to receive a first level signal, and the gate of the third electronic switch is turned on at time t0 when the widening signal is received, so that the drain of the third electronic switch outputs the first level signal, and the gate of the third electronic switch is turned off at time t2 when the first sub-transmission signal is not received, so that the drain of the third electronic switch stops outputting the first level signal, thereby continuously generating a high level control signal in the first period t01 and the second period t12.

[0043] In application, the control module composed of the third electronic switch has the advantages of simple structure, easy control, stable output and low cost, and when combined with the first widening unit and the second widening unit which have the same advantages, the stability of the driving circuit can be further improved and the manufacturing cost of the display panel can be reduced.

[0044] Example 5 As shown in FIG. 7, based on the fourth embodiment corresponding to FIG. 6, the driving circuit 1 of the display panel provided by the fifth embodiment of the present application is as follows: the output module 40 includes a first output unit 410 and a second output unit 420, the first output unit 410 is electrically connected to the third electronic switch 201 and the bootstrap module 30 respectively, the second output unit 420 is electrically connected to the third electronic switch 201 and the bootstrap module 30 respectively, and the input port of the first output unit 410 is connected to the input port of the second output unit 420 to form the input port 430 of the output module 40; The first output unit 410 is used to receive a clock signal, and when receiving a bootstrap signal, generate a gate driving signal according to the clock signal, and send the gate driving signal to the sub-pixel 210 of the display panel 2; The second output unit 420 is used to receive a clock signal, and when receiving a bootstrap signal, generate a second transmission signal according to the clock signal, and send the second transmission signal; The second output unit 420 further receives the first sub-transmission signal, and is used to be a bleeder of the clock signal when receiving the control signal and the clock signal.

[0045] In application, the output module may include multiple output units, the operating principle of each output unit being consistent with the operating principle of the output module provided in the above embodiment, the number of output units may be determined based on the number of output targets connected to the output module, and each output unit is used to provide an independent signal to one output target.

[0046] FIG. 8 illustrates an example of a timing chart of the first sub-transmission signal, the second sub-transmission signal, the control signal, the bootstrap signal, the potential of the input port of the output module, the clock signal, the gate driving signal and the second transmission signal. The operating principles of the first output unit and the second output unit will be described below with reference to FIG. 8.

[0047] The first output unit and the second output unit hold receiving the clock signal, the first output unit starts charging at time t0 when it receives the control signal and continues at time t2, thereby pulling up the potential of the input port of the first output unit to a first high potential, so that the first output unit outputs an unstable gate drive signal in the first period t01, and at time t2, when the first output unit does not receive the control signal (the control signal switches from high level to low level) and the first output unit receives the bootstrap signal, the potential of the input port of the first output unit is further pulled up to a second high potential, making the first output unit fully turn on and start outputting a stable gate drive signal, and at time t3 when the first output unit does not receive the bootstrap signal, it turns off and stops outputting the clock signal, so that it holds the output of a stable gate drive signal in the third period t23. The second output unit is consistent with the operation principle of the first output unit, and the description is omitted, and the differences are as follows: the second output unit does not output the second transmission signal by being a bleeder of the clock signal in the t01 period, and the second output unit can output a stable second transmission signal in the third period t23. Here, the potentials of the input port of the first output unit, the input port of the second output unit and the input port of the output module are equal, and the magnitude of the potential of the input port of the output module is determined according to the magnitude of the voltage of the control signal and the magnitude of the voltage of the bootstrap signal, and the magnitude of the voltage of the control signal and the magnitude of the voltage of the bootstrap signal can be set according to actual needs.

[0048] Example 6 As shown in FIG. 9, based on the fifth embodiment corresponding to FIG. 7, the sixth embodiment of the present application provides a driving circuit 1 for a display panel, in which a first output unit 410 includes a fourth electronic switch 411, a second output unit 420 includes a fifth electronic switch 421 and a sixth electronic switch 422, The gate of the fourth electronic switch 411 is connected to the drain of the third electronic switch 201, the drain of the fourth electronic switch 411 is connected to the sub-pixel 210 of the display panel 2, the gate of the fourth electronic switch 411, the drain of the fourth electronic switch 411 and the gate of the fifth electronic switch 421 are respectively electrically connected to the bootstrap module 30, and the gate of the fourth electronic switch 411 constitutes the input port 412 of the first output unit 410; The gate of the fifth electronic switch 421 is connected to the drain of the third electronic switch, the drain of the fifth electronic switch 421 is connected to the source of the sixth electronic switch 422, and the gate of the fifth electronic switch 421 constitutes the input port 423 of the second output unit; A source of the fourth electronic switch 411 is used to receive a clock signal, and when a gate of the fourth electronic switch 411 receives a bootstrap signal, a drain of the fourth electronic switch 411 is used to generate a gate driving signal according to the clock signal, and send the gate driving signal to the display panel 2; A source of the fifth electronic switch 421 is used to receive a clock signal, and when a gate of the fifth electronic switch 421 receives a bootstrap signal, a drain of the fifth electronic switch 421 is used to generate a second transmission signal based on the clock signal and transmit the second transmission signal; The gate of the sixth electronic switch 422 is used to receive the first sub-transmission signal, the gate of the fifth electronic switch 421 receives a control signal, and the source of the fifth electronic switch 421 receives a clock signal, and the drain of the sixth electronic switch 422 is used to be a bleeder of the clock signal based on the first sub-transmission signal.

[0049] In application, the type selection of the fourth electronic switch and the fifth electronic switch is consistent with the type selection of the first electronic switch and the second electronic switch described above, and thus the description is omitted here.

[0050] The operation principles of the fourth electronic switch, the fifth electronic switch, and the sixth electronic switch will be described below with reference to the timing chart of FIG.

[0051] The source of the fourth electronic switch and the source of the fifth electronic switch keep receiving the clock signal, the gate of the fourth electronic switch starts charging at time t0 when the control signal is received and can continue until time t2, thereby pulling up the gate of the fourth electronic switch to a first high potential, so that the drain of the fourth electronic switch outputs an unstable gate drive signal in the first period t01, at time t2, the gate of the fourth electronic switch does not receive a control signal (the control signal switches from high level to low level), and the gate of the fourth electronic switch receives a bootstrap signal, the potential of the gate of the fourth electronic switch is further pulled up to a second high potential, making the fourth electronic switch fully turn on and start to output a stable gate drive signal, the gate of the fourth electronic switch turns off at time t3 when the bootstrap signal is not received, and the drain of the fourth electronic switch stops outputting the clock signal, so that the drain of the fourth electronic switch keeps outputting a stable gate drive signal in the third period t23. The fifth electronic switch is consistent with the fourth electronic switch in the operating principle, and the description is omitted, and the differences are as follows: The gate of the sixth electronic switch receives the first sub-transmission signal in the first period t01, thereby turning on the sixth electronic switch and becoming a bleeder of the clock signal, so that the fifth electronic switch does not output the second transmission signal in the first period t01, and the drain of the fifth electronic switch can output a stable second transmission signal in the third period t23.

[0052] In application, the first output unit composed of the fourth electronic switch, the second output unit composed of the fifth electronic switch and the sixth electronic switch have the advantages of simple structure, easy control, stable output and low cost, and when combined with the first widening unit, the second widening unit and the control module which have the same advantages, the stability of the driving circuit can be further improved and the manufacturing cost of the display panel can be reduced.

[0053] Example 7 As shown in FIG. 10, based on the sixth embodiment corresponding to FIG. 9, the driving circuit 1 of the display panel provided by the seventh embodiment of the present application is as follows: the bootstrap module 30 includes a first capacitor 301, a first end of the first capacitor 301 is respectively connected to the drain of the third electronic switch 201, the gate of the fourth electronic switch 411 and the gate of the fifth electronic switch 421; and a second end of the first capacitor 301 is respectively connected to the drain of the fourth electronic switch 411 and the display panel; a first end of the first capacitor 301 is used to receive a control signal, and charge the first capacitor 301 when the control signal is at a high level; The first end of the first capacitor 301 is further used to pull up the gates of the fourth electronic switch 411 and the fifth electronic switch 421 to a second high potential by sending a bootstrap signal to the gates of the fourth electronic switch 411 and the fifth electronic switch 421 when the control signal is switched to a low level.

[0054] In application, the maximum amount of charge that can be stored in the first capacitor can be determined based on the capacitance value of the first capacitor, and the larger the capacitance value of the first capacitor, the larger the potential difference between the second high potential and the first high potential, where the capacitance value of the first capacitor can be set according to actual needs, and the second high potential is equal to or greater than the preset potential.

[0055] The operating principle of the first capacitor will be described below with reference to the timing chart of FIG.

[0056] The first end of the first capacitor starts charging at time t0 when the high-level control signal is received, accumulates charge in the first capacitor, and continues charging until time t2 when the control signal switches from high to low. At time t2, the first end of the first capacitor releases the charge accumulated in the first period t01 and the second period t12, i.e., pulls up the gates of the fourth electronic switch and the fifth electronic switch to the second high potential by sending a bootstrap signal to the gates of the fourth electronic switch and the fifth electronic switch.

[0057] In application, a capacitor is selected as the energy storage element of the bootstrap module to achieve rapid and stable cycle charging and discharging, which can ensure the charging efficiency and charging speed of the driving circuit, while improving the durability and reliability of the driving circuit.

[0058] Example 8 As shown in FIG. 11, based on the seventh embodiment corresponding to FIG. 10, the eighth embodiment of the present application provides a driving circuit 1 of a display panel, the driving circuit further includes a reset module 50, the reset module 50 is electrically connected to the control module 20, the bootstrap module 30 and the output module 40 respectively; The reset module 50 is used to receive the control signal, and transmit the control signal to the ground terminal when receiving the third transmission signal; The reset module 50 includes a seventh electronic switch 501, the source of which is respectively connected to the drain of the third electronic switch 201, the gate of the fourth electronic switch 411, the gate of the fifth electronic switch 421 and the first end of the first capacitor; The source of the seventh electronic switch 501 is used to receive a control signal, and the drain of the seventh electronic switch 501 is used to transmit the control signal to the ground terminal, when the gate of the seventh electronic switch 501 receives the third transmission signal.

[0059] In application, the third transmission signal can be sent to the reset module at any time after the output module sends the gate driving signal and the second transmission signal, the specific sending time is when the gate driving signal or the second transmission signal is switched to a low level, and may be one-sixth period of the clock signal after the gate driving signal or the second transmission signal is switched to a low level, and the reset module can send a control signal to the ground end when it receives the third transmission signal, thereby preventing the control module from continuing to output the control signal at times other than the first time period and the second time period, and resetting the potential of the input port of the output module to zero by deriving the control signal remaining in the driving circuit, thereby improving the stability of the control module outputting the control signal and the stability of the operation of the driving circuit.

[0060] In one embodiment, the reset module is further adapted to receive a bootstrap signal, and to transmit the bootstrap signal to ground when receiving the third transmission signal.

[0061] In application, the third transmission signal can be further sent to the reset module at any time after the bootstrap module sends the bootstrap signal, the specific sending time being when the bootstrap signal is switched to a low level, which may be one-sixth period of the clock signal after the bootstrap signal is switched to a low level; the reset module can send a control signal to the ground end when it receives the third transmission signal, thereby preventing the bootstrap module from continuing to output the bootstrap signal at times other than the third time period, and resetting the potential of the input port of the output module to zero by deriving the bootstrap signal remaining in the driving circuit, thereby improving the stability of the bootstrap module outputting the bootstrap signal and the operation stability of the driving circuit.

[0062] In application, the type selection of the seventh electronic switch is consistent with the type selection of the first electronic switch and the second electronic switch, and the description thereof is omitted here.

[0063] FIG. 12 is a timing chart illustrating an example of the control signal transmitted to the reset module when the bootstrap signal is switched to a low level, the bootstrap signal, the potential of the input port of the output module, and the third transmission signal.

[0064] The operation principle of the seventh electronic switch will be described below with reference to FIG.

[0065] The source of the seventh electronic switch holds receiving the control signal and the bootstrap signal, and the gate of the seventh electronic switch can turn on at time t3 when the third transmission signal is received and send the bootstrap signal to the ground end, and turn off at time t4 when the third transmission signal is not received and stop sending the bootstrap signal to the ground end, thereby sending the bootstrap signal to the ground end in a fourth period t34, and making the potential of the input port of the output module zero. Here, the time length of the third transmission signal can be set according to actual needs.

[0066] Example 9 As shown in FIG. 13, based on the eighth embodiment corresponding to FIG. 11, the driving circuit 1 of the display panel provided by the ninth embodiment of the present application is such that the driving circuit further includes a cutoff module 60, and the cutoff module 60 is electrically connected to the output module; The cut-off module 60 is used to receive the gate driving signal, and transmit the gate driving signal to the ground terminal when receiving the cut-off signal; The interruption module 60 includes an eighth electronic switch 601; The source of the eighth electronic switch 601 is connected to the drain of the fourth electronic switch 411 and the second end of the first capacitor 301 respectively; The source of the eighth electronic switch 601 is used to receive a gate driving signal, and when the gate of the eighth electronic switch 601 receives a blocking signal, the drain of the eighth electronic switch 601 is used to transmit the gate driving signal to the ground terminal.

[0067] In application, the type selection of the eighth electronic switch is consistent with the type selection of the first electronic switch and the second electronic switch, and the description thereof is omitted here.

[0068] In application, the cut-off signal may be an inverted signal of the control signal, and the cut-off signal may be obtained by inputting the control signal of the driving circuit into an inverter, and the type of the inverter may be a TTL (Transistor Logic) NOT gate, a CMOS (Complementary Metal Oxide Semiconductor) inverter. The cut-off signal is used to ground the second output unit during the period when the output module is not charging, to avoid sending extra or residual gate driving signals to the display panel, which can improve the stability of the output of the gate driving signal and further improve the display effect of the display panel.

[0069] The driving circuit of the display panel provided in the embodiment of the present application includes a widening module, a control module, a bootstrap module and an output module, the control module is electrically connected to the widening module, the bootstrap module and the output module respectively, the bootstrap module is electrically connected to the output module, the widening module can generate a widening signal to charge the bootstrap module for a sufficient time, and ensure that the output module reaches or exceeds a predetermined potential when receiving the bootstrap signal, thereby avoiding the voltage being unstable when outputting the gate driving signal and avoiding the phenomenon that the gate driving signal stops outputting early, thereby improving the stability of outputting the gate driving signal, and further improving the refresh rate and resolution of the display panel while improving the display brightness and stability of the display effect of the display panel.

[0070] Example 10 As shown in FIG. 14, the display panel driving device provided by the tenth embodiment of the present application includes a 2a clock signal generator and an n driving circuit provided by any one of the first to eighth embodiments; The jth clock signal generator is connected to the output module of the j+2kath driver circuit, the first widening unit of the i+2ath driver circuit 1001 is connected to the second output unit of the ith driver circuit 1002, the second output unit of the i+2ath driver circuit 1001 is connected to the second output unit of the ith driver circuit 1002, and the second widening unit of the i+2ath driver circuit 1001 is connected to the second output unit of the i+ath driver circuit 1003; The jth clock signal generator is used to generate a clock signal and send it to the output module of the j+2kath driving circuit, and the phase difference between the clock signal generated by the jth clock signal generator and the clock signal generated by the j+1th clock signal generator is π / 2a; the first widening unit of the (i+2a)th driver circuit 1001 is used to send the first sub-widening signal to the control module when receiving the first sub-transmission signal sent from the second output unit of the i-th driver circuit 1002; the second widening unit of the (i+2a)th driver circuit 1001 is used to send the second sub-widening signal to the control module when receiving the second sub-transmission signal sent from the second output unit of the (i+a)th driver circuit 1003; Here, a is an integer greater than or equal to 1, n is an integer greater than 2a, and i ∈ [1, n-2a], j = 1, 2, ..., 2a, k = 0, 1, 2, ..., [n / 2a], and j+2ka is less than or equal to n.

[0071] FIG. 14 exemplarily shows a structural schematic diagram when the i-th driving circuit receives a clock signal transmitted from the first clock signal generator, and shows the input / output relationship between the first sub-transmission signal, the second sub-transmission signal and the third transmission signal of the i+2a-th driving circuit 1001.

[0072] In application, the driving device includes nth cascaded driving circuits, a first output unit of each driving circuit is connected to a sub-pixel of the display panel, and the number of driving circuits is determined based on the number of sub-pixel rows of the display panel, for example, the number of driving circuits may be equal to the number of sub-pixel rows of the display panel, or may be equal to the number of sub-pixel rows of the display panel plus 2a.

[0073] In application, the gate driving signals can be sequentially sent to the sub-pixels of the first row to the sub-pixels of the nth row of the display panel according to the order of the first driving circuit to the nth driving circuit, and the time interval between the previously sent gate driving signal and the next sent gate driving signal is π / 2a. Here, the time interval between the gate driving signals is determined according to the number of clock signal generators, and the number of clock signal generators can be determined according to the actual performance of the display panel. When the TCON or SOC needs to output the gate driving signal by the driving device, it can trigger the driving device to start working by sending a high-level signal that is consistent with the widening signal waveform to the control module of any driving circuit.

[0074] The following describes the connection relationship between the drive circuits in the drive device using examples of a=3, n=7 and a=1, n=4.

[0075] When a=3 and n=7, the driving device includes six clock signal generators and seven driving circuits, the first clock signal generator to the sixth clock signal generator are respectively connected to the first output unit of the first driving circuit to the first output unit of the sixth driving circuit in a one-to-one correspondence, the first clock signal generator is further connected to the seventh driving circuit, the second output unit of the 1(i)th driving circuit is respectively connected to the second widening unit of the 4(i+a)th driving circuit, the first widening unit of the 7(i+2a)th driving circuit, and the second output unit of the 7(i+2a)th driving circuit and sends a second transmission signal, and the second output unit of the second driving circuit is respectively connected to the second widening unit of the fifth driving circuit, the first widening unit of the first driving circuit, the second output unit of the third driving circuit is respectively connected to the second widening unit of the sixth driving circuit, the first widening unit of the second driving circuit, and the second output unit of the second driving circuit and transmits the second transmission signal; the second output unit of the fourth driving circuit is respectively connected to the second widening unit of the seventh driving circuit, and the second output unit of the third driving circuit and transmits the second transmission signal; the second output unit of the fifth driving circuit is respectively connected to the second widening unit of the first driving circuit, the first widening unit of the fourth driving circuit, and the second output unit of the fourth driving circuit and transmits the second transmission signal; the second widening unit of the seventh driving circuit is connected to the second widening unit of the third driving circuit, the first widening unit of the sixth driving circuit, and the second output unit of the sixth driving circuit respectively and transmits a second transmission signal; and the second output unit of the seventh driving circuit is connected to the second widening unit of the third driving circuit, the first widening unit of the sixth driving circuit, and the second output unit of the sixth driving circuit respectively and transmits a second transmission signal.

[0076] When a=1, n=4, the driving device includes two clock signal generators and four driving circuits, the first clock signal generator is respectively connected to the first output unit of the first driving circuit and the first output unit of the third driving circuit, the second clock signal generator is respectively connected to the first output unit of the second driving circuit and the first output unit of the fourth driving circuit, the second output unit of the 1(i)th driving circuit is respectively connected to the second widening unit of the 2(i+a)th driving circuit, the first widening unit of the 3(i+2a)th driving circuit, and the second output unit of the 3(i+2a)th driving circuit and sends a second transmission signal, the second output unit of the second driving circuit is respectively connected to the second widening unit of the third driving circuit, the first widening unit of the fourth driving circuit, and the second output unit of the fourth driving circuit and sends a second transmission signal, and the second output unit of the third driving circuit is respectively connected to the second widening unit of the fourth driving circuit, the first widening unit of the first driving circuit, and the second output unit of the first driving circuit and sends a second transmission signal.

[0077] In application, the second transmission signal generated by each driving circuit has the same waveform as a stable gate driving signal, and the first sub-transmission signal and the second sub-transmission signal of each driving circuit can be obtained based on the second transmission signal sent by the remaining driving circuits of the driving device. Specifically, the second output unit of the i-th driving circuit is connected to the first widening unit and the second output unit of the i+2a-th driving circuit, and the second transmission signal is sent to the first widening unit and the second output unit of the i+2a-th driving circuit, which becomes the first sub-transmission signal of the first widening unit and the second output unit of the i+2a-th driving circuit; the second output unit of the i+a-th driving circuit is connected to the second widening unit of the i+2a-th driving circuit, and the second transmission signal is sent to the second widening unit of the i+2a-th driving circuit, which becomes the second sub-transmission signal of the second widening unit of the i+2a-th driving circuit.

[0078] In application, the phase difference between the clock signal generated by the jth clock signal generator and the clock signal generated by the j+1th clock signal generator is π / 2a, and the clock signal generated by the jth clock signal generator is sent to the output module of the j+2kath driver circuit, so the phase difference between the stable gate drive signal (second transmission signal) generated by the ith driver circuit and the stable gate drive signal (second transmission signal) generated by the i+1th driver circuit is also π / 2a, and the phase difference between the first sub-transmission signal received by the i+2ath driver circuit and the gate drive signal generated by the i+2ath driver circuit is π / 2, and the phase difference between the second sub-transmission signal received by the i+2ath driver circuit and the gate drive signal generated by the i+2ath driver circuit is π. The operation principle of charging the bootstrap module for a sufficient time by the widening signal generated based on the first sub-transmission signal and the second sub-transmission signal can refer to the operation principle provided by the above-mentioned embodiments 1 to 8, and the description will be omitted here.

[0079] FIG. 15 exemplarily illustrates a timing chart of the first clock signal generated by the first clock signal generator to the seventh clock signal generated by the seventh clock signal generator when a=3.

[0080] Figure 16 shows an example timing chart of the first level signal, first sub transfer signal, first sub widening signal, second sub transfer signal, second sub widening signal, second sub transfer signal, second sub widening signal, widening signal, control signal, bootstrap signal, potential of the input port of the output module, clock signal, gate drive signal and second transfer signal of the i+2ath drive circuit.

[0081] In one embodiment, the jth clock signal generator is connected to the output module of the j+2kath driver circuit, the first widening unit of the i+2ath driver circuit is connected to the second output unit of the i+1th driver circuit, and the second widening unit of the i+2th driver circuit is connected to the second output unit of the i+a-1th driver circuit; the first widening unit of the (i+2a)th driving circuit is used to send the first sub-widening signal to the control module when receiving the first sub-transmission signal sent from the second output unit of the (i+1)th driving circuit; The second widening unit of the (i+2a)th driving circuit is used to send the second sub-widening signal to the control module when it receives the second sub-transmission signal sent from the second output unit of the (i+a-1)th driving circuit.

[0082] Figure 17 exemplarily shows a timing chart of the first level signal, the first sub transmission signal, the first sub widening signal, the second sub transmission signal, the second sub widening signal, the second sub transmission signal, the second sub widening signal, the widening signal, the control signal, the bootstrap signal, the potential of the input port of the output module, the clock signal, the gate driving signal and the second transmission signal when the first widening unit of the i+2ath driving circuit receives the first sub transmission signal transmitted from the second output unit of the i+1th driving circuit and the second widening unit of the i+2ath driving circuit receives the second sub transmission signal transmitted from the second output unit of the i+a-1th driving circuit.

[0083] In application, due to hardware limitations of the first electronic switch transmitting the first sub-widening signal and the second electronic switch transmitting the second sub-widening signal, the transmission of the first sub-widening signal and the second sub-widening signal may have delays, and the widening signals formed thereby also have delays, so there is a risk that the control signal still holds the output after time t2, and the potential of the input port of the output module cannot be pulled up to the second high potential in a timely manner in the third period t23, which affects the stability and time length of the gate driving signal output in the third period t23.

[0084] In application, in order to avoid the control signal still maintaining an output after time t2, on the premise that the time length of the control signal can satisfy the requirement that the potential of the input port of the output module can reach the second high potential, the connection relationship between the first amplifying unit and the second amplifying unit of the i+2ath driving circuit can be adjusted, specifically, the first amplifying unit of the i+2ath driving circuit is connected to the second output unit of the i+1th driving circuit, and the second amplifying unit of the i+2th driving circuit is connected to the second output unit of the i+a-1th driving circuit, thereby shortening the time length of the amplifying signal and leaving a time of π / a in advance to avoid the amplifying signal still maintaining an output after time t2.

[0085] In application, the driving circuits are installed in a cascade connection and combined with a driving device configured with a clock signal generator, which has the advantages of using fewer input signals, having a simple structure, allowing the driving device to stably operate in a cyclic manner and continuously output gate driving signals with multiple timings, having high disturbance resistance, low cost, and stable output.

[0086] Example 11 As shown in FIG. 14, in the driving device provided in the embodiment 11 of the present application, the reset module of the (i+2a)th driving circuit 1001 is connected to the second output unit of the (i+3a+1)th driving circuit 1004; The reset module of the (i+2a)th driver circuit 1001 is used to send a control signal to the ground terminal when receiving the third transmission signal sent from the second output unit of the (i+3a+1)th driver circuit 1004.

[0087] In application, the reset module of the (i+2a)th driver circuit is connected to the second output unit of the (i+3a+1)th driver circuit, and can receive the second transmission signal transmitted from the second output unit of the (i+3a+1)th driver circuit as the third transmission signal of the reset module of the (i+2a)th driver circuit, and further multiplex the second transmission signals transmitted from the second output units of each driver circuit to improve the signal utilization rate and the integration of the driver device.

[0088] In addition, the reset module of the nath driving circuit to the reset module of the nth driving circuit do not have a corresponding output module for providing a third transmission signal, and the reset module of the nath driving circuit to the reset module of the nth driving circuit are connected to a TCON or SOC to obtain the third transmission signal.

[0089] In application, the reset module of the i+2ath driver circuit may be connected to the second output unit of the i+3ath driver circuit and the second output unit of any one of the driver circuits after the second output unit of the i+3ath driver circuit, and the connection relationship can be determined according to the reset speed. Specifically, the reset module of the 1+2ath driver circuit may be connected to the second output unit of the i+3ath driver circuit, and the phase difference between the third transmission signal and the control signal is π / 2, or may be connected to the second output unit of the i+3a+1th driver circuit, and the phase difference between the third transmission signal and the control signal is π / 2+π / a, or may be connected to the second output unit of the i+3a+2th driver circuit, and the phase difference between the third transmission signal and the control signal is π / 2+2π / a, and the embodiments of the present application do not limit the driver circuit specifically connected to the reset module of the i+2ath driver circuit.

[0090] FIG. 18 exemplarily shows a timing chart of the control signal, the bootstrap signal, the potential of the input port of the output module, and the third transmission signal of the (i+2a)th driving circuit when the reset module of the (i+2a)th driving circuit is connected to the second output unit of the (i+3a+1)th driving circuit.

[0091] The above are only preferred embodiments of the present application, and are not intended to limit the present application. Those skilled in the art can make various modifications and changes to the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should be included in the scope of the claims of the present application.

Claims

1. A driving circuit for a display panel including a control module and a bootstrap capacitor, The driving circuit further includes a control signal generating module and an output module, the control module is electrically connected to the control signal generating module, the bootstrap capacitor and the output module, respectively, and the bootstrap capacitor is electrically connected to the output module; The control signal generating module receives a first level signal, and when receiving a first transmission signal, generates a control signal generating signal based on the first level signal, and transmits the control signal generating signal to the control module, the first transmission signal includes at least two sub-transmission signals having different timings of becoming high level and low level, and the time length of the control signal generating signal is determined based on the time length of the first transmission signal; the control module is used to receive the first level signal, and when receiving the control signal generating signal, generate a control signal based on the first level signal, and send the control signal to the output module and the bootstrap capacitor; the bootstrap capacitor is used to receive the control signal and transmit the bootstrap signal to the output module when the control signal is switched to a low level; the output module is further used to receive a clock signal, and when receiving the bootstrap signal, generate a gate driving signal and a second transmission signal according to the clock signal, and transmit the gate driving signal to a sub-pixel of the display panel and transmit the second transmission signal; the output module includes a first output unit and a second output unit, the first output unit is electrically connected to a third electronic switch and the bootstrap capacitor respectively, the second output unit is electrically connected to a third electronic switch and the bootstrap capacitor respectively, and an input port of the first output unit is connected to an input port of the second output unit to form an input port of the output module; the first output unit is used to receive the clock signal, and when receiving the bootstrap signal, generate the gate driving signal according to the clock signal, and send the gate driving signal to a sub-pixel of the display panel; the second output unit is used to receive the clock signal, and when receiving the bootstrap signal, generate the second transmission signal based on the clock signal, and transmit the second transmission signal; the second output unit includes a fifth electronic switch and a sixth electronic switch; a gate of the fifth electronic switch is connected to a drain of the third electronic switch, a drain of the fifth electronic switch is connected to a source of the sixth electronic switch, and a gate of the fifth electronic switch constitutes an input port of the second output unit; The control signal generating signal is used to extend the charging time of the bootstrap capacitor by the control signal.

13. A display panel drive circuit comprising:

2. the control signal generating module includes a first control signal generating unit and a second control signal generating unit, the first control signal generating unit and the second control signal generating unit are respectively electrically connected to the control module, and the first transmission signal includes a first sub-transmission signal and a second sub-transmission signal; The first control signal generating unit receives the first level signal, and when receiving the first sub-transmission signal, generates a first sub-control signal generating signal according to the first level signal, and sends the first sub-control signal generating signal to the control module; The second control signal generating unit receives the first level signal, and when receiving the second sub-transmission signal, generates a second sub-control signal generating signal according to the first level signal, and sends the second sub-control signal generating signal to the control module; Here, the control signal generating signal includes the first sub-control signal generating signal and the second sub-control signal generating signal.

2. The drive circuit according to claim 1 .

3. The first control signal generating unit includes a first electronic switch, the second control signal generating unit includes a second electronic switch, a source of the first electronic switch is connected to a source of the second electronic switch, and a drain of the first electronic switch is electrically connected to a drain of the second electronic switch and the control module respectively.

3. The drive circuit according to claim 2.

4. a source of the first electronic switch is used to receive the first level signal, and a drain of the first electronic switch is used to generate the first sub control signal generating signal according to the first level signal when the gate of the first electronic switch receives the first sub transmission signal, and transmit the first sub control signal generating signal to the control module; A source of the second electronic switch is used to receive the first level signal, and a gate of the second electronic switch is used to receive the second sub-transmission signal, and a drain of the second electronic switch is used to generate the second sub-control signal generating signal according to the first level signal, and transmit the second sub-control signal generating signal to the control module.

4. The drive circuit according to claim 3.

5. the control module includes a third electronic switch, a gate of the third electronic switch is respectively connected to the drain of the first electronic switch and the drain of the second electronic switch, and a drain of the third electronic switch is respectively electrically connected to the bootstrap capacitor and the output module; A source of the third electronic switch is used to receive the first level signal, and when a gate of the third electronic switch receives the control signal generating signal, a drain of the third electronic switch is used to generate the control signal according to the first level signal, and send the control signal to the bootstrap capacitor and the output module.

2. The drive circuit according to claim 1 .

6. the first output unit includes a fourth electronic switch; a gate of the fourth electronic switch is connected to a drain of the third electronic switch, a drain of the fourth electronic switch is connected to a sub-pixel of the display panel, a gate of the fourth electronic switch, a drain of the fourth electronic switch and a gate of the fifth electronic switch are electrically connected to the bootstrap capacitor respectively, and a gate of the fourth electronic switch constitutes an input port of the first output unit; 2. The drive circuit according to claim 1 .

7. A source of the fourth electronic switch is used to receive the clock signal, and a drain of the fourth electronic switch is used to generate the gate driving signal according to the clock signal and transmit the gate driving signal to the display panel when a gate of the fourth electronic switch receives the bootstrap signal.

7. The drive circuit according to claim 6.

8. a source of the fifth electronic switch is used to receive the clock signal, and a drain of the fifth electronic switch is used to generate the second transmission signal according to the clock signal and transmit the second transmission signal when a gate of the fifth electronic switch receives the bootstrap signal; a gate of the sixth electronic switch is used to receive a first sub-transmission signal, and a gate of the fifth electronic switch receives the control signal; 7. The drive circuit according to claim 6.

9. The bootstrap capacitor includes a first capacitor, a first end of the first capacitor is respectively connected to the drain of the third electronic switch, the gate of the fourth electronic switch, and the gate of the fifth electronic switch, and a second end of the first capacitor is respectively connected to the drain of the fourth electronic switch and the display panel.

2. The drive circuit according to claim 1 .

10. a first end of the first capacitor is used to receive the control signal and charge the first capacitor when the control signal is at a high level; The first end of the first capacitor is further used for transmitting the bootstrap signal to the gate of the fourth electronic switch and the gate of the fifth electronic switch when the control signal is switched to a low level.

10. The drive circuit according to claim 9.

11. The drive circuit further includes a reset module, the reset module electrically connected to the control module, the bootstrap capacitor, and the output module, respectively; The reset module is used to receive the control signal and transmit the control signal to a ground terminal when a third transmission signal is received.

2. The drive circuit according to claim 1 .

12. the reset module includes a seventh electronic switch, the source of the seventh electronic switch is respectively connected to the drain of the third electronic switch, the gate of the fourth electronic switch, the gate of the fifth electronic switch and the first end of the first capacitor; The source of the seventh electronic switch is used to receive the control signal, and the gate of the seventh electronic switch is used to transmit the control signal to the ground terminal when the gate of the seventh electronic switch receives the third transmission signal.

12. The driving circuit according to claim 11.

13. A display panel driver including a 2a-th clock signal generator and an n-th driver circuit according to claim 1, The jth clock signal generator is connected to the output module of the j+2kath driving circuit, the first control signal generating unit of the i+2ath driving circuit is connected to the second output unit of the ith driving circuit, the second output unit of the i+2ath driving circuit is connected to the second output unit of the ith driving circuit, and the second control signal generating unit of the i+2ath driving circuit is connected to the second output unit of the i+ath driving circuit; the jth clock signal generator is used to generate a clock signal and send it to the output module of the j+2kath driving circuit, and the phase difference between the clock signal generated by the jth clock signal generator and the clock signal generated by the j+1th clock signal generator is π / 2a; the first control signal generating unit of the (i+2a)th driving circuit is used to send a first sub-control signal generating signal to the control module when receiving the first sub-transmission signal sent from the second output unit of the i-th driving circuit; the second control signal generating unit of the (i+2a)th driving circuit is used to send a second sub-control signal generating signal to the control module when receiving the second sub-transmission signal sent from the second output unit of the (i+a)th driving circuit; a second output unit of the (i+2a)th driving circuit receives a first sub-transmission signal transmitted from the second output unit of the i-th driving circuit; where a is an integer greater than or equal to 1, n is an integer greater than 2a, i ∈ [1, n-2a], j = 1, 2, ..., 2a, k = 0, 1, 2, ..., [n / 2a], and j+2ka is less than or equal to n.

2. A display panel driving device comprising:

14. The reset module of the (i+2a)th driving circuit is connected to the second output unit of the (i+3a+1)th driving circuit; The reset module of the (i+2a)th driving circuit is used to transmit the control signal to the ground terminal when receiving a third transmission signal transmitted from the second output unit of the (i+3a+1)th driving circuit.

14. The drive arrangement according to claim 13.

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