Data error correction circuit and data transmission method

Abstract

The present disclosure provides a data error correction circuit and a data transmission method. The data error correction circuit includes a data error correction module used for receiving first data and a first check code corresponding to the first data, correcting an error in the first data according to the first check code to generate second data, and outputting the second data, and a check code generation module used for receiving the first data and the first check code, and generating and outputting the second check code according to the first data and the first check code. The embodiment of the present disclosure can save elements and layout area required for the data error correction function.

Description

[Technical field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This disclosure claims priority to a Chinese patent application filed on March 4, 2022, bearing application number 202210209652.0 and titled "DATA ERROR CORRECTION CIRCUIT AND DATA TRANSMISSION METHOD," the entire contents of which are incorporated herein by reference.

[0002] The present disclosure relates to the field of integrated circuit technology, and in particular to a data error correction circuit and a data transmission method applied to the data error correction circuit. [Background technology]

[0003] The ever-increasing speed of the channel between the memory and the system (controller / processor) brings about a huge challenge to the accuracy of signal transmission. In this context, the related art installs a link error correcting code (Link ECC) in the data receiving terminal (controller / processor) to correct errors in the received data, thereby correcting errors that may occur during channel transmission.

[0004] In order to accurately improve the accuracy of error correction, in the related art, it is usually necessary to generate a second check code including a full check value of the data according to the received data and a first check code corresponding to the data at the data receiving terminal, and then correct the error of the data according to the second check code. Here, the full check value is generated according to the data and each bit of the first check code. This sets a threshold value for the circuit function of the data receiving terminal, and also increases the number of elements and layout area of ​​the data receiving terminal.

[0005] Therefore, how to reduce the demands on the data receiving terminal while maintaining the accuracy of error correction is a technical point that can be improved in integrated circuits having data transmission functions.

[0006] It should be explained that the information disclosed in the above background section is used only to enhance understanding of the background of the present disclosure and may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention [Means for solving the problem]

[0007] The present disclosure aims to provide a data error correction circuit and a data transmission method applied to the data error correction circuit, which solves at least to some extent the problem in related art that a large number of circuit elements are required for the data error correction function and that the layout area occupied is large.

[0008] According to a first aspect of the present disclosure, there is provided a data error correction circuit configured in a memory, the data error correction circuit including: a data error correction module used to receive first data and a first check code corresponding to the first data, correct an error in the first data based on the first check code to generate second data, and output the second data; and a check code generation module used to receive the first data and the first check code, and generate and output a second check code based on the first data and the first check code.

[0009] In one exemplary embodiment of the present disclosure, the data error correction module includes: an error correction code generation unit, which is used to receive the first data and the first check code, and generate a data error correction code and a check error correction code based on the first data and the first check code; and a data error correction unit, which is connected to the error correction code generation unit, is used to receive the first data and the data error correction code, and correct errors in the first data based on the data error correction code to generate and output second data.

[0010] In one exemplary embodiment of the present disclosure, the check code generation module is connected to the error correcting code generation unit and receives the data error correcting code and the check error correcting code, and the check code generation module corrects the second check code based on the data error correcting code or the check error correcting code.

[0011] In one exemplary embodiment of the present disclosure, the check code generation module comprises: a full check value generation unit connected to the error correcting code generation unit, used to receive the first data and the first check code, and generate a full check value based on the first data, the first check code, and the data error correcting code, or to generate the full check value based on the first data, the first check code, and the check error correcting code, wherein the second check code includes the full check value;

[0012] In one exemplary embodiment of the present disclosure, the full check value generation unit includes: a full check value calculation unit used to receive the first data and the first check code and generate an initial full check value based on the first data and the first check code; and a full check value error correction unit connected to the full check value calculation unit and the error correcting code generation unit and used to correct errors in the initial full check value based on the data error correcting code or the check error correcting code, and output the full check value.

[0013] In one exemplary embodiment of the present disclosure, the full check value error correction unit is used for inverting the initial full check value to generate the full check value after receiving the data error correcting code or the check error correcting code.

[0014] In one exemplary embodiment of the present disclosure, the initial full check value is obtained by performing an exclusive-or operation on each bit in the first data and each bit in the first check code.

[0015] In one exemplary embodiment of the present disclosure, the check code generation module includes a check code error correction unit connected to the error correction code generation unit, used to receive the first check code and correct an error in the first check code based on the check error correction code, wherein the second check code includes the first check code after error correction.

[0016] In one exemplary embodiment of the present disclosure, the most significant bit of the second check code is the full check value, and the first check code after error correction constitutes the remaining bits of the second check code.

[0017] In one exemplary embodiment of the present disclosure, the first check code includes 8 bits of data.

[0018] According to a second aspect of the present disclosure, there is provided a memory, the memory including a data error correction circuit as described above, a first output terminal used to output second data, and a second output terminal used to output a second check code corresponding to the second data.

[0019] According to a third aspect of the present disclosure, there is provided an integrated storage device, the integrated storage device including: a memory as described above; and a controller connected to the memory and adapted to receive second data and a second check code, and to perform checking and error correction on the second data based on the second check code.

[0020] In one exemplary embodiment of the present disclosure, the controller determines whether a multiple bit error exists in the second data based on the second check code.

[0021] According to a fourth aspect of the present disclosure, there is provided a data transmission method, which is executed by the memory described in any one of the above, and includes obtaining first data to be transmitted and a first check code corresponding to the first data, correcting an error in the first data based on the first check code and the first data to generate second data, generating a second check code based on the first data and the first check code, and simultaneously outputting the second data and the second check code to a controller, so that the controller performs inspection and error correction on the second data based on the second check code.

[0022] In one exemplary embodiment of the present disclosure, generating a second check code based on the first data and the first check code includes: performing an exclusive-or operation on each bit of the first data and each bit of the first check code to generate an initial full check value; obtaining a check result of the first data and the first check code; and generating the second check code based on the check result, the first check code, and the full check value.

[0023] In one exemplary embodiment of the present disclosure, generating the second check code based on the check result, the first check code, and the full check value includes, when determining based on the check result that an error occurs in the first check code and no error occurs in the first data, correcting the error in the initial full check value to generate a full check value and correcting the error in the first check code; and generating the second check code based on the first check code and the full check value after the error correction.

[0024] In one exemplary embodiment of the present disclosure, generating the second check code based on the check result, the first check code, and the full check value includes, when determining based on the check result that no error has occurred in the first check code and that an error has occurred in the first data, correcting the error in the initial full check value to generate a full check value, and generating the second check code based on the first check code and the full check value.

[0025] In one exemplary embodiment of the present disclosure, generating the second check code based on the check result, the first check code, and the full check value includes, when it is determined based on the check result that no error occurs in both the first data and the first check code, generating the second check code based on the first check code and the initial full check value.

[0026] In one exemplary embodiment of the present disclosure, correcting errors in the initial full check value to generate a full check value includes inverting the initial full check value to generate the full check value.

[0027] In one exemplary embodiment of the present disclosure, generating a second check code based on the first data and the first check code includes: obtaining a check result of the first data and the first check code; when it is determined based on the check result that an error does not occur in both the first data and the first check code, performing an exclusive-OR operation on each bit of the first data and each bit of the first check code, and then determining a total check value, and generating the second check code based on the total check value and the first check code; when it is determined based on the check result that an error has occurred only in the first data, performing an exclusive-OR operation on each bit of the second data and each bit of the first check code, and then determining a total check value, and generating the second check code based on the total check value and the first check code; when it is determined based on the check result that an error has occurred only in the first check code, performing an exclusive-OR operation on each bit of the first data and each bit of the first check code after error correction, and then determining a total check value, and generating the second check code based on the total check value and the first check code after error correction.

[0028] In the embodiment of the present disclosure, the generation of the second check code is completed in the data error correction circuit of the memory, and the second data after error correction and the second check code corresponding to the second data are directly output, so that the data receiving terminal can directly perform inspection and error correction on the second data based on the second check code, which reduces the complicated program in the related art of re-generating the check code in the data receiving terminal based on the received data and check code, reduces the functional requirements for the data receiving terminal, and further reduces the number of elements and layout area of ​​the data receiving terminal, thereby improving the compatibility capability of the memory.

[0029] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. [Brief description of the drawings]

[0030] [Figure 1] FIG. 2 is a structural schematic diagram of a data error correction circuit in an exemplary embodiment of the present disclosure. [Diagram 2] FIG. 2 is a schematic diagram of a data error correction circuit in one embodiment of the present disclosure. [Diagram 3] 3 is a schematic diagram of a full test value generating unit 121 shown in FIG. 2 in one embodiment of the present disclosure. [Figure 4] FIG. 2 is a schematic diagram of a memory according to an embodiment of the present disclosure. [Diagram 5] 5 is a schematic diagram of an integrated storage device to which the memory shown in FIG. 4 is applied. [Figure 6] 4 is a flowchart of a data transmission method according to an embodiment of the present disclosure. [Figure 7] 13 is a sub-flowchart of step S3 in one embodiment of the present disclosure. [Figure 8] 8 is a sub-flowchart of step S33 shown in FIG. 7 in one embodiment of the present disclosure. [Figure 9] 13 is a sub-flowchart of step S3 in another embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0031] The drawings herein are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and are used together with the specification to interpret the principles of the present disclosure. Obviously, the drawings described above are only some embodiments of the present disclosure, and those skilled in the art can obtain other drawings based on these drawings without creative efforts.

[0032] Exemplary embodiments will now be described more fully with reference to the drawings. However, exemplary embodiments may be implemented in various forms and should not be understood to be limited to the examples described herein. On the contrary, these embodiments are provided to make the present disclosure more complete and complete, and to fully convey the concept of exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be incorporated in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a thorough understanding of the embodiments of the present disclosure. However, those skilled in the art should recognize that the technical solutions of the present disclosure may be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of the present disclosure in a false sense of the word.

[0033] In addition, the drawings are only schematic illustrations of the present disclosure, and the same reference numerals in the drawings indicate the same or similar parts, so that redundant explanations thereof will be omitted. Some block diagrams shown in the drawings are functional entities, and do not necessarily correspond to physically or logically independent entities. These functional entities may be realized in software form, in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0034] Hereinafter, exemplary embodiments of the present disclosure will be described in detail in conjunction with the drawings.

[0035] FIG. 1 is a structural schematic diagram of a data error correction circuit in an exemplary embodiment of the present disclosure.

[0036] Referring to FIG. 1, a data error correction circuit 100 is configured in a memory. a data error correction module 11 used to receive first data Data1 and a first check code Parity1 corresponding to the first data, correct an error in the first data Data1 according to the first check code Parity1 to generate second data Data2, and output the second data Data2; It may include a check code generation module 12 used to receive first data Data1 and a first check code Parity1, and generate and output a second check code Parity2 based on the first data Data1 and the first check code Parity1.

[0037] When a memory serves as a data transmitting terminal and transmits data to a data receiving terminal, before outputting the data, it performs error correction on any errors in the data to be transmitted that may be caused by the memory array, i.e., it sets an on-die error correction circuit (On Die ECC: On Die Error Correcting Code) to perform error correction on errors in the memory array.

[0038] In the embodiment of the present disclosure, by improving the on-die error correction circuit of the memory, error correction of the first data Data1 can be realized, and at the same time, a second check code Parity2 can be generated and output directly based on the first data Data1 and the first check code Parity1, so that the data receiving terminal can directly perform checking and error correction on the second data Data2 finally output by the memory based on the second check code, thereby reducing the complicated program in the related art of re-generating the check code at the data receiving terminal based on the received data and check code, saving the functional requirements for the data receiving terminal, further reducing the number of elements and layout area of ​​the data receiving terminal, and improving the compatibility capability of the memory.

[0039] Fig. 2 is a schematic diagram of a data error correction circuit in one embodiment of the present disclosure. In the embodiment shown in Fig. 2, assume that the first data Data1 is 128 bits and is represented as Data<127:0>, correspondingly, the first check code (ECC check code of the first data) Parity1 is 8 bits and is represented as Parity<7:0>, the second data Data2 is 128 bits and is represented as ABus<127:0>, and the second check code Parity2 includes all check values ​​of the second data Data2, is 9 bits and is represented as ABusParity<8:0>.

[0040] Referring to FIG. 2, in one embodiment, the data error correction module 11 includes: an error correction code generating unit 111, which is used to receive a first data Data<127:0> and a first check code Parity<7:0>, and generate a data error correction code Code1 or a check error correction code Code2 according to the first data Data<127:0> and the first check code Parity<7:0>; and a data error correction unit 112 connected to the error correction code generation unit 111, used for receiving the first data Data<127:0> and the data error correction code Code1, and correcting the error in the first data Data<127:0> based on the data error correction code Code1 to generate and output the second data ABus<127:0>.

[0041] The check code generation module 12 is connected to the error correcting code generation unit 111 and receives the data error correcting code Code1 and the check error correcting code Code2, and the check code generation module 12 corrects the second check code ABusParity<8:0> based on the data error correcting code Code1 or the check error correcting code Code2.

[0042] Illustratively, in one embodiment, the check code generating module 12 includes a full check value generating unit 121 and a check code error correcting unit 122 .

[0043] The full check value generation unit 121 is connected to the error correction code generation unit 111, receives the first data Data<127:0> and the first check code Parity<7:0>, and generates a full check value Parity<7:0> according to the first data Data<127:0>, the first check code Parity<7:0>, and the data error correction code Code1. <8> or generates a total check value Parity based on the first data Data<127:0>, the first check code Parity<7:0> and the check error correction code Code2. <8> The second check code ABusParity<8:0> is used to generate the total check value Parity <8> Includes.

[0044] The check code error correction unit 122 is connected to the error correcting code generation unit 111 and is used to receive the first check code Parity<7:0>, correct errors in the first check code Parity<7:0> based on the check error correcting code Code2, and output the error-corrected first check code ABusParity<7:0>, and the second check code ABusParity<8:0> includes the error-corrected first check code ABusParity<7:0>.

[0045] All test values ​​Parity <8> and the error-corrected first check code ABusParity<7:0> are combined and output to form the second check code ABusParity<8:0>. In one embodiment, the most significant bit of the second check code ABusParity<8:0> is the total check value Parity <8> The first check code Parity<7:0> after error correction constitutes the remaining bits of the second check code ABusParity<8:0>. By setting the output timing of the full check value generation unit 121 and the check code error correction unit 122, the full check value generation unit 121 and the check code error correction unit 122 can combine and output the 9-bit second check code ABusParity<8:0>.

[0046] In the embodiment of the present disclosure, the first check code is an ECC check code of the first data output by the memory. The generation of the ECC check code is performed by performing an exclusive OR operation on different bits in the first data based on a setting rule, and the exclusive OR result of a plurality of sets of different bits is set as one bit of the ECC check code. According to the generation rule of the ECC check code, it is possible to detect whether the data has an error based on the ECC check code of the data, and to correct the error of the erroneous data bit by the ECC check code. By checking the data using the ECC check code of the data, it is possible to detect errors in an odd number of bits of the data.

[0047] The second check code of the data is generated based on the data and the first check code of the data. The lower bits of the second check code of the data are the first check code of the data, and the most significant bit is the total check value of the data. The total check value is generated based on the data and the first check code of the data, and in one embodiment, the total check value may be, for example, an exclusive OR result of each bit of the data and each bit of the first check code. According to the above rule, by checking the data using the second check code of the data, it is possible to detect whether the data has an even number of bits of error data.

[0048] By combining the first and second check codes of the data, comprehensive checking and error correction can be performed on the data.

[0049] In the embodiment shown in FIG. 2, the error correction code generation unit 111 receives the first data and the first check code, and the first check code is generated based on the first data, so that the error correction code generation unit 111 can check the first data and the first check code, and determine whether the first data and the first check code have an error based on the check result. The error correction code generation unit 111 indicates the check result by the values ​​of the two output error correction codes. One error correction code is a data error correction code Code1 for indicating that the first data has an error, and the other error correction code is a check error correction code Code2 for indicating that the first check code has an error. It can be assumed that when the data error correction code Code1 is a first value, it indicates that the first data has an error, and when the data error correction code Code1 is a second value, it indicates that the first data is correct, and the first value and the second value are, for example, logic level 1 and logic level 0, respectively, or the first value and the second value are other values, and the present disclosure is not particularly limited thereto. Similarly, it can be assumed that when the check error correcting code Code2 is a first value, it indicates that the first check code is erroneous, and when the check error correcting code Code2 is a second value, it indicates that the first check code is correct.

[0050] The data error correction unit 112 is used to correct an error in the first data, and when the data error correction unit 112 receives a data error correction code Code1 indicating that the data is erroneous, the data error correction unit 112 corrects the error in the first data based on the data error correction code Code1 and outputs second data; when the data error correction unit 112 receives a data error correction code Code1 indicating that the data is correct, the data error correction unit 112 does not correct the error in the first data based on the data error correction code Code1, and directly outputs the first data as the second data.

[0051] Similarly, the check error correction unit 122 is used to correct an error in the first check code, and when the check error correction unit 122 receives a check error correction code Code2 indicating that the first check code is incorrect, the check error correction unit 122 corrects the error in the first check code based on the check error correction code Code2 and outputs the first check code after the error is corrected; when the check error correction unit 122 receives a check error correction code Code2 indicating that the first check code is correct, the check error correction unit 122 does not correct the error in the first check code based on the check error correction code Code2, and directly outputs the first check code after the error is corrected.

[0052] The check code generation module 12 needs to generate a second check code related to the first data and the first check code, and whether an error occurs in the first data or the first check code, both will affect the accuracy of the entire check value, and the check code generation module 12 receives the data error correcting code Code1 and the check error correcting code Code2.

[0053] Here, the full check value generation unit 121 is used to generate a full check value of the first data, and whether an error occurs in the first data or in the first check code, both will affect the accuracy of the full check value, and the full check value generation unit 121 simultaneously receives the data error correcting code Code1 and the check error correcting code Code2.

[0054] In order to correct errors in only the first check code, the check error correction unit 122 receives the check error correction code Code2, corrects the errors in the first check code based on the instructions of the check error correction code Code2, and outputs the first check code ABusParity<7:0> (also 8 bits) after error correction.

[0055] In the embodiment of the present disclosure, not only the error of the first data is corrected to generate the second data, but also all check values ​​are modified according to whether the first data is correct, and the second check code is further modified, so that the accuracy of the second check code can be guaranteed. In addition, the embodiment of the present disclosure checks the first check code, and when an error occurs in the first check code, the errors of the first check code and all check values ​​are corrected, so that the accuracy of the second check code can be further guaranteed.

[0056] Therefore, the embodiments of the present disclosure can improve the accuracy of the second check code, and since the existing memory on-die error correction circuit is utilized, the burden on the circuit structure and signal connections is not significantly increased. Compared with the second check code generation circuit in the related art that needs to be set in each data receiving terminal connected to the memory, the embodiments of the present disclosure can significantly reduce the total number of circuit elements and layout area of ​​the memory and each data receiving terminal.

[0057] FIG. 3 is a schematic diagram of the full test value generating unit 121 shown in FIG. 2 in one embodiment of the present disclosure.

[0058] Referring to FIG. 3, in one embodiment, the full check value generating unit 121 may include a full check value calculating unit 1211 and a full check value error correcting unit 1211.

[0059] The full check value calculation unit 1211 receives the first data Data<127:0> and the first check code Parity<7:0>, and calculates an initial full check value NParity based on the first data Data<127:0> and the first check code Parity<7:0>. <8> is used to generate

[0060] The full check value error correction unit 1212 corrects the full check value Parity <8> A calculation unit and an error correction code generating unit 111 are connected to the calculation unit and the error correction code generating unit 111, and an initial full check value NParity is calculated based on the data error correction code Code1 or the check error correction code Code2. <8> Correct the error and check all Parity values <8> It is used to output the

[0061] Here, the initial test value NParity <8> may be obtained by, for example, performing an exclusive OR operation on each bit in the first data Data<127:0> and each bit in the first check code Parity<7:0>.

[0062] In one embodiment, the full check value error correction unit 1212 receives the data error correction code Code1 and the check error correction code Code2, and then calculates an initial full check value NParity <8> Invert all the test values ​​Parity <8> is used to generate

[0063] The overall operation logic of the data error correction circuit corresponding to the embodiment shown in FIG.

[0064] If the error correcting code generation unit 111 determines that there is no error in both the first data Data<127:0> and the first check code Parity<7:0>, the error correcting code generation unit 111 outputs the values ​​of Code1 and Code2, which indicate that the data and the check code are correct, the check code error correction unit 122 does not correct the error in the first check code Parity<7:0>, and directly outputs it as the first check code ABusParity<7:0> after the error is corrected (i.e., the lower 8 bits of the second check code), and the full check value error correction unit 1212 does not correct the error in the full check value after receiving the values ​​of the data error correcting code Code1 and the check error correcting code Code2, which indicate that the data and the check code are correct, and outputs the initial full check value NParity calculated by the full check value calculation unit 1211. <8> All check codes Parity <8> After error correction, the first check code ABusParity<7:0> and Parity <8> forms the second check code ABusParity<8:0>. The data error correction unit 112 directly outputs the first data Data<127:0> as the second data ABus<127:0>, and controls the transmission timing of the data error correction module 11 and the check code generation module 12 so as to simultaneously transmit the second check code ABusParity<8:0> and the second data ABus<127:0> via the output port.

[0065] If the error correcting code generation unit 111 determines that the first data Data<127:0> has an error, the check code error correction unit 122 receives the check error correcting code Code2 indicating that the first check code is correct, does not correct the error in the first check code Parity<7:0>, and directly outputs the first check code ABusParity<7:0> after the error in the first check code Parity<7:0> has been corrected (i.e., the lower 8 bits of the second check code). The full check value error correction unit 1212 calculates the initial full check value NParity calculated by the full check value calculation unit 1211 based on the data error correcting code Code1 indicating that the data is erroneous. <8> Invert and then Parity <8> (i.e., the most significant bit of the second check code), and the first check code ABusParity<7:0> and Parity <8> forms a second check code ABusParity<8:0>, and the data error correction unit 112 corrects the error in the first data Data<127:0> based on the data error correction code Code1, which indicates that the data is erroneous, and then outputs the second data ABus<127:0>, and controls the transmission timing of the data error correction module 11 and the check code generation module 12 so as to simultaneously transmit the second check code ABusParity<8:0> and the second data ABus<127:0> via the output port.

[0066] If the error correcting code generation unit 111 determines that the first check code Parity<7:0> has an error, the check code error correction unit 122 receives the check error correcting code Code2 indicating that the first check code is correct, corrects the error in the first check code Parity<7:0>, and then outputs the error-corrected first check code ABusParity<7:0> (i.e., the lower 8 bits of the second check code). The full check value error correction unit 1212 calculates the initial full check value NParity calculated by the full check value calculation unit 1211 based on the check error correcting code Code2 indicating that the first check code is correct. <8> Invert and then Parity <8> (i.e., the most significant bit of the second check code), and the first check code ABusParity<7:0> and Parity <8> forms a second check code ABusParity<8:0>, and the data error correction unit 112 does not correct the error in the first data Data<127:0> based on the data error correction code Code1, which indicates that the data is correct, but directly outputs it as the second data ABus<127:0>, and controls the transmission timing of the data error correction module 11 and the check code generation module 12 so as to simultaneously transmit the second check code ABusParity<8:0> and the second data ABus<127:0> via the output port.

[0067] FIG. 4 is a schematic diagram of a memory according to an embodiment of the present disclosure.

[0068] Referring to FIG. 4, the memory 400 includes: A data error correction circuit according to any one of the above embodiments; a first output terminal OUT1 used to output second data Data2; and a second output terminal OUT2 used to output a second check code Parity2 corresponding to the second data Data2.

[0069] The memory shown in FIG. 4 has the function of directly outputting a second check code, which includes the full check code of the second data, and does not require the data receiving terminal to separately install a full check code generation module. It allows the data receiving terminal to directly perform checking and error correction on the second data based on the second check code, which can greatly reduce the technical requirements and power consumption of the data receiving terminal. When connected to multiple data receiving terminals, the area and power consumption of the entire circuit can be greatly reduced.

[0070] FIG. 5 is a schematic diagram of an integrated storage device to which the memory shown in FIG. 4 is applied.

[0071] Referring to FIG. 5, an integrated storage device 500 includes: A memory 400 and a controller 51, The controller 51 is connected to the memory 400, and is used to receive the second data Data2 and the second check code Parity2, and to perform checking and error correction on the second data Data2 based on the second check code Parity2.

[0072] In one embodiment, the controller 51 can determine whether multiple bit errors exist in the second data Data2 based on the second check code Parity2.

[0073] The integrated memory device shown in FIG. 5 does not need to set up a full test value generation circuit in the controller 51, and the controller 51 can directly perform testing and error correction on the second data based on the second test value including the full test value, so that the controller 51 has a smaller circuit area and lower power consumption.

[0074] 6 is a flow chart of a data transmission method according to an embodiment of the present disclosure. The method shown in FIG. 6 may be performed by the memory 400 shown in FIG.

[0075] Referring to FIG. 6, a data transmission method 600 may include steps S1 to S4.

[0076] In step S1, first data to be transmitted and a first check code corresponding to the first data are obtained.

[0077] In step S2, an error in the first data is corrected based on the first check code and the first data to generate second data.

[0078] In step S3, a second check code is generated based on the first data and the first check code.

[0079] In step S4, the second data and the second check code are simultaneously output to the controller, so that the controller performs checking and error correction on the second data based on the second check code.

[0080] Combining Figures 1 and 2, step S1 shown in Figure 6 may be jointly performed by the data error correction module 11 and the check code generation module 12, step S2 is performed by the data error correction module 11, step S3 is performed by the check code generation module 12, and step S4 is jointly performed by the data error correction module 11 and the check code generation module 12.

[0081] The first check code corresponding to the first data is, for example, an ECC check code, and the second check code is formed according to the first data and the ECC check code. The second check code is generated in the memory directly according to the first data and the first check code, so that the data receiving terminal can directly correct the error of the second data according to the second check code, thereby saving the number of circuit elements and the layout area of ​​the data receiving terminal, and improving the compatibility of the memory.

[0082] FIG. 7 is a sub-flowchart of step S3 in one embodiment of the present disclosure.

[0083] Referring to FIG. 7, in one embodiment, step S3 may include steps S31 to S33.

[0084] In step S31, an exclusive OR operation is performed on each bit of the first data and each bit of the first check code to generate an initial full check value.

[0085] In step S32, the check results of the first data and the first check code are obtained.

[0086] In step S33, a second check code is generated based on the check result, the first check code and all check values.

[0087] The embodiment shown in Fig. 7 can be implemented by the circuit shown in Fig. 3. Step S31 can be implemented by the full check value calculation unit 1211, and steps S32 and S33 can be implemented by the full check value error correction unit 1212.

[0088] FIG. 8 is a sub-flowchart of step S33 shown in FIG. 7 in one embodiment of the present disclosure.

[0089] Referring to FIG. 7, in one embodiment, step S33 may include steps S331 to S333.

[0090] In step S331, if it is determined based on the inspection result that an error occurs in the first inspection code and no error occurs in the first data, the errors in the initial full inspection value are corrected to generate a full inspection value, the errors in the first inspection code are corrected, and then a second inspection code is generated based on the first inspection code and the full inspection value after the error correction.

[0091] In step S332, if it is determined based on the inspection result that no error has occurred in the first check code and an error has occurred in the first data, the error in the initial full check value is corrected to generate a full check value, and then a second check code is generated based on the first check code and the full check value.

[0092] In step S333, if it is determined based on the check result that no error occurs in both the first data and the first check code, a second check code is generated based on the first check code and the initial full check value.

[0093] Here, correcting errors in the initial all check values ​​to generate all check values ​​includes inverting the initial all check values ​​to generate all check values.

[0094] In the embodiment shown in FIGS. 2 and 3, the method shown in FIG.

[0095] If there are no errors in both the first data Data<127:0> and the first check code Parity<7:0>, the first check code Parity<7:0> is set to ABusParity<7:0> (i.e., the lower 8 bits of the second check code), and the calculated initial total check value NParity is <8> All check codes Parity <8> Let ABusParity<7:0> and Parity <8> forms the second check code ABusParity<8:0>. The first data Data<127:0> is directly transmitted as the second data ABus<127:0>, and the second check code ABusParity<8:0> and the second data ABus<127:0> are simultaneously transmitted via the output port.

[0096] If an error exists in the first data Data<127:0>, the first check code Parity<7:0> is set to ABusParity<7:0> (i.e., the lower 8 bits of the second check code), and the calculated initial total check value NParity <8> After inverting, all check codes are parity <8> Let ABusParity<7:0> and Parity <8> forms a second check code ABusParity<8:0>, corrects the error in the first data Data<127:0>, and then transmits the second data ABus<127:0>, and then transmits the second check code ABusParity<8:0> and the second data ABus<127:0> through the output port.

[0097] If there is an error in the first check code Parity<7:0>, the full check value error correction unit 1212 corrects the error in the first check code Parity<7:0> and sets it as ABusParity<7:0> (i.e., the lower 8 bits of the second check code), and the calculated initial full check value NParity <8> After inverting, all check codes are parity <8> Let ABusParity<7:0> and Parity <8> forms the second check code ABusParity<8:0>, transmits the first data Data<127:0> directly as the second data ABus<127:0>, and then transmits the second check code ABusParity<8:0> and the second data ABus<127:0> through the output port.

[0098] Besides first generating all check values ​​and then directly correcting the errors in the all check values ​​based on the data error correcting code and the check error correcting code, it is also possible to first perform error correction and then generate all check values ​​based on the correct data after the error correction.

[0099] FIG. 9 is a sub-flowchart of step S3 in another embodiment of the present disclosure.

[0100] Referring to FIG. 9, in another embodiment, step S3 may include steps S91 to S94.

[0101] In step S91, the check result of the first data and the first check code is obtained.

[0102] In step S92, if it is determined based on the check result that no errors occur in either the first data or the first check code, an exclusive-OR operation is performed on each bit of the first data and each bit of the first check code, and then a total check value is determined, and a second check code is generated based on the total check value and the first check code.

[0103] In step S93, if it is determined based on the check result that an error has occurred only in the first data, an exclusive-OR operation is performed on each bit of the second data and each bit of the first check code, and then a total check value is determined, and a second check code is generated based on the total check value and the first check code.

[0104] In step S94, if it is determined based on the inspection result that an error has occurred only in the first check code, an exclusive OR operation is performed on each bit of the first data and each bit of the first check code after the error correction, and then a total check value is determined, and a second check code is generated based on the total check value and the first check code after the error correction.

[0105] The embodiment shown in FIG. 9 may have more accurate processing results when the first check code is applied to other kinds of check codes such as non-ECC check codes.

[0106] In the embodiment shown in FIG. 9, when an error occurs only in the first data, the second data after error correction is directly used to generate a full check value, which requires that error correction for the first data must be completed before generating the second check value. When an error occurs only in the first check code, error correction must be performed on the first check code first, and then a full check value must be generated, which requires that error correction for the first check code must be completed before generating the full check value. When the first check code is an ECC check code, the embodiment shown in FIG. 7 generates a full check value more quickly than the embodiment shown in FIG. 9, and based on the generation principle of the ECC check code, the full check value can be corrected by a simple operation of inversion, and there is no need to wait for error correction for the first data and error correction for the first check value, and the two error corrections can be performed in parallel with the process of generating a full check value, and the data processing speed is relatively fast.

[0107] As can be seen from the above description, the data processing method according to the embodiments of the present disclosure can realize error correction for the first data, and at the same time, can directly generate and output a second check code based on the first data and the first check code, so that the data receiving terminal can directly perform checking and error correction on the second data finally output by the memory based on the second check code, thereby reducing the functional requirements for the data receiving terminal, further reducing the number of elements and layout area of ​​the data receiving terminal, and improving the compatibility ability of the memory.

[0108] Other embodiments of the present disclosure will be readily envisioned by those skilled in the art after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses or adaptations of the present disclosure, which variations, uses or adaptations conform to the general principles of the present disclosure and include known knowledge or customary techniques in the art that are not disclosed by the present disclosure. The specification and examples are considered as merely exemplary, with the true scope and spirit of the present disclosure being indicated by the following claims. [Industrial Applicability]

[0109] In the embodiment of the present disclosure, the generation of the second check code is completed in the data error correction circuit of the memory, and the second data after error correction and the second check code corresponding to the second data are directly output, so that the data receiving terminal can directly perform inspection and error correction on the second data based on the second check code, which reduces the complicated program in the related art of re-generating the check code in the data receiving terminal based on the received data and check code, reduces the functional requirements for the data receiving terminal, and further reduces the number of elements and layout area of ​​the data receiving terminal, thereby improving the compatibility capability of the memory.

Claims

1. A data error correction circuit configured in a memory, comprising: a data error correction module used to receive first data and a first check code corresponding to the first data, correct an error in the first data according to the first check code to generate second data, and output the second data; a check code generating module for receiving the first data and the first check code, and generating and outputting a second check code based on the first data and the first check code; The data error correction module includes: an error correction code generation unit, which is used to receive the first data and the first check code, and generate a data error correction code and a check error correction code based on the first data and the first check code; a data error correction unit connected to the error correction code generation unit, for receiving the first data and the data error correction code, and correcting an error in the first data based on the data error correction code to generate and output second data; The check code generation module includes: a full check value generating unit connected to the error correction code generating unit, for receiving the first data and the first check code, and for generating a full check value based on the first data, the first check code and the data error correction code, or for generating the full check value based on the first data, the first check code and the check error correction code, wherein the second check code includes the full check value; Data error correction circuitry.

2. The full test value generating unit includes: a total check value calculation unit, the total check value calculation unit being used to receive the first data and the first check code and generate an initial total check value based on the first data and the first check code, the initial total check value being obtained by performing an exclusive OR operation on each bit in the first data and each bit in the first check code; a total check value error correction unit connected to the total check value calculation unit and the error correction code generation unit, and used for correcting errors in the initial total check value based on the data error correction code or the check error correction code to output the total check value; 2. The data error correction circuit of claim 1.

3. The full check value error correction unit is used for inverting the initial full check value to generate the full check value after receiving the data error correction code or the check error correction code.

3. The data error correction circuit of claim 2.

4. The check code generation module includes: A check code error correction unit is connected to the error correction code generation unit, and is used to receive the first check code and correct an error in the first check code based on the check error correction code, where the second check code includes the first check code after error correction; the most significant bit of the second check code is the full check value, and the first check code after error correction constitutes the remaining bits of the second check code; the first check code includes 8 bits of data; The data error correction circuit according to any one of claims 1 to 3.

5. A data error correction circuit according to any one of claims 1 to 3; a first output terminal used for outputting second data; a second output terminal used for outputting a second check code corresponding to the second data.

6. A memory according to claim 5; a controller coupled to the memory, the controller being used to receive second data and a second check code, and to perform checking and error correction on the second data based on the second check code; The controller determines whether a plurality of bit errors exist in the second data based on the second check code.

7. A data transmission method, which is performed by a memory according to claim 5, comprising the steps of: Obtaining first data to be transmitted and a first check code corresponding to the first data; correcting an error in the first data based on the first check code and the first data to generate second data; generating a second check code based on the first data and the first check code; and simultaneously outputting the second data and the second check code to a controller so that the controller performs checking and error correction on the second data based on the second check code.

8. Generating a second check code based on the first data and the first check code includes: performing an exclusive OR operation on each bit of the first data and each bit of the first check code to generate an initial full check value; Obtaining a check result of the first data and the first check code; generating the second check code based on the check result, the first check code, and a full check value; Or, Generating a second check code based on the first data and the first check code includes: Obtaining a check result of the first data and the first check code; When it is determined based on the check result that no error occurs in both the first data and the first check code, performing an exclusive OR operation on each bit of the first data and each bit of the first check code, and then determining a total check value, and generating the second check code based on the total check value and the first check code; When it is determined based on the check result that an error has occurred only in the first data, performing an exclusive OR operation on each bit of the second data and each bit of the first check code, and then determining a total check value, and generating the second check code based on the total check value and the first check code; When it is determined based on the check result that an error has occurred only in the first check code, performing an exclusive OR operation on each bit of the first data and each bit of the first check code after error correction, and then determining a total check value, and generating the second check code based on the total check value and the first check code after error correction. The data transmission method according to claim 7.

9. generating the second check code based on the check result, the first check code, and the full check value, when it is determined based on the check result that an error occurs in the first check code and that an error does not occur in the first data, correcting the error in the initial full check value to generate a full check value, thereby correcting the error in the first check code; generating the second check code based on the first check code after error correction and the full check value; Or, generating the second check code based on the check result, the first check code, and the full check value, when it is determined based on the check result that no error has occurred in the first check code and an error has occurred in the first data, correcting the error in the initial full check value to generate a full check value; generating the second check code based on the first check code and the full check value; Or, generating the second check code based on the check result, the first check code, and the full check value, generating the second check code based on the first check code and the initial full check value when it is determined based on the check result that no error occurs in both the first data and the first check code; The data transmission method according to claim 8.

10. Correcting errors in the initial full check values ​​to generate full check values ​​includes: inverting the initial full test value to generate the full test value.

10. The data transmission method according to claim 9.

Images