Electrical connector assembly having horizontal to vertical wafer interconnects - Patents.com

Abstract

To provide a high speed connector having a minimal footprint including a wafer assembly incorporating separately interconnected low speed and / or power terminals while maintaining suitable electrical characteristics for transmitting signals at high data rates.SOLUTION: An electrical connector assembly may include a plurality of horizontal wafers used in combination with a plurality of vertical wafers. The vertical wafers may include terminals that interconnect with a set of non-high speed terminals disposed within the horizontal wafers. The vertical wafers may be positioned side-by-side and positioned to engage the trailing edges of the horizontal wafers.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Provisional Patent Application No. 63 / 089,005, filed October 8, 2020 (the "005 Application"), which is incorporated herein by reference in its entirety. [Background technology]

[0002] High speed or high data rate electrical connectors often incorporate multiple wafer assemblies supporting multiple conductive terminals. However, when physical space is at a minimum, it is a challenge to construct a high speed or high data rate connector ("high speed" and "high data rate" may be used interchangeably herein) using a wafer assembly that incorporates separately interconnected low speed and / or power terminals within such a minimum footprint while at the same time maintaining suitable electrical properties for transmitting signals at high data rates.

[0003] It is therefore desirable to provide a high speed connector having a minimal footprint including a wafer assembly that incorporates separately interconnected low speed and / or power terminals while at the same time maintaining suitable electrical properties for transmitting signals at high data rates. Summary of the Invention

[0004] The present disclosure describes an electrical connector assembly for electrically interconnecting a first plurality of wafers (i.e., a plurality of horizontally configured wafers) to a second plurality of wafers (i.e., a parallel collection of vertically configured wafers). Each horizontal wafer may include a first set of terminals conducting high data rate signals and a second set of terminals conducting non-high data rate signals (e.g., low data rate signals and / or power connections). The parallel collection of vertically configured wafers may be formed to include non-high speed terminals in a similar number and position to the second set of terminals in the horizontal wafer, providing a path for the conduction of non-high data rate signals separate from the path provided for the high data rate signals exiting the horizontal wafer.

[0005] In one embodiment, the electrical connector assembly may include a plurality of horizontal wafers used in combination with a set of vertical wafers, the vertical wafers having non-high speed terminals that interconnect with similar terminals in the plurality of horizontal wafers. In particular, each horizontal wafer may include high speed terminals configured to transmit signals at a high data rate and non-high speed terminals configured to provide power and transmit signals at a lower data rate than the high speed terminals. The high speed terminals and non-high speed terminals may have contacts aligned in a row adjacent the front edge of the horizontal wafer and may have terminal bodies extending rearward of the contacts and terminating as terminal ends that are either exposed beyond the rear edge of the horizontal wafer or terminated to the conductors of a cable. Each of the horizontal wafers may include a ground shield that extends either above or below a portion of the terminal body of the high speed terminal. The vertical wafers may be positioned in parallel, with each vertical wafer including a non-high speed terminal having a contact portion, a terminal portion, and a body portion therebetween, the contact portion configured to mate with, for example, the terminal portion of each non-high speed terminal of the plurality of horizontal wafers.

[0006] More particularly, in one embodiment, the electrical connector assembly comprises: (i) a plurality of horizontal wafers, each horizontal wafer having high speed terminals configured to transmit signals at a high data rate (e.g., data rates generally of 50 Gbps or greater, potentially 112 Gbps or greater) and non-high speed terminals configured to transmit power and signals at a low data rate (e.g., data rates typically less than 20 Gbps, often less than 5 Gbps), the high speed terminals and non-high speed terminals having contacts aligned adjacent a front edge of the horizontal wafer and terminal bodies extending rearward of the contacts, the high speed terminals configured to terminate to conductors in a cable that extends beyond the rear edge of the horizontal wafer, and the non-high speed terminals configured to terminate to conductors in a cable that extends beyond the rear edge of the horizontal wafer when their ends are exposed at the rear edge of the horizontal wafer. and (ii) a plurality of vertical wafers positioned in parallel, each vertical wafer comprising a terminal, each terminal comprising a contact portion (e.g., a C-clamp structure or a cantilevered element including a conductive bump), an end portion, and a body portion therebetween, each contact portion configured to mate with an end portion of a respective non-high speed terminal at an inner edge of the plurality of horizontal wafers.

[0007] The vertical wafers may, for example, include a stepped configuration for mating with the inner edges of the horizontal wafers.

[0008] In one embodiment, where the contact portion comprises a C-clamp structure, such structure may comprise, for example, a pair of pinhole elements separated by a throat spacing.

[0009] The electrical connector assembly of the present invention may also include support and stabilizing elements configured to support the multiple vertical wafers in a stable, parallel position, and / or locating pins configured to pass through a set of openings formed in each vertical wafer of the multiple vertical wafers and an opening formed in an end termination region of the insulating housing, the locating pins configured to support the multiple vertical wafers in aligned relationship with the multiple horizontal wafers.

[0010] In one embodiment, the high speed terminals may comprise differential pairs of signal terminals and one or more ground terminals, and the electrical connector assembly may further comprise a ground shield that may be configured to contact the ground terminals adjacent the contacts. The high speed terminals of each horizontal wafer may be terminated to a cable configured to transmit signaling at, for example, high data rates.

[0011] Further, in another embodiment, each vertical wafer may be configured as a stepped structure and may include a plurality of separate landing steps exposing respective contact portions of the vertical wafer terminals, the plurality of separate landing steps being at least sufficient to support a plurality of horizontal wafers in a one-to-one relationship, each exposed contact portion connecting with an inner edge.

[0012] In addition to the electrical connector assemblies described above, additional electrical connector assemblies are described herein. For example, in one embodiment, an exemplary electrical connector assembly includes: (i) a plurality of horizontal wafers, each horizontal wafer having high speed terminals configured for signal transmission at a high data rate and non-high speed terminals configured for power and signal transmission at a low data rate, the high speed terminals and non-high speed terminals having aligned contacts adjacent a front edge of the horizontal wafer and terminal bodies extending rearward of the contacts, at least a portion of the high speed terminals configured to terminate to conductors in a cable, the non-high speed terminals terminating as exposed ends from the rear edge and terminal bodies adjacent the ends. and (ii) a plurality of vertical wafers, the plurality of vertical wafers positioned in parallel, each vertical wafer having a terminal having a contact portion (e.g., a C-clamp structure), an end portion, and a body portion therebetween, the contact portion configured to mate with an end portion of each non-high speed terminal on an inner edge of the plurality of horizontal wafers, the plurality of vertical wafers having exactly one vertical wafer for each non-high speed terminal on one of the horizontal wafers, and each horizontal wafer of the plurality of horizontal wafers having the same number of non-high speed terminals.

[0013] Additionally, the electrical connector assembly may include support and stabilization elements configured to span across and capture the plurality of vertical wafers to support and stabilize the parallel arrangement. Additionally, each vertical wafer of the connector assembly may include alignment openings and locating pins configured to pass through the alignment openings to support the plurality of vertical wafers in an aligned position relative to the plurality of horizontal wafers.

[0014] In one embodiment, the high speed terminals may comprise a differential pair of signal terminals.

[0015] Similar to the above, the additional electrical assembly may include an insulating housing configured to enclose the bonded array of the horizontal wafers and the vertical wafers. Further, in one embodiment, the terminals of the vertical wafers may be configured to exit through a bottom surface of the insulating housing, and the high speed terminals of the horizontal wafers may be configured to exit through a surface of the insulating housing other than the bottom surface.

[0016] Components of an electrical connector assembly are also disclosed, including, but not limited to, a horizontal wafer for use in an electrical connector assembly, which may include a frame constructed of an insulating material, the frame element having a front edge and an opposing rear edge, a plurality of high speed terminals supported by the frame, configured for signal transmission at high data rates, each high speed terminal having a contact end portion exposed at the front edge and a terminal end portion exposed at the rear edge of the frame element, and having a body portion of each high speed terminal embedded in the insulating material of the frame element, and non-high speed terminals configured for power and signal transmission at low data rates, the non-high speed terminals aligned with the plurality of high speed terminals, each non-high speed terminal having a contact portion exposed at the front edge and a terminal end portion exposed at an inner edge recessed from the rear edge of the frame element, and having a body portion of each high speed terminal embedded in the insulating material of the frame.

[0017] The above features and advantages, as well as others, will become apparent from the following detailed description and the accompanying drawings. [Brief description of the drawings]

[0018] The present disclosure is illustrated by way of example and not limitation in the accompanying drawings in which like reference numbers refer to similar elements.

[0019] [Figure 1] FIG. 2 is a perspective top view of an exemplary electrical connector assembly for mating multiple horizontal wafers with a side-by-side array of vertical wafers. [Diagram 2]FIG. 2 is a perspective bottom view of the electrical connector assembly shown in FIG. 1. [Diagram 3] FIG. 2 is a simplified side view of the electrical connector assembly of FIG. 1. [Figure 4] FIG. 2 is an exploded view of the electrical connector assembly of FIG. 1. [Diagram 5] 2 is a partially exploded view of the electrical connector assembly of FIG. 1 showing the spatial relationship between an exemplary insulator and a horizontal wafer, as well as the spatial relationship between the horizontal wafer and a collection of vertical wafers. [Figure 6] FIG. 2 is a top perspective view of a horizontal wafer showing the locations of the various terminals. [Figure 7] FIG. 7 is a partially exploded view of some of the components of the horizontal wafer of FIG. 6, particularly showing an exemplary frame that can be used to support the terminals and an external ground shield (plated) with exposed ground pins for mating with ground terminals on the frame. [Figure 8] 8 is another partially exploded view of some of the components of the horizontal wafer of FIG. 6 , particularly showing the frame combined with a lower ground shield (similarly plated) having exposed ground pins for mating with ground terminals on the frame, which in combination with the ground shield of FIG. 7 completes the EMI shielding for the high speed signal paths passing through the connector assembly. [Figure 9] In this enlarged view of a portion of the horizontal wafer, a diagram showing the next step in the assembly of a representative horizontal wafer is shown, showing the attachment of individual conductors to each of the terminal ends of the high speed terminals exposed on the back side of the horizontal wafer, as well as a cable that can accommodate pairs of conductors as shown to form a twin-axial cable wiring array. [Figure 10] FIG. 10 illustrates the assembly steps in forming a representative horizontal wafer following attachment of conductors and cables as shown in FIG. 9, and in particular shows a conductive lead frame that is added to provide shielding for high speed terminal / conductor connections at the rear of the horizontal wafer. [Figure 11]A side perspective view of a vertical wafer illustrating a stepped configuration of a frame combined with terminals positioned to interconnect with low speed and / or power terminals (collectively referred to as "non-high speed terminals") of multiple horizontal wafers. [Figure 12] FIG. 1 is a close-up view of a representative connector portion of a vertical wafer terminal shown in combination with an end portion of a non-high speed terminal from a horizontal wafer prior to contact between the two wafers. [Figure 13] 14 is an enlarged view similar to FIG. 13, further illustrating the representative location of the distal end portion of a non-high speed terminal within a vertical wafer terminal C-clamp connector following wafer-to-wafer connection. [Figure 14] FIG. 13 is a side isometric view of a conductive terminal that can be used in a vertical wafer to provide connection to a non-high speed terminal of a horizontal wafer. [Figure 15] FIG. 1 illustrates a parallel configuration of a collection of vertical wafers that can be interconnected with multiple horizontal wafers to provide paths for non-high data rate signals. [Figure 16] FIG. 13 is a cutaway side view of an alternative interconnect configuration using a representative cantilevered beam in a vertical wafer to provide electrical connections to non-high speed terminals in multiple horizontal wafers. [Figure 17] FIG. 2 is an exploded isometric view showing the relationship between a typical number of non-high speed terminals formed in a horizontal wafer and the number of vertical wafers that can be used for complete interconnection. [Figure 18] FIG. 1 is an isometric cutaway view of an exemplary combination of multiple horizontal wafers and a parallel stack of vertical wafers. [Figure 19] 1 is an isometric view of an exemplary insulating housing element and a number of horizontal wafers that may be used in forming an electrical connector assembly. [Figure 20] FIG. 20 is an isometric view related to FIG. 19 further illustrating the relationship of multiple horizontal wafers to the parallel stack of vertical wafers. [Figure 21] FIG. 21 is an isometric view related to FIGS. 19 and 20 showing an exemplary assembled connector that may include a housing, multiple horizontal wafers, and a parallel assembly of vertical wafers. [Figure 22] FIG. 13 is a cutaway side view of an exemplary combination of multiple horizontal wafers and a parallel collection of vertical wafers, in which the vertical wafer terminals may be formed to exit through the rear edge of the vertical wafers. [Figure 23] FIG. 1 is an exploded isometric view of an exemplary connector assembly that may include a pair of horizontal wafers and interconnected parallel vertical wafers. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] Simplicity and clarity in both illustration and description are required to effectively enable a person skilled in the art to make, use, and best practice the embodiments disclosed herein in view of what is already known in the art. Those skilled in the art will appreciate that various modifications and changes may be made to the specific embodiments described herein without departing from the spirit and scope of the present disclosure. Thus, the specification and drawings should be regarded as illustrative and representative, rather than restrictive or comprehensive, and all such modifications to the specific embodiments described herein are intended to be included within the scope of the present disclosure. Furthermore, it should be understood that the following detailed description describes representative embodiments and is not intended to be limited to the combinations expressly disclosed. Thus, unless otherwise specified, features disclosed herein may be combined together to form additional combinations not otherwise described or shown for purposes of brevity.

[0021] It should also be noted that one or more exemplary embodiments may be described as a method. Although the method may be described in a representative sequence (i.e., sequentially), it should be understood that such methods may be performed in parallel, jointly, or simultaneously. Additionally, the order of each variant step within a method may be permuted. The described method may be terminated when completed, or may include additional steps not described herein, for example, if such steps are known to one of ordinary skill in the art.

[0022] As used herein, the terms "embodiment" or "exemplary" refer to examples falling within the scope of the present disclosure.

[0023] 1-4, one embodiment of a representative electrical connector assembly 10 (referred to as "assembly 10") is shown, with FIG. 1 showing a side view of assembly 10, FIG. 2 showing an isometric view from underneath assembly 10, FIG. 3 showing a cutaway side view of assembly 10 along line 3-3 in FIG. 1, and FIG. 4 showing a partially exploded view of the components of assembly 10. In one embodiment, assembly 10 may include an insulating housing 11, which may be constructed of a Liquid Crystal Polymer (LCP) material or other desired resin, such as, for example, a plurality of horizontal wafers 12 and a plurality of vertical wafers 14. The housing defines a card slot 11a including terminal grooves 11b configured to align with at least some of the contacts of a high speed terminal. The housing further includes alignment openings 11c that may be used to receive pins (not shown), which may be inserted through alignment openings 11c and through openings in the vertical wafers to provide additional support.

[0024] In one embodiment, multiple horizontal wafers 12 may be mated with multiple vertical wafers 14 within the insulating housing 11 such that non-high speed terminals in the horizontal wafers 12 mate with connectors (not shown) in the vertical wafers 14 to conduct respective low speed data (e.g., 1 Gbps) or power signals along electrical paths separate and distinct from paths dedicated to conducting signals at high data rates that may pass through the electrical connector assembly 10. Stated differently, in this embodiment, high data rate signals passing through and along separate sets of terminals in the horizontal wafers 12 are not connected to the vertical wafers 14, but instead are directly connected to a mating high speed structure (e.g., an electrical transmission cable such as a twin-axial cable).

[0025] 1-3, one representative configuration of high data rate signal paths 13H is shown exiting at the rear edge 10E of assembly 10, while non-high data rate signal paths 13N are shown exiting along the bottom surface 10B of assembly 10. As can be appreciated, the high data rate signal paths can be in the form of a cable with two conductors, such as, but not limited to, a twin-axial cable, and can include different forms of drain wire configurations ranging from no drain wire, to a wide flat drain wire, to twin drain wire, or any other desired configuration.

[0026] A representative parallel array of vertical wafers 14 may be combined with multiple horizontal wafers 12 to form a low profile, minimized footprint (i.e., small size) electrical connector assembly 10 that provides separate signal paths for high data rate signals, low data rate / power signals, and direct board connections for the low data rate and / or power signals.

[0027] 4, the exemplary assembly 10 may include four separate horizontal wafers 12-1, 12-2, 12-3, and 12-4, which may each include high speed terminals 16 and non-high speed terminals 18. In one embodiment, connector ends 18c of the non-high speed terminals 18 may be positioned in registration with connector ends 16c of the high speed terminals 16.

[0028] The number of individual vertical wafers 14 used in the electrical connector assembly 10 may be selected such that at least one vertical wafer 14 may be connected to each individual horizontal wafer 12-i. As shown in FIG. 4, each vertical wafer 14 may be formed to exhibit a stepped structure including a set of landing tiers (see, for example, elements 44-1, 44-2 in FIG. 11) for exposing the separate vertical terminals 42. The number of landing tiers formed in each vertical wafer 14 may be selected, for example, to accommodate at least the total number of individual horizontal wafers 12. In one embodiment, in an electrical connector assembly 10 including a set of four horizontal wafers 12, each vertical wafer 14 may include at least four separate landing tiers, it being understood that two horizontal wafers or more than four horizontal wafers may be used, if desired. Furthermore, in an electrical connector assembly 10 using horizontal wafers 12 each having a set of five non-high speed terminals 18, a collection of five vertical wafers 14 (positioned in parallel) may be used to fully interconnect the terminals 18.

[0029] Referring now to FIG. 5, there is shown a representative configuration of an electrical connector assembly 10 that may be formed by inserting multiple horizontal wafers 12 into an insulating housing 11, followed by a parallel collection of vertical wafers 14 to engage non-high speed terminals that may emerge on the underside of each horizontal wafer 12.

[0030] 6 illustrates an isometric view of an exemplary horizontal wafer 12, particularly illustrating an exemplary configuration of the high speed terminals 16 and non-high speed terminals 18 across the width of the wafer 12. In one embodiment, the horizontal wafer 12 may include a frame 20 formed from an insulating material and configured to include a front edge 22 and a rear edge 24. As shown, the frame 20 includes a front portion 20a that supports the high speed terminals 16 and the non-high speed terminals 18, and a rear portion 20b that is overmolded onto the front portion and overmolded onto the corresponding cables once the conductors are attached to the high speed terminals 16. Of course, if the cable conductors are pre-attached to the high speed terminals 16, the frame 20 may be formed in a single molding operation.

[0031] Connector portions 16C of high speed terminals 16 may extend in alignment beyond front edge 22 of frame 20, and connector portions 18C of non-high speed terminals 18 may also extend beyond front edge 22 and be positioned in alignment with connector portions 16C. Body portions of terminals 16, 18 (e.g., body portion 16B shown below in FIG. 7) may be embedded within and supported by the insulating material of frame 20.

[0032] FIG. 7 illustrates high speed terminals 16 and non-high speed terminals 18 that may be supported within a frame 19. The central location of the non-high speed terminals 18 is clearly shown, with a pair of high speed terminals 16 shown on either side. Each high speed terminal 16 may be formed to include a connector portion 16C, an end portion 16T, and a body portion 16B therebetween. As discussed above, the body portion 16B may ultimately be embedded within the insulating material of the frame 20. Each non-high speed terminal 18 may similarly be formed to include a connector portion 18C, an end portion 18T, and a body portion 18B therebetween (body portion 18B is hidden within the material of the frame 19 in the view of FIG. 7). As will be explained in more detail below, the end portion 18T of the non-high speed terminal 18 terminates along an inner edge 28 of the frame 20 (see FIG. 6), with the end portion 16T possibly extending further out from the frame 19 before being attached to a cable conductor 21, as shown in FIG. 9.

[0033] Continuing with Figure 7, also shown on the frame 19 is a set of ground terminals 17 that can be connected to other components to form a ground plane and provide EMI shielding for high speed signal paths. In an exemplary embodiment shown in Figure 7, a ground shield 30 may be positioned over the frame 19 and used to provide EMI shielding. As shown, the ground shield 30 includes a set of ground tabs 31 that can engage the ground terminals 17 when the ground shield 30 is positioned over the frame 19.

[0034] A lower ground shield 30A may also be used in combination with the frame 19 to complete the EMI shielding structure. Figure 8 shows one embodiment of this configuration, with only the frame 19 and lower ground shield 30A shown for clarity (it should be understood that the ground shield 30 positioned over the frame 19 may also be included in the final structure). The ground shield 30A includes a ground lead frame 31A that may engage with the ground terminal 17 on the frame 19.

[0035] FIG. 9 illustrates the next step in the exemplary assembly of the horizontal wafer 12. FIG. 9 is an enlarged view of a terminal portion 16T of the high speed terminals 16 that may be in place on the lower ground shield 30A (see FIG. 8). In this example, each high speed terminal 16 is shown as taking the form of a differential pair of conductive terminals 16a, 16b, which may be a preferred arrangement for supporting the transmission of signals at high data rates. In one embodiment, the exemplary electrical connector assembly 10 may be used in a system supporting data transmission in the typical range of 100-120 Gbps (e.g., 112 Gbps). Separate conductors 21a, 21b may be attached to the paired conductive terminals 16a, 16b. The example shown in FIG. 9 creates a structure having a set of four high speed outputs, with each separate conductor pair 21a, 21b housed within a cable 26 (shown in FIG. 9 as cables 261, 262, 263, and 264 for illustrative purposes only). As discussed above, the cables may be of a desirable biaxial configuration. A pair of ground straps 30B1 and 30B2 may then be positioned over the "cable-like" termination of high speed terminal 16 having conductor 21 thereon, as shown in FIG.

[0036] The details of the assembly process of the horizontal wafer 12 as shown in Figures 7-10 are intended to aid in understanding the operation of the horizontal wafer 12 described above in connection with Figure 6, and further explanation of Figure 6 regarding the interconnections between the horizontal wafer 12 and the vertical wafer 14 continues in the following paragraphs.

[0037] 6, in one embodiment, end portions 18T of non-high speed terminals 18 may be exposed along a recessed rear edge 28 that may be recessed somewhat relative to rear edge 24 of frame 20 by an amount "S". The amount of spacing "S" between recessed rear edge 28 and rear edge 24 may vary for each horizontal wafer 12 and may be designed to properly engage with the stepped configuration of vertical wafer 14. In one exemplary embodiment, spacing amount S may range, for example, from 4 millimeters to 15 millimeters. For purposes of illustration, a set of five individual non-high speed terminals 181-185 are shown on horizontal wafer 12 in FIG. 6.

[0038] 11, a close-up view of a representative vertical wafer 14 is shown. The wafer 14 may include a frame 40, which may be formed from an insulating material and may be configured to include one or more vertical terminals 42 that may form one or more connections between the non-high speed terminals 18 of the plurality of horizontal wafers 12 and a circuit board (or other suitable low speed / power wire connections, not shown in FIG. 11). In this embodiment, each vertical terminal 42 is shown as having a connector end portion 42C (configured to mate with a corresponding non-high speed terminal 18 of the horizontal wafer 12), a vertically configured terminal end portion 42T, and a body portion 42B therebetween. FIG. 11 also shows a representative terminal portion 42T of the vertical terminal 42. In one embodiment, the portion 42T may include a press-fit pin for terminating a low speed data or power connection. Alternatively, a Surface-Mount-Technology (SMT) type connection may be used as the terminal portion of the vertical terminal 42. The frame 40 may include multiple landing steps 44, with each individual landing step being used to support a separate one of the horizontal wafers 12. In particular, the recessed trailing edge 28 of the horizontal wafer 12 may be positioned on the landing steps 44 (see, e.g., FIG. 13 ). In one embodiment, the staggered arrangement of landing steps (i.e., stepped structure) combined with the different spacing amounts S between the trailing edge 24 and the recessed trailing edge 28 allows a parallel arrangement of vertical wafers 14 to engage the horizontal wafers 12 in a compact, low-profile configuration.

[0039] In the exemplary embodiment of FIG. 11, the vertical wafers 14 include openings 46 that can be used to support any fixed pins that pass through the parallel set of vertical wafers (see FIG. 17). As also shown in FIG. 11, angled surfaces 48 may be formed within the structure of the frame 40. In one embodiment, when the vertical wafers 14 are positioned in parallel, optional tie bars 70 (which may be constructed from a metal alloy such as stainless steel) may be positioned to engage a complete set of angled surfaces 48 (see, for example, FIG. 15) to further support and stabilize the connection of the multiple vertical wafers 14 to the multiple horizontal wafers 12.

[0040] In the embodiment of FIG. 11, the connector end portion 42C of the vertical terminal 42 may be formed as a C-clamp arrangement of a pair of Eye-Of-Needle (EON) terminations 41, 43. Referring now to FIG. 12, a close-up view of a representative connector portion 42C and associated terminal end portion 18T from a non-high speed terminal 18 exiting a horizontal wafer 12 is shown. In one embodiment, the C-clamp arrangement of the EONs 41, 43 can guide the terminal end portion 18T into a throat region 45 disposed between the EONs 41, 43, where the movement of the terminal end portion 18T is indicated by the arrows in FIG. 12. FIG. 13 illustrates that the compressed EONs 41, 43 apply a normal force to both the top and bottom surfaces of the terminal end portion 18T as the terminal end portion 18T is guided (e.g., slid) into position within the C-clamp connector portion 42C.

[0041] 14, there is shown an isometric view of representative vertical terminals 42 that can be used as components of the vertical wafer 14 in the embodiment shown in FIG. 12. The vertical terminals 42, shown in FIG. 14 prior to singulation and prior to being overmolded, may comprise a metallic material such as a copper alloy. The vertical terminals 42 are shown four in a row, but may be any other number and therefore used to form the vertical wafer 14. The inner body portion 42B of each vertical terminal 42 is specifically shown in this view, with the body portions 42B each terminating in their respective end portions 42T (again shown as press-fit pins).

[0042] FIG. 15 illustrates a representative parallel arrangement of multiple vertical wafers 14 that can ultimately mate with exposed ends of multiple horizontal wafers 12 (not shown). The isometric side view of FIG. 15 illustrates a representative parallel arrangement of connector end portions 42C of vertical terminals 42, with each individual connector end portion 42C positioned to mate with a terminal portion 18T from a non-high speed terminal 18 in a one-to-one relationship. For example, as discussed above, if each horizontal wafer includes a representative set of five separate non-high speed terminals 181-185 (see FIG. 17), then a set of five individual vertical wafers (arranged in parallel) may be used such that each terminal 181-185 of each horizontal wafer 12-i has a mated non-high speed connection. Similarly, the stepped arrangement of the parallel collection of vertical wafers 14 illustrates that the number of landing tiers 44 (and associated connector end portions 42C) may be the same as the number of individual horizontal wafers 12.

[0043] FIG. 16 is a cutaway side view of an alternative interconnection configuration of non-high speed terminals 18 and multiple vertical wafers 14. Instead of terminals having C-clamp connectors 42C as shown in FIGS. 12-15, a cantilevered array of conductive connector bumps 47 configured on the underside of landing shoulder 44 may be included to contact non-high speed end portions 18T. In one embodiment, when engaging multiple horizontal wafers 12, landing shoulder 44 of vertical wafer 14 may apply a slight force to end portions 18T to induce end portions 18T into contact with conductive bumps 47. The compressive spring force applied by conductive bumps 47 functions to maintain physical contact between conductive bumps 47 and associated end portions 18T. Similar to the vertical terminals 42 of the above arrangement, conductive connector bumps 47 may then extend as conductors within frame material 40 and exit along a connection surface shown here as comprising multiple press-fit pins 47P that exit the underside of vertical wafer 14.

[0044] 17, an exploded isometric view is shown illustrating the relationship between a representative number of non-high speed terminals 18 formed in horizontal wafers 12-1 through 12-4 and a representative number of vertical wafers 14 that can be used to interconnect with those terminals. Also apparent from this view is the one-to-one relationship between the number of individual horizontal wafers 12 and the number of individual landing tiers (steps) that may be formed in each vertical wafer 14 to provide connections to each individual horizontal wafer 12. As shown, a set of four individual horizontal wafers 12-1 through 12-4 may be configured to form a plurality of horizontal wafers, with each horizontal wafer 12-i including a set of five individual non-high speed terminals 181 through 185. Thus, a set of five vertical wafers 14-1 through 14-5 may be used, as shown in FIG. 17, to engage the set of five terminal portions 18T1 through 18T5 of each horizontal wafer 12-i. Each vertical wafer 14 may be structurally stepped to include a set of four separate landing steps 44-1-44-4 (and associated connector end portions 42C). Representative tie bars 70 are also shown and may be configured to slide into juxtaposition on the inclined surfaces 48, thereby supporting and stabilizing the collection of vertical wafers 14.

[0045] FIG. 18 shows an isometric cutaway view of a combination of multiple horizontal wafers 12 and a parallel set of vertical wafers 14. The cutaway view is taken longitudinally between the vertical wafers 14-1 and 14-2 such that the side SS of the vertical wafer 14-2 is visible. Representative locations of the non-high speed terminals 18 for each horizontal wafer 12-1-12-4 are apparent in this view, as is the representative engagement of each horizontal wafer 12-1-12-4 with a separate landing step 44-1-44-4 on the stepped configuration of the vertical wafer 14-2. Body portions 42B of the vertical terminals 42 in the vertical wafer 14-2 are also shown in this view, which further shows the termination of each terminal 42 at a tip portion 42T that can ultimately engage a defined location on an electrical circuit board (or another similar type of structure).

[0046] 19, an isometric view of a representative insulating housing 11 and a number of horizontal wafers 12 is shown with arrows indicating the direction in which the horizontal wafers 12 may be positioned within the housing 11. More specifically, a representative front edge 22 of a frame 20 forming the horizontal wafer 12 may be inserted into a rear opening of the housing 11, with a rear edge 24 of the horizontal frame 20 positioned to ultimately align with a rear edge 11B of the housing 11 when the horizontal wafer 12 is fully inserted. Cables 26 carrying signal paths associated with the high speed terminals 16 may exit the horizontal wafer 12 along a set of rear edges 24 as shown. A recessed rear edge 28 of the horizontal wafer 12 may remain exposed at this point in the assembly, allowing the parallel collection of vertical wafers 14 to engage the non-high speed terminals 18 of the horizontal wafer 12. In fact, FIG. 20 illustrates a subsequent step in a typical assembly process in which the parallel collection of vertical wafers 14 may be inserted into the open area between the rear edges 24 of the frame 20 (of the horizontal wafers 12) and mated with the recessed rear edges 28 of the frame 20 in the manner previously described to provide electrical connection between the non-high speed terminals 18 of the horizontal wafers 12 and an external structure (e.g., an electrical circuit board).

[0047] FIG. 21 shows a representative isometric view of the electrical connector assembly 10 showing the vertical wafers 14 connected to the horizontal wafers 12 within the insulating housing 11. In this view, tie bars 70 may be used to secure the parallel grouping of the vertical wafers 14. Also shown in this view are aligned openings 11c formed in the insulating housing 11 (openings 11c are best shown in FIGS. 19 and 20), as well as optional locating pins 80 that may pass through the clustered openings 46 of the vertical wafers 14. The interconnection of the horizontal wafers 12 and vertical wafers 14 as previously described herein provides a path for transmitting non-high data rate signals (either signals at lower data rates or lower power signals) without interfering with the paths used for transmitting high data rate signals.

[0048] 22 is a cutaway side view of an exemplary combination of a horizontal wafer 12 and a side-by-side collection of vertical wafers 14A. In this embodiment, each vertical wafer 14A may include a set of non-high speed terminals 100 that cannot exit through the bottom edge of the vertical wafer (compared to the vertical connectors 42 described above). Instead, the non-high speed terminals 100 are contained within each vertical wafer 14 and remain in substantially the same horizontal plane, as well as the positioning of the high speed signal paths shown to be housed within the cables 26 in the view of FIG. 22, and exit at the rear of the connector assembly 10.

[0049] Referring to FIG. 23, a representative exploded isometric view of an alternative electrical connector assembly 10A is shown. In this embodiment, only a pair (e.g., two) of horizontal wafers 12A are provided (in some cases, the pair of horizontal wafers may correspond to the "top" horizontal wafer 12-1 and the "bottom" horizontal wafer 12-4 of the arrangement described above). The horizontal wafer 12A may include a set of five non-high speed terminals 18. Thus, a similar parallel collection of five individual vertical wafers 14 may be connected to the pair of horizontal wafers 12A to form the required non-high speed interconnections. In this embodiment, when the wafers 12A, 14 are bonded together, the lower horizontal wafer 12-1 may be positioned on the lowest landing step 44-1 of each vertical wafer 14, and the upper horizontal wafer 12-4 may be positioned on the highest landing step 44-4 of each vertical wafer 14. FIG. 23 shows only one alternative, but an assembly using a set of three horizontal wafers, for example, is another possible assembly configuration.

[0050] As can be appreciated from the above description, in certain embodiments, the housing is configured to support a plurality of horizontal wafers that engage a plurality of vertical wafers, with high speed signals extending behind the horizontal wafers via cables while non-high speed signals are directed downwardly towards the supporting substrate via vertical terminals that engage the substrate via any desired mounting means such as, but not limited to, press-fit or SMT mounting. Additionally, the horizontal non-high speed terminals in the horizontal wafers engage with the vertical terminals in the vertical wafers.

[0051] It will be understood that the foregoing description provides examples of electrical connector assemblies of the present disclosure. However, it is contemplated that other implementations of the present disclosure may differ in detail from the foregoing examples. Any reference to the present disclosure or its examples is intended to refer to the specific example described at the time, and is not intended to imply any limitation on the scope of the disclosure more generally. The recitation of ranges of values ​​herein is intended merely to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise stated herein, and each separate value is incorporated into the specification as if it were individually set forth herein.

[0052] Accordingly, this disclosure includes all modifications and equivalents of the subject matter recited in the claims appended hereto as permitted by applicable law. Moreover, any combination of the above-described elements in all possible variations thereof is encompassed by this disclosure unless otherwise indicated herein or otherwise clearly contradicted by context. Moreover, the advantages described herein may not be applicable to all embodiments encompassed by the claims.

[0053] While benefits, advantages, and solutions have been described above with respect to particular embodiments of the present invention, it is to be understood that such benefits, advantages, and solutions, and any elements which cause or may cause such benefits, advantages, or solutions to be more pronounced, are not to be construed as critical, necessary, or essential features or elements of any or all claims appended to or arising from this disclosure.

Claims

1. 1. An electrical connector assembly comprising: Housing and a plurality of horizontal wafers positioned within the housing, each horizontal wafer comprising: a pair of high speed terminals connected to the pair of conductors, the high speed terminals being configured to transmit signals at a high data rate; a plurality of non-high speed terminals configured for powering and signaling at a low data rate, the high speed terminals and the non-high speed terminals comprising aligned contacts adjacent a front edge of the horizontal wafer and terminal bodies extending rearward of the contacts, the high speed terminals being terminated to conductors in a cable, the cable extending from a rear edge of the horizontal wafer, and the non-high speed terminals being configured to terminate as exposed ends at a recessed rear edge of the horizontal wafer; a ground shield portion above or below a portion of the terminal body of the high speed terminal; A plurality of vertical wafers, the plurality of vertical wafers being positioned in a parallel arrangement, each vertical wafer comprising:

1. An electrical connector assembly comprising: a plurality of vertical wafers comprising a plurality of vertical terminals, each vertical terminal having a contact portion, an end portion and a body portion therebetween, each contact portion configured to mate with an end portion of a respective non-high speed terminal at a recessed rear edge of the plurality of horizontal wafers, the end portion of each vertical terminal having a press-fit end portion or a Surface-Mount-Technology (SMT) end portion.

2. 2. The electrical connector assembly of claim 1, wherein each vertical wafer is configured as a stepped structure and includes a plurality of separate landing steps exposing a contact portion of each vertical terminal, the plurality of separate landing steps being at least sufficient to support a plurality of horizontal wafers in a one-to-one relationship, each exposed contact portion extending from the recessed rear side edge.

3. 1. An electrical connector assembly comprising a housing, a plurality of horizontal wafers, and a plurality of vertical wafers, Each horizontal wafer is A frame, a high speed terminal configured to transmit signals at a high data rate and supported by the frame; a non-high speed terminal supported by the frame, the non-high speed terminal configured to provide power and signal transmission at a low data rate; the high speed terminals and the non-high speed terminals include contacts aligned in a row adjacent a front edge of the horizontal wafer and terminal bodies extending rearward of the contacts, the high speed terminals are connected to cables extending beyond a rear edge of the horizontal wafer, and the non-high speed terminals are configured to terminate in exposed ends at an inner edge somewhat recessed from the rear edge; The plurality of vertical wafers are positioned in a parallel manner, each vertical wafer comprising: A frame, a terminal including a contact portion, an end portion and a body portion therebetween; the contact portions are configured to mate with distal ends of respective non-high speed terminals at inner edges of the horizontal wafer; a vertical wafer of the plurality of vertical wafers corresponds to each non-high speed terminal of a respective horizontal wafer of the plurality of horizontal wafers; each horizontal wafer of the plurality of horizontal wafers has the same number of non-high speed terminals; Electrical connector assembly.

4. 4. The electrical connector assembly of claim 3, wherein the electrical connector assembly is configured to support high data rates of 50 Gigabits per second (Gbps).

5. The electrical connector assembly of claim 4 , wherein the electrical connector assembly is configured to support a high data rate of 100 Gbps.

6. 4. The electrical connector assembly of claim 3, wherein at least one contact portion of the terminal of the vertical wafer comprises a C-clamp structure.

7. 4. The electrical connector assembly of claim 3, further comprising a support and stabilization element configured to span across and capture the plurality of vertical wafers to support and stabilize the parallel array.

8. 1. A horizontal wafer for use in an electrical connector assembly, the horizontal wafer comprising: a frame constructed from an insulating material, the frame having a front edge and an opposing rear edge; a plurality of high speed terminals supported by the frame and configured for signal transmission at high data rates, each high speed terminal including a contact end portion exposed at a front edge of the frame and a distal end portion terminated to a conductor of a twinaxial cable, the twinaxial cable extending from a rear edge of the frame, a body portion and a distal end portion of each high speed terminal being embedded within an insulating material of the frame; a plurality of non-high speed terminals supported by the frame and configured to transmit signals at a low data rate; the plurality of non-high speed terminals are aligned with the plurality of high speed terminals, each non-high speed terminal including a contact portion exposed at a front edge of the frame and a terminal end portion exposed at a recessed rear edge, and a body portion of each non-high speed terminal is embedded within the frame; Horizontal wafer.

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