Reduced Bandwidth Tessellation Factor

Abstract

The graphics pipeline reduces the number of tessellation coefficients written to and read from graphics memory. The hull shader stage detects whether at least a threshold percentage of tessellation coefficients for thread groups of a patch are the same and whether at least a threshold percentage of tessellation coefficients for thread groups of a patch have the same value indicating whether multiple patches are culled or multiple patches are passed to a tessellator stage of the graphics pipeline. In response to detecting that at least a threshold percentage of tessellation coefficients for thread groups are the same, the hull shader stage bypasses writing at least some of the tessellation coefficients for thread groups of a patch to graphics memory, thereby reducing bandwidth and increasing efficiency of the graphics pipeline.

Description

[Background technology]

[0001] A graphics processing unit (GPU) processes three-dimensional (3-D) graphics using a graphics pipeline that is made up of a sequence of programmable shaders and fixed-function hardware blocks. For example, a 3-D model of an object visible in a frame may be represented by a set of triangles, other polygons, or patches that are processed in the graphics pipeline to generate pixel values ​​for display to a user. The triangles, other polygons, or patches are collectively referred to as primitives. This process includes mapping tessellation coefficients onto primitives to represent finer levels of detail, indicated by tessellation coefficients that specify the granularity of the primitives generated by the tessellation process. The GPU includes a dedicated memory that is used to store tessellation coefficients so that the tessellation coefficients are available for mapping onto primitives being processed in the graphics pipeline. The tessellation coefficients stored in the dedicated GPU memory are populated by generating data procedurally. Typically, the dedicated GPU memory is a relatively small memory, so there is a limit to the amount of tessellation coefficients that the dedicated GPU memory can store. Furthermore, the overhead required to write tessellation coefficients to memory and the overhead required to read tessellation coefficients from memory can be significant.

[0002] The present disclosure can be better understood, and its numerous features and advantages made apparent to those skilled in the art by reference to the following drawings, in which: The use of the same reference numbers in different drawings indicates similar or identical items. [Brief description of the drawings]

[0003] [Figure 1]FIG. 1 is a block diagram of a processing system including a graphics processing unit (GPU) for generating visual images for output to a display, according to some embodiments. [Diagram 2] FIG. 1 illustrates a graphics pipeline capable of processing high-order geometry primitives to generate rasterized images of three-dimensional (3D) scenes while storing and retrieving a reduced amount of tessellation coefficients in memory, in accordance with some embodiments. [Diagram 3] FIG. 4 illustrates a hull shader of the graphics pipeline of FIG. 2 bypassing (omitting) writing tessellation factors to memory and sending an indication to a patch fetcher of the graphics pipeline in response to detecting that at least a threshold percentage of tessellation factors for a thread group have values ​​that indicate that patches of the thread group are culled, in accordance with some embodiments. [Figure 4] FIG. 4 illustrates a hull shader of the graphics pipeline of FIG. 2 bypassing writing of tessellation coefficients to memory and sending an indication to a patch fetcher of the graphics pipeline in response to detecting that at least a threshold percentage of tessellation coefficients for a thread group have values ​​that indicate that a patch of the thread group is to be passed to a tessellator stage of the graphics pipeline, in accordance with some embodiments. [Diagram 5] FIG. 3 illustrates a hull shader of the graphics pipeline of FIG. 2 writing a single instance of a tessellation factor to memory and sending an indication to a patch fetcher of the graphics pipeline that the single tessellation factor is applied to all tessellation coefficients for the patch, in accordance with some embodiments. [Figure 6] FIG. 13 illustrates multiple tessellation factors for a patch packaged into a single word, according to some embodiments. [Figure 7]1 is a flowchart illustrating a method for bypassing writing at least a portion of tessellation coefficients to memory in accordance with some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0004] A graphics pipeline for processing three-dimensional (3-D) graphics consists of a sequence of fixed-function hardware block arrays supported by programmable shaders and memory. These configurations are typically defined by a graphics application programming interface (API) processing order, such as that defined in the Direct 3D 11, Microsoft DX 11 / 12, or Khronos Group OpenGL / Vulkan API specifications. An example of a graphics pipeline includes a geometry front-end implemented using vertex and hull shaders that operate on high-order primitives such as patches that represent a 3D model of a scene.

[0005] The geometry front end provides high-order primitives, such as surface patches, and tessellation coefficients generated by the hull shader to a tessellator, which in some embodiments is implemented as a fixed-function hardware block. Tessellation allows for dynamic addition and removal of detail to and from a 3D polygonal (3D polygon) mesh based on control parameters. The tessellator generates low-order primitives (triangles, lines, points, etc.) from the input high-order primitives based on tessellation parameters (also referred to herein as tessellation coefficients) that control how fine the 3D polygonal mesh is. This tessellation allows for the generation of smoother surfaces than would be generated by the original 3D polygonal mesh. Low-order primitives, such as polygons, are formed of interconnected vertices. For example, a typical object, such as a mesh, includes multiple triangles formed by three vertices. The low-order primitives are provided to a geometry backend that includes a geometry shader, which replicates, shades, or subdivides the low-order primitives, such as the ability to generate large amounts of hair.

[0006] The vertices of primitives generated by the portion of the graphics pipeline that processes geometry workloads in object space are then provided through portions that process pixel workloads in image space (e.g., primitive, vertex, and index buffers, as well as cache memory buffers). The pixel portion includes configurations of fixed-function hardware combined with programmable pixel shaders that perform culling, rasterization, depth testing, color blending, etc. on the primitives to generate fragments or pixels from the input geometry primitives. Fragments are individual pixels, or in some cases sub-pixels. The programmable pixel shaders then shade the fragments and merge them with the scene frame image for display.

[0007] 1-7 disclose systems and techniques for improving efficiency and bandwidth of a graphics processing pipeline. In some embodiments, a method for bypassing writing tessellation coefficients to and reading tessellation coefficients from graphics memory includes detecting, in a hull shader of a graphics processing pipeline of a graphics processing unit (GPU), whether all tessellation coefficients for a patch, or at least a threshold percentage of tessellation coefficients for all patches in a thread group, are the same value, and whether at least the threshold percentage of tessellation coefficients indicate whether the thread group's patches are to be culled or whether the thread group's patches are to be passed to a tessellator. If at least the threshold percentage of tessellation coefficients for a thread group indicate that the thread group's patches are to be culled (referred to herein as having a tessellation coefficient with a value of 0), the hull shader bypasses writing tessellation coefficients to graphics memory and sends a message to a patch fetcher indicating that the tessellation coefficients for the thread group are to be discarded. In response to receiving the message, the patch fetcher bypasses reading tessellation factors for the thread group from the graphics memory and discards the patches for the thread group.

[0008] If the hull shader determines that at least a threshold percentage of the tessellation coefficients for a thread group indicate that the thread group's patches are to be passed to the tessellator stage (referred to herein as having a tessellation coefficient with a value of one), the hull shader bypasses writing the tessellation coefficients for the thread group to graphics memory and sends a message to the patch fetcher indicating that all tessellation coefficients for the thread group indicate that the thread group's patches are to be passed to the tessellator stage. In response to receiving the message, the patch fetcher bypasses reading the tessellation coefficients from graphics memory and provides the thread group's patches to the tessellator stage.

[0009] In some embodiments, if the hull shader determines that at least a threshold percentage of the tessellation factors for a thread group have values ​​that are equal to one another but not equal to 0 or 1, the hull shader writes a single instance of the value of the tessellation factor to memory and sends a message to the patch fetcher indicating that the single value of the tessellation factor stored in the graphics memory is applied to all tessellation factors for the patches of the thread group. In response to receiving the message, the patch fetcher reads the single tessellation factor from the graphics memory and applies the single tessellation factor to each of the batches in the thread group before providing the patches to the tessellator.

[0010] If the tessellation coefficients for a patch of a thread group do not have equal values ​​to each other, in some embodiments, the hull fetcher performs integer compression and writes the compressed tessellation coefficients for the patch in a single word to the graphics memory. For example, an isoline patch is associated with two tessellation coefficients. Thus, in some embodiments, the hull fetcher writes both tessellation coefficients for the isoline patch in a single word to the graphics memory. Similarly, a triangle patch is associated with four tessellation coefficients. In some embodiments, the hull fetcher writes all four tessellation coefficients associated with the triangle patch in a single word to the graphics memory. A quad patch is associated with six tessellation coefficients. In some embodiments, the hull fetcher writes the first three tessellation coefficients associated with the quad patch in a first single word to the graphics memory and the remaining three tessellation coefficients associated with the quad patch in a second single word to the graphics memory.

[0011] Each patch primitive type (e.g., isoline, triangle, quad) is associated with two, four, or six tessellation factors. In particular, for tessellation factors of 0 or 1, more bandwidth may be consumed writing the tessellation factors to and reading them from graphics memory than is saved by reducing the granularity of the tessellation primitives generated using the tessellation factors. The graphics processing pipeline improves GPU bandwidth and efficiency by reducing the amount of data written to and read from graphics memory.

[0012] 1 is a block diagram of a processing system 100 for implementing reduced bandwidth tessellation factors, according to some embodiments. The processing system 100 includes a central processing unit (CPU) 102, a system memory 104, a graphics processing subsystem 106 including a graphics processing unit (GPU) 108, and a display device 110 communicatively coupled to each other by a system data bus 112. As shown, the system data bus 112 connects the CPU 102, the system memory 104, and the graphics processing subsystem 106. In other embodiments, the system memory 104 connects directly to the CPU 102. In some embodiments, the CPU 102, a portion of the graphics processing subsystem 106, the system data bus 112, or any combination thereof, are integrated into a single processing unit. Additionally, in some embodiments, the functionality of the graphics processing subsystem 106 is included in a chipset or some other type of special purpose processing unit or co-processor.

[0013] CPU 102 executes program instructions stored in system memory 104, manipulates data stored in system memory 104, and sends instructions and / or data (e.g., work or tasks to be completed) to graphics processing unit 108 for completion, which forms part of graphics processing subsystem 106 for completing work. In some embodiments, system memory 104 includes dynamic random access memory (DRAM) for storing programming instructions and data for processing by CPU 102 and graphics processing subsystem 106.

[0014] In various embodiments, the CPU 102 sends instructions intended for processing on the GPU 108 to a command buffer. In some embodiments, the command buffer is in system memory 104, for example, coupled to system data bus 112. In other embodiments, the CPU 102 sends graphics commands intended for the GPU 108 to another memory communicatively coupled to system data bus 112. The command buffer temporarily stores a stream of graphics commands that includes input to the GPU 108. The stream of graphics commands includes, for example, one or more command packets and / or one or more state update packets. In some embodiments, the command packets include drawing commands (also interchangeably referred to as "draw calls") that instruct the GPU 108 to perform operations on image data that is to be output for display. For example, the drawing commands instruct the GPU 108 to render pixels determined by a group of one or more vertices stored in memory (e.g., defined in a vertex buffer). In some embodiments, the geometry determined by a group of one or more vertices corresponds to a number of primitives to be rendered.

[0015] GPU 108 receives and processes work sent from CPU 102. For example, in various embodiments, GPU 108 processes the work to render and display graphics images on display device 110, such as by using one or more graphics pipelines 114. Graphics pipelines 114 include fixed-function stages and programmable shader stages. Fixed-function stages include typical hardware stages included in a fixed-function pipeline of a GPU. Programmable shader stages include streaming multiprocessors. Each streaming multiprocessor can execute a relatively large number of threads simultaneously. Furthermore, each streaming multiprocessor can be programmed to perform processing tasks related to a wide variety of applications, including, but not limited to, linear and nonlinear data transformations, filtering of video and / or audio data, modeling operations (e.g., applying physics to determine object position, velocity, and other attributes), and the like. In other embodiments, graphics processing subsystem 106 is used for non-graphics processing.

[0016] As shown, the system memory 104 includes an application program 116 (e.g., an operating system or other application), an application programming interface (API) 118, and a GPU driver 120. The application program 116 generates calls to the API 118 to generate a desired set of results, typically in the form of a series of graphics images. The graphics processing subsystem 106 includes a GPU data bus 122 that communicatively couples the GPU 108 to a graphics memory 124. In various embodiments, the GPU uses the graphics memory 124 and the system memory 104 in any combination for memory operations. The CPU 102 allocates portions of these memories to the GPU 108 to perform work. For example, in various embodiments, the GPU 108 receives instructions from the CPU 102, processes the instructions to render graphics data and images, and stores the images in the graphics memory 124. The GPU 108 then displays the graphics images stored in the graphics memory 124 on the display device 110. The graphics memory 124 stores data and programming used by the GPU 108. As shown in FIG. 1, graphics memory 124 includes a frame buffer 126 that stores data for driving display device 110 .

[0017] In various embodiments, the GPU 108 includes one or more computational units, such as one or more processing cores 128 including one or more processing units 130 that execute threads concurrently with execution of other threads in a wavefront, for example according to a single instruction, multiple data (SIMD) execution model. The processing units 130 are also referred to interchangeably as "SIMD units." The SIMD execution model is a model in which multiple processing elements share a single program control flow unit and program counter to execute the same program, but may execute the program with different data. The processing cores 128 of the GPU 108 are also referred to interchangeably as shader cores or streaming multiprocessors (SMX). The number of processing cores 128 implemented in the GPU 108 is a matter of design choice.

[0018] Each of the one or more processing cores 128 executes a respective instantiation of a particular work item to process input data. Here, the basic unit of execution in the one or more processing cores 128 is a work item (e.g., a thread). Each work item represents a single instantiation of a collection of parallel executions of kernels invoked on the device, for example, by commands executed in parallel. Work items are executed by one or more processing elements as part of a thread group (e.g., a work group) that executes on the processing core 128. In various embodiments, the GPU 108 issues and executes on a single processing unit 130. Multiple wavefronts are included in a "thread group" that includes a collection of work items designated to execute the same program. A thread group is executed by executing each of the wavefronts that make up the thread group. In some embodiments, the wavefronts are executed sequentially on a single processing unit 130 or partially or fully in parallel on different SIMD units. In other embodiments, all wavefronts from a thread group are processed on the same processing core 128. A wavefront is also referred to interchangeably as a warp, vector, or thread. In some embodiments, wavefronts include instances of parallel execution of shader programs, with each wavefront including multiple work-items executing simultaneously on a single processing unit 130 (e.g., one instruction control unit executing the same stream of instructions on multiple data) according to the SIMD paradigm. Scheduler 132 performs operations related to scheduling several wavefronts on different processing cores 128 and processing units 130, and performing other operations for orchestrating several tasks on the graphics processing subsystem 106.

[0019] The parallel processing provided by one or more processing cores 128 is suitable for graphics-related operations such as pixel value calculations, vertex transformations, tessellation, geometry shading operations, and other graphics operations. The graphics pipeline 114 receives graphics processing commands from the CPU 102 and provides computational tasks accordingly to one or more processing cores 128 for execution in parallel. Some graphics pipeline operations, such as pixel processing and other parallel computational operations, require the same command stream or computation kernel to be executed on a stream or collection of input data elements. To process such data elements in parallel, respective instantiations of the same computation kernel are executed simultaneously on multiple processing units 130 in one or more processing cores 128. As described herein, for example, a computation kernel is a function that includes instructions that are declared in a program and executed on the processing cores 128. The function may also be referred to as a kernel, a shader, a shader program, or a program.

[0020] As described in more detail below with respect to FIG. 2, the GPU 108 includes a graphics pipeline 114 that reduces the number of tessellation coefficients written to and read from the graphics memory 124. Abstract patch types include isolines, triangles, and quads. An isoline patch is a horizontal line determined by two tessellation coefficients. A triangle patch is a triangle determined by three outer tessellation coefficients and one inner tessellation coefficient for a total of four tessellation coefficients. A quad patch is a square determined by four outer tessellation coefficients and two inner tessellation coefficients for a total of six tessellation coefficients. In some embodiments, each tessellation coefficient includes 32 bits. Thus, writing all tessellation coefficients for all patches of a thread group to the graphics memory 124 and reading all tessellation coefficients for patches of a thread group from the graphics memory 124 consumes significant bandwidth. Graphics pipeline 114 detects whether at least a threshold percentage of tessellation factors for the thread groups of the patch are the same, and in some embodiments, whether at least a threshold percentage of tessellation factors for the thread groups of the patch are 0 (i.e., indicating that the patch is culled) or 1 (i.e., indicating that the patch is passed to a tessellator stage of graphics pipeline 114). In some embodiments, the threshold is programmable and set to a relatively high value, such as 98%. In response to detecting that the threshold percentage of tessellation factors for the thread groups are the same (or, additionally, in some embodiments, the threshold percentage of tessellation factors are 0 or 1), graphics pipeline 114 bypasses writing to and reading from graphics memory 124 at least a portion of the tessellation factors for the thread groups of the patch, thereby reducing bandwidth and increasing efficiency of graphics pipeline 114.

[0021] FIG. 2 illustrates a graphics pipeline capable of processing high-order geometry primitives to generate rasterized images of three-dimensional (3D) scenes while storing and retrieving a reduced amount of tessellation coefficients in and from memory, according to some embodiments. FIG. 2 illustrates various elements and pipeline stages associated with a GPU. In some embodiments, the graphics pipeline includes other elements and stages not illustrated in FIG. 2. It should also be noted that FIG. 2 is merely a schematic diagram, and that, for example, in some embodiments, the illustrated functional units and pipeline stages actually share hardware circuitry, even though they are illustrated diagrammatically as separate stages in FIG. 2. It should also be understood that each stage, element, and unit of the graphics processing pipeline 200 is implemented as necessary and accordingly includes, for example, appropriate circuitry and / or processing logic for performing the associated operations and functions.

[0022] In various embodiments, graphics processing pipeline 200 is configured to render graphics as images that depict a scene having three-dimensional geometry in a virtual space (sometimes referred to herein as "world space"), but potentially two-dimensional geometry. Graphics processing pipeline 200 generally receives a representation of a three-dimensional scene, processes the representation, and outputs a two-dimensional raster image. These stages of graphics processing pipeline 200 initially process data that is properties at the endpoints (or vertices) of geometric primitives. Primitives provide information about the object being rendered. Common primitives for three-dimensional graphics include triangles and lines. The vertices of these geometric primitives provide information about, for example, xyz coordinates, texture, and reflectance.

[0023] Throughout graphics processing pipeline 200, data is read from and written to one or more memory units. These memory units are generally shown in FIG. 2 as graphics memory 210. Graphics memory 210 includes a hierarchy of one or more memories or caches used to implement buffers and store tessellation coefficients, vertex data, texture data, etc. Graphics memory 210 is implemented using some embodiments of system memory 104 shown in FIG. 1.

[0024] Graphics memory 210 includes video memory and / or hardware state memory, including various buffers and / or graphics resources utilized in the rendering pipeline. In various embodiments, one or more individual memory units of graphics memory 210 are embodied as one or more video random access memory unit(s), one or more caches, one or more processor registers, etc., depending on the nature of the data at a particular stage in the rendering. Graphics memory 210 is therefore understood to refer to any processor-accessible memory utilized in graphics processing pipeline 200. A processing unit, such as a dedicated GPU, is configured to perform various operations in the pipeline and read / write to graphics memory 210 accordingly.

[0025] The initial stages of graphics processing pipeline 200 include operations performed in world space and then transformed into screen space where the scene is rasterized and transformed into a set of discrete image elements suitable for output on a pixelated display device. Throughout graphics processing pipeline 200, various resources contained in graphics memory 210 are utilized by the pipeline stages, and inputs and outputs to the stages are temporarily stored in buffers contained in graphics memory 210 before the final values ​​of the image are determined.

[0026] The input assembler stage 220 is configured to access information from the graphics memory 210 that is used to determine objects that represent portions of a model of a scene. For example, in various embodiments, the input assembler stage 220 reads primitive data (e.g., points, lines, and / or triangles) from a user-filled buffer and assembles the data into primitives that are used by other pipeline stages of the graphics processing pipeline 200. As used herein, the term "user" refers to an application program 116 or other entity that provides shader code and three-dimensional objects to the graphics processing pipeline 200 for rendering. The input assembler stage 220 assembles vertices into several different primitive types (such as line lists, triangle strips, or adjacent primitives) based on the primitive data contained in the user-filled buffer and formats the assembled primitives for use by the rest of the graphics processing pipeline 200.

[0027] In various embodiments, graphics processing pipeline 200 manipulates one or more virtual objects determined by a set of vertices set up in world space and having geometry defined in terms of coordinates in a scene. For example, input data utilized by graphics processing pipeline 200 may include a polygonal mesh model of scene geometry whose vertices correspond to primitives processed in a rendering pipeline in accordance with aspects of the present disclosure, and initial vertex geometry is set up in graphics memory in an application stage executed by the CPU.

[0028] The vertex processing stage 230 includes various calculations for processing the vertices of an object in a world space geometry. In some embodiments, the vertex processing stage 230 includes a vertex shader stage 232 that performs vertex shader calculations that manipulate various parameter values ​​of the vertices in the scene, such as position values ​​(e.g., XY coordinates and Z depth values), color values, lighting values, texture coordinates, etc. Preferably, the vertex shader calculations are performed by one or more programmable vertex shaders 232. The vertex shader calculations are performed uniquely for each zone that an object overlaps, and the object's zone index is utilized in vertex shading to determine the rendering context and associated parameters that the object uses and how the vertex values ​​should be manipulated accordingly upon subsequent rasterization. In various embodiments, the vertex shader stage 232 is implemented in software and logically receives as input a single vertex of a primitive and outputs a single vertex. Some embodiments of the vertex shader perform single instruction multiple data (SIMD) processing to allow multiple vertices to be processed simultaneously.

[0029] Vertex processing stage 230 also optionally includes additional vertex processing calculations that subdivide primitives and generate new vertices and new geometry in world space. In the illustrated embodiment, vertex processing stage 230 includes a vertex shader stage 232, a hull shader stage 233, a patch fetcher 234, a tessellator stage 235, a domain shader stage 236, and a geometry shader stage 237. Hull shader stage 233 operates on input high-order patches or control points that are used to determine input patches. Hull shader stage 233 outputs tessellation coefficients and other patch data. Primitives generated by hull shader stage 233 may be provided to tessellator stage 235 by patch fetcher 234. The tessellator stage 235 receives objects (e.g., patches) from the hull shader stage 233 and generates information identifying primitives that correspond to the input objects, e.g., by tessellating the input objects based on tessellation factors provided to the tessellator stage 235 by the hull shader stage 233. Tessellation subdivides input high-order primitives, such as patches, into a set of lower-order output primitives that represent finer levels of detail, e.g., as indicated by tessellation factors that specify the granularity of the primitives produced by the tessellation process. Thus, a model of a scene can be represented with a smaller number of high-order primitives (to save memory or bandwidth), and further detail can be added by tessellating the higher-order primitives.

[0030] The domain shader stage 236 inputs a domain location and, in some embodiments, other patch data. The domain shader stage 236 operates on the information provided and generates a single vertex for output based on the input domain location and other information. The geometry shader stage 237 receives an input primitive and outputs up to four primitives generated by the geometry shader stage 237 based on the input primitive. In some embodiments, the geometry shader stage 237 takes vertex data from the graphics memory 210 and generates new graphics primitives, such as lines and triangles, from the vertex data in the graphics memory 210. Specifically, the geometry shader stage 237 takes the vertex data of primitives together and generates zero or more primitives. For example, the geometry shader stage 237 may operate on a triangle primitive with three vertices.

[0031] Upon completion of the vertex processing stage 230, the scene is defined by a set of vertices, each having a set of vertex parameter values ​​stored in the graphics memory 210. In a particular embodiment, the vertex parameter values ​​output from the vertex processing stage 230 include positions determined in homogeneous coordinates that differ for each zone.

[0032] Next, the graphics processing pipeline 200 proceeds to a rasterization stage 240, where shading operations and other operations such as clipping, perspective dividing, scissoring, viewport selection, etc. are performed. In various embodiments, the rasterization stage 240 converts the scene geometry into screen space and a set of discrete image elements (e.g., pixels as used in the graphics processing pipeline, although it should be noted that the term pixel does not necessarily imply that a pixel corresponds to a display pixel value in the final display buffer image). The virtual space geometry is converted to screen space geometry by an operation that computes the projection of objects and vertices from a world space of objects and vertices onto a display window (or "viewport") of the scene, which is composed of a number of discrete screen space pixels sampled by the rasterizer. According to aspects of the present disclosure, the screen region includes a number of distinct zones with different rendering parameters. The rendering parameters include different rasterization parameters for each zone.

[0033] The illustrated rasterization stage 240 includes a primitive assembly stage 242 that sets up primitives defined by each set of vertices in the scene. Each vertex is defined by a vertex index, and each primitive is defined in terms of these vertex indices and stored in an index buffer in the graphics memory 210. Primitives must include triangles defined by at least three vertices, but may also include point primitives, line primitives, and other polygons. During the primitive assembly stage 242, certain primitives are culled. For example, primitives whose vertex indices and homogeneous coordinate space positions indicate a particular winding order are considered to be back-facing and are therefore culled from the scene. The primitive assembly stage 242 also includes a screen space transformation for primitive vertices, which may include different screen space transformation parameters for each zone of the screen region.

[0034] The rasterization stage 240 performs clipping, perspective division, transforms points to homogeneous space, and maps vertices to the viewport. The raster data is snapped to integer positions, they are culled and clipped (to draw the minimum number of pixels), and per-pixel attributes are interpolated (from the per-vertex attributes). Thus, the rasterization stage 240 determines which pixel primitives overlap, clips primitives, prepares primitives for the pixel shader, and decides how to call the pixel shader stage 250.

[0035] In a conventional geometry pipeline, the hull shader stage 233 writes all tessellation coefficients for all patches to the graphics memory 210, and the patch fetcher 234 reads all tessellation coefficients for all patches from the graphics memory 210. This can result in wasted computing resources and processing bottlenecks. For example, there are frequent large runs where all of the tessellation coefficients are the same or a high percentage of the tessellation coefficients are the same. The hull shader stage 233 detects whether at least a threshold percentage of the tessellation coefficients for the thread groups of the patches are the same. If at least a threshold percentage of the tessellation coefficients for the thread groups are the same, in some embodiments, the hull shader stage 233 further detects whether at least a threshold percentage of the tessellation coefficients for the thread groups indicate that the patches of the thread groups are to be culled (e.g., have a value of 0) or that the patches of the thread groups are to be passed to the tessellator stage 235 (e.g., have a value of 1). In response to detecting that at least a threshold percentage of the tessellation coefficients for the thread groups are the same, hull shader stage 233 bypasses writing at least some of the tessellation coefficients to graphics memory 210. For example, in response to detecting that at least a threshold percentage of the tessellation coefficients for the thread groups of a patch all have the same value of 0 or 1, hull shader stage 233 sends a message to patch fetcher 234. Hull shader stage 233 bypasses writing the tessellation coefficients to graphics memory 210, and patch fetcher 234 bypasses reading the tessellation coefficients from graphics memory 210 in response to receiving the message.In response to detecting that at least a threshold percentage of the tessellation factors for the thread group are the same but not equal to 0 or 1, hull shader stage 233 writes a single instance of the value of the majority of the tessellation factors to graphics memory 210 and sends a message to patch fetcher 234 indicating that the single value of the tessellation factor stored in graphics memory 210 applies to all patches of the thread group.

[0036] 3 illustrates hull shader stage 233 of the graphics pipeline of FIG. 2 bypassing writing tessellation coefficients to graphics memory 210 and sending an indication to patch fetcher 234 of the graphics pipeline that all tessellation coefficients for a thread group have values ​​indicating that the thread group's patches are culled, in accordance with some embodiments. In response to hull shader stage 233 detecting that at least a threshold percentage of tessellation coefficients for the thread group's patches have values ​​indicating that the thread group's patches are culled (e.g., have a value of 0), hull shader stage 233 bypasses writing tessellation coefficients for the thread group to graphics memory 210. Hull shader stage 233 also sends a message 302 to patch fetcher 234 indicating that all tessellation coefficients for all patches of the thread group have values ​​indicating that the thread group's patches are culled (e.g., equal to 0). In response to receiving message 302, patch fetcher 234 bypasses reading tessellation factors for the thread group from graphics memory 210. Because a tessellation factor of 0 culls a patch, patch fetcher 234 further discards the thread group's patch rather than passing it to a tessellator stage (not shown).

[0037] 4 illustrates hull shader stage 233 of the graphics pipeline of FIG. 2 bypassing writing of tessellation coefficients to graphics memory 210 and sending an indication to patch fetcher 234 of the graphics pipeline in response to detecting that at least a threshold percentage of tessellation coefficients for a thread group have a value indicating that the patch for the thread group is passed to a tessellator stage, according to some embodiments. In response to hull shader stage 233 detecting that at least a threshold percentage of tessellation coefficients for a patch for a thread group have a value indicating that the patch for the thread group is passed to a tessellator stage (e.g., have a value of 1), hull shader stage 233 bypasses writing of tessellation coefficients for the thread group to graphics memory 210. Hull shader stage 233 also sends message 402 to patch fetcher 234 indicating that the tessellation coefficients for the patch for the thread group have a value indicating that the patch for the thread group is passed to a tessellator stage (e.g., equal to 1). In response to receiving message 402, patch fetcher 234 bypasses reading tessellation factors for the thread group from graphics memory 210. In addition, patch fetcher 234 unpacks the thread group's patches and passes them to a tessellator (not shown).

[0038] 5 illustrates the hull shader stage 233 of the graphics pipeline of FIG. 2 writing a single instance of a tessellation factor value to graphics memory 210 and sending an indication to the patch fetcher 234 of the graphics pipeline that a single tessellation factor value applies to all tessellation coefficients for a patch, in accordance with some embodiments. In response to detecting that all tessellation coefficients associated with patch 506 have the same value, hull shader stage 233 bypasses writing all tessellation coefficients for the patch to graphics memory 210. Instead, hull shader stage 233 writes a single instance of a tessellation factor 502 to graphics memory 210 and sends a flag 504 to patch fetcher 234 indicating that a single instance of a tessellation factor value applies to all tessellation coefficients corresponding to patch 506. In response to receiving flag 504, patch fetcher 234 reads patch 506 and the single instance of tessellation factor 502 from graphics memory 210. The patch fetcher 234 applies the tessellation coefficients 502 to all tessellation coefficients that correspond to the patch 506 and provides the patch 506 and the tessellation coefficients 502 to a tessellator stage 235, which uses the tessellation coefficients to generate the final primitives.

[0039] FIG. 6 is a diagram illustrating multiple tessellation coefficients for a patch packaged into a single word, according to some embodiments. In some embodiments, the hull shader stage writes the tessellation coefficients to the graphics memory in a 32-bit word. Each tessellation coefficient has a value between 0 and 64. Thus, each tessellation coefficient can be written using 8 bits. To reduce the number of words written to the graphics memory 210 and the number of words read from the graphics memory 210, in some embodiments, the hull shader stage (not shown) packages multiple tessellation coefficients into a single word. For example, an isoline patch has two tessellation coefficients. The hull shader stage writes a single word 601 to the graphics memory (not shown) that includes a first tessellation coefficient TF-1 602 and a second tessellation coefficient TF-2 604 that correspond to the isoline patch. As another example, a triangle patch has four tessellation coefficients. The hull shader stage writes a single word 611 to the graphics memory that includes a first tessellation coefficient TF-1 612, a second tessellation coefficient TF-2 614, a third tessellation coefficient TF-3 616, and a fourth tessellation coefficient TF-4 618 that corresponds to the triangle patch. Similarly, a quad patch has six tessellation coefficients. Because all six 8-bit tessellation coefficients cannot fit in a single 32-bit word, the hull shader stage packages the six tessellation coefficients that correspond to the quad patch into two words. For example, the hull shader stage writes a first word 621 containing a first tessellation coefficient TF-1 622, a second tessellation coefficient TF-2 624, and a third tessellation coefficient TF-3 626, and a second word 627 containing a fourth tessellation coefficient TF-4 628, a fifth tessellation coefficient TF-5 630, and a sixth tessellation coefficient TF-6 632, corresponding to a quad patch, to the graphics memory.In this way, in the hull shader stage, the number of words of tessellation coefficients written to and read from graphics memory is reduced from 2 words to 1 word (for isoline patches), 4 words to 1 word (for triangle patches), and 6 words to 2 words (for quad patches).

[0040] 7 is a flow chart illustrating a method 700 for bypassing writing at least a portion of tessellation coefficients to memory, in accordance with some embodiments. In some embodiments, the method is performed by graphics pipeline 114 of FIG. 1 or graphics processing pipeline 200 of FIG. 2.

[0041] At block 702, the hull shader stage 233 determines whether at least a threshold percentage of tessellation coefficients for all patches of the thread group have equal values. If at block 702 the hull shader stage 233 determines that at least a threshold percentage of tessellation coefficients for all patches of the thread group do not have equal values, method flow continues to block 704. At block 704, the hull shader stage 233 determines whether all tessellation coefficients for the patches of the thread group have equal values. If at block 704 the hull shader stage 233 determines that all tessellation coefficients for the patch do not have equal values, method flow continues to block 706. At block 706, the hull shader stage 233 writes the tessellation coefficients for the patch to the graphics memory 210. In some embodiments, the hull shader stage 233 writes multiple tessellation coefficients corresponding to the patch in a single word. For example, for an isoline patch with two tessellation coefficients, the hull shader stage 233 writes both tessellation coefficients for the isoline patch in a single word. For a triangle patch with four tessellation coefficients, the hull shader stage 233 writes all four tessellation coefficients for the triangle in a single word. For a quad patch with six tessellation coefficients, the hull shader stage 233 writes, for example, the first three tessellation coefficients for the quad patch in a first word and the second three tessellation coefficients for the quad patch in a second word.

[0042] If at block 704, the hull shader stage 233 determines that at least a threshold percentage of the tessellation coefficients for the patch have equal values, method flow continues at block 708. At block 708, the hull shader stage 233 writes the single instance of the tessellation coefficient to graphics memory 210 and sends a flag 504 to the patch fetcher indicating that the single instance of the tessellation coefficient is applied to all tessellation coefficients corresponding to the patch.

[0043] If at block 702, the hull shader stage 233 determines that at least a threshold percentage of the tessellation factors for all patches of the thread group have equal values, the method flow continues to block 710. At block 710, the hull shader stage 233 determines whether at least a threshold percentage of the tessellation factors for all patches of the thread group have values ​​that indicate the patches of the thread group are culled. If at block 710, the hull shader stage 233 determines that at least a threshold percentage of the tessellation factors for all patches of the thread group have values ​​that indicate the patches of the thread group are culled, the method flow continues to block 712. At block 712, the hull shader stage 233 bypasses writing the tessellation factors for the thread group to the graphics memory 210 and sends a message 302 to the patch fetcher 234 indicating that the tessellation factors for the thread group have values ​​that indicate the patches of the thread group are culled. In response to receiving message 302, patch fetcher 234 bypasses reading tessellation factors for the thread group from graphics memory 210 and culls (discards) patches for the thread group.

[0044] If at block 710, the hull shader stage 233 determines that at least a threshold percentage of the tessellation factors for all patches of the thread group do not have values ​​that indicate the patches of the thread group are to be culled, then method flow continues to block 714. At block 714, the hull shader stage 233 determines whether at least a threshold percentage of the tessellation factors for all patches of the thread group have values ​​that indicate the patches of the thread group are to be passed to the tessellator stage 235. If at block 714, the hull shader stage 233 determines that at least a threshold percentage of the tessellation factors for all patches of the thread group have values ​​that indicate the patches of the thread group are to be passed to the tessellator stage 235, then method flow continues to block 716. At block 716, the hull shader stage 233 bypasses writing the tessellation coefficients for the thread group's patches to the graphics memory 210 and sends a message 402 to the patch fetcher 234 indicating that all tessellation coefficients for all patches of the thread group have values ​​indicating that the patches of the thread group are to be passed to the tessellator stage 235. In response to receiving the message 402, the patch fetcher 234 unpacks the patches from the graphics memory 210 and provides the patches to the tessellator stage 235. If at block 714 the hull shader stage 233 determines that at least a threshold percentage of the tessellation coefficients for all patches of the thread group do not have values ​​indicating that the patches of the thread group are to be passed to the tessellator stage 235, method flow continues to block 708. In this case, because the hull shader stage has determined that at least a threshold percentage of the tessellation coefficients for all patches of the thread group have equal values, in block 706 the hull shader stage writes a single instance of the most prevalent tessellator coefficient value to graphics memory 210 and sends a flag 504 to the patch fetcher indicating that the single tessellator coefficient stored in graphics memory 210 applies to all tessellation coefficients for all patches of the thread group.

[0045] A computer-readable storage medium includes any non-transitory storage medium or combination of non-transitory storage media that can be accessed by a computer system during use to provide instructions and / or data to the computer system. Such storage media may include, but are not limited to, optical media (e.g., compact discs (CDs), digital versatile discs (DVDs), Blu-ray discs), magnetic media (e.g., floppy disks, magnetic tape, magnetic hard drives), volatile memory (e.g., random access memory (RAM) or cache), non-volatile memory (e.g., read-only memory (ROM) or flash memory), or micro-electromechanical systems (MEMS) based storage media. The computer-readable storage medium (e.g., system RAM or ROM) may be internal to the computing system, the computer-readable storage medium (e.g., a magnetic hard drive) may be permanently attached to the computing system, the computer-readable storage medium (e.g., an optical disk or Universal Serial Bus (USB)-based flash memory) may be removably attached to the computing system, or the computer-readable storage medium (e.g., network-accessible storage (NAS)) may be coupled to the computer system via a wired or wireless network.

[0046] In some embodiments, some aspects of the above techniques may be implemented by one or more processors of a processing system executing software. The software includes one or more sets of executable instructions stored in or tangibly embodied on a non-transitory computer-readable storage medium. The software may include instructions and specific data that, when executed by one or more processors, operate the one or more processors to perform one or more aspects of the above techniques. The non-transitory computer-readable storage medium may include, for example, a magnetic or optical disk storage device, a solid-state storage device such as a flash memory, a cache, a random access memory (RAM), or one or more other non-volatile memory devices, etc. The executable instructions stored on the non-transitory computer-readable storage medium may be source code, assembly language code, object code, or other instruction formats that can be interpreted or executed by one or more processors.

[0047] In addition to the above, it should be noted that not all activities or elements described in the summary description are required, some of the specific activities or devices may not be required, one or more additional activities may be performed, and one or more additional elements may be included. Furthermore, the order in which the activities are listed is not necessarily the order in which they are performed. Also, the concepts have been described with reference to specific embodiments. However, those skilled in the art will appreciate that various changes and modifications can be made without departing from the scope of the invention as set forth in the claims. Thus, the specification and drawings should be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the invention.

[0048] Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and features from which any benefit, advantage, or solution may arise or be manifested are not to be construed as critical, essential, or essential features of any or all of the claims. Moreover, the specific embodiments described above are illustrative only, as the disclosed invention may be modified and practiced in different but similar manners apparent to those skilled in the art having the benefit of the teachings herein. No limitations are intended to the details of construction or design herein shown, other than as described in the appended claims. It is therefore apparent that the specific embodiments described above may be altered or modified, and all such variations are considered to be within the scope of the disclosed invention. Accordingly, the protection sought herein is set forth in the appended claims.

Claims

1. In response to detecting, in a hull shader stage of a graphics pipeline of a graphics processing unit (GPU), that at least a threshold percentage of tessellation factors corresponding to a plurality of patches in a thread group have the same value, bypassing writing of at least a portion of the tessellation coefficients corresponding to the plurality of patches to a graphics memory of the graphics pipeline. method.

2. in response to detecting, in the hull shader stage, that the tessellation factor of at least a threshold percentage indicates that the plurality of patches are to be culled, sending a message to a patch fetcher of the graphics pipeline indicating that the plurality of patches are to be culled; in the patch fetcher, in response to receiving the message, bypassing reading from the graphics memory the tessellation coefficients corresponding to the plurality of patches; discarding the plurality of patches in the patch fetcher.

2. The method of claim 1.

3. in response to detecting, in the hull shader stage, that at least the threshold percentage of tessellation coefficients corresponding to the plurality of patches indicate that the plurality of patches are to be passed to a tessellator stage of the graphics pipeline, sending a message to a patch fetcher of the graphics pipeline that all of the tessellation coefficients corresponding to the plurality of patches indicate that the plurality of patches are to be passed to a tessellator stage of the graphics pipeline; bypassing writing of the tessellation coefficients to the graphics memory; and in the patch fetcher, in response to receiving the message, bypassing reading from the graphics memory the tessellation coefficients corresponding to the plurality of patches; sending the plurality of patches to the tessellator stage.

2. The method of claim 1.

4. in response to detecting, in the hull shader stage, that at least a threshold percentage of tessellation coefficients corresponding to any of the plurality of patches have the same value that does not indicate that the plurality of patches are to be culled or that the plurality of patches are to be passed to a tessellator stage of the graphics pipeline, writing values ​​of the tessellation coefficients to the graphics memory and sending a flag to a patch fetcher of the graphics pipeline indicating that the value is to be applied to all tessellation coefficients corresponding to the patch; reading, in the patch fetcher, the value from the graphics memory in response to receiving the flag; applying the value to all tessellation coefficients corresponding to the patch.

2. The method of claim 1.

5. and in response to detecting in the hull shader stage that all of the tessellation coefficients corresponding to any one of the plurality of patches are not the same, writing at least one word to the graphics memory, the at least one word including a plurality of tessellation coefficients corresponding to the patch along with an indication that the at least one word includes the plurality of tessellation coefficients.

2. The method of claim 1.

6. the patch comprises an isoline patch and the at least one word comprises two tessellation coefficients; The method of claim 5.

7. the patch comprises a triangular patch, and the at least one word comprises four tessellation coefficients; The method of claim 5.

8. the patch comprises a quadrilateral patch, and the at least one word comprises six tessellation coefficients; The method of claim 5.

9. performing integer compression on the tessellation coefficients to generate compressed tessellation coefficients; and writing the compressed tessellation coefficients to the graphics memory. The method of claim 5.

10. A graphics processing unit (GPU), a patch fetcher configured to read tessellation coefficients stored in a graphics memory; and a hull shader stage configured to bypass writing at least a portion of the tessellation coefficients corresponding to a plurality of patches in a thread group to the graphics memory in response to detecting that at least a threshold percentage of the tessellation coefficients have the same value. GPU.

11. the hull shader stage is configured to, in response to detecting that at least a threshold percentage of the tessellation coefficients have values ​​indicative of the plurality of patches being culled, send an indication to the patch fetcher that all of the tessellation coefficients corresponding to the plurality of patches have values ​​indicative of the plurality of patches being culled; The patch fetcher includes: responsive to receiving the indication, bypassing reading the tessellation coefficients corresponding to the plurality of patches from the graphics memory; discarding said plurality of patches; [0023] The GPU of claim 10.

12. It also features a tessellator stage. the hull shader stage is configured to, in response to detecting that at least a threshold percentage of tessellation coefficients corresponding to the plurality of patches have values ​​indicative of the plurality of patches being passed to the tessellator stage, send an indication to the patch fetcher indicating that all of the tessellation coefficients corresponding to the plurality of patches have values ​​indicative of the plurality of patches being passed to the tessellator stage; the patch fetcher is configured to provide the plurality of patches to the tessellator stage of the GPU in response to receiving the indication. The GPU of claim 10.

13. the hull shader stage is configured to, in response to detecting that all of the tessellation coefficients corresponding to any one of the plurality of patches have the same value that does not indicate either that the plurality of patches is to be culled or that the plurality of patches is to be passed to a tessellator stage, write the value of the tessellation coefficient to the graphics memory and send a flag to the patch fetcher indicating that the value is to be applied to all tessellation coefficients corresponding to the patch; the patch fetcher is configured to, in response to receiving the flag, read the value from the graphics memory and apply the value to all tessellation coefficients corresponding to the patch. The GPU of claim 10.

14. the hull shader stage is configured to, in response to detecting that all of the tessellation coefficients corresponding to any one of the plurality of patches are not the same, write at least one word to the graphics memory, the at least one word including a plurality of tessellation coefficients corresponding to the patch along with an indication that the at least one word includes the plurality of tessellation coefficients. The GPU of claim 10.

15. the patch comprises an isoline patch and the at least one word comprises two tessellation coefficients; 15. The GPU of claim 14.

Images