High Resolution Monolithic RGB Array

Abstract

1. A light emitting diode structure comprising a p-type region, an n-type region, and a light emitting region for recombination of carriers injectable by the p-type region and the n-type region, wherein at least one of the n-type region and the p-type region is formed at least partially within a via that penetrates the light emitting region, the via defining a periphery of a light emitting surface of at least one pixel.

Description

[Technical field]

[0001] Light Emitting Diode Structures and Methods for Forming Light Emitting Diode Structures Field of the Invention The present invention relates to light emitting diode structures and methods for forming light emitting diode structures. Specifically, but not exclusively, the present invention relates to high resolution monolithic arrays of light emitting diode structures. [Background technology]

[0002] Arrays of conventional red-green-blue (RGB) micro light-emitting diode (μLED) light-emitting pixels are typically realized using pick-and-place techniques or through the use of color conversion materials deposited or embedded within standard planar LED structures. However, as the pixel pitch in such arrays is scaled down to very small pitches (e.g., less than 5 μm) to provide higher resolution arrays, numerous problems arise.

[0003] For example, the use of pick-and-place may be impractical due to the high cost, low throughput, and limited positional accuracy of transferring μLEDs. In the case of color conversion, the use of such techniques is limited by the phosphor size used for color conversion, which is typically larger than 10 μm (i.e., larger than the pixel pitch of arrays with very small pitches required for higher resolution). Furthermore, color conversion techniques may suffer from low reliability and inefficiency due to the small absorption coefficient associated with quantum dots (QDs). For example, a thickness of color conversion QD material greater than 10 μm is required to fully absorb the blue radiation that excites the QDs, and therefore QDs are unsuitable for arrays with very small pixel pitches.

[0004] To avoid the need to transfer LEDs and to provide high quality efficient light emission, it would be beneficial to provide a native LED array on the same substrate. One approach to construct a native LED array on the same substrate relies on selective area growth of nanowires, which is an array of individual structures grown substantially perpendicular to a patterned growth substrate to form light emitting structures, with the light emitting surface defined by the cross-sectional area of ​​the nanowires using a typical epitaxial quantum well structure grown between epitaxial n-type and p-type doped layers. However, such nanowire growth is usually difficult to control and may suffer from severe limitations in achievable light efficiency and color gamut, for example due to poor light extraction efficiency and impurity incorporation. Summary of the Invention [Means for solving the problem]

[0005] In order to alleviate at least some of the above-mentioned problems, there is provided a light emitting diode structure according to the appended claims. Further, there is provided an array of light emitting diode structures and a method for forming one or more light emitting diode structures according to the appended claims.

[0006] In one embodiment, a light emitting diode structure is provided comprising a p-type region, an n-type region, and a light emitting region for recombination of carriers injectable by the p-type region and the n-type region, where at least one of the n-type region and the p-type region is at least partially formed in a via that penetrates the light emitting region, the via defining a periphery of the light emitting surface of at least one pixel. Advantageously, the material used to inject carriers into the light emitting region is itself used to define the periphery of the light emitting surface of at least one pixel, which periphery separates the pixels while still providing the pixels with a source of carriers that allows efficient recombination and light emission across the entire light emitting surface.

[0007] Preferably, the light emitting region comprises at least one epitaxial quantum well layer. Advantageously, the epitaxial quantum well layer is grown with high crystallinity, leading to efficient light generation.

[0008] Preferably, the vias enable lateral carrier injection into the light emitting region. Advantageously, lateral carrier injection into one or more quantum wells in the light emitting region provides efficient hole injection into the light emitting region.

[0009] Preferably, both the n-type and p-type regions are at least partially formed in vias that penetrate the light-emitting region. Advantageously, such a configuration allows lateral carrier injection from both the n-type and p-type regions, leading to efficient recombination. Beneficially, the very regions used for lateral carrier injection are also used to separate pixels.

[0010] Preferably, the light-emitting diode structure comprises a further via, the via and the further via are configured to provide an anode and a cathode. Advantageously, such a configuration allows lateral carrier injection from both the n-type region and the p-type region, leading to efficient recombination. Advantageously, the very regions used for lateral carrier injection are also used to separate pixels. In addition, the anode and the cathode can be selectively energized to control the light-emitting form of the light-emitting diode structure.

[0011] Preferably, the light emitting diode structure comprises further light emitting regions. Conveniently, the light emitting regions may be energized simultaneously or individually and may be configured to have the same or different primary peak wavelengths.

[0012] Preferably, the light emitting region and the further light emitting region are separated by an undoped region, thereby providing a stack of light emitting regions. Advantageously, carrier injection into the different light emitting regions is achieved by forming a via connection to the light emitting region, without the need for stacked n-GaN and p-GaN stacks as shown in conventional LED structures. Advantageously, in the absence of a p-type doping layer, there is no problem with p-type dopant diffusion, and the multiple quantum wells (MQWs) of the light emitting regions can be closer together, without the need for tunnel junctions. Furthermore, in this structure, no electron blocking layer is required.

[0013] Preferably the via passes through both the light emitting region and the further light emitting region, advantageously providing a common connection for the light emitting regions, making processing of the initial epitaxial structure easier.

[0014] Preferably, the light emitting region and the further light emitting region are configured to emit light of different wavelengths. Advantageously, the structure emits light of different primary peak wavelengths, allowing the structure to be realised in a multicolour array.

[0015] Preferably, the light emitting region and the further light emitting region are arranged such that the surface areas of the light emitting region and the further light emitting region partially overlap. Advantageously, in plan view, there are different regions arranged to provide a light emitting surface based on different light emitting regions (and thus can be arranged to provide different light emission, e.g. different intensity, timing or colour, etc.).

[0016] Preferably, the light emitting diode structure comprises at least three light emitting regions, one of the light emitting regions emitting blue light, one of the light emitting regions emitting green light, and One emits red light. Advantageously, the use of three light-emitting regions provides increased flexibility, including the ability to provide high resolution red-green-blue (RGB) light for color displays.

[0017] Preferably, the vias are grid vias that define an array comprising a plurality of pixels. Preferably, the grid is configured to provide a common electrode. Advantageously, the connections can be made in one process step. Furthermore, the use of grid vias to define pixels means that no electrical insulating etching is required between pixels, allowing for higher density pixel integration.

[0018] Preferably, at least two pixels are configured to emit light at different wavelengths.Conveniently, multiple color outputs can be provided from a monolithic array.

[0019] Preferably the further via comprises a cylindrical via, with an n-type or p-type region formed within the further via. Advantageously, a cylindrical via provides an efficient means of providing carrier injection.

[0020] Preferably, the cylindrical vias are configured to provide electrodes to thereby allow control of emission at the pixels defined by the vias. Advantageously, the electrodes can be used to selectively control emission of light from individual pixels in a high resolution pixel array.

[0021] Preferably, the light emitting region and / or the further light emitting region are formed on an undoped epitaxial layer. Advantageously, the undoped epitaxial layer allows electrical isolation of the pixel.

[0022] Preferably, the light emitting region and / or further light emitting region are formed between undoped epitaxial layers. Advantageously, the undoped epitaxial layers allow electrical isolation of the pixels and allow processing of the epitaxial structure for individual pixel connections by etching through the light emitting region and / or further light emitting region formed between the undoped epitaxial layers.

[0023] Preferably, the undoped epitaxial layer is formed on a barrier layer configured to block vertical carrier diffusion. Advantageously, the light emitting structure can be formed on a doped material that can be part of the substrate and / or preferred growth technique, while allowing for separation of the light emitting region such that one of the n-type and p-type regions is formed through the light emitting region.

[0024] Preferably, the light emitting diode structure is a gallium nitride based structure. Gallium nitride is known for its properties of providing efficient light emitting diode devices with a range of primary peak wavelengths. The growth of gallium nitride structures is well developed and the growth and processing of such materials is controllable, providing high quality devices. Therefore, preferably, the undoped epitaxial layer is gallium nitride.

[0025] Preferably the barrier layer is AlGaN. Advantageously, the barrier provides a stable surface for subsequent processing steps.

[0026] Preferably, at least one of the n-type and p-type regions is formed in a via that connects to a planar n-type region or a planar p-type region, respectively. Advantageously, the use of a planar region results in light emission due to carrier diffusion, which may be advantageous in reducing etching damage and loss of active area, which would otherwise be caused by lateral diffusion of carriers into the light emitting region. For the directional implant, a central via etch will be used.

[0027] Preferably, the n-type regions are formed in the vias by selective area growth of n-type material. Advantageously, selective area growth at least partially repairs etch damage. Furthermore, because no open surfaces remain through the multiple quantum wells, no passivation is required.

[0028] Preferably, the p-type regions are formed in the vias by selective area growth of p-type material. Advantageously, selective area growth at least partially repairs etch damage. Furthermore, because no open surfaces remain through the multiple quantum wells, no passivation is required.

[0029] Preferably, the vias are etched vias. Anisotropic etching techniques are known and allow larger scale epitaxial structures to be grown and subsequently processed to provide light emitting diode structures with pixel peripheries defined by etched vias. This means that known techniques for growing high quality and efficient epitaxial structures can be used, as opposed to small scale techniques such as growing patterned nanowires.

[0030] Preferably, the light emitting surface has an area based on the diffusion length of the carriers in the light emitting region. Advantageously, the shape and / or size of the light emitting surface can be optimized based on the diffusion carrier length, which helps to provide uniform light emission in the micro-LED.

[0031] Preferably, the area of ​​the light emitting surface is 100 μm 2 Less than or equal to 16 μm, more preferably 2 Advantageously, the use of vias containing n-type or p-type material to define pixels allows for the formation of micro LEDs with light emitting surfaces that provide pixels with high resolution.

[0032] Advantageously, vias comprising n-type or p-type material are used to define pixels, allowing the formation of microLEDs with emitting surfaces that provide pixels with high resolution that can be formed into arrays. Such arrays are suitable for connection to a backplane and therefore for incorporation into high resolution displays or other high resolution arrays, which may be monochromatic or multichromatic.

[0033] Preferably, the array of light emitting diode structures and / or micro LEDs is provided by forming multiple epitaxial layers on a substrate. Advantageously, forming multiple epitaxial layers on a substrate means that high quality structures can be provided in successive growths, thereby reducing growth times and impurities in the growth.

[0034] Preferably, the plurality of epitaxial layers comprises an n-type region and a light emitting region. Advantageously, such plurality of epitaxial layers comprises layers of a conventional LED structure. Beneficially, the conventional LED structure (which may be terminated before the p-cladding) can be used as a basis for further processing of a monolithic micro LED array.

[0035] Preferably, the epitaxial layers are etched such that the etching penetrates the light emitting area to provide vias that define the pixel periphery. Anisotropic etching techniques are known and allow larger scale epitaxial structures to be grown and subsequently processed to provide a light emitting diode structure having a pixel periphery defined by the etched vias. This means that known techniques for growing high quality and efficient epitaxial structures can be used, as opposed to small scale techniques such as growing patterned nanowires.

[0036] Preferably, the p-type or n-type regions are grown in etched vias.

[0037] Preferably, the further vias are etched to the p-type or n-type regions.

[0038] Preferably, a further via passes through the light emitting region configured to provide a particular wavelength.

[0039] Preferably, still further vias are etched for the p-type or n-type regions, the further and still further vias being configured to allow carrier injection into the different light emitting regions, thereby providing light of different wavelengths.

[0040] Preferably, for either the p-type region or the n-type region, etching still further vias includes etching at least partially through at least one light emitting region to locally remove unwanted longest wavelengths.

[0041] Further aspects of the present invention will become apparent from the specification and the appended claims.

[0042] DETAILED DESCRIPTION OF EMBODIMENTS OF THE PRESENTINVENTION A detailed description of embodiments of the present invention will now be described, by way of example only, with reference to the drawings, in which: [Brief description of the drawings]

[0043] [Figure 1A] A cross-sectional view of the epitaxial structure is shown. [Figure 1B] A cross-sectional view of the processed epitaxial structure is shown. [Figure 1C] A cross-sectional view of the processed epitaxial structure is shown. [Figure 2A] A cross-sectional view of the processed epitaxial structure is shown. [Figure 2B] 2B shows a plan view including the processed epitaxial structure of FIG. 2A. [Figure 3A] 1 shows a cross-sectional view of a light-emitting structure. [Figure 3B] 3B shows a plan view including the light emitting structure of FIG. 3A. [Figure 4] 1 shows a cross-sectional view of a processed light emitting structure. [Diagram 5] 1 shows a cross-sectional view of a light-emitting structure. [Figure 6] 1 shows a cross-sectional view of a processed light emitting structure. [Figure 7] 1 shows a cross-sectional view of a light-emitting structure. [Figure 8] 1 shows a cross-sectional view of a light-emitting structure. [Figure 9] 1 shows a cross-sectional view of an epitaxial structure having three different light emitting regions. [Figure 10A]10 shows a cross-sectional view including the processed epitaxial structure of FIG. [Figure 10B] 10B shows a top view of the processed epitaxial structure of FIG. 10A. [Figure 11A] 10B shows a cross-sectional view of the further processed epitaxial structure of FIG. 10A. [Figure 11B] 11B shows a top view including the further processed epitaxial structure of FIG. 11A. [Figure 12A] 1 shows a light emitting structure having three different light emitting regions. [Figure 12B] 12B shows a plan view of the light-emitting structure of FIG. 12A. [Figure 13A] The treated light-emitting structure of FIG. 12A is shown. [Figure 13B] 13B illustrates lateral carrier injection in the structure of FIG. 13A. [Figure 14] 1 illustrates a pixel implementation having three distinct light emitting regions within the pixel defined by a perimeter formed by vias through the light emitting regions. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0044] Light emitting diodes (LEDs) are typically formed by the formation of epitaxial crystalline layers on a relatively large wafer substrate in a reactor, such as, for example, an MOCVD (metal organic chemical vapor deposition) reactor, an MBE (molecular beam epitaxy) reactor, or other chemical vapor deposition reactor. The nanowire LED arrays are formed by processing elongated light emitting structures. For the reasons discussed above, known methods of constructing arrays of high resolution micro LEDs face challenges in processing LEDs made by crystal growth on relatively large wafer substrates to provide micro LEDs for high resolution arrays. The use of nanowire LED arrays to overcome these processing challenges leads to challenges in controlling the growth process as well as generally inferior performance to that seen with conventional LED growth on relatively large wafer substrates.

[0045] The present disclosure describes microLEDs that are advantageously formed as part of a monolithic high-resolution array by processing light-emitting structures that can be grown on a relatively large wafer substrate. Beneficially, native color pixels can be formed that are smaller, more efficient, and more resistant to degradation compared to color-converting pixels. Compared to pick-and-place assembly, processing epitaxial structures grown directly on a wafer means that forming pixel arrays on a wafer eliminates the need to transfer millions of pixels (and the associated defects in the transfer process), thus allowing for higher throughput. Compared to nanowires, processing standard planar epitaxial deposition layer growth means that multiple quantum wells (MQWs) can be formed in a manner that results in high quality growth and thus a relatively high internal quantum efficiency (IQE). Furthermore, processing of the epitaxial structures results in planar devices that are suitable for light extraction using standard surface patterning techniques.

[0046] Further advantages arising from the described methods and structures will become apparent in the following description. The method of providing a micro LED array is described below with reference to various processing steps (which may include steps performed both in the growth reactor and outside the growth reactor using other processing and / or growth equipment). The methods and structures are described with reference to III-V semiconductor materials. In particular, the methods and structures are described with reference to nitride structures, including gallium nitride (GaN)-based light emitting structures, which are well known to result in relatively high efficiency light emitting structures. However, in further embodiments, the methods and structures are applicable to light emitting structures based on other materials, in particular based on other semiconductor materials.

[0047] In the following figures, like reference numbers are used to denote aspects of structure associated with the same or equivalent features provided by the same or similar processes.

[0048] 1A shows a cross-sectional portion of a structure 100 that is an epitaxial structure 100 that forms the base of a monochromatic micro LED pixel array. Such a monochromatic micro LED pixel array has a plurality of individual pixels, each of which may be individually addressable based on how such a monochromatic micro LED pixel array is connected to a power source (e.g., depending on the configuration of a backplane relative to the micro LED pixel array).

[0049] Structure 100 is a GaN-based epitaxial multiple quantum well (MQW) structure grown by metalorganic chemical vapor deposition (MOCVD), which is effectively an LED structure grown and terminated prior to the p-cladding that would otherwise provide a conventional pn junction sandwiching a light emitting region formed to include at least one or more quantum wells. Beneficially, known techniques can be used to provide high quality material that can be processed to provide monolithic high resolution micro LED arrays.

[0050] In Figure 1A, an AlGaN barrier layer 104 with 10% aluminum is shown grown on an n-type doped (n-GaN) n-type region 102. The n-type region 102 is typically formed on a substrate (not shown). The AlGaN barrier layer 104 is This prevents vertical carrier diffusion from 102.

[0051] An undoped region 106 (GaN that is not intentionally doped) is grown on the barrier layer 104, and a GaN-based superlattice structure 108 is grown on the undoped region 106. On top of the superlattice structure 108 is a light emitting region 110 having multiple quantum wells (MQWs). The n-type region 102, barrier layer 104, undoped region 106, superlattice 108, and light emitting region 110 are shown in cross section as multiple epitaxial layers grown on a substrate (the substrate is not shown insofar as it is not the n-type region 102 itself).

[0052] An undoped region 106 (GaN that is not intentionally doped) is grown on the barrier layer 104, and a GaN-based superlattice structure 108 is grown on the undoped region 106. On top of the superlattice structure 108 is a light emitting region 110 having multiple quantum wells (MQWs). The n-type region 102, barrier layer 104, undoped region 106, superlattice 108, and light emitting region 110 are shown in cross section as epitaxial layers grown on a substrate (not shown).

[0053] Light emitting region 110 comprises an MQW. Additionally or alternatively, light emitting region 110 may comprise a single quantum well (SQW). Additionally or alternatively, light emitting region 110 may include one or more quantum dots or other structures to enable carrier combination and light emission. The quantum wells and quantum dots confine carriers and, in use, provide a light source based on radiative carrier recombination within the quantum structure following carrier injection by the n-type and p-type regions, for example when the n-type and p-type regions are connected to a cathode and an anode, respectively.

[0054] A further barrier layer 112, an AlGaN barrier layer 112, is visible on top of the light emitting region 110. The barrier layer 112 provides a stable surface for subsequent processing steps.

[0055] Although the barrier layer 112 is shown as being an AlGaN barrier layer 112, in addition or alternatively, the barrier layer 112 may be formed from a different material or the barrier layer may be omitted.

[0056] Light emitting region 110 comprises MQWs, although in further embodiments light emitting region 110 may have a single quantum well (SQW). Light emitting region 110 comprises multiple layers of material forming an active region. For example, light emitting region 110 may comprise layers such as short period superlattices and / or undoped recovery layers, which result in high quality crystalline material and light emission from light emitting region 110. Additionally or alternatively, light emitting region 110 may include one or more quantum dots. The quantum wells and quantum dots confine carriers, and in use provide a light source based on carrier recombination in the quantum structure following carrier injection by the n-type and p-type regions when the n-type and p-type regions are connected to a cathode and an anode, respectively.

[0057] The n-type region is typically formed on a substrate, but alternatively, the n-type region may itself be a free-standing substrate suitable for the growth of subsequent crystalline layers. In one embodiment, the substrate is a sapphire substrate. In further embodiments, the substrate is a silicon substrate or a GaN substrate.

[0058] The epitaxial structure 100 is grown using an MOCVD reactor. Advantageously, such a structure 100 can be optimized for MOCVD growth and can result in high quality growth for efficient light generation. Additionally or alternatively, other deposition and / or growth methods may be used to provide the epitaxial structure 100, such as MBE.

[0059] N-type region 102 is formed from n-type gallium nitride. Alternatively, n-type region 102 may be formed from and / or based on other materials. Barrier layer 104 is formed from aluminum gallium nitride, e.g., AlGaN with 10% aluminum. However, in further embodiments, barrier layer 104 may additionally or alternatively not be used or may be formed from a different material. Superlattice 108 is formed from a gallium nitride based material. Additionally or alternatively, superlattice 108 is formed from another material. Light emitting region 110 comprises at least one quantum well. Additionally or alternatively, light emitting region 110 comprises further quantum wells. Additionally or alternatively, light emitting region 110 comprises quantum dots or other quantum structures. Light emitting region 110 is a gallium nitride based region, and at least the quantum wells are formed from a gallium nitride based material, such as indium gallium nitride (InGaN) or aluminum indium gallium nitride (AlINGaN). Additionally or alternatively, different materials are used depending on the structure to be grown. The composition of the quantum wells in the light emitting region 110 is determined based on the primary peak wavelength selected for emission from the light emitting region 110. The barrier layer 112 is formed from aluminum gallium nitride. Additionally or alternatively, different materials may be used to form the barrier layer 112. The light emitting region 110 does not include any doping. For example, the light emitting region does not include silicon doping or magnesium doping due to intentional doping of the light emitting region 110 during growth of the structure 100. In further embodiments, doping is used in the light emitting region 110, but to a degree that does not affect carrier injection for emission through the light emitting surface of the pixel defined by the via through the light emitting region 110. In further embodiments, different semiconductor layers are grown or otherwise formed to provide the base structure necessary to process a monolithic array of micro-LEDs.

[0060] 1A depicts a particular epitaxial structure 100, those skilled in the art will appreciate that additional layers, exclusion of layers, and alternative layers may be used to achieve the concepts described herein depending on the particular needs of a particular implementation. A description of a layer being formed on another layer indicates a positional relationship with respect to the order of growth of the layers, and does not necessarily exclude the presence of a layer between a first layer and a second layer that is described as being on the first layer.

[0061] Once the epitaxial structure 100 is provided, it can be treated to provide conductive regions through which carriers can be injected into the final structure.

[0062] Thus, FIG. 1B shows a processed epitaxial structure 100'. The epitaxial structure 100 of FIG. 1A is shown with an additional mask layer 114. The mask layer 114 is formed and processed using known techniques, including lithographic techniques, to selectively structure openings and expose portions of the underlying epitaxial structure 100, such as the barrier layer 112. Once the portions of the mask layer 114 are selectively removed, a selective etch of the underlying epitaxial structure 100 is performed. Such selective etching provides vias in the epitaxial structure 100. The vias are structured by removal of material to leave paths through the remaining material. Depending on the shape of the exposed areas in the mask layer 114 and the depth of the etch, the vias formed will have a corresponding shape, which in one embodiment is a trench via or a cylindrical via. Vias may be constructed by etching material to leave trenches, holes, or other pathways, however, in further embodiments, vias may additionally or alternatively be constructed by forming material such that the absence of material creates a via structure within another structure, as opposed to removing material.

[0063] In one embodiment, the mask layer 114 is silicon nitride. Additionally or alternatively, different materials such as silicon dioxide may be used. Advantageously, silicon nitride is an effective and controllable mask layer 114 for subsequent processing steps.

[0064] FIG. 1C shows the further processed epitaxial structure 100″ with vias 115 etched through the epitaxial structure 100. The vias 115 are shown etched through the epitaxial structure 100 down to the n-type region 102. To etch the vias 115, lithographic techniques are used to pattern a mask layer and open openings in the mask layer to allow etching of the material exposed by the openings formed in the mask. The vias 115 are shown in cross section. In plan view, the vias 115 are formed in a grid structure (see, for example, the grid in FIG. 2B) to define pixels, and the vias define the periphery of the light emitting surface of the individual pixels 208 by penetrating the light emitting region 110 to form trench vias 115 that separate the individual pixels. The width 210 of the pixel 208 is the distance between the vias 115 shown in FIG. 1C.

[0065] Once vias 115 are formed in epitaxial structure 100, selective overgrowth of n-type material is formed. Such overgrowth or deposition of material in vias 115 can be performed with mask layer 114 remaining in place, for example, so that no growth occurs on barrier layer 112. Thus, Figure 2A illustrates a cross-sectional view of the processed epitaxial structure shown in Figure 1.

[0066] In one embodiment, via 115 is formed using a dry etching technique, such as a plasma-based technique. Preferably, a wet etching process is used to repair any damage caused by the etching of via 115. Additionally or alternatively, any suitable etching technique may be used to form via 115.

[0067] FIG. 2A shows the same basic structure 100, 100′, 100″ as shown in FIGS. 1A, 1B, and 1C, but the structure 200 of FIG. 2A is shown to have been further processed. The processed epitaxial structure 200 of FIG. 2A shows a deposited mask layer 114, which in one embodiment is a silicon nitride layer, etched through the mask layer to provide a via 115 as shown in FIGS. 1A-1C. The via 115 is etched vertically through the epitaxial structure 100 to the doped n-type region 102. An n-type overgrowth 116 of n-type doped GaN (n-GaN) is then formed in the via 115 to provide a conductive region through the light emitting region 110.

[0068] In FIG. 2A, a cross section of a single pixel (with width 210) is shown, but it is understood that the selective etching of the epitaxial structure 100 and the overgrowth of n-type material in the via trenches provided by the selective etching results in an n-type grid, which is in effect a common electrode (in this case a cathode) for all of the pixels, defined by the n-type overgrowth 116 that penetrates the light emitting region 110 of the epitaxial structure 100. Advantageously, the selective area growth of n-type material is performed using a metalorganic chemical vapor deposition (MOCVD) reactor using a relatively high temperature. Such a relatively high temperature anneals the defects and also passivates any open surfaces of the MQW. After processing, no dangling bonds remain at the MQW periphery, and therefore no passivation is required. Beneficially, non-radiative recombination is therefore greatly reduced in the light emitting region 110.

[0069] The n-type overgrowth 116 is shown as rising from the surface of the mask layer 114. Advantageously, this allows for contact to the doped overgrowth. The structure 200 is not shown to scale, but in one embodiment, the structure formed on the n-type region 102 may have a thickness 202 of about 300 nm, and the n-type overgrowth 116 may extend beyond the thickness 202 of the epitaxial structure 200 to a height 204 of an additional 700 nm. In one embodiment, the via 115 may have a width 206 of about 800 nm. In further embodiments, the dimensions of the structure may be determined, for example, by the technology used and the structure desired. For example, the crystal habit of the material used may determine the growth shape of the raised surfaces of any mask layer material. By etching through the openings exposed in mask layer 114, a grid can be formed by growing n-type material in vias 115, as shown in FIG. 2B.

[0070] FIG 2B shows a plan view 200' of the corresponding structure 200 shown in FIG 2A. The plan view 200' shows many more pixels 208 than shown in FIG 2A. Those skilled in the art will appreciate that the number of pixels 208 that can be formed by the methods described herein is not limited to the number of pixels 208 shown in FIG 2B, and that FIG 2B shows an example portion of the plan view 200' of a via 115 etched through an epitaxial structure, the via 115 having an n-type overgrowth 116 therein. A grid structure is used to form a common electrode, such as a common cathode, using the n-type overgrowth 116. A grid can be used to define pixels 208 (although only one of the pixels is labeled, a matrix formed by trench vias 115 with n-type region overgrowth is used to define multiple pixels 208), with the emitting surface of each pixel 208 shown as an area in a plan view 200' of square pixels 208 defined by selectively etched vias 115 formed in a grid matrix with n-type overgrowth 116 within the vias 115. Although vias are constructed by etching material to leave trenches, holes, or other pathways, in further embodiments, vias are additionally or alternatively constructed by forming material such that the absence of material allows a via structure to be constructed within another structure, as opposed to removal of material.

[0071] In one embodiment, the width 210 of the pixels 208 is about 3 μm. The width 210 of the pixels 208 is preferably selected based on the carrier diffusion length used to enable efficient light emission from the light emitting surface of the pixels 208. Advantageously, the electrode formed by the n-type overgrowth 116 runs around the periphery of each pixel 208 through the light emitting region 110, so that no further electrical insulation of the pixels 208 is required. In a further embodiment, the light emitting surface of each pixel 208 is less than 100 square micrometers. In yet a further embodiment, the light emitting surface of each pixel 208 is less than 16 square micrometers. Although the pixels 208 are shown as having light emitting surfaces of the same size and shape, in a further embodiment, the array is provided with different pixels of different shapes and / or sizes.

[0072] Once an effective cathode has been provided in via 115 by n-type overgrowth 116 , an anode is provided based on p-type overgrowth 118 formed in a further via 117 .

[0073] FIG. 3A shows the structure 200 of FIG. 2A further processed to provide a light emitting structure 300. An n-type overgrowth 116 is shown in a via 115 through the light emitting region 110 to the n-type region 102. A via 117 is also shown through the light emitting region 110, with a p-type overgrowth 118 formed in the further via 117. This is achieved by depositing a further mask layer (shown as mask layer 120 over the n-type overgrowth 116 and in addition to the mask layer 114) on the mask layer 114 of FIG. 2A, selectively patterning the further mask layer 120 and the mask layer 114 to construct an opening to expose the underlying structure, and etching through the mask layers 114, 120 to the active area provided by the light emitting region 110 using known lithography and etching techniques. As described with respect to the construction of the via 115 for the n-type overgrowth 116, the via 117 for the p-type overgrowth 118 is formed using dry etching techniques. In one embodiment, a wet etching process is used, if necessary, to repair damage caused by the dry etching.

[0074] Further via 117 is a cylindrical via centrally formed within the pixel periphery defined by vias 115 formed through light emitting region 110. Additionally or alternatively, further via 117 is located at any suitable location for providing light emission. The cross-sectional shape of further via 117 when viewed in plan view is determined by the patterning and etching steps used to provide further via 117. Via 117 has a width of approximately 800 nm. In a further embodiment, via 117 has a width dimensioned to satisfy a preferred implementation for carrier injection and pixel configuration.

[0075] As shown by the arrows in FIG. 3A, n-type overgrowth 116 provides an effective cathode and p-type overgrowth 118 provides an effective anode from n-type overgrowth 116 and p-type overgrowth 118 into light-emitting region 110, allowing lateral injection of carriers into light-emitting region 110 when a suitable power source is used. Such lateral carrier injection in light-emitting region 110 results in more efficient carrier injection, including more efficient hole injection, and therefore more efficient light emission. Carrier injection into light-emitting region 110 may be based on the carrier diffusion length of carriers injected into the multiple quantum well structure of light-emitting region 110 to provide light, which can be emitted through a light-emitting surface defined by a pixel periphery formed by n-type overgrowth 116 in vias 115 etched through light-emitting region 110. A top view 300′ of light-emitting structure 300 is shown in FIG. 3B.

[0076] 3B shows n-type overgrowth 116 formed in grid vias 115 etched through the structure 100 as described with respect to FIG. 1A. Additionally, p-type overgrowth 118 is shown formed in a central via 117 in the pixels 208 defined by the n-type overgrowth 116 in the vias 115 of the common electrode provided by the n-type overgrowth 116. In one embodiment, the central via 117 is formed in each of the pixels 208 to be addressed. The p-type overgrowth 118 is shown in the via 117 centrally positioned in each pixel 208. Such a configuration of a common n-type region that can form a common cathode electrode and individual cylindrical p-type overgrowth regions that can form individually addressable anode electrodes can be used to energize individual pixels 208 in a monochromatic high resolution micro LED array.

[0077] Advantageously, in comparison to known selective area growth techniques, only the n-type and p-type regions may be overgrown, eliminating the problems associated with poor uniformity and compositional pulling commonly encountered when growing AlGaN and InGaN alloys on patterned surfaces.

[0078] Although the vias 115 that penetrate the light emitting region 110 of the epitaxial structure to form trenches that define the light emitting surface of the pixels 208 are shown based on etching the epitaxial structure, in further embodiments other techniques are used to form the light emitting regions through which the vias penetrate to define the periphery of the light emitting surfaces of the pixels in the pixel array.

[0079] Figure 4 shows a cross-sectional view of a processed light emitting structure as described with respect to Figures 1-3. Processed light emitting structure 400 is provided by inverting the light emitting structure of Figure 3A to extract light through n-type region 102, thus avoiding absorption due to p-type contact 404 (the arrows in Figure 4 indicate the direction of light passing through light emitting region 110 from the light emitting surface of pixel 208 defined by via 115).

[0080] 4 further shows an insulating layer 402. The insulating layer 402 insulates the n-type overgrowth 116 from any connections used to contact the p-type overgrowth. Preferably, the insulating layer is silicon dioxide. Shown is a contact 404 to which the anode is connected. Additionally shown is a mirror / barrier layer 405 configured to reflect light emitted from light emitting region 110 and out of an emitting surface defined by n-type overgrowth 116 in vias 115 that define the periphery of pixel 208. Conveniently, contacts 404 are connected to a backplane, which allows contacts 404 for each pixel in the array to be contacted and independently addressable.

[0081] A metal grid 408 is shown designed to contact the common cathode n-type grid of the light emitting array. Such metal 408 grid is aligned with the n-type overgrowth 116 in the vias 115 to maximize light extraction and thus, when viewed in plan, can take substantially the same shape as the grid provided by the vias 115 etched through the light emitting region 110 of the epitaxial structure 100.

[0082] Also shown is a transparent conductive layer 406, which may preferably be indium tin oxide (ITO) formed around and / or between the conductive metal grids 408 to provide electrical conductivity and efficient light extraction from the pixels 208 of the micro LED light emitting array.

[0083] Although cross-sectional views of individual pixels are shown in Figures 1-4, those skilled in the art will appreciate that each pixel forms part of a pixel array. Although the array is shown (e.g., in Figures 2B and 3B) as a grid having square pixels, in further embodiments pixels of different shapes can be provided, for example, by etching different patterns through the epitaxial structure shown in Figure 1.

[0084] While the template concept has been shown using n-GaN n-type region 102, along with a centrally etched via 117 having a p-type overgrowth 118 provided by p-GaN to provide a grid of vias that penetrate the light emitting area and define pixels, in further examples different implementations of the concept are possible, some of which are described in connection with the following figures.

[0085] For example, monolithic high resolution micro LED arrays in which vias define pixels can be provided using different structures that use lateral carrier injection or carrier diffusion into the quantum structures.

[0086] FIG. 5 shows a cross-sectional view of a light-emitting structure 500 according to the concept described above (e.g., one pixel of a pixel array is defined and the same nomenclature is used to correlate with the pixel 208 having the pixel width 210 shown in FIG. 2B). The same epitaxial structure 100 is shown as described with respect to FIG. 1. However, instead of etching through a mask layer 114 to form vias 115 connecting to the n-type region 102, vias 115 are shown etched through the light-emitting region 110, which terminate in the undoped region 106 to provide trenches for p-type overgrowth 118. The p-type overgrowth 118 in these trench vias 115 is used to provide a common anode grid through the light-emitting region 110 that defines the pixels 208. 1-4, a cathode can be provided at each pixel 208 by etching through a central via 117 and depositing / growing an n-type overgrowth 116 material within the via 117. The patterning and etching steps are accomplished depending on the particular structure being fabricated and may use known techniques.

[0087] FIG. 6 shows a processed light emitting structure 600 based on the light emitting structure 500 described with respect to FIG. 5. The processed light emitting structure 600 is an inverted structure of the light emitting structure of FIG. The light is extracted through the light emitting surface defined by the via grid, but is intended to pass through the n-type region 102 (the arrows indicate the direction of light exiting the structure, and in three dimensions it is understood to illuminate the pixel 208, as the light emitting surface of the pixel 208 has its periphery defined by the vias 115 that penetrate the light emitting region 110). A common anode grid 602 is provided to contact the p-type overgrowth 118 in the vias 115 etched through the light emitting region 110. For each light emitting pixel to be addressed, a contact 604 is formed to allow carrier injection into the n-type overgrowth 116 of the cathode. The contact 604 may be reflective to enhance light extraction from the light emitting structure 600. The structure is planarized, so that the planarized insulating layer 402 provides a surface where a backplane can connect to the contacts 604 of other pixels 208 and to other contacts 604, so that each pixel 208 can be individually addressed.

[0088] 7 and 8 show a light emitting structure as described with respect to FIGS. 1-4, but without the additional via 117 penetrating the light emitting region 110. An undoped region 702 is shown separating the light emitting region 110 from the central overgrowths 116, 118 of the patterned doped regions. FIG. 7 shows a light emitting structure 700 with a p-type overgrowth 118 in a via 115 that defines a pixel 208, and a central n-type overgrowth 116. FIG. 8 shows a light emitting structure 800 with an n-type overgrowth 116 in a via 115 that defines a pixel 208, and a p-type overgrowth 118. By selecting appropriate dimensions for the structures of FIGS. 7 and 8, carrier diffusion into the light emitting region 110 occurs. For example, if the vertical distance 704 from the central doped region to the light emitting region 110 is on the order of about tens of nanometers and the horizontal distance 706 from the n-type overgrowth 116 to the p-type overgrowth 118 is on the order of about hundreds of nanometers, recombination in the quantum structure of the light emitting region 110 is feasible.

[0089] Although single color high resolution micro LED arrays have been described above, it is possible to provide multi-color high resolution micro LED arrays based on etching through multiple light emitting regions as described herein.

[0090] FIG. 9 shows an epitaxial structure 900. The epitaxial structure 900 is provided in a similar manner to the epitaxial structure 100 described with reference to FIG. 1. However, instead of having one light emitting region 110 configured to emit light with a peak primary wavelength, the structure 900 has three light emitting regions. A superlattice 906 is shown, on which a light emitting region 907 is provided. On top of the light emitting region 907, an undoped region 902 is provided, followed by a second superlattice 908 and a second light emitting region 909. On top of the second light emitting region 909, a further undoped region 904 and a third superlattice 910 are provided, followed by a third light emitting region 911. It is understood that the undoped regions 902, 904 provide a recovery layer, whereby V-pits occurring at the level of the corresponding superlattice layers 906, 908, 910 are filled and a smooth surface is achieved. The first light-emitting region 907 is configured to emit a primary peak wavelength that is different from the primary peak wavelength that the second light-emitting region 909 is configured to emit, which in turn is different from the primary peak wavelength that the third light-emitting region 911 is configured to emit. The first light-emitting region 907 is configured to emit blue light, the second light-emitting region 909 is configured to emit green light, and the third light-emitting region 911 is configured to emit red light. This structure 900, which typically has a thickness 912 of 600 nm to 800 nm, is the epitaxial structure 900 that forms the basis for processing (which may include further growth steps) to provide a monolithic high resolution RGB micro LED array. Although epitaxial structure 900 is shown to include superlattice layers 908, 910 and recovery layers 902, 904, in further embodiments, structure 900 may instead be thinner by omitting one or more of superlattice layers 908, 910 and one or more of recovery layers 902, 904. In such a case, the blue, green, and red light emitting layers are separated by thinner quantum barriers of about 5 nm to 20 nm, and the complete structure 900 may be only 100 nm to 200 nm thick.

[0091] Beneficially, structure 900 is formed in one growth process. Advantageously, structure 900 is formed such that light emitting regions 907, 909, 911 are relatively closely spaced and vertical (as indicated by thickness 912 including light emitting regions 907, 909, 911 and the superlattice structure and undoped recovery layer), so that a shallow etch can be subsequently used to etch through and remove light emitting regions 907, 909, 911, where any of light emitting regions 907, 909, 911 may not be considered unnecessary. This proves particularly beneficial in the following process for providing a high resolution monolithic color array of micro LEDs. Although light emitting regions 907, 909, 911 each comprise MQWs, in further embodiments the light emitting regions additionally or alternatively comprise a single quantum well in each light emitting region. In further embodiments the light emitting regions additionally or alternatively comprise a quantum barrier layer between each single quantum well of the light emitting regions. Advantageously, the use of thin layers with small separations facilitates shallow etching of different regions of structure 900 using suitable techniques, such as atomic layer etching, to provide different emitting surfaces for emission of different wavelengths of light. Beneficially, the shallow etching results in reduced height differences between pixels and a gentler topology, which facilitates further processing of the structure.

[0092] The epitaxial structure 900 of FIG. 9 is processed in a manner similar to the epitaxial structure 100 of FIG. 1 to provide the processed structure 1000 of FIG. 10A. FIG. 10A shows a mask layer 1004 deposited on the epitaxial structure 900 and patterned using lithographic techniques. The mask layer is to expose the underlying epitaxial structure 900 to allow selective etching through the epitaxial structure 900, and in particular through the three light emitting regions 907, 909, 911. Selective etching through the epitaxial structure 900 (typically using dry etching techniques) provides a via 1001. The via 1001 can be filled by forming a region of n-type overgrowth 1002 in the via 1001. The via 1001 and the n-type overgrowth 1402 within the via 1001 penetrate the light emitting regions 907, 909, 911 to define the periphery of the individual pixels. This is illustrated in the plan view 1000' of Figure 14B, which shows pixels 1006 (only one is labeled) surrounded by n-type overgrowth 1002 formed in trench via 1001, effectively providing a common electrode for pixel 1006. As shown in Figures 10A and 10B, the pixels defined by trench via 1001 penetrating light emitting regions 907, 909, 911 have three distinct light emitting regions 907, 909, 911, respectively. Thus, to provide an RGB array, the pixels are selectively etched to remove undesired wavelengths at a particular pixel. This is illustrated with reference to Figures 11A and 11B.

[0093] FIG. 11A shows how the longest unnecessary wavelengths are locally removed to leave the desired light-emitting regions for the individual pixels. The processed epitaxial structure 1100 of FIG. 11A shows n-type overgrowth 1002 forming a common grid cathode that penetrates all of the light-emitting regions 907, 909, 911. In the first pixel 1102, the second light-emitting region 909, green, and the third light-emitting region 911, red, were etched away to leave the first light-emitting region 907, blue. In the second pixel 1104, the third light-emitting region 909, red, was etched away to leave the first light-emitting region 907, blue, and the second light-emitting region 909, green. In the third pixel 1106, none of the light-emitting regions 907, 909, 911 were removed, so all remain. Each of the pixels 1102 , 1104 , 1106 is defined by a via 1001 etched through the epitaxial structure 900 , and in particular through the light emitting regions 907 , 909 , 911 .

[0094] FIG. 11B illustrates how selective etching of light emitting regions 907, 909, 911 results in pixels dedicated to emitting different wavelengths. For example, a first pixel 1102 can be contacted to emit blue light. A second pixel 1104 can be contacted to emit green light. A third pixel 1106 can be contacted to emit red light. By selectively dedicating pixels to emission of specific primary peak wavelengths, a high resolution monolithic red-green-blue light emitting micro LED array can be formed. As described above, each of the light emitting regions 907, 909, 911 comprises MQWs, however, in further embodiments, the light emitting regions additionally or alternatively comprise a single quantum well in each light emitting region. In further embodiments, the light emitting regions additionally or alternatively comprise a quantum barrier layer between the single quantum wells in each of the light emitting regions. Advantageously, the use of thin layers with small separations facilitates shallow etching of different regions of the structure 900 to provide different light emitting surfaces for emission of different wavelengths of light. Beneficially, the shallow etch results in a reduced height difference between the pixels 1102, 1104, 1106 and a looser topology, which facilitates further processing of the structure described with respect to at least Figures 12A and 12B.

[0095] FIG. 12A shows a thin conformal mask layer 1204 that is patterned and opened to expose a central hole in each pixel 1102, 1104, 1106. Once the central hole is exposed (using lithographic techniques) in each pixel 1102, 1104, 1106, the epitaxial structure 900 can be selectively etched to provide a via 1201 in which a p-type overgrowth 1202 is formed. Since the locally longest wavelength light emitting area has been removed, the selective etching goes down to the desired wavelength light emitting area for each pixel. Advantageously, the construction of the structure and the processing of the structure are coordinated to minimize the number of processing steps to form the resulting structure. This is shown in FIG. 12B, which shows a top view 1200′ of an array with a p-type overgrowth 1202 forming a central via in each of the pixels 1102, 1104, 1106.

[0096] In a manner similar to that described above for the single-color monolithic high-resolution micro LED array, the processed light emitting structure 1200 can be inverted and further processed to connect to a backplane for control of the individual pixels. Figure 13A shows a cross-sectional view of a light emitting array 1300 having three different color pixels. Shown is a first pixel 1102 configured to emit light having a primary peak wavelength that is blue, a second pixel 1104 configured to emit light having a primary peak wavelength that is green, and a third pixel 1106 configured to emit light having a primary peak wavelength that is red.

[0097] As shown in Figure 13B, carrier injection into each of the pixels 1102, 1104, 1106 occurs in the horizontal direction. Although the high resolution RGB micro LED array has been described with reference to a common cathode formed with n-type overgrowth formed in vias defining the periphery of the pixel and p-type overgrowth forming a central via in each pixel for backplate connection, those skilled in the art will appreciate that alternative implementations, such as those described with reference to the high resolution monochromatic micro LED array, may be applied to the high resolution RGB micro LED array. Further, those skilled in the art will appreciate that while the embodiments shown with respect to Figures 9-13 show the formation of vias 1001 penetrating light-emitting regions 907, 909, 911 to define the pixel periphery, the vias 1001 having n-type overgrowth 1002 within the vias 1001, and a central via 1201 in each pixel, the central via 1201 having p-type overgrowth 1202 formed within the vias 1201, in further embodiments different implementations are used (e.g., using p-type overgrowth 1202 within the vias 1001 that define the light-emitting surface of the pixel together with n-type overgrowth 1002 within the central via 1201, or using any of the implementations described with respect to Figures 1-8).

[0098] While the above describes a pixel having an emissive surface defining the pixel, and a pixel periphery defined by vias penetrating one or more of the emissive regions such that the pixel is configured to emit light having a primary peak wavelength, in one embodiment, for a multi-color structure, a common via is formed through multiple emissive regions, and portions of the emissive surface defined by the vias forming the periphery are selectively etched using overgrowth as described above to form contacts, such that multiple different primary peak wavelengths can be emitted from the pixel. This is illustrated in FIG. 14, which shows a plan view 1400 of a triad of micro LEDs defined by overgrowth 1002 formed in vias as described above with reference to FIGS. 9-13. A cross-sectional view 1400' of the structure shown in the plan view 1400 is shown following the diagonal dotted line. A cross-sectional view 1400'' of the structure shown in the plan view 1400 is shown following the horizontal dotted line. Similar features shown in plan view 1400 and cross-sectional views 1400', 1400'' illustrate how such a structure can be realized. Advantageously, such a structure allows for higher density integration of micro-LEDs.

[0099] Advantageously, by using the above-described structures and methods, a monolithic array of high-resolution micro LEDs is provided. Such arrays can include monochromatic or multi-chromatic arrays and are therefore applicable to many applications requiring high-resolution light emitting structures. Beneficially, the pixel pitch of such monolithic high-resolution micro LED arrays is less than 10 micrometers. In some embodiments, the pixel pitch of such monolithic high-resolution micro LED arrays is less than 4 micrometers. In further embodiments, the pixel pitch of such monolithic high-resolution micro LED arrays is less than 3 micrometers. Although the arrays are described with respect to square pixels in a grid configuration, in further embodiments, other configurations and patterns of pixels in the array are realized.

[0100] High quality light emitting arrays are produced due at least in part to the use of planar epitaxial structures that are formed (grown or provided) and processed with minimal overgrowth to separate pixels in a densely integrated array. Beneficially, vias through the light emitting regions of the epitaxial structures provide a means for improved electrical contact to all of the pixels in the array, which can be driven independently. Advantageously, the provision of a stack of light emitting regions means that the desired light emitting regions can be identified and their surfaces exposed for efficient processing and contact to provide improved light emitting diode structures and monolithic high resolution micro LED arrays.

[0101] Although the LED structures above are described with respect to growth by MOCVD, in some embodiments growth by different and / or complementary techniques may be beneficial. For example, growth by MBE may allow for lower temperature growth and / or slower growth rates, which may have advantages with respect to the growth and processing steps described above. Although the process steps above are described in any order, those skilled in the art will appreciate that in further embodiments the process steps may be performed in any order suitable to obtain the target structure.

Claims

1. A p-type region; an n-type region; a first light emitting region for recombination of carriers injectable by the p-type region and the n-type region; A light emitting diode structure comprising:

1. A light emitting diode structure, wherein both the n-type region and the p-type region are formed at least partially within respective first vias that extend through the first light emitting region, the first vias defining a periphery of a light emitting surface of at least one pixel, and further wherein the n-type region and the p-type region are formed within the first vias by selective area growth of n-type and p-type material, respectively.

2. 10. The light emitting diode structure of claim 1, wherein the first light emitting region comprises at least one epitaxial quantum well layer and / or the first via enables lateral carrier injection into the first light emitting region.

3. 3. The light emitting diode structure of claim 1 or 2, wherein the light emitting diode structure comprises a second via, the first via and the second via being configured to provide an anode and a cathode, respectively.

4. The light-emitting diode structure of claim 1, further comprising a second light-emitting region.

5. 5. The light emitting diode structure of claim 4, wherein the first and second light emitting regions are separated by an undoped region thereby providing a stack of light emitting regions, the first via penetrates both the first and second light emitting regions, the first and second light emitting regions are configured to emit light of different wavelengths, the first and second light emitting regions are configured such that surface areas of the first and second light emitting regions overlap, and the light emitting diode structure comprises at least three light emitting regions, one of the first light emitting regions emits blue light, one of the first light emitting regions emits green light, and one of the first light emitting regions emits red light.

6. 6. The light emitting diode structure of claim 1, wherein the first via is a via defining an array comprising a plurality of pixels, the array configured to provide a common electrode, at least one pixel of the plurality of pixels comprising a first electrode different from the common electrode, the first electrode being centrally located within a periphery of the light emitting surface of the at least one pixel, and at least two pixels configured to emit light of different wavelengths.

7. The light emitting diode structure comprising a second via, 7. The light emitting diode structure of claim 4, wherein the second via comprises a cylindrical via, at least one of the n-type region and the p-type region being formed in the second via, the cylindrical via being configured to provide a second electrode thereby enabling control of emission at a pixel defined by the first via.

8. The light emitting diode structure comprising a second light emitting region, 8. The light emitting diode structure of claim 1, wherein the first light emitting region and / or the second light emitting region are formed on an undoped epitaxial layer, and / or the first light emitting region and / or the second light emitting region are formed between undoped epitaxial layers, the undoped epitaxial layers being formed on a barrier layer configured to block vertical carrier diffusion, and the undoped epitaxial layers are gallium nitride.

9. 9. The light emitting diode structure of claim 1, wherein at least one of the n-type region and the p-type region is formed in a via that is connected to a planar n-type region or a planar p-type region, respectively.

10. The light emitting diode structure of any one of claims 1 to 9, wherein the first via is an etched via.

11. The light emitting surface has an area based on the diffusion length of carriers in the first light emitting region, and the area of ​​the light emitting surface is 100 μm ２ 11. The light emitting diode structure according to claim 1, wherein:

12. A light emitting diode structure according to any preceding claim, wherein the at least one pixel is entirely defined about its periphery by a single electrode.

13. A high resolution micro LED array comprising a light emitting diode structure according to any one of claims 1 to 12.

14. 14. The high resolution micro LED array of claim 13, wherein the high resolution micro LED array is a multi-color array and / or the high resolution micro LED array has a pixel pitch of less than 10 micrometers.

15. 1. A method for forming a light emitting diode structure, the light emitting diode structure comprising: A p-type region; an n-type region; a first light emitting region for recombination of carriers injectable by the p-type region and the n-type region, Both the n-type region and the p-type region are at least partially formed within respective first vias that extend through the first light emitting region, the first vias defining a periphery of a light emitting surface of at least one pixel, and further wherein the n-type region and the p-type region are each formed of an n-type material. and forming a p-type material in the first via by selective area growth of p-type material.

16. 16. The method of claim 15, wherein the first light emitting region comprises at least one epitaxial quantum well layer and / or the first via enables lateral carrier injection into the first light emitting region, the method comprising forming a plurality of epitaxial layers on a substrate, the plurality of epitaxial layers comprising the n-type region and the first light emitting region, etching through the first light emitting region to provide the first via defining a periphery of the pixel, growing the p-type region or the n-type region at least partially within the first via, and etching a second via for the p-type region or the n-type region.

17. A method as described in claim 15 or 16, comprising providing a second via, wherein the first via and the second via are configured to provide an anode and a cathode, respectively, the second via is a cylindrical via, and the n-type region or the p-type region is formed in the second via, the cylindrical via is configured to provide a first electrode, thereby enabling control of emission at a pixel defined by the first via.

18. 20. The method of claim 17, wherein the first and second light-emitting regions are configured such that the surface areas of the first and second light-emitting regions partially overlap, and an area of ​​a planar surface of the second light-emitting region is smaller than an area of ​​a planar surface of the first light-emitting region.

19. 19. The method of claim 17 or 18, comprising at least three light-emitting regions, one of the three light-emitting regions emitting blue light, one of the three light-emitting regions emitting green light, and one of the three light-emitting regions emitting red light.

20. 20. The method of any one of claims 15 to 19, wherein the first via is a via defining a plurality of pixels, the plurality of pixels being configured to provide a common electrode, and further comprising forming a second electrode different from the common electrode for at least one of the plurality of pixels, the second electrode being formed centrally within a periphery of the light emitting surface of the at least one pixel, and at least two pixels being configured to emit light of different wavelengths.

21. 21. The method of any one of claims 15 to 20, comprising etching through the first light emitting region to form the first via, a second via through a second light emitting region configured to provide a particular wavelength, etching a third via for the p-type region or the n-type region, the second and third vias configured to allow carrier injection into a third light emitting region to thereby provide light of a different wavelength, and comprising etching at least partially through at least one light emitting region to locally remove unwanted longest wavelengths.

22. A method of forming a high resolution LED array comprising the method of any one of claims 15 to 21.

23. 23. The method of claim 22, wherein the high resolution LED array is a multi-color array, and the high resolution LED array has a pixel pitch of less than 10 micrometers.

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