Image display device manufacturing method and image display device

Abstract

An embodiment relates to a method for manufacturing an image display device, the method comprising: a step for preparing a second substrate comprising a first substrate on which a semiconductor layer is formed; a step for affixing the semiconductor layer onto a first surface of a third substrate; a step for removing the first substrate; a step for etching the semiconductor layer to form a light emitting element including a light emitting surface opposing a bottom surface on the first surface; a step for forming a first insulating film covering the first surface and the light emitting element; a step for forming a circuit element on the first insulating film; a step for forming a second insulating film covering the circuit element and the first insulating film; a step for removing a part of the first and second insulating films to expose a surface including the light emitting surface; a step for forming a via through the first and second insulating films; and a step for forming a wiring layer on the second insulating film.

Description

[Technical field]

[0001] An embodiment of the present invention relates to a manufacturing method for an image display device and an image display device. [Background technology]

[0002] There is a demand for a thin image display device that has high brightness, a wide viewing angle, high contrast, and low power consumption. In order to meet such market demands, development of display devices using self-luminous elements is underway.

[0003] The emergence of display devices using micro LEDs, which are minute light-emitting elements, is expected as a self-emitting element. As a manufacturing method for display devices using micro LEDs, a method of sequentially transferring individually formed micro LEDs to a driving circuit has been introduced. However, as the number of micro LED elements increases with the trend toward higher image quality such as full high definition, 4K, 8K, etc., the transfer process requires an enormous amount of time if a large number of micro LEDs are individually formed and sequentially transferred to a substrate on which a driving circuit, etc. is formed. Furthermore, there is a risk of poor connection between the micro LEDs and the driving circuit, etc., resulting in a decrease in yield.

[0004] A technique is known in which a semiconductor layer including a light emitting layer is grown on a Si substrate, electrodes are formed on the semiconductor layer, and then the semiconductor layer is bonded to a circuit board on which a driving circuit is formed (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2002-141492 A Summary of the Invention [Problem to be solved by the invention]

[0006] An embodiment of the present invention provides a method for manufacturing an image display device that shortens the transfer step of light-emitting elements and improves yield. [Means for solving the problem]

[0007] A method for manufacturing an image display device according to an embodiment of the present invention includes the steps of: preparing a second substrate on which a semiconductor layer including a light-emitting layer is formed; bonding the semiconductor layer to a first surface of a third substrate; removing the first substrate; etching the semiconductor layer to form a light-emitting element including a bottom surface on the first surface and a light-emitting surface provided opposite the bottom surface; forming a first insulating film covering the first surface and the light-emitting element; forming a circuit element on the first insulating film; forming a second insulating film covering the circuit element and the first insulating film; removing a part of the first insulating film and a part of the second insulating film to expose a surface including the light-emitting surface; forming a via penetrating the first insulating film and the second insulating film; and forming a wiring layer on the second insulating film. The light-emitting element includes a connection portion formed on the first surface. The via is provided between the wiring layer and the connection portion and electrically connects the wiring layer and the connection portion.

[0008] An image display device according to one embodiment of the present invention includes a substrate having a first surface, a light-emitting element including a bottom surface on the first surface and a light-emitting surface that is a surface facing the bottom surface, a first insulating film covering a side surface and the first surface of the light-emitting element, a circuit element provided on the first insulating film, a second insulating film covering the circuit element and the first insulating film, a via provided through the first insulating film and the second insulating film, and a wiring layer provided on the second insulating film. The light-emitting element includes a connection portion formed on the first surface. The via is provided between the wiring layer and the connection portion, and electrically connects the wiring layer and the connection portion.

[0009] An image display device according to one embodiment of the present invention includes a substrate having a first surface, a semiconductor layer including a bottom surface on the first surface and a surface facing the bottom surface and including a plurality of light emitting surfaces on the surface, a first insulating film covering a side surface of the semiconductor layer and the first surface, a plurality of transistors provided on the first insulating film, a second insulating film covering the plurality of transistors and the first insulating film, a plurality of vias provided penetrating the first insulating film and the second insulating film, and a wiring layer provided on the second insulating film. The semiconductor layer includes a connection portion formed on the first surface. The plurality of vias are provided between the wiring layer and the connection portion and electrically connect the wiring layer and the connection portion. Effect of the Invention

[0010] According to one embodiment of the present invention, a method for manufacturing an image display device is realized that shortens the transfer process of light emitting elements and improves yield. [Brief description of the drawings]

[0011] [Figure 1] 1 is a schematic cross-sectional view illustrating a portion of an image display device according to a first embodiment. [Diagram 2] FIG. 11 is a cross-sectional view that illustrates a schematic view of a part of a modified example of the image display device according to the first embodiment. [Diagram 3] FIG. 1 is a schematic block diagram illustrating an image display device according to a first embodiment. [Figure 4] FIG. 2 is a schematic plan view illustrating a portion of the image display device according to the first embodiment. [Figure 5A] 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 5B] 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 5C] 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 6] 1A to 1C are schematic perspective views illustrating a method for manufacturing the image display device according to the first embodiment. [Figure 7A]2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 7B] 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 7C] 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 8A] 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 8B] 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 9A] 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 9B] 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 9C] 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 10A] 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 10B] 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 11A] 5A to 5C are schematic cross-sectional views illustrating a manufacturing method of a modified example of the image display device of the first embodiment. [Figure 11B] 5A to 5C are schematic cross-sectional views illustrating a manufacturing method of a modified example of the image display device of the first embodiment. [Figure 12] 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 13A] 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 13B] 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 13C] 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 13D]2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. [Figure 14] FIG. 1 is a schematic perspective view illustrating an image display device according to a first embodiment. [Figure 15] FIG. 11 is a schematic cross-sectional view illustrating a portion of an image display device according to a second embodiment. [Figure 16] FIG. 11 is a schematic block diagram illustrating an image display device according to a second embodiment. [Figure 17A] 5A to 5C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a second embodiment. [Figure 17B] 5A to 5C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a second embodiment. [Figure 17C] 5A to 5C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a second embodiment. [Figure 18A] 5A to 5C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a second embodiment. [Figure 18B] 5A to 5C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a second embodiment. [Figure 19A] 5A to 5C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a second embodiment. [Figure 19B] 5A to 5C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a second embodiment. [Figure 20] FIG. 11 is a schematic cross-sectional view illustrating a portion of an image display device according to a third embodiment. [Figure 21A] 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a third embodiment. [Figure 21B] 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a third embodiment. [Figure 22A] 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a third embodiment. [Figure 22B] 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a third embodiment. [Diagram 23]FIG. 13 is a schematic cross-sectional view illustrating a portion of an image display device according to a fourth embodiment. [Figure 24A] 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a fourth embodiment. [Figure 24B] 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a fourth embodiment. [Diagram 25] FIG. 13 is a schematic cross-sectional view illustrating a portion of an image display device according to a fifth embodiment. [Figure 26A] 13A to 13C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a fifth embodiment. [Figure 26B] 13A to 13C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a fifth embodiment. [Figure 26C] 13A to 13C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a fifth embodiment. [Figure 27A] 13A to 13C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a fifth embodiment. [Figure 27B] 13A to 13C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a fifth embodiment. [Figure 28A] 13A to 13C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a fifth embodiment. [Figure 28B] 13A to 13C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a fifth embodiment. [Figure 29] FIG. 13 is a schematic cross-sectional view illustrating a part of an image display device according to a modified example of the fifth embodiment. [Figure 30A] 13A to 13C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a modified example of the fifth embodiment. [Figure 30B] 13A to 13C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a modified example of the fifth embodiment. [Figure 30C] 13A to 13C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a modified example of the fifth embodiment. [Figure 31A] 13A to 13C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a modified example of the fifth embodiment. [Figure 31B]13A to 13C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a modified example of the fifth embodiment. [Diagram 32] 1 is a graph illustrating the characteristics of a pixel LED element. [Diagram 33] FIG. 13 is a block diagram illustrating an image display device according to a sixth embodiment. [Diagram 34] FIG. 23 is a block diagram illustrating an image display device according to a modified example of the sixth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as in reality. Even when the same part is shown, the dimensions and ratios of each part may be different depending on the drawing. In this specification and each drawing, elements similar to those described above with reference to the previous drawings are given the same reference numerals and detailed description thereof will be omitted as appropriate.

[0013] (First embodiment) FIG. 1 is a schematic cross-sectional view illustrating a part of the image display device according to the present embodiment. 1 shows a schematic configuration of a sub-pixel 20 of an image display device according to this embodiment. A pixel constituting an image displayed on the image display device is made up of a plurality of sub-pixels 20.

[0014] In the following, the three-dimensional coordinate system of XYZ may be used for explanation. The subpixels 20 are arranged in a two-dimensional plane as shown in FIG. 14 described later. The two-dimensional plane on which the subpixels 20 are arranged is defined as the XY plane. The subpixels 20 are arranged along the X-axis direction and the Y-axis direction. FIG. 1 shows a cross section taken along line AA' in FIG. 4 described later, and is a cross section obtained by connecting multiple cross sections in planes perpendicular to the XY plane on one plane. In other figures, as in FIG. 1, the X-axis and Y-axis are not shown in the cross sections in multiple planes perpendicular to the XY plane, but the Z-axis perpendicular to the XY plane is shown. That is, in these figures, the plane perpendicular to the Z-axis is defined as the XY plane. For convenience, the positive direction of the Z-axis may be referred to as "up" or "upward" and the negative direction of the Z-axis may be referred to as "down" or "downward", but the direction along the Z-axis is not necessarily the direction in which gravity is applied. The length along the Z-axis may be referred to as the height.

[0015] The subpixel 20 has a light emitting surface 153S that is substantially parallel to the XY plane. The light emitting surface 153S is a surface that mainly emits light in the positive direction of the Z axis that is perpendicular to the XY plane.

[0016] As shown in FIG. 1, a subpixel 20 of the image display device includes a substrate 102, a light emitting element 150, a first interlayer insulating film 156, a transistor 103, a second interlayer insulating film 108, a via 161k, and a wiring layer 110.

[0017] In this embodiment, the substrate 102 on which the light emitting element 150 is formed is a light-transmitting substrate, for example, a glass substrate. The substrate 102 has a first surface 102a. The first surface 102a is a surface that is approximately parallel to the XY plane. The transistor 103 is a thin film transistor (TFT) and is formed on a first interlayer insulating film 156. The light emitting element 150 is formed on the first surface 102a. The light emitting element 150 is driven by the TFT provided via the first interlayer insulating film 156. The process of forming circuit elements including TFTs on a large glass substrate has been established for the manufacture of liquid crystal panels, organic EL panels, etc., and has the advantage that an existing plant can be used.

[0018] The subpixel 20 further includes a color filter 180. The color filter 180 (wavelength conversion member) is provided on the surface resin layer 170 via a transparent thin-film adhesive layer 188. The surface resin layer 170 is provided on the second interlayer insulating film 108 and the wiring layer 110.

[0019] The configuration of the sub-pixel 20 will be described in detail below. In this example, the light emitting element 150 is provided on the first surface 102a via a buffer layer 140. The buffer layer 140 is made of an insulating material. The buffer layer 140 is used in growing the semiconductor layers for forming the light emitting element 150, and will be described in detail later in the description of the manufacturing method.

[0020] The light-emitting element 150 includes a light-emitting surface 153S. The light-emitting element 150 is a prismatic or cylindrical element having a bottom surface 151B on the first surface 102a. The light-emitting surface 153S is a surface facing the bottom surface 151B of the light-emitting element 150. In this example, the bottom surface 151B of the light-emitting element 150 is a surface in contact with the buffer layer 140.

[0021] The light emitting element 150 includes an n-type semiconductor layer 151, a light emitting layer 152, and a p-type semiconductor layer 153. The n-type semiconductor layer 151, the light emitting layer 152, and the p-type semiconductor layer 153 are laminated in this order from the bottom surface 151B toward the light emitting surface 153S. Therefore, in this example, the n-type semiconductor layer 151 is provided in contact with the buffer layer 140.

[0022] The n-type semiconductor layer 151 includes a connection portion 151a. The connection portion 151a is provided on the first surface 102a, together with the buffer layer 140, protruding in one direction from the n-type semiconductor layer 151. The height of the connection portion 151a is the same as or lower than the height of the n-type semiconductor layer 151, and the light emitting element 150 is formed in a stepped shape. The connection portion 151a is n-type and is electrically connected to the n-type semiconductor layer 151. The connection portion 151a is connected to one end of the via 161k, and the n-type semiconductor layer 151 is electrically connected to the via 161k through the connection portion 151a.

[0023] When the light emitting element 150 has a prismatic shape, the shape of the light emitting element 150 in the XY plane view is, for example, substantially square or rectangular. When the shape of the light emitting element 150 in the XY plane view is a polygon including a square, the corners of the light emitting element 150 may be rounded. When the shape of the light emitting element 150 in the XY plane view is cylindrical, the shape of the light emitting element 150 in the XY plane view is not limited to a circle, and may be, for example, an ellipse. By appropriately selecting the shape and arrangement of the light emitting element in the plan view, the degree of freedom of the wiring layout, etc. is improved.

[0024] The light emitting element 150 may include, for example, In X Al Y Ga 1-X-YA gallium nitride compound semiconductor including a light emitting layer of, for example, N (0≦X, 0≦Y, X+Y<1) is preferably used. Hereinafter, the above-mentioned gallium nitride compound semiconductor may be simply referred to as gallium nitride (GaN). The light emitting element 150 in one embodiment of the present invention is a so-called light emitting diode. The wavelength of light emitted by the light emitting element 150 may be in the range from the near ultraviolet region to the visible light region, for example, about 467 nm±20 nm. The wavelength of light emitted by the light emitting element 150 may be blue-violet light of about 410 nm±20 nm. The wavelength of light emitted by the light emitting element 150 is not limited to the above-mentioned value, and may be any appropriate value.

[0025] The area of ​​the light-emitting layer 152 in the XY plane view is set according to the emission colors of the red, green, and blue subpixels. Hereinafter, the area in the XY plane view may be simply referred to as the area. The area of ​​the light-emitting layer 152 is appropriately set depending on the luminosity factor and the conversion efficiency of the color conversion section 182 of the color filter 180. In other words, the area of ​​the light-emitting layer 152 of the subpixels 20 of each emission color may be the same or may differ for each emission color. The area of ​​the light-emitting layer 152 is the area of ​​the region surrounded by the periphery of the light-emitting layer 152 projected onto the XY plane.

[0026] The first interlayer insulating film 156 (first insulating film) covers the first surface 102a. The first interlayer insulating film 156 covers the side surface of the buffer layer 140 and the side surface of the light emitting element 150. The first interlayer insulating film 156 insulates the light emitting elements 150 from each other. The first interlayer insulating film 156 insulates the light emitting element 150 from circuit elements such as the transistor 103. The first interlayer insulating film 156 provides a flat surface for forming the circuit 101 including the circuit elements such as the transistor 103. By covering the light emitting element 150, the first interlayer insulating film 156 protects the light emitting element 150 from thermal stress and the like when forming the transistor 103 and the like.

[0027] The first interlayer insulating film 156 is formed of an organic insulating material. The organic insulating material used for the first interlayer insulating film 156 is preferably a white resin. Since the white resin reflects the lateral emitted light of the light emitting element 150 and the return light caused by the interface of the color filter 180, etc., using a white resin for the first interlayer insulating film 156 contributes to a substantial improvement in the luminous efficiency of the light emitting element 150.

[0028] The white resin is formed by dispersing scattering particles having a Mie scattering effect in a transparent resin such as a silicon-based resin, such as SOG (Spin On Glass), or a novolac-type phenol-based resin. The scattering particles are colorless or white, and have a diameter of about 1 / 10 to several times the wavelength of the light emitted by the light-emitting element 150. The scattering particles preferably have a diameter of about 1 / 2 the wavelength of the light. For example, TiO 2 , Al 2 SO 3 , ZnO, etc.

[0029] Alternatively, the white resin can be formed by utilizing a large number of fine voids dispersed in a transparent resin. In order to whiten the first interlayer insulating film 156, a SiO 2 film formed by ALD (Atomic-Layer-Deposition) or CVD is layered on the SOG or the like. 2 A membrane or the like may also be used.

[0030] The first interlayer insulating film 156 may be a black resin. By making the first interlayer insulating film 156 a black resin, scattering of light in the subpixels 20 is suppressed, and stray light is more effectively suppressed. An image display device in which stray light is suppressed can display sharper images.

[0031] A TFT lower layer film 106 is formed over the first interlayer insulating film 156. The TFT lower layer film 106 is provided for the purpose of ensuring flatness when the transistor 103 is formed, and protecting the TFT channel 104 of the transistor 103 from contamination during heat treatment. The TFT lower layer film 106 is made of, for example, SiO 2 and the like are insulating films.

[0032] The transistor 103 is formed on a TFT lower layer film 106. In addition to the transistor 103, other circuit elements such as other transistors and a capacitor are formed on the TFT lower layer film 106, and a circuit 101 is formed by wiring and the like. For example, in FIG. 3 described later, the transistor 103 corresponds to a drive transistor 26. In FIG. 3, other circuit elements include a selection transistor 24 and a capacitor 28. The circuit 101 includes a TFT channel 104, an insulating layer 105, a second interlayer insulating film 108, vias 111s and 111d, and a wiring layer 110.

[0033] In this example, the transistor 103 is a p-channel thin film transistor (TFT). The transistor 103 includes a TFT channel 104 and a gate 107. The TFT channel 104 is preferably formed by a low temperature polysilicon (LTPS) process. In the LTPS process, the TFT channel 104 is formed by polycrystallizing and activating an amorphous Si region formed on the TFT underlayer film 106. For example, laser annealing using a laser is used to polycrystallize and activate the amorphous Si region. The TFT formed by the LTPS process has a sufficiently high mobility.

[0034] The TFT channel 104 includes regions 104s, 104i, and 104d. The regions 104s, 104i, and 104d are all provided on the TFT underlayer film 106. The region 104i is provided between the region 104s and the region 104d. The regions 104s and 104d are doped with boron ions (B +) or boron fluoride ion (BF 2+ ) and is doped with p-type impurities and is in ohmic contact with the vias 111s and 111d.

[0035] The gate 107 is provided on the TFT channel 104 via an insulating layer 105. The insulating layer 105 is provided to insulate the TFT channel 104 from the gate 107 and to insulate the gate 107 from other adjacent circuit elements. When a potential lower than that of the region 104s is applied to the gate 107, a channel is formed in the region 104i, thereby controlling the current flowing between the regions 104s and 104d.

[0036] The insulating layer 105 is, for example, SiO 2 The insulating layer 105 is made of SiO 2 Or Si 3 N 4 The insulating layer may be a multi-layer insulating layer including the above.

[0037] The gate 107 may be made of, for example, polycrystalline Si, or may be made of a high melting point metal such as W or Mo. The polycrystalline Si film of the gate 107 is generally formed by CVD or the like.

[0038] The second interlayer insulating film 108 is provided on the gate 107 and the insulating layer 105. The second interlayer insulating film 108 is formed of, for example, the same material as the first interlayer insulating film 156. That is, the second interlayer insulating film 108 is formed of, for example, a white resin or SiO 2 The second interlayer insulating film 108 also functions as a planarizing film for forming the wiring layer 110.

[0039] The first interlayer insulating film 156, the TFT lower film 106, the insulating layer 105, and the second interlayer insulating film 108 are configured as described above, and therefore are not provided above the light-emitting surface 153S. In other words, the light-emitting surface 153S is exposed from the first interlayer insulating film 156, the TFT lower film 106, the insulating layer 105, and the second interlayer insulating film 108 by the opening 158. As will be described later, the opening 158 is filled with a surface resin layer 170.

[0040] The vias 111s and 111d are provided penetrating the second interlayer insulating film 108 and the insulating layer 105. The wiring layer 110 is formed on the second interlayer insulating film 108. The wiring layer 110 includes a plurality of wirings that may have different potentials. In this example, the wiring layer 110 includes wirings 110s, 110d, and 110k.

[0041] A part of the wiring 110s is provided above the region 104s. The other part of the wiring 110s is connected to a power line 3 shown in FIG. 3, which will be described later, for example. A part of the wiring 110d (second wiring) is provided above the region 104d. The other part of the wiring 110d is connected to a surface including the light-emitting surface 153S. The surface including the light-emitting surface 153S is the same plane as the light-emitting surface 153S, and one end of the other part of the wiring 110d is connected to a surface on this surface other than the light-emitting surface 153S. A part of the wiring 110k (first wiring) is provided above the connection portion 151a. The other part of the wiring 110k is connected to a ground line 4 shown in FIG. 3, which will be described later, for example.

[0042] In the wiring layers in the cross-sectional views of FIG. 1 and subsequent figures, unless otherwise specified, the reference numeral for the wiring layer is indicated next to one of the wires included in the wiring layer to which the reference numeral should be attached.

[0043] The via 111s is provided between the wiring 110s and the region 104s, and electrically connects the wiring 110s and the region 104s. The via 111d is provided between the wiring 110d and the region 104d, and electrically connects the wiring 110d and the region 104d.

[0044] The wiring 110s is connected to the region 104s through a via 111s. The region 104s is the source region of the transistor 103. Therefore, the source region of the transistor 103 is electrically connected to the power line 3 through the via 111s and the wiring 110s.

[0045] The wiring 110d is connected to the region 104d through the via 111d. The region 104d is the drain region of the transistor 103. Therefore, the drain region of the transistor 103 is electrically connected to the p-type semiconductor layer 153 through the via 111d and the wiring 110d.

[0046] The via 161k is provided so as to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156. The via 161k is provided between the wiring 110k and the connection portion 151a, and electrically connects the wiring 110k and the connection portion 151a. Therefore, the n-type semiconductor layer 151 is electrically connected to the ground line 4 via the connection portion 151a, the via 161k, and the wiring 110k.

[0047] The wiring layer 110 and the vias 111s, 111d, and 161k are formed of, for example, Al, an Al alloy, a laminated film of Al and Ti, etc. For example, in the laminated film of Al and Ti, Al is laminated on a thin film of Ti, and Ti is further laminated on Al.

[0048] The surface resin layer 170 covers the second interlayer insulating film 108 and the wiring layer 110. The surface resin layer 170 is also filled in the opening 158. The surface resin layer 170 covers the light emitting surface 153S. The surface resin layer 170 filled in the opening 158 covers the side surfaces of the first interlayer insulating film 156, the TFT lower film 106, the insulating layer 105, and the second interlayer insulating film 108. The surface resin layer 170 is a transparent resin, and protects the interlayer insulating film 156 and the wiring layer 110, and provides a flat surface for bonding the color filter 180.

[0049] The color filter 180 includes a light shielding portion 181 and a color conversion portion 182. The color conversion portion 182 is provided directly above the light emitting surface 153S of the light emitting element 150 in accordance with the shape of the light emitting surface 153S. In the color filter 180, the portion other than the color conversion portion 182 is made into a light shielding portion 181. The light shielding portion 181 is a so-called black matrix, and reduces bleeding due to color mixing of light emitted from adjacent color conversion portions 182, making it possible to display a sharp image.

[0050] The color conversion section 182 may have one layer or two or more layers. FIG. 1 shows a case where the color conversion section 182 has two layers. Whether the color conversion section 182 has one layer or two layers is determined by the color, i.e., the wavelength, of the light emitted by the subpixel 20. When the emission color of the subpixel 20 is red, the color conversion section 182 is preferably made up of two layers, that is, the color conversion layer 183 and the filter layer 184 that transmits red light. When the emission color of the subpixel 20 is green, the color conversion section 182 is preferably made up of two layers, that is, the color conversion layer 183 and the filter layer 184 that transmits green light. When the emission color of the subpixel 20 is blue, the color conversion section 182 is preferably made up of one layer.

[0051] When color conversion section 182 has two layers, the first layer is color conversion layer 183 and the second layer is filter layer 184. First color conversion layer 183 is provided at a position closer to light emitting element 150. Filter layer 184 is laminated on color conversion layer 183.

[0052] The color conversion layer 183 converts the wavelength of light emitted by the light emitting element 150 into a desired wavelength. In the case of a subpixel 20 that emits red light, the color conversion layer 183 converts the light of the wavelength of the light emitting element 150, 467 nm±20 nm, into light of a wavelength of, for example, about 630 nm±20 nm. In the case of a subpixel 20 that emits green light, the color conversion layer 183 converts the light of the wavelength of the light emitting element 150, 467 nm±20 nm, into light of a wavelength of, for example, about 532 nm±20 nm.

[0053] Filter layer 184 blocks the wavelength component of blue emitted light that remains without being color converted by color conversion layer 183 .

[0054] When the color of light emitted by the subpixel 20 is blue, the subpixel 20 may output the light via the color conversion layer 183, or may output the light directly without passing through the color conversion layer 183. When the wavelength of the light emitted by the light emitting element 150 is about 467 nm±20 nm, the subpixel 20 may output the light without passing through the color conversion layer 183. When the wavelength of the light emitted by the light emitting element 150 is 410 nm±20 nm, it is preferable to provide one color conversion layer 183 in order to convert the wavelength of the output light to about 467 nm±20 nm.

[0055] Even in the case of a blue subpixel 20, the subpixel 20 may have a filter layer 184. By providing the blue subpixel 20 with the filter layer 184 that transmits blue light, minute reflection of external light other than blue light that occurs on the surface of the light-emitting element 150 is suppressed.

[0056] FIG. 2 is a cross-sectional view that diagrammatically shows a part of a modified example of the image display device according to the present embodiment. In the cross-sectional views of the subpixels in Fig. 2 and subsequent figures, the surface resin layer 170, the transparent thin film adhesive layer 188, and the color filter 180 are omitted to avoid complexity. In the subsequent figures, except for cross-sectional views for explaining the manufacturing method, structures above the surface resin layer 170 are provided on the second interlayer insulating film 108, the wiring layer 110, and the opening 158 unless otherwise specified. The same applies to the other embodiments and their modified examples described later.

[0057] 2, the subpixel 20a has a different method of connecting the light-emitting element 150 and the wiring 110d1 from the method of connecting the light-emitting element 150 and the wiring 110d in the first embodiment described above. This modification also differs from the first embodiment in that a translucent electrode 159s is provided over the wiring 110s. In other respects, this modification is the same as the first embodiment, and the same components are denoted by the same reference numerals and detailed descriptions thereof are omitted as appropriate. 2, the subpixel 20a includes a light-emitting element 150, a wiring 110d1, and a light-transmitting electrode 159d. The wiring 110d1 is provided above the region 104d and the via 111d. The wiring 110d1 is connected to the region 104d through the via 111d. The wiring 110d1 is not extended to reach the light-emitting surface 153S, and is not directly connected to the light-emitting surface 153S.

[0058] The translucent electrode 159d is provided over the wiring 110d1. The translucent electrode 159d is provided over the light-emitting surface 153S. The translucent electrode 159d is also provided between the wiring 110d1 and the light-emitting surface 153S, and electrically connects the wiring 110d1 and the light-emitting surface 153S.

[0059] The transparent electrode 159s is provided over the wiring 110s. The transparent electrodes 159d and 159s are formed of a transparent conductive film. An ITO film, a ZnO film, or the like is preferably used for the transparent electrodes 159d and 159s. A transparent electrode may also be provided on the wiring 110k.

[0060] The light emitting surface 153S is preferably roughened. When the light emitting surface 153S of the light emitting element 150 is roughened, the light extraction efficiency can be improved.

[0061] By providing the transparent electrode 159d on the light-emitting surface 153S, the connection area between the transparent electrode 159d and the p-type semiconductor layer 153 can be increased, and the area of ​​the light-emitting surface 153S can be increased, thereby improving the light-emitting efficiency. When the light-emitting surface 153S is a rough surface, the connection area between the light-emitting surface 153S and the transparent electrode 159d can be increased to reduce the contact resistance, thereby further improving the light-emitting efficiency.

[0062] This embodiment may include any of the configurations of sub-pixels 20, 20a shown above. FIG. 3 is a schematic block diagram illustrating the image display device according to the present embodiment. 3, the image display device 1 of this embodiment includes a display area 2. Sub-pixels 20 are arranged in the display area 2. The sub-pixels 20 are arranged, for example, in a lattice pattern. For example, n sub-pixels 20 are arranged along the X axis, and m sub-pixels 20 are arranged along the Y axis.

[0063] A pixel 10 includes a number of sub-pixels 20 that emit light of different colors. Sub-pixel 20R emits red light. Sub-pixel 20G emits green light. Sub-pixel 20B emits blue light. The emission color and brightness of one pixel 10 are determined by the three types of sub-pixels 20R, 20G, and 20B emitting light at a desired brightness.

[0064] One pixel 10 includes three sub-pixels 20R, 20G, and 20B, which are arranged linearly on the X-axis, as shown in Fig. 3. In each pixel 10, sub-pixels of the same color may be arranged in the same column, or, as in this example, sub-pixels of different colors may be arranged in each column.

[0065] The image display device 1 further includes a power supply line 3 and a ground line 4. The power supply line 3 and the ground line 4 are laid out in a grid pattern along the arrangement of the sub-pixels 20. The power supply line 3 and the ground line 4 are electrically connected to each sub-pixel 20, and supply power to each sub-pixel 20 from a DC power supply connected between a power supply terminal 3a and a GND terminal 4a. The power supply terminal 3a and the GND terminal 4a are provided at the ends of the power supply line 3 and the ground line 4, respectively, and are connected to a DC power supply circuit provided outside the display area 2. A positive voltage is supplied to the power supply terminal 3a with respect to the GND terminal 4a.

[0066] The image display device 1 further includes scanning lines 6 and signal lines 8. The scanning lines 6 are arranged in a direction parallel to the X-axis. That is, the scanning lines 6 are arranged along the row direction arrangement of the sub-pixels 20. The signal lines 8 are arranged in a direction parallel to the Y-axis. That is, the signal lines 8 are arranged along the column direction arrangement of the sub-pixels 20.

[0067] The image display device 1 further includes a row selection circuit 5 and a signal voltage output circuit 7. The row selection circuit 5 and the signal voltage output circuit 7 are provided along the outer edge of the display area 2. The row selection circuit 5 is provided along the Y-axis direction of the outer edge of the display area 2. The row selection circuit 5 is electrically connected to the sub-pixels 20 of each column via scanning lines 6, and supplies a selection signal to each sub-pixel 20.

[0068] The signal voltage output circuit 7 is provided along the X-axis direction on the outer edge of the display area 2. The signal voltage output circuit 7 is electrically connected to the sub-pixels 20 in each row via signal lines 8, and supplies a signal voltage to each sub-pixel 20.

[0069] The subpixel 20 includes a light emitting element 22, a selection transistor 24, a drive transistor 26, and a capacitor 28. In Figure 3 and Figure 4 described below, the selection transistor 24 may be labeled T1, the drive transistor 26 may be labeled T2, and the capacitor 28 may be labeled Cm.

[0070] The light-emitting element 22 is connected in series with the driving transistor 26. In this embodiment, the driving transistor 26 is a p-channel TFT, and the anode electrode of the light-emitting element 22 is connected to the drain electrode of the driving transistor 26. The main electrodes of the driving transistor 26 and the selection transistor 24 are the drain electrode and the source electrode. The anode electrode of the light-emitting element 22 is connected to the p-type semiconductor layer. The cathode electrode of the light-emitting element 22 is connected to the n-type semiconductor layer. The series circuit of the light-emitting element 22 and the driving transistor 26 is connected between the power supply line 3 and the ground line 4. The driving transistor 26 corresponds to the transistor 103 in FIG. 1, and the light-emitting element 22 corresponds to the light-emitting element 150 in FIG. 1. The current flowing through the light-emitting element 22 is determined by the voltage applied between the gate and source of the driving transistor 26, and the light-emitting element 22 emits light with a luminance according to the current flowing through it.

[0071] The selection transistor 24 is connected between the gate electrode of the drive transistor 26 and a signal line 8 via a main electrode. The gate electrode of the selection transistor 24 is connected to a scanning line 6. A capacitor 28 is connected between the gate electrode of the drive transistor 26 and a power line 3.

[0072] The row selection circuit 5 selects one row from an array of m rows of subpixels 20 and supplies a selection signal to a scanning line 6. The signal voltage output circuit 7 supplies a signal voltage having a required analog voltage value to each subpixel 20 in the selected row. The signal voltage is applied between the gate and source of the drive transistor 26 of the subpixel 20 in the selected row. The signal voltage is held by a capacitor 28. The drive transistor 26 passes a current corresponding to the signal voltage to the light-emitting element 22. The light-emitting element 22 emits light with a luminance corresponding to the current passing through the light-emitting element 22.

[0073] The row selection circuit 5 sequentially switches the selected row and supplies a selection signal. That is, the row selection circuit 5 scans the rows in which the sub-pixels 20 are arranged. A current corresponding to the signal voltage flows through the light-emitting elements 22 of the sequentially scanned sub-pixels 20, causing them to emit light. Each pixel 10 emits light with a color and brightness determined by the color and brightness emitted by the RGB sub-pixels 20, and an image is displayed in the display area 2.

[0074] FIG. 4 is a schematic plan view illustrating a part of the image display device of the present embodiment. 1, the light emitting element 150 and the driving transistor 103 are stacked in the Z-axis direction with a first interlayer insulating film 156 interposed therebetween. The light emitting element 150 corresponds to the light emitting element 22 in Fig. 3. The driving transistor 103 corresponds to the driving transistor 26 in Fig. 3 and is also denoted as T2.

[0075] 4, the cathode electrode of the light emitting element 150 is provided by the connection portion 151a. The connection portion 151a is provided in a layer lower than the transistor 103 and the wiring layer 110. The connection portion 151a is electrically connected to the wiring 110k through a via 161k. More specifically, one end of the via 161k is connected to the connection portion 151a. The other end of the via 161k is connected to the wiring 110k through a contact hole 161k1.

[0076] The anode electrode of the light-emitting element 150 is provided by the p-type semiconductor layer 153 shown in FIG. 1. The wiring 110d extends to the surface including the light-emitting surface 153S through the opening 158. The p-type semiconductor layer 153 is connected to one end of the wiring 110d through the surface including the light-emitting surface 153S. The surface including the light-emitting surface 153S is in the same plane as the light-emitting surface 153S. One end of the wiring 110d is connected to the surface including the light-emitting surface 153S, and the remaining surface is the light-emitting surface 153S.

[0077] The other end of the wiring 110d is connected to the drain electrode of the transistor 103 through a via 111d. The drain electrode of the transistor 103 is the region 104d shown in FIG. 1. The source electrode of the transistor 103 is connected to the wiring 110s through a via 111s. The source electrode of the transistor 103 is the region 104s shown in FIG. 1. In this example, the wiring layer 110 includes a power line 3, and the wiring 110s is connected to the power line 3.

[0078] In this example, the ground line 4 is provided in a layer even higher than the wiring layer 110. Although not shown in Fig. 1, an interlayer insulating film is further provided on the wiring layer 110. The ground line 4 is provided on the uppermost interlayer insulating film and is insulated from the power line 3.

[0079] In this manner, by using the via 161k, the light emitting element 150 can be electrically connected to the wiring layer 110 provided in a layer above the light emitting element 150. In addition, the light emitting element 150 can be electrically connected to the wiring layer 110 provided in a layer above the light emitting element 150 by providing an opening 158 that exposes the light emitting surface 153S.

[0080] A method for manufacturing the image display device 1 of this embodiment will be described. 5A to 5C are schematic cross-sectional views illustrating a method for manufacturing the image display device of this embodiment. 5A, in the manufacturing method of the image display device 1 of this embodiment, a plurality of semiconductor growth substrates 1194 are prepared. Each of the plurality of semiconductor growth substrates 1194 includes a crystal growth substrate 1001, a buffer layer 1140, and a semiconductor layer 1150. The crystal growth substrate (first substrate) 1001 is, for example, a Si substrate or a sapphire substrate. Preferably, a Si substrate is used as the crystal growth substrate 1001. In addition, when a low-temperature crystal growth process such as a low-temperature sputtering method is used as described later, a less expensive glass substrate or the like can also be used.

[0081] The buffer layer 1140 is formed on one surface of the crystal growth substrate 1001. A nitride such as AlN is preferably used for the buffer layer 1140. By growing the semiconductor layer 1150 through the buffer layer 1140, it is possible to reduce mismatch at the interface between the GaN crystal and the crystal growth substrate 1001.

[0082] The semiconductor layer 1150 is formed on the buffer layer 1140. The semiconductor layer 1150 includes an n-type semiconductor layer 1151, an emission layer 1152, and a p-type semiconductor layer 1153. The n-type semiconductor layer 1151, the emission layer 1152, and the p-type semiconductor layer 1153 are stacked in this order from the buffer layer 1140 side. The semiconductor layer 1150 is formed, for example, by a chemical vapor deposition (CVD) method, and a metal organic chemical vapor deposition (MOCVD) method is preferably used. Alternatively, even at a process temperature of 700° C. or less, the semiconductor layer 1150 can be epitaxially grown by a low-temperature sputtering method, and thus the manufacturing cost can be reduced by using a glass substrate or device with low heat resistance. The semiconductor layer 1150 includes, for example, GaN, and more specifically, In X Al Y Ga 1-X-Y Includes N (0≦X, 0≦Y, X+Y<1), etc.

[0083] In the early stage of crystal growth, crystal defects due to mismatch of crystal lattice constants may occur, and crystals with crystal defects exhibit n-type. Therefore, when the semiconductor layer 1150 is formed from the n-type semiconductor layer 1151 on the crystal growth substrate 1001 as in this example, there is an advantage that the margin in the production process can be made large, and the yield can be easily improved.

[0084] 5B, after the semiconductor layer 1150 is formed on the buffer layer 1140, a support substrate 1190 is bonded to the exposed surface of the p-type semiconductor layer 1153. The support substrate 1190 is made of, for example, quartz glass or Si. After the support substrate 1190 is bonded to the semiconductor layer 1150, the crystal growth substrate 1001 is removed to form a substrate 1195 (second substrate). The crystal growth substrate 1001 is removed by, for example, wet etching or laser lift-off.

[0085] The steps up to forming semiconductor growth substrate 1194 and the steps of processing after forming substrate 1195 may be performed in the same plant or in different plants. For example, substrate 1195 may be manufactured in a first plant, and substrate 1195 may be carried into a second plant different from the first plant to perform the subsequent steps.

[0086] 5C, a plurality of substrates 1195 are bonded to one substrate 102 (third substrate). The semiconductor layers 1150 of the plurality of substrates 1195 are bonded to the first surface 102a of the single substrate 102 with the buffer layers 1140 interposed therebetween.

[0087] In the substrate bonding process, the surfaces of the substrates are bonded together. In this process, for example, the substrates are heated and thermocompressed to bond them together. A low melting point metal or a low melting point alloy may be used when performing the thermocompression bonding. The low melting point metal may be, for example, Sn or In, and the low melting point alloy may be an alloy mainly composed of, for example, Zn, In, Ga, Sn, Bi, or the like.

[0088] In the substrate bonding process, in addition to the above, the bonding surfaces of each substrate may be planarized using chemical mechanical polishing (CMP) or the like, and then the bonding surfaces may be cleaned by plasma treatment in a vacuum to adhere to each other.

[0089] The substrate 102 is, for example, a substantially rectangular glass substrate of about 1500 mm×1800 mm. The substrate 1195 is rectangular or square with a size of about 10 mm square to 150 mm square, and is, for example, about 4 inches to 6 inches in terms of wafer dimensions. The size of the substrate 102 is appropriately selected depending on the size of the image display device, etc. When the size of the substrate 102 is, for example, a rectangular or square with a size of about 10 mm square to 150 mm square, one semiconductor layer 1150 may be bonded to one substrate 102 as in the case of the second embodiment described later.

[0090] FIG. 6 is a perspective view illustrating a method for manufacturing the image display device of this embodiment. The diagram above the arrow in Fig. 6 shows that a plurality of substrates 1195 are arranged in a lattice pattern. The diagram below the arrow in Fig. 6 shows that substrate 102 is arranged. Fig. 6 shows by an arrow that the plurality of substrates 1195 arranged in a lattice pattern are bonded together at the positions indicated by the two-dot chain lines, as described below. Since the crystal quality deteriorates at and near the ends of the semiconductor layer 1150, care must be taken to avoid forming the light emitting element 150 at and near the ends of the semiconductor layer 1150. As shown in Fig. 6, the ends of the semiconductor layer 1150 are formed so as to almost coincide with the ends of the support substrate 1190. Therefore, the multiple substrates 1195 are arranged facing the substrate 102 in a lattice pattern, for example, as shown by the solid line in Fig. 6, so as to minimize gaps between adjacent substrates 1195. The semiconductor layer 1150 is bonded onto the substrate 102 via a buffer layer 1140, as shown by the two-dot chain line in Fig. 6.

[0091] When multiple semiconductor layers 1150 are bonded to one substrate 102, the substrate 102 to which the multiple semiconductor layers 1150 are bonded can be divided before or after the incorporation of color filters to produce image display devices of a number and size according to the number of divisions. Since it is preferable that the end of the semiconductor layer 1150 with reduced crystal quality becomes the end of the display region, the unit of division is preferably set to match the shape of the substrate 1195. The process of incorporation of color filters will be described later with reference to Fig. 12 and Figs. 13A to 13D.

[0092] 7A to 8B are schematic cross-sectional views illustrating a method for manufacturing the image display device of this embodiment. Figures 7A to 8B show two modified examples of the substrate bonding step. In the substrate bonding step, the steps of Figures 5A to 5C may be replaced with the steps of Figures 7A to 7C. Also, the steps of Figures 5A to 5C may be replaced with the steps of Figures 8A and 8B.

[0093] In the manufacturing process shown in FIGS. 7A to 7C, the semiconductor layer 1150 is formed on one surface of the crystal growth substrate 1001 without the buffer layer 1140 shown in FIG. 5A therebetween. As shown in Fig. 7A, a plurality of semiconductor growth substrates 1194a are prepared in place of the plurality of semiconductor growth substrates 1194 shown in Fig. 5A. Each of the plurality of semiconductor growth substrates 1194a includes a crystal growth substrate 1001 and a semiconductor layer 1150. The semiconductor layer 1150 is formed directly on one surface of the crystal growth substrate 1001. The semiconductor layer 1150 is formed by a CVD method, an MOCVD method, or the like, as in the case of Fig. 5A.

[0094] 7B, a support substrate 1190 is bonded to the exposed surface of the p-type semiconductor layer 1153. After the support substrate 1190 is bonded to the semiconductor layer 1150, the crystal growth substrate 1001 is removed by using wet etching, laser lift-off, or the like, to form a substrate 1195a.

[0095] 7C, the exposed surface of the n-type semiconductor layer 1151 is disposed opposite the first surface 102a of the substrate 102. Then, the exposed surface of the n-type semiconductor layer 1151 is bonded to the first surface 102a.

[0096] 8A and 8B, a semiconductor growth substrate 1294 is bonded to the substrate 102 without being transferred to a support substrate. In the semiconductor growth substrate 1294, the stacking order of the semiconductor layers formed on the crystal growth substrate 1001 differs from that in the cases of FIGS. 5A and 7A. 8A, each of the multiple semiconductor growth substrates 1294 includes a crystal growth substrate 1001 and a semiconductor layer 1150. The semiconductor layer 1150 is grown directly on one surface of the crystal growth substrate 1001. The semiconductor layer 1150 includes a p-type semiconductor layer 1153, a light emitting layer 1152, and an n-type semiconductor layer 1151. The p-type semiconductor layer 1153, the light emitting layer 1152, and the n-type semiconductor layer 1151 are stacked in this order from the crystal growth substrate 1001 side.

[0097] 8B, the semiconductor growth substrate 1294 is turned upside down, and the exposed surface of the n-type semiconductor layer 1151 is disposed opposite to the first surface 102a of the substrate 102. The exposed surface of the n-type semiconductor layer 1151 disposed opposite to the first surface 102a of the substrate 102 is bonded to the first surface 102a of the substrate 102.

[0098] Instead of the semiconductor growth substrate 1294, a buffer layer may be formed on the crystal growth substrate 1001, and the p-type semiconductor layer 1153, the light emitting layer 1152, and the n-type semiconductor layer 1151 may be formed on the buffer layer in this order from the buffer layer side. In this case, a step of removing the remaining buffer layer must be added either before or after the step of processing the semiconductor layer 1150 to form the light emitting element.

[0099] The method of bonding the semiconductor layer 1150 to the substrate 102 is not limited to the above, and the following method can also be used. That is, after the semiconductor layer 1150 is formed on the crystal growth substrate 1001, the semiconductor layer 1150 is housed in a container with the crystal growth substrate 1001 removed, and is stored, for example, with a support substrate 1190 attached in the container. After storage, the semiconductor layer 1150 is taken out of the container and bonded to the substrate 102. Alternatively, the semiconductor layer 1150 is stored in the container without being attached to the support substrate 1190. After storage, the semiconductor layer 1150 is taken out of the container and bonded to the substrate 102 as is.

[0100] Returning to the manufacturing process after the substrate bonding process, the explanation will be continued. 9A to 10B are schematic cross-sectional views illustrating a method for manufacturing the image display device of this embodiment. As shown in FIG. 9A, the support substrate 1190 shown in FIG. 5C is removed by wet etching, laser lift-off, or the like.

[0101] 6, the multiple substrates 1195 are disposed adjacent to each other and bonded to the substrate 102. Position X1 is a position where the ends of the adjacent substrates 1195 are disposed. At position X1, the ends of the semiconductor layer 1150 are also adjacent to each other and close to each other.

[0102] As shown in Fig. 9B, the semiconductor layer 1150 shown in Fig. 9A is processed into a desired shape by etching to form the light emitting element 150. The light emitting element 150 is formed at a position sufficiently away from the region including the position X1. The region including the position X1 is determined based on the evaluation result of the crystal quality near the end of the semiconductor layer 1150.

[0103] In the light emitting element 150, the connection portion 151a is formed, and then, by further etching, other portions are formed. In this way, it is possible to form the light emitting element 150 having the connection portion 151a protruding from the n-type semiconductor layer 151 on the first surface 102a in the positive direction of the X-axis. For example, a dry etching process is used to form the light emitting element 150, and preferably, anisotropic plasma etching (Reactive Ion Etching, RIE) is used. The buffer layer 1140 shown in FIG. 9A is etched together with the semiconductor layer 1150, and remains as the buffer layer 140 between the first surface 102a and the n-type semiconductor layer 151.

[0104] 9C, a first interlayer insulating film 156 (first insulating film) is formed to cover the first surface 102a, the buffer layer 140, and the light emitting element 150. The TFT lower film 106 is formed on the first interlayer insulating film 156 by, for example, CVD or the like.

[0105] The TFT channel 104 is formed at a predetermined position on the TFT underlayer film 106. For example, in the LTPS process, the transistor 103 is formed as follows. First, amorphous Si is deposited in the shape of the TFT channel 104. The amorphous Si film is deposited by, for example, CVD or the like. The deposited amorphous Si film is polycrystallized by laser annealing, and the TFT channel 104 is formed.

[0106] Thereafter, the source electrode and the drain electrode of the TFT channel 104 are formed by, for example, implanting B + The step of forming the source electrode and the drain electrode may be performed after the step of forming the gate 107.

[0107] The insulating layer 105 is formed over the TFT underlayer film 106 and the TFT channel 104. The insulating layer 105 is formed by, for example, CVD or the like. The gate 107 is formed at a position above the TFT channel 104 via the insulating layer 105. An appropriate formation method is used to form the gate 107 depending on the material of the gate 107. For example, when the gate 107 is polycrystalline Si, it is formed by laser annealing amorphous Si to polycrystallize it, similar to the TFT channel 104.

[0108] The second interlayer insulating film 108 (second insulating film) is provided so as to cover the insulating layer 105 and the gate 107. The second interlayer insulating film 108 is formed by a suitable manufacturing method depending on the material of the second interlayer insulating film 108. For example, when the second interlayer insulating film 108 is made of SiO 2 When the thin film is formed by the above method, techniques such as ALD and CVD are used.

[0109] The flatness of the second interlayer insulating film 108 may be sufficient to form the wiring layer 110, and the flattening step may not necessarily be performed. If the flattening step is not performed on the second interlayer insulating film 108, the number of steps can be reduced. For example, when there is a portion around the light emitting element 150 where the thickness of the second interlayer insulating film 108 is thin, the depth of the via hole 162k becomes shallow, so that a sufficient opening diameter can be ensured. Therefore, it becomes easy to ensure electrical connection by the via, and a decrease in yield due to poor electrical characteristics can be suppressed.

[0110] As shown in FIG. 10A, the via hole 162k is formed to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156, and reach the surface of the connection portion 151a. The opening 158 is formed to reach the light-emitting surface 153S by removing a part of the second interlayer insulating film 108, a part of the insulating layer 105, a part of the TFT lower film 106, and a part of the first interlayer insulating film 156. The part of the second interlayer insulating film 108, a part of the insulating layer 105, a part of the TFT lower film 106, and a part of the first interlayer insulating film 156 are the parts of these insulating layers and insulating films formed on the light-emitting surface 153S. The via hole 112d is formed to penetrate the second interlayer insulating film 108 and the insulating layer 105, and reach the surface of the region 104d. The via hole 112s is formed so as to penetrate the second interlayer insulating film 108 and the insulating layer 105 and expose the surface of the region 104s. The via hole and the opening are formed by, for example, RIE or the like.

[0111] As shown in Fig. 10B, the via 161k is formed by filling the via hole 162k shown in Fig. 10A with a conductive material. The vias 111d and 111s are also formed by filling the via holes 112d and 112s shown in Fig. 10A with a conductive material, respectively. Thereafter, the wiring layer 110 is formed on the second interlayer insulating film 108, and the wirings 110k, 110d, and 110s are formed. The wiring layer 110 may be formed simultaneously with the formation of the vias 161k, 111d, and 111s.

[0112] 11A and 11B are schematic cross-sectional views illustrating a manufacturing method of a modified example of the image display device of this embodiment. 11A and 11B show steps for forming the subpixel 20a shown in FIG. 2. In this modification, the steps from forming the second interlayer insulating film 108 to forming the via holes 162k, 112d, and 112s are the same as those described above. In the following description, it is assumed that the steps in FIG. 11A and FIG. 11B are performed after the step in FIG. 10A.

[0113] As shown in FIG. 11A, the vias 161k, 111d, and 111s are formed by filling the via holes 162k, 112d, and 112s shown in FIG. 10A with a conductive material. Then, the wiring layer 110 is formed, and the wirings 110k, 110d1, and 110s are formed. Here, one end of the wiring 110d1 is connected to the via 111d. Meanwhile, the other end of the wiring 110d1 is not directly connected to the light emitting surface 153S, and is located away from the opening 158. The vias 161k, 111d, and 111s and the wiring layer 110 may be formed simultaneously, as in the first embodiment.

[0114] As shown in FIG. 11B, a translucent electrode 159d is formed over the wiring 110d1 and the light-emitting surface 153S. The translucent electrode 159d is also formed between the wiring 110d1 and the light-emitting surface 153S, and electrically connects the wiring 110d1 and the light-emitting surface 153S. The translucent electrode 159s is formed over the wiring 110s. The translucent electrodes 159d and 159s are formed at the same time. When a translucent electrode is formed on the wiring 110k, it is formed at the same time as the translucent electrodes 159d and 159s. Note that the roughening treatment on the light-emitting surface 153S can be performed at any timing between the formation of the opening 158 and the formation of the translucent electrode 159d.

[0115] In this manner, the modified sub-pixel 20a is formed.

[0116] For example, the circuit in Fig. 3 is a drive circuit that drives a light-emitting element 150 by a selection transistor 24, a drive transistor 26, and a capacitor 28. Such a drive circuit is formed within the subpixels 20, 20a. Part of the circuits other than the drive circuit is formed outside the subpixels 20, 20a, for example, in the peripheral portion of the display area 2 shown in Fig. 1. For example, the row selection circuit 5 shown in Fig. 3 is formed simultaneously with the drive transistors, selection transistors, etc., and is formed in the peripheral portion of the display area 2. In other words, the row selection circuit 5 can be simultaneously incorporated by the above-mentioned manufacturing process.

[0117] The signal voltage output circuit 7 is preferably incorporated into a semiconductor device manufactured by a manufacturing process capable of high integration through microfabrication. The signal voltage output circuit 7 is mounted on a separate substrate together with a CPU and other circuit elements, and is connected to the sub-pixels 20, 20a via connectors or the like provided on the periphery of the display area, for example, before or after the incorporation of a color filter, which will be described later.

[0118] In the image display device 1 of this embodiment, each light emitting element 150 can form an image in the display region 2 by emitting light upward from the light emitting surface 153S. However, if light is scattered below the light emitting surface 153S, the light emitting efficiency is substantially reduced because the substrate 102 has translucency. Therefore, for example, a light reflecting film or a light reflecting plate can be provided on the surface of the substrate 102 facing the first surface 102a, so that the light scattered toward the substrate 102 can be reflected toward the light emitting surface 153S. Such a light reflecting film or the like may be provided on the substrate 102, or may be provided inside a case, a frame, or the like to which the image display device 1 is fixed.

[0119] 12A to 12C are schematic cross-sectional views illustrating a method for manufacturing the image display device of this embodiment. In Fig. 12, the diagram above the arrow shows a configuration including a color filter 180, and the diagram below the arrow shows a structure including the light-emitting element 150 formed in the above-mentioned process. In Fig. 12, the arrow shows the process of bonding a color filter to the structure including the light-emitting element 150. In FIG. 12, in order to avoid complication, components other than those on the illustrated substrate 102 are omitted. The omitted components are the buffer layer 140, the circuit 101 including the TFT channel 104 and the wiring layer 110, and the via 161k shown in FIG. 1. Also, FIG. 12 shows a part of a color conversion member such as a color filter 180. In the explanation related to FIG. 12 to FIG. 13D, the light emitting element 150, the first interlayer insulating film 156, the circuit 101, the TFT lower layer film 106, and the surface resin layer 170 are referred to as a light emitting circuit section 172, and a structure including the substrate 102, the light emitting circuit section 172, and the components whose illustration is omitted is referred to as a structure 1192. Note that in FIG. 12, among the components that constitute the circuit 101, the TFT channel 104, the vias 111s and 111d, and the wiring layer 110 are omitted from illustration.

[0120] 12, one surface of color filter (wavelength conversion member) 180 is bonded to structure 1192. The other surface of color filter 180 is bonded to glass substrate 186. One surface of color filter 180 is provided with transparent thin film adhesive layer 188, and color filter 180 is bonded to the exposed surface of surface resin layer 170 of structure 1192 via transparent thin film adhesive layer 188.

[0121] In this example, color filter 180 has color conversion sections arranged in the positive direction of the X-axis in the order of red, green, and blue. For red, red color conversion layer 183R is provided as the first layer, and for green, green color conversion layer 183G is provided as the first layer, and filter layer 184 is provided as the second layer in each case. For blue, single-layer color conversion layer 183B may be provided, or filter layer 184 may be provided. Light shielding sections 181 are provided between each color conversion section, and it goes without saying that the frequency characteristics of filter layer 184 can be changed for each color of color conversion section.

[0122] The color filter 180 is attached to the structure 1192 by aligning the positions of the color conversion layers 183 R, 183 G, and 183 B of each color with the position of the light emitting element 150 .

[0123] 13A to 13D are schematic cross-sectional views showing a modified example of the manufacturing method for the image display device of this embodiment. 13A to 13D show a method for forming a color filter by an inkjet method.

[0124] As shown in FIG. 13A, a structure 1192 is prepared in which components such as a light emitting element 150 are formed on a substrate 102.

[0125] 13B, light shielding portion 181 is formed on structure 1192. Light shielding portion 181 is formed by using, for example, screen printing, photolithography technology, or the like.

[0126] As shown in FIG. 13C, phosphors corresponding to the luminescent color are ejected from the inkjet nozzle to form the color conversion layer 183. The phosphors color the areas where the light-shielding portion 181 is not formed. For example, fluorescent paint using a general phosphor material, a perovskite phosphor material, or a quantum dot phosphor material is used as the phosphor. When a perovskite phosphor material or a quantum dot phosphor material is used, each luminescent color can be realized, and monochromaticity and color reproducibility are high, which is preferable. After drawing with the inkjet nozzle, a drying process is performed at an appropriate temperature and time. The thickness of the coating film during coloring is set to be thinner than the thickness of the light-shielding portion 181.

[0127] As already explained, for blue-emitting subpixels, if no color conversion section is formed, color conversion layer 183 is not formed. Furthermore, when forming a blue color conversion layer for a blue-emitting subpixel, if only one layer of color conversion section is required, the thickness of the coating of the blue phosphor is preferably approximately the same as the thickness of light-shielding section 181.

[0128] As shown in Fig. 13D, the paint for the filter layer 184 is sprayed from an inkjet nozzle. The paint is applied over the phosphor coating. The total thickness of the phosphor and paint coatings is approximately the same as the thickness of the light-shielding portion 181.

[0129] Whether it is a film-type color filter or an inkjet-type color filter, it is desirable that the color conversion layer 183 is as thick as possible in order to improve the color conversion efficiency. On the other hand, if the color conversion layer 183 is too thick, the emitted light of the color-converted light is approximated to Lambertian, whereas the emission angle of the blue light that is not color-converted is limited by the light shielding portion 181. This causes a problem that the display color of the displayed image becomes visual angle dependent. In order to match the light distribution of the subpixel in which the color conversion layer 183 is provided to the light distribution of the blue light that is not color-converted, it is desirable that the thickness of the color conversion layer 183 is about half the opening size of the light shielding portion 181.

[0130] For example, in the case of a high-definition image display device of about 250 ppi, the pitch of the subpixels 20 is about 30 μm, so the thickness of the color conversion layer 183 is preferably about 15 μm. Here, when the color conversion material is made of spherical phosphor particles, it is preferable that they are stacked in a close-packed structure to suppress light leakage from the light emitting element 150. For this reason, at least three particle layers are required. Therefore, the particle size of the phosphor material constituting the color conversion layer 183 is preferably about 5 μm or less, and more preferably about 3 μm or less.

[0131] FIG. 14 is a schematic perspective view illustrating the image display device according to the present embodiment. 14, the image display device of this embodiment has a light-emitting circuit section 172 having a large number of sub-pixels 20 provided on a substrate 102. A color filter 180 is provided on the light-emitting circuit section 172. Other embodiments and modified examples described later also have the same configuration as that shown in FIG.

[0132] The effects of the image display device 1 of this embodiment will be described. In the manufacturing method of the image display device 1 of this embodiment, after the semiconductor layer 1150 is bonded to the substrate 102, the semiconductor layer 1150 is etched to form the light emitting element 150. Thereafter, the light emitting element 150 is covered with a first interlayer insulating film 156, and the circuit 101 including circuit elements such as the transistor 103 that drives the light emitting element 150 is fabricated on the first interlayer insulating film 156. Therefore, the manufacturing process is significantly shortened compared to the case where the individual light emitting elements are individually transferred to the substrate 102.

[0133] For example, in an image display device with 4K image quality, the number of subpixels exceeds 24 million, and in the case of an image display device with 8K image quality, the number of subpixels exceeds 99 million. It takes a huge amount of time to individually form such a large number of light-emitting elements and mount them on a circuit board. Therefore, it is difficult to realize an image display device using micro LEDs at a realistic cost. Furthermore, if a large number of light-emitting elements are individually mounted, the yield rate decreases due to poor connection during mounting, and further cost increases are unavoidable. However, the manufacturing method for the image display device of this embodiment has the following effects.

[0134] As described above, in the manufacturing method of the image display device 1 of this embodiment, the semiconductor layer 1150 is entirely bonded to the substrate 102, and then the light emitting element is formed by etching, so that the transfer step is completed in one step. Therefore, in the manufacturing method of the image display device 1 of this embodiment, the time for the transfer step can be shortened and the number of steps can be reduced compared to the conventional manufacturing methods.

[0135] Furthermore, the semiconductor layer 1150 is bonded to the substrate 102 at the wafer level without being divided into individual pieces in advance or forming electrodes at positions corresponding to the circuit elements. Therefore, alignment is not required at the bonding stage. Therefore, the bonding process can be easily performed in a short time. Since alignment is not required at the time of bonding, the light emitting element 150 can be easily miniaturized, which is suitable for a high-definition display.

[0136] In this embodiment, for example, the glass substrate formed as described above is covered with an interlayer insulating film, and a driving circuit including TFTs and a scanning circuit can be formed on the planarized surface using an LTPS process, etc. Therefore, there is an advantage that the existing manufacturing process and plant for flat panel displays can be used.

[0137] In this embodiment, the light emitting element 150 formed below the transistor 103 etc. can be electrically connected to the power supply line, ground line, driving transistor etc. formed above by forming vias penetrating the first interlayer insulating film 156, the TFT lower film 106, the insulating layer 105 and the second interlayer insulating film 108. By using such a technically established multilayer wiring technique, a uniform connection structure can be easily realized and the yield can be improved. Therefore, a decrease in the yield due to poor connection of the light emitting element etc. is suppressed.

[0138] Second embodiment FIG. 15 is a schematic cross-sectional view illustrating a part of the image display device according to this embodiment. This embodiment differs from the other embodiments described above in that the light reflecting layer 120 including the light reflecting plate 120a is provided on the first surface 102a, and the light emitting element 250 is provided on the light reflecting plate 120a via the insulating layer 114. This embodiment differs from the other embodiments described above in that the n-type semiconductor layer 251 provides the light emitting surface 251S. This embodiment differs from the other embodiments described above in that the light emitting element 250 is driven by the transistor 203. The same components as those in the other embodiments are denoted by the same reference numerals, and detailed description thereof will be omitted as appropriate.

[0139] As shown in FIG. 15, the subpixel 220 of the image display device of this embodiment includes a substrate 102, a light reflecting layer 120, a light emitting element 250, a first interlayer insulating film 156, a transistor 203, a second interlayer insulating film 108, a via 261a, and a wiring layer 110.

[0140] The light reflecting layer 120 (a layer having light reflectivity) is provided on the first surface 102a. The light reflecting layer 120 includes a light reflecting plate 120a. The light reflecting plate 120a (first portion) is a film-like, layer-like, or plate-like member having a rectangular shape or any polygonal, elliptical, circular, or other shape in the XY plane view.

[0141] The light reflecting layer 120 includes a plurality of light reflecting plates 120a, and the light reflecting plates 120a are provided at locations where the light emitting elements 250 are provided. In this example, the plurality of light reflecting plates 120a are separated from each other.

[0142] The outer periphery of the light reflecting plate 120a may be set so as to include the outer periphery of the light emitting element 250 when the light emitting element 250 is projected in the XY plane view. The light reflecting plate 120a may be provided for each light emitting element 250, or for each of a plurality of light emitting elements 250. The light reflecting plate 120a may not be separated for each light emitting element 250, but may be connected in a lattice shape, for example. In that case, the light emitting element 250 is provided, for example, on the position of the lattice where the light reflecting plates 120a cross. The light reflecting layer 120 may be a single light reflecting plate 120a. The single light reflecting plate 120a is provided, for example, on the entire surface of the display area 2 shown in FIG. 2.

[0143] The light reflecting plate 120a is made of a material having light reflectivity. The light reflecting plate 120a is made of a metal material such as Ag or an alloy containing Ag. As long as the material has light reflectivity, it is not limited to Ag, and any other appropriate material can be used.

[0144] An insulating layer 114 is provided over the first surface 102a, the light reflecting layer 120, and the light reflecting plate 120a. The insulating layer 114 is made of SiO 2 The insulating layer 114 is formed of an oxide film or the like. The insulating layer 114 is provided to insulate the light reflecting plate 120a from the light emitting element 250. As will be described later, the insulating layer 114 also provides a flat surface when the substrates are bonded together.

[0145] The light emitting element 250 is provided on the light reflecting plate 120a via the insulating layer 114. The light emitting element 250 is provided directly above the light reflecting plate 120a.

[0146] By providing the light reflecting plate 120a in this manner, the light scattered downward from the light emitting element 250 is reflected upward by the light reflecting plate 120a. Therefore, the light emitting efficiency of the light emitting element 250 is substantially improved. Preferably, the outer periphery of the light reflecting plate 120a is set so as not to include the outer periphery of the transistor 203 when the transistor 203 is projected onto a plane including the light reflecting plate 120a in the XY plane view. By doing so, the transistor 203 is less likely to receive reflected light from the light reflecting plate 120a, and the probability of malfunction can be sufficiently reduced. The outer periphery of the transistor 203 in the XY plane view is the outer periphery of the TFT channel in the XY plane view.

[0147] The light emitting element 250 includes a light emitting surface 251S. As in the other embodiments described above, the light emitting element 250 is a prismatic or cylindrical element having a bottom surface 253B on the first surface 102a. The light emitting surface 251S is a surface facing the bottom surface 253B. In this example, the bottom surface 253B is a surface in contact with the insulating layer 114.

[0148] The light emitting element 250 includes a p-type semiconductor layer 253, a light emitting layer 252, and an n-type semiconductor layer 251. The p-type semiconductor layer 253, the light emitting layer 252, and the n-type semiconductor layer 251 are laminated in this order from the bottom surface 253B toward the light emitting surface 251S. In this embodiment, the light emitting surface 251S is provided by the n-type semiconductor layer 251. The n-type semiconductor layer 251 can have a lower resistance value than the p-type semiconductor layer 253, and therefore can be made thicker. Therefore, it is easy to roughen the light emitting surface 251S.

[0149] The light emitting element 250 includes a connection portion 253a. The connection portion 253a is provided on the insulating layer 114 so as to protrude in one direction from the p-type semiconductor layer 253. The height of the connection portion 253a is the same as or lower than the p-type semiconductor layer 253, and the light emitting element 250 is formed in a stepped shape. The connection portion 253a is p-type and is electrically connected to the p-type semiconductor layer 253. The connection portion 253a is connected to one end of the via 261a, and electrically connects the p-type semiconductor layer 253 to the via 261a.

[0150] The light emitting element 250 has a shape in the XY plane view similar to that of the light emitting element 150 of the other embodiment described above. An appropriate shape is selected depending on the layout of the circuit elements, etc. The shape of the light reflecting plate 120a in the XY plane view can be any shape as described above, and an appropriate shape is selected depending on the layout of the circuit elements, etc.

[0151] The light emitting element 250 is a light emitting diode similar to the light emitting element 150 of the other embodiments described above. That is, the wavelength of light emitted by the light emitting element 250 is, for example, blue light of about 467 nm±20 nm, or blue-violet light of about 410 nm±20 nm. The wavelength of light emitted by the light emitting element 250 is not limited to the above values ​​and can be any appropriate value.

[0152] The transistor 203 is provided on the TFT lower layer film 106. The transistor 203 is an n-channel TFT. The transistor 203 includes a TFT channel 204 and a gate 107. Preferably, the transistor 203 is formed by an LTPS process or the like, as in the other embodiments described above. In this embodiment, the circuit 101 includes the TFT channel 204, the insulating layer 105, the second interlayer insulating film 108, the vias 111s and 111d, and the wiring layer 110.

[0153] The TFT channel 204 includes regions 204s, 204i, and 204d. The regions 204s, 204i, and 204d are provided on the TFT lower layer film 106. The regions 204s and 204d are doped with phosphorus ions (P -The region 204s is doped with an n-type impurity such as ZnO. The region 204s is ohmic-connected to the via 111s. The region 204d is ohmic-connected to the via 111d.

[0154] The gate 107 is provided on the TFT channel 204 via an insulating layer 105. The insulating layer 105 insulates the TFT channel 204 from the gate 107.

[0155] In the transistor 203, when a voltage higher than that of the region 204s is applied to the gate 107, a channel is formed in the region 204i. The current flowing between the regions 204s and 204d is controlled by the voltage applied to the region 204s of the gate 107. The TFT channel 204 and the gate 107 are formed of the same material and by the same manufacturing method as the TFT channel 104 and the gate 107 in the above-mentioned other embodiments.

[0156] The wiring layer 110 includes wirings 110s, 110d1, and 210a. The wirings 110s and 110d1 are the same as those in the modified example of the first embodiment described above in FIG. 2. A part of the wiring 210a (first wiring) is provided above the connection portion 253a. The other part of the wiring 210a extends to, for example, a power supply line 3 shown in FIG. 16 described later, and is connected to the power supply line 3.

[0157] The vias 111s and 111d are provided penetrating the second interlayer insulating film 108. The via 111s is provided between the wiring 110s and the region 204s. The via 111s electrically connects the wiring 110s and the region 204s. The via 111d is provided between the wiring 110d1 and the region 204d. The via 111d electrically connects the wiring 110d1 and the region 204d. The vias 111s and 111d are formed using the same material and manufacturing method as in the other embodiments described above.

[0158] The via 261a is provided so as to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156. The via 261a is provided between the wiring 210a and the connection portion 253a, and electrically connects the wiring 210a and the connection portion 253a.

[0159] The wiring 110s (second wiring) is electrically connected to, for example, a ground line 4 shown in Fig. 16, which will be described later. The wiring 110d1 is electrically connected to the n-type semiconductor layer 251 via a light-transmitting electrode 159d.

[0160] In this embodiment, the translucent electrode 159d is provided over the roughened light emitting surface 251S of the n-type semiconductor layer 251. The translucent electrode 159d is provided over the wiring 110d1. The translucent electrode 159d is also provided between the light emitting surface 251S and the wiring 110d, and electrically connects the n-type semiconductor layer 251 and the wiring 110d. As in the other embodiments described above, the wiring 110d may be extended and directly connected to the n-type semiconductor layer 251, as in the example shown in FIG.

[0161] FIG. 16 is a schematic block diagram illustrating an image display device according to this embodiment. 16, an image display device 201 of this embodiment includes a display area 2, a row selection circuit 205, and a signal voltage output circuit 207. In the display area 2, as in the other embodiments described above, for example, sub-pixels 220 are arranged in a lattice pattern on the XY plane.

[0162] As in the other embodiments described above, pixel 10 includes multiple sub-pixels 220 that emit different colored light. Sub-pixel 220R emits red light. Sub-pixel 220G emits green light. Sub-pixel 220B emits blue light. The emission color and brightness of one pixel 10 are determined by the three types of sub-pixels 220R, 220G, and 220B emitting light at a desired brightness.

[0163] One pixel 10 includes three sub-pixels 220R, 220G, and 220B, which are arranged linearly on the X-axis as in this example. Each pixel 10 may have sub-pixels of the same color arranged in the same column, or may have sub-pixels of different colors arranged in different columns as in this example.

[0164] The subpixel 220 includes a light emitting element 222, a select transistor 224, a drive transistor 226, and a capacitor 228. In Figure 16, the select transistor 224 may be labeled T1, the drive transistor 226 may be labeled T2, and the capacitor 228 may be labeled Cm.

[0165] In this embodiment, the light emitting element 222 is provided on the power supply line 3 side, and the driving transistor 226 connected in series to the light emitting element 222 is provided on the ground line 4 side. In other words, the driving transistor 226 is connected to a lower potential side than the light emitting element 222. The driving transistor 226 is an n-channel transistor.

[0166] The selection transistor 224 is connected between the gate electrode of the driving transistor 226 and the signal line 208. The capacitor 228 is connected between the gate electrode of the driving transistor 226 and the ground line 4.

[0167] The row selection circuit 205 and the signal voltage output circuit 207 supply a signal voltage of a different polarity from that in the other embodiments described above to the signal line 208 in order to drive the drive transistor 226, which is an n-channel transistor.

[0168] In this embodiment, the polarity of the driving transistor 226 is n-channel, and therefore the polarity of the signal voltage and the like differ from those of the other embodiments described above. That is, the row selection circuit 205 supplies a selection signal to the scanning line 206 to sequentially select one row from the array of m rows of sub-pixels 220. The signal voltage output circuit 207 supplies a signal voltage having a required analog voltage value to each sub-pixel 220 of the selected row. The driving transistor 226 of the sub-pixel 220 of the selected row passes a current according to the signal voltage to the light-emitting element 222. The light-emitting element 222 emits light with a luminance according to the current that has passed.

[0169] A method for manufacturing the image display device of this embodiment will be described.

[0170] 17A to 19B are schematic cross-sectional views illustrating a method for manufacturing the image display device of this embodiment. 17A, in the manufacturing method of the image display device of this embodiment, one semiconductor growth substrate (second substrate) 1194a is prepared and bonded to one substrate 102 (third substrate). As in the other embodiments described above, a plurality of semiconductor growth substrates can be prepared and bonded to one substrate 102. The other embodiments described above and their various modified examples can be applied to the method of bonding the semiconductor layer 1150 to the substrate 102.

[0171] The semiconductor growth substrate 1194a has a semiconductor layer 1150 formed on a crystal growth substrate (first substrate) 1001. As already described, the crystal growth substrate 1001 is, for example, a Si substrate or a sapphire substrate, and is preferably a Si substrate. Alternatively, when a low-temperature crystallization process is used, a less expensive glass substrate can also be used.

[0172] The semiconductor layer 1150 includes an n-type semiconductor layer 1151, a light emitting layer 1152, and a p-type semiconductor layer 1153. The n-type semiconductor layer 1151, the light emitting layer 1152, and the p-type semiconductor layer 1153 are laminated in this order from the crystal growth substrate 1001 side. The semiconductor layer 1150 is formed in the same manner as in the other embodiments described above, and can be formed as a low-temperature process at 700° C. or less by epitaxial growth using a CVD method, an MOCVD method, or a low-temperature sputtering method.

[0173] The light reflecting layer 120 (a layer having light reflectivity) is formed on the first surface 102a before the semiconductor layer 1150 is bonded to the substrate 102. The light reflecting layer 120 may be formed by sputtering or the like, or may be formed by applying Ag paste or the like to the shape of the light reflecting plate 120a and then baking it. The light reflecting plate 120a of the light reflecting layer 120 is provided at a position where the light emitting element 250 is to be formed. The insulating layer 114 is formed over the first surface 102a, the light reflecting layer 120, and the light reflecting plate 120a before the semiconductor layer 1150 is bonded to the substrate 102. The insulating layer 114 is formed by CVD or the like. The exposed surface of the insulating layer 114 is the surface to be bonded to the substrate 102, and is therefore planarized by CMP or the like.

[0174] The semiconductor growth substrate 1194a is disposed so that the exposed surface of the p-type semiconductor layer 1153 faces the planarized exposed surface of the insulating layer 114 provided on the substrate 102. The exposed surface of the p-type semiconductor layer 1153 is bonded to the exposed surface of the insulating layer 114.

[0175] As shown in FIG. 17B, the crystal growth substrate 1001 shown in FIG. 17A is removed by wet etching, laser lift-off, or the like.

[0176] As shown in Fig. 17C, the semiconductor layer 1150 shown in Fig. 17B is shaped into a desired shape by etching to form the light emitting element 250. As in the first embodiment, the light emitting element 250 is formed after the connection portion 253a is formed, and the remaining portion is formed. The light emitting element 250 is formed, for example, by a dry etching process, preferably by RIE.

[0177] As shown in FIG. 18A, a first interlayer insulating film 156 is formed to cover the insulating layer 114 and the light emitting element 250. As shown in FIG.

[0178] 18B, the TFT lower layer film 106 is formed over the first interlayer insulating film 156 by CVD or the like. The TFT channel 204 is formed on the planarized TFT lower layer film 106. An insulating layer 105 is formed to cover the TFT lower layer film 106 and the TFT channel 204. A gate 107 is formed on the TFT channel 204 with the insulating layer 105 interposed therebetween. A second interlayer insulating film 108 is formed to cover the insulating layer 105 and the gate 107.

[0179] As shown in FIG. 19A, the via hole 162a is formed to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156, and reach the surface of the connection portion 253a. The opening 158 is formed to reach the light-emitting surface 251S by removing a part of the second interlayer insulating film 108, a part of the insulating layer 105, a part of the TFT lower film 106, and a part of the first interlayer insulating film 156. The part of the second interlayer insulating film 108, a part of the insulating layer 105, a part of the TFT lower film 106, and a part of the first interlayer insulating film 156 are the parts of these insulating layers and insulating films formed on the light-emitting surface 251S. The via hole 112d is formed to penetrate the second interlayer insulating film 108 and the insulating layer 105, and reach the surface of the region 204d. The via hole 112s is formed to penetrate the second interlayer insulating film 108 and the insulating layer 105, and reach the surface of the region 204s. The via holes and openings are formed by, for example, RIE.

[0180] As shown in Fig. 19B, the via 261a is formed by filling the via hole 162a shown in Fig. 19A with a conductive material. The vias 111d and 111s are also formed by filling the via holes 112d and 112s shown in Fig. 19A with a conductive material, respectively. Thereafter, the wiring layer 110 is formed, and the wirings 210a, 110d1, and 110s are formed. The wiring layer 110 may be formed simultaneously with the formation of the vias 261a, 111d1, and 111s.

[0181] A light-transmitting conductive film is formed to cover the second interlayer insulating film 108, the light-emitting surface 251S, and the wiring layer 110. Desired light-transmitting electrodes 159d, 159s are formed by photolithography.

[0182] A translucent electrode 159d is formed over the light-emitting surface 251S and the wiring 110d1. The translucent electrode 159d is also formed between the light-emitting surface 251S and the wiring 110d, and electrically connects the light-emitting surface 251S and the wiring 110d. The translucent electrode 159s is formed over the wiring 110s. The translucent electrodes 159d and 159s are formed at the same time. The translucent electrode may be formed on the wiring 210a.

[0183] Thereafter, a color filter 180 (wavelength conversion member) and the like are provided to form the sub-pixels 220 of the image display device 201 of this embodiment.

[0184] The effects of the image display device of this embodiment will be described. In the image display device of this embodiment, similarly to the other embodiments described above, the time required for the transfer process for forming the light emitting element 250 can be shortened, and the number of processes can be reduced. In addition, by using the n-type semiconductor layer 251 as the light emitting surface 251S, the light emitting surface 251S can be sufficiently roughened. Therefore, the light emitting efficiency is improved, and an increase in loss due to contact resistance can be suppressed.

[0185] (Third embodiment) FIG. 20 is a schematic cross-sectional view illustrating a part of the image display device according to the present embodiment. This embodiment differs from the other embodiments described above in that a light emitting element 250 having an n-type semiconductor layer 251 as a light emitting surface 251S is driven by a p-type transistor 103. The same components as those in the other embodiments described above are denoted by the same reference numerals, and detailed description thereof will be omitted as appropriate.

[0186] 20, a subpixel 320 of the image display device of this embodiment includes a substrate 102, a light-emitting element 250, a first interlayer insulating film 156, a transistor 103, a second interlayer insulating film 108, a via 361a, and a wiring layer 110. The transistor 103 is a p-channel TFT. The light-emitting element 250 provides a light-emitting surface 251S by an n-type semiconductor layer 251.

[0187] The light emitting element 250 is provided on the light reflecting plate 120a via the insulating layer 114. The light reflecting plate 120a is provided in the same configuration as in the other embodiments described above. The light reflecting plate 120a is provided directly below the light emitting element 250. The outer periphery of the light reflecting plate 120a is set so as to include the outer periphery of the light emitting element 250 when the light emitting element 250 is projected in the XY plane view. The light reflecting plate 120a reflects the scattered light downward from the light emitting element 250 to the light emitting surface 251S side, thereby substantially improving the light emitting efficiency.

[0188] The light emitting element 250 is a prismatic or cylindrical element having a bottom surface 253B on the first surface 102a. The light emitting surface 251S is a surface facing the bottom surface 253B. The bottom surface 253B is a surface in contact with the insulating layer 114 in this example.

[0189] The light emitting element 250 includes a p-type semiconductor layer 253, a light emitting layer 252, and an n-type semiconductor layer 251. The p-type semiconductor layer 253, the light emitting layer 252, and the n-type semiconductor layer 251 are laminated in this order from the bottom surface 253B toward the light emitting surface 251S. The p-type semiconductor layer 253 includes a connection portion 253a. The connection portion 253a is provided so as to protrude from the p-type semiconductor layer 253 in one direction on the insulating layer 114. The connection portion 253a is connected to one end of the via 361a, and electrically connects the p-type semiconductor layer 253 to the via 361a.

[0190] The configuration of the transistor 103 is the same as that of the first embodiment, and a detailed description of the configuration of the transistor 103 will be omitted.

[0191] The wiring layer 110 is formed on the second interlayer insulating film 108. The wiring layer 110 includes wirings 310k, 310a, 110d1, and 110s. The wirings 310a and 310k are provided above the light-emitting element 250 and in close proximity to the light-emitting element 250. The wiring 310a (third wiring) is provided above the connection portion 253a. The wiring 310k (fourth wiring) is provided at a position that does not intersect with the wiring 310a.

[0192] The via 361a is provided so as to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156. The via 361a is provided between the wiring 310a and the connection portion 253a. The via 361a electrically connects the wiring 310a and the connection portion 253a.

[0193] The vias 111d and 111s are provided in the same manner as in the other embodiments described above.

[0194] The transparent electrode 359k is provided over the wiring 310k. The transparent electrode 359k is provided over the light-emitting surface 251S. The transparent electrode 359k is also provided between the wiring 310k and the light-emitting surface 251S, and electrically connects the wiring 310k and the light-emitting surface 251S. The wiring 310k and the transparent electrode 359k are connected to the ground line 4 shown in FIG. 3, for example. Therefore, the n-type semiconductor layer 251 is electrically connected to the ground line 4 via the light-emitting surface 251S, the transparent electrode 359k, and the wiring 310k.

[0195] A transparent electrode 359d is provided over the wiring 310a. A transparent electrode 359d is provided over the wiring 110d1. A transparent electrode 359k is also provided between the wiring 310a and the wiring 110d1, and electrically connects the wiring 310a and the wiring 110d1. Therefore, the p-type semiconductor layer 253 is electrically connected to the region 104d through the connection portion 253a, the via 361a, the wiring 310a, the transparent electrode 359d, the wiring 110d1, and the via 111d.

[0196] The transparent electrode 159s is provided over the wiring 110s. The wiring 110s and the transparent electrode 159s are connected to the power line 3 shown in Fig. 3, for example. Therefore, the region 104s of the transistor 103 is electrically connected to the power line 3 through the via 111s, the wiring 110s, and the transparent electrode 159s.

[0197] The vias 361a, 111d, and 111s and the wirings 310k, 310a, 110d1, and 110s are formed from the same materials and by the same manufacturing method as in the above-mentioned other embodiments and their modified examples.

[0198] As in the other embodiments described above, a color filter 180 and the like are further provided.

[0199] A method for manufacturing the image display device of this embodiment will be described. 21A to 22B are schematic cross-sectional views illustrating a method for manufacturing the image display device of this embodiment. The steps up to bonding the semiconductor layer 1150 formed on the crystal growth substrate 1001 to the substrate 102 on which the light reflecting layer 120 and the insulating layer 114 are formed can be the same as those in the second embodiment. The method of bonding the substrates described in the first embodiment may be used. In the following description, it is assumed that the steps in Fig. 17B and subsequent steps are performed in the steps of Fig. 21A to Fig. 22B.

[0200] As shown in Fig. 21A, the semiconductor layer 1150 shown in Fig. 17B is processed into a desired shape to form the light emitting element 250. After the connection portion 253a is formed, other portions of the light emitting element 250 are formed.

[0201] 21B, a first interlayer insulating film 156 is formed to cover the insulating layer 114 and the light emitting element 250. In the same manner as in the first embodiment, a TFT lower film 106 is formed, a TFT channel 104 is formed, an insulating layer 105 is formed, and a gate 107 is formed. A second interlayer insulating film 108 is formed to cover the insulating layer 105 and the gate 107.

[0202] 22A, the via hole 362a is formed to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156, and to reach the surface of the connecting portion 253a. The opening 158 and the via holes 112d and 112s are formed in the same manner as in the other embodiments described above.

[0203] As shown in Fig. 22B, the via holes 362a, 112d, and 112s shown in Fig. 22A are filled with a conductive material to form vias 361a, 111d, and 111s. The wiring layer 110 is formed on the second interlayer insulating film 108. A light-transmitting conductive film is formed on the wiring layer 110, and light-transmitting electrodes 359k, 359d, and 159s are formed.

[0204] According to the image display device of this embodiment, it is possible to configure a circuit in which the n-type semiconductor layer 251 is the light-emitting surface 251S, and the p-channel transistor 103 drives the light-emitting element 250. This provides the effect of facilitating roughening of the light-emitting surface, as in the second embodiment. In addition, by roughening the light-emitting surface, the light-emitting efficiency is improved, and an increase in loss due to contact resistance can be suppressed.

[0205] (Fourth embodiment) FIG. 23 is a schematic cross-sectional view illustrating a part of the image display device according to the present embodiment. The image display device of this embodiment includes a flexible substrate 402 instead of a glass substrate. Light emitting elements and circuit elements such as transistors are formed on a first surface 402a of the substrate 402. In other respects, the present embodiment is similar to the other embodiments described above, and the same components are denoted by the same reference numerals and detailed description thereof will be omitted as appropriate.

[0206] As shown in Fig. 23, the image display device of this embodiment includes a subpixel 420. The subpixel 420 includes a substrate 402. The substrate 402 includes a first surface 402a. A layer 113 containing a silicon compound is formed on the first surface 402a. The layer 113 containing a silicon compound is, for example, SiO 2 and SiN x The light reflecting layer 120 is formed on the layer 113 containing a silicon compound. The layer 113 containing a silicon compound is provided to improve adhesion with the light reflecting layer 120 formed of a metal material.

[0207] An insulating layer 114 is formed over the layer 113 containing a silicon compound and the light reflecting layer 120. The insulating layer 114 is planarized by CMP or the like.

[0208] The light emitting element 250 is provided on the light reflecting plate 120a via the insulating layer 114. In this example, the structure and components above the insulating layer 114 are the same as those in the second embodiment described above, and detailed description thereof will be omitted.

[0209] The substrate 402 is flexible. The substrate 402 is formed of, for example, polyimide resin. The first interlayer insulating film 156, the second interlayer insulating film 108, the wiring layer 110, and the like are preferably formed of a material having a certain degree of flexibility according to the flexibility of the substrate 402. The wiring layer 110, which has the longest wiring length, is at the highest risk of being broken when bent. Therefore, it is desirable to adjust the film thickness, film quality, and material of each layer so that the neutral plane including multiple protective films added to the front and back surfaces as necessary is located at the position of the wiring layer 110.

[0210] In this example, the structure and components above the insulating layer 114 are the same as in the second embodiment, although other embodiments and variations are possible.

[0211] A method for manufacturing the image display device of this embodiment will be described. 24A and 24B are schematic cross-sectional views illustrating a method for manufacturing the image display device of this embodiment. As shown in FIG. 24A, in this embodiment, a substrate 1002 different from those in the other embodiments described above is prepared. The substrate 1002 (fourth substrate) includes two layers of substrates 102 and 402. The substrate 102 is, for example, a glass substrate. The substrate 402 is provided on the first surface 102a of the substrate 102. For example, the substrate 402 is formed by applying a polyimide material onto the first surface 102a of the substrate 102 and baking it. Before forming the substrate 402, a SiN x Alternatively, an inorganic film such as a polyimide film or the like may be formed. In this case, the substrate 402 is formed by applying a polyimide material onto the inorganic film and baking it. A layer 113 containing a silicon compound is formed over the first surface 402a of the substrate 402. The first surface 402a of the substrate 402 is the surface opposite to the surface on which the substrate 102 is provided.

[0212] By applying the steps described above with reference to, for example, FIGS. 17A to 19B and 12 to 13D to such a substrate 1002, the upper structure of the sub-pixels 420 is formed.

[0213] As shown in FIG. 24B, the substrate 102 is removed from the structure on which an upper structure including a color filter (not shown) is formed. For example, laser lift-off or the like is used to remove the substrate 102. The substrate 102 can be removed not only at the above-mentioned time point, but also at other appropriate time points. For example, the substrate 102 may be removed after substrate bonding or before the formation of a color filter. By removing the substrate 102 at an earlier time point, defects such as cracks and chips during the manufacturing process can be reduced.

[0214] The effects of the image display device of this embodiment will be described.

[0215] Since the substrate 402 is flexible, it can be bent to form an image display device, and can be attached to a curved surface or used in a wearable device or the like without any sense of incongruity.

[0216] Fifth embodiment FIG. 25 is a schematic cross-sectional view illustrating a part of the image display device according to the present embodiment. In this embodiment, a display device with higher light emission efficiency is realized by forming a plurality of light emitting surfaces 551S1 and 551S2 on a single semiconductor layer 550 including a light emitting layer. In the following description, the same components as those in the other embodiments described above are denoted by the same reference numerals, and detailed description thereof will be omitted as appropriate.

[0217] As shown in FIG. 25, the image display device of the present embodiment includes a subpixel group 520. The subpixel group 520 includes a substrate 102, a semiconductor layer 550, a first interlayer insulating film 156, transistors 103-1 and 103-2, a second interlayer insulating film 108, vias 561a1 and 561a2, and a wiring layer 110. The semiconductor layer 550 is provided on the first surface 102a side of the substrate 102. In this example, a light reflecting layer 120 is provided between the substrate 102 and the semiconductor layer 550. The light reflecting layer 120 is provided on the first surface 102a. The light reflecting layer 120 includes a light reflecting plate 120a. An insulating layer 114 covers the first surface 102a, the light reflecting layer 120, and the light reflecting plate 120a. The insulating layer 114 is planarized.

[0218] In this embodiment, holes are injected from one side of the semiconductor layer 550 through the wiring layer 110 and the vias 561a1 and 561a2 by turning on the p-channel transistors 103-1 and 103-2. Electrons are injected from the other side of the semiconductor layer 550 through the wiring layer 110 by turning on the p-channel transistors 103-1 and 103-2. Holes and electrons are injected into the semiconductor layer 550, and the light-emitting layer 552 emits light due to the combination of the holes and electrons. The driving circuit for driving the light-emitting layer 552 may have the circuit configuration shown in FIG. 3, for example. Using the other embodiment described above, the n-type semiconductor layer and the p-type semiconductor layer of the semiconductor layer may be swapped up and down to drive the semiconductor layer with n-channel transistors. In that case, the driving circuit may have the circuit configuration shown in FIG. 16.

[0219] The configuration of the sub-pixel group 520 will now be described in detail. The semiconductor layer 550 is provided on the light reflecting plate 120a via the insulating layer 114. The outer periphery of the light reflecting plate 120a is set to include the outer periphery of the semiconductor layer 550 when the semiconductor layer 550 is projected onto the light reflecting plate 120a in the XY plane view. Preferably, the outer periphery of the light reflecting plate 120a is set not to include the outer periphery of the transistors 103-1 and 103-2 when the transistors 103-1 and 103-2 are projected onto a surface including the light reflecting plate 120a in the XY plane view. The outer periphery of the transistors 103-1 and 103-2 in the XY plane view is the outer periphery of the TFT channels 104-1 and 104-2 in the XY plane view.

[0220] The semiconductor layer 550 includes a plurality of light emitting surfaces 551S1 and 551S2. The semiconductor layer 550 is a prismatic or cylindrical laminate having a bottom surface 553B on the first surface 102a. The light emitting surfaces 551S1 and 551S2 are surfaces facing the bottom surface 553B of the semiconductor layer 550. In this example, the bottom surface 553B is a surface in contact with the insulating layer 114. The light emitting surfaces 551S1 and 551S2 are preferably surfaces in substantially parallel planes. The substantially parallel planes may be the same plane or different planes. The light emitting surfaces 551S1 and 551S2 are provided at a distance from each other.

[0221] The semiconductor layer 550 includes a p-type semiconductor layer 553, a light emitting layer 552, and an n-type semiconductor layer 551. The p-type semiconductor layer 553, the light emitting layer 552, and the n-type semiconductor layer 551 are stacked in this order from a bottom surface 553B toward light emitting surfaces 551S1 and 551S2.

[0222] The p-type semiconductor layer 553 includes connection portions 553a1 and 553a2. The connection portion 553a1 is provided so as to protrude in one direction from the p-type semiconductor layer 553 on the insulating layer 114. The connection portion 553a2 is provided so as to protrude in a direction different from the connection portion 553a1 from the p-type semiconductor layer 553 on the insulating layer 114. The height of the connection portions 553a1 and 553a2 is lower than the height of the semiconductor layer 550, and as in this example, is the same as or lower than the height of the p-type semiconductor layer 553, and the semiconductor layer 550 is formed in a stepped shape.

[0223] The connecting portion 553a1 is p-type, and electrically connects the via 561a1 connected at one end to the connecting portion 553a1 to the p-type semiconductor layer 553. The connecting portion 553a2 is p-type, and electrically connects the via 561a2 connected at one end to the connecting portion 553a2 to the p-type semiconductor layer 553.

[0224] The n-type semiconductor layer 551 has two light emitting surfaces 551S1 and 551S2 on the upper surface. The two light emitting surfaces 551S1 and 551S2 are arranged spaced apart from each other. That is, one subpixel group 520 substantially includes two subpixels. In this embodiment, as in the other embodiments described above, the subpixel groups 520 each substantially including two subpixels are arranged in a lattice pattern to form a display area.

[0225] The protruding direction of the connection parts 553a1 and 553a2 is determined, for example, according to the arrangement of the light emitting surfaces 551S1 and 551S2. The connection part 553a1 is provided, for example, so that the distance from the light emitting surface 551S1 is shorter than the distance from the light emitting surface 551S2. That is, the connection part 553a1 is provided at a position closer to the light emitting surface 553S1 than the light emitting surface 553S2. The connection part 553a2 is provided, for example, so that the distance from the light emitting surface 551S2 is shorter than the distance from the light emitting surface 551S1. That is, the connection part 553a2 is provided at a position closer to the light emitting surface 551S2 than the light emitting surface 551S1.

[0226] The first interlayer insulating film 156 (first insulating film) covers the connecting portions 553a1, 553a2, the side surfaces of the p-type semiconductor layer 553, the side surfaces of the light emitting layer 552, and the side surfaces of the n-type semiconductor layer 551. The first interlayer insulating film 156 covers a part of the upper surface of the n-type semiconductor layer 551. Of the n-type semiconductor layer 551, the light emitting surfaces 551S1, 551S2 are not covered with the first interlayer insulating film 156. The first interlayer insulating film 156 is preferably a white resin, as in the other embodiments described above.

[0227] The TFT lower film 106 is formed over the first interlayer insulating film 156. The TFT lower film 106 is not provided over the light emitting surfaces 551S1 and 551S2. The TFT lower film 106 is flattened, and the TFT channels 104-1, 104-2, etc. are formed on the TFT lower film 106.

[0228] The insulating layer 105 covers the TFT lower layer film 106 and the TFT channels 104-1 and 104-2. The gate 107-1 is provided on the TFT channel 104-1 via the insulating layer 105. The gate 107-2 is provided on the TFT channel 104-2 via the insulating layer 105. The transistor 103-1 includes the TFT channel 104-1 and the gate 107-1. The transistor 103-2 includes the TFT channel 104-2 and the gate 107-2.

[0229] A second interlayer insulating film 108 (second insulating film) covers the insulating layer 105 and the gates 107-1 and 107-2.

[0230] The TFT channels 104-1 and 104-2 include p-type doped regions, and the transistors 103-1 and 103-2 are p-channel TFTs. The transistor 103-1 is provided at a position closer to the light emitting surface 551S1 than the light emitting surface 551S2. The transistor 103-2 is provided at a position closer to the light emitting surface 551S2 than the light emitting surface 551S1.

[0231] An opening 558-1 is provided above the light-emitting surface 551S1. An opening 558-2 is provided above the light-emitting surface 551S2. The second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156 are not provided in the openings 558-1 and 558-2, and the light-emitting surfaces 551S1 and 551S2 are exposed from the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156.

[0232] A transparent electrode 559k is provided over the light-emitting surfaces 551S1 and 551S2. Electrons are injected through the transparent electrode 559k and the light-emitting surfaces 551S1 and 551S2. The light-emitting surfaces 551S1 and 551S2 are covered with the transparent electrode 559k, and the openings 558-1 and 558-2 are filled with the surface resin layer 170.

[0233] The light emitting surfaces 551S1 and 551S2 are square, rectangular, other polygonal, circular, etc., in the XY plane view. The shape of the top of the openings 558-1 and 558-2 can also be square, rectangular, other polygonal, circular, etc. In order to reduce the loss of light caused by reflection on the wall surface of the openings 558-1 and 558-2, it is preferable that the openings 558-1 and 558-2 are formed in a tapered shape so that the area becomes wider toward the top, as in this example. In the XY plane view, the shape of the light emitting surfaces 551S1 and 551S2 and the shape of the top of the openings 558-1 and 558-2 may or may not be similar.

[0234] The wiring layer 110 is provided on the second interlayer insulating film 108. The wiring layer 110 includes wirings 510s1, 510d1, 510k, 510d2, and 510s2.

[0235] The wiring 510k is provided between the light emitting surface 551S1 and the light emitting surface 551S2. A transparent electrode 559k is provided over the wiring 510k. The wiring 510k and the transparent electrode 559k are connected to, for example, the ground line 4 in FIG.

[0236] The vias 111d1, 111s1, 111d2, and 111s2 are provided through the second interlayer insulating film 108, the insulating layer 105, and the TFT lower film 106. The via 111d1 is provided between one region of the transistor 103-1 that is doped with p-type and the wiring 510d1. The via 111s1 is provided between the other region of the transistor 103-1 that is doped with p-type and the wiring 510s1. The via 111d2 is provided between one region of the transistor 103-2 that is doped with p-type and the wiring 510d2. The via 111s2 is provided between the other region of the transistor 103-2 that is doped with p-type and the wiring 510s2.

[0237] The wiring 510d1 is provided above the connection portion 553a1. The wiring 510d1 is connected to the p-type region corresponding to the drain electrode of the transistor 103-1 through the via 111d1. The wiring 510s1 is connected to the p-type region corresponding to the source electrode of the transistor 103-1 through the via 111s1. The wiring 510d2 is provided above the connection portion 553a2. The wiring 510d2 is connected to the region corresponding to the drain electrode of the transistor 103-2 through the via 111d2. The wiring 510s2 is connected to the region corresponding to the source electrode of the transistor 103-2 through the via 111s2.

[0238] The via 561a1 is provided to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156. The via 561a1 is provided between the connection portion 553a1 and the wiring 510d1, and electrically connects the connection portion 553a1 and the wiring 510d1.

[0239] The via 561a2 is provided to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156. The via 561a2 is provided between the connection portion 553a2 and the wiring 510d2, and electrically connects the connection portion 553a2 and the wiring 510d2.

[0240] The transistors 103-1 and 103-2 are driving transistors of adjacent subpixels and are driven sequentially. Holes supplied from one of the two transistors 103-1 and 103-2 are injected into the light-emitting layer 552, and electrons supplied from the wiring 510k are injected into the light-emitting layer 552, causing the light-emitting layer 552 to emit light.

[0241] In this embodiment, the drift current flowing in a direction parallel to the XY plane is suppressed by the resistance of the n-type semiconductor layer 551 and the p-type semiconductor layer 553. Therefore, the electrons injected from the light emitting surfaces 551S1 and 551S2 and the holes injected from the vias 561a1 and 561a2 all proceed along the stacking direction of the semiconductor layer 550. Since the outside of the light emitting surfaces 551S1 and 551S2 rarely become a light emission source, the multiple light emitting surfaces 551S1 and 551S2 provided on one semiconductor layer 550 can be made to emit light by the transistors 103-1 and 103-2, respectively.

[0242] As described above, since the outside of the light emitting surfaces 551S1 and 551S2 does not become a light source, the light reflecting plate 120a may be provided for each of the light emitting surfaces 551S1 and 551S2.

[0243] A method for manufacturing the image display device of this embodiment will be described. 26A to 28B are schematic cross-sectional views illustrating a method for manufacturing the image display device of this embodiment. As shown in Fig. 26A, a semiconductor growth substrate (second substrate) 1194a and a substrate 102 (third substrate) are prepared. The substrate 102 is provided in advance with a light reflecting layer 120 including a light reflecting plate 120a on a first surface 102a, and an insulating layer 114 covering the light reflecting layer 120. The semiconductor growth substrate 1194a is the same as that shown in Fig. 6A, and detailed description thereof will be omitted. The substrates are bonded to each other by bonding the exposed surface of the p-type semiconductor layer 1153 formed on the semiconductor growth substrate 1194a to the planarized insulating layer 114.

[0244] As shown in Fig. 26B, the crystal growth substrate 1001 shown in Fig. 26A is removed. For example, wet etching, laser lift-off, or the like is used to remove the crystal growth substrate 1001.

[0245] As shown in Fig. 26C, the semiconductor layer 1150 shown in Fig. 26B is processed into a desired shape by etching to form the semiconductor layer 550 including the connecting portions 553a1 and 553a2. The desired shape is, for example, a square or rectangle, or another polygon, circle, or the like in the XY plan view.

[0246] As shown in FIG. 27A, a first interlayer insulating film 156 is formed to cover the insulating layer 114 and the semiconductor layer 550.

[0247] As shown in FIG. 27B, the TFT lower layer film 106 is formed on the first interlayer insulating film 156, and the TFT channels 104-1 and 104-2 are formed on the TFT lower layer film 106. The insulating layer 105 is formed over the TFT lower layer film 106 and the TFT channels 104-1 and 104-2. The gate 107-1 is formed on the TFT channel 104-1 through the insulating layer 105. The gate 107-2 is formed on the TFT channel 104-2 through the insulating layer 105. The second interlayer insulating film 108 is formed over the insulating layer 105 and the gates 107-1 and 107-2. The methods of forming and materials for the TFT channels 104-1 and 104-2, the insulating layer 105, and the gates 107-1 and 107-2 can be the same as those in the other embodiments described above.

[0248] As shown in FIG. 28A, via holes 112d1 and 112s1 are formed, penetrating the second interlayer insulating film 108, the insulating layer 105, and the TFT lower film 106, and reaching the TFT channel 104-1. Via holes 112d2 and 112s2 are formed, penetrating the second interlayer insulating film 108, the insulating layer 105, and the TFT lower film 106, and reaching the TFT channel 104-2. A via hole 562a1 is formed, penetrating the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156, and reaching the connection portion 553a1. A via hole 562a2 is formed, penetrating the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156, and reaching the connection portion 553a2. A part of the second interlayer insulating film 108, a part of the insulating layer 105, a part of the TFT lower film 106, and a part of the first interlayer insulating film 156 are removed to form an opening 558-1 that reaches the light-emitting surface 551S1. A part of the second interlayer insulating film 108, a part of the insulating layer 105, a part of the TFT lower film 106, and a part of the first interlayer insulating film 156 are removed to form an opening 558-2 that reaches the light-emitting surface 551S2.

[0249] 28B, the via holes 112d1, 112s1, 112d2, 112s2, 562a1, and 562a2 are filled with a conductive material to form vias 111d1, 111s1, 111d2, 111s2, 561a1, and 561a2. The wiring layer 110 is formed, and wirings 510d1, 510s1, 510d2, 510s2, and 510k are formed.

[0250] The light-emitting surfaces 551S1 and 551S2 are each roughened. Then, a translucent conductive film is provided to cover the wiring layer 110, and the translucent electrodes 559d1, 559s1, 559d2, 559s2, and 559k are formed. The translucent electrode 559k is formed to cover the light-emitting surfaces 551S1 and 551S2, and electrically connects the light-emitting surfaces 551S1 and 551S2 and the wiring 510k.

[0251] In this manner, a sub-pixel group 520 is formed, which includes a semiconductor layer 550 having two light emitting surfaces 551S1 and 551S2.

[0252] In this embodiment, two light-emitting surfaces 551S1 and 551S2 are provided on one semiconductor layer 550, but the number of light-emitting surfaces is not limited to two, and it is also possible to provide three or more light-emitting surfaces on one semiconductor layer 550. As an example, one or two columns of subpixels may be realized with a single semiconductor layer 550. As a result, as will be described later, it is possible to reduce the recombination current that does not contribute to light emission per light-emitting surface, and to increase the effect of realizing finer light-emitting elements.

[0253] (Modification) FIG. 29 is a schematic cross-sectional view illustrating a part of an image display device according to a modified example of the present embodiment. This modification differs from the fifth embodiment in that two n-type semiconductor layers 5551a1 and 5551a2 are provided on the light emitting layer 552. In other respects, this modification is the same as the fifth embodiment, and the same components are denoted by the same reference numerals and detailed description thereof will be omitted as appropriate.

[0254] 29, the image display device of this modified example includes a subpixel group 520a. The subpixel group 520a includes a semiconductor layer 550a. The semiconductor layer 550a includes a p-type semiconductor layer 553, a light-emitting layer 552, and n-type semiconductor layers 5551a1 and 5551a2. The p-type semiconductor layer 553 and the light-emitting layer 552 are stacked in this order from the insulating layer 114 side. The n-type semiconductor layers 5551a1 and 5551a2 are both stacked on the light-emitting layer 552.

[0255] The n-type semiconductor layers 5551a1 and 5551a2 are disposed apart from each other along the X-axis direction on the light emitting layer 552. A first interlayer insulating film 156 is provided between the n-type semiconductor layers 5551a1 and 5551a2, and the n-type semiconductor layers 5551a1 and 5551a2 are separated from each other by the first interlayer insulating film 156.

[0256] The n-type semiconductor layers 5551a1 and 5551a2 have approximately the same shape in the XY plan view, and the shape is approximately square or rectangular, but may be another polygonal shape, a circle, or the like.

[0257] The n-type semiconductor layer 5551a1 has a light-emitting surface 5551S1. The n-type semiconductor layer 5551a2 has a light-emitting surface 5551S2. The light-emitting surface 5551S1 is a surface of the n-type semiconductor layer 5551a1 exposed from the first interlayer insulating film 156, the TFT lower film 106, the insulating layer 105, and the second interlayer insulating film 108 by the opening 558-1. The light-emitting surface 5551S2 is a surface of the n-type semiconductor layer 5551a2 exposed from the first interlayer insulating film 156, the TFT lower film 106, the insulating layer 105, and the second interlayer insulating film 108 by the opening 558-2.

[0258] The shapes of the light emitting surfaces 5551S1 and 5551S2 in the XY plane view are almost the same as the shapes of the light emitting surfaces in the fifth embodiment, and are almost square or the like. The shapes of the light emitting surfaces 5551S1 and 5551S2 are not limited to a square as in this embodiment, but may be a circle, an ellipse, or a polygon such as a hexagon. The shapes of the light emitting surfaces 5551S1 and 5551S2 may be similar to the shapes of the openings 558-1 and 558-2, or may be different shapes.

[0259] The translucent electrode 559k is provided on each of the light-emitting surfaces 5551S1 and 5551S2. The translucent electrode 559k is also provided on the wiring 510k. The translucent electrode 559k is provided between the wiring 510k and the light-emitting surface 5551S1, and is also provided between the wiring 510k and the light-emitting surface 5551S2. The translucent electrode 559k electrically connects the wiring 510k and the light-emitting surfaces 5551S1 and 5551S2.

[0260] A manufacturing method for this modified example will be described. 30A to 31B are schematic cross-sectional views illustrating a method for manufacturing the image display device of this modified example. In this modification, the same steps as those described in Figures 26A and 26B in the fifth embodiment are applied up to the step of bonding the substrates together. The steps after the step described above in Figure 26B are described below.

[0261] 30A, in this modification, the semiconductor layer 1150 shown in FIG. 26B is etched to form a p-type semiconductor layer 553 including a light emitting layer 552 and connecting portions 553a1 and 553a2. Further etching is performed to form two n-type semiconductor layers 5551a1 and 5551a2.

[0262] When forming n-type semiconductor layers 5551a1 and 5551a2, etching may be performed deeper. For example, etching for forming n-type semiconductor layers 5551a1 and 5551a2 may be performed to a depth greater than that reaching light emitting layer 552 and p-type semiconductor layer 553. When forming n-type semiconductor layers by deep etching, it is desirable to etch 1 μm or more outside the outer periphery of light emitting surfaces 5551S1 and 5551S2 shown in FIG. 29. By moving the etching position outside the outer periphery of light emitting surfaces 5551S1 and 5551S2, the recombination current can be suppressed.

[0263] As shown in FIG. 30B, a first interlayer insulating film 156 is formed covering the insulating layer 114 and the semiconductor layer 550a.

[0264] 30C, the TFT lower layer film 106 is formed on the first interlayer insulating film 156, and the TFT channels 104-1 and 104-2 are formed on the TFT lower layer film 106. Furthermore, the insulating layer 105 is formed on the TFT channels 104-1 and 104-2, and the gates 107-1 and 107-2 are formed on the insulating layer 105. The second interlayer insulating film 108 is formed to cover the insulating layer 105 and the gates 107-1 and 107-2.

[0265] 31A, the via holes 112d1, 112s1, 112d2, 112s2, 562a1, and 562a2 are formed in the same manner as in the fifth embodiment. The opening 558-1 is formed by removing the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156, so as to reach the light-emitting surface 5551S1. The opening 558-2 is formed by removing the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156, so as to reach the light-emitting surface 5551S2.

[0266] As shown in FIG. 31B, similarly to the fifth embodiment, the wiring layer 110 is formed, and then a light-transmitting conductive film is formed.

[0267] In this manner, a sub-pixel group 520a having two light emitting surfaces 5551S1 and 5551S2 is formed.

[0268] In this modification, similarly to the fifth embodiment, the number of light emitting surfaces is not limited to two, and three or more light emitting surfaces may be provided in one semiconductor layer 550a.

[0269] The effects of the image display device of this embodiment will be described. FIG. 32 is a graph illustrating the characteristics of a pixel LED element. The vertical axis of Figure 32 represents the luminous efficiency [%], and the horizontal axis represents the relative value of the current density applied to the pixel LED element. As shown in Figure 32, in the region where the relative value of the current density is less than 1.0, the luminous efficiency of the pixel LED element is almost constant or increases monotonically. In the region where the relative value of the current density is greater than 1.0, the luminous efficiency decreases monotonically. In other words, there exists an appropriate current density for the pixel LED element that maximizes the luminous efficiency.

[0270] It is expected that a highly efficient image display device can be realized by suppressing the current density to a level where sufficient brightness can be obtained from the light-emitting element. However, as shown in Figure 32, at low current densities, the luminous efficiency tends to decrease as the current density decreases.

[0271] As described in the first to fourth embodiments, the light emitting element is formed by individually separating all layers of the semiconductor layer 1150 including the light emitting layer by etching or the like. At this time, the junction surface between the light emitting layer and the n-type semiconductor layer is exposed at the end. Similarly, the junction surface between the light emitting layer and the p-type semiconductor layer is exposed at the end.

[0272] When such an edge exists, electrons and holes recombine at the edge. However, such recombination does not contribute to light emission. Recombination at the edge occurs almost independently of the current flowing through the light-emitting device. It is considered that recombination occurs according to the length of the junction surface that contributes to the light emission of the edge.

[0273] When two cubic light-emitting elements of the same dimensions are made to emit light, the four side surfaces of each light-emitting element become ends, so that the two light-emitting elements have a total of eight ends, and recombination can occur at the eight ends.

[0274] In contrast, in this embodiment, the semiconductor layers 550 and 550a have four side surfaces, and two light-emitting surfaces have four ends. However, since the region between the openings 558-1 and 558-2 has few electrons and holes injected and hardly contributes to light emission, it can be considered that the number of ends that contribute to light emission is six. Thus, in this embodiment, the number of ends of the semiconductor layer is substantially reduced, thereby reducing recombination that does not contribute to light emission. By reducing recombination that does not contribute to light emission, the drive current for each light-emitting surface is reduced.

[0275] In cases where the distance between subpixels is shortened for higher definition or where the current density is relatively high, the distance between the light-emitting surface 551S1 and the light-emitting surface 551S2 is shortened in the subpixel group 520 of the fifth embodiment. In this case, if the n-type semiconductor layer is shared as in the fifth embodiment, some of the electrons injected into the driven light-emitting surface may be diverted, causing the light-emitting surface that is not driven to emit weak light. In the subpixel group 520a of the modified example, the n-type semiconductor layer is separated into two, and each n-type semiconductor layer has a light-emitting surface, so that it is possible to reduce the occurrence of weak light emission in the light-emitting surface on the side that is not driven.

[0276] In this embodiment, the semiconductor layer including the light emitting layer is laminated in the order of a p-type semiconductor layer, a light emitting layer, and an n-type semiconductor layer from the side of the first interlayer insulating film 156, which is preferable from the viewpoint of roughening the exposed surface of the n-type semiconductor layer to improve the light emitting efficiency. As in the other embodiments, the lamination order of the p-type semiconductor layer and the n-type semiconductor layer may be reversed, and the n-type semiconductor layer, the light emitting layer, and the p-type semiconductor layer may be laminated in this order, as described above.

[0277] Specific examples have been described for the subpixels and subpixel groups of the image display device of each of the above-mentioned embodiments. Each of the specific examples is merely an example, and other configuration examples can be obtained by appropriately combining the configurations and process procedures of these embodiments. For example, in the case of the first embodiment, instead of the p-type semiconductor layer being the light emitting surface, an n-type semiconductor layer can be used, and in the cases of the second to fourth embodiments, instead of the n-type semiconductor layer being the light emitting surface, a p-type semiconductor layer can be used as the light emitting surface.

[0278] Sixth embodiment The above-mentioned image display device can be an image display module having an appropriate number of pixels, and can be, for example, a computer display, a television, a portable terminal such as a smartphone, or a car navigation system.

[0279] FIG. 33 is a block diagram illustrating an image display device according to this embodiment. FIG. 33 shows the main components of a computer display. 33, an image display device 601 includes an image display module 602. The image display module 602 is an image display device having the configuration of, for example, the first embodiment described above. The image display module 602 includes a display area 2 in which a plurality of subpixels including the subpixel 20 are arranged, a row selection circuit 5, and a signal voltage output circuit 7.

[0280] The image display device 601 further includes a controller 670. The controller 670 receives a control signal that is separated and generated by an interface circuit (not shown) and controls the row selection circuit 5 and the signal voltage output circuit 7 to drive each sub-pixel and to control the drive order.

[0281] (Modification) The above-mentioned image display device can be an image display module having an appropriate number of pixels, and can be, for example, a computer display, a television, a portable terminal such as a smartphone, or a car navigation system.

[0282] FIG. 34 is a block diagram illustrating an image display device according to a modified example of this embodiment. FIG. 34 shows the configuration of a high-definition thin television. As shown in Fig. 34, an image display device 701 includes an image display module 702. The image display module 702 is, for example, the image display device 1 having the configuration of the first embodiment described above. The image display device 701 includes a controller 770 and a frame memory 780. The controller 770 controls the drive order of each sub-pixel in the display area 2 based on a control signal supplied by a bus 740. The frame memory 780 stores one frame's worth of display data and is used for processing such as smooth video playback.

[0283] The image display device 701 has an I / O circuit 710. The I / O circuit 710 is simply indicated as "I / O" in Fig. 34. The I / O circuit 710 provides an interface circuit for connecting to an external terminal, device, etc. The I / O circuit 710 includes, for example, a USB interface for connecting an external hard disk device, an audio interface, etc.

[0284] The image display device 701 has a receiving unit 720 and a signal processing unit 730. An antenna 722 is connected to the receiving unit 720, and separates and generates necessary signals from radio waves received by the antenna 722. The signal processing unit 730 includes a DSP (Digital Signal Processor), a CPU (Central Processing Unit), etc., and the signals separated and generated by the receiving unit 720 are separated by the signal processing unit 730 into image data, audio data, etc., and generated.

[0285] By configuring the receiving unit 720 and the signal processing unit 730 as a high-frequency communication module for transmitting and receiving signals in a mobile phone, for WiFi, a GPS receiver, etc., the image display device can be configured as another image display device. For example, an image display device equipped with an image display module with an appropriate screen size and resolution can be configured as a mobile information terminal such as a smartphone or a car navigation system.

[0286] The image display module in this embodiment is not limited to the configuration of the image display device in the first embodiment, but may be a modified example thereof or a modified example thereof. It goes without saying that the image display module in this embodiment and the modified example includes a large number of sub-pixels as shown in FIG.

[0287] According to the embodiment described above, it is possible to realize a manufacturing method for an image display device and an image display device that shortens the transfer process of light emitting elements and improves the yield.

[0288] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. In addition, the above-mentioned embodiments can be implemented in combination with each other. [Explanation of symbols]

[0289] 1,201,601,701 Image display device, 2 Display area, 3 Power supply line, 4 Ground line, 5,205 Row selection circuit, 6,206 Scanning line, 7,207 Signal voltage output circuit, 8,208 Signal line, 10 Pixel, 20,20a,220,320,420 Subpixel, 22,222 Light-emitting element, 24,224 Selection transistor, 26,226 Drive transistor, 28,228 Capacitor, 101 Circuit, 102,402 Substrate, 102a First surface, 103,103-1,103-2,203 Transistor, 104,104-1,104-2,204 TFT channel, 105 Insulating layer, 107,107-1,107-2 Gate, 108 Second interlayer insulating film, 110 Wiring layer, 120 light reflecting layer, 120a light reflecting plate, 150, 250 light emitting element, 153S, 251S, 551S1, 551S2, 5551S1, 5551S2 light emitting surface, 156 first interlayer insulating film, 159d, 159s, 359d, 359k, 559k transparent electrode, 161k, 261a, 361a, 561a1, 561a2 via, 180 color filter, 520, 520a subpixel group, 1001 crystal growth substrate, 1140 buffer layer, 1150 semiconductor layer, 1190 support substrate, 1192 structure, 1194, 1194a, 1294 semiconductor growth substrate

Claims

1. A method for manufacturing a semiconductor device comprising: preparing a first substrate; and a second substrate including a semiconductor layer including a light emitting layer formed on the first substrate; bonding the semiconductor layer to a first surface of a third substrate; removing the first substrate; Etching the semiconductor layer to form a light emitting element including a bottom surface on the first surface, a light emitting surface provided opposite to the bottom surface, and a connection portion; forming a first insulating film covering the first surface and the light emitting element; forming a circuit element on the first insulating film; forming a second insulating film covering the circuit element and the first insulating film; removing a portion of the first insulating film and a portion of the second insulating film to expose a surface including the light emitting surface; forming a via penetrating the first insulating film and the second insulating film; forming a wiring layer on the second insulating film; Equipped with The via is provided between the wiring layer and the connection portion, and electrically connects the wiring layer and the connection portion.

2. forming a layer having light reflectivity on the first surface before bonding the semiconductor layer to the first surface; forming an insulating layer on the light-reflective layer; The method for manufacturing an image display device according to claim 1 , further comprising:

3. the light-reflective layer includes a first portion having light-reflective properties, The light emitting device is formed on the first portion, The method for manufacturing an image display device according to claim 2 , wherein the outer periphery of the first portion includes an outer periphery of the light emitting element when the light emitting element is projected onto the first portion in a plan view.

4. 4. The method for manufacturing an image display device according to claim 1, wherein the step of bonding the semiconductor layer to the third substrate includes bonding a plurality of the second substrates to one of the third substrates.

5. 5. The method for manufacturing an image display device according to claim 1, wherein the third substrate includes a light-transmitting substrate.

6. the third substrate further includes a fourth substrate having flexibility and provided on the light-transmitting substrate, The method for manufacturing an image display device according to claim 5 , further comprising the step of removing the light-transmitting substrate after bonding the semiconductor layer to the fourth substrate in the step of bonding the semiconductor layer to the third substrate.

7. The semiconductor layer is laminated in this order from the first substrate side, including a first semiconductor layer of a first conductivity type, the light emitting layer, and a second semiconductor layer of a second conductivity type different from the first conductivity type; the second semiconductor layer includes the connection portion, the first conductivity type is n-type, 2. The method for manufacturing an image display device according to claim 1, wherein the second conductivity type is a p-type.

8. 8. The method for manufacturing an image display device according to claim 1, further comprising the step of forming a translucent electrode on the exposed light-emitting surface.

9. 9. The method for manufacturing an image display device according to claim 1, wherein the semiconductor layer contains a gallium nitride compound semiconductor.

10. The method for manufacturing an image display device according to any one of claims 1 to 9, further comprising the step of forming a wavelength conversion member on the light emitting element.

11. a substrate having a first surface; a light emitting element including a bottom surface on the first surface, a light emitting surface that is a surface facing the bottom surface, and a connection portion; a first insulating film covering a side surface and the first surface of the light emitting element; A circuit element provided on the first insulating film; a second insulating film covering the circuit element and the first insulating film; a via provided through the first insulating film and the second insulating film; A wiring layer provided on the second insulating film; Equipped with The via is provided between the wiring layer and the connection portion, and electrically connects the wiring layer and the connection portion.

12. The image display device according to claim 11 , wherein the substrate includes a light-transmitting substrate.

13. The image display device according to claim 11 , wherein the substrate includes a flexible substrate.

14. a light-reflective layer provided on the first surface; an insulating layer covering the light-reflective layer; The image display device according to any one of claims 11 to 13, further comprising:

15. The light-reflective layer includes a first portion, The light emitting element is provided on the first portion, The image display device according to claim 14 , wherein the outer periphery of the first portion includes an outer periphery of the light emitting element when the light emitting element is projected onto the first portion in a plan view.

16. the light-emitting element is formed by stacking a first semiconductor layer of a first conductivity type, a light-emitting layer, and a second semiconductor layer of a second conductivity type different from the first conductivity type in this order from the first surface toward the light-emitting surface; 16. The image display device according to claim 11, wherein the first semiconductor layer includes the connection portion.

17. the wiring layer includes a first wiring connected to the via and a second wiring connected to a surface including the light emitting surface, The image display device according to claim 16 , wherein the second semiconductor layer is electrically connected to the circuit element via a surface including the light emitting surface and the second wiring.

18. the wiring layer includes a third wiring connected to the via and a fourth wiring connected to a surface including the light emitting surface, The image display device according to claim 16 , wherein the first semiconductor layer is electrically connected to the circuit element through the via and the third wiring.

19. the first conductivity type is p-type, 19. The image display device according to claim 16, wherein the second conductivity type is an n-type.

20. The light-emitting device further includes a light-transmitting electrode provided on the light-emitting surface, 20. The image display device according to claim 16, wherein the second semiconductor layer is connected to the wiring layer via the light-transmitting electrode.

21. 21. The image display device according to claim 11, wherein the light emitting element includes a gallium nitride compound semiconductor.

22. 22. The image display device according to claim 11, wherein the circuit elements include thin film transistors.

23. 23. The image display device according to claim 11, further comprising a wavelength conversion member on the light emitting element.

24. a substrate having a first surface; a semiconductor layer including a bottom surface on the first surface and a surface facing the bottom surface, the semiconductor layer including a plurality of light emitting surfaces and connection portions on the surface; a first insulating film covering a side surface of the semiconductor layer and the first surface; A plurality of transistors provided on the first insulating film; a second insulating film covering the plurality of transistors and the first insulating film; a plurality of vias provided through the first insulating film and the second insulating film; A wiring layer provided on the second insulating film; Equipped with The plurality of vias are provided between the wiring layer and the connection portion, electrically connecting the wiring layer and the connection portion.

25. The semiconductor layer is laminated in the order of a first semiconductor layer of a first conductivity type, a light emitting layer, and a second semiconductor layer of a second conductivity type different from the first conductivity type from the bottom surface toward the plurality of light emitting surfaces, The image display device according to claim 24 , wherein the second semiconductor layer is separated by the first insulating film.

Images