COMPUTER DEVICE, SYSTEM, CONTROL METHOD, AND PROGRAM

Abstract

To provide a computer device etc. capable of accessing an external device from a plurality of processors at low access cost in a NUMA system. [Solution] The computer device comprises an input / output control unit that exists for each path for input / output to an external device and controls input / output to the external device through that path, an input / output management unit that selects the path to be used in response to an input / output request to the external device from a process running on a processor, and instructs the input / output control unit of the selected path to perform input / output to the external device, and a process management unit that controls a process to go into a run state in one of the multiple processors when the input / output instructed by the input / output management unit to the input / output control unit is completed, and the process management unit can select a processor that will go into a run state when the input / output is completed, in accordance with the path selected by the input / output management unit.

Description

[Technical field]

[0001] The present disclosure relates to a computer device, a system, a control method, and a program. [Background technology]

[0002] For example, Patent Document 1 describes a process in which, when selecting an access memory for a device, any processor included in an information processing device selects the access memory as a memory on the same system bus as the device, and a process in which a startup processor for a device driver corresponding to the device is selected as a processor on the same system bus as the device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 4609521 Summary of the Invention [Problem to be solved by the invention]

[0004] In the information processing device described in Patent Document 1, the node connected to a certain device is fixed. Therefore, when accessing a certain device, the path cannot be distributed. In other words, a specific device cannot be accessed from multiple processors (multiple nodes) at low access cost.

[0005] An object of the present disclosure is to provide a computer device, a system, a control method, and a program that solve the above-mentioned problems. [Means for solving the problem]

[0006] A computer device according to one embodiment of the present disclosure comprises a plurality of processors; an input / output control unit that exists for each path for input / output to an external device and controls input / output to the external device through the path; an input / output management unit that selects a path to use in response to an input / output request to the external device from a process running on the processor, and instructs the input / output control unit of the selected path to perform input / output to the external device; and a process management unit that controls the process to be in a run state in any one of the plurality of processors when the input / output instructed by the input / output management unit to the input / output control unit is completed, and the process management unit can select a processor that will put the process in a run state when the input / output is completed, in accordance with the path selected by the input / output management unit. Effect of the Invention

[0007] According to the above aspect, when performing input / output with an external device, the paths used can be distributed, and the process that originated the input / output request can be put into a running state in a processor selected according to the selected path (path used) after the input / output is completed. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is an example of a system configuration diagram according to the present disclosure. [Diagram 2] 1 is a schematic diagram showing an access path between a CPU and storage in a system according to the present disclosure in a case where a CPU that executes a process and an I / O control unit belong to the same node. [Diagram 3] 1 is a schematic diagram showing an access path between a CPU and storage in a case where a CPU that executes a process and an I / O control unit belong to different nodes in a system according to the present disclosure. FIG. [Figure 4] 1 is a reference diagram showing an example of a sequence of relationships between a CPU that executes a process when accessing storage according to a related technique related to the present disclosure and a path to be used. [Diagram 5]1 is a schematic diagram showing an example of a sequence of a relationship between a CPU that executes a process and a path to be used when the process accesses storage in a computer system according to the present disclosure. FIG. [Figure 6] FIG. 2 is a block diagram showing an example of the configuration of programs and data placed on a main memory in a computer system according to the present disclosure. [Figure 7] FIG. 11 is a reference diagram showing an example of an operation sequence when a computer system operates using related technology related to the present disclosure. [Figure 8] 1 is a schematic diagram showing an example of an operation sequence when a computer system according to the present disclosure operates. [Figure 9] 13 is a flowchart showing the procedure of processing a process (511) in a computer system according to the present disclosure. [Figure 10] 13 is a flowchart showing the procedure of processing a process (511) in a computer system according to the present disclosure. [Figure 11] 11 is a flowchart showing the procedure of an initialization process executed at the time of OS startup of an I / O management unit (521) in a computer system according to the present disclosure. [Figure 12] 13 is a flowchart showing the procedure of a timer interrupt operation of an I / O management unit (521) in a computer system according to the present disclosure. [Figure 13] 11 is a flowchart showing the procedure of main processing of a process management unit (531) in the computer system according to the present disclosure. [Figure 14] 13 is a flowchart showing a procedure for processing an I / O request by a process management unit (531) in the computer system according to the present disclosure. [Figure 15] 13 is a flowchart showing a procedure for processing a wait request by a process management unit (531) in the computer system according to the present disclosure. [Figure 16] 13 is a flowchart showing a processing procedure for accessing storage by an I / O control unit (533) in the computer system according to the present disclosure. [Figure 17] 13 is a flowchart showing a procedure for processing an I / O end request by a process management unit (531) in the computer system according to the present disclosure. [Figure 18] FIG. 11 is a schematic diagram showing an example of an operation sequence (1 / 2) when the computer system according to the present disclosure operates. [Figure 19] FIG. 11 is a schematic diagram showing an example of an operation sequence (2 / 2) when the computer system according to the present disclosure operates. [Figure 20] 1 is a block diagram showing a schematic configuration of a computer device according to the present disclosure and a schematic configuration of a system including the computer device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, each embodiment will be described with reference to the drawings. In all the drawings, the same or corresponding components are denoted by the same reference numerals, and common descriptions will be omitted.

[0010] First Embodiment Hereinafter, an embodiment according to the present disclosure will be described with reference to the drawings.

[0011] This embodiment is based on, for example, a NUMA system and a multipath configuration in which multiple paths are provided to connect the system and storage. NUMA is an abbreviation for "Non-Uniform Memory Access." This embodiment is characterized by optimizing storage access performance by distributing the paths used and matching the CPU (Central Processing Unit) and the paths used to the same node (affinity).

[0012] A processing device such as a CPU is also called a "processor."

[0013] In this embodiment, as a method for distributing and using paths, the same path is used for a certain period of time, and the path to be used is changed at time intervals or at intervals based on the number of accesses. When the path is changed, the CPU that executes the process is also dynamically changed, and the CPU and the path to be used are always on the same node, which is a feature of the system, improving storage access performance.

[0014] In addition, in this embodiment, paths are distributed by using a different path for each process, which is a feature of the present invention in that paths are distributed globally throughout the entire system.

[0015] If path distribution is performed, affinity cannot be achieved, and if affinity is performed, path distribution cannot be achieved. In other words, distribution of multipath use and affinity are mutually contradictory technical elements. However, the present embodiment is a technology characterized by achieving both distribution of multipath use and affinity.

[0016] A process is the smallest unit for executing an application program. A process always runs on a single CPU. This is to improve performance by increasing the cache hit rate by fixing the CPU that runs a process.

[0017] Furthermore, in computer systems with a multipath configuration where there are multiple paths to storage, in order to distribute the load, the path used by a process is changed each time it accesses the storage. When a process accesses storage, it calls a function of the I / O control unit (input / output control unit) of the OS (operating system or operating system). The selection of the multipath is controlled by the OS.

[0018] 1 is an example of a system configuration diagram for implementing an embodiment. The computer system 1 is a NUMA system. That is, in the computer system 1, all main memories are managed in a unified address space, and all addresses of the main memory can be accessed from any CPU. That is, a certain CPU can access the main memory in the same node, and can also access the main memory in another node. However, while a certain CPU can quickly access the main memory in the same node (which may be called local memory) using a high-speed transmission line, it takes relatively longer to access the main memory in another node (which may be called remote memory).

[0019] The computer system 1 is also called a "computer device."

[0020] In the illustrated example, the computer system 1 is configured to include a plurality of nodes 3 and an interconnect 8 that interconnects the plurality of nodes. In the illustrated example, the computer system 1 has four nodes 3, and the nodes 3 are numbered #0, #1, #2, and #3. Each node 3 is configured to include a CPU group 4, a main memory 5, an I / O control unit 6, and a cache 7 (cache memory). The CPU group 4 has, for example, a four-core CPU. Each CPU is numbered as follows. That is, the CPU group 4 of node #0 includes four CPUs, CPU#0, CPU#1, CPU#2, and CPU#3. The CPU group 4 of node #1 includes four CPUs, CPU#4, CPU#5, CPU#6, and CPU#7. The CPU group 4 of node #2 includes four CPUs, CPU#8, CPU#9, CPU#a, and CPU#b. Furthermore, the CPU group 4 of node #3 includes four CPUs: CPU #c, CPU #d, CPU #e, and CPU #f. The CPUs included in the CPU group 4 can access the main memory 5 and the I / O control unit 6 via the cache 7 in the own node. The CPUs are equipped with various registers, and can hold and read process information required to execute a process.

[0021] That is, the computer system 1 is configured to have a plurality of nodes 3. Furthermore, each node 3 has a path used for input / output. Furthermore, each node 3 may include one or more CPUs.

[0022] The I / O control unit 6 is also called an "input / output control unit."

[0023] The computer system 1 is also connected to a storage 2. The storage 2 is realized using, for example, a magnetic hard disk drive (HDD) or a solid state drive (SSD), and has a function of recording information. Specifically, an I / O control unit 6 of each node 3 in the computer system 1 is connected to the storage 2 via a path. Based on a request from the CPU, the I / O control unit 6 writes information to the storage 2 or reads information from the storage 2.

[0024] The storage 2 is one aspect of the "external device."

[0025] The combination of the computer system 1 and the storage 2 (external device) may be called a "system."

[0026] As a premise of this embodiment, data stored in the main memory 5 is basically held in the cache 7. Therefore, affinity settings between the main memory 5 and the CPU or the I / O control unit 6 are not described. In many literature on affinity, the main memory 5 and the CPU are set on the same node. In this embodiment, the CPU and the I / O control unit 6 are set on the same node, enabling efficient access to data on the cache 7 of the same node, thereby improving performance.

[0027] The CPU can access an external device (such as storage 2) via the I / O control unit 6 in the same node and the path thereto, or can access an external device (such as storage 2) via the I / O control unit 6 in another node and the path thereto. Each of Figures 2 and 3 shows these two forms (states).

[0028] 2 is a schematic diagram showing an access path between a CPU and the storage 2 in the case where the CPU that executes a process and the I / O control unit 6 belong to the same node. Data can be exchanged between the CPU and the I / O control unit 6 that belong to the same node via the cache 7. At this time, the access performance from the CPU to the storage 2 is optimized. The technology of this embodiment described below aims to maintain this optimal state. That is, in this embodiment, a path to be used is selected with the aim of maintaining this state.

[0029] FIG. 3 is a schematic diagram showing the access path between the CPU and the storage 2 in the case where the CPU that executes the process and the I / O control unit 6 belong to different nodes. Data is exchanged between the CPU and the I / O control unit 6 that belong to different nodes through the following path. Data that the CPU on node #0 reads from the main memory 5 and data that the CPU writes to the main memory 5 are registered in the cache 7 on node #0. On the other hand, data that the I / O control unit 6 on node #1 reads from or writes to the main memory 5 or the storage 2 is registered in the cache 7 on node #1. For example, when the I / O control unit 6 on node #1 reads data written by the CPU on node #0, the I / O control unit 6 on node #1 reads the cache 7 on node #0 via the interconnect 8. In other words, the access performance to the storage 2 deteriorates. The reverse is also true: when the CPU on node #0 reads data written by the I / O control unit 6 on node #1, the CPU on node #0 reads the cache 7 on node #1 via the interconnect 8. In other words, the access performance to the storage 2 deteriorates. The technology of this embodiment aims to eliminate such a state.

[0030] FIG. 4 is a reference diagram showing an example of a sequence of the relationship between a CPU that executes a process and a path to be used when accessing storage according to the related technology. One row in the diagram corresponds to one access to storage. The length of the horizontal line in each row represents the I / O latency. In the example shown here, the CPU that executes the process is always CPU#0. Also, the path to be used when accessing storage is different each time. In other words, the path to be used circulates in the order of node#0→node#1→node#2→node#3→node#0→... (similarly below). In such related technology, the paths to be used are strictly distributed, but the ratio (optimization rate) of the CPU and the I / O control unit 6 to be used existing on the same node is only 25%.

[0031] FIG. 5 is a schematic diagram showing an example of a sequence of the relationship between a CPU executing a process and a path to be used when a process accesses storage in the present disclosure. In the illustrated example, the path to be used is switched at the timing every time a certain process accesses storage 10 times. In the method of this embodiment, when the path is switched, the CPU executing the process is also dynamically switched. Specifically, in the illustrated example, every time the storage is accessed 10 times, the I / O control unit 6 to be used changes from node #0 to node #1 to node #2 to node #3 to node #0 to... (similarly below). In addition, when the I / O control unit 6 is switched, the CPU is also switched, so that when the storage is accessed next time, an access request is issued from a CPU that exists in the same node as the I / O control unit 6 to be used. In other words, in the method of this example, the ratio (optimization rate) of the CPU executing the process and the I / O control unit 6 used when accessing storage belonging to the same node is 90%. In other words, compared to the reference example (related technology) shown in FIG. 4, the storage access performance is improved.

[0032] 5 (and a generalized method thereof), a CPU that executes a process is selected according to the selected path to be used. This results in a higher ratio (optimization rate) of the CPU that executes the process and the I / O control unit 6 used when accessing storage belonging to the same node than in the related technology. In other words, in this embodiment, storage access performance is improved compared to the related technology.

[0033] In addition, in the method of this embodiment, I / O is performed using different paths between processes. In other words, even when multiple processes access a storage, the paths used between those storages are distributed. Therefore, even when viewed from a global perspective throughout the entire system, the paths used are distributed.

[0034] 6 is a block diagram showing an example of the configuration of programs and data arranged on main memory 5 in the present disclosure. The programs are roughly divided into application 51 (application program), OS 52, and firmware 53. Note that in this embodiment, functions are shared between OS 52 and firmware 53, but a configuration may also be adopted in which firmware 53 is not provided and the functions of firmware 53 are realized by OS 52.

[0035] 6, the process 511, the I / O management unit 521, the process management unit 531, and the I / O control unit 533 are programs. Also, the process information 512, the application data 513, the path information 522, the timer notification interval 524, the issue count control information 525, the semaphore 523 (wait queue), the ready queue 532, the instruction queue 534, and the end queue 535 are data.

[0036] The application 51 includes a process 511, process information 512, and application data 513. The process 511 is the smallest unit of a program to be executed. There may be a plurality of processes 511. To distinguish the processes 511 from one another, they may be numbered as process #0, process #1, . . . , process #n. The process information 512 is a snapshot of the execution state of each process 511. The process information 512 is information that is passed to a CPU when the process 511 is executed by the CPU. The process information 512 includes a process ID. The process ID is information (value) for uniquely identifying a process within the computer system 1. There is process information 512 for each process 511. The application data 513 is data required to run an application (for example, data in an application area).

[0037] The OS·52 includes an I / O management unit 521, path information 522, a semaphore 523, a timer notification interval 524, and issuance count control information 525. The OS·52 may have other data or programs that are unrelated to the purpose of this embodiment (control of the path used when accessing the external storage 2).

[0038] The I / O management unit 521 manages input / output (I / O) under the management of the OS 52. Input / output (I / O) includes, for example, writing of information to the storage 2 (output from the CPU side) and reading of information from the storage 2 (input to the CPU side). The I / O management unit 521 selects a path to be used in response to an I / O request to the storage 2 (external device) from a process 511 running on the CPU. The I / O management unit 521 also instructs an I / O control unit 533 of the selected path to input / output to the storage 2.

[0039] The I / O management unit 521 is also called an "input / output management unit."

[0040] The path information 522 is information about paths for storage 2. Specifically, the path information 522 holds the current path number (master path number) and other information related to paths for each storage unit or for each divided area within the storage unit. The path number (master path number) is the number of the path to be used to access a specific storage unit or an area within the storage unit.

[0041] The semaphore 523 is data that is temporarily generated for access to the storage 2. The semaphore 523 is data for controlling access to the storage 2. The semaphore 523 has a queue for a process to wait during I / O access. In other words, the semaphore 523 is information used to control the number of simultaneous accesses to a specific resource under the management of the OS 52.

[0042] The timer notification interval 524 is a value that defines the time interval for periodically changing the above-mentioned master path number.

[0043] The issue count control information 525 includes an issue count counter and a continuous issue upper limit. The issue count control information 525 is information for counting the number of accesses to a specific storage or an area in the storage and controlling the change of the master path number. When an access is made to a specific storage or an area in the storage, the issue count counter is incremented (+1). When the value of the issue count counter reaches the continuous issue upper limit, the master path number is changed.

[0044] The firmware 53 includes a process management unit 531 for each CPU, a ready queue 532 for each node, an I / O control unit 533 for each node, an instruction queue 534 for each node, and an end queue 535 for each node. In other words, assuming the configuration shown in FIG. 1, the process management unit 531 exists corresponding to each of the 16 CPUs, CPU#0, CPU#1, CPU#2, . . . , CPU#f. Also, the ready queue 532, the I / O control unit 533, the instruction queue 534, and the end queue 535 exist corresponding to each of the four nodes, node#0, node#1, node#2, and node#3. The firmware 53 may include other functions and elements that are not directly related to the purpose of this embodiment.

[0045] The process management unit 531 manages the operation of the process 511. The process management unit 531 manages the state of the process 511 (such as a ready state or a wait state) and controls the process 511 to run on a specified CPU. The process management unit 531 of this embodiment controls the process 511 to run in any one of the multiple CPUs when the I / O management unit 521 completes the I / O control unit 533 instructed to perform I / O. The process management unit 531 can select a CPU that will put the process 511 into the run state when the I / O is completed, depending on the path (path in use) selected by the I / O management unit 521.

[0046] The ready queue 532 is a queue for processes in a ready state. In order to make a process that has been waiting ready again, the process is removed from the wait queue and added to the ready queue 532. A predetermined amount of CPU resources is sequentially allocated to the processes registered in the ready queue 532. In other words, the CPU refers to the ready queue 532, removes a process waiting in the ready queue 532, and executes it (runs it).

[0047] An I / O control unit 533 exists for each path for input / output to the storage 2 (external device). The I / O control unit 533 controls input / output to the storage 2 through the path. The I / O control unit 533 performs input / output to the storage 2 according to an instruction from the process management unit 531. When the I / O control unit 533 completes the input / output to the storage 2, it passes a completion notification to the process management unit 531. During the execution of the input / output, the process is in a wait state, but the I / O control unit 533 sending a completion notification to the process management unit 531 serves as a trigger to allow the process in the wait state to return to a run state again. The I / O control unit 533 operates in the I / O control unit 6 shown in FIG. 1.

[0048] The I / O control unit 533 is also called an "input / output control unit."

[0049] The instruction queue 534 is a queue for storing instruction information corresponding to an access request to the storage 2 .

[0050] The completion queue 535 is a queue for storing completion information (information including the access result, etc.) when access to the storage 2 is completed.

[0051] Among the queues described above, the ready queue 532 and the wait queue are FIFO (first-in, first-out) queues for registering and retrieving processes. The instruction queue 534 and the completion queue 535 are FIFO queues for registering and retrieving instructions and terminations related to I / O requests, respectively. Since the I / O management unit 521, the process management unit 531, and the I / O control unit 533 may attempt to access the above queues simultaneously, appropriate exclusive control is performed for each queue using a lock mechanism or the like. The mechanism of exclusive control required here can be realized using known existing technology, so detailed explanation is omitted.

[0052] Next, the operation of the computer system 1 will be described.

[0053] FIG. 7 is a reference diagram (reference example) showing an example of an operation sequence when a computer system operates using the related technology.

[0054] In the example sequence shown in this figure, the CPU on which process 511 is executed is always CPU #0. However, when the process 511 accesses storage 2 (Read / Write), a different path (for example, a path via node #0, a path via node #1, etc.) is used each time. In other words, since process 511 is executed by CPU #0 on node #0, when path #1, path #2, or path #3 is selected, the latency in accessing storage 2 worsens. The specific sequence is as follows:

[0055] In the explanation of this figure, reference numerals S201 to S209 indicate operations relating to a first I / O by the process 511. Reference numerals S210 to S218 indicate operations relating to a second I / O by the process 511.

[0056] A process 511 is being executed by CPU #0. When the process 511 performs read / write (I / O) to the storage 2 in S201, the process 511 calls an I / O management unit 521 of the OS.

[0057] In S202, the I / O management unit 521 acquires the path number to be used from the path information 522, and updates the path number in the path information 522. For example, the update is performed according to the following formula (1).

[0058] New pass number = (current pass number + 1)% total pass number ... (1)

[0059] Here, "%" in formula (1) is an operator for calculating the remainder in integer division. That is, according to formula (1), the new path number is the remainder when (current path number + 1) is divided by the total number of paths. That is, the I / O management unit 521 updates the path information 522 so that the path number in the path information 522 becomes the above-mentioned new path number.

[0060] In S202, the I / O management unit 521 issues a Read / Write (I / O) instruction to the storage 2 to the I / O control unit 533 of the node (node ​​#0 in this case) corresponding to the path number obtained above.

[0061] Furthermore, in S203, the I / O management unit 521 generates a semaphore 523 and notifies the process management unit 531 in the CPU that is executing the process of a wait instruction for the process.

[0062] Upon receiving the notification, the process management unit 531 transitions the process 511 to a wait state in S203. That is, the process management unit 531 stores the values ​​of various registers (register sets) of CPU #0 at that time in the process information 512 of the process 511. In addition, the process management unit 531 adds the process 511 to a wait queue of the semaphore 523. As a result, the process enters a wait state (S205).

[0063] On the other hand, the I / O control unit 533 receives a Read / Write (I / O) instruction to the storage 2 and performs a Read / Write access to the storage 2 in S206.

[0064] In addition, in S207, the I / O control unit 533 sends a completion notification to CPU #0, which is the issuer of the instruction. These read / write instructions and completion notifications are managed in a queue structure. An instruction queue 534 and a completion queue 535 exist for each node. The notifying party adds an instruction or notification to the queue, and the notifying party removes the instruction or notification from the queue.

[0065] Upon receiving the termination notification, the process management unit 531 transitions the process 511 to the run state in S208. That is, the process management unit 531 takes the process out of the wait queue of the semaphore 523 and stores the process information 512 in CPU #0, thereby causing the process to be executed by CPU #0. This puts the process into the run state (S209). The above is a series of operations for one storage access.

[0066] The second I / O process is also shown in Figure 7. In this second process, the process running on CPU #0 accesses storage 2 using the path of node #1.

[0067] That is, the operation of S211 corresponds to the operation of S202 in the first I / O. Furthermore, the operation of S212 corresponds to the operation of S203 in the first I / O. Furthermore, the operation of S213 corresponds to the operation of S204 in the first I / O. Furthermore, the operation of S214 corresponds to the operation of S205 in the first I / O.

[0068] The operation of S215 corresponds to the operation of S206 in the first I / O. Also, the operation of S216 corresponds to the operation of S207 in the first I / O. However, in this second I / O, the I / O control unit 533 of node #1 performs the operations of S215 and S216.

[0069] The operation of S217 corresponds to the operation of S208 in the first I / O. Moreover, the operation of S218 corresponds to the operation of S209 in the first I / O.

[0070] The same applies to the third and subsequent I / Os. That is, from the third time onwards, the process 511 running on CPU #0 accesses the storage 2 while changing the path in the order of node #2 → node #3 → node #0 → node #1 →... (and so on).

[0071] That is, the first I / O in Fig. 7 corresponds to the I / O (access to storage 2) shown in Fig. 2. The second I / O in Fig. 7 corresponds to the I / O (access to storage 2) shown in Fig. 3.

[0072] FIG. 8 is a schematic diagram showing an example of an operation sequence when the computer system 1 according to the present disclosure operates.

[0073] In the example shown in the figure, the CPU that executes the process 511 may be dynamically switched. That is, during the first predetermined number of I / Os or during a predetermined time, the process 511 is continuously executed by the CPU #0. Then, path switching may occur at a predetermined timing. The path switching may be performed, for example, when a predetermined number of I / Os have been executed or when a predetermined time has elapsed. For example, the path is switched from path #0 to path #1. After the path switching, the path #1 is continuously used. After returning from the wait, the CPU that executes the process 511 is switched to the CPU #4 on the node #1. After that, until the next path switching timing comes, the I / O using the path #1 is continuously performed, and the process 511 is continuously executed on the CPU #4.

[0074] In the operation sequence shown in FIG. 8, the operations specific to this embodiment (that is, operations different from the operation sequence in FIG. 7) are as follows. That is, one of the features of this embodiment is the method (calculation method) by which the I / O management unit 521 determines the path to be used in S302 and S313. Another feature of this embodiment is that in S303 and S314, the process management unit 531 calculates the end notification destination node number based on the number of the path to be used, and notifies the I / O control unit 533 of the calculated node number when instructing storage access (Read / Write). Another feature of this embodiment is that in S308 and S319, the I / O control unit 533 notifies the end to the CPU under the end notification destination node number received above. As a result, the I / O request source process 511 is executed in the CPU belonging to the node determined based on the path to be used after the I / O is completed. The detailed procedure will be described below.

[0075] In this example, the process 511 is running on CPU #0. In S301, the process 511 performs read / write on the storage 2. When the process 511 performs read / write (I / O) on the storage 2, it calls the function of the I / O management unit 521.

[0076] The called I / O management unit 521 acquires the master path number from the path information 522 in S302. At this point, the I / O management unit 521 does not update the master path number in the path information 522. The I / O management unit 521 calculates the path number to be actually used from the acquired master path number and the process ID. The I / O management unit 521 calculates the path number to be used, for example, by performing a calculation using the following formula (2).

[0077] Path number used = (master path number + hash (process ID)) % total number of paths (2)

[0078] In the above formula (2), hash() is an appropriate hash function. By using such a hash function, the number (based on the process ID) to be added to the master path number can be distributed as evenly as possible. If the process ID itself is originally distributed evenly, there is no need to use such a hash function, and the process ID can be added directly to the master path number.

[0079] As shown in formula (2), the I / O management unit 521 determines a master path number for identifying a master path from among a plurality of paths, and selects a path to be used based on the master path number and the process ID for identifying the process 511 that made the I / O request. This distributes paths to be used for I / O for each process 511.

[0080] Also, as shown in formula (2), the I / O management unit 521 may select a path to be used based on a value obtained by applying a hash function to a process ID. Also, the I / O management unit 521 can select a path to be used based on a value obtained by applying a hash function to a process ID using a method (mathematical formula) other than formula (2). Here, the hash function has the effect of distributing paths to be used for input / output for each process 511 based on the process ID.

[0081] Furthermore, as shown in equation (2), the I / O management unit 521 may select the path to be used by adding (or subtracting) the value obtained by applying a hash function to the process ID in a modulo system modulo the number of paths (total number of paths) to the master path number.

[0082] Next, the I / O management unit 521 issues a read / write instruction to the storage 2 to the process management unit 531 of the CPU that is executing the process.

[0083] The process management unit 531 that has received the instruction calculates the end notification destination node number from the path number to be used in S303. The process management unit 531 notifies the I / O control unit 533 of the calculated node number and issues a storage access (Read / Write) instruction.

[0084] Also, in S304, the I / O management unit 521 prepares (creates) a semaphore 523 and notifies the process management unit 531 of the running CPU of a process wait instruction.

[0085] In S305, the process management unit 531 that has received the process wait instruction stores the state of CPU #0 in the process information 512 of the process 511, and adds the process to the wait queue of the semaphore 523. This puts the process into a wait state (S306).

[0086] On the other hand, the I / O control unit 533 (here, the I / O control unit 533 of node #0) that has received the instruction to read / write to the storage 2 performs read / write access to the storage 2 in S307.

[0087] When the access to the storage 2 is completed, the I / O control unit 533 (node ​​#0) in S308 sends a completion notification to the subordinate CPU of the completion notification destination node number that was received at the time of the I / O instruction.

[0088] Upon receiving this termination notification, the process management unit 531 transitions the process 511 to the run state in S309. That is, the process management unit 531 takes out the process from the wait queue of the semaphore 523, stores the process information 512 of the process in CPU #0, and causes the process to be executed by CPU #0. This puts the process into the run state (S310).

[0089] The above steps from S301 to S310 constitute one access to the storage 2.

[0090] In the second and subsequent storage accesses, the path number to be used will not change as long as the master path number does not change. In other words, the process on CPU #0 accesses storage 2 using the I / O control unit 533 of node #0.

[0091] At the timing of path switching, the I / O management unit 521 updates (switches) the master path number. The timing of path switching may be when the number of storage accesses using the same master path number reaches a predetermined number, or when a periodic timing arrives after a predetermined time has elapsed, or both.

[0092] The I / O management unit 521 calculates the post-switching master path number, for example, by the following formula (3).

[0093] New Master Pass Number = (Current Master Pass Number + 1)% Total Passes (3)

[0094] As shown in formula (3), the I / O management unit 521 may update the master path number at a predetermined timing so as to circulate the master path number. Note that the method of updating the master path number so as to circulate the master path number is not limited to the method using the calculation of formula (3). In other words, the I / O management unit 521 may circulate the master path number using a method other than the method of incrementing the master path number by "+1".

[0095] 8, the I / O management unit 521 switches the path number in S311. The path calculated by the I / O management unit 521 to be used in the operation after the path switching is path #1 (node ​​#1).

[0096] In S312, the process 511 performs the next I / O. That is, the process 511 calls the function of the I / O management unit 521.

[0097] Then, in S313, the I / O management unit 521 calculates the path to be used, and issues a read / write instruction to the storage 2 to the process management unit 531 of the executing CPU.

[0098] The process management unit 531 that has received this instruction calculates the node number of the completion notification destination from the path number to be used in S314. Then, the process management unit 531 notifies the I / O control unit 533 of the node of the path to be used (here, the I / O control unit 533 of node #1) of the completion notification destination node number and issues an instruction to access the storage 2.

[0099] In S315, the I / O management unit 521 prepares (creates) a semaphore 523 and notifies the process management unit 531 of the executing CPU of a process wait instruction.

[0100] Upon receiving the instruction to wait for the process, the process management unit 531 transitions the process 511 to a wait state in S316. That is, the process management unit 531 stores the state of CPU#0 in the process information 512 of the process 511, and adds the process 511 to the wait queue of the semaphore 523. As a result, this process enters a wait state (S317).

[0101] On the other hand, the I / O control unit 533 (node ​​#1) that has received the instruction to read / write to the storage 2 performs read / write access to the storage 2 in S318.

[0102] Furthermore, in S319, the I / O control unit 533 sends a completion notification to the CPU (#4) under the node number (node ​​#1) of the completion notification destination that was received together with the Read / Write instruction.

[0103] Upon receiving this termination notification, the process management unit 531 (CPU #4) transitions the process 511 to the run state in S320. That is, the process management unit 531 (CPU #4) takes out the process from the wait queue of the semaphore 523, stores the process information 512 of the process in CPU #4, and causes the process to be executed by CPU #4. This brings the process into the run state (S321).

[0104] In this manner, in this embodiment, as in the illustrated operation sequence, the CPU that executes the process may be dynamically switched.

[0105] After this, unless the master path number changes, the path number to be used also remains the same, and the process executed on CPU #4 uses the I / O control unit 533 of node #1 to access the storage 2. Every time a path switch occurs at a predetermined timing (for example, periodically), the master path number is updated, and the path to be used and the CPU executing the process change dynamically.

[0106] As described above with reference to FIG. 8, the features of this embodiment are as follows. The computer system 1 includes a plurality of CPUs (processors). The I / O management unit 521 (input / output management unit) selects a path to be used in response to an input / output request from the process 511 running on the CPU to the storage 2 (external device). The I / O management unit 521 also instructs an I / O control unit 533 (input / output control unit) of the selected path to input / output to the storage 2. When the input / output instructed by the I / O management unit 521 to the I / O control unit 533 is completed, the process management unit 531 controls the process 511 to be in a run state in any one of the plurality of CPUs. The process management unit 531 can also select a CPU (or a node in which the CPU is located) that will put the process 511 in a run state when the input / output is completed, in accordance with the path selected by the I / O management unit 521.

[0107] In this embodiment, when the process management unit 531 selects a CPU that will put the process 511 into a running state when the input / output is completed, the process management unit 531 selects a CPU that belongs to the same node as the path selected for input / output by the I / O management unit 521.

[0108] Next, the detailed operation of each function will be described with reference to a flowchart.

[0109] 9 is a flowchart showing the procedure of processing of process 511. Various applications 51 can run on computer system 1. Process 511 is managed by the OS as the smallest program unit constituting application 51. Process 511 runs on the CPU. The procedure will be described below with reference to this flowchart.

[0110] In step S000, the process 511 determines whether or not to end. If the process 511 ends (step S000: YES), the entire processing of this flowchart ends. If the process 511 does not end (step S000: NO), the process proceeds to the next step S001.

[0111] In step S001, the process 511 performs processing specific to the application. However, the processing in this step does not include I / O. The I / O processing is performed in the next step S002.

[0112] In step S002, the process 511 makes a request for access (Read / Write) to the storage 2. Specifically, the process 511 accesses the storage 2 by calling the I / O management unit 521, which is a part of the function of the OS 52. After the processing of this step ends, the process returns to step S000.

[0113] 10 is a flowchart showing the procedure of the initialization process executed by the I / O management unit 521 when the OS is started. A plurality of storages 2 can be connected to the computer system 1. One of the plurality of storages 2 is referred to as storage (i), where i is an integer that serves as an index. The procedure will be explained below with reference to this flowchart.

[0114] In step S010, the I / O management unit 521 judges whether or not creation of path information for all storages 2 connected to the computer system 1 has been completed. If it has been completed (step S010: YES), the process jumps to step S013. If it has not been completed (step S010: NO), the process proceeds to the next step S011. In other words, after creation of path information for all storages has been completed, the process proceeds to step S013 and subsequent steps.

[0115] When the process proceeds to step S011, the I / O management unit 521 acquires information about the I / O path connected to the storage (i).

[0116] Next, in step S012, the I / O management unit 521 stores the path information of the storage (i) in the area of ​​the path information 522. The path information of each storage that the I / O management unit 521 writes to the area of ​​the path information 522 includes the number of I / O paths (N), an initial value of the master path number (M), and information of the I / O control unit (C) of each path. The value of the master path number (M) is an integer between 0 and (N-1). The initial value of the master path number (M) may be, for example, 0. The value of the master path number (M) changes, for example, at a predetermined time interval. After the processing of this step is completed, the process returns to step S010 to determine whether there is another storage for which path information creation has not been completed.

[0117] When the process proceeds to step S013, the I / O management unit 521 sets a timer notification interval 524. This timer notification interval 524 is a time interval for changing the value of the above-mentioned master path number (M).

[0118] Next, in step S014, the I / O management unit 521 sets the continuous issuance upper limit number (the issuance number control information 525). The continuous issuance upper limit number may be set to any number, and may be set to "10" as an example.

[0119] Next, in step S015, the I / O management unit 521 clears (sets to an initial value 0) the issuance count counters (the issuance count control information 525) of all storages. The issuance count counters are used to determine whether the number of I / Os has reached the above-mentioned continuous issuance upper limit number.

[0120] Next, in step S016, the I / O management unit 521 starts a timer. This timer is a general timer implemented in a CPU. When this timer is started, a timekeeping operation begins, and a timer interrupt of the I / O management unit 521 occurs periodically at the timer notification interval 524 set in step S013. When this timer interrupt occurs, a timer interrupt process (see FIG. 12) described later is called.

[0121] 11 is a flowchart showing the procedure of processing a storage read / write request by the I / O management unit 521. The processing of this I / O management unit 521 is started by the storage read / write request from the process 511 in step S002 of FIG.

[0122] First, in step S020, the I / O management unit 521 acquires, from the path information 522, path information for the storage (i) designated as the access target.

[0123] In step S021, the I / O management unit 521 judges whether the value of the issue counter of the storage (i) has reached the continuous issue upper limit number. The issue counter and the continuous issue upper limit number are both included in the issue count control information 525. If the value of the issue counter has already reached the continuous issue upper limit number (step S021: YES), proceed to the next step S022. If the value of the issue counter has not yet reached the continuous issue upper limit number (step S021: NO), jump to step S024.

[0124] When the process proceeds to step S022, the I / O management unit 521 performs processing to change the path to the storage (i). That is, the I / O management unit 521 updates the master path number (M) of the storage (i). The formula for this update is as shown in formula (4) below. In formula (4), "%" is an operator that finds the remainder in integer division.

[0125] M = (M + 1)% Number of passes (N) (4)

[0126] That is, by performing the calculation of equation (4), as described above, the I / O manager 521 updates the master path numbers so as to circulate the master path numbers.

[0127] Next, in step S023, the I / O management unit 521 clears the value of the issue counter of the storage (i). That is, the I / O management unit 521 initializes the issue counter to 0.

[0128] In step S024, the I / O management unit 521 calculates a path number (P) to be used from the master path number (M) and the process ID of the initiating process. The path number is calculated using the following formula (5).

[0129] P = (M + hash(process ID))%N (5)

[0130] Equation (5) is intended to distribute the paths used by each process as evenly as possible. In equation (5), hash() is an appropriate hash function. This equation distributes the paths used globally. Note that it is desirable to simplify the logic (calculation procedure) of the hash function hash() as much as possible, and to reduce the number of bits of the calculated hash value so that it can express the number of paths (N), thereby quickly calculating the hash value. Note that if the process ID values ​​are originally distributed, the hash function may not be necessary.

[0131] Next, in step S025, the I / O management unit 521 prepares or generates a semaphore ID corresponding to the calculated path number (P).

[0132] Next, in step S026, the I / O management unit 521 increments (+1) the value of the issue count counter of the storage (i).

[0133] In step S027, the I / O management unit 521 instructs the process management unit 531 of the execution CPU to read / write by notifying the access instruction information, the semaphore ID (F) of the destination of the end notification, and the I / O control unit (C) of the path number (P). The access instruction information includes the transfer target storage (i), the storage address, the main memory address, the data transfer size, the data transfer direction, etc.

[0134] Based on the notification in step S027, the process management unit 531 starts the operation of the I / O request (see FIG. 14). When the process management unit 531 finishes processing the I / O request, the process returns to the I / O management unit 521. Then, the I / O management unit 521 proceeds to step S028 without waiting for a response from the I / O control unit 533.

[0135] In step S028, the I / O management unit 521 requests the process management unit 531 to wait at the completion notification destination semaphore ID (F) prepared or generated in step S025. In response to this request, the process management unit processes the wait request (see FIG. 15). As a result, the process 511 being executed on the CPU transitions to a wait state (step S029).

[0136] When the read / write is completed, in step S030, the process 511 transitions to the run state.

[0137] Fig. 12 is a flowchart showing the procedure of the timer interrupt operation of the I / O management unit 521. The process shown in Fig. 12 is periodically executed by the timer operating according to the timer notification interval 524 set in step S013 of Fig. 10.

[0138] In step S040, the I / O management unit 521 updates the master path numbers (M) of all storage devices. The I / O management unit 521 calculates the updated master path numbers (M) using the following formula (6).

[0139] M = (M + 1)%N (6)

[0140] In step S041, the I / O management unit 521 clears (initializes to 0) the issue count counters of all storage devices. Through these processes, the timer interrupt process of the I / O management unit 521 ends.

[0141] The process shown in Fig. 12 is executed periodically. In other words, the master path number of the storage is switched periodically.

[0142] 13 is a flowchart showing the procedure of the main processing of the process management unit 531. The main processing of the process management unit 531 will be described below with reference to this flowchart.

[0143] First, in step S050, the process management unit 531 checks whether there is a request from the I / O management unit 521 or the I / O control unit 533. If there is a request (step S050: YES), the process proceeds to step S056. If there is no request (step S050: NO), the process proceeds to step S051.

[0144] When the process proceeds to step S051, the process management unit 531 checks whether or not a process exists in the ready queue of the own node, and then branches to the next step S052 depending on the check result.

[0145] In step S052, the process management unit 531 branches according to the confirmation result in step S051 above. That is, if there is a process in the ready queue of the own node (step S052: YES), the process proceeds to step S053 to execute the process. If there is no process in the ready queue of the own node (step S052: NO), the process proceeds to step S059.

[0146] In step S053, the process management section 531 extracts the process (A) to be executed from the ready queue of the own node.

[0147] Next, in step S054, the process management unit 531 sets the process information 512 of the process (A) to be executed in various registers in the CPU.

[0148] Next, in step S055, process management unit 531 executes the process. That is, process (A) is executed on the CPU, and the process (A) goes into a run state.

[0149] On the other hand, when the process proceeds from step S050 to step S056, the process management unit 531 sequentially determines the type of the request. That is, in step S056, the process management unit 531 determines whether or not the request confirmed in step S050 is a wait request. If it is a wait request (step S056: YES), the process proceeds to step S060 (FIG. 15). If it is not a wait request (step S056: NO), the process proceeds to the next step S057.

[0150] In step S057, the process management unit 531 judges whether the request confirmed in step S050 is an I / O request. If it is an I / O request (step S057: YES), the process proceeds to step S070 (FIG. 14). If it is not an I / O request (step S057: NO), the process proceeds to the next step S058.

[0151] In step S058, the process management unit 531 determines whether the request confirmed in step S050 is an I / O termination request. If it is an I / O termination request (step S058: YES), the process proceeds to step S090 (FIG. 17). If it is not an I / O termination request (step S058: NO), the process management unit 531 further determines what other request it is and handles it accordingly.

[0152] After performing the processing in response to each request, the control of process management unit 531 returns to step S050. Also, after executing the process in step S055, the control of process management unit 531 returns to step S050.

[0153] If it is determined in step S052 that there is no ready process, in step S059, the process management unit 531 determines whether or not a process is currently being executed. If a process is currently being executed (step S059: YES), the process proceeds to step S055. That is, the process is in a run state. On the other hand, if a process is not currently being executed (step S059: NO), the process returns to step S050 again.

[0154] Fig. 14 is a flowchart showing the procedure for processing an I / O request by the process management unit 531. The process in Fig. 14 is called from the branch of step S057: YES in Fig. 13 via the connector "B". Note that the processing of an I / O request to the process management unit 531 is based on the notification from the I / O management unit 521 in step S027 in Fig. 11.

[0155] In step S070, the process management unit 531 calculates the completion notification destination node number (D) from the I / O control unit (C) notified from the I / O management unit 521. The completion notification destination node number (D) to be calculated is the number of the node to which the I / O control unit (C) belongs. In this step, the process management unit 531 may calculate the completion notification destination node number (D) from the number of the I / O control unit (C), or may calculate the completion notification destination node number (D) by calculating some configuration information.

[0156] Next, in step S071, the process management unit 531 adds instruction data to the instruction queue of the I / O control unit (C). This instruction data includes access instruction information, a completion notification destination semaphore ID (F), and a completion notification destination node number (D).

[0157] Next, in step S072, the process management unit 531 notifies the I / O control unit (C) that the instruction data has been added to the instruction queue. After this step ends, the control of the process management unit 531 returns to the main processing (FIG. 13).

[0158] By issuing the notification in step S072, the process in step S027 (FIG. 11) in the I / O management unit 521 is completed.

[0159] Fig. 15 is a flowchart showing the procedure for processing a wait request by the process management unit 531. The process in Fig. 15 is called from the branch of step S056: YES in Fig. 13 via the connector "A". Note that the processing of an I / O request to the process management unit 531 is based on the wait request from the I / O management unit 521 in step S028 in Fig. 11. The process procedure will be explained below with reference to the flowchart.

[0160] In step S060, process management unit 531 reads various registers in the CPU and stores the contents in process information 512 of process (A). As a result, the execution state of process (A) is saved in process information 512. By saving the register contents at the time of entering the wait state in this way, it becomes possible to resume process processing from that state the next time the process enters the run state.

[0161] Next, in step S061, the process management unit 531 adds the process (A) to the wait queue of the semaphore ID (F). This puts the process (A) into a wait state. After this step ends, the control of the process management unit 531 returns to the main processing (FIG. 13).

[0162] Fig. 16 is a flowchart showing the procedure for accessing the storage 2 in the I / O control unit 533. The I / O control unit 533 operates in the I / O control unit 6 shown in Fig. 1. Upon receiving the notification made by the process management unit 531 in step S072 in Fig. 14, the process shown in Fig. 16 is started. The procedure will be described below with reference to the flowchart.

[0163] In step S080, the I / O control unit 533 refers to and checks the instruction queue of its own node.

[0164] In step S081, the I / O control unit 533 determines whether or not there is instruction data in the instruction queue of its own node. If there is instruction data (step S081: YES), the process proceeds to the next step S082. If there is no instruction data (step S081: NO), the process performs anomaly handling and then ends the process of this flowchart.

[0165] In step S082, the I / O control unit 533 extracts instruction data from the instruction queue of the own node. The instruction data is added to the instruction data in the process in step S071 of Fig. 14. That is, the instruction data includes access instruction information, the completion notification destination semaphore ID (F), and the completion notification destination node number (D).

[0166] Next, in step S083, the I / O control unit 533 performs read / write to the storage 2 in accordance with the access instruction information extracted in step S082 above. The I / O control unit 533 also transfers data to and from the main memory 5. That is, when reading data from the storage 2, the I / O control unit 533 writes the data read from the storage 2 to the main memory 5. Also, when writing data to the storage 2, the I / O control unit 533 sends the data read from the main memory 5 to the storage 2 side. When this data transfer is complete, that is, when the read / write is complete, the process proceeds to the next step S084.

[0167] In step S084, the I / O control unit 533 adds the end notification destination semaphore ID (F) to the end queue of the own node.

[0168] Next, in step S085, the I / O control unit 533 issues an I / O end request to the CPU belonging to node number (D). In the processing of this step, if there are multiple CPUs belonging to the target node, the I / O control unit 533 may select one of the multiple CPUs by using some method and issue an I / O end request to the selected CPU. Alternatively, the I / O control unit 533 may issue an I / O end request to all CPUs belonging to the target node.

[0169] In the former case (when selecting one CPU), a CPU selection method may be, for example, to store information in the main memory indicating whether each CPU included in the CPU group 4 is executing a process, and the I / O control unit 533 refers to the information and notifies the CPUs that are not executing a process. In the latter case (when issuing a termination request to all CPUs in the target node), all CPUs that receive the notification start the process of FIG. 17, but only the CPU that first checks the end queue (the process of steps S091 and S092 in FIG. 17) among those CPUs performs subsequent processes from the end queue and performs subsequent processes (the process after step S093 in FIG. 17). In other words, a mechanism may be used in which the CPU that checks the end queue second or later determines that the end queue is empty (S092: NO) and suspends the process.

[0170] That is, one node may have multiple CPUs (processors). In this case, which of the multiple CPUs belonging to a specific node will take over the execution of the process is determined using one of multiple methods (first method or second method) as follows. As a first method, the process management unit 531 selects one of the multiple CPUs on the node. Also, the process management unit 531 controls the selected CPU so that the target process is in a run state. Here, an example of the method for selecting one CPU is as follows. That is, the process management unit 531 can select one CPU that is not executing other processes from the multiple CPUs on the node, and control the selected CPU so that the target process is in a run state. As a second method, the process management unit 531 notifies the multiple CPUs on the node (for example, all CPUs on the node) to put the target process in a run state. As an example, the process management unit 531 puts all of those CPUs in a state where they can take out a notification from the queue. Then, the CPU that takes out the notification earliest among the multiple CPUs that have received the notification puts the target process in a run state in its own CPU.

[0171] Fig. 17 is a flowchart showing the procedure for processing an I / O end request by the process management unit 531. The process shown in Fig. 17 is started by the process of step S085 by the I / O control unit 533 in Fig. 16. The procedure for the I / O end request process will be described below with reference to the flowchart.

[0172] In step S090, the process management unit 531 identifies the I / O control unit (C) that has issued the I / O termination request. A request from the I / O control unit 533 to the process management unit 531 is generally made using a hardware function for inter-processor communication (inter-CPU communication). Inter-processor communication is an existing technology. In inter-processor communication, it is also possible to identify and specify the request source (sender) processor using existing technology. The process management unit 531 can identify the I / O control unit (C) that has issued the I / O termination request using such existing technology.

[0173] Next, in step S091, the process management section 531 checks the end queue of the I / O control section (C).

[0174] Then, in step S092, the process management unit 531 determines whether or not a destination semaphore ID for end notification exists in the end queue confirmed in step S091. If a destination semaphore ID for end notification exists (S092: YES), the process proceeds to the next step S093. If a destination semaphore ID for end notification does not exist (S093: NO), the process determines that an abnormality has occurred and performs further processing to address the situation, or simply interrupts and ends the processing of this flowchart. As described above, if another CPU in the same node has already extracted data from the end queue, the destination semaphore ID for end notification does not exist in the end queue.

[0175] In step S093, the process management unit 531 extracts the end notification destination semaphore ID (F) from the end queue.

[0176] Next, in step S094, the process management unit 531 checks the wait queue of the completion notification destination semaphore ID (F) extracted in step S093.

[0177] Then, in step S095, the process management unit 531 determines whether or not there is a wait process in the wait queue confirmed in step S094. If there is a wait process in the wait queue (S095: YES), the process proceeds to the next step S096. If there is no wait process in the wait queue (S095: NO), some kind of abnormality has occurred, and the process management unit 531 performs processing to deal with this abnormality.

[0178] In step S096, the process management section 531 takes out the process (A) from the wait queue.

[0179] Next, in step S097, the process management unit 531 adds the process (A) to the ready queue of the own node, whereby the process (A) becomes ready.

[0180] When the processing in Fig. 17 ends, the process returns to the main processing in Fig. 13. In the main processing in Fig. 13, the process (A) in the ready state is taken out of the ready queue and execution of the process is resumed on the CPU, thereby ending the processing of the I / O management unit 521 in Fig. 11. Furthermore, the processing of step S002 in Fig. 9 is also completed.

[0181] According to this embodiment, the I / O management unit 521 can select a path for performing I / O (input / output). Furthermore, after the I / O is completed, the process that is the source of the I / O request can be put into a run state in the CPU selected according to the selected path. In other words, the CPU that executes the process 511 can be dynamically changed. This can improve the performance of access to the storage 2 (external device).

[0182] Second Embodiment Next, another embodiment according to the present disclosure will be described with reference to the drawings. Note that the description of the matters already described in the other embodiments may be omitted below. Here, the description will be centered on matters unique to this embodiment.

[0183] Fig. 18 and Fig. 19 are schematic diagrams showing an example of an operation sequence when the computer system 1 of the present disclosure operates. Fig. 18 and Fig. 19 show a series of operation sequences. That is, after the operation sequence shown in Fig. 18, the operation sequence shown in Fig. 19 is executed.

[0184] The basic configuration of the hardware and software of the computer system in this embodiment is similar to that described in the other embodiments, so a detailed description thereof will be omitted here.

[0185] In the embodiment already described, the paths used for accessing the storage 2 were distributed based on the number of accesses. The operation sequence of this embodiment (FIGS. 18 and 19) improves on this point. That is, in this embodiment, the paths to be used are distributed based on the amount of data transferred when accessing the storage 2. In other words, this embodiment acts to eliminate or reduce the imbalance in the amount of data between I / O paths. In other words, this embodiment can level out the imbalance in the amount of data transferred for each path used.

[0186] The specific features of the operation procedure in this embodiment are as follows.

[0187] One of the features of the operation sequence of this embodiment is the operation of S409 (FIG. 18) and S423 (FIG. 19) by the I / O control unit 533 operating in each node. After notifying the process management unit 531 of the end of storage access (S075), the I / O control unit 533 stores I / O operation information in the main memory in S409 (node ​​#0) or S423 (node ​​#2). Here, the I / O operation information is, for example, a value obtained by dividing the time actually taken for data transfer by the actual time (=operation rate), and is a value measured by the I / O control unit 533 at intervals of several seconds. The I / O operation information written in the main memory can be read by other functional units.

[0188] Incidentally, the storage of the above operational information in the main memory by the I / O control unit 533 of each node may be performed, for example, immediately before or immediately after the notification of the I / O end request described in step S085 of FIG. 16.

[0189] Another feature of the operation sequence of this embodiment is the process performed when the I / O management unit 521 switches the master path number. In this embodiment, the I / O management unit 521 determines the new master path number based on the I / O operation information of all nodes stored in the main memory at the timing of switching the master path number.

[0190] Specifically, in S412 of FIG. 18, the I / O management unit 521 reads out the operation information of all the nodes from the main memory. Next, in S413, the I / O management unit 521 determines the number of the I / O path with the lowest operation rate from among all the nodes. The I / O management unit 521 sets the path number as the master path number after switching. The I / O management unit 521 saves the determined master path number in a storage means or the like. Then, in S414, the I / O management unit 521 calculates the difference between the operation rate of the I / O path with the highest operation rate and the operation rate of the I / O path with the lowest operation rate. The I / O management unit 521 saves the value of the difference in a storage means or the like. The information on the updated master path number and the information on the difference in the operation rates are referred to when the I / O management unit 521 calculates the path number (P) to be used.

[0191] In the flowchart of Fig. 11, the I / O management unit 521 updates the master path number (M) in step S022. In the flowchart of Fig. 12, the I / O management unit 521 updates the master path number (M) in step S040.

[0192] Another feature of the operation sequence of this embodiment is the method used by the I / O management unit 521 to calculate the paths to be used in S402 (FIG. 18) or S416 (FIG. 19). In this embodiment, when the I / O management unit 521 calculates the path numbers to be used in S402 or S416, it forcibly replaces the path numbers to be used with master path numbers at a predetermined rate.

[0193] As a more specific method, for example, when the I / O management unit 521 determines the path number (P) to be used, it uses the following formula (7) at a predetermined ratio instead of the already explained formula (5).

[0194] P = (M + hash(process ID))%N (5)

[0195] P = (M + 0)% N = M (7)

[0196] That is, equation (7) is obtained by replacing the hash function value "hash (process ID)" in equation (5) with "0". As a result, the master path number (M) is determined as the used path number (P) at a predetermined ratio. Note that the "predetermined ratio" may be, for example, the difference between the operation rate of the I / O path with the highest operation rate and the operation rate of the I / O path with the lowest operation rate. Since the number of the path with the lowest operation rate is determined as the master path number (M), by using equation (7), it becomes possible to increase the usage rate of the path with the low operation rate and perform load balancing taking into account the data transfer volume during I / O access.

[0197] The determination of the path number (P) by the I / O management unit 521 is the process of step S024 in the flowchart of FIG.

[0198] A specific example of this embodiment will be described. For example, if the I / O operating rates of nodes #0, #1, #2, and #3 are 25%, 30%, 10%, and 20%, respectively, the highest operating rate is 30% for node #1, and the lowest operating rate is 10% for node #2. In this case, the I / O management unit 521 sets the node #2, which has the lowest operating rate, as the master path number. That is, the master path number (M) is "2". The I / O management unit 521 also calculates the difference between the highest operating rate and the lowest operating rate as "20%" (=30%-10%). When calculating the path number to be used, the I / O management unit 521 uses the maximum value (MAX) that the hash function value "hash (process ID)" in formula (5) can take. Then, when the I / O management unit 521 actually calculates the hash function value "hash(process ID)" of equation (5), if the value is smaller than (MAX*(the above difference in operation rates)) (where "*" is a multiplication operator), it replaces "hash(process ID)" with 0. That is, it uses equation (7) instead of equation (5). For example, by using such a calculation method, it is possible to increase the frequency of use of paths with low operation rates by the amount of the above difference in operation rates.

[0199] For example, when the hash function "hash()" generates a 32-bit unsigned binary hash value, it is as follows. That is, in this case, 0xffffffff is the logical maximum value (MAX) of the hash value. Therefore, when the condition hash(process ID)<(20% (difference in operation rate)*0xffffffff) is satisfied, the I / O management unit 521 replaces the value of hash(process ID) with 0. In other words, on the premise that the hash function distributes process IDs evenly, statistically, the path number (P) used by 20% of all processes becomes the master path number (M). That is, it is as shown in the following formula (8).

[0200] P = (M + 0)% N = (2 + 0)% 4 = 2 ... (8)

[0201] The procedure for distributing paths described here is merely an example, and other calculation methods for leveling the data transfer volume between paths during I / O access may be used. For example, in addition to adjusting the frequency of use of the path number with the lowest operating rate, the frequency of use of the path number with the second or third lowest operating rate may also be adjusted.

[0202] As described above, according to this embodiment, the I / O control unit 533 records operation information that indicates the operation status of the path. Furthermore, the I / O management unit 521 selects a path to be used based on the operation information recorded for each of all paths. Here, the operation information is information that indicates the operation status of the path. In the example described in this embodiment, the operation information of a path is the input / output data transfer volume of the path in a predetermined period of the past. Note that other information may be used as the operation information. Furthermore, the I / O management unit 521 manages paths such that the smaller the input / output data transfer volume of a path in a predetermined period of the past, the more likely that the path is to be selected as a path to be used. This makes it possible to avoid concentration of use on a specific path.

[0203] In this embodiment, the I / O management unit 521 calculates the availability of each path based on the input / output data transfer volume, subtracts the availability of the path with the lowest availability from the availability of the path with the highest availability to obtain an availability difference, and makes the path with the lowest availability more likely to be selected as the path to be used based on the availability difference. This makes it more likely that the path with the lowest availability will be selected as the path to be used at an appropriate rate based on the above-mentioned availability difference.

[0204] <Third embodiment> Hereinafter, an embodiment according to the present disclosure will be described with reference to the drawings. Note that the description of the matters already described in the other embodiments may be omitted below. Here, the description will be centered on matters unique to this embodiment.

[0205] FIG. 20 is a block diagram showing a schematic configuration of a computer device according to the present disclosure and a schematic configuration of a system including the computer device.

[0206] As shown in the figure, a computer device 1001 includes a plurality of processors 1004, an input / output management unit 1521, a process management unit 1531, and a plurality of input / output control units 1533. A system 1999 includes the computer device 1001 and an external device 1002.

[0207] The computer device 1001 and the external device 1002 are connected via a plurality of paths. The paths are used for transferring input / output data between the computer device 1001 and the external device 1002, etc. In the example shown in the figure, the computer device 1001 and the external device 1002 are connected by P paths (P is an integer equal to or greater than 2). Each path is distinguished by a number such as path #0, path #1, . . . , path #(P-1). An input / output control unit 1533 exists in each of the plurality of paths.

[0208] The processor 1004 sequentially reads a series of instructions from a main memory (not shown) or the like, and operates according to those instructions. The processor 1004 may be a so-called CPU (Central Processing Unit) or GPU (Graphics Processing Unit), etc. The processor 1004 may also be a CPU having multiple cores. The processor 1004 may also be some other general-purpose or dedicated processing device. Note that while this figure shows only one processor 1004 possessed by the computer device 1001, as described above, the computer device 1001 has multiple processors 1004.

[0209] The process 1511 runs on one of the multiple processors 1004. The process 1511 may request the input / output management unit 1521 to perform input / output to the external device 1002. The process 1511 running on a certain processor 1004 can continue to run on another processor 1004 by taking over the context. For example, the process 1511 can run on a second processor 1004 different from the first processor 1004 when the process is interrupted from a state where the process was running on the first processor 1004 for some reason (for example, transition to a waiting state due to its own processing) and is restarted due to some event (for example, an interrupt from the outside). Here, the above-mentioned "context" may be the values ​​of various registers at the time when the process is interrupted, or a value stored in a main memory (not shown), or some other situation, or a combination of any two or more of them.

[0210] The external device 1002 is a device connected to the outside of the computer device 1001. The external device 1002 is, for example, a storage device. Typical examples of storage devices are a magnetic hard disk device and an SSD (solid state drive) device. The external device 1002 may be a device other than a storage device. For example, the external device 1002 may be a communication device, a printing device (printer), an image reading device (scanner), or some kind of dedicated processing device. Input / output processing (transfer of input / output data, etc.) is performed between the external device 1002 and the computer device 1001 via a path. Note that multiple paths may exist.

[0211] The I / O management unit 1521 appropriately selects a path (path in use) to be used for I / O in response to an I / O request from the process 1511 to the external device 1002, and notifies the I / O request to the I / O control unit 1533 for that path. That is, the I / O management unit 1521 selects a path to be used in response to an I / O request from the process 1511 running on the processor 1004 to the external device 1002, and instructs the I / O control unit 1533 of the selected path to perform I / O to the external device 1002. When the I / O in the external device 1002 is completed, the I / O management unit 1521 notifies the requesting process 1511 of the completion. The I / O management unit 1521 may be realized as a part of the functions of the OS. The I / O management unit 1521 is also called an "I / O management unit".

[0212] Normally, the time that the process 1511 waits for completion of input / output in the external device 1002 is longer than the time that the process 1511 waits for completion of input / output in the external device 1002 when it is executing instructions in the CPU 1004 (running state). Therefore, while the process 1511 waits for completion of input / output in the external device 1002, it is controlled to enter a waiting state without consuming the CPU.

[0213] The I / O control unit 1533 has a function of controlling I / O to the external device 1002 through a path. The I / O control unit 1533 exists for each path for I / O to the external device 1002. A destination to which a plurality of paths are connected may be a single (common) external device 1002. A destination to which a plurality of paths are connected may be a plurality of individual external devices 1002. The I / O control unit 1533 performs I / O to the external device 1002 based on an instruction from the I / O management unit 1521. This instruction from the I / O management unit 1521 may be transmitted to the I / O control unit 1533 via the process management unit 1531. When the I / O to the external device 1002 is completed, the I / O management unit 1533 notifies the process management unit 1531 of the completion. Based on this, the process 1511 that has been waiting for the completion of the I / O can detect the completion of the I / O. The I / O control unit 1533 is also called an "I / O control unit".

[0214] The process management unit 1531 controls the process 1511 (the process 1511 that requested the input / output) to be in a run state in any one of the processors 1004 when the input / output instructed by the input / output management unit 1521 to the input / output control unit 1533 is completed. Furthermore, the process management unit 1531 can select the processor 1004 that will put the process 1511 in a run state when the input / output is completed according to the path selected by the input / output management unit 1521. Instead of selecting an individual processor 1004, the process management unit 1531 may select a node to which the processor 1004 belongs. In this case, one node may include a plurality of processors 1004. When the process management unit 1531 selects a node to which the processor 1004 belongs instead of selecting an individual processor 1004, this has the same meaning as the process management unit 1531 selecting the processor 1004 that belongs to the selected node.

[0215] The process management unit 1531 can select the processor 1004 (or select the node to which the processor 1004 belongs) so that the I / O cost is as small as possible at least on some given occasion. The I / O cost represents the amount of computational resources required for I / O. The I / O cost may include the time required to read data transferred for I / O (I / O data) from a main memory or the like, transfer the data, and write the data to a main memory or the like.

[0216] As described above, the process management unit 1531 may select the processor 1004 (or the node to which the processor 1004 belongs) at least on some predetermined occasion. In other words, the process management unit 1531 may always (that is, every time input / output is performed) select the processor 1004 (or the node to which the processor 1004 belongs) so that the input / output cost is small, or may select the processor 1004 (or the node to which the processor 1004 belongs) less frequently so that the input / output cost is small.

[0217] The I / O cost may vary depending on the relationship between the processor 1004 on which the process 1511 runs and the path used for I / O.

[0218] As an example, the process management unit 1531 may select the processor 1004 (or the node to which the processor 1004 belongs) based on the number of the path selected for input / output (the number of the path to be used). However, the method by which the process management unit 1531 selects the processor 1004 (or the node to which the processor 1004 belongs) is not necessarily limited to this.

[0219] The process management unit 1531 may be realized as firmware, for example, but may also be a part of the functions of the OS rather than firmware.

[0220] That is, in this embodiment, a computer device is controlled by the following control method. That is, the control method is a control method for controlling a computer device having a plurality of processors, and includes a process in which an I / O control unit present for each path for I / O to an external device controls I / O to the external device through the path, an I / O management unit selects a path to be used in response to an I / O request to the external device from a process running on the processor, and instructs the I / O control unit of the selected path to perform I / O to the external device, and a process management unit controls the process to be in a run state in any one of the plurality of processors when the I / O instructed by the I / O management unit to the I / O control unit is completed, and the process management unit can select a processor that will put the process in a run state when the I / O is completed, in accordance with the path selected by the I / O management unit.

[0221] According to this embodiment, it is possible to dynamically change the path used for input / output. It is also possible to dynamically change the processor 1004 that executes the process 1511. In other words, by appropriately selecting the processor 1004 that executes the process 1511, it is possible to improve the efficiency of input / output.

[0222] The computer system 1 and computer device 1001 in the present disclosure are realized, for example, using the technology of a von Neumann architecture computer. In this case, a processor (such as a CPU) sequentially reads program instructions from a main memory and executes them. The processor writes data to the main memory, reads data from the main memory, and performs arithmetic and logical operations according to each instruction. When accessing the main memory, a cache memory may be used as necessary. The processor also transfers input / output data to and from the external device by issuing instructions to the external device.

[0223] The functions of each component described in the present disclosure (which may include application functions, OS functions, and other functions (e.g., middleware, etc.)) may be realized as a program (including firmware). In that case, the functions may be realized by recording a program for realizing the functions in a computer-readable recording medium, reading the program recorded in the recording medium into a computer system, and executing the program. Here, the term "computer-readable recording medium" refers to a portable medium such as a flexible disk, an optical magnetic disk, a ROM, a CD-ROM, a DVD-ROM, a USB memory, and a storage device such as a hard disk built into a computer system. In other words, the term "computer-readable recording medium" may be a non-transitory computer-readable recording medium. Furthermore, the term "computer-readable recording medium" may also include a medium that temporarily and dynamically holds a program, such as a communication line when a program is transmitted via a network such as the Internet or a communication line such as a telephone line, and a medium that holds a program for a certain period of time, such as a volatile memory inside a computer system that is a server or client in that case. The above-mentioned program may be a program for realizing a part of the above-mentioned functions, and may further be a program that can be realized in combination with a program already recorded in the computer system.

[0224] At least a part of the functions may be realized by using some kind of dedicated circuit (electronic circuit) instead of a general-purpose computer and program.

[0225] As described above, according to the present disclosure, it is possible to dynamically change the execution CPU at a predetermined timing so that the process of the I / O request source is executed by a processor of the same node as the I / O path. Also, it is possible to make the I / O path used different depending on the process. In other words, it is possible to reduce the cost of accessing the I / O path from the CPU executing the process requesting the I / O while distributing the load of the I / O path overall. For example, it is possible to control the CPU executing the process requesting the I / O and the I / O path to be on the same node.

[0226] The above "predetermined timing" is, for example, the timing when the I / O path to be used changes. However, it is not necessary to dynamically change the CPU that executes the process at every timing when the I / O path to be used changes.

[0227] In other words, it is possible to access an external device by increasing the frequency of using an optimal combination of an optimal CPU and an I / O path without deteriorating the latency of memory access.

[0228] Generally, affinity and I / O path distribution are contradictory requirements, but the technology disclosed herein makes it possible to achieve both of them simultaneously.

[0229] The background to this is that large server computers and mainframe computers are sometimes required to run mission-critical tasks 24 hours a day, 365 days a year, meaning that high performance and availability are required at the same time.

[0230] In recent years, large computers have adopted the NUMA model, and in order to pursue high performance, affinity technology is used to optimize memory access by operating the CPU and memory on the same node.

[0231] Furthermore, in order to improve availability, a multipath technology is used in which a computer device and an external device such as a storage device are connected with multiple cables so that even if a failure occurs in a path of one cable, operation can be continued through the paths of the remaining healthy cables. In a multipath configuration, multiple (all) paths are used to access an external device in order to distribute the load on the paths. When using distributed paths, if the CPU is fixed by affinity, there is a problem that in cases where a path of a different node is used, memory access crosses between nodes, resulting in worsening latency of memory access. The technology disclosed herein solves this problem.

[0232] Although the application of the technology of the present disclosure is not limited, it is particularly effective to apply the technology to, for example, large-scale computer systems such as large server computers and mainframes. In addition, it is particularly effective to apply the technology to, for example, a computer system with a NUMA architecture and a multipath configuration that is connected to an external device (such as storage) via multiple paths.

[0233] Although the present disclosure has been described above with reference to the embodiments, the present disclosure is not limited to the above-mentioned embodiments. Various modifications that can be understood by a person skilled in the art can be made to the configuration and details of the present disclosure within the scope of the present disclosure. Furthermore, each embodiment can be appropriately combined with other embodiments.

[0234] A part or all of the above-described embodiments may be described as, but is not limited to, the following supplementary notes.

[0235] (Appendix 1) A plurality of processors; an input / output control unit that exists for each path for input / output to an external device and controls input / output to the external device through the path; an input / output management unit that selects a path to be used in response to an input / output request from a process running on the processor to the external device, and instructs an input / output control unit of the selected path to input / output to the external device; a process management unit that controls the process to be in a run state in any one of the plurality of processors when an input / output instructed by the input / output management unit to the input / output control unit is completed; Equipped with the process management unit can select a processor that will put the process into a run state when the input / output is completed, according to the path selected by the input / output management unit; Computer equipment.

[0236] (Appendix 2) the computer device is configured to have a plurality of nodes; The node comprises the path and one or more of the processors. 2. The computing device of claim 1.

[0237] (Appendix 3) the process management unit, when selecting a processor for putting the process into a run state when the input / output is completed, selects the processor belonging to the same node as the path selected by the input / output management unit. 3. The computing device of claim 2.

[0238] (Appendix 4) the I / O management unit determines a master path number for identifying a master path among a plurality of paths, and selects the path to be used based on a process ID for identifying the process that has made the I / O request and the master path number; 4. A computer device according to any one of claims 1 to 3.

[0239] (Appendix 5) The input / output control unit records operation information indicating an operation status of the path, the I / O management unit selects the path to be used based on the operation information recorded for each of all paths; 2. The computing device of claim 1.

[0240] (Appendix 6) The operational information is an input / output data transfer volume in the path during a predetermined period in the past. 6. The computing device of claim 5.

[0241] (Appendix 7) the input / output management unit makes it more likely that a path having a smaller input / output data transfer volume in a predetermined period in the past is selected as the path to be used; 7. The computing device of claim 6.

[0242] (Appendix 8) A computer device; an external device connected to the computer device; A system comprising: The computer device comprises: A plurality of processors; an input / output control unit that exists for each path for input / output to an external device and controls input / output to the external device through the path; an input / output management unit that selects a path to be used in response to an input / output request from a process running on the processor to the external device, and instructs an input / output control unit of the selected path to input / output to the external device; a process management unit that controls the process to be in a run state in any one of the plurality of processors when an input / output instructed by the input / output management unit to the input / output control unit is completed; Equipped with the process management unit can select a processor that will put the process into a run state when the input / output is completed, according to the path selected by the input / output management unit; system.

[0243] (Appendix 9) A method for controlling a computer device having a plurality of processors, comprising: an input / output control unit provided for each path for input / output to an external device controls input / output to the external device through the path; an input / output management unit selecting a path to be used in response to an input / output request from a process running on the processor to the external device, and instructing the input / output control unit of the selected path to input / output to the external device; a process management unit controlling the process to be in a run state in any one of the plurality of processors when an input / output instructed by the input / output management unit to the input / output control unit is completed; Including, the process management unit can select a processor that will put the process into a run state when the input / output is completed, according to the path selected by the input / output management unit; Control methods.

[0244] (Appendix 10) A program for causing a computer device having a plurality of processors to execute a control method, The control method includes: an input / output control unit provided for each path for input / output to an external device controls input / output to the external device through the path; an input / output management unit selecting a path to be used in response to an input / output request from a process running on the processor to the external device, and instructing the input / output control unit of the selected path to input / output to the external device; a process management unit controlling the process to be in a run state in any one of the plurality of processors when an input / output instructed by the input / output management unit to the input / output control unit is completed; Including, the process management unit can select a processor that will put the process into a run state when the input / output is completed, according to the path selected by the input / output management unit; program.

[0245] (Appendix 11) One of the nodes includes a plurality of the processors. 3. The computing device of claim 2.

[0246] (Appendix 12) the process management unit selects one of the plurality of processors on the node, and controls the process to be in a run state on the selected processor; 12. The computer device of claim 11.

[0247] (Appendix 13) the process management unit selects one processor that is not currently executing another process from among the plurality of processors on the node, and controls the selected processor so that the process is in a run state; 13. The computer device of claim 12.

[0248] (Appendix 14) the process management unit notifies the processors on the node to put the process into a run state; A processor that receives the notification earliest among the plurality of processors places the process in a run state in the processor itself. 12. The computer device of claim 11.

[0249] (Appendix 15) the input / output management unit selects the path to be used based on a value obtained by applying a hash function to the process ID. 5. The computing device of claim 4.

[0250] (Appendix 16) the input / output management unit selects the path to be used by adding a value obtained by applying a hash function to the process ID in a modulo system modulo the number of paths to the master path number. 16. The computer device of claim 15.

[0251] (Appendix 17) the input / output management unit updates the master path number at a predetermined timing so as to circulate the master path number; 17. The computer device of any one of Supplementary Note 4, Supplementary Note 15, or Supplementary Note 16.

[0252] (Appendix 18) the input / output management unit calculates an operation rate of each path based on the input / output data transfer volume, determines a difference in operation rates by subtracting the operation rate of the path with the lowest operation rate from the operation rate of the path with the highest operation rate, and makes the path with the lowest operation rate more likely to be selected as the path to be used based on the difference in operation rate. 7. The computing device of claim 6.

[0253] (Appendix 19) The external device is a storage device. 17. A computer apparatus according to any one of claims 1 to 7 or claims 11 to 18.

[0254] (Appendix 20) the computer device is configured to have a plurality of nodes; The node comprises the path and one or more of the processors. 9. The system of claim 8.

[0255] (Appendix 21) the process management unit, when selecting a processor for putting the process into a run state when the input / output is completed, selects the processor belonging to the same node as the path selected by the input / output management unit. 21. The system of claim 20.

[0256] (Appendix 22) the I / O management unit determines a master path number for identifying a master path among a plurality of paths, and selects the path to be used based on a process ID for identifying the process that has made the I / O request and the master path number; 22. The system of claim 8, 20, or 21.

[0257] (Appendix 23) The input / output control unit records operation information indicating an operation status of the path, the I / O management unit selects the path to be used based on the operation information recorded for each of all paths; 9. The system of claim 8.

[0258] (Appendix 24) The operational information is an input / output data transfer volume in the path during a predetermined period in the past. 24. The system of claim 23.

[0259] (Appendix 25) the input / output management unit makes it more likely that a path having a smaller input / output data transfer volume in a predetermined period in the past is selected as the path to be used; 25. The system of claim 24.

[0260] (Appendix 26) One of the nodes includes a plurality of the processors. 21. The system of claim 20.

[0261] (Appendix 27) the process management unit selects one of the plurality of processors on the node, and controls the process to be in a run state on the selected processor; 27. The system of claim 26.

[0262] (Appendix 28) the process management unit selects one processor that is not currently executing another process from among the plurality of processors on the node, and controls the selected processor so that the process is in a run state; 28. The system of claim 27.

[0263] (Appendix 29) the process management unit notifies the processors on the node to put the process into a run state; A processor that receives the notification earliest among the plurality of processors places the process in a run state in the processor itself. 27. The system of claim 26.

[0264] (Appendix 30) the input / output management unit selects the path to be used based on a value obtained by applying a hash function to the process ID. 23. The system of claim 22.

[0265] (Appendix 31) the input / output management unit selects the path to be used by adding a value obtained by applying a hash function to the process ID in a modulo system modulo the number of paths to the master path number. 31. The system of claim 30.

[0266] (Appendix 32) the input / output management unit updates the master path number at a predetermined timing so as to circulate the master path number; 32. The system of claim 22, 30, or 31.

[0267] (Appendix 33) the input / output management unit calculates an operation rate of each path based on the input / output data transfer volume, determines a difference in operation rates by subtracting the operation rate of the path with the lowest operation rate from the operation rate of the path with the highest operation rate, and makes the path with the lowest operation rate more likely to be selected as the path to be used based on the difference in operation rate. 25. The system of claim 24.

[0268] (Appendix 34) The external device is a storage device. 8, or any one of claims 20 to 33.

[0269] (Appendix 35) the computer device is configured to have a plurality of nodes; The node comprises the path and one or more of the processors. 10. The control method according to claim 9.

[0270] (Appendix 36) the process management unit, when selecting a processor for putting the process into a run state when the input / output is completed, selects the processor belonging to the same node as the path selected by the input / output management unit. 36. The control method of claim 35.

[0271] (Appendix 37) the I / O management unit determines a master path number for identifying a master path among a plurality of paths, and selects the path to be used based on a process ID for identifying the process that has made the I / O request and the master path number; 37. The control method of any one of Supplementary Note 9, Supplementary Note 35, or Supplementary Note 36.

[0272] (Appendix 38) The input / output control unit records operation information indicating an operation status of the path, the I / O management unit selects the path to be used based on the operation information recorded for each of all paths; 10. The control method according to claim 9.

[0273] (Appendix 39) The operational information is an input / output data transfer volume in the path during a predetermined period in the past. 39. The control method of claim 38.

[0274] (Appendix 40) the input / output management unit makes it more likely that a path having a smaller input / output data transfer volume in a predetermined period in the past is selected as the path to be used; 40. The control method of claim 39.

[0275] (Appendix 41) One of the nodes includes a plurality of the processors. 36. The control method of claim 35.

[0276] (Appendix 42) the process management unit selects one of the plurality of processors on the node, and controls the process to be in a run state on the selected processor; 42. The control method of claim 41.

[0277] (Appendix 43) the process management unit selects one processor that is not currently executing another process from among the plurality of processors on the node, and controls the selected processor so that the process is in a run state; 43. The control method of claim 42.

[0278] (Appendix 44) the process management unit notifies the processors on the node to put the process into a run state; A processor that receives the notification earliest among the plurality of processors places the process in a run state in the processor itself. 42. The control method of claim 41.

[0279] (Appendix 45) Claim* the input / output management unit selects the path to be used based on a value obtained by applying a hash function to the process ID. 38. The control method of claim 37.

[0280] (Appendix 46) the input / output management unit selects the path to be used by adding a value obtained by applying a hash function to the process ID in a modulo system modulo the number of paths to the master path number. 46. ​​The control method of claim 45.

[0281] (Appendix 47) the input / output management unit updates the master path number at a predetermined timing so as to circulate the master path number; 47. The control method of any one of Appendix 37, Appendix 45, or Appendix 46.

[0282] (Appendix 48) the input / output management unit calculates an operation rate of each path based on the input / output data transfer volume, determines a difference in operation rates by subtracting the operation rate of the path with the lowest operation rate from the operation rate of the path with the highest operation rate, and makes the path with the lowest operation rate more likely to be selected as the path to be used based on the difference in operation rate. 40. The control method of claim 39.

[0283] (Appendix 49) The external device is a storage device. A control method according to any one of appendices 9, or appendices 35 to 48.

[0284] (Appendix 50) the computer device is configured to have a plurality of nodes; The node comprises the path and one or more of the processors. 11. The program according to claim 10.

[0285] (Appendix 51) the process management unit, when selecting a processor for putting the process into a run state when the input / output is completed, selects the processor belonging to the same node as the path selected by the input / output management unit. 51. The program according to claim 50.

[0286] (Appendix 52) the I / O management unit determines a master path number for identifying a master path among a plurality of paths, and selects the path to be used based on a process ID for identifying the process that has made the I / O request and the master path number; 5. The program of claim 10, 50, or 51.

[0287] (Appendix 53) The input / output control unit records operation information indicating an operation status of the path, the I / O management unit selects the path to be used based on the operation information recorded for each of all paths; 11. The program according to claim 10.

[0288] (Appendix 54) The operational information is an input / output data transfer volume in the path during a predetermined period in the past. 54. The program according to claim 53.

[0289] (Appendix 55) the input / output management unit makes it more likely that a path having a smaller input / output data transfer volume in a predetermined period in the past is selected as the path to be used; 55. The program according to claim 54.

[0290] (Appendix 56) One of the nodes includes a plurality of the processors. 51. The program according to claim 50.

[0291] (Appendix 57) the process management unit selects one of the plurality of processors on the node, and controls the process to be in a run state on the selected processor; 57. The program according to claim 56.

[0292] (Appendix 58) the process management unit selects one processor that is not currently executing another process from among the plurality of processors on the node, and controls the selected processor so that the process is in a run state; 58. The program according to claim 57.

[0293] (Appendix 59) the process management unit notifies the processors on the node to put the process into a run state; A processor that receives the notification earliest among the plurality of processors places the process in a run state in the processor itself. 57. The program according to claim 56.

[0294] (Appendix 60) the input / output management unit selects the path to be used based on a value obtained by applying a hash function to the process ID. 53. The program according to claim 52.

[0295] (Appendix 61) the input / output management unit selects the path to be used by adding a value obtained by applying a hash function to the process ID in a modulo system modulo the number of paths to the master path number. 61. The program according to claim 60.

[0296] (Appendix 62) the input / output management unit updates the master path number at a predetermined timing so as to circulate the master path number; 62. The program of claim 52, 60, or 61.

[0297] (Appendix 63) the input / output management unit calculates an operation rate of each path based on the input / output data transfer volume, determines a difference in operation rates by subtracting the operation rate of the path with the lowest operation rate from the operation rate of the path with the highest operation rate, and makes the path with the lowest operation rate more likely to be selected as the path to be used based on the difference in operation rate. 55. The program according to claim 54.

[0298] (Appendix 64) The external device is a storage device. A program according to any one of appendices 10, 50 to 63.

[0299] (Appendix 65) A computer-readable recording medium having a program recorded thereon for causing a computer device having a plurality of processors to execute a control method, The control method includes: an input / output control unit provided for each path for input / output to an external device controls input / output to the external device through the path; an input / output management unit selecting a path to be used in response to an input / output request from a process running on the processor to the external device, and instructing the input / output control unit of the selected path to input / output to the external device; a process management unit controlling the process to be in a run state in any one of the plurality of processors when an input / output instructed by the input / output management unit to the input / output control unit is completed; Including, the process management unit can select a processor that will put the process into a run state when the input / output is completed, according to the path selected by the input / output management unit; A computer-readable recording medium.

[0300] (Appendix 66) the computer device is configured to have a plurality of nodes; The node comprises the path and one or more of the processors. 66. The computer-readable storage medium of claim 65.

[0301] (Appendix 67) the process management unit, when selecting a processor for putting the process into a run state when the input / output is completed, selects the processor belonging to the same node as the path selected by the input / output management unit. 67. The computer-readable storage medium of claim 66.

[0302] (Appendix 68) the I / O management unit determines a master path number for identifying a master path among a plurality of paths, and selects the path to be used based on a process ID for identifying the process that has made the I / O request and the master path number; 68. A computer-readable recording medium according to any one of claims 65 to 67.

[0303] (Appendix 69) The input / output control unit records operation information indicating an operation status of the path, the I / O management unit selects the path to be used based on the operation information recorded for each of all paths; 66. The computer-readable storage medium of claim 65.

[0304] (Appendix 70) The operational information is an input / output data transfer volume in the path during a predetermined period in the past. 70. The computer-readable storage medium of claim 69.

[0305] (Appendix 71) the input / output management unit makes it more likely that a path having a smaller input / output data transfer volume in a predetermined period in the past is selected as the path to be used; 71. The computer-readable storage medium of claim 70.

[0306] (Appendix 72) One of the nodes includes a plurality of the processors. 67. The computer-readable storage medium of claim 66.

[0307] (Appendix 73) the process management unit selects one of the plurality of processors on the node, and controls the process to be in a run state on the selected processor; 73. The computer-readable storage medium of claim 72.

[0308] (Appendix 74) the process management unit selects one processor that is not currently executing another process from among the plurality of processors on the node, and controls the selected processor so that the process is in a run state; 74. The computer-readable storage medium of claim 73.

[0309] (Appendix 75) the process management unit notifies the processors on the node to put the process into a run state; A processor that receives the notification earliest among the plurality of processors places the process in a run state in the processor itself. 73. The computer-readable storage medium of claim 72.

[0310] (Appendix 76) the input / output management unit selects the path to be used based on a value obtained by applying a hash function to the process ID. 69. The computer-readable storage medium of claim 68.

[0311] (Appendix 77) the input / output management unit selects the path to be used by adding a value obtained by applying a hash function to the process ID in a modulo system modulo the number of paths to the master path number. 77. The computer-readable storage medium of claim 76.

[0312] (Appendix 78) the input / output management unit updates the master path number at a predetermined timing so as to circulate the master path number; 68, 76, or 77. The computer-readable storage medium of claim 68, 76, or 77.

[0313] (Appendix 79) the input / output management unit calculates an operation rate of each path based on the input / output data transfer volume, determines a difference in operation rates by subtracting the operation rate of the path with the lowest operation rate from the operation rate of the path with the highest operation rate, and makes the path with the lowest operation rate more likely to be selected as the path to be used based on the difference in operation rate. 71. The computer-readable storage medium of claim 70.

[0314] (Appendix 80) The external device is a storage device. 79. The computer-readable storage medium of any one of claims 65 to 79. [Explanation of symbols]

[0315] 1. Computer systems (computer equipment) 2 Storage (external device) 3 Node 4 CPU Group (Processor Group) 5. Main memory 6 I / O control unit (input / output control unit) 7. Cache 8 Interconnect 51 Applications 52 OS 53 Firmware 511 Process 512 Process Information 513 Application Data 521 I / O management section (input / output management section) 522 Path Information 523 Semaphore 524 timer notification interval 525 Issue count control information 531 Process Management Department 532 Ready Queue 533 I / O control unit (input / output control unit) 534 Instruction Queue 535 End Queue 1001 Computer equipment 1002 External device 1004 Processor 1511 Process 1521 Input / output management section (I / O management section) 1531 Process Management Department 1533 Input / Output Control Unit (I / O Control Unit) 1999 System

Claims

1. A plurality of processors; an input / output control unit that exists for each path for input / output to an external device and controls input / output to the external device through the path; an input / output management unit that selects a path to be used in response to an input / output request from a process running on the processor to the external device, and instructs an input / output control unit of the selected path to input / output to the external device; a process management unit that controls the process to be in a run state in any one of the plurality of processors when an input / output instructed by the input / output management unit to the input / output control unit is completed; Equipped with the process management unit can select a processor for putting the process into a run state when the input / output is completed, according to the path selected by the input / output management unit; Computer equipment.

2. the computer device is configured to have a plurality of nodes; The node comprises the path and one or more of the processors. The computer device of claim 1.

3. the process management unit, when selecting a processor for putting the process into a run state when the input / output is completed, selects the processor belonging to the same node as the path selected by the input / output management unit.

3. The computer device of claim 2.

4. the I / O management unit determines a master path number for identifying a master path among a plurality of paths, and selects the path to be used based on a process ID for identifying the process that has made the I / O request and the master path number; The computer device of claim 1.

5. The input / output control unit records operation information indicating an operation status of the path, the I / O management unit selects the path to be used based on the operation information recorded for each of all paths; The computer device of claim 1.

6. The operational information is an input / output data transfer volume in the path during a predetermined period in the past.

6. The computer device of claim 5.

7. the input / output management unit makes it more likely that a path having a smaller input / output data transfer volume in a predetermined period in the past is selected as the path to be used; 7. The computer device of claim 6.

8. A computer device; an external device connected to the computer device; A system comprising: The computer device comprises: A plurality of processors; an input / output control unit that exists for each path for input / output to an external device and controls input / output to the external device through the path; an input / output management unit that selects a path to be used in response to an input / output request from a process running on the processor to the external device, and instructs an input / output control unit of the selected path to input / output to the external device; a process management unit that controls the process to be in a run state in any one of the plurality of processors when an input / output instructed by the input / output management unit to the input / output control unit is completed; Equipped with the process management unit can select a processor that will put the process into a run state when the input / output is completed, according to the path selected by the input / output management unit; system.

9. A method for controlling a computer device having a plurality of processors, comprising: an input / output control unit provided for each path for input / output to an external device controls input / output to the external device through the path; an input / output management unit selecting a path to be used in response to an input / output request from a process running on the processor to the external device, and instructing the input / output control unit of the selected path to input / output to the external device; a process management unit controlling the process to be in a run state in any one of the plurality of processors when an input / output instructed by the input / output management unit to the input / output control unit is completed; Including, the process management unit can select a processor that will put the process into a run state when the input / output is completed, according to the path selected by the input / output management unit; Control methods.

10. A program for causing a computer device having a plurality of processors to execute a control method, The control method includes: an input / output control unit provided for each path for input / output to an external device controls input / output to the external device through the path; an input / output management unit selecting a path to be used in response to an input / output request from a process running on the processor to the external device, and instructing the input / output control unit of the selected path to input / output to the external device; a process management unit controlling the process to be in a run state in any one of the plurality of processors when an input / output instructed by the input / output management unit to the input / output control unit is completed; Including, the process management unit can select a processor for putting the process into a run state when the input / output is completed, according to the path selected by the input / output management unit; program.

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