METHOD AND APPARATUS FOR NR SIDELINK SS / PBCH BLOCK

Abstract

To provide a communication method and a system thereof for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT).SOLUTION: In a wireless network 100, a method of first UE of user equipment UE 111 to 116 comprises: determining a sidelink synchronization identity (SL-SID) and a set of resources; generating at least one sidelink synchronization signal and physical broadcast channel block (S-SSB) on the basis of the SL-SID and the set of resources; generating a first sequence corresponding to a S-PSS; generating a second sequence corresponding to a S-SSS; and transmitting, the at least one S-SSB over sidelink channels established with second UE of the UE.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present application relates generally to wireless communication systems, and more specifically, the present disclosure relates to NR sidelink SS / PBCH blocks. [Background technology]

[0002] Efforts are being made to develop improved 5G or pre-5G communication systems to meet the increasing demand for wireless data traffic after the commercialization of 4G communication systems. For this reason, 5G or pre-5G communication systems are called Beyond 4G Network or Post LTE communication systems. To achieve high data transmission rates, 5G communication systems are being considered for implementation in ultra-high frequency (mmWave) bands (e.g., 60 GHz bands). To mitigate the path loss of radio waves in ultra-high frequency bands and increase the transmission distance of radio waves, beamforming, massive MIMO, full dimensional MIMO (FD-MIMO), array antenna, analog beam-forming, and large scale antenna technologies are being discussed for 5G communication systems. Furthermore, to improve the system network, technological developments are underway in the 5G communication system, such as advanced small cell, cloud radio access network (cloud RAN), ultra-dense network, Device to Device communication (D2D), wireless backhaul, moving network, cooperative communication, CoMP (Coordinated Multi-Points), and interference cancellation.In addition, advanced coding modulation (ACM) methods such as FQAM (Hybrid FSK and QAM Modulation) and SWSC (Sliding Window Superposition Coding) and advanced access technologies such as FBMC (Filter Bank Multi Carrier), NOMA (non orthogonal multiple access), and SCMA (sparse code multiple access) are being developed for the 5G system.

[0003] Meanwhile, the Internet is evolving from a human-centered connection network where humans generate and consume information to an IoT (Internet of Things) network that exchanges and processes information between distributed components such as things. IoE (Internet of Everything) technology is also emerging, combining big data processing technology through connection to cloud servers with IoT technology. To realize IoT, technological elements such as sensing technology, wired and wireless communication and network infrastructure, service interface technology, and security technology are required, and recently technologies such as sensor networks for connecting things, machine to machine (M2M), and MTC (Machine Type Communication) are being researched. In the IoT environment, intelligent IT (Internet Technology) services can be provided that collect and analyze data generated by connected things to create new value in human life. Through the convergence and integration of existing IT (information technology) and various industries, IoT can be applied to fields such as smart homes, smart buildings, smart cities, smart cars or connected cars, smart grids, healthcare, smart home appliances, and advanced medical services.

[0004] As a result, various attempts are being made to apply 5G communication systems to IoT networks. For example, technologies such as sensor networks, machine to machine (M2M), and MTC (machine type communication) are embodied by 5G communication technologies using techniques such as beamforming, MIMO, and array antennas. The application of cloud radio access network (cloud RAN) as a big data processing technology mentioned above is also an example of the convergence of 5G technology and IoT technology. Summary of the Invention [Problem to be solved by the invention]

[0005] The present disclosure relates to a pre-5G or 5G communication system provided to support higher data transmission rates beyond 4th generation (4G) communication systems such as LTE (long-term evolution). Traditionally, cellular communication networks have been designed to establish wireless communication links between mobile user equipment (UE) and fixed communication infrastructure components (e.g., base stations (BS), enhanced base stations (gNB), or access points (AP)) that serve the UE in a wide or local geographic range. However, wireless networks can also be implemented without fixed infrastructure components, utilizing only device-to-device (D2D) communication links. This type of network is generally referred to as an "ad-hoc" network. Hybrid communication networks can support devices connected to both fixed infrastructure components and other D2D supporting devices. Although UEs such as smartphones can be envisioned for D2D networks, vehicular communication can also be supported by communication protocols in which vehicles exchange control or data information with other vehicles, other infrastructure, or UEs. Such networks are referred to as vehicle-to-everything (V2X) networks. Many types of communication links may be supported by nodes supporting V2X in a network and may utilize the same or different protocols and systems. [Means for solving the problem]

[0006] In one embodiment, a first user equipment (UE) of a wireless communication system is provided, the first UE including at least one processor configured to: determine a sidelink synchronization identity (SL-SID) and a set of resources; generate at least one sidelink synchronization signal and physical broadcast channel block (S-SSB) based on the SL-SID and the set of resources; each S-SSB of the at least one S-SSB including first two symbols for a sidelink primary synchronization signal (S-PSS) and second two symbols for a sidelink secondary synchronization signal (S-SSS); generate a first sequence corresponding to the S-PSS; the first sequence is determined based on a binary phase shift keying (BPSK) modulated M-sequence having a sequence length of 127 and low cross-correlation with the primary synchronization signal (PSS); and generate a second sequence corresponding to the S-SSS; the second sequence is determined based on a BPSK modulated Gold-sequence having a sequence length of 127. The first UE further includes a transceiver operably connected to the at least one processor and configured to transmit at least one S-SSB to the second UE via a sidelink channel established with the second UE.

[0007] In another embodiment, a second user equipment (UE) of a wireless communication system is provided, the second UE including a transceiver configured to receive at least one sidelink synchronization signal and a physical broadcast channel block (S-SSB) from the first UE via a sidelink channel established with the first UE. The second UE further includes at least one processor operatively coupled to the transceiver, the at least one processor being configured to: determine a set of resources - at least one S-SSB is received based on the set of resources, each S-SSB of the at least one S-SSB including first two symbols for a sidelink primary synchronization signal (S-PSS) and second two symbols for a sidelink secondary synchronization signal (S-SSS); detect a first sequence corresponding to the S-PSS - the first sequence is determined based on a binary phase shift keying (BPSK) modulated M-sequence having a sequence length of 127 and low cross-correlation with the primary synchronization signal (PSS); detect a second sequence corresponding to the S-SSS - the second sequence is determined based on a BPSK modulated Gold-sequence having a sequence length of 127; and further determine a sidelink synchronization identity (SL-SID) based on the detected second sequence.

[0008] In yet another embodiment, a method is provided for a first user equipment (UE) in a wireless communication system, the method including: determining a sidelink synchronization identity (SL-SID) and a set of resources; generating at least one sidelink synchronization signal and physical broadcast channel block (S-SSB) based on the SL-SID and the set of resources, each S-SSB including first two symbols for a sidelink primary synchronization signal (S-PSS) and second two symbols for a sidelink secondary synchronization signal (S-SSS); generating a first sequence corresponding to the S-PSS, the first sequence being determined based on a binary phase shift keying (BPSK) modulated M-sequence having a sequence length of 127 and low cross-correlation with the primary synchronization signal (PSS); generating a second sequence corresponding to the S-SSS, the second sequence being determined based on a BPSK modulated Gold-sequence having a sequence length of 127; and transmitting the at least one S-SSB to the second UE via a sidelink channel established with the second UE.

[0009] Other technical features may become readily apparent to those skilled in the art from the following drawings, descriptions and claims.

[0010] Before proceeding with the detailed description below, it may be helpful to provide definitions of certain words and phrases used throughout this patent specification. The term "couple" and its derivatives refer to any direct or indirect communication between two or more elements, whether or not those elements are in physical contact with one another. The terms "transmit," "receive," and "communicate" and their derivatives include both direct and indirect communication. The terms "include" and "comprise" and their derivatives are intended to mean inclusive but not limiting. The term "or" is used as an inclusive term meaning 'and / or'. The phrase "associated with" and its derivatives means include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, have a relationship to or with, and the like. The term "controller" means any device, system, or part thereof that controls at least one operation. Such a controller may be embodied in hardware or a combination of hardware and software and / or firmware. The functionality associated with a particular controller may be centralized or distributed, whether locally or remotely.The phrase "at least one of," when used in conjunction with a list of items, means that different combinations of one or more of the listed items can be used. For example, "at least one of A, B, and C" includes any one of the following combinations: A, B, C, A and B, A and C, B and C, and A, B and C.

[0011] Additionally, the various functions described below may be embodied or supported by one or more computer programs formed from computer-readable program code and embodied in a computer-readable medium. The terms "application" and "program" refer to one or more computer programs, software components, instruction sets, procedures, functions, objects, classes, instances, associated data, or portions thereof that are embodied in suitable computer-readable program code. The term "computer-readable program code" includes types of computer code, including source code, object code, and executable code. The term "computer-readable medium" includes any type of medium that can be accessed by a computer, such as read only memory (ROM), random access memory (RAM), hard disk drive, compact disc (CD), digital video disc (DVD), or any other type of memory. "Non-transitory" computer-readable medium excludes communications links that convey wired, wireless, optical, transitory electrical, or other signals. Non-transitory computer readable media includes media in which data is permanently stored, and media in which data can be stored and later overwritten, such as re-recordable optical disks or erasable memory devices.

[0012] Definitions for other specific words and phrases are provided throughout this patent specification. Those of skill in the art should understand that in many, if not most, cases such definitions may apply to both the prior and future uses of such defined words and phrases. Effect of the Invention

[0013] The present disclosure relates to pre-5G or 5G communication systems provided to support higher data transmission rates over 4G communication systems such as LTE. Embodiments of the present disclosure provide a transmission structure and format in the advanced communication system. [Brief description of the drawings]

[0014] [Figure 1] 1 illustrates an example wireless network in accordance with an embodiment of the present disclosure. [Diagram 2] 1 is a diagram illustrating an exemplary gNB according to an embodiment of the present disclosure. [Diagram 3] 1 illustrates an example UE according to an embodiment of the present disclosure. [Figure 4] 1 is a diagram illustrating an example use case of a vehicle-centric communication network according to an example embodiment of the present disclosure. [Diagram 5] 1 is a diagram illustrating an example configuration of a sidelink synchronization subframe in LTE-V2X according to an embodiment of the present disclosure. [Figure 6] 1 illustrates an example configuration of an SS / PBCH block according to an embodiment of the present disclosure. [Figure 7] 1 is a diagram illustrating an example SS / PBCH block mapping pattern with respect to subcarrier spacing in accordance with an embodiment of the present disclosure. [Figure 8] 1 is a diagram illustrating example SS / PBCH block locations within a half according to an embodiment of the present disclosure. [Figure 9A] 1 is a diagram illustrating an exemplary design of an S-SSB according to an embodiment of the present disclosure. [Figure 9B] 1 is a diagram illustrating another exemplary design of an S-SSB according to an embodiment of the present disclosure. [Figure 10A] 1 is a diagram illustrating an example S-SSB according to an embodiment of the present disclosure. [Figure 10B] 1 is a diagram illustrating another exemplary S-SSB according to an embodiment of the present disclosure. [Figure 11] 1 is a diagram illustrating yet another exemplary S-SSB according to an embodiment of the present disclosure. [Figure 12A] 1 is a diagram illustrating yet another exemplary S-SSB according to an embodiment of the present disclosure. [Figure 12B] 1 is a diagram illustrating yet another exemplary S-SSB according to an embodiment of the present disclosure. [Figure 12C] 1 is a diagram illustrating yet another exemplary S-SSB according to an embodiment of the present disclosure. [Figure 13A] 1 is a diagram illustrating yet another exemplary S-SSB according to an embodiment of the present disclosure. [Figure 13B] 1 is a diagram illustrating yet another exemplary S-SSB according to an embodiment of the present disclosure. [Figure 14A] 1 is a diagram illustrating yet another exemplary S-SSB according to an embodiment of the present disclosure. [Figure 14B] 1 is a diagram illustrating yet another exemplary S-SSB according to an embodiment of the present disclosure. [Figure 14C] 1 is a diagram illustrating yet another exemplary S-SSB according to an embodiment of the present disclosure. [Figure 14D] 1 is a diagram illustrating yet another exemplary S-SSB according to an embodiment of the present disclosure. [Figure 14E] 1 is a diagram illustrating yet another exemplary S-SSB according to an embodiment of the present disclosure. [Figure 15A] 1 is a diagram illustrating yet another exemplary S-SSB according to an embodiment of the present disclosure. [Figure 15B] 1 is a diagram illustrating yet another exemplary S-SSB according to an embodiment of the present disclosure. [Figure 15C] 1 is a diagram illustrating yet another exemplary S-SSB according to an embodiment of the present disclosure. [Figure 16A] 1 is a diagram illustrating yet another exemplary S-SSB according to an embodiment of the present disclosure. [Figure 16B] 1 is a diagram illustrating yet another exemplary S-SSB according to an embodiment of the present disclosure. [Figure 17]1 is a diagram illustrating an example time domain mapping of an S-SSB burst set according to an embodiment of the present disclosure. [Figure 18] 1 is a diagram illustrating example PAPR values ​​of S-PSS sequences according to an embodiment of the present disclosure. [Figure 19] 11 is a diagram illustrating other example PAPR values ​​of S-PSS sequences according to an embodiment of the present disclosure. [Figure 20] 4 illustrates yet other example PAPR values ​​of S-PSS sequences in accordance with an embodiment of the present disclosure. [Figure 21] 1 is a diagram illustrating an example time domain mapping of an S-SSB burst set according to an embodiment of the present disclosure. [Figure 22] 1 is a drawing illustrating another example time domain mapping of S-SSB burst sets according to an embodiment of the present disclosure. [Figure 23] 1 is a drawing illustrating another example time domain mapping of S-SSB burst sets according to an embodiment of the present disclosure. [Figure 24] 1 is a drawing illustrating another example time domain mapping of S-SSB burst sets according to an embodiment of the present disclosure. [Diagram 25] 1 is a diagram illustrating an example scrambling of a PSBCH according to an embodiment of the present disclosure. [Figure 26] 13 is a diagram illustrating another example scrambling of the PSBCH according to an embodiment of the present disclosure. [Figure 27] 11 is a diagram illustrating yet another example scrambling of a PSBCH according to an embodiment of the present disclosure. [Figure 28] 11 is a diagram illustrating yet another example scrambling of a PSBCH according to an embodiment of the present disclosure. [Figure 29] 11 is a diagram illustrating yet another example scrambling of a PSBCH according to an embodiment of the present disclosure. [Diagram 30] 1 is a diagram illustrating an example TDM pattern for PSBCH and DMRS according to an embodiment of the present disclosure. [Diagram 31]1 is a diagram illustrating an example S-SSB according to an embodiment of the present disclosure. [Diagram 32] 1 is a diagram illustrating another exemplary S-SSB according to an embodiment of the present disclosure. [Figure 33A] 1 is a diagram illustrating yet another exemplary S-SSB according to an embodiment of the present disclosure. [Figure 33B] 1 is a diagram illustrating yet another exemplary S-SSB according to an embodiment of the present disclosure. [Figure 34A] 1 is a diagram illustrating yet another exemplary S-SSB according to an embodiment of the present disclosure. [Figure 34B] 1 is a diagram illustrating yet another exemplary S-SSB according to an embodiment of the present disclosure. [Figure 35A] 1 is a diagram illustrating yet another exemplary S-SSB according to an embodiment of the present disclosure. [Figure 35B] 1 is a diagram illustrating yet another exemplary S-SSB according to an embodiment of the present disclosure. [Figure 36A] 1 is a diagram illustrating yet another exemplary S-SSB according to an embodiment of the present disclosure. [Figure 36B] 1 is a diagram illustrating yet another exemplary S-SSB according to an embodiment of the present disclosure. [Figure 37] 1 is a diagram illustrating an example S-SSB location within a slot according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] For a more complete understanding of the present disclosure, and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings, in which like reference characters indicate like parts and in which:

[0016] 1 to 37 described below, and various embodiments used to explain the principles of the present disclosure in this patent specification, are merely illustrative and should not be construed in any way as limiting the scope of the present disclosure. Those skilled in the art will appreciate that the principles of the present disclosure may be embodied in any suitably configured system or device.

[0017] The following documents, namely 3GPP(R) TS 38.211 v15.2.0, “NR;Physical channels and modulation;”3GPPTS38.212v15.2.0, “NR;Multiplexing and channel coding;”3GPP TS 38.213 v15.2.0, “NR;Physical layer procedures for control;”3GPP TS 38.214 3GPP TS 36.212 v15.2.0, “E-UTRA;Multiplexing and Channel coding;”3GPP TS 3GPP TS 36.213 v15.2.0, "E-UTRA; Physical Layer Procedures;" and 3GPP TS 36.331 v15.2.0, "E-UTRA; Radio Resource Control (RRC) Protocol Specification;," are incorporated by reference into this disclosure as if fully set forth herein.

[0018] In the following, Fig. 1 to Fig. 3, various embodiments implemented in a wireless communication system using orthogonal frequency division multiplexing (OFDM) or orthogonal frequency division multiple access (OFDMA) communication technology are described. The description in Fig. 1 to Fig. 3 does not imply physical or architectural limitations on the manner in which different embodiments may be implemented. Other embodiments of the present disclosure may be implemented in any appropriately configured communication system.

[0019] 1 is a diagram illustrating an example wireless network according to an embodiment of the present disclosure. The embodiment of the wireless network illustrated in FIG. 1 is for illustration only. Other embodiments for the wireless network 100 may be used within the scope of the present disclosure.

[0020] 1, the wireless network includes gNB101, gNB102, and gNB103. gNB101 communicates with gNB102 and gNB103. gNB101 also communicates with at least one network 130, such as the Internet, a dedicated Internet Protocol (IP) network, or other data network.

[0021] The gNB 102 provides wireless broadband access to the network 130 for a first plurality of user equipment (UE) within the coverage area 120 of the gNB 102. The first plurality of UEs includes UE 111, which may be located at a small or medium business (SB); UE 112, which may be located at a large enterprise (E); UE 113, which may be located at a WiFi hotspot (HS); UE 114, which may be located at a first residential area (R); UE 115, which may be located at a second residential area (R); and UE 116, which may be a mobile device (M) such as a mobile phone, wireless laptop, wireless PDA, etc. The gNB 103 provides wireless broadband access to the network 130 for a second plurality of UEs within the coverage area 125 of the gNB 103. The second plurality of UEs includes UE 115 and UE 116. In some embodiments, one or more of the gNBs 101-103 can communicate among each other and with the UEs 111-116 using 5G, LTE, LTE-A, WiMAX, WiFi, or other wireless communication technologies.

[0022] Depending on the network type, the term "base station" or "BS" may refer to a component (or collection of components) configured to provide wireless access to the network, such as a transmission point (TP), a transmit-receive point (TRP), an enhanced base station (eNodeB or eNB), a 5G base station (gNB), a macrocell, a femtocell, a WiFi access point (AP), or other wireless-enabled device. A base station may provide wireless access via one or more wireless communication protocols, such as 5G 3GPP new radio interface / access (NR), long term evolution (LTE), LTE-advanced (LTE-A), high speed packet access (HSPA), Wi-Fi 802.11a / b / g / n / ac, etc. For convenience, the terms "BS" and "TRP" are used interchangeably in this patent specification to refer to a network infrastructure that provides wireless access to remote terminals. Additionally, depending on the network type, the term "user equipment" or "UE" can refer to any component such as a "mobile station," "subscriber station," "remote terminal," "wireless terminal," "receiving point," or "user equipment." For convenience, the terms "user equipment" and "UE" are used in this patent specification to refer to remote wireless equipment that wirelessly accesses a BS, whether the UE is a mobile device (e.g., a mobile phone or smartphone) or what are generally considered fixed devices (e.g., a desktop computer or vending machine).

[0023] The dotted lines indicate the approximate extents of coverage areas 120 and 125, shown in approximate outline for purposes of illustration and explanation only. It should be clearly understood that the coverage areas associated with a gNB, e.g., coverage areas 120 and 125, may have other shapes, including irregular shapes, depending on the configuration of the gNB and changes in the radio environment with respect to natural and man-made obstacles.

[0024] As described in more detail below, one or more of the UEs 111-116 include circuitry, programming, or a combination thereof for reliable reception of data and control information in an advanced wireless communication system. In certain embodiments, one or more of the gNBs 101-103 include circuitry, programming, or a combination thereof for efficient NR sidelink SS / PBCH block operation in an advanced wireless communication system.

[0025] Although Figure 1 illustrates an example wireless network, various changes may be made to Figure 1. For example, a wireless network may include any number of gNBs and any number of UEs in any suitable arrangement. Also, gNB 101 may directly communicate with any number of UEs and provide the UEs with wireless broadband access to network 130. Similarly, each gNB 102-103 may directly communicate with network 130 and provide the UEs with direct wireless broadband access to network 130. Also, gNBs 101, 102, and / or 103 may provide access to different or additional external networks, such as an external telephone network or other types of data networks.

[0026] 2 is a diagram illustrating an example gNB 102 according to an embodiment of the present disclosure. The embodiment of gNB 102 illustrated in FIG. 2 is for illustrative purposes only, and gNBs 101 and 103 of FIG. 1 may have the same or similar configurations. However, gNBs may have a variety of different configurations, and FIG. 2 does not limit the scope of the present disclosure to any particular implementation of a gNB.

[0027] 2, the gNB 102 includes multiple antennas 205a-205n, multiple RF transceivers 210a-210n, transmit (TX) processing circuitry 215, and receive (RX) processing circuitry 220. The gNB 102 also includes a controller / processor 225, a memory 230, and a backhaul or network interface 235.

[0028] The RF transceivers 210a-210n receive incoming RF signals from the antennas 205a-205n, such as signals transmitted by UEs in the network 100. The RF transceivers 210a-210n down-convert the incoming RF signals and generate IF or baseband signals. The IF or baseband signals are transmitted to RX processing circuitry 220, which generates processed baseband signals by filtering, decoding, and / or digitizing the baseband or IF signals. The RX processing circuitry 220 transmits the processed baseband signals to the controller / processor 225 for further processing.

[0029] TX processing circuitry 215 receives analog or digital data (e.g., voice data, web data, email, or interactive video game data) from controller / processor 225. TX processing circuitry 215 encodes, multiplexes, and / or digitizes outgoing baseband data and generates processed baseband or IF signals. RF transceivers 210a-210n receive the outgoing processed baseband or IF signals from TX processing circuitry 215 and upconvert the baseband or IF signals to RF signals that are transmitted via antennas 205a-205n.

[0030] The controller / processor 225 may include one or more processors or other processing devices that control the overall operation of the gNB 102. For example, the controller / processor 225 may control the reception of forward channel signals and the transmission of reverse channel signals by the RF transceivers 210a-210n, the RX processing circuitry 220, and the TX processing circuitry 215 according to well-known principles. The controller / processor 225 may also support additional functionality, such as more advanced wireless communication functions. For example, the controller / processor 225 may support beamforming or directional routing operations in which outgoing signals from multiple antennas 205a-205n are weighted differently to effectively steer in a desired direction. Any of a variety of other functions may be supported in the gNB 102 by the controller / processor 225.

[0031] Controller / processor 225 may also execute programs and other processes, such as the operating system, that reside in memory 230. Controller / processor 225 may move data into or out of memory 230 as requested by the executing processes.

[0032] The controller / processor 225 is also coupled to a backhaul or network interface 235. The backhaul or network interface 235 enables the gNB 102 to communicate with other devices or systems over a backhaul connection or over a network. The interface 235 may support communication over any suitable wired or wireless connection. For example, if the gNB 102 is embodied as part of a cellular communication system (e.g., supporting 5G, LTE, or LTE-A), the interface 235 may enable the gNB 102 to communicate with other gNBs over a wired or wireless backhaul connection. If the gNB 102 is embodied as an access point, the interface 235 enables the gNB 102 to transmit over a wired or wireless local area network, or over a larger network (e.g., the Internet) over a wired or wireless connection. The interface 235 includes any suitable structure supporting communication over a wired or wireless connection, e.g., an Ethernet or RF transceiver.

[0033] The memory 230 is coupled to the controller / processor 225. A portion of the memory 230 may include RAM, and another portion of the memory 230 may include flash memory or other ROM.

[0034] Although FIG. 2 illustrates one example of a gNB 102, various changes can be made to FIG. 2. For example, the gNB 102 can include any number of each component shown in FIG. 2. As one particular example, an access point can include multiple interfaces 235, and the controller / processor 225 can support a routing function for routing data between different network addresses. As another particular example, although illustrated as including a single instance of a TX processing circuit 215 and a single instance of a RX processing circuit 220, the gNB 102 can include multiple instances of each (e.g., one per RF transceiver). Additionally, the various components of FIG. 2 can be combined, subdivided, or omitted, and additional components can be added as needed.

[0035] Figure 3 is a diagram illustrating an example UE 116 according to an embodiment of the present disclosure. The embodiment of the UE 116 illustrated in Figure 3 is for illustrative purposes only, and the UEs 111-115 of Figure 1 may have the same or similar configurations. However, UEs may have a variety of different configurations, and Figure 3 does not limit the scope of the present disclosure to any particular implementation for a UE.

[0036] 3, the UE 116 includes an antenna 305, a radio frequency (RF) transceiver 310, a TX processing circuit 315, a microphone 320, and a receive (RX) processing circuit 325. The UE 116 also includes a speaker 330, a processor 340, an input / output (I / O) interface (IF) 345, a touch screen 350, a display 355, and a memory 360. The memory 360 includes an OS 361 and one or more applications 362.

[0037] The RF transceiver 310 receives from the antenna 305 an inbound RF signal transmitted by a gNB of the network 100. The RF transceiver 310 down-converts the inbound RF signal to generate an intermediate frequency (IF) or baseband signal. The IF or baseband signal is transmitted to the RX processing circuitry 325 which generates a processed baseband signal by filtering, decoding, and / or digitizing the baseband or IF signal. The RX processing circuitry 325 transmits the processed baseband signal to the speaker 330 (e.g., voice data) or to the processor 340 for further processing (e.g., web browsing data).

[0038] TX processing circuitry 315 receives analog or digital voice data from microphone 320 or other outbound baseband data (e.g., web data, email, or interactive video game data) from processor 340. TX processing circuitry 315 encodes, multiplexes, and / or digitizes the outbound baseband data and generates a processed baseband or IF signal. RF transceiver 310 receives the outbound processed baseband or IF signal from TX processing circuitry 315 and upconverts the baseband or IF signal into an RF signal that is transmitted via antenna 305.

[0039] Processor 340 may include one or more processors or other processing devices and may control the overall operation of UE 116 by executing an OS 361 stored in memory 360. For example, processor 340 may control the reception of forward channel signals and the transmission of reverse channel signals by RF transceiver 310, RX processing circuitry 325, and TX processing circuitry 315 in accordance with well-known principles. In some embodiments, processor 340 includes at least one microprocessor or microcontroller.

[0040] The processor 340 may also execute other processes and programs resident in the memory 360, such as processes for beam management. The processor 340 may move data into or out of the memory 360 as required by the executing processes. In some embodiments, the processor 340 is configured to execute applications 362 based on the OS 361 or upon signals received from the gNB or an operator. The processor 340 is further coupled to an I / O interface 345 that provides the UE 116 with the ability to connect to other devices, such as laptop computers and portable computers. The I / O interface 345 is a communication path between this peripheral and the processor 340.

[0041] Processor 340 is also coupled to a touchscreen 350 and a display 355. An operator of UE 116 can input data into UE 116 using touchscreen 350. Display 355 can be, for example, a liquid crystal display, light emitting diode display, or other display capable of rendering text and / or at least limited graphics from a website.

[0042] Memory 360 is coupled to processor 340. A portion of memory 360 may include random access memory (RAM), and another portion of memory 360 may include flash memory or other read-only memory (ROM).

[0043] Although FIG. 3 illustrates one example of a UE 116, various changes may be made to FIG. 3. For example, various components of FIG. 3 may be combined, further subdivided, or omitted, and additional components may be added as needed. As one particular example, the processor 340 may be divided into multiple processors, such as one or more central processing units (CPUs) and one or more graphics processing units (GPUs). Additionally, although FIG. 3 illustrates a UE 116 configured as a mobile phone or smartphone, the UE may be configured to operate as other types of mobile or fixed devices.

[0044] The present disclosure relates generally to wireless communication systems, and more particularly to improving PDCCH reception reliability and reducing associated signaling overhead. The communication system includes a downlink (DL) that indicates transmission from a base station or one or more transmission points to a UE, and an uplink (UL) that indicates transmission from the UE to a base station or one or more reception points.

[0045] Efforts are underway to develop improved 5G or pre-5G communication systems to meet the increasing demand for wireless data traffic after the construction of the 4G communication system. For this reason, 5G or pre-5G communication systems are called 'Beyond 4G networks' or 'Post LTE systems'. 5G wireless communication systems are expected to be implemented in higher frequency (mmWave) bands (e.g., 60 GHz band) to achieve higher data transmission rates. To reduce radio wave loss and increase transmission distance, beamforming, massive MIMO, full dimensional MIMO (FD-MIMO), array antenna, analog beamforming, and large scale antenna technologies are being discussed for 5G communication systems.

[0046] In addition, to improve the system network, the 5G communication system includes the development of advanced small cell, cloud radio access network (cloud RAN), ultra-dense network, device-to-device (D2D) communication, wireless backhaul, mobile network, cooperative communication, CoMP (Coordinated Multi-Points), and receiver interference cancellation. The 5G system includes advanced coding modulation (ACM) technologies such as FQAM (hybrid frequency shift keying and quadrature amplitude modulation) and SWSC (sliding window superposition coding), and advanced access technologies such as FBMC (filter bank multi carrier), NOMA (non-orthogonal multiple access), and SCMA (sparse code multiple access).

[0047] A time unit for DL ​​or UL signaling in a cell is called a slot, which can contain one or more symbols. Symbols can also be used in additional time units. A frequency (or bandwidth (BW)) unit is called a resource block (RB). One RB contains a number of subcarriers (SCs). For example, a slot can have a duration of 0.5 ms or 1 ms and can contain 7 symbols or 14 symbols, respectively, and an RB can have a BW of 180 kHz or 360 kHz and can contain 12 SCs with spacing between SCs of 15 kHz or 30 kHz.

[0048] DL signals include data signals carrying information content, control signals carrying DL control information (DCI), and reference signals (RS), also known as pilot signals. A gNB can transmit data information or DCI over its respective physical DL shared channel (PDSCH) or physical DL control channel (PDCCH). A gNB can transmit one or more of many types of RS, including a channel state information RS (CSI-RS) and a demodulation RS (DMRS). The CSI-RS is for a UE to measure channel state information (CSI) or perform other measurements, such as measurements related to mobility support. The DMRS can be transmitted only in the BW of each PDCCH or PDSCH, and the UE can use the DMRS to demodulate data or control information.

[0049] Vehicle-to-everything (V2X) communication includes three types of communication: 1) V2V (vehicle-to-vehicle) communication; 2) V2I (vehicle-to-infrastructure) communication; and 3) V2P (vehicle-to-pedestrian) communication. These three types of V2X can provide more intelligent services to end users by using "cooperative awareness". This means that vehicles, roadside infrastructure, and pedestrians can provide more intelligent services such as cooperative collision warning or autonomous driving by collecting knowledge of the local environment (e.g., information received from other nearby vehicles or sensor equipment), processing and sharing the knowledge. In V2V, direct communication between vehicles is based on the sidelink (SL) interface, and SL is an interface between UEs for synchronization, discovery, and communication.

[0050] 4 is a diagram illustrating an example use case of a vehicle-centric communication network 400 according to an example embodiment of the present disclosure. The embodiment of the gNB 102 illustrated in FIG. 4 is for illustration purposes only. FIG. 4 does not limit the scope of the present disclosure to any particular implementation.

[0051] 5 is a diagram illustrating an example configuration of a sidelink synchronization subframe 500 in LTE-V2X according to an embodiment of the present disclosure. The embodiment of the configuration of the sidelink synchronization subframe 500 illustrated in FIG. 5 is for illustration purposes only. FIG. 5 does not limit the scope of the present disclosure to any particular implementation.

[0052] In LTE-V2X, sidelink synchronization is achieved by detecting a sidelink synchronization signal located in a sidelink synchronization subframe. An illustration of the structure of a sidelink synchronization subframe (for a common cyclic prefix) is shown in FIG. 5, where the subframe includes 14 symbols, 13 of which are mapped for a primary sidelink synchronization signal (PSSS), a secondary sidelink synchronization signal (SSSS), a physical sidelink broadcast channel (PSBCH), or a demodulation reference signal (DMRS). The remaining one symbol (e.g., the last symbol) is reserved as empty for other purposes (e.g., DL / UL switch gap). The bandwidth of all signals and channels in a synchronization subframe is 6 RBs and is mapped to the central 6 RBs of the carrier.

[0053] The sequences constituting the PSSS are based on one of two ZC-sequences with root indices 26 and 37, respectively, to indicate one of two sets of physical layer sidelink synchronization identities. The sequences constituting the SSSS are similar to the sequences constituting the LTE Secondary Synchronization Signal (SSS), i.e., interleaved M-sequences with cyclic shifts.

[0054] The system information transmitted by PSBCH in LTE-V2X is MIB (Master Information Block), which can be further combined with CRC (Cyclic Redundancy Check) to form the entire PBCH content. The summary of LTE-V2X MIB is summarized in Table 1, which includes the field name, the bit size of each field, and the value. The total number of bits of MIB is 48, and the total bit size of PBCH content is 64 bits, adding 16 bits for another CRC.

[0055] [Table 1]

[0056] 6 is a diagram illustrating an example configuration of an SS / PBCH block 600 according to an embodiment of the present disclosure. The embodiment of the configuration of the SS / PBCH block 600 shown in FIG. 6 is for illustration purposes only. FIG. 6 does not limit the scope of the present disclosure to any particular implementation.

[0057] NR (New Radio) also supports synchronization via a synchronization signal transmitted in the downlink. Compared to LTE, NR supports a wider range of carrier frequencies and more flexible numerology. For example, NR supports multiple synchronization signals and physical broadcast channel blocks (SS / PBCH blocks) in each carrier frequency range, where each SS / PBCH block compromises four consecutive orthogonal frequency division multiplexing (OFDM) symbols (see FIG. 6), where the first symbol is mapped for the primary synchronization signal (PSS), the second and fourth symbols are mapped for the PBCH, and the third symbol is mapped for both the secondary synchronization signal (SSS) and the PBCH.

[0058] The same SS / PBCH block configuration applies to all supported carrier frequency ranges of NR from 0 GHz to 52.6 GHz. The transmission bandwidth of the PSS and SSS (e.g., 12 resource blocks (RBs)) is smaller than the transmission bandwidth of the entire SS / PBCH block (e.g., 20 RBs). In every RB mapped for the PBCH, 3 of the 12 resource elements (REs) are mapped for the DMRS (demodulation reference signal) of the PBCH, where the 3 REs are evenly distributed across the PRBs and the starting position of the first RE is based on the cell ID. In addition, NR Rel-15 supports one or two subcarrier spacings (SCSs) for SS / PBCH blocks in a given band, where the same SCS is used for the PSS, SSS and PBCH (including DMRS). For a carrier frequency range of 0 GHz to 6 GHz, 15 kHz and / or 30 kHz can be used for the SS SCS. For a carrier frequency range of 6 GHz to 52.6 GHz, 120 kHz and / or 240 kHz can be used for the SS SCS.

[0059] The sequences constituting the PSS are based on M-sequences that are cyclically shifted to indicate the cell ID information transmitted by the PSS, and the sequences constituting the SSS are based on Gold-sequences (XOR of two M-sequences), where each M-sequence constituting the Gold-sequence is cyclically shifted to indicate the cell ID information transmitted by the SSS.

[0060] 7 is a diagram illustrating an example SS / PBCH block mapping pattern 700 for subcarrier spacing according to an embodiment of the present disclosure. The embodiment of SS / PBCH block mapping pattern 700 for subcarrier spacing illustrated in FIG. 7 is for illustration purposes only. FIG. 7 does not limit the scope of the present disclosure to any particular implementation.

[0061] In NR, the SS / PBCH block can be transmitted in a beam sweeping manner to the network implementation, and multiple candidate positions for transmitting the SS / PBCH block are predefined in the half-frame unit. The mapping patterns of the SS / PBCH block for one slot are shown in 701 and 702 of FIG. 7 as the reference SCS for 15 kHz below 6 GHz and the reference SCS for 60 kHz above 6 GHz, respectively. Two mapping patterns were designed for the 30 kHz SS SCS: Pattern 1 is used for the non-LTE-NR coexistence band, and Pattern 2 is used for the LTE-NR coexistence band.

[0062] 8 is a diagram illustrating an example SS / PBCH block location 800 within a half according to an embodiment of the present disclosure. The embodiment of SS / PBCH block location 800 within a half shown in FIG. 8 is for illustration only. FIG. 8 does not limit the scope of the present disclosure to any particular implementation.

[0063] The maximum number of SS / PBCH blocks represented in L_SSB is determined based on the carrier frequency range: for carrier frequency range 0 GHz to 3 GHz, L_SSB is 4; for carrier frequency range 3 GHz to 6 GHz, L_SSB is 8; for carrier frequency range 6 GHz to 52.6 GHz, L_SSB is 64. The determination of slots within a half-frame unit containing candidate positions for SS / PBCH blocks for each combination of SS SCS and L_SSB is shown in FIG.

[0064] During initial cell selection, the UE assumes a default SS burst set periodicity of 20 ms, and to detect non-independent NR cells, the network provides the UE with one SS burst set periodicity information per frequency carrier and, if possible, information to derive measurement timing / duration.

[0065] The SS / PBCH block index is represented as the PBCH DMRS in an SS / PBCH block corresponding to a carrier frequency range of 0 to 6 GHz, and the three least significant bits (LSBs) of the SS / PBCH block index are represented as the PBCH DMRS in an SS / PBCH block corresponding to a carrier frequency range of 6 GHz to 52.6 GHz (and the three most significant bits (MSBs) are represented as the PBCH content).

[0066] In NR, the bit size of the PBCH content is 56, including the 24-bit CRC. A summary of the NR 24-bit MIB along with the other 8 bits generated by the physical layer is set forth in Table 2, where some bit sizes and their corresponding assigned values ​​are specified for each carrier frequency range.

[0067] [Table 2]

[0068] In NR V2X, the NR sidelink synchronization signal can use the downlink synchronization signal as a baseline, and potential improvements and / or modifications to address proprietary requirements for V2X can be supported. This disclosure focuses on the design of the sidelink SS / PBCH block (S-SSB), including the S-SSB configuration, synchronization signal, NR sidelink PBCH (PSBCH) content, PSBCH scrambling, DMRS for PSBCH, and pre-configured system information.

[0069] The present disclosure, features and advantages will become apparent from the following detailed description, simply by way of illustration of a number of specific embodiments and implementations, including the best mode contemplated for carrying out the disclosure. The present disclosure is capable of further different embodiments, and several details may be modified in various obvious respects, all of which do not depart from the spirit and scope of the present disclosure. Accordingly, the drawings and description should be regarded as illustrative in nature, and not restrictive. The present disclosure is illustrated by way of non-limiting example in the accompanying drawings.

[0070] The present disclosure includes a number of components that can be used together or in combination with each other, or that can operate in an independent manner.

[0071] In one embodiment, the NRSS / PBCH block configuration (e.g., FIG. 6) can be a starting point for designing the NR sidelink SS and PBCH block (S-SSB). This embodiment details a design aspect for the S-SSB configuration.

[0072] 9A is a diagram illustrating an example design of an S-SSB 900 according to an embodiment of the present disclosure. The design embodiment of the S-SSB 900 shown in FIG. 9A is for illustration purposes only. FIG. 9A does not limit the scope of the present disclosure to any particular implementation.

[0073] 9B is a diagram illustrating another exemplary design of an S-SSB 920 according to an embodiment of the present disclosure. The design embodiment of the S-SSB 920 illustrated in FIG. 9B is for illustration purposes only. FIG. 9B does not limit the scope of the present disclosure to any particular implementation.

[0074] 9A and 9B show design examples of S-SSB. The S-SSB may include at least one symbol mapped for S-PSS, at least one symbol mapped for PSBCH, and at least one symbol mapped for S-SSS or multiplexing of S-SSS and PSBCH.

[0075] As an example, only when the bandwidth of the S-SSB is 11 or 12 RBs (942 in FIG. 9B), one or more symbols mapped for the S-PSS can be mapped for the S-PSS. As another example, when the bandwidth of the S-SSB is greater than 12 RBs (e.g., 20 RBs) (943 in FIG. 9B), at least one symbol mapped for the S-PSS can be mapped for multiplexing of the S-PSS and empty REs (e.g., S-PSS and FDM-modified empty REs). As another example, when the bandwidth of the S-SSB is 24 RBs (944 in FIG. 9B), at least one symbol mapped for the S-PSS can be mapped for the S-PSS in an interleaved manner with the empty REs (e.g., empty REs and IFDM-modified symbols at the RE level such as the S-PSS sequence are mapped only to even REs or odd REs).

[0076] For example, only when the bandwidth of the S-SSB is 11 or 12 RBs (932 in FIG. 9B), at least one symbol mapped for S-SSS or multiplexing of S-SSS and PSBCH can be mapped for S-SSS. As another example, when the bandwidth of the S-SSB is greater than 12 RBs (e.g., 20 RBs) (933 in FIG. 9B), at least one symbol mapped for S-SSS or multiplexing of S-SSS and PSBCH can be mapped for multiplexing of S-SSS and PSBCH (e.g., PSBCH FDMed with S-SSS). As another example, when the bandwidth of the S-SSB is 24 RBs (934 in FIG. 9B), at least one symbol mapped for multiplexing of S-SSS or S-SSS and PSBCH can be mapped for S-SSS in an interleaved manner with empty REs (e.g., empty REs and IFDM symbols at the RE level such as the S-SSS sequence are mapped only to even REs or odd REs).

[0077] In the first approach, there can be only one symbol mapped for S-PSS in the S-SSB, for example, in the example (a) of Figure 9A, only one symbol is mapped for S-PSS in the S-SSB.

[0078] In the second approach, there may be many symbols mapped for S-PSS, where the symbols mapped for S-PSS are consecutive. For example, if there are two symbols mapped for S-PSS (e.g., example (b) of FIG. 9A), the two symbols mapped for S-PSS are #0 and #1 symbols in S-SSB. As another example, if there are three symbols mapped for S-PSS (e.g., example (c) of FIG. 9), the three symbols mapped for S-PSS are #0, #1, and #2 symbols in S-SSB. As another example, if there are two symbols mapped for S-PSS (e.g., example (b) of FIG. 9A), the two symbols mapped for S-PSS are #1 and #2 symbols in S-SSB, and the #0 symbol is for AGC purposes.

[0079] In the third approach, when there are many symbols mapped for S-PSS (e.g., example (b) or (c) in FIG. 9A), the sequences constituting the many S-PSSs with different symbols may be identical. For example, the many symbols mapped for S-PSSs (excluding cyclic prefixes) are repeated.

[0080] In the fourth approach, when there are many symbols mapped for an S-PSS (e.g., examples (b) or (c) of FIG. 9A), the sequences constituting the many S-PSSs on different symbols may be different from each other, e.g., the sequences of different symbols may be orthogonal to each other or have low cross-correlation with each other.

[0081] In the fifth approach, there can be only one symbol mapped for S-SSS in the S-SSB, for example, in example (a) of Figure 9A, only one symbol is mapped for S-SSS in the S-SSB.

[0082] In the sixth approach, there may be many symbols mapped for S-SSS, where the symbols mapped for S-SSS are non-contiguous. As an example, when there are two symbols mapped for S-SSS (e.g., example (b) of FIG. 9A), at least one symbol is mapped for PSBCH between two symbols mapped for S-SSS in S-SSB. As another example, when there are three symbols mapped for S-SSS (e.g., example (c) of FIG. 9A), at least one symbol is mapped for PSBCH between each two adjacent symbols mapped for S-SSS in S-SSB.

[0083] In the seventh approach, there may be many symbols mapped for S-SSS, where the symbols mapped for S-SSS are consecutive. As an example, if there are X_SSS (where X_SSS>1, e.g., X_SSS=2 or X_SSS=3) symbols mapped for S-SSS, the X_SSS symbols mapped for S-SSS are the last X_SSS symbols in the S-SSB.

[0084] In the eighth approach, when there are many symbols mapped for S-SSS (e.g., example (b) or (c) in FIG. 9A), the sequences constituting the many S-SSSs with different symbols may be the same. For example, the many symbols mapped for S-SSSs (excluding the cyclic prefix) are repeated.

[0085] In the ninth approach, when there are multiple symbols mapped for S-SSS (e.g., (b) or (c) of FIG. 9A), the sequences constituting the multiple S-SSS on different symbols may be different from each other. For example, the sequences of different symbols may be orthogonal to each other or have low cross-correlation with each other. As another example, a sequence of one symbol may be a sequence of another symbol scrambled by a predefined sequence.

[0086] In the tenth approach, the number of symbols mapped for PSBCH (including DMRS) in each subblock separated by symbols including S-PSS or S-SSS (e.g., 902, 904, 913, 915, 917, 924, 926, 928, 930 in FIG. 9A) may be 0, 1 or 2 and can be determined independently for each subblock.

[0087] In the eleventh approach, the DMRS of the PSBCH can be TDMed with the PSBCH. For example, some symbols of subblocks separated by symbols including S-PSS or S-SSS (e.g., 902, 904, 913, 915, 917, 924, 926, 928, and 930 in FIG. 9A) can be mapped for the DMRS of the PSBCH and can be TDMed with other symbols mapped for the PSBCH.

[0088] In the 12th approach, the DMRS of the PSBCH can be IFDMed with the PSBCH. For example, in all RBs of symbols mapped for the PSBCH, and in all RBs mapped for the PSBCH in symbols mapped for multiplexing of the S-SSS and the PSBCH when the bandwidth of the S-SSB is greater than 12 RBs, a portion of the REs are mapped for the DMRS of the PSBCH, and the remaining are mapped for the PSBCH.

[0089] In the thirteenth approach, if there are a number of consecutive symbols mapped for the PSBCH, then a number of symbols mapped for the PSBCH or a set of a number of symbols mapped for the PSBCH (excluding the cyclic prefix) may be repeated.

[0090] In a fourteenth approach, the first symbol in the S-SSB is mapped to the PSBCH, for example for processing automatic gain control (AGC).

[0091] In the 15th approach, S-PSS, S-SSS and PSBCH (including DMRS) are transmitted using the same antenna port.

[0092] Examples of approaches or combinations of approaches for this embodiment are illustrated in Figures 10A-16B.

[0093] FIG 10A is a diagram illustrating an example S-SSB 1000 according to an embodiment of the present disclosure. The embodiment of the S-SSB 1000 illustrated in FIG 10A is for illustrative purposes only. FIG 10A does not limit the scope of the present disclosure to any particular implementation.

[0094] FIG 10B is a diagram illustrating another exemplary S-SSB 1020 according to an embodiment of the present disclosure. The embodiment of the S-SSB 1020 illustrated in FIG 10B is for illustrative purposes only. FIG 10B does not limit the scope of the present disclosure to any particular implementation.

[0095] 11 is a diagram illustrating another exemplary S-SSB 1100 according to an embodiment of the present disclosure. The embodiment of the S-SSB 1100 illustrated in FIG. 11 is for illustrative purposes only. FIG. 11 does not limit the scope of the present disclosure to any particular implementation.

[0096] 12A is a diagram illustrating another exemplary S-SSB 1200 according to an embodiment of the present disclosure. The embodiment of the S-SSB 1200 illustrated in FIG. 12A is for illustrative purposes only. FIG. 12A does not limit the scope of the present disclosure to any particular implementation.

[0097] FIG 12B is a diagram illustrating yet another exemplary S-SSB 1220 according to an embodiment of the present disclosure. The embodiment of the S-SSB 1220 illustrated in FIG 12B is for illustrative purposes only. FIG 12B does not limit the scope of the present disclosure to any particular implementation.

[0098] FIG 12C is a diagram illustrating yet another exemplary S-SSB 1240 according to an embodiment of the present disclosure. The embodiment of the S-SSB 12 shown in FIG 12C is for illustrative purposes only. FIG 12C does not limit the scope of the present disclosure to any particular implementation.

[0099] FIG 13A is a diagram illustrating yet another exemplary S-SSB 1300 according to an embodiment of the present disclosure. The embodiment of the S-SSB 1300 illustrated in FIG 13A is for illustrative purposes only. FIG 13A does not limit the scope of the present disclosure to any particular implementation.

[0100] FIG 13B is a diagram illustrating yet another exemplary S-SSB 1320 according to an embodiment of the present disclosure. The embodiment of the S-SSB 1320 illustrated in FIG 13B is for illustrative purposes only. FIG 13B does not limit the scope of the present disclosure to any particular implementation.

[0101] FIG 14A is a diagram illustrating yet another exemplary S-SSB 1400 according to an embodiment of the present disclosure. The embodiment of the S-SSB 1400 illustrated in FIG 14A is for illustrative purposes only. FIG 14A does not limit the scope of the present disclosure to any particular implementation.

[0102] FIG 14B is a diagram illustrating yet another exemplary S-SSB 1420 according to an embodiment of the present disclosure. The embodiment of the S-SSB 1420 illustrated in FIG 14B is for illustrative purposes only. FIG 14B does not limit the scope of the present disclosure to any particular implementation.

[0103] FIG 14C is a diagram illustrating another exemplary S-SSB 1440 according to an embodiment of the present disclosure. The embodiment of the S-SSB 1440 illustrated in FIG 14C is for illustrative purposes only. FIG 14C does not limit the scope of the present disclosure to any particular implementation.

[0104] FIG 14D is a diagram illustrating yet another exemplary S-SSB 1460 according to an embodiment of the present disclosure. The embodiment of the S-SSB 1460 illustrated in FIG 14D is for illustrative purposes only. FIG 14D does not limit the scope of the present disclosure to any particular implementation.

[0105] FIG 14E is a diagram illustrating yet another exemplary S-SSB 1480 according to an embodiment of the present disclosure. The embodiment of the S-SSB 1480 illustrated in FIG 14E is for illustrative purposes only. FIG 14E does not limit the scope of the present disclosure to any particular implementation.

[0106] FIG 15A is a diagram illustrating yet another exemplary S-SSB 1500 according to an embodiment of the present disclosure. The embodiment of the S-SSB 1500 illustrated in FIG 15A is for illustrative purposes only. FIG 15A does not limit the scope of the present disclosure to any particular implementation.

[0107] FIG 15B is a diagram illustrating yet another exemplary S-SSB 1520 according to an embodiment of the present disclosure. The embodiment of the S-SSB 1520 illustrated in FIG 15B is for illustrative purposes only. FIG 15B does not limit the scope of the present disclosure to any particular implementation.

[0108] FIG 15C is a diagram illustrating yet another exemplary S-SSB 1540 according to an embodiment of the present disclosure. The embodiment of the S-SSB 1540 illustrated in FIG 15C is for illustrative purposes only. FIG 15C does not limit the scope of the present disclosure to any particular implementation.

[0109] FIG 16A is a diagram illustrating yet another exemplary S-SSB 1600 according to an embodiment of the present disclosure. The embodiment of the S-SSB 1600 illustrated in FIG 16A is for illustrative purposes only. FIG 16A does not limit the scope of the present disclosure to any particular implementation.

[0110] FIG 16B is a diagram illustrating yet another exemplary S-SSB 1620 according to an embodiment of the present disclosure. The embodiment of the S-SSB 1620 illustrated in FIG 16B is for illustrative purposes only. FIG 16B does not limit the scope of the present disclosure to any particular implementation.

[0111] 10A and 10B are diagrams showing an example of this embodiment in which one slot having 14 symbols includes two consecutive PSBCH blocks (SSBs) and two symbols of the slot (e.g., the first and last symbols in FIG. 10A or the seventh and last symbols in FIG. 10B) are reserved for other purposes such as automatic gain control (AGC) or transmission-to-reception (TX / RX) switch gaps. In one consideration, each PSBCH block includes two symbols for S-PSS, two symbols for S-SSS or multiplexing of S-SSS and PSBCH, and two symbols for PSBCH. In another consideration, each PSBCH block includes two symbols for S-PSS, one symbol for S-SSS or multiplexing of S-SSS and PSBCH, and three symbols for PSBCH. In yet another consideration, each PSBCH block includes one symbol for the S-PSS, two symbols for the S-SSS or multiplexing of the S-SSS and the PSBCH, and three symbols for the PSBCH. In yet another consideration, each PSBCH block includes one symbol for the S-PSS, one symbol for the S-SSS or multiplexing of the S-SSS and the PSBCH, and four symbols for the PSBCH.

[0112] As an example (e.g., 1001 in FIG. 10A), the first and last symbols in a slot are reserved for other purposes, symbols #1 to #6 are mapped for the first S-SSB in the slot, and symbols #7 to #12 are mapped for the second S-SSB in the slot, where the two S-SSBs have the same configuration with respect to time domain mapping: the first and second symbols of the S-SSB (i.e., symbols #1, #2, #7, and #8 in terms of symbol index in the slot) are mapped for the S-PSS, and the second S-SSB is mapped for the S-PSS. The 4th and 6th symbols of the SSB (i.e., symbols #4, #6, #10, and #12 in terms of symbol index within a slot) are mapped for S-SSS (if the BW of the S-SSB is 12 RB or 24 RB) or for multiplexing of S-SSS and PSBCH (if the BW of the S-SSB is greater than 12 RB, e.g., 20 RB), and the 3rd and 5th symbols of the S-SSB (i.e., symbols #3, #5, #9, and #11 in terms of symbol index within a slot) are mapped for PSBCH.

[0113] As another example (e.g., 1002 of FIG. 10A), the first and last symbols in a slot are reserved for other purposes, and symbols #1 to #6 are mapped for the first S-SSB in the slot, and symbols #7 to #12 are mapped for the second S-SSB in the slot, where the two S-SSBs have the same configuration with respect to time domain mapping: the first and second symbols of the S-SSB (i.e., symbols #1, #2, #7, and #8 in terms of symbol index in the slot) are mapped for the S-PSS, The fourth and fifth symbols of the S-SSB (i.e., symbols #4, #6, #10 and #11 in terms of symbol index within the slot) are mapped for S-SSS (if the BW of the S-SSB is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the BW of the S-SSB is greater than 12 RBs, e.g., 20 RBs), and the third and sixth symbols of the S-SSB (i.e., symbols #3, #6, #9 and #12 in terms of symbol index within the slot) are mapped for PSBCH.

[0114] As another example (e.g., 1003 of FIG. 10A), the first and last symbols in a slot are reserved for other purposes, and symbols #1 through #6 are mapped for the first S-SSB in the slot, and symbols #7 through #12 are mapped for the second S-SSB in the slot, where the two S-SSBs have the same configuration with respect to time domain mapping: the first symbol of the S-SSB (i.e., symbols #1 and #7 in terms of symbol index in the slot) is mapped for the S-PSS, and the third and The fifth symbol (i.e., symbols #3, #5, #9, and #11 in terms of symbol index within the slot) is mapped for S-SSS (if the BW of the S-SSB is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the BW of the S-SSB is greater than 12 RBs, e.g., 20 RBs), and the second, fourth, and sixth symbols of the S-SSB (i.e., symbols #2, #4, #6, #8, #10, and #12 in terms of symbol index within the slot) are mapped for PSBCH.

[0115] As another example (e.g., 1004 of FIG. 10A), the first and last symbols in a slot are reserved for other purposes, and symbols #1 through #6 are mapped for the first S-SSB in the slot, and symbols #7 through #12 are mapped for the second S-SSB in the slot, where the two S-SSBs have the same configuration with respect to time domain mapping: the second symbol of the S-SSB (i.e., symbols #2 and #8 in terms of symbol index in the slot) is mapped for the S-PSS, and the fourth and The first, second and fifth symbols (i.e., symbols #4, #5, #10 and #11 in terms of symbol index within a slot) are mapped for S-SSS (if the BW of the S-SSB is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the BW of the S-SSB is greater than 12 RBs, e.g., 20 RBs), and the first, third and sixth symbols of the S-SSB (i.e., symbols #1, #3, #6, #7, #9 and #12 in terms of symbol index within a slot) are mapped for PSBCH.

[0116] As another example (e.g., 1005 of FIG. 10A), the first and last symbols in a slot are reserved for other purposes, and symbols #1 through #6 are mapped for the first S-SSB in the slot, and symbols #7 through #12 are mapped for the second S-SSB in the slot, where the two S-SSBs have the same configuration with respect to time domain mapping: the second symbol of the S-SSB (i.e., symbols #2 and #8 in terms of symbol index in the slot) is mapped for the S-PSS, and the fourth and The first, second and sixth symbols (i.e., symbols #4, #6, #10 and #12 in terms of symbol index within a slot) are mapped for S-SSS (if the BW of the S-SSB is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the BW of the S-SSB is greater than 12 RBs, e.g., 20 RBs), and the first, third and fifth symbols of the S-SSB (i.e., symbols #1, #3, #5, #7, #9 and #11 in terms of symbol index within a slot) are mapped for PSBCH.

[0117] As another example (e.g., 1006 of FIG. 10A), the first and last symbols in a slot are reserved for other purposes, and symbols #1 through #6 are mapped for the first S-SSB in the slot, and symbols #7 through #12 are mapped for the second S-SSB in the slot, where the two S-SSBs have the same configuration with respect to time domain mapping: the first and second symbols of the S-SSB (i.e., symbols #1, #2, #7, and #8 in terms of symbol index in the slot) are mapped for the S-PSS. The fourth symbol of the S-SSB (i.e., symbols #4 and #10 in terms of symbol index within the slot) is mapped for S-SSS (if the BW of the S-SSB is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the BW of the S-SSB is greater than 12 RBs, e.g., 20 RBs), and the third, fifth and sixth symbols of the S-SSB (i.e., symbols #3, #5, #6, #9, #11 and #12 in terms of symbol index within the slot) are mapped for PSBCH.

[0118] As another example (e.g., 1007 in FIG. 10A), the first and last symbols in a slot are reserved for other purposes, and symbols #1 through #6 are mapped for the first S-SSB in the slot, and symbols #7 through #12 are mapped for the second S-SSB in the slot, where the two S-SSBs have the same configuration with respect to time domain mapping: the second symbol of the S-SSB (i.e., symbols #2 and #8 in terms of symbol index in the slot) is mapped for the S-PSS, and the fourth symbol of the S-SSB is mapped for the S-PSS. The first, third, fifth and sixth symbols of the S-SSB (i.e., symbols #4 and #10 in terms of symbol index within the slot) are mapped for S-SSS (if the BW of the S-SSB is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the BW of the S-SSB is greater than 12 RBs, e.g., 20 RBs), and the first, third, fifth and sixth symbols of the S-SSB (i.e., symbols #1, #3, #5, #6, #7, #9, #11 and #12 in terms of symbol index within the slot) are mapped for PSBCH.

[0119] As another example (e.g., 1011 in FIG. 10B), the seventh and last symbols in a slot are reserved for other purposes, and symbols #0 to #5 are mapped for the first S-SSB in the slot, and symbols #7 to #12 are mapped for the second S-SSB in the slot, where the two S-SSBs have the same configuration with respect to time domain mapping: the first and second symbols of the S-SSB (i.e., symbols #1, #2, #7, and #8 in terms of symbol index in the slot) are mapped for the S-PSS. The fourth and sixth symbols of the S-SSB (i.e., symbols #3, #5, #10, and #12 in terms of symbol index within a slot) are mapped for S-SSS (if the BW of the S-SSB is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the BW of the S-SSB is greater than 12 RBs, e.g., 20 RBs), and the third and fifth symbols of the S-SSB (i.e., symbols #2, #4, #9, and #11 in terms of symbol index within a slot) are mapped for PSBCH.

[0120] As another example (e.g., 1012 in FIG. 10B), the seventh and last symbols in a slot are reserved for other purposes, and symbols #0 to #5 are mapped for the first S-SSB in the slot, and symbols #7 to #12 are mapped for the second S-SSB in the slot, where the two S-SSBs have the same configuration with respect to time domain mapping: the first and second symbols of the S-SSB (i.e., symbols #0, #1, #7, and #8 in terms of symbol index in the slot) are mapped for the S-PSS. The fourth and fifth symbols of the S-SSB (i.e., symbols #3, #4, #10 and #11 in terms of symbol index within the slot) are mapped for S-SSS (if the BW of the S-SSB is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the BW of the S-SSB is greater than 12 RBs, e.g., 20 RBs), and the third and sixth symbols of the S-SSB (i.e., symbols #2, #5, #9 and #12 in terms of symbol index within the slot) are mapped for PSBCH.

[0121] As another example (e.g., 1013 in FIG. 10B), the seventh and last symbols in a slot are reserved for other purposes, and symbols #0 to #5 are mapped for the first S-SSB in the slot, and symbols #7 to #12 are mapped for the second S-SSB in the slot, where the two S-SSBs have the same configuration with respect to time domain mapping: the second and third symbols of the S-SSB (i.e., symbols #1, #2, #8, and #9 in terms of symbol index in the slot) are mapped for the S-PSS, The fifth symbol of the S-SSB (i.e., symbols #4 and #11 in terms of symbol index within the slot) is mapped for S-SSS (if the BW of the S-SSB is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the BW of the S-SSB is greater than 12 RBs, e.g., 20 RBs), and the first, fourth and sixth symbols of the S-SSB (i.e., symbols #0, #3, #5, #7, #10 and #12 in terms of symbol index within the slot) are mapped for PSBCH.

[0122] As another example (e.g., 1014 in FIG. 10B), the seventh and last symbol in a slot is reserved for other purposes, and symbols #0 to #5 are mapped for the first S-SSB in the slot, and symbols #7 to #12 are mapped for the second S-SSB in the slot, where the two S-SSBs have the same configuration with respect to time domain mapping: the second symbol of the S-SSB (i.e., symbols #1 and #8 in terms of symbol index in the slot) is mapped for the S-PSS, and the fourth and The first, second and fifth symbols (i.e., symbols #3, #4, #10 and #11 in terms of symbol index within a slot) are mapped for S-SSS (if the BW of the S-SSB is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the BW of the S-SSB is greater than 12 RBs, e.g., 20 RBs), and the first, third and sixth symbols of the S-SSB (i.e., symbols #0, #2, #5, #7, #9 and #12 in terms of symbol index within a slot) are mapped for PSBCH.

[0123] As another example (e.g., 1015 of FIG. 10B), the seventh and last symbol in a slot is reserved for other purposes, and symbols #0 to #5 are mapped for the first S-SSB in the slot, and symbols #7 to #12 are mapped for the second S-SSB in the slot, where the two S-SSBs have the same configuration with respect to time domain mapping: the second symbol of the S-SSB (i.e., symbols #1 and #8 in terms of symbol index in the slot) is mapped for the S-PSS, and the third and fourth symbols of the S-SSB are mapped for the S-PSS. The first, second and fifth symbols (i.e., symbols #2, #4, #9 and #11 in terms of symbol index within a slot) are mapped for S-SSS (if the BW of the S-SSB is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the BW of the S-SSB is greater than 12 RBs, e.g., 20 RBs), and the first, fourth and sixth symbols of the S-SSB (i.e., symbols #0, #3, #5, #7, #10 and #12 in terms of symbol index within a slot) are mapped for PSBCH.

[0124] As another example (e.g., 1016 of FIG. 10B), the seventh and last symbol in a slot is reserved for other purposes, and symbols #0 to #5 are mapped for the first S-SSB in the slot, and symbols #7 to #12 are mapped for the second S-SSB in the slot, where the two S-SSBs have the same configuration with respect to time domain mapping: the second symbol of the S-SSB (i.e., symbols #1 and #8 in terms of symbol index in the slot) is mapped for the S-PSS, and the fourth symbol of the S-SSB is mapped for the S-PSS. The first, third, fourth and sixth symbols of the S-SSB (i.e., symbols #3 and #10 in terms of symbol index within the slot) are mapped for S-SSS (if the BW of the S-SSB is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the BW of the S-SSB is greater than 12 RBs, e.g., 20 RBs), and the first, third, fourth and sixth symbols of the S-SSB (i.e., symbols #0, #2, #4, #5, #7, #9, #11 and #12 in terms of symbol index within the slot) are mapped for PSBCH.

[0125] As another example (e.g., 1017 in FIG. 10B), the seventh and last symbol in a slot is reserved for other purposes, and symbols #0 to #5 are mapped for the first S-SSB in the slot, and symbols #7 to #12 are mapped for the second S-SSB in the slot, where the two S-SSBs have the same configuration with respect to time domain mapping: the second symbol of the S-SSB (i.e., symbols #1 and #8 in terms of symbol index in the slot) is mapped for the S-PSS, and the fifth symbol of the S-SSB is mapped for the S-PSS. The first, third, fourth and sixth symbols of the S-SSB (i.e., symbols #4 and #11 in terms of symbol index within the slot) are mapped for S-SSS (if the BW of the S-SSB is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the BW of the S-SSB is greater than 12 RBs, e.g., 20 RBs), and the first, third, fourth and sixth symbols of the S-SSB (i.e., symbols #0, #2, #3, #5, #7, #9, #10 and #12 in terms of symbol index within the slot) are mapped for PSBCH.

[0126] 11 is a diagram showing an example of this embodiment in which a slot having 14 symbols includes two consecutive PSBCH blocks (SSB), each PSBCH block includes 7 symbols, and no symbols in the slot are reserved for other purposes. In one consideration, each PSBCH block includes 2 symbols for S-PSS, 2 symbols for S-SSS or multiplexing of S-SSS and PSBCH, and 3 symbols for PSBCH.

[0127] As another example (e.g., 1101 of FIG. 11), symbols #0 to #6 may be mapped for the first S-SSB in a slot, and symbols #7 to #13 may be mapped for the second S-SSB in the slot, where the two S-SSBs have the same configuration with respect to time domain mapping: the first and second symbols of the S-SSB (i.e., symbols #0, #1, #7, and #8 in terms of symbol index in the slot) are mapped for the S-PSS, and the fourth and sixth symbols of the S-SSB (i.e., symbols #1, #2, #3, #4, and #5) are mapped for the S-PSS. That is, symbols #3, #5, #10, and #12 in terms of symbol index within a slot) are mapped for S-SSS (if the BW of the S-SSB is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the BW of the S-SSB is greater than 12 RBs, e.g., 20 RBs), and the 3rd, 5th, and 7th symbols of the S-SSB (i.e., symbols #2, #4, #6, #9, #11, and #13 in terms of symbol index within a slot) are mapped for PSBCH.

[0128] As another example (e.g., 1102 of FIG. 11), symbols #0 to #6 may be mapped for the first S-SSB in a slot, and symbols #7 to #13 may be mapped for the second S-SSB in the slot, where the two S-SSBs have the same configuration with respect to time domain mapping: the first and second symbols of the S-SSB (i.e., symbols #0, #1, #7, and #8 in terms of symbol index in the slot) are mapped for the S-PSS, and the sixth and seventh symbols of the S-SSB (i.e., symbols #1, #2, #3, #4, and #5) are mapped for the S-PSS. That is, symbols #5, #6, #12, and #13 in terms of symbol index within the slot) are mapped for S-SSS (if the BW of the S-SSB is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the BW of the S-SSB is greater than 12 RBs, e.g., 20 RBs), and the third, fourth, and fifth symbols of the S-SSB (i.e., symbols #2, #3, #4, #9, #10, and #11 in terms of symbol index within the slot) are mapped for PSBCH.

[0129] As another example (e.g., 1103 of FIG. 11), symbols #0 to #6 may be mapped for the first S-SSB in a slot, and symbols #7 to #13 may be mapped for the second S-SSB in the slot, where the two S-SSBs have the same configuration with respect to time domain mapping: the second and third symbols of the S-SSB (i.e., symbols #1, #2, #8, and #9 in terms of symbol index in the slot) are mapped for the S-PSS, and the fifth and sixth symbols of the S-SSB (i.e., symbols #1, #2, #8, and #9 in terms of symbol index in the slot) are mapped for the S-PSS. That is, symbols #4, #5, #11, and #12 in terms of symbol index within a slot) are mapped for S-SSS (if the BW of the S-SSB is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the BW of the S-SSB is greater than 12 RBs, e.g., 20 RBs), and the 1st, 4th, and 7th symbols of the S-SSB (i.e., symbols #0, #3, #6, #7, #10, and #13 in terms of symbol index within a slot) are mapped for PSBCH.

[0130] As another example (e.g., 1104 of FIG. 11), symbols #0 through #6 may be mapped for the first S-SSB in a slot, and symbols #7 through #13 may be mapped for the second S-SSB in the slot, where the two S-SSBs have the same configuration with respect to time domain mapping: the second and third symbols of the S-SSB (i.e., symbols #1, #2, #8, and #9 in terms of symbol index in the slot) are mapped for the S-PSS, and the fifth and seventh symbols of the S-SSB (i.e., symbols #1, #2, #8, and #9 in terms of symbol index in the slot) are mapped for the S-PSS. That is, symbols #4, #6, #11, and #13 in terms of symbol index within a slot) are mapped for S-SSS (if the BW of the S-SSB is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the BW of the S-SSB is greater than 12 RBs, e.g., 20 RBs), and the 1st, 4th, and 6th symbols of the S-SSB (i.e., symbols #0, #3, #5, #7, #10, and #12 in terms of symbol index within a slot) are mapped for PSBCH.

[0131] As another example (e.g., 1105 of FIG. 11), symbols #0 to #6 may be mapped for a first S-SSB in a slot, and symbols #7 to #13 may be mapped for a second S-SSB in the slot, where the two S-SSBs have the same configuration with respect to time domain mapping: the second and third symbols of the S-SSB (i.e., symbols #1, #2, #8, and #9 in terms of symbol index in the slot) are mapped for an S-PSS, and the fourth and sixth symbols of the S-SSB (i.e., symbols #1, #2, #8, and #9 in terms of symbol index in the slot) are mapped for an S-PSS. That is, symbols #3, #5, #10, and #12 in terms of symbol index within a slot) are mapped for S-SSS (if the BW of the S-SSB is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the BW of the S-SSB is greater than 12 RBs, e.g., 20 RBs), and the 1st, 3rd, and 5th symbols of the S-SSB (i.e., symbols #0, #4, #6, #7, #11, and #13 in terms of symbol index within a slot) are mapped for PSBCH.

[0132] 12A, 12B, and 12C are diagrams showing an example of this embodiment in which a slot with 14 symbols includes one PSBCH block (SSB), the PSBCH block includes 12 symbols, and the first and last symbols of the slot are reserved for other purposes such as automatic gain control (AGC) or transmit-receive (TX / RX) switch gap. In one consideration, each PSBCH block includes 3 symbols for S-PSS, 3 symbols for S-SSS or multiplexing of S-SSS and PSBCH, and 6 symbols for PSBCH. In another consideration, each PSBCH block includes 2 symbols for S-PSS, 2 symbols for S-SSS or multiplexing of S-SSS and PSBCH, and 8 symbols for PSBCH. In yet another consideration, each PSBCH block includes 4 symbols for S-PSS, 4 symbols for multiplexing of S-SSS or multiplexing of S-SSS and PSBCH, and 4 symbols for PSBCH.

[0133] As an example (e.g., 1201 in FIG. 12A), symbols #1 to #12 are mapped for S-SSB in a slot, where: the first, second and third symbols of S-SSB (i.e., symbols #1, #2 and #3 in terms of symbol index in the slot) are mapped for S-PSS, the sixth, ninth and twelfth symbols of S-SSB (i.e., symbols #6, #9 and #12 in terms of symbol index in the slot) are mapped for S-SSS (if the BW of S-SSB is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the BW of S-SSB is greater than 12 RBs, e.g., 20 RBs), and the fourth, fifth, seventh, eighth, tenth and eleventh symbols of S-SSB (i.e., symbols #4, #5, #7, #8, #10 and #11 in terms of symbol index in the slot) are mapped for PSBCH.

[0134] As another example (e.g., 1202 of FIG. 12A), symbols #1 to #12 are mapped for S-SSB in a slot, where: the first, second and third symbols of the S-SSB (i.e., symbols #1, #2 and #3 in terms of symbol index in the slot) are mapped for S-PSS, the tenth, eleventh and twelfth symbols of the S-SSB (i.e., symbols #10, #11 and #12 in terms of symbol index in the slot) are mapped for S-SSS (if the BW of the S-SSB is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the BW of the S-SSB is greater than 12 RBs, e.g., 20 RBs), and the fourth, fifth, sixth, seventh, eighth and ninth symbols of the S-SSB (i.e., symbols #4, #5, #6, #7, #8 and #9 in terms of symbol index in the slot) are mapped for PSBCH.

[0135] As another example (e.g., 1203 in FIG. 12A), symbols #1 to #12 are mapped for S-SSB in a slot, where: the first, second and third symbols of the S-SSB (i.e., symbols #1, #2 and #3 in terms of symbol index in the slot) are mapped for S-PSS, the fifth, eighth and eleventh symbols of the S-SSB (i.e., symbols #5, #8 and #11 in terms of symbol index in the slot) are mapped for S-SSS (if the BW of the S-SSB is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the BW of the S-SSB is greater than 12 RBs, e.g., 20 RBs), and the fourth, sixth, seventh, ninth, tenth and twelfth symbols of the S-SSB (i.e., symbols #4, #6, #7, #9, #10 and #12 in terms of symbol index in the slot) are mapped for PSBCH.

[0136] As another example (e.g., 1211 in FIG. 12B), symbols #1 to #12 are mapped for S-SSB in a slot, where: the first and second symbols of the S-SSB (i.e., symbols #1 and #2 in terms of symbol index in the slot) are mapped for S-PSS, the sixth and ninth symbols of the S-SSB (i.e., symbols #6 and #9 in terms of symbol index in the slot) are mapped for S-SSS (if the BW of the S-SSB is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the BW of the S-SSB is greater than 12 RBs, e.g., 20 RBs), and the third, fourth, fifth, seventh, eighth, tenth, eleventh, and twelfth symbols of the S-SSB (i.e., symbols #3, #4, #5, #7, #8, #10, #11, and #12 in terms of symbol index in the slot) are mapped for PSBCH.

[0137] As another example (e.g., 1212 of FIG. 12B), symbols #1 to #12 are mapped for S-SSB in a slot, where: the first and second symbols of the S-SSB (i.e., symbols #1 and #2 in terms of symbol index in the slot) are mapped for S-PSS, the fifth and tenth symbols of the S-SSB (i.e., symbols #5 and #10 in terms of symbol index in the slot) are mapped for S-SSS (if the BW of the S-SSB is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the BW of the S-SSB is greater than 12 RBs, e.g., 20 RBs), and the third, fourth, sixth, seventh, eighth, ninth, eleventh, and twelfth symbols of the S-SSB (i.e., symbols #3, #4, #6, #7, #8, #9, #11, and #12 in terms of symbol index in the slot) are mapped for PSBCH.

[0138] As another example (e.g., 1213 of FIG. 12B), symbols #1 to #12 are mapped for S-SSB in the slot, where: the first and second symbols of the S-SSB (i.e., symbols #1 and #2 in terms of symbol index in the slot) are mapped for S-PSS, the seventh and eighth symbols of the S-SSB (i.e., symbols #7 and #8 in terms of symbol index in the slot) are mapped for S-SSS (if the BW of the S-SSB is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the BW of the S-SSB is greater than 12 RBs, e.g., 20 RBs), and the third, fourth, fifth, sixth, ninth, tenth, eleventh, and twelfth symbols of the S-SSB (i.e., symbols #3, #4, #6, #7, #8, #9, #11, and #12 in terms of symbol index in the slot) are mapped for PSBCH.

[0139] As another example (e.g., 1221 of FIG. 12C), symbols #1 to #12 are mapped for S-SSB in a slot, where: the first, second, third and fourth symbols of the S-SSB (i.e., symbols #1, #2, #3 and #4 in terms of symbol index in the slot) are mapped for S-PSS, the sixth, seventh, tenth and eleventh symbols of the S-SSB (i.e., symbols #6, #7, #10 and #11 in terms of symbol index in the slot) are mapped for S-SSS (if the BW of the S-SSB is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the BW of the S-SSB is greater than 12 RBs, e.g., 20 RBs), and the fifth, eighth, ninth and twelfth symbols of the S-SSB (i.e., symbols #5, #8, #9 and #12 in terms of symbol index in the slot) are mapped for PSBCH.

[0140] As another example (e.g., 1222 of FIG. 12C), symbols #1 to #12 are mapped for S-SSB in a slot, where: the first, second, third and fourth symbols of the S-SSB (i.e., symbols #1, #2, #3 and #4 in terms of symbol index in the slot) are mapped for S-PSS, the seventh, eighth, ninth and tenth symbols of the S-SSB (i.e., symbols #7, #8, #9 and #10 in terms of symbol index in the slot) are mapped for S-SSS (if the BW of the S-SSB is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the BW of the S-SSB is greater than 12 RBs, e.g., 20 RBs), and the fifth, sixth, eleventh and twelfth symbols of the S-SSB (i.e., symbols #5, #6, #11 and #12 in terms of symbol index in the slot) are mapped for PSBCH.

[0141] As another example (e.g., 1223 of FIG. 12C), symbols #1 to #12 are mapped for S-SSB in a slot, where: the first, second, third and fourth symbols of the S-SSB (i.e., symbols #1, #2, #3 and #4 in terms of symbol index in the slot) are mapped for S-PSS, the fifth, seventh, ninth and eleventh symbols of the S-SSB (i.e., symbols #5, #7, #9 and #11 in terms of symbol index in the slot) are mapped for S-SSS (if the BW of the S-SSB is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the BW of the S-SSB is greater than 12 RBs, e.g., 20 RBs), and the sixth, eighth, tenth and twelfth symbols of the S-SSB (i.e., symbols #6, #8, #10 and #12 in terms of symbol index in the slot) are mapped for PSBCH.

[0142] As another example (e.g., 1224 of FIG. 12C), symbols #1 to #12 are mapped for S-SSB in a slot, where: the first, second, third and fourth symbols of the S-SSB (i.e., symbols #1, #2, #3 and #4 in terms of symbol index in the slot) are mapped for S-PSS, the sixth, eighth, tenth and twelfth symbols of the S-SSB (i.e., symbols #6, #8, #10 and #12 in terms of symbol index in the slot) are mapped for S-SSS (if the BW of the S-SSB is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the BW of the S-SSB is greater than 12 RBs, e.g., 20 RBs), and the fifth, seventh, ninth and eleventh symbols of the S-SSB (i.e., symbols #5, #7, #9 and #11 in terms of symbol index in the slot) are mapped for PSBCH.

[0143] 13A and 13B are diagrams showing an example of this embodiment in which a slot with 14 symbols includes one PSBCH block (SSB), the PSBCH block includes 13 symbols, and the first symbol of the slot is reserved for other purposes such as automatic gain control (AGC) or transmit-receive (TX / RX) switch gap. In one consideration, each PSBCH block includes 3 symbols for S-PSS, 3 symbols for S-SSS or multiplexing S-SSS and PSBCH, and 7 symbols for PSBCH. In another consideration, each PSBCH block includes 2 symbols for S-PSS, 2 symbols for S-SSS or multiplexing S-SSS and PSBCH, and 9 symbols for PSBCH. In yet another consideration, each PSBCH block includes 4 symbols for S-PSS, 4 symbols for S-SSS or multiplexing S-SSS and PSBCH, and 5 symbols for PSBCH.

[0144] As an example (e.g., 1301 in FIG. 13A), symbols #1 through #13 are mapped for S-SSB in a slot, where: the first, second, and third symbols of the S-SSB (i.e., symbols #1, #2, and #3 in terms of symbol index in the slot) are mapped for S-PSS, and the sixth, ninth, and twelfth symbols of the S-SSB (i.e., symbols #6, #9, and #12 in terms of symbol index in the slot) are mapped for S-PSS. The 4th, 5th, 7th, 8th, 9th, 11th, and 13th symbols of the S-SSB (i.e., symbols #4, #5, #7, #8, #10, #11, and #13 in terms of symbol index within the slot) are mapped for S (if the S-SSB BW is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the S-SSB BW is greater than 12 RBs, e.g., 20 RBs) and the 4th, 5th, 7th, 8th, 9th, 11th, and 13th symbols of the S-SSB (i.e., symbols #4, #5, #7, #8, #10, #11, and #13 in terms of symbol index within the slot) are mapped for the PSBCH.

[0145] As another example (e.g., 1302 of FIG. 13A), symbols #1 through #13 may be mapped for an S-SSB in a slot, where: the first, second, and third symbols of the S-SSB (i.e., symbols #1, #2, and #3 in terms of symbol index within the slot) are mapped for an S-PSS, and the eleventh, twelfth, and thirteenth symbols of the S-SSB (i.e., symbols #11, #12, and #13 in terms of symbol index within the slot) are mapped for an S-PSS. The 4th, 5th, 6th, 7th, 8th, 9th, and 10th symbols of the S-SSB (i.e., symbols #4, #5, #6, #7, #8, #9, and #10 in terms of symbol index within the slot) are mapped for S-SSS (if the S-SSB BW is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the S-SSB BW is greater than 12 RBs, e.g., 20 RBs) and the 4th, 5th, 6th, 7th, 8th, 9th, and 10th symbols of the S-SSB (i.e., symbols #4, #5, #6, #7, #8, #9, and #10 in terms of symbol index within the slot) are mapped for PSBCH.

[0146] As yet another example (e.g., 1303 of FIG. 13A), symbols #1 through #13 may be mapped for an S-SSB in a slot, where: the first, second, and third symbols of the S-SSB (i.e., symbols #1, #2, and #3 in terms of symbol index within the slot) are mapped for an S-PSS, and the fifth, eighth, and eleventh symbols of the S-SSB (i.e., symbols #5, #8, and #11 in terms of symbol index within the slot) are mapped for an S-PSS. The 4th, 6th, 7th, 9th, 10th, 12th and 13th symbols of the S-SSB (i.e., symbols #4, #6, #7, #9, #10, #12 and #13 in terms of symbol index within the slot) are mapped for SSS (if the S-SSB BW is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the S-SSB BW is greater than 12 RBs, e.g., 20 RBs) and the 4th, 6th, 7th, 9th, 10th, 12th and 13th symbols of the S-SSB (i.e., symbols #4, #6, #7, #9, #10, #12 and #13 in terms of symbol index within the slot) are mapped for PSBCH.

[0147] As yet another example (e.g., 1304 of FIG. 13A), symbols #1 through #13 may be mapped for an S-SSB in a slot, where: the first, second, and third symbols of the S-SSB (i.e., symbols #1, #2, and #3 in terms of symbol index within the slot) are mapped for an S-PSS, and the seventh, eighth, and ninth symbols of the S-SSB (i.e., symbols #7, #8, and #9 in terms of symbol index within the slot) are mapped for an S-PSS. The 4th, 5th, 6th, 10th, 11th, 12th and 13th symbols of the S-SSB (i.e., symbols #4, #5, #6, #10, #11, #12 and #13 in terms of symbol index within the slot) are mapped for S (if the BW of the S-SSB is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the BW of the S-SSB is greater than 12 RBs, e.g., 20 RBs) and the 4th, 5th, 6th, 10th, 11th, 12th and 13th symbols of the S-SSB (i.e., symbols #4, #5, #6, #10, #11, #12 and #13 in terms of symbol index within the slot) are mapped for the PSBCH.

[0148] As yet another example (e.g., 1305 of FIG. 13A ), symbols #1 through #13 may be mapped for an S-SSB in a slot, where: the first, second, and third symbols of the S-SSB (i.e., symbols #1, #2, and #3 in terms of symbol index within the slot) are mapped for an S-PSS, and the eighth, ninth, and tenth symbols of the S-SSB (i.e., symbols #8, #9, and #10 in terms of symbol index within the slot) are mapped for an S-PSS. The 4th, 5th, 6th, 7th, 11th, 12th and 13th symbols of the S-SSB (i.e., symbols #4, #5, #6, #7, #11, #12 and #13 in terms of symbol index within the slot) are mapped for SSS (if the S-SSB BW is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the S-SSB BW is greater than 12 RBs, e.g., 20 RBs) and the 4th, 5th, 6th, 7th, 11th, 12th and 13th symbols of the S-SSB (i.e., symbols #4, #5, #6, #7, #11, #12 and #13 in terms of symbol index within the slot) are mapped for PSBCH.

[0149] As yet another example (e.g., 1311 of FIG. 13B), symbols #1 through #13 may be mapped for S-SSB in a slot, where: the first, second, third, and fourth symbols of the S-SSB (i.e., symbols #1, #2, #3, and #4 in terms of symbol index in the slot) are mapped for S-PSS, and the sixth, eighth, tenth, and twelfth symbols of the S-SSB (i.e., symbols #6, #8, and #9 in terms of symbol index in the slot) are mapped for S-PSS. , #10, and #12) are mapped for S-SSS (if the S-SSB BW is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the S-SSB BW is greater than 12 RBs, e.g., 20 RBs), and the 5th, 7th, 9th, 11th, and 13th symbols of the S-SSB (i.e., symbols #5, #7, #9, #11, and #13 in terms of symbol index within the slot) are mapped for PSBCH.

[0150] As yet another example (e.g., 1312 of FIG. 13B), symbols #1 through #13 may be mapped for an S-SSB in a slot, where: the first, second, third, and fourth symbols of the S-SSB (i.e., symbols #1, #2, #3, and #4 in terms of symbol index within the slot) are mapped for an S-PSS, and the tenth, eleventh, twelfth, and thirteenth symbols of the S-SSB (i.e., symbols #10, #11, #12, and #13 in terms of symbol index within the slot) are mapped for an S-PSS. #11, #12, and #13) are mapped for S-SSS (if the S-SSB BW is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the S-SSB BW is greater than 12 RBs, e.g., 20 RBs), and the 5th, 6th, 7th, 8th, and 9th symbols of the S-SSB (i.e., symbols #5, #6, #7, #8, and #9 in terms of symbol index within the slot) are mapped for PSBCH.

[0151] As yet another example (e.g., 1313 of FIG. 13B), symbols #1 through #13 may be mapped for an S-SSB in a slot, where: the first, second, third, and fourth symbols of the S-SSB (i.e., symbols #1, #2, #3, and #4 in terms of symbol index within the slot) are mapped for an S-PSS, and the eighth, ninth, tenth, and eleventh symbols of the S-SSB (i.e., symbols #8, #9, #10, and #11) are mapped for S-SSS (if the S-SSB BW is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the S-SSB BW is greater than 12 RBs, e.g., 20 RBs), and the 5th, 6th, 7th, 12th, and 13th symbols of the S-SSB (i.e., symbols #5, #6, #7, #12, and #13 in terms of symbol index within the slot) are mapped for PSBCH.

[0152] As yet another example (e.g., 1314 of FIG. 13B), symbols #1 through #13 may be mapped for an S-SSB in a slot, where: the first, second, third, and fourth symbols of the S-SSB (i.e., symbols #1, #2, #3, and #4 in terms of symbol index within the slot) are mapped for an S-PSS, and the seventh, eighth, ninth, and tenth symbols of the S-SSB (i.e., symbols #7, #8, #9 in terms of symbol index within the slot) are mapped for an S-PSS. Symbols #9, and #10) are mapped for S-SSS (if the S-SSB BW is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the S-SSB BW is greater than 12 RBs, e.g., 20 RBs), and the 5th, 6th, 11th, 12th, and 13th symbols of the S-SSB (i.e., symbols #5, #6, #11, #12, and #13 in terms of symbol index within the slot) are mapped for PSBCH.

[0153] As yet another example (e.g., 1315 of FIG. 13B), symbols #1 through #13 may be mapped for an S-SSB in a slot, where: the first, second, third, and fourth symbols of the S-SSB (i.e., symbols #1, #2, #3, and #4 in terms of symbol index within the slot) are mapped for an S-PSS, and the seventh, eighth, tenth, and eleventh symbols of the S-SSB (i.e., symbols #7, #8, #10, and #11) are mapped for S-SSS (if the S-SSB BW is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the S-SSB BW is greater than 12 RBs, e.g., 20 RBs), and the 5th, 6th, 9th, 12th, and 13th symbols of the S-SSB (i.e., symbols #5, #6, #9, #12, and #13 in terms of symbol index within the slot) are mapped for PSBCH.

[0154] As yet another example (e.g., 1316 of FIG. 13B), symbols #1 through #13 may be mapped for an S-SSB in a slot, where: the first, second, third, and fourth symbols of the S-SSB (i.e., symbols #1, #2, #3, and #4 in terms of symbol index within the slot) are mapped for an S-PSS, and the sixth, seventh, eleventh, and twelfth symbols of the S-SSB (i.e., symbols #6, #7, #8, #9, #10, #11, #12, #13, #14, #15, #16, #17, #18, #19, #20, #21, #22, #23, #24, #25, #26, #27, #28, #29, #30, #31, #32, #33, #34, #35, #36, #37, #38, #39, #40, #41, #42, #43, #44, #45, #46, #47, #48, #49, #50, #51, #52, #53, #54, #55, #56, #57, #58, #59, #60, #61, #62, #63, #64, #65, #66, #67, #68, #79, #71, #72, #73, #74, #75, #76, #77, #78, #79, #89, #90, #91, #92, #93, #94, #95, #96, #97, #98, #99, #100, #101, #102, #103, #104, #105, #106, #107, #108, #109 Symbols #11, and #12) are mapped for S-SSS (if the S-SSB BW is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the S-SSB BW is greater than 12 RBs, e.g., 20 RBs), and the 5th, 8th, 9th, 10th, and 13th symbols of the S-SSB (i.e., symbols #5, #8, #9, #10, and #13 in terms of symbol index within the slot) are mapped for PSBCH.

[0155] 14A, 14B, 14C, and 14D are diagrams showing an example of this embodiment in which a slot having 14 symbols includes one PSBCH block (SSB), the PSBCH block includes 13 symbols, and the last symbol of the slot is reserved for other purposes such as a transmit-receive (TX / RX) switch gap. In one consideration, each PSBCH block includes 3 symbols for S-PSS, 3 symbols for multiplexing S-SSS or S-SSS and PSBCH, and 7 symbols for PSBCH. In another consideration, each PSBCH block includes 2 symbols for S-PSS, 2 symbols for multiplexing S-SSS or S-SSS and PSBCH, and 9 symbols for PSBCH. In yet another consideration, each PSBCH block includes 4 symbols for S-PSS, 4 symbols for multiplexing S-SSS or S-SSS and PSBCH, and 5 symbols for PSBCH.

[0156] As an example (e.g., 1401 in FIG. 14A), symbols #0 through #12 are mapped for S-SSB in a slot, where: the first, second, and third symbols of the S-SSB (i.e., symbols #0, #1, and #2 in terms of symbol index in the slot) are mapped for S-PSS, and the sixth, ninth, and twelfth symbols of the S-SSB (i.e., symbols #5, #8, and #11 in terms of symbol index in the slot) are mapped for S-PSS. The 4th, 5th, 7th, 8th, 9th, 11th and 13th symbols of the S-SSB (i.e., symbols #3, #4, #6, #7, #9, #10 and #12 in terms of symbol index within the slot) are mapped for the SS (if the S-SSB BW is 12 RBs or 24 RBs) or for multiplexing of the S-SSS and PSBCH (if the S-SSB BW is greater than 12 RBs, e.g., 20 RBs) and the 4th, 5th, 7th, 8th, 9th, 11th and 13th symbols of the S-SSB (i.e., symbols #3, #4, #6, #7, #9, #10 and #12 in terms of symbol index within the slot) are mapped for the PSBCH.

[0157] As another example (e.g., 1402 of FIG. 14A), symbols #0 through #12 may be mapped for the S-SSB in a slot, where: the first, second, and third symbols of the S-SSB (i.e., symbols #0, #1, and #2 in terms of symbol index within the slot) are mapped for the S-PSS, and the eleventh, twelfth, and thirteenth symbols of the S-SSB (i.e., symbols #10, #11, and #12 in terms of symbol index within the slot) are mapped for the S-PSS. are mapped for S-SSS (if the S-SSB BW is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the S-SSB BW is greater than 12 RBs, e.g., 20 RBs), and the 4th, 5th, 6th, 7th, 8th, 9th and 10th symbols of the S-SSB (i.e., symbols #3, #4, #5, #6, #7, #8, and #9 in terms of symbol index within the slot) are mapped for PSBCH.

[0158] As yet another example (e.g., 1403 of FIG. 14A), symbols #0 through #12 may be mapped for an S-SSB in a slot, where: the first, second, and third symbols of the S-SSB (i.e., symbols #0, #1, and #2 in terms of symbol index within the slot) are mapped for an S-PSS, and the fifth, eighth, and eleventh symbols of the S-SSB (i.e., symbols #4, #7, and #10 in terms of symbol index within the slot) are mapped for an S-PSS. The 4th, 6th, 7th, 9th, 10th, 12th and 13th symbols of the S-SSB (i.e., symbols #3, #5, #6, #8, #9, #11 and #12 in terms of symbol index within the slot) are mapped for SSS (if the S-SSB BW is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the S-SSB BW is greater than 12 RBs, e.g., 20 RBs) and the 4th, 6th, 7th, 9th, 10th, 12th and 13th symbols of the S-SSB (i.e., symbols #3, #5, #6, #8, #9, #11 and #12 in terms of symbol index within the slot) are mapped for PSBCH.

[0159] As yet another example (e.g., 1404 of FIG. 14A), symbols #0 through #12 may be mapped for an S-SSB in a slot, where: the first, second, and third symbols of the S-SSB (i.e., symbols #0, #1, and #2 in terms of symbol index within the slot) are mapped for an S-PSS, and the seventh, eighth, and ninth symbols of the S-SSB (i.e., symbols #6, #7, and #8 in terms of symbol index within the slot) are mapped for an S-PSS. The 4th, 5th, 6th, 10th, 11th, 12th and 13th symbols of the S-SSB (i.e., symbols #3, #4, #5, #9, #10, #11 and #12 in terms of symbol index within the slot) are mapped for S (if the BW of the S-SSB is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the BW of the S-SSB is greater than 12 RBs, e.g., 20 RBs) and the 4th, 5th, 6th, 10th, 11th, 12th and 13th symbols of the S-SSB (i.e., symbols #3, #4, #5, #9, #10, #11 and #12 in terms of symbol index within the slot) are mapped for the PSBCH.

[0160] As yet another example (e.g., 1405 of FIG. 14A), symbols #0 through #12 may be mapped for an S-SSB in a slot, where: the first, second, and third symbols of the S-SSB (i.e., symbols #0, #1, and #2 in terms of symbol index within the slot) are mapped for an S-PSS, and the eighth, ninth, and tenth symbols of the S-SSB (i.e., symbols #7, #8, and #9 in terms of symbol index within the slot) are mapped for an S-PSS. The 4th, 5th, 6th, 7th, 11th, 12th and 13th symbols of the S-SSB (i.e., symbols #3, #4, #5, #6, #10, #11 and #12 in terms of symbol index within the slot) are mapped for the SS (if the BW of the S-SSB is 12 RBs or 24 RBs) or for multiplexing of the S-SSS and PSBCH (if the BW of the S-SSB is greater than 12 RBs, e.g., 20 RBs) and the 4th, 5th, 6th, 7th, 11th, 12th and 13th symbols of the S-SSB (i.e., symbols #3, #4, #5, #6, #10, #11 and #12 in terms of symbol index within the slot) are mapped for the PSBCH.

[0161] As yet another example (e.g., 1411 of FIG. 14B), symbols #0 through #12 may be mapped for S-SSB in a slot, where: the first, second, third, and fourth symbols of the S-SSB (i.e., symbols #0, #1, #2, and #3 in terms of symbol index in the slot) are mapped for S-PSS, and the sixth, eighth, tenth, and twelfth symbols of the S-SSB (i.e., symbols #5, #7, #8, #9 in terms of symbol index in the slot) are mapped for S-PSS. , #9, and #11) are mapped for S-SSS (if the S-SSB BW is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the S-SSB BW is greater than 12 RBs, e.g., 20 RBs), and the 5th, 7th, 9th, 11th, and 13th symbols of the S-SSB (i.e., symbols #4, #6, #8, #10, and #12 in terms of symbol index within the slot) are mapped for PSBCH.

[0162] As yet another example (e.g., 1412 of FIG. 14B), symbols #0 through #12 may be mapped for S-SSB in a slot, where: the first, second, third, and fourth symbols of the S-SSB (i.e., symbols #0, #1, #2, and #3 in terms of symbol index within the slot) are mapped for S-PSS, and the tenth, eleventh, twelfth, and thirteenth symbols of the S-SSB (i.e., symbols #9, #10, #11, #12, and #13 in terms of symbol index within the slot) are mapped for S-PSS. Symbols #10, #11, and #12) are mapped for S-SSS (if the S-SSB BW is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the S-SSB BW is greater than 12 RBs, e.g., 20 RBs), and the 5th, 6th, 7th, 8th, and 9th symbols of the S-SSB (i.e., symbols #4, #5, #6, #7, and #8 in terms of symbol index within the slot) are mapped for PSBCH.

[0163] As yet another example (e.g., 1413 of FIG. 14B), symbols #0 through #12 may be mapped for S-SSB in a slot, where: the first, second, third, and fourth symbols of the S-SSB (i.e., symbols #0, #1, #2, and #3 in terms of symbol index within the slot) are mapped for S-PSS, and the eighth, ninth, tenth, and eleventh symbols of the S-SSB (i.e., symbols #7, #8, and #9 in terms of symbol index within the slot) are mapped for S-PSS. , #9, and #10) are mapped for S-SSS (if the S-SSB BW is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the S-SSB BW is greater than 12 RBs, e.g., 20 RBs), and the 5th, 6th, 7th, 12th, and 13th symbols of the S-SSB (i.e., symbols #4, #5, #6, #11, and #12 in terms of symbol index within the slot) are mapped for PSBCH.

[0164] As yet another example (e.g., 1414 of FIG. 14B), symbols #0 through #12 may be mapped for the S-SSB in a slot, where: the first, second, third, and fourth symbols of the S-SSB (i.e., symbols #0, #1, #2, and #3 in terms of symbol index within the slot) are mapped for the S-PSS, and the seventh, eighth, ninth, and tenth symbols of the S-SSB (i.e., symbols #6, #7, #8, #9, #10, #11, #12, #13, #14, #15, #16, #17, #18, #19, #20, #21, #22, #23, #24, #25, #26, #27, #28, #29, #30, #31, #32, #33, #34, #35, #36, #37, #38, #39, #40, #41, #42, #43, #44, #45, #46, #47, #48, #49, #50, #51, #52, #53, #54, #55, #56, #57, #58, #69, #70, #71, #72, #73, #74, #75, #76, #77, #78, #89, #90, #91, #92, #93, #94, #95, #96, #97, #98, #99, #100, #101, #102, #103, #104, #105, #106, #107, #108, #109, #110, #111, #122, #131, #142, #143, #154, #165, #1 #8, and #9) are mapped for S-SSS (if the S-SSB BW is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the S-SSB BW is greater than 12 RBs, e.g., 20 RBs), and the 5th, 6th, 11th, 12th, and 13th symbols of the S-SSB (i.e., symbols #4, #5, #10, #11, and #12 in terms of symbol index within the slot) are mapped for PSBCH.

[0165] As yet another example (e.g., 1415 of FIG. 14B), symbols #0 through #12 may be mapped for the S-SSB in a slot, where: the first, second, third, and fourth symbols of the S-SSB (i.e., symbols #0, #1, #2, and #3 in terms of symbol index within the slot) are mapped for the S-PSS, and the seventh, eighth, tenth, and eleventh symbols of the S-SSB (i.e., symbols #6, #7, and #8 in terms of symbol index within the slot) are mapped for the S-PSS. , #9, and #10) are mapped for S-SSS (if the S-SSB BW is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the S-SSB BW is greater than 12 RBs, e.g., 20 RBs), and the 5th, 6th, 9th, 12th, and 13th symbols of the S-SSB (i.e., symbols #4, #5, #8, #11, and #12 in terms of symbol index within the slot) are mapped for PSBCH.

[0166] As yet another example (e.g., 1416 of FIG. 14B), symbols #0 through #12 may be mapped for the S-SSB in a slot, where: the first, second, third, and fourth symbols of the S-SSB (i.e., symbols #0, #1, #2, and #3 in terms of symbol index within the slot) are mapped for the S-PSS, and the sixth, seventh, eleventh, and twelfth symbols of the S-SSB (i.e., symbols #5, #6, and #7 in terms of symbol index within the slot) are mapped for the S-PSS. , #10, and #11) are mapped for S-SSS (if the S-SSB BW is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the S-SSB BW is greater than 12 RBs, e.g., 20 RBs), and the 5th, 8th, 9th, 10th, and 13th symbols of the S-SSB (i.e., symbols #4, #7, #8, #9, and #12 in terms of symbol index within the slot) are mapped for PSBCH.

[0167] As yet another example (e.g., 1421 of FIG. 14C), symbols #0 through #12 are mapped for S-SSB in a slot, where: the second, third, and fourth symbols of the S-SSB (i.e., symbols #1, #2, and #3 in terms of symbol index in the slot) are mapped for S-PSS, and the sixth, ninth, and twelfth symbols of the S-SSB (i.e., symbols #5, #8, and #11 in terms of symbol index in the slot) are mapped for S-PSS. The 1st, 5th, 7th, 8th, 10th, 11th and 13th symbols of the S-SSB (i.e., symbols #0, #4, #6, #7, #9, #10 and #12 in terms of symbol index within the slot) are mapped for SSS (if the S-SSB BW is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the S-SSB BW is greater than 12 RBs, e.g., 20 RBs) and the 1st, 5th, 7th, 8th, 10th, 11th and 13th symbols of the S-SSB (i.e., symbols #0, #4, #6, #7, #9, #10 and #12 in terms of symbol index within the slot) are mapped for PSBCH.

[0168] As yet another example (e.g., 1422 of FIG. 14C), symbols #0 through #12 may be mapped for the S-SSB in a slot, where: the second, third, and fourth symbols of the S-SSB (i.e., symbols #1, #2, and #3 in terms of symbol index within the slot) are mapped for the S-PSS, and the eleventh, twelfth, and thirteenth symbols of the S-SSB (i.e., symbols #10, #11, and #12 in terms of symbol index within the slot) are mapped for the S-PSS. ) is mapped for S-SSS (if the S-SSB BW is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the S-SSB BW is greater than 12 RBs, e.g., 20 RBs), and the 1st, 5th, 6th, 7th, 8th, 9th and 10th symbols of the S-SSB (i.e., symbols #0, #4, #5, #6, #7, #8, and #9 in terms of symbol index within the slot) are mapped for PSBCH.

[0169] As yet another example (e.g., 1423 of FIG. 14C), symbols #0 through #12 are mapped for S-SSB in a slot, where: the second, third, and fourth symbols of the S-SSB (i.e., symbols #1, #2, and #3 in terms of symbol index in the slot) are mapped for S-PSS, and the eighth, ninth, and tenth symbols of the S-SSB (i.e., symbols #7, #8, and #9 in terms of symbol index in the slot) are mapped for S-PSS. The first, fifth, sixth, seventh, eleventh, twelfth and thirteenth symbols of the S-SSB (i.e., symbols #0, #4, #5, #6, #10, #11 and #12 in terms of symbol index within the slot) are mapped for the SS (if the S-SSB BW is 12 RBs or 24 RBs) or for multiplexing of the S-SSS and PSBCH (if the S-SSB BW is greater than 12 RBs, e.g., 20 RBs), and the first, fifth, sixth, seventh, eleventh, twelfth and thirteenth symbols of the S-SSB (i.e., symbols #0, #4, #5, #6, #10, #11 and #12 in terms of symbol index within the slot) are mapped for the PSBCH.

[0170] As yet another example (e.g., 1424 of FIG. 14C), symbols #0 through #12 may be mapped for an S-SSB in a slot, where: the second, third, and fourth symbols of the S-SSB (i.e., symbols #1, #2, and #3 in terms of symbol index within the slot) are mapped for an S-PSS, and the fifth, eighth, and eleventh symbols of the S-SSB (i.e., symbols #4, #7, and #10 in terms of symbol index within the slot) are mapped for an S-PSS. The 1st, 6th, 7th, 9th, 10th, 12th and 13th symbols of the S-SSB (i.e., symbols #0, #5, #6, #8, #9, #11 and #12 in terms of symbol index within the slot) are mapped for SSS (if the S-SSB BW is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the S-SSB BW is greater than 12 RBs, e.g., 20 RBs) and the 1st, 6th, 7th, 9th, 10th, 12th and 13th symbols of the S-SSB (i.e., symbols #0, #5, #6, #8, #9, #11 and #12 in terms of symbol index within the slot) are mapped for PSBCH.

[0171] As yet another example (e.g., 1431 of FIG. 14D), symbols #0 through #12 are mapped for S-SSB in a slot, where: the second and third symbols of the S-SSB (i.e., symbols #1 and #2 in terms of symbol index in the slot) are mapped for S-PSS, and the sixth and tenth symbols of the S-SSB (i.e., symbols #5 and #9 in terms of symbol index in the slot) are mapped for S-SSS. The 1st, 4th, 5th, 7th, 8th, 9th, 11th, 12th and 13th symbols of the S-SSB (i.e., symbols #0, #3, #4, #6, #7, #8, #10, #11 and #12 in terms of symbol index within the slot) are mapped for the PSBCH, or for multiplexing of the S-SSS and PSBCH (if the S-SSB BW is 12 RBs or 24 RBs), and the 1st, 4th, 5th, 7th, 8th, 9th, 11th, 12th and 13th symbols of the S-SSB (i.e., symbols #0, #3, #4, #6, #7, #8, #10, #11 and #12 in terms of symbol index within the slot) are mapped for the PSBCH.

[0172] As another example (e.g., 1432 of FIG. 14D), symbols #0 through #12 may be mapped for S-SSB in a slot, where: the second and third symbols of the S-SSB (i.e., symbols #1 and #2 in terms of symbol index within the slot) are mapped for S-PSS, and the twelfth and thirteenth symbols of the S-SSB (i.e., symbols #11 and #12 in terms of symbol index within the slot) are mapped for S-SSS. The first, fourth, fifth, sixth, seventh, eighth, ninth, tenth and eleventh symbols of the S-SSB (i.e., symbols #0, #3, #4, #5, #6, #7, #8, #9 and #10 in terms of symbol index within the slot) are mapped for the PSBCH, or the second, fourth, fifth, sixth, seventh, eighth, ninth, tenth and eleventh symbols of the S-SSB (i.e., symbols #0, #3, #4, #5, #6, #7, #8, #9 and #10 in terms of symbol index within the slot) are mapped for the PSBCH.

[0173] As yet another example (e.g., 1433 of FIG. 14D), symbols #0 through #12 are mapped for S-SSB in a slot, where: the second and third symbols of the S-SSB (i.e., symbols #1 and #2 in terms of symbol index in the slot) are mapped for S-PSS, and the eighth and ninth symbols of the S-SSB (i.e., symbols #7 and #8 in terms of symbol index in the slot) are mapped for S-SSS. For multiplexing of S-SSS and PSBCH (if the S-SSB BW is greater than 12 RBs, e.g., 20 RBs), the 1st, 4th, 5th, 6th, 7th, 10th, 11th, 12th and 13th symbols of the S-SSB (i.e., symbols #0, #3, #4, #5, #6, #9, #10, #11 and #12 in terms of symbol index within the slot) are mapped for the PSBCH.

[0174] As yet another example (e.g., 1434 of FIG. 14D), symbols #0 through #12 are mapped for S-SSB in a slot, where: the second and third symbols of the S-SSB (i.e., symbols #1 and #2 in terms of symbol index in the slot) are mapped for S-PSS, and the fourth and ninth symbols of the S-SSB (i.e., symbols #3 and #8 in terms of symbol index in the slot) are mapped for S-SSS. For S-SSB multiplexing (when the S-SSB BW is 12 RBs or 24 RBs) or for S-SSS and PSBCH multiplexing (when the S-SSB BW is greater than 12 RBs, e.g., 20 RBs), the 1st, 5th, 6th, 7th, 8th, 10th, 11th, 12th and 13th symbols of the S-SSB (i.e., symbols #0, #4, #5, #6, #7, #9, #10, #11 and #12 in terms of symbol index within the slot) are mapped for the PSBCH.

[0175] As yet another example (e.g., 1435 of FIG. 14D), symbols #0 through #12 are mapped for S-SSB in a slot, where: the second and third symbols of the S-SSB (i.e., symbols #1 and #2 in terms of symbol index in the slot) are mapped for S-PSS, and the sixth and ninth symbols of the S-SSB (i.e., symbols #4 and #8 in terms of symbol index in the slot) are mapped for S-SSS. For S-SSB multiplexing (when the S-SSB BW is 12 RBs or 24 RBs) or for S-SSS and PSBCH multiplexing (when the S-SSB BW is greater than 12 RBs, e.g., 20 RBs), the 1st, 4th, 6th, 7th, 8th, 10th, 11th, 12th and 13th symbols of the S-SSB (i.e., symbols #0, #3, #5, #6, #7, #9, #10, #11 and #12 in terms of symbol index within the slot) are mapped for the PSBCH.

[0176] As yet another example (e.g., 1436 of FIG. 14D), symbols #0 through #12 are mapped for S-SSB in a slot, where: the second and third symbols of the S-SSB (i.e., symbols #1 and #2 in terms of symbol index in the slot) are mapped for S-PSS, and the fifth and tenth symbols of the S-SSB (i.e., symbols #4 and #9 in terms of symbol index in the slot) are mapped for S-SSS. The first, fourth, sixth, seventh, eighth, ninth, eleventh, twelfth and thirteenth symbols of the S-SSB (i.e., symbols #0, #3, #5, #6, #7, #8, #10, #11 and #12 in terms of symbol index within the slot) are mapped for the PSBCH, or for multiplexing of the S-SSS and PSBCH (if the S-SSB BW is 12 RBs or 24 RBs), and the first, fourth, sixth, seventh, eighth, ninth, eleventh, twelfth and thirteenth symbols of the S-SSB (i.e., symbols #0, #3, #5, #6, #7, #8, #10, #11 and #12 in terms of symbol index within the slot) are mapped for the PSBCH.

[0177] As yet another example (e.g., 1441 of FIG. 14E), symbols #0 through #12 are mapped for S-SSB in a slot, where: the second, third, fourth, and fifth symbols of the S-SSB (i.e., symbols #1, #2, #3, and #4 in terms of symbol index in the slot) are mapped for S-PSS, and the eighth, ninth, tenth, and eleventh symbols of the S-SSB (i.e., symbols #7, #8, and #9 in terms of symbol index in the slot) are mapped for S-PSS. , #9, and #10) are mapped for S-SSS (if the S-SSB BW is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the S-SSB BW is greater than 12 RBs, e.g., 20 RBs), and the 1st, 6th, 7th, 12th, and 13th symbols of the S-SSB (i.e., symbols #0, #5, #6, #11, and #12 in terms of symbol index within the slot) are mapped for PSBCH.

[0178] As yet another example (e.g., 1442 of FIG. 14E), symbols #0 through #12 are mapped for S-SSB in a slot, where: the second, third, fourth, and fifth symbols of the S-SSB (i.e., symbols #1, #2, #3, and #4 in terms of symbol index within the slot) are mapped for S-PSS, and the tenth, eleventh, twelfth, and thirteenth symbols of the S-SSB (i.e., symbols #9, Symbols #10, #11, and #12) are mapped for S-SSS (if the S-SSB BW is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the S-SSB BW is greater than 12 RBs, e.g., 20 RBs), and the 1st, 6th, 7th, 8th, and 9th symbols of the S-SSB (i.e., symbols #0, #5, #6, #7, and #8 in terms of symbol index within the slot) are mapped for PSBCH.

[0179] As a seventeenth example (e.g., 1443 of FIG. 14E), symbols #0 through #12 are mapped for S-SSB in a slot, where: the second, third, fourth, and fifth symbols of the S-SSB (i.e., symbols #1, #2, #3, and #4 in terms of symbol index in the slot) are mapped for S-PSS, and the seventh, ninth, eleventh, and thirteenth symbols of the S-SSB (i.e., symbols #6, #8, and #9 in terms of symbol index in the slot) are mapped for S-PSS. , #10, and #12) are mapped for S-SSS (if the S-SSB BW is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the S-SSB BW is greater than 12 RBs, e.g., 20 RBs), and the 1st, 6th, 8th, 10th, and 12th symbols of the S-SSB (i.e., symbols #0, #5, #7, #9, and #11 in terms of symbol index within the slot) are mapped for PSBCH.

[0180] As yet another example (e.g., 1444 of FIG. 14E), symbols #0 through #12 may be mapped for S-SSB in a slot, where: the second, third, fourth, and fifth symbols of the S-SSB (i.e., symbols #1, #2, #3, and #4 in terms of symbol index in the slot) are mapped for S-PSS, and the sixth, eighth, tenth, and twelfth symbols of the S-SSB (i.e., symbols #5, #7, #8 in terms of symbol index in the slot) are mapped for S-PSS. , #9, and #11) are mapped for S-SSS (if the S-SSB BW is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the S-SSB BW is greater than 12 RBs, e.g., 20 RBs), and the 1st, 7th, 9th, 11th, and 13th symbols of the S-SSB (i.e., symbols #0, #6, #8, #10, and #12 in terms of symbol index within the slot) are mapped for PSBCH.

[0181] 15A, 15B, and 15C are diagrams showing an example of this embodiment in which a slot having 14 symbols includes one PSBCH block (SSB), the PSBCH block includes 14 symbols, and the symbols in the slot are not reserved for other purposes. In one consideration, each PSBCH block includes 3 symbols for S-PSS, 3 symbols for multiplexing S-SSS or S-SSS and PSBCH, and 8 symbols for PSBCH. In another consideration, each PSBCH block includes 2 symbols for S-PSS, 2 symbols for multiplexing S-SSS or S-SSS and PSBCH, and 10 symbols for PSBCH. In yet another consideration, each PSBCH block includes 4 symbols for S-PSS, 4 symbols for multiplexing S-SSS or S-SSS and PSBCH, and 6 symbols for PSBCH.

[0182] As an example (e.g., 1501 in FIG. 15A), symbols #0 through #13 are mapped for S-SSB in a slot, where: the first, second, and third symbols of the S-SSB (i.e., symbols #0, #1, and #2 in terms of symbol index in the slot) are mapped for S-PSS, and the sixth, ninth, and twelfth symbols of the S-SSB (i.e., symbols #5, #8, and #11 in terms of symbol index in the slot) are mapped for S-PSS. (if the S-SSB BW is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the S-SSB BW is greater than 12 RBs, e.g., 20 RBs), and the 4th, 5th, 7th, 8th, 9th, 11th and 13th symbols of the S-SSB (i.e., symbols #3, #4, #6, #7, #9, #10, #12 and #13 in terms of symbol index within the slot) are mapped for the PSBCH.

[0183] As another example (e.g., 1502 of FIG. 15A), symbols #0 through #13 may be mapped for S-SSB in a slot, where: the first, second, and third symbols of the S-SSB (i.e., symbols #0, #1, and #2 in terms of symbol index within the slot) are mapped for S-PSS, and the twelfth, thirteenth, and fourteenth symbols of the S-SSB (i.e., symbols #11, #12, and #13 in terms of symbol index within the slot) are mapped for S-PSS. (if the S-SSB BW is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the S-SSB BW is greater than 12 RBs, e.g., 20 RBs), and the 4th, 5th, 7th, 8th, 9th, 11th, 13th and 14th symbols of the S-SSB (i.e., symbols #3, #4, #6, #7, #9, #10, #12 and #13 in terms of symbol index within the slot) are mapped for the PSBCH.

[0184] As a third example (e.g., 1503 of FIG. 15A), symbols #0 through #13 are mapped for S-SSB in a slot, where: the first, second, and third symbols of the S-SSB (i.e., symbols #0, #1, and #2 in terms of symbol index within the slot) are mapped for S-PSS, and the eighth, ninth, and tenth symbols of the S-SSB (i.e., symbols #7, #8, and #9 in terms of symbol index within the slot) are mapped for S-SSS. (if the S-SSB BW is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the S-SSB BW is greater than 12 RBs, e.g., 20 RBs), and the 4th, 5th, 6th, 7th, 11th, 12th, 13th and 14th symbols of the S-SSB (i.e., symbols #3, #4, #5, #6, #10, #11, #12 and #13 in terms of symbol index within the slot) are mapped for the PSBCH.

[0185] As yet another example (e.g., 1504 of FIG. 15A ), symbols #0 through #13 may be mapped for S-SSB in a slot, where: the first, second, third, and fourth symbols of the S-SSB (i.e., symbols #0, #1, #2, and #3 in terms of symbol index within the slot) are mapped for S-PSS, and the eighth, ninth, tenth, and eleventh symbols of the S-SSB (i.e., symbols #7, #8, #9, and #10) are mapped for S-SSS (if the S-SSB BW is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the S-SSB BW is greater than 12 RBs, e.g., 20 RBs), and the 5th, 6th, 7th, 12th, 13th and 14th symbols of the S-SSB (i.e., symbols #4, #5, #6, #11, #12 and #13 in terms of symbol index within the slot) are mapped for PSBCH.

[0186] As yet another example (e.g., 1505 of FIG. 15A), symbols #0 through #13 may be mapped for S-SSB in a slot, where: the first, second, third, and fourth symbols of the S-SSB (i.e., symbols #0, #1, #2, and #3 in terms of symbol index within the slot) are mapped for S-PSS, and the eleventh, twelfth, thirteenth, and fourteenth symbols of the S-SSB (i.e., symbols #10, #11, #20, #22, and #24 in terms of symbol index within the slot) are mapped for S-PSS. , #12, and #13) are mapped for S-SSS (if the S-SSB BW is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the S-SSB BW is greater than 12 RBs, e.g., 20 RBs), and the 5th, 6th, 7th, 8th, 9th, and 10th symbols of the S-SSB (i.e., symbols #4, #5, #6, #7, #8, and #9 in terms of symbol index within the slot) are mapped for PSBCH.

[0187] As yet another example (e.g., 1506 of FIG. 15A), symbols #0 through #13 may be mapped for S-SSB in a slot, where: the first, second, third, and fourth symbols of the S-SSB (i.e., symbols #0, #1, #2, and #3 in terms of symbol index within the slot) are mapped for S-PSS, and the seventh, eighth, eleventh, and twelfth symbols of the S-SSB (i.e., symbols #6, #7, #10 in terms of symbol index within the slot) are mapped for S-PSS. , and #11) are mapped for S-SSS (if the S-SSB BW is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the S-SSB BW is greater than 12 RBs, e.g., 20 RBs), and the 5th, 6th, 9th, 10th, 13th and 14th symbols of the S-SSB (i.e., symbols #4, #5, #8, #9, #12, and #13 in terms of symbol index within the slot) are mapped for PSBCH.

[0188] As yet another example (e.g., 1511 of FIG. 15B), symbols #0 through #13 may be mapped for S-SSB in a slot, where: the second, third, and fourth symbols of the S-SSB (i.e., symbols #1, #2, and #3 in terms of symbol index within the slot) are mapped for S-PSS, and the seventh, tenth, and thirteenth symbols of the S-SSB (i.e., symbols #6, #9, and #12 in terms of symbol index within the slot) are mapped for S-PSS. (if the BW of the S-SSB is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the BW of the S-SSB is greater than 12 RBs, e.g., 20 RBs), and the 1st, 5th, 6th, 8th, 9th, 11th, 12th and 14th symbols of the S-SSB (i.e., symbols #0, #4, #5, #7, #8, #10, #11 and #13 in terms of symbol index within the slot) are mapped for the PSBCH.

[0189] As yet another example (e.g., 1512 of FIG. 15B), symbols #0 through #13 may be mapped for an S-SSB in a slot, where: the second, third, and fourth symbols of the S-SSB (i.e., symbols #1, #2, and #3 in terms of symbol index within the slot) are mapped for an S-PSS, and the twelfth, thirteenth, and fourteenth symbols of the S-SSB (i.e., symbols #11, #12, and #13 in terms of symbol index within the slot) are mapped for an S-PSS. The first, fifth, sixth, seventh, eighth, ninth, tenth and eleventh symbols of the S-SSB (i.e., symbols #0, #4, #5, #6, #7, #8, #9 and #10 in terms of symbol index within the slot) are mapped for SSS (if the S-SSB BW is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the S-SSB BW is greater than 12 RBs, e.g., 20 RBs), and the first, fifth, sixth, seventh, eighth, ninth, tenth and eleventh symbols of the S-SSB (i.e., symbols #0, #4, #5, #6, #7, #8, #9 and #10 in terms of symbol index within the slot) are mapped for PSBCH.

[0190] As yet another example (e.g., 1513 of FIG. 15B), symbols #0 through #13 may be mapped for S-SSB in a slot, where: the second, third, and fourth symbols of the S-SSB (i.e., symbols #1, #2, and #3 in terms of symbol index within the slot) are mapped for S-PSS, and the eighth, ninth, and tenth symbols of the S-SSB (i.e., symbols #7, #8, and #9 in terms of symbol index within the slot) are mapped for S-SSS. For S-SSB multiplexing (when the BW of the S-SSB is 12 RBs or 24 RBs) or for S-SSS and PSBCH multiplexing (when the BW of the S-SSB is greater than 12 RBs, e.g., 20 RBs), the 1st, 5th, 6th, 7th, 11th, 12th, 13th, and 14th symbols of the S-SSB (i.e., symbols #0, #4, #5, #6, #10, #11, #12, and #13 in terms of symbol index within a slot) are mapped for the PSBCH.

[0191] As yet another example (e.g., 1514 of FIG. 15B), symbols #0 through #13 may be mapped for an S-SSB in a slot, where: the second, third, and fourth symbols of the S-SSB (i.e., symbols #1, #2, and #3 in terms of symbol index within the slot) are mapped for an S-PSS, and the ninth, tenth, and eleventh symbols of the S-SSB (i.e., symbols #8, #9, and #10 in terms of symbol index within the slot) are mapped for an S-PSS. For S-SSB, the 1st, 5th, 6th, 7th, 8th, 12th, 13th and 14th symbols (i.e., symbols #0, #4, #5, #6, #7, #11, #12 and #13 in terms of symbol index within the slot) are mapped for PSBCH (if the BW of the S-SSB is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the BW of the S-SSB is greater than 12 RBs, e.g., 20 RBs), and the 1st, 5th, 6th, 7th, 8th, 12th, 13th and 14th symbols of the S-SSB (i.e., symbols #0, #4, #5, #6, #7, #11, #12 and #13 in terms of symbol index within the slot) are mapped for PSBCH.

[0192] As yet another example (e.g., 1521 of FIG. 15C), symbols #0 through #13 are mapped for S-SSB in a slot, where: the second, third, fourth, and fifth symbols of the S-SSB (i.e., symbols #1, #2, #3, and #4 in terms of symbol index in the slot) are mapped for S-PSS, and the eleventh, twelfth, thirteenth, and fourteenth symbols of the S-SSB (i.e., symbols #10, #11, #22, #24, #26 in terms of symbol index in the slot) are mapped for S-PSS. Symbols #12, and #13) are mapped for S-SSS (if the S-SSB BW is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the S-SSB BW is greater than 12 RBs, e.g., 20 RBs), and the 1st, 6th, 7th, 8th, 9th, and 10th symbols of the S-SSB (i.e., symbols #0, #5, #6, #7, #8, and #9 in terms of symbol index within the slot) are mapped for PSBCH.

[0193] As yet another example (e.g., 1522 of FIG. 15C), symbols #0 through #13 may be mapped for S-SSB in a slot, where: the second, third, fourth, and fifth symbols of the S-SSB (i.e., symbols #1, #2, #3, and #4 in terms of symbol index within the slot) are mapped for S-PSS, and the seventh, eighth, eleventh, and twelfth symbols of the S-SSB (i.e., symbols #6, #7, #10 in terms of symbol index within the slot) are mapped for S-PSS. , and #11) are mapped for S-SSS (if the S-SSB BW is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the S-SSB BW is greater than 12 RBs, e.g., 20 RBs), and the 1st, 6th, 9th, 10th, 13th and 14th symbols of the S-SSB (i.e., symbols #0, #5, #8, #9, #12, and #13 in terms of symbol index within the slot) are mapped for PSBCH.

[0194] As yet another example (e.g., 1523 of FIG. 15C), symbols #0 through #13 may be mapped for S-SSB in a slot, where: the second, third, fourth, and fifth symbols of the S-SSB (i.e., symbols #1, #2, #3, and #4 in terms of symbol index within the slot) are mapped for S-PSS, and the eighth, ninth, tenth, and eleventh symbols of the S-SSB (i.e., symbols #7, #8, #9, and #10) are mapped for S-SSS (if the S-SSB BW is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the S-SSB BW is greater than 12 RBs, e.g., 20 RBs), and the 1st, 6th, 7th, 12th, 13th and 14th symbols of the S-SSB (i.e., symbols #0, #5, #6, #11, #12 and #13 in terms of symbol index within the slot) are mapped for PSBCH.

[0195] As yet another example (e.g., 1524 of FIG. 15C), symbols #0 through #13 are mapped for S-SSB in a slot, where: the second, third, fourth, and fifth symbols of the S-SSB (i.e., symbols #1, #2, #3, and #4 in terms of symbol index in the slot) are mapped for S-PSS, and the ninth, tenth, eleventh, and twelfth symbols of the S-SSB (i.e., symbols #8, #9, #1 in terms of symbol index in the slot) are mapped for S-PSS. Symbols #0, #11, and #20 of the S-SSB are mapped for S-SSS (if the S-SSB BW is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the S-SSB BW is greater than 12 RBs, e.g., 20 RBs), and the 1st, 6th, 7th, 8th, 13th, and 14th symbols of the S-SSB (i.e., symbols #0, #5, #6, #7, #12, and #13 in terms of symbol index within the slot) are mapped for PSBCH.

[0196] As yet another example (e.g., 1525 of FIG. 15C), symbols #0 through #13 may be mapped for S-SSB in a slot, where: the second, third, fourth, and fifth symbols of the S-SSB (i.e., symbols #1, #2, #3, and #4 in terms of symbol index within the slot) are mapped for S-PSS, and the eighth, ninth, twelfth, and thirteenth symbols of the S-SSB (i.e., symbols #7, #8, #11 in terms of symbol index within the slot) are mapped for S-PSS. , and #12) are mapped for S-SSS (if the S-SSB BW is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the S-SSB BW is greater than 12 RBs, e.g., 20 RBs), and the 1st, 6th, 7th, 10th, 11th and 14th symbols of the S-SSB (i.e., symbols #0, #5, #6, #9, #10 and #13 in terms of symbol index within the slot) are mapped for PSBCH.

[0197] 16A and 16B are diagrams showing an example of this embodiment in which a slot with 12 symbols (e.g., in the case of an extended CP) includes one PSBCH block (SSB), the PSBCH block includes 11 symbols, and one symbol (e.g., the last symbol) in the slot is reserved for other purposes such as a transmit-receive (TX / RX) switch gap. In one consideration, each PSBCH block includes 3 symbols for S-PSS, 3 symbols for multiplexing S-SSS or S-SSS and PSBCH, and 5 symbols for PSBCH. In another consideration, each PSBCH block includes 2 symbols for S-PSS, 2 symbols for multiplexing S-SSS or S-SSS and PSBCH, and 7 symbols for PSBCH. In yet another consideration, each PSBCH block includes 4 symbols for S-PSS, 4 symbols for multiplexing S-SSS or S-SSS and PSBCH, and 3 symbols for PSBCH.

[0198] As an example (e.g., 1601 in FIG. 16A), symbols #0 to #10 are mapped for S-SSB in a slot, where: the second and third symbols of the S-SSB (i.e., symbols #1 and #2 in terms of symbol index in the slot) are mapped for S-PSS, the sixth and eleventh symbols of the S-SSB (i.e., symbols #5 and #8 in terms of symbol index in the slot) are mapped for S-SSS (if the BW of the S-SSB is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the BW of the S-SSB is greater than 12 RBs, e.g., 20 RBs), and the first, fourth, fifth, seventh, eighth, tenth and eleventh symbols of the S-SSB (i.e., symbols #0, #3, #4, #6, #7, #9, and #10 in terms of symbol index in the slot) are mapped for PSBCH.

[0199] As another example (e.g., 1602 of FIG. 16A), symbols #0 to #10 are mapped for S-SSB in the slot, where: the second and third symbols of the S-SSB (i.e., symbols #1 and #2 in terms of symbol index in the slot) are mapped for S-PSS, the seventh and eighth symbols of the S-SSB (i.e., symbols #6 and #7 in terms of symbol index in the slot) are mapped for S-SSS (if the BW of the S-SSB is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the BW of the S-SSB is greater than 12 RBs, e.g., 20 RBs), and the first, fourth, fifth, sixth, ninth, tenth and eleventh symbols of the S-SSB (i.e., symbols #0, #3, #4, #5, #8, #9 and #10 in terms of symbol index in the slot) are mapped for PSBCH.

[0200] As another example (e.g., 1603 of FIG. 16A), symbols #0 to #10 are mapped for S-SSB in the slot, where: the second and third symbols of the S-SSB (i.e., symbols #1 and #2 in terms of symbol index in the slot) are mapped for S-PSS, the fifth and ninth symbols of the S-SSB (i.e., symbols #4 and #8 in terms of symbol index in the slot) are mapped for S-SSS (if the BW of the S-SSB is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the BW of the S-SSB is greater than 12 RBs, e.g., 20 RBs), and the first, fourth, sixth, seventh, eighth, tenth and eleventh symbols of the S-SSB (i.e., symbols #0, #3, #5, #6, #7, #9, and #10 in terms of symbol index in the slot) are mapped for PSBCH.

[0201] As another example (e.g., 1604 of FIG. 16A), symbols #0 through #10 are mapped for S-SSB in the slot, where: the second and third symbols of the S-SSB (i.e., symbols #1 and #2 in terms of symbol index in the slot) are mapped for S-PSS, the fifth and eighth symbols of the S-SSB (i.e., symbols #4 and #7 in terms of symbol index in the slot) are mapped for S-SSS (if the BW of the S-SSB is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the BW of the S-SSB is greater than 12 RBs, e.g., 20 RBs), and the first, fourth, sixth, seventh, ninth, tenth and eleventh symbols of the S-SSB (i.e., symbols #0, #3, #5, #6, #8, #9 and #10 in terms of symbol index in the slot) are mapped for PSBCH.

[0202] As another example (e.g., 1605 of FIG. 16A), symbols #0 to #10 are mapped for S-SSB in the slot, where: the second and third symbols of the S-SSB (i.e., symbols #1 and #2 in terms of symbol index in the slot) are mapped for S-PSS, the fourth and eighth symbols of the S-SSB (i.e., symbols #3 and #7 in terms of symbol index in the slot) are mapped for S-SSS (if the BW of the S-SSB is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the BW of the S-SSB is greater than 12 RBs, e.g., 20 RBs), and the first, fifth, sixth, seventh, ninth, tenth and eleventh symbols of the S-SSB (i.e., symbols #0, #4, #5, #6, #8, #9 and #10 in terms of symbol index in the slot) are mapped for PSBCH.

[0203] As another example (e.g., 1606 of FIG. 16A), symbols #0 through #10 are mapped for S-SSB in the slot, where: the second and third symbols of the S-SSB (i.e., symbols #1 and #2 in terms of symbol index in the slot) are mapped for S-PSS, the tenth and eleventh symbols of the S-SSB (i.e., symbols #9 and #10 in terms of symbol index in the slot) are mapped for S-SSS (if the BW of the S-SSB is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the BW of the S-SSB is greater than 12 RBs, e.g., 20 RBs), and the first, fourth, fifth, sixth, seventh, eighth and ninth symbols of the S-SSB (i.e., symbols #0, #3, #4, #5, #6, #7 and #8 in terms of symbol index in the slot) are mapped for PSBCH.

[0204] As another example (e.g., 1611 in FIG. 16B), symbols #0 through #10 are mapped for S-SSB in a slot, where: the second, third, and fourth symbols of the S-SSB (i.e., symbols #1, #2, and #3 in terms of symbol index in the slot) are mapped for S-PSS, the sixth, eighth, and tenth symbols of the S-SSB (i.e., symbols #5, #7, and #9 in terms of symbol index in the slot) are mapped for S-SSS (if the BW of the S-SSB is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the BW of the S-SSB is greater than 12 RBs, e.g., 20 RBs), and the first, fifth, seventh, ninth, and eleventh symbols of the S-SSB (i.e., symbols #0, #4, #6, #8, and #10 in terms of symbol index in the slot) are mapped for PSBCH.

[0205] As another example (e.g., 1612 of FIG. 16B), symbols #0 to #10 are mapped for S-SSB in the slot, where: the second, third and fourth symbols of the S-SSB (i.e., symbols #1, #2 and #3 in terms of symbol index in the slot) are mapped for S-PSS, the fifth, seventh and ninth symbols of the S-SSB (i.e., symbols #4, #6 and #8 in terms of symbol index in the slot) are mapped for S-SSS (if the BW of the S-SSB is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the BW of the S-SSB is greater than 12 RBs, e.g., 20 RBs), and the first, sixth, eighth, tenth and eleventh symbols of the S-SSB (i.e., symbols #0, #5, #7, #9 and #10 in terms of symbol index in the slot) are mapped for PSBCH.

[0206] As another example (e.g., 1613 of FIG. 16B), symbols #0 to #10 are mapped for S-SSB in the slot, where: the second, third and fourth symbols of the S-SSB (i.e., symbols #1, #2 and #3 in terms of symbol index in the slot) are mapped for S-PSS, the seventh, eighth and ninth symbols of the S-SSB (i.e., symbols #6, #7 and #8 in terms of symbol index in the slot) are mapped for S-SSS (if the BW of the S-SSB is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the BW of the S-SSB is greater than 12 RBs, e.g., 20 RBs), and the first, fifth, sixth, tenth and eleventh symbols of the S-SSB (i.e., symbols #0, #4, #5, #9 and #10 in terms of symbol index in the slot) are mapped for PSBCH.

[0207] As another example (e.g., 1614 of FIG. 16B), symbols #0 through #10 are mapped for S-SSB in the slot, where: the second, third, and fourth symbols of the S-SSB (i.e., symbols #1, #2, and #3 in terms of symbol index in the slot) are mapped for S-PSS, the ninth, tenth, and eleventh symbols of the S-SSB (i.e., symbols #8, #9, and #10 in terms of symbol index in the slot) are mapped for S-SSS (if the BW of the S-SSB is 12 RBs or 24 RBs) or for multiplexing of S-SSS and PSBCH (if the BW of the S-SSB is greater than 12 RBs, e.g., 20 RBs), and the first, fifth, sixth, seventh, and eighth symbols of the S-SSB (i.e., symbols #0, #4, #5, #6, and #7 in terms of symbol index in the slot) are mapped for PSBCH.

[0208] In a first approach for time domain mapping of an S-SSB burst set, consecutive slots containing an S-SSB burst set can be mapped from a predefined location, such as the start of the period for transmitting the S-SSB burst set.

[0209] 17 is a diagram illustrating an example time domain mapping of an S-SSB burst set 1700 according to an embodiment of the present disclosure. The embodiment of the time domain mapping of an S-SSB burst set 1700 shown in FIG. 17 is for illustration only. FIG. 17 does not limit the scope of the present disclosure to any particular implementation.

[0210] As an example of this approach (e.g., 1701 in FIG. 17), if the period for transmitting an S-SSB burst set is N slots and the duration of the S-SSB burst set is M slots, consecutive slots comprising the S-SSB burst set can start from the first slot of every N slot period, e.g., the burst set is mapped to slots #0, #1, ..., #M-1.

[0211] In a second approach for time domain mapping of an S-SSB burst set, consecutive slots comprising the S-SSB burst set can be mapped starting from any slot within the period in which the S-SSB burst set is transmitted. In this approach, the starting position of the S-SSB burst set (e.g., slot index within the period) can be indicated to the V2X UE (e.g., using a synchronization signal, or PBCH content, or DMRS on the PBCH, or a combination thereof) or can be preconfigured in the V2X UE.

[0212] As an example of this approach (e.g., 1702 in FIG. 17), if the period for transmitting an S-SSB burst set is N slots and the duration of the S-SSB burst set is M slots, the consecutive slots including the S-SSB burst set can start from any slot within the N slots (e.g., slots #S, #S+1, ..., #S+M-1), and the starting position (e.g., information for slot S) can be indicated to the V2X UE using a synchronization signal, or PBCH content, or DMRS of the PBCH, or a combination thereof (e.g., in the form of a slot index, or a combination of slot index within SFN / DFN indicated as SFN (System Frame Number) / DFN (Direct Frame Number)).

[0213] As another example of this approach, if the period for transmitting an S-SSB burst set is N slots and the duration of the S-SSB burst set is M slots, consecutive slots including the S-SSB burst set can start from any frame boundary, and the starting position (e.g., information for slot S) can be indicated to the V2X UE using a synchronization signal, or PBCH content, or PBCH DMRS, or a combination thereof (e.g., in the form of SFN (System Frame Number) / DFN (Direct Frame Number)) or can be pre-configured in the V2X UE.

[0214] As another example of this approach, if the period for transmitting an S-SSB burst set is N slots and the duration of the S-SSB burst set is M slots, consecutive slots including the S-SSB burst set can start from any half-frame boundary, and the starting position (e.g., information for slot S) can be indicated to the V2X UE using a synchronization signal, or PBCH content, or DMRS of the PBCH, or a combination thereof (e.g., in the form of a half-frame index and SFN / DFN in the System Frame Number (SFN) / Direct Frame Number (DFN)) or can be pre-configured in the V2X UE.

[0215] In a third approach to time domain mapping of S-SSB burst sets, the slots that comprise an S-SSB burst set may be non-contiguous. In a lower approach, all transmissions of an S-SSB burst set may occupy only one slot, and the multiple slots that comprise an S-SSB burst set may be evenly spaced within the S-SSB burst set period.

[0216] As a first example of this approach (e.g., 1703 in FIG. 17), if the period for transmitting an S-SSB burst set is N slots and the duration of the S-SSB burst set is M slots, the slots containing S-SSBs can be uniformly distributed within the entire period duration, e.g., the slots containing S-SSBs are #0, #(N / M), #2*(N / M), ..., #(M-1)*(N / M).

[0217] As a second example of this approach (e.g., 1704 of FIG. 17), if the period for transmitting an S-SSB burst set is N slots and the duration of the S-SSB burst set is M slots, the slots containing S-SSBs can be uniformly distributed within a subset of the period duration, e.g., the slots containing S-SSBs are #0, #(N / K), #2*(N / K), ..., #(M-1)*(N / K), where K is a predefined value and K>M.

[0218] As a third example of this approach (e.g., 1705 in FIG. 17), if the period for transmitting an S-SSB burst set is N slots and the duration of the S-SSB burst set is M slots, the slots containing the S-SSB can be uniformly distributed within the entire period duration and the start slot can be arbitrary and can be indicated to the V2X UE, e.g., the slots containing the S-SSB can be #X, #X+(N / M), #X+2*(N / M), ..., #X+(M-1)*(N / M), where X is the start position and indicated to the V2X UE using a synchronization signal, or PBCH content, or DMRS of the PBCH, or a combination thereof (e.g., in the form of a slot index, or a combination of slot indexes within the SFN / DFN indicated as SFN / DFN).

[0219] As a fourth example of this approach (e.g., 1706 in FIG. 17), if the period for transmitting an S-SSB burst set is N slots and the duration of the S-SSB burst set is M slots, the slots containing the S-SSB may be uniformly distributed within a subset of the period duration and the starting slot may be arbitrary and may be indicated to the V2X UE, e.g., the slots containing the S-SSB may be #X, #X+(N / K), #X+2*(N / K), ..., #X+(M-1)*(N / K), where K is a predefined value and K>M, and X may be indicated to the V2X UE using a synchronization signal, or PBCH content, or DMRS of the PBCH, or a combination thereof at the starting position, or may be pre-configured in the V2X UE (e.g., in the form of a slot index, or a combination of slot indexes within the SFN / DFN indicated as SFN / DFN). In one embodiment, the design of the S-PSS sequence can be combined with other example embodiments of this disclosure.

[0220] In one approach scheme, the number of sequences constituting the S-PSS in each symbol is one (i.e., N_SPSS=1). In one aspect of this approach scheme, the sequences constituting the S-PSS do not carry information on the sidelink synchronization ID. In another aspect of this approach scheme, the sidelink synchronization ID set can be subsequently divided into groups to indicate different synchronization sources, where the size of each group may not be the same. In this example approach scheme, three sidelink synchronization ID groups are to indicate the GNSS, the in-coverage UE, and the out-of-coverage UE, respectively, where the number of IDs for each group may not be the same.

[0221] In a first example of this approach, if there is a single symbol mapped for an S-PSS within an S-SSB, the single sequence constituting the S-PSS is one of the sequences constituting the NR-PSS (e.g., one of the three sequences constituting the NR-PSS is selected).

[0222] In a second example of this approach, if there is a single symbol mapped for S-PSS within the S-SSB, the single sequence that constitutes the S-PSS is orthogonal or has low cross-correlation with all sequences that constitute the NR-PSS.

[0223] In a third example of this approach, when there are many symbols mapped for S-PSS within the S-SSB, the single sequence constituting the S-PSS on different symbols is different, and the sequence constituting the S-PSS is from the set of sequences constituting the NR-PSS or from a subset of the set (e.g., a selection of two or three of the three sequences constituting the NR-PSS).

[0224] In a fourth example of this approach, when there are many symbols mapped for S-PSS within an S-SSB, the single sequences constituting the S-PSS in different symbols are different, and some of the sequences constituting the S-PSS in one symbol are from the set of sequences constituting the NR-PSS or from a subset of the set (e.g., selecting one, two or three out of the three sequences constituting the NR-PSS), and the remaining sequences are orthogonal to or have low cross-correlation with the sequences from the subset of sequences constituting the NR-PSS.

[0225] In a fifth example of this approach, when there are many symbols mapped for the S-PSS within the S-SSB, the single sequences constituting the S-PSS on different symbols are different, none of the sequences constituting the S-PSS are from the set of sequences constituting the NR-PSS, and all sequences are orthogonal to or have low cross-correlation with all the sequences constituting the NR-PSS.

[0226] In a sixth example of this approach, when there are many symbols mapped for S-PSS in an S-SSB, the single sequences constituting the S-PSS in different symbols are the same but are mapped in different patterns to the symbols for S-PSS, for example, the single sequences constituting the S-PSS are mapped from low to high in the frequency domain in some of the symbols for S-PSS and from high to low in the frequency domain in other symbols for S-PSS.

[0227] In a seventh example of this approach, when there are many symbols mapped for S-PSS within an S-SSB, the single sequence constituting the S-PSS with different symbols is identical and is mapped to the symbols for S-PSS in the same pattern (e.g., the symbols for S-PSS (excluding CP) are repeated).

[0228] In an eighth example of this approach, if there are many symbols mapped for S-PSS within the S-SSB, a single sequence for the S-PSS can be generated and mapped to all symbols for the S-PSS.

[0229] In another approach, the number of sequences constituting the S-PSS in each symbol is two (i.e., N_SPSS=2), in which the sequences constituting the S-PSS can be used to identify group indices within the two sidelink synchronization ID groups.

[0230] As an example for the two groups, the synchronization source may be referred to as being from an NR node or an LTE node. As another example for the two groups, the synchronization source may be referred to as being within the coverage of a gNB / eNB or not. As yet another example for the two groups, the synchronization source may be referred to as being a NodeB or a UE. As yet another example for the two groups, the synchronization source may be referred to as being within the coverage of a gNB / eNB or within the GNSS or outside the coverage of a gNB / eNB. As yet another example for the two groups, the synchronization source may be referred to as being within the coverage of a gNB / eNB or outside the gNB / eNB coverage or outside the GNSS.

[0231] As an example for the number of sidelink synchronization IDs in each group, the size of the two groups may be the same (e.g., it is easy to design an S-SSS sequence). As another example for the number of sidelink synchronization IDs in each group, the size of the two groups may not be the same (e.g., when the IDs of the two groups indicate outside the gNB / eNB coverage and inside the gNB / eNB coverage, the number of IDs of each group may not be the same depending on the use case of each group).

[0232] In a first example of this approach, when there is a single symbol mapped for an S-PSS within the S-SSB, the set of sequences that make up the S-PSS is a subset of the sequences that make up the NR-PSS (e.g., a selection of two of the three sequences that make up the NR-PSS).

[0233] In a second example of this approach, if there is a single symbol mapped for an S-PSS within the S-SSB, none of the sequences that make up the S-PSS are from the set of sequences that make up the NR-PSS, and they are orthogonal to or have low cross-correlation with all of the sequences that make up the NR-PSS.

[0234] In a third example of this approach, when there are many symbols mapped for S-PSS in the S-SSB, the segments of the sequences constituting the S-PSS for different symbols are different, and the sets of sequences constituting the S-PSS for different symbols are orthogonal or have low cross-correlation across the sets. For example, for some symbols, one set of sequences constituting the S-PSS is a subset of the sequences constituting the NR-PSS (e.g., two of the three sequences constituting the NR-PSS are selected), and the remaining set of sequences is not from the set of sequences constituting the NR-PSS, but is orthogonal or has low cross-correlation with the set of sequences constituting the NR-PSS.

[0235] In a fourth example of this approach, if there are many symbols mapped for the S-PSS in the S-SSB, the sets of sequences constituting the S-PSS on different symbols are different and the sets of sequences constituting the S-PSS on different symbols are orthogonal or have low cross-correlation across the sets, e.g., none of the sequences constituting the S-PSS are from the set of sequences constituting the NR-PSS, and are orthogonal or have low cross-correlation with all the sequences constituting the NR-PSS.

[0236] In a fifth example of this approach, when there are many symbols mapped for S-PSS in an S-SSB, the set of sequences constituting the S-PSS in different symbols is the same, but is mapped to different patterns for the symbols for S-PSS, for example, the sequences constituting the S-PSS are mapped from low to high in the frequency domain in one of the symbols for S-PSS, and from high to low in the frequency domain in another symbol for S-PSS.

[0237] In a sixth example of this approach, when there are many symbols mapped for S-PSS within an S-SSB, the set of sequences constituting the S-PSS with different symbols is identical and is mapped to the symbols for S-PSS in the same pattern (e.g., the symbols for S-PSS (excluding CP) are repeated).

[0238] In a seventh example of this approach, when there are many symbols mapped for S-PSS in the S-SSB, two sequences each for the S-PSS can be generated and mapped to all symbols for the S-PSS.

[0239] In another approach, the number of sequences constituting the S-PSS in each symbol is three (i.e., N_SPSS=3). In this approach, the sequences constituting the S-PSS can be used to identify the sidelink synchronization ID group index.

[0240] In the example for the three groups, it can be noted that different types of synchronization sources are considered, such as NR gNB, NR UE, or LTE eNB.

[0241] In one example, the number of sidelink synchronization IDs in each group is the same (e.g., for ease of S-SSS sequence design), and each group indicates a specific use case. In another example, the number of sidelink synchronization IDs in each group is the same (e.g., for ease of S-SSS sequence design), and two groups indicate a use case while the other groups indicate another use case (e.g., two groups are for in-gNB coverage and one group is for out-of-gNB coverage, or one group is for in-gNB / eNB coverage and two groups are for out-of-gNB / eNB coverage). In still another example, the number of sidelink synchronization IDs in each group is not the same (e.g., if the IDs of three groups indicate different use cases, the number of IDs of each group may not be the same for each use case).

[0242] In a first example of this approach, if there is a single symbol mapped for an S-PSS within an S-SSB, the set of sequences that make up the S-PSS is the set of sequences that make up the NR-PSS (e.g., the three sequence selections that make up the NR-PSS).

[0243] In a second example of this approach, if there is a single symbol mapped for an S-PSS within the S-SSB, none of the sequences that make up the S-PSS are from the set of sequences that make up the NR-PSS and are orthogonal or have low cross-correlation with all of the sequences that make up the NR-PSS.

[0244] In a third example of this approach, when there are many symbols mapped for S-PSS in the S-SSB, the sets of sequences constituting the S-PSS for different symbols are different, and the sets of sequences constituting the S-PSS for different symbols are orthogonal or have low cross-correlation across the sets. For example, one set of sequences constituting the S-PSS for some symbols is from the set of sequences constituting the NR-PSS (e.g., three sequence selections constituting the NR-PSS), and the remaining set of sequences is not from the set of sequences constituting the NR-PSS, but is orthogonal or has low cross-correlation with the set of sequences constituting the NR-PSS.

[0245] In a fourth example of this approach, if there are many symbols mapped for the S-PSS in the S-SSB, the sets of sequences constituting the S-PSS on different symbols are different and the sets of sequences constituting the S-PSS on different symbols are orthogonal or have low cross-correlation across the sets, e.g., none of the sequences constituting the S-PSS are from the set of sequences constituting the NR-PSS, and are orthogonal or have low cross-correlation with all the sequences constituting the NR-PSS.

[0246] In a fifth example of this approach, when there are many symbols mapped for S-PSS in an S-SSB, the set of sequences constituting the S-PSS in different symbols is the same, but is mapped to different patterns for the symbols for S-PSS, for example, the sequences constituting the S-PSS are mapped from low to high in the frequency domain in one of the symbols for S-PSS, and from high to low in the frequency domain in another symbol for S-PSS.

[0247] In a sixth example of this approach, when there are many symbols mapped for S-PSS within an S-SSB, the set of sequences constituting the S-PSS with different symbols is identical and is mapped to the symbols for S-PSS in the same pattern (e.g., the symbols for S-PSS (excluding CP) are repeated).

[0248] In a seventh example of this approach, when there are many symbols mapped for S-PSS in the S-SSB, three sequences each for the S-PSS can be generated and mapped to all symbols for the S-PSS.

[0249] Some examples of sequences that make up the S-PSS are described in detail below, where the sequence design reflects the above approach in this embodiment. There may be many instances used simultaneously (e.g., one instance mapped for one symbol for the S-PSS and another instance mapped for another symbol for the S-PSS).

[0250] In one example III-1, a sequence of symbols d_SPSS(n) for S-PSS is defined by a BPSK modulated M-sequence of length 127, given by d_SPSS(n)=1-2*x(m), m=(n+43*N_GID^SL) mod 127, 0≦n<127, where x(m) is an M-sequence with generator polynomial g(x)=x^7+x^4+1, i.e., x(i+7)=(x(i+4)+x(i)) mod 2, for i=0,1,...,119, and the initial condition for x(m) is given by x(6:0)=[1110110].

[0251] In one aspect, if the number of sequences for S-PSS in a symbol is 1, then the SL synchronization ID group index N_GID^SL=0.

[0252] In another aspect, if the number of sequences for S-PSS in a symbol is two, the SL synchronization ID group index N_GID^SL is 0 or 1.

[0253] In another aspect, if the number of sequences for S-PSS in a symbol is three, the SL synchronization ID group index N_GID^SL is 0, 1, or 2.

[0254] As an example of III-2, a sequence of symbols d_SPSS(n) for an S-PSS is defined by a BPSK modulated M-sequence of length 127 and is given by d_SPSS(n)=1-2*x(m), m=(n+43*N_GID^SL+K_1) mod 127, 0≦n<127, where x(m) is an M-sequence with generator polynomial g(x)=x^7+x^4+1, i.e., x(i+7)=(x(i+4)+x(i)) mod 2 (i=0,1,...,119), and the initial condition for x(m) is given by x(6:0)=[1110110], and K_1 is a predefined integer other than 0, 43 or 86.

[0255] In one aspect, if the number of sequences for S-PSS in a symbol is 1, then the SL synchronization ID group index N_GID^SL=0.

[0256] In another aspect, if the number of sequences for S-PSS in a symbol is two, the SL synchronization ID group index N_GID^SL is 0 or 1.

[0257] In another aspect, if the number of sequences for S-PSS in a symbol is three, the SL synchronization ID group index N_GID^SL is 0, 1, or 2.

[0258] In one subexample, if within an S-SSB, a sequence of symbols for the S-PSS is different from a sequence of symbols for the S-PSS of another symbol for the S-PSS, K_1 can be selected to be different for the two symbols, for example, K_1=21 for one symbol for the S-PSS and K_1=64 for the other symbol for the S-PSS, or K_1=22 for one symbol for the S-PSS and K_1=65 for the other symbol for the S-PSS.

[0259] 18 is a diagram illustrating example PAPR values ​​of an S-PSS sequence 1800 according to an embodiment of the present disclosure. The embodiment of the PAPR values ​​of the S-PSS sequence 1800 shown in FIG. 18 is for illustration purposes only. FIG. 18 does not limit the scope of the present disclosure to any particular implementation.

[0260] As another subexample, K_1 can be selected to minimize the PAPR value of the S-PSS sequence, for example, K_1=63 (eg, according to FIG. 18).

[0261] In yet another subexample, K_1 can be selected to have the maximum distance (e.g., 0, 43, and 86) from the cyclic shifts used in NR-PSS, e.g., K_1=21 or K_1=22 or K_1=64, or K_1=65.

[0262] As an example of III-3, a sequence of symbols d_SPSS(n) for an S-PSS is defined by a BPSK modulated M-sequence of length 127, given by d_SPSS(n)=1-2*x(m), m=(n+K_1)mod127, 0≦n<127, where x(m) is an M-sequence with a generator polynomial given by one of the examples in Table 3, e.g., g(x)=x^7+x+1 or g(x)=x^7+x^3+1, with an appropriate initial condition (e.g., x(6:0)=[1110110] or [0000001]); K_1 is an integer that can vary depending on the SL synchronization ID group index N_GID^SL.

[0263] 19 is a diagram illustrating another example PAPR value of an S-PSS sequence 1900 according to an embodiment of the present disclosure. The embodiment of the PAPR value of the S-PSS sequence 1900 shown in FIG. 19 is for illustration purposes only. FIG. 19 does not limit the scope of the present disclosure to any particular implementation.

[0264] 20 is a diagram illustrating another example PAPR value of an S-PSS sequence 2000 according to an embodiment of the present disclosure. The embodiment of the PAPR value of the S-PSS sequence 2000 shown in FIG. 20 is for illustration purposes only. FIG. 20 does not limit the scope of the present disclosure to any particular implementation.

[0265] In one aspect, if the number of sequences for S-PSS in a symbol is one, then the SL synchronization ID group index N_GID^SL=0. Then, K_1 can be a constant integer predefined for this aspect. In one consideration for this aspect, K_1 can be selected as 0 (no cyclic shift for a single sequence). In another consideration for this aspect, K_1 can be selected to minimize the PAPR value of the S-PSS sequence, for example, K_1=72 (e.g., according to FIG. 19) when the generator uses g(x)=x^7+x+1, or K_1=123 (e.g., according to FIG. 20) when the generator uses g(x)=x^7+x^3+1. Among other considerations, K_1 may be selected to have the greatest distance from the cyclic shifts used in NR-PSS (e.g., 0, 43, and 86), e.g., K_1=21, or K_1=22, or K_1=64, or K_1=65.

[0321] In another aspect, when the number of sequences for S-PSS in a symbol is two, the SL synchronization ID group index N_GID^SL is 0 or 1. Then, K_1 takes one of two predefined candidate integer values ​​depending on the value of N_GID^SL. In one consideration for this aspect, K_1 can be selected to minimize the PAPR value of the S-PSS sequence, for example, K_1=72 for N_GID^SL=0 and K_1=102 for N_GID^SL=1 when the generator uses g(x)=x^7+x+1 (e.g., according to FIG. 19), or K_1=55 for N_GID^SL=0 and K_1=123 for N_GID^SL=1 when the generator uses g(x)=x^7+x^3+1 (e.g., according to FIG. 20). In other considerations, K_1 may be selected to have the greatest distance from the cyclic shifts used for NR-PSS (e.g., 0, 43, and 86), e.g., for N_GID^SL=0, K_1=21, and for N_GID^SL=1, K_1=65. In still other considerations, K_1 is of the form K_1=N_GID^SL*64+K_2, where K_2 is a predefined integer, e.g., K_2=0 or K_2=32. In still other considerations, K_1 is of the form K_1=N_GID^SL*43+K_2, where K_2 is a predefined integer, e.g., K_2=0, or K_2=21, or K_2=22.

[0266] In yet another aspect, if the number of sequences for S-PSS in a symbol is 3, the SL synchronization ID group index N_GID^SL is 0 or 1 or 2. In one consideration for this aspect, K_1 can be selected to minimize the PAPR value of the S-PSS sequence. In another consideration, K_1 is of the form K_1=N_GID^SL*43+K_2, where K_2 is a predefined integer, for example, K_2=0, or K_2=21, or K_2=22.

[0267] As one subexample, if a sequence of symbols for an S-PSS in an S-SSB is different from a sequence of symbols for an S-PSS in another S-PSS, g(x) may be selected to be different for the two symbols, e.g., g(x)=x^7+x+1 for one symbol for the S-PSS and g(x)=x^7+x^3+1 for the other symbol for the S-PSS.

[0268] [Table 3]

[0269] In the example of III-4, the sequence of symbols d_SPSS(n) for the S-PSS is defined by a BPSK modulated M-sequence of length 255, given by d_SPSS(n)=1-2*x(m), m=(n+K_1*N_GID^SL)mod255, 0≦n<255, where x(m) is an M-sequence with a generator polynomial given by one of the examples in Table 4, e.g., g(x)=x^8+x^7+x^6+x+1, with appropriate initial conditions (e.g., x(7:0)=[10000000] or [00000001]); K_1 is a predefined constant integer, e.g., for N_SPSS>1,

number

[0270] In one aspect, if the number of sequences for S-PSS in a symbol is 1, then the SL synchronization ID group index N_GID^SL=0.

[0271] In another aspect, if the number of sequences for the S-PSS in a symbol is two, the SL synchronization ID group index N_GID^SL is 0 or 1.

[0272] In another aspect, if the number of sequences for S-PSS in a symbol is three, the SL synchronization ID group index N_GID^SL is 0, 1, or 2.

[0273] [Table 4]

[0274] As an example of III-5: a sequence of symbols d_SPSS(n) for an S-PSS is defined by a BPSK modulated M-sequence of length 127 and is given by d_SPSS(n)=1-2*x(m), m=(n+K_1)mod127, 0≦n<127, where x(m) is an M-sequence with generator polynomial g(x)=x^7+x^4+1, i.e., x(i+7)=(x(i+4)+x(i))mod2(i=0,1,...,119), and the initial condition of x(m) is given by x(6:0)=[1110110], where K_1 is an integer other than 0, 43 or 86 and can vary depending on the SL synchronization ID group index N_GID^SL.

[0275] In one aspect, if the number of sequences for S-PSS in a symbol is 1, then the SL synchronization ID group index N_GID^SL = 0. In one consideration, K_1 may be selected to minimize the PAPR value of the S-PSS sequence, e.g., K_1 = 63 (e.g., according to FIG. 18). In another consideration, K_1 may be selected to have the maximum distance from the cyclic shifts (e.g., 0, 43, and 86) used for NR-PSS, e.g., K_1 = 21, or K_1 = 22, or K_1 = 64, or K_1 = 65.

[0276] In another aspect, when the number of sequences for S-PSS in a symbol is 2, the SL synchronization ID group index N_GID^SL is 0 or 1. In one consideration, K_1 may be selected to minimize the PAPR value of the S-PSS sequence, e.g., K_1=20 for N_GID^SL=0 and K_1=63 for N_GID^SL=1 (e.g., according to FIG. 18). In another consideration, K_1 may be selected to have a maximum distance from the cyclic shifts (e.g., 0, 43, and 86) used for NR-PSS, e.g., K_1=21 for N_GID^SL=0 and K_1=65 for N_GID^SL=1, or K_1=22 for N_GID^SL=0 and K_1=64 for N_GID^SL=1.

[0277] In another aspect, when the number of sequences for S-PSS in a symbol is 3, the SL synchronization ID group index N_GID^SL is 0 or 1 or 2. In one consideration, K_1 can be selected to minimize the PAPR value of the S-PSS sequence, for example, K_1=20 for N_GID^SL=0, K_1=63 for N_GID^SL=1, and K_1=100 for N_GID^SL=2 (e.g., according to FIG. 18). Among other considerations, K_1 can be selected to have the greatest distance from the cyclic shifts used for NR-PSS (e.g., 0, 43, and 86), e.g., K_1=21 for N_GID^SL=0, K_1=65 for N_GID^SL=1, and K_1=108 for N_GID^SL=2, or K_1=22 for N_GID^SL=0, K_1=64 for N_GID^SL=1, and K_1=107 for N_GID^SL=2.

[0278] In one embodiment, the design of the S-SSS sequence can be combined with other example embodiments of the present disclosure.

[0279] In one approach, the number of sequences constituting the S-SSS in each symbol is equal to the number of sidelink synchronization IDs (e.g., every sidelink synchronization ID is mapped to a unique sequence for the S-SSS in each symbol mapped for the S-SSS).

[0280] In a first example of this approach, if there is a single symbol mapped for S-SSS within the S-SSB, then if the number of sequences for the S-SSS is 1008 or less, then the set of sequences that make up the S-SSS is a subset of the sequences that make up the NR-SSS.

[0281] In a second example of this approach, when there is a single symbol mapped for S-SSS within the S-SSB, the set of sequences constituting the S-SSS differs from the set of sequences constituting the NR-SSS, for example by using at least one different M-sequence generating polynomial and / or cyclic shift.

[0282] In a third example of this approach, when there are many symbols mapped for S-SSS in an S-SSB, the sequences constituting the S-SSS in different symbols may be the same, and may be mapped to different patterns for the symbols for S-SSS. For example, the sequences constituting the S-SSS may be mapped from low to high in the frequency domain in one of the symbols for S-SSS, and from high to low in the frequency domain in another symbol for S-SSS.

[0283] In a fourth example of this approach, when there are many symbols mapped for S-SSS within an S-SSB, the sequence constituting the S-SSS with different symbols only needs to be identical, and they can be mapped to symbols for S-SSS in the same pattern (e.g., the symbols for S-SSS (excluding CP) are repeated).

[0284] In a fifth example of this approach, when there are many symbols mapped for S-SSS in an S-SSB, the sequence constituting the S-SSS in one symbol may be different from the sequence constituting the S-SSS in another symbol, and may be mapped to the symbols for S-SSS in the same pattern (e.g., a time-frequency domain mapping procedure), where each symbol sequence may use the sequence in the first or second example of this approach. For example, one way to achieve a set of different sequences in different symbols is to use a cover code (i.e., the sequence constituting the S-SSS in one symbol may be the sequence constituting the S-SSS in another symbol with a cover code), and another way to achieve a set of different sequences in different symbols is to use different generator polynomials and / or different cyclic shifts.

[0285] A sixth example of this approach is that when there are many symbols mapped for S-SSS in an S-SSB, a sequence constituting S-SSS in one symbol may be different from a sequence constituting S-SSS in other symbols, and may be mapped to a different pattern for the symbols for S-SSS, where the sequence of each symbol may use the sequence of the first or second example of this approach. For example, the sequence constituting S-SSS may be mapped from low to high in the frequency domain for some symbols for S-SSS, and from high to low in the frequency domain for other symbols for S-SSS. For example, one way to achieve a set of different sequences for different symbols is to use a cover code (i.e., a sequence constituting S-SSS in one symbol may be a sequence constituting S-SSS in other symbols with a cover code), and another way to achieve a set of different sequences for different symbols is to use different generator polynomials and / or different cyclic shifts.

[0286] In a seventh example of this approach, if there are many symbols mapped for S-SSS in the S-SSB, each sequence for the S-SSS can be generated and mapped to all symbols for the S-SSS.

[0287] Some examples of sequences that make up S-SSS are described in detail below, where the sequence design reflects the above approach in this embodiment. There may be many instances used simultaneously (e.g., one instance mapped for one symbol for S-SSS and another instance mapped for another symbol for S-SSS).

[0288] In the example of IV-1, the construction method is the same as NR-SSS, and therefore the S-SSS set is the same subset as the NR-SSS set. For example, the sequence of symbols d_SSSS(n) for S-SSS is defined as a BPSK-modulated Gold-sequence of length 127,

number

[0289] As an example, N_SPSS=1, N_GID^SL=0, and N_IDinG^SL is the same as N_ID^SL.

[0290] In another example, when N_SPSS=2, N_GID^SL=0 or 1.

[0291] In the example of IV-2, the sequence of symbols d_SSSS(n) for S-SSS is defined by a BPSK modulated Gold-sequence of length 127,

number

[0292] As an example, when N_SPSS=1, N_GID^SL=0, N_IDinG^SL is the same as N_ID^SL, and N_NID^SL is 336, then K_2=15, K_3=112, and K_4=0.

[0293] As another example, when N_SPSS=1, N_GID^SL=0, N_IDinG^SL is the same as N_ID^SL, and N_NID^SL is 336, then K_2=45, K_3=112, and K_4=0.

[0294] As another example, when N_SPSS=1, N_GID^SL=0, N_IDinG^SL is the same as N_ID^SL, and N_NID^SL is 504, K_2=15, K_3=112, and K_4=0.

[0295] As another example, when N_SPSS=1, N_GID^SL=0, N_IDinG^SL is the same as N_ID^SL, and N_NID^SL is 504, K_2=45, K_3=112, and K_4=0.

[0296] As another example, when N_SPSS=1, N_GID^SL=0, N_IDinG^SL is the same as N_ID^SL, and N_NID^SL is 672, then K_2=15, K_3=112, and K_4=0.

[0297] As another example, when N_SPSS=1, N_GID^SL=0, N_IDinG^SL is the same as N_ID^SL, and N_NID^SL is 1008, K_2=15, K_3=126, and K_4=0.

[0298] In yet another specific example, when N_SPSS=1, N_GID^SL=0, N_IDinG^SL is the same as N_ID^SL, and N_NID^SL is 1008, then K_2=15, K_3=112, and K_4=0.

[0299] As another example, when N_SPSS=2, N_GID^SL=0 or 1, and N_NID^SL is 672, K_2=15, K_3=112, and K_4=5.

[0300] As another example, when N_SPSS=2, N_GID^SL=0 or 1, and N_NID^SL is 336, K_2=15, K_3=84, and K_4=5.

[0301] As another example, when N_SPSS=2, N_GID^SL=0 or 1, and N_NID^SL is 336, K_2=15, K_3=56, and K_4=5.

[0302] As another example, when N_SPSS=3, N_GID^SL=0 or 1 or 2, and N_NID^SL is 672, K_2=15, K_3=112, and K_4=5.

[0303] As another example, when N_SPSS=3, N_GID^SL=0 or 1 or 2, and N_NID^SL is 672, K_2=15, K_3=75, and K_4=5.

[0304] As another example, when N_SPSS=3, N_GID^SL=0 or 1 or 2, and N_NID^SL is 336, K_2=15, K_3=112, and K_4=5.

[0305] In the example of IV-3, the sequence of symbols d_SSSS(n) for S-SSS is defined by a BPSK modulated Gold-sequence of length 127,

number

[0306] As an example, when N_SPSS=1, N_GID^SL=0, and N_IDinG^SL is the same as N_ID^SL, if N_NID^SL is 336, 504, or 672, then K_2=15, K_3=112, and K_4=0.

[0307] As another example, when N_SPSS=2 and N_GID^SL=0 or 1, if N_NID^SL is 672, then K_2=15, K_3=112, and K_4=5.

[0308] As another example, when N_SPSS=2, N_GID^SL=0 or 1, and N_NID^SL is 336, K_2=15, K_3=84, and K_4=5.

[0309] As another example, when N_SPSS=2, N_GID^SL=0 or 1, and N_NID^SL is 336, K_2=15, K_3=56, and K_4=5.

[0310] In yet another specific example, when N_SPSS=3 and N_GID^SL=0 or 1 or 2, if N_NID^SL is 672, then K_2=15, K_3=112, and K_4=5.

[0311] As another example, when N_SPSS=3, N_GID^SL=0 or 1 or 2, and N_NID^SL is 672, K_2=15, K_3=75, and K_4=5.

[0312] As another example, when N_SPSS=3, N_GID^SL=0 or 1 or 2, and N_NID^SL is 336, K_2=15, K_3=112, and K_4=5.

[0313] In the example of IV-4, the sequence of symbols d_SSSS(n) for S-SSS is defined by a BPSK modulated Gold-sequence of length 255,

number

[0314] As an example, when N_SPSS=1, N_GID^SL=0, and N_IDinG^SL is the same as N_ID^SL, if N_NID^SL is 336, 504, or 672, then K_2=30, K_3=224, and K_4=0.

[0315] As another example, when N_SPSS=2 and N_GID^SL=0 or 1, if N_NID^SL is 672, then K_2=30, K_3=224, and K_4=10.

[0316] As another example, when N_SPSS=2, N_GID^SL=0 or 1, and N_NID^SL is 336, K_2=30, K_3=168, and K_4=10.

[0317] As another example, when N_SPSS=3, N_GID^SL=0 or 1 or 2, and N_NID^SL is 672, K_2=30, K_3=224, and K_4=10.

[0318] As another example, when N_SPSS=3, N_GID^SL=0 or 1 or 2, and N_NID^SL is 336, K_2=30, K_3=112, and K_4=10.

[0319] In the example of IV-5, the sequence of symbols d_SSSS(n) for S-SSS is defined by a BPSK modulated Gold-sequence of length 127,

number

[0320] As an example, when N_SPSS=1, N_GID^SL=0, N_IDinG^SL is the same as N_ID^SL, and N_NID^SL is 336, then K_2=15, K_3=112, K_4=0, and K_5=3.

[0321] As another example, when N_SPSS=3, N_GID^SL=0 or 1 or 2, if N_NID^SL is 336, then K_2=15, K_3=112, K_4=0, and K_5=3.

[0322] As another example, when N_SPSS=1, N_GID^SL=0, N_IDinG^SL is the same as N_ID^SL, and N_NID^SL is 504, K_2=15, K_3=112, K_4=0, and K_5=2.

[0323] As another example, when N_SPSS=2, N_GID^SL=0 or 1, and N_NID^SL is 504, K_2=15, K_3=112, K_4=0, and K_5=2.

[0324] In the example of IV-6, the construction method is the same as NR-SSS, and therefore the S-SSS set is the same subset as the NR-SSS set. For example, the sequence of symbols d_SSSS(n) for S-SSS is defined by a BPSK-modulated Gold-sequence of length 127,

number

[0325] In one embodiment, there is a single S-PSS sequence (e.g., N_SPSS=1) and a single SL synchronization ID group (e.g., N_G=1). In this embodiment, the number of SL synchronization IDs is 336, N_GID^SL=0, and N_IDinG^SL may be the same as N_ID^SL. In an example of this embodiment, K_1=0 and the set of S-SSS sequences is a subset of the NR-SSS sequences. In another example of this embodiment, the set of S-SSS sequences is a subset of the NR-SSS sequences with a cyclic shift and K_1>0 (e.g., K_1=2 or K_1=3).

[0326] In another embodiment, there is a single S-PSS sequence (e.g., N_SPSS=1) and there are two SL synchronization ID groups (e.g., N_G=2), e.g., the NR-SL_PSS sequence does not convey a group ID. In this embodiment, the number of SL synchronization IDs may be 672 and N_GID^SL=0 or 1. In an example of this embodiment, K_1=0 and the set of S-SSS sequences is a subset of the NR-SSS sequences. In yet another example of this embodiment, the set of S-SSS sequences is a subset of the NR-SSS sequences with a cyclic shift and K_1>0 (e.g., K_1=2 or K_1=3).

[0327] In yet another embodiment, there are two S-PSS sequences (e.g., N_SPSS=2) and there are two SL synchronization ID groups (e.g., N_G=2), e.g., each S-PSS sequence indicates one of the SL synchronization ID groups. In this embodiment, the number of SL synchronization IDs is 672, and N_GID^SL=0 or 1. In an example of this embodiment, K_1=0, and the set of S-SSS sequences is a subset of the NR-SSS sequences. In another example of this embodiment, the set of S-SSS sequences is a subset of the NR-SSS sequences with a cyclic shift, and K_1>0 (e.g., K_1=7 or K_1=8).

[0328] In one embodiment for PSBCH content components, one or more access schemes may be simultaneously supported for configuring the PSBCH content, for example, some access schemes or access scheme instances may only be supported for a range of carrier frequencies.

[0329] In the first approach, the PSBCH content may include time domain information indicating where the PSBCH of the S-SSB is located, where the time domain information may include at least one of DFN-level information (e.g., DFN or part of DFN), half-frame-level information (e.g., half-frame indicator), slot-level information (e.g., slot index within a frame or half-frame or predefined time duration), or S-SSB index (e.g., two or more S-SSBs in a slot for L_SSB>1). Upon detecting the system information included in the PSBCH content, the UE may determine a symbol index within the slot using a predefined S-SSB mapping of the slot, where the S-SSB index may be used to determine a symbol index within the slot if one slot includes two S-SSBs, and the UE may determine a slot index within the frame and DFN using the system information included in the PSBCH content.

[0330] Figure 21 is a diagram illustrating an example time domain mapping of an S-SSB burst set 2100 according to an embodiment of the present disclosure. The embodiment of the time domain mapping of the S-SSB burst set 2100 shown in Figure 21 is for illustration only. Figure 21 does not limit the scope of the present disclosure to any particular implementation.

[0331] In a first example of the first approach, an S-SSB burst set contains only a single S-SSB (i.e., L_SSB=1), e.g., the S-SSB operates in a single beam mode, and the location of the slot containing the S-SSB is fixed by specification, e.g., fixed as a specific slot (e.g., the first slot) within the period of the S-SSB burst set (e.g., 2101 in FIG. 21), or fixed as a specific slot (e.g., the first slot) within the DFN, or fixed as a specific slot (e.g., the first slot) within a half frame.

[0332] In one subexample, if the period of an S-SSB burst set is 2^n frames (n≧0) and the position of the slot containing the S-SSB is fixed at a particular slot (e.g., the first slot) within the period of the S-SSB burst set, the (10-n) MSB (e.g., a (10-n) bit field) of the DFN in which the PSBCH of that S-SSB is located can be indicated in the PSBCH content.

[0333] In another subexample, if the period of an S-SSB burst set is 2^n frames (n≧0) and the position of the slot containing the S-SSB is fixed at a specific slot (e.g., the first slot) within the DFN, the DFN in which the PSBCH of that S-SSB is located (e.g., a 10-bit field having a value from 0 to 1023) can be indicated in the PSBCH content.

[0334] In yet another subexample, if the position of the slot containing the S-SSB is fixed to a specific slot (e.g., the first slot) within a half-frame, the DFN in which the PSBCH of that S-SSB is located (e.g., a 10-bit field having a value from 0 to 1023) and the half-frame number (e.g., a 1-bit field indicating the first or second half-frame within a frame) can be indicated in the PSBCH content.

[0335] In a second example of the first approach, an S-SSB burst set contains only a single S-SSB (i.e., L_SSB=1), e.g., the S-SSB operates in a single beam mode, and the location of the slot containing the S-SSB is variable and indicated (e.g., 2102 in FIG. 21).

[0336] In one subexample, the DFN in which the PSBCH of the S-SSB is located (e.g., a 10-bit field having a value from 0 to 1023) and a slot index within the indicated DFN may be indicated in the PSBCH content, where the slot index within the DFN may be represented as a (k+4)-bit field having a value from 0 to M-1, where M=10*2^k, and 15*2^k is the largest SCS supported for the NR sidelink (e.g., k=4) or supported for the carrier frequency range of the NR sidelink (e.g., k=4 for above 6 GHz, k=2 for below 6 GHz).

[0337] 22 is a diagram illustrating another example time domain mapping of an S-SSB burst set 2200 according to an embodiment of the present disclosure. The embodiment of the time domain mapping of an S-SSB burst set 2200 shown in FIG. 22 is for illustration only. FIG. 22 does not limit the scope of the present disclosure to any particular implementation.

[0338] In a third example of the first approach, one S-SSB burst set includes multiple S-SSBs (i.e., L_SSB>1), e.g., the S-SSBs may operate in a multi-beam and / or repetitive manner, the slots including the S-SSBs are contiguous, and the location of the slots including the S-SSBs is fixed by specification, e.g., fixed by starting at a specific slot (e.g., the first slot) within the period of the S-SSB burst set (e.g., 2201 in FIG. 22) or fixed by starting at a specific slot (e.g., the first slot) within a half frame.

[0339] In one subexample, if the period of an S-SSB burst set is 2^n frames (n≧0) and the position of the slot containing the S-SSB is fixed to start from a particular slot (e.g., the first slot) within the period of the S-SSB burst set, the (10-n)MSB (e.g., a (10-n) bit field) of the DFN in which the PSBCH of that S-SSB is located and the S-SSB index (or the MSB of the S-SSB index) can be indicated in the PSBCH content.

[0340] In another subexample, if the period of the S-SSB burst set is 2^n frames (n≧0) and the position of the slot containing the S-SSB is fixed to start from a particular slot (e.g., the first slot) within the period of the S-SSB burst set, the (10-n) MSB (e.g., a (10-n) bit field) of the DFN in which the PSBCH of that S-SSB is located can be indicated in the PSBCH content, and the S-SSB index can be indicated using other signals / channels of the PSBCH, such as the DMRS of the PSBCH.

[0341] In another subexample, if the period of the S-SSB burst set is 2^n frames (n≧0) and the position of the slot containing the S-SSB is fixed starting from a particular slot (e.g., the first slot) within the DFN, the DFN (e.g., a 10-bit field having a value from 0 to 1023) in which the PSBCH of that S-SSB is located and the S-SSB index can be indicated in the PSBCH content.

[0342] As another subexample, if the period of an S-SSB burst set is 2^n frames (n≧0) and the position of the slot containing the S-SSB is fixed by starting from a particular slot (e.g., the first slot) within the DFN, the DFN in which the PSBCH of that S-SSB is located (e.g., a 10-bit field having a value from 0 to 1023) can be indicated in the PSBCH content, and the S-SSB index can be indicated using other signals / channels of the PSBCH, such as the DMRS of the PSBCH.

[0343] As another subexample, if the position of the slot containing the S-SSB is fixed by starting at a particular slot (e.g., the first slot) within a half-frame, the DFN in which the PSBCH for that S-SSB is located (e.g., a 10-bit field having a value from 0 to 1023) and the half-frame number (e.g., a 1-bit field indicating the first or second half-frame within a frame) can be indicated in the PSBCH content.

[0344] As another subexample, if the position of a slot containing an S-SSB is fixed by starting at a particular slot (e.g., the first slot) within a half-frame, the DFN (e.g., a 10-bit field having a value from 0 to 1023) in which the PSBCH of that S-SSB is located and the half-frame number (e.g., a 1-bit field indicating the first or second half-frame within a frame) can be indicated in the PSBCH content, and the S-SSB index can be indicated using another signal / channel of the PSBCH, such as the DMRS of the PSBCH.

[0345] In a fourth example of the first approach, one S-SSB burst set includes multiple S-SSBs (i.e., L_SSB>1), e.g., the S-SSBs can operate in a multi-beam and / or repetitive manner, the slots including the S-SSBs are contiguous, and the starting positions of the slots including the S-SSBs are variable and indicated (e.g., 2202 in FIG. 22).

[0346] In one subexample, the DFN in which the first slot containing the S-SSB is located (e.g., a 10-bit field having a value from 0 to 1023) and a slot index within the indicated DFN may be indicated in the PSBCH content, where the slot index within the DFN may be represented as a (k+4)-bit field having a value from 0 to M-1, where M=10*2^k, and 15*2^k is the largest SCS supported for the NR sidelink (e.g., k=4) or supported for the carrier frequency range of the NR sidelink (e.g., k=4 for above 6 GHz, k=1 for below 6 GHz).

[0347] In another subexample, the DFN in which the first slot containing the S-SSB is located (e.g., a 10-bit field having a value from 0 to 1023) and a slot index within the indicated DFN may be indicated in the PSBCH content, where the slot index within the DFN may be represented as a (k+4)-bit field having a value from 0 to M-1, where M=10*2^k, where 15*2^k is the largest SCS supported for the NR sidelink (e.g., k=4) or supported for the carrier frequency range of the NR sidelink (e.g., k=4 for above 6 GHz, k=1 for below 6 GHz), and the S-SSB index is indicated using other signals / channels of the PSBCH, such as DMRS of the PSBCH.

[0348] 23 is a diagram illustrating another example time domain mapping of an S-SSB burst set 2300 according to an embodiment of the present disclosure. The embodiment of the time domain mapping of an S-SSB burst set 2300 shown in FIG. 23 is for illustration only. FIG. 23 does not limit the scope of the present disclosure to any particular implementation.

[0349] In a fifth example of the first approach, an S-SSB burst set includes multiple S-SSBs (i.e., L_SSB>1), for example, the S-SSBs may operate in a multi-beam and / or repetitive manner, the slots including the S-SSBs may be non-contiguous, the slots including the S-SSBs may be uniformly distributed at fixed intervals within the period of the S-SSB burst set, and the first slot including the S-SSB is fixed to a specification, for example, fixed by starting at a specific slot (e.g., the first slot) within the period of the S-SSB burst set (e.g., 2301 in FIG. 23), or fixed by starting at a specific slot (e.g., the first slot) within the DFN, or fixed by starting at a specific slot (e.g., the first slot) within a half frame. For example, the indices of slots containing S-SSBs within the period of an S-SSB burst set (or DFN or half-frame) may be given by #0, #(N / L_SSB), #2*(N / L_SSB), ..., #(L_SSB-1)*(N / L_SSB) if each slot contains a single S-SSB, and #0, #2*(N / L_SSB), #2*2*(N / L_SSB), ..., #2*(L_SSB / 2-1)*(N / L_SSB) if each slot contains two S-SSBs, where L_SSB is the maximum number of S-SSBs in the burst set determined per carrier frequency range, and N is the period of the S-SSB burst set (or DFN or half-frame) in terms of slots.

[0350] As one subexample, if the period of an S-SSB burst set is 2^n frames (n≧0) and the position of the slot containing the S-SSB is fixed starting from a particular slot (e.g., the first slot) within the period of the S-SSB burst set, the (10-n)MSB (e.g., a (10-n) bit field) of the DFN in which the PSBCH of the S-SSB is located and the S-SSB index (or the MSB of the S-SSB index) can be indicated in the PSBCH content.

[0351] As another subexample, if the period of an S-SSB burst set is 2^n frames (n≧0) and the position of the slot containing the S-SSB is fixed starting from a particular slot (e.g., the first slot) within the period of the S-SSB burst set, the (10-n) MSB (e.g., a (10-n) bit field) of the DFN in which the PSBCH of that S-SSB is located can be indicated in the PSBCH content, and the S-SSB index can be indicated using other signals / channels of the PSBCH, such as the DMRS of the PSBCH.

[0352] As another subexample, if the period of an S-SSB burst set is 2^n frames (n≧0) and the position of the slot containing the S-SSB is fixed starting from a particular slot (e.g., the first slot) within the DFN, the DFN (e.g., a 10-bit field having a value from 0 to 1023) in which the PSBCH of that S-SSB is located and the S-SSB index can be indicated in the PSBCH content.

[0353] As another subexample, if the period of an S-SSB burst set is 2^n frames (n≧0) and the position of the slot containing the S-SSB is fixed to start from a particular slot (e.g., the first slot) within the DFN, the DFN in which the PSBCH of that S-SSB is located (e.g., a 10-bit field having a value from 0 to 1023) can be indicated in the PSBCH content, and the S-SSB index can be indicated using other signals / channels of the PSBCH, such as the DMRS of the PSBCH.

[0354] As another subexample, if the position of the slot containing the S-SSB is fixed by starting at a particular slot (e.g., the first slot) within a half-frame, the DFN (e.g., a 10-bit field having a value from 0 to 1023) in which the PSBCH of that S-SSB is located, the half-frame number (e.g., a 1-bit field indicating the first or second half-frame within a frame), and the S-SSB index (or the MSB of the S-SSB index) can be indicated in the PSBCH content.

[0355] In yet another subexample, if the position of the slot containing the S-SSB is fixed by starting at a particular slot (e.g., the first slot) within a half-frame, the DFN (e.g., a 10-bit field having a value from 0 to 1023) in which the PSBCH of that S-SSB is located and the half-frame number (e.g., a 1-bit field indicating the first or second half-frame within a frame) can be indicated in the PSBCH content, and the S-SSB index can be indicated using another signal / channel of the PSBCH, such as the DMRS of the PSBCH.

[0356] In a sixth example of the first approach, an S-SSB burst set contains multiple S-SSBs (i.e., L_SSB>1), e.g., the S-SSBs operate in a multi-beam and / or repetitive manner, the slots containing the S-SSBs may be non-contiguous, the slots containing the S-SSBs are uniformly distributed at fixed intervals within the period of the S-SSB burst set, and the first slot containing the S-SSB is indicated as variable (e.g., 2302 in FIG. 23).

[0357] For example, the index of a slot containing an S-SSB within the period of an S-SSB burst set (or DFN or half-frame) may be given by #M, #M+(N / L_SSB), #M+2*(N / L_SSB), ..., #M+(L_SSB-1)*(N / L_SSB) if each slot contains a single S-SSB, and #M, #M+2*(N / L_SSB), #M+2*2*(N / L_SSB), ..., #M+2*(L_SSB / 2-1)*(N / L_SSB) if each slot contains two S-SSBs, where L_SSB is the maximum number of S-SSBs in the burst set determined per carrier frequency range, N is the period of the S-SSB burst set (or DFN or half-frame) in terms of slots, and M is the index of the first slot containing the indicated S-SSB.

[0358] As one subexample, the DFN in which the first slot containing the S-SSB is located (e.g., a 10-bit field having a value from 0 to 1023) and a slot index within the indicated DFN, and the S-SSB index (or the MSB of the S-SSB index) may be indicated in the PSBCH content, where the slot index within the DFN may be represented as a (k+4)-bit field having a value from 0 to M-1, where M=10*2^k, and 15*2^k is the largest SCS supported for the NR sidelink (e.g., k=4) or supported for the carrier frequency range of the NR sidelink (e.g., k=4 for above 6 GHz, k=1 for below 6 GHz).

[0359] As another subexample, the DFN in which the first slot containing the S-SSB is located (e.g., a 10-bit field having a value from 0 to 1023) and a slot index within the indicated DFN may be indicated in the PSBCH content, where the slot index within the DFN may be represented as a (k+4)-bit field having a value from 0 to M-1, where M=10*2^k, where 15*2^k is the largest SCS supported for the NR sidelink (e.g., k=4) or supported for the carrier frequency range of the NR sidelink (e.g., k=4 for above 6 GHz, k=1 for below 6 GHz), and the S-SSB index is indicated using other signals / channels of the PSBCH, such as DMRS of the PSBCH.

[0360] In a seventh example of the first approach, an S-SSB burst set includes multiple S-SSBs (i.e., L_SSB>1), e.g., the S-SSBs operate in a multi-beam and / or repetitive manner, the slots including the S-SSBs may be non-contiguous, the slots including the S-SSBs are uniformly distributed at fixed intervals within a subset of the period of the S-SSB burst set, and the first slot including the S-SSB is fixed to a specification, e.g., fixed by starting at a specific slot (e.g., the first slot) within the period of the S-SSB burst set (e.g., 2303 in FIG. 23), or fixed by starting at a specific slot (e.g., the first slot) within the DFN, or fixed by starting at a specific slot (e.g., the first slot) within a half-frame.

[0361] For example, the indices of slots containing S-SSBs within the period of an S-SSB burst set (or DFN or half-frame) may be given by #0, #(N / L), #2*(N / L), ..., #(L_SSB-1)*(N / L) if each slot contains a single S-SSB, or #0, #2*(N / L), #2*2*(N / L), ..., #2*(L_SSB / 2-1)*(N / L) if each slot contains two S-SSBs, where L_SSB is the maximum number of S-SSBs in the burst set determined per carrier frequency range, N is the period of the S-SSB burst set (or DFN or half-frame) in terms of slots, and L is a predefined integer such that L>L_SSB.

[0362] In one subexample, if the period of an S-SSB burst set is 2^n frames (n≧0) and the position of the slot containing the S-SSB is fixed starting from a particular slot (e.g., the first slot) within the period of the S-SSB burst set, the (10-n)MSB (e.g., a (10-n) bit field) of the DFN in which the PSBCH of the S-SSB is located and the S-SSB index (or the MSB of the S-SSB index) can be indicated in the PSBCH content.

[0363] As one subexample, if the period of an S-SSB burst set is 2^n frames (n≧0) and the position of the slot containing the S-SSB is fixed starting from a particular slot (e.g., the first slot) within the period of the S-SSB burst set, then the (10-n) MSB (e.g., a (10-n) bit field) of the DFN in which the PSBCH of that S-SSB is located can be indicated in the PSBCH content, and the S-SSB index can be indicated using other signals / channels of the PSBCH, such as the DMRS of the PSBCH.

[0364] As another subexample, if the period of an S-SSB burst set is 2^n frames (n≧0) and the position of the slot containing the S-SSB is fixed starting from a particular slot (e.g., the first slot) within the DFN, the DFN (e.g., a 10-bit field having a value from 0 to 1023) in which the PSBCH of that S-SSB is located and the S-SSB index can be indicated in the PSBCH content.

[0365] In yet another subexample, if the period of the S-SSB burst set is 2^n frames (n≧0) and the position of the slot containing the S-SSB is fixed to start from a particular slot (e.g., the first slot) within the DFN, the DFN in which the PSBCH of that S-SSB is located (e.g., a 10-bit field having a value from 0 to 1023) can be indicated in the PSBCH content, and the S-SSB index can be indicated using other signals / channels of the PSBCH, such as the DMRS of the PSBCH.

[0366] As another subexample, if the position of the slot containing the S-SSB is fixed by starting at a particular slot (e.g., the first slot) within a half-frame, the DFN (e.g., a 10-bit field having a value from 0 to 1023) in which the PSBCH of that S-SSB is located, the half-frame number (e.g., a 1-bit field indicating the first or second half-frame within a frame), and the S-SSB index (or the MSB of the S-SSB index) can be indicated in the PSBCH content.

[0367] As another subexample, if the position of a slot containing an S-SSB is fixed by starting at a particular slot (e.g., the first slot) within a half-frame, the DFN (e.g., a 10-bit field having a value from 0 to 1023) in which the PSBCH of that S-SSB is located and the half-frame number (e.g., a 1-bit field indicating the first or second half-frame within a frame) can be indicated in the PSBCH content, and the S-SSB index can be indicated using another signal / channel of the PSBCH, such as the DMRS of the PSBCH.

[0368] In an eighth example of the first approach, an S-SSB burst set contains multiple S-SSBs (i.e., L_SSB>1), e.g., the S-SSBs operate in a multi-beam and / or repetitive manner, the slots containing the S-SSBs may be non-contiguous, the slots containing the S-SSBs are uniformly distributed at fixed intervals within a subset of the period of the S-SSB burst set, and the first slot containing the S-SSB is indicated as variable (e.g., 2304 in FIG. 23). For example, the index of a slot containing an S-SSB within the period of an S-SSB burst set (or DFN or half-frame) may be given by #M, #M+(N / L), #M+2*(N / L), ..., #M+(L_SSB-1)*(N / L) if each slot contains a single S-SSB, and #M, #M+2*(N / L), #M+2*2*(N / L), ..., #M+2*(L_SSB / 2-1)*(N / L) if each slot contains two S-SSBs, where L_SSB is the maximum number of S-SSBs in the burst set determined per carrier frequency range, N is the period of the S-SSB burst set (or DFN or half-frame) in terms of slots, M is the index of the first slot containing the indicated S-SSB, and L is a predefined integer such that L>L_SSB.

[0369] In one subexample, the DFN in which the first slot containing the S-SSB is located (e.g., a 10-bit field having a value from 0 to 1023) and a slot index within the indicated DFN, and the S-SSB index (or the MSB of the S-SSB index) may be indicated in the PSBCH content, where the slot index within the DFN may be represented as a (k+4)-bit field having a value from 0 to M-1, where M=10*2^k, and 15*2^k is the largest SCS supported for the NR sidelink (e.g., k=4) or supported for the carrier frequency range of the NR sidelink (e.g., k=4 for above 6 GHz, k=1 for below 6 GHz).

[0370] In another subexample, the DFN in which the first slot containing the S-SSB is located (e.g., a 10-bit field having a value from 0 to 1023) and a slot index within the indicated DFN may be indicated in the PSBCH content, where the slot index within the DFN may be represented as a (k+4)-bit field having a value from 0 to M-1, where M=10*2^k, where 15*2^k is the largest SCS supported for the NR sidelink (e.g., k=4) or supported for the carrier frequency range of the NR sidelink (e.g., k=4 for above 6 GHz, k=1 for below 6 GHz), and the S-SSB index is indicated using other signals / channels of the PSBCH, such as DMRS of the PSBCH.

[0371] 24 is a diagram illustrating another example time domain mapping of an S-SSB burst set 2400 according to an embodiment of the present disclosure. The embodiment of the time domain mapping of an S-SSB burst set 2400 shown in FIG. 24 is for illustration only. FIG. 24 does not limit the scope of the present disclosure to any particular implementation.

[0372] In a ninth example of the first approach, an S-SSB burst set includes multiple S-SSBs (i.e., L_SSB>1), e.g., the S-SSBs operate in a multi-beam and / or repetition manner, the slots including the S-SSBs may be non-contiguous, and each slot including an S-SSB may be constrained within a predefined slot group, where the slot groups have the same number of slots and are configured with the period of the SSB burst set (e.g., 2401 in FIG. 24). For example, the period of the S-SSB burst set is divided into L_SSB slot groups if each slot includes a single S-SSB, and into L_SSB / 2 slot groups if each slot includes two S-SSBs, where each group has the same number of slots and each group includes one slot including an S-SSB, and the position of the slot including the S-SSB may be variable and indicated within the group. In this example, if each slot contains a single S-SSB, the group index is identical to the S-SSB index, and if each slot contains two S-SSBs, the combination of the position of the S-SSB within the slot (e.g., a one-bit representation) and the group index is identical to the S-SSB index.

[0373] In one subexample, the DFN (e.g., a 10-bit field having a value from 0 to 1023), the slot index within the group, and the S-SSB index (or the MSB of the S-SSB index or group index) may be indicated in the PSBCH content.

[0374] As another subexample, the DFN (e.g., a 10-bit field having a value from 0 to 1023) and the slot index within the group may be indicated in the PSBCH content, and the S-SSB index (or the LSB of the S-SSB index or group index) may be indicated as a DMRS-like signal for the PSBCH. Such other signals / channels of the PSBCH are displayed.

[0375] In a tenth example of the first approach, an S-SSB burst set includes multiple S-SSBs (i.e., L_SSB>1), e.g., the S-SSBs operate in a multi-beam and / or repetition manner, the slots including the S-SSBs may be non-contiguous, and each slot including an S-SSB is constrained within a predefined slot group, where the slot group has the same number of slots and is composed of a subset of the period of the S-SSB burst set (e.g., 2402 in FIG. 24).

[0376] For example, the periodic subset of the S-SSB burst set is divided into L_SSB slot groups if each slot contains a single S-SSB, or L_SSB / 2 slot groups if each slot contains two S-SSBs, where each group has the same number of slots, each group contains one slot containing an S-SSB, and the position of the slot containing the S-SSB may be variable within the group and may be represented as In this example, if each slot contains a single S-SSB, the group index is the same as the S-SSB index, and if each slot contains two S-SSBs, the combination of the position of the S-SSB within the slot (e.g., represented as a single bit) and the group index is the same as the S-SSB index.

[0377] As one subexample, the DFN (e.g., a 10-bit field having a value from 0 to 1023), the slot index within the group, and the S-SSB index (or the MSB of the S-SSB index or group index) may be indicated in the PSBCH content.

[0378] As another subexample, the DFN (e.g., a 10-bit field having a value from 0 to 1023) and the slot index within the group can be indicated in the PSBCH content, and the S-SSB index (or the LSB of the S-SSB index or group index) can be indicated using other signals / channels of the PSBCH, such as DMRS of the PSBCH.

[0379] In an eleventh example of the first approach, one S-SSB burst set includes multiple S-SSBs (i.e., L_SSB>1), for example, the S-SSBs operate in a multi-beam and / or repetitive manner, the slots including the S-SSBs may be non-contiguous, and the position of each slot including the S-SSB may be variable and displayed within the period of the S-SSB burst set (e.g., 2403 in FIG. 24).

[0380] In one subexample, the DFN in which the PSBCH for that S-SSB is located (e.g., a 10-bit field having a value from 0 to 1023) and the slot index within the indicated DFN may be indicated in the PSBCH content, where the slot index within the DFN may be represented as a (k+4)-bit field having a value from 0 to M-1, where M=10*2^k, where 15*2^k is the largest SCS supported for the NR sidelink (e.g., k=4) or supported for the NR sidelink carrier frequency range (e.g., k=4 for above 6 GHz, k=1 for below 6 GHz). If each slot contains two S-SSBs, the position of the S-SSB within the slot (e.g., a 1-bit indication for one of the two S-SSBs in the slot) may also be indicated in the PSBCH content.

[0381] As another subexample, the DFN in which the PSBCH of the S-SSB is located (e.g., a 10-bit field having a value from 0 to 1023) and a slot index within the indicated DFN may be indicated in the PSBCH content, where the slot index within the DFN may be represented as a (k+4)-bit field having a value from 0 to M-1, where M=10*2^k, where 15*2^k is the largest SCS supported for the NR sidelink (e.g., k=4) or supported for the carrier frequency range of the NR sidelink (e.g., k=4 above 6 GHz, k=1 below 6 GHz). If each slot contains two S-SSBs, the position of the S-SSB within the slot (e.g., a 1-bit indication of one of the two S-SSBs in the slot) may be indicated using another signal / channel of the PSBCH, such as the DMRS of the PSBCH.

[0382] In a twelfth example of the first approach, a single S-SSB burst set includes multiple S-SSBs (i.e., L_SSB>1), e.g., the S-SSBs operate in a multi-beam and / or repetitive manner, the slots including the S-SSBs may be non-contiguous, and the position of each slot including an S-SSB may be variable and indicated within a subset of the period of the S-SSB burst set (e.g., 2404 in FIG. 24).

[0383] As one subexample, the DFN in which the PSBCH for that S-SSB is located (e.g., a 10-bit field having a value from 0 to 1023) and a slot index within the indicated DFN may be indicated in the PSBCH content, where the slot index within the DFN may be represented as a (k+4)-bit field having a value from 0 to M-1, where M=10*2^k, where 15*2^k is the largest SCS supported for the NR sidelink (e.g., k=4) or supported for the NR sidelink carrier frequency range (e.g., k=4 above 6 GHz, k=1 below 6 GHz). If each slot contains two S-SSBs, the position of the S-SSB within the slot (e.g., a 1-bit indication of one of the two S-SSBs in the slot) may also be indicated in the PSBCH content.

[0384] In another subexample, the DFN in which the PSBCH for that S-SSB is located (e.g., a 10-bit field having a value from 0 to 1023) and a slot index within the indicated DFN may be indicated in the PSBCH content, where the slot index within the DFN may be represented as a (k+4)-bit field having a value from 0 to M-1, where M=10*2^k, where 15*2^k is the largest SCS supported for the NR sidelink (e.g., k=4) or supported for the NR sidelink carrier frequency range (e.g., k=4 above 6 GHz, k=1 below 6 GHz). If each slot contains two S-SSBs, the position of the S-SSB within the slot (e.g., a 1-bit indication of one of the two S-SSBs in the slot) may be indicated using another signal / channel of the PSBCH, such as the DMRS of the PSBCH.

[0385] In a second approach, the PSBCH content may include the sidelink carrier bandwidth.

[0386] In a first example of this approach, the sidelink carrier bandwidth is expressed from a set of values ​​in RB units, where the RBs correspond to the SCS of the S-SSB. The set of values ​​can be determined for each carrier frequency range.

[0387] In a second example of this approach, the sidelink carrier bandwidth is indicated from a set of values ​​in RB units, where the RBs correspond to the SCSs indicated in the PSBCH content. A set of values ​​can be determined per indicated SCS and / or carrier frequency range.

[0388] In a third example of this approach, the sidelink carrier bandwidth is expressed from a set of values ​​in MHz, which can be determined for each carrier frequency range.

[0389] In a third approach, the PSBCH content may include pneumatics for the NR sidelink physical control channel (PSCCH) and / or the NR sidelink physical shared channel (PSSCH).

[0390] In a first example of this approach, the neurology may include at least a subcarrier spacing for the PSSCH and / or PSCCH expressed from a predefined set of values ​​in kHz, where the set of values ​​may be determined for each carrier frequency range.

[0391] In a second example of this approach, the neurology can include at least subcarrier spacing for the PSSCH and / or PSCCH, where the DMRS of the PSSCH and / or PSCCH is currently quasico-located with the DMRS of the PSBCH, and the subcarrier spacing is expressed in kHz from a predefined set of values, which can be determined for each carrier frequency range.

[0392] In a fourth approach, the PSBCH content may include a frequency offset, where the frequency offset may include at least one of an RE-level offset and an RB-level offset, where the RE or the RB is related to the neurology of the PSCCH.

[0393] In a first example of this approach, the frequency offset denotes the difference between the lowest RE of S-SSB and the lowest RE of PSCCH.

[0394] In a second example of this approach, the frequency offset denotes the difference between the lowest RE of the S-SSB and the lowest RE of the carrier.

[0395] In a third example of this approach, the frequency offset denotes the difference between the lowest RE of S-SSB and the lowest RE of PSSCH.

[0396] In a fourth example of this approach, the frequency offset represents the difference between the lowest RE of the S-SSB and the lowest RE of the BWP in which the S-SSB is located.

[0397] In a fifth approach, the PSBCH content may include configurations of the PSCCH and / or the PSSCH.

[0398] In an example of this approach, the configuration may include a BWP configuration.

[0399] In another example of this approach, the configuration can include a multiplexing pattern of PSCCH and PSSCH.

[0400] As yet another example of this approach, the configuration may include a resource allocation for the PSCCH, eg, time domain and frequency domain resources mapped to the PSCCH.

[0401] As yet another example of this approach, the configuration may include a TDD slot configuration.

[0402] In the sixth approach, the PSBCH content may include information on the S-SSBs that are actually transmitted within the burst set.

[0403] As an example, the S-SSBs actually transmitted in a burst set are a bitmap whose length is equal to the maximum number of SS / PBCH blocks in a period supported for a given band or carrier frequency range.

[0404] In another approach, if the PSBCH content does not contain information for the S-SSBs actually transmitted in a burst set, the UE can assume that all S-SSBs in the burst set have been transmitted.

[0405] In the seventh approach, the PSBCH content may include information on the power offset between the S-SSB and the PSCCH (or PSSCH).

[0406] For example, the power offset may indicate the energy per resource element (EPRE) between the S-SSS of the S-SSB (or equivalent to the DMRS of the PSBCH if the S-SSS and DMRS of the PSBCH have the same EPRE or a predefined EPRE ratio) and the DMRS of the PSCCH.

[0407] In the eighth approach, the PSBCH content may include information on the periodicity of the S-SSB burst set.

[0408] In a ninth approach, the PSBCH content may include a system information category indication of the PSBCH content.

[0409] For example, one bit can be used to indicate whether the system information is from a base station or from the vehicle itself.

[0410] In another example, two bits can be used to indicate the type of base station (e.g., NR base station or LTE base station) as well as whether the system information is from a base station or from the vehicle itself.

[0411] In the tenth approach, the PSBCH content may include one or more reserved bits for future expansion. In one embodiment, an approach to scrambling the PSBCH is specified.

[0412] In the first approach, if the TTI (transmission time interval) of the PSBCH is 2^mDFN and the period of the S-SSB burst set is 2^nDFN (where m and n are integers and m≧n), the (n+1)th to mth LSBs of the DFN in the PSBCH content are not scrambled by the first level scrambling sequence (if m=n, all bits of the DFN are scrambled), and the other bits of the PSBCH content (except the CRC) are scrambled by the first level scrambling sequence, where the first level scrambling sequence is constructed based on the (n+1)th to mth LSBs of the DFN and the sidelink synchronization ID. All bits after the first level scrambling and the (n+1)th through mth LSBs of the DFN that are not scrambled by the first level scrambling are used to generate a CRC, and all bits after the first level scrambling and the (n+1)th through mth LSBs of the DFN that are not scrambled by the first level scrambling are scrambled by the second level scrambling together with the generated CRC, where the second level scrambling sequence is formed based on the sidelink synchronization ID and other timing information carried by the S-SSB other than the PSBCH, if applicable (e.g., S-SSS and / or DMRS of the PSBCH). A diagram of this example is shown in FIG. 25.

[0413] 25 is a diagram illustrating an example scrambling of a PSBCH 2500 according to an embodiment of the present disclosure. The scrambling embodiment of the PSBCH 2500 illustrated in FIG. 25 is for illustration purposes only. FIG. 25 does not limit the scope of the present disclosure to any particular implementation.

[0414] In the second approach, if the TTI (Transmission Time Interval) of the PSBCH is 2^mDFN and the period of the S-SSB burst set is 2^nDFN (where m and n are integers, m≧n), the 1st to mth LSBs of the DFN in the PSBCH content are not scrambled by the first level scrambling sequence (if m=0, all bits of the DFN are scrambled), and other bits of the PSBCH content (except the CRC) are scrambled by the first level scrambling sequence, where the first level scrambling sequence is constructed based on the 1st to mth LSBs of the DFN and the sidelink synchronization ID.

[0415] All bits after the first level scrambling and the 1st through mth LSBs of the DFN that are not scrambled by the first level scrambling are used to generate a CRC, and all bits after the first level scrambling and the 1st through mth LSBs of the DFN that are not scrambled by the first level scrambling are scrambled by the second level scrambling together with the generated CRC, where the second level scrambling sequence is based on the sidelink synchronization ID and other timing information carried by the S-SSB other than the PSBCH (e.g., S-SSS and / or DMRS of the PSBCH), if applicable. A diagram of this example is shown in FIG. 26.

[0416] 26 is a diagram illustrating another example scrambling of the PSBCH 2600 according to an embodiment of the present disclosure. The scrambling embodiment of the PSBCH 2600 illustrated in FIG. 26 is for illustration purposes only. FIG. 26 does not limit the scope of the present disclosure to any particular implementation.

[0417] In the third approach, if the TTI (transmission time interval) of the PSBCH is 2^mDFN and the period of the S-SSB burst set is 2^nDFN (where m and n are integers and m≧n), the 1st to mth LSBs of the DFN in the PSBCH content are not scrambled by the first level scrambling sequence (if m=0, all bits of the DFN are scrambled), and other bits of the PSBCH content (except for the CRC) are scrambled by the first level scrambling sequence, where the first level scrambling sequence is constructed based on the (n+1)th to mth LSBs of the DFN and the sidelink synchronization ID. All bits after the first level scrambling and the 1st through mth LSBs of the DFN that are not scrambled by the first level scrambling are used to generate a CRC, and all bits after the first level scrambling and the 1st through mth LSBs of the DFN that are not scrambled by the first level scrambling are scrambled by the second level scrambling together with the generated CRC, where the second level scrambling sequence is based on the sidelink synchronization ID and other timing information carried by the S-SSB other than the PSBCH (e.g., S-SSS and / or DMRS of the PSBCH), if applicable. A diagram of this example is shown in FIG. 27.

[0418] 27 is a diagram illustrating another example scrambling of the PSBCH 2700 according to an embodiment of the present disclosure. The scrambling embodiment of the PSBCH 2700 illustrated in FIG. 27 is for illustration purposes only. FIG. 27 does not limit the scope of the present disclosure to any particular implementation.

[0419] In the fourth approach, all bits of the DFN in the PSBCH content are scrambled by a first level scrambling sequence, where the first level scrambling sequence is based only on the sidelink synchronization ID. All bits after the first level scrambling are used to generate a CRC, and all bits after the first level scrambling are scrambled by a second level scrambling sequence, where the second level scrambling sequence is based on the sidelink synchronization ID and other timing information carried by the S-SSB other than the PSBCH (e.g., S-SSS and / or DMRS of the PSBCH), if applicable. A diagram of this example is shown in FIG. 28.

[0420] 28 is a diagram illustrating another example scrambling of the PSBCH 2800 according to an embodiment of the present disclosure. The scrambling embodiment of the PSBCH 2800 illustrated in FIG. 28 is for illustration purposes only. FIG. 28 does not limit the scope of the present disclosure to any particular implementation.

[0421] In the fifth approach, all bits in the PSBCH content except the CRC are scrambled by a scrambling sequence, which is based on the sidelink synchronization ID and other timing information (e.g., S-SSS and / or DMRS of the PSBCH) carried by the S-SSB other than the PSBCH, if applicable. All bits after scrambling are used to generate the CRC. There is only one scrambling level in this approach. A diagram of this example is shown in Figure 29.

[0422] 29 is a diagram illustrating another example scrambling of the PSBCH 2900 according to an embodiment of the present disclosure. The scrambling embodiment of the PSBCH 2900 illustrated in FIG. 29 is for illustration purposes only. FIG. 29 does not limit the scope of the present disclosure to any particular implementation. In one embodiment, a manner for PSBCH to DMRS RE mapping is specified.

[0423] In the first approach, a portion of the symbols in the S-SSB are mapped for the DMRS of the PSBCH, such that the symbols containing the DMRS of the PSBCH are time division multiplexed (TDMed) with the symbols containing the PSBCH.

[0424] In one lower approach method, when the BW of the S-SSB is greater than 12 RBs and the BW of the S-SSS is 12 RBs, the remaining RBs in the symbol including the S-SSS in the S-SSB that are not mapped to the S-SSS can be mapped for the DMRS of the PSBCH.

[0425] In this example approach, two or more TDM patterns may be supported, and each TDM pattern is associated with a sidelink synchronization ID group. For example, sidelink synchronization IDs may be divided into two groups (e.g., in-network and out-network), and the UE may assume a TDM pattern of symbols including DMRS of PSBCH and symbols including PSBCH according to the sidelink synchronization ID detected from S-PSS and / or S-SSS. An example of two TDM patterns is shown in Figure 30, where some of the symbols including DMRS of PSBCH in the first TDM pattern are mapped for PSBCH in the second TDM pattern, and some of the symbols including PSBCH in the first TDM pattern are mapped for DMRS of PSBCH in the second TDM pattern.

[0426] 30 is a diagram illustrating an example TDM pattern of a PSBCH and a DMRS 3000 according to an embodiment of the present disclosure. The embodiment of the TDM pattern of a PSBCH and a DMRS 3000 shown in FIG. 30 is for illustration purposes only. FIG. 30 does not limit the scope of the present disclosure to any particular implementation.

[0427] In the second approach, the DMRS of the PSBCH is mapped to a portion of the REs in each RB that contains the RE carrying the PSBCH, thereby allowing the RE carrying the DMRS of the PSBCH to be interleaved frequency division multiplexed (IFDMed) with the RE carrying the PSBCH.

[0428] In an example of this approach, the RE index within the RB of the RE carrying the DMRS of the PSBCH is fixed in the specification as N_RE^DMRS mod4=1 or N_RE^DMRS mod2=0, where N_RE^DMRS is the RE index within the RB of the RE carrying the DMRS of the PSBCH.

[0429] In another example of this approach, the RE index within the RB of the RE carrying the DMRS for the PSBCH is determined by the sidelink synchronization ID. In one subexample, N_RE^DMRS mod4 = (N_ID^SL mod4), where N_RE^DMRS is the RE index within the RB of the RE carrying the DMRS for the PSBCH. In another subexample, N_RE^DMRS mod2 = (N_ID^SL mod2), where N_RE^DMRS is the RE index within the RB of the RE carrying the DMRS for the PSBCH.

[0430] In one embodiment, some of the system information may also be pre-configured and known to V2X UEs attempting to synchronize with the source.

[0431] To configure the preconfigured system information, one or more access schemes may be supported simultaneously, for example, some access schemes or access scheme instances may only be supported for a range of carrier frequencies.

[0432] In the first approach, the preconfigured system information may include a pneumatic system for the NR sidelink, and if there is additional configuration of the pneumatic system, all NR sidelink signals and channels use the preconfigured pneumatic system until further configuration. The pneumatic system includes at least one of a subcarrier spacing and a CP length.

[0433] In a second approach, the preconfigured system information may include the sidelink carrier bandwidth.

[0434] In a first example of this approach, the sidelink carrier bandwidth is indicated from a set of values ​​defined in RB units, where the RBs relate to the SCSs included in the preconfigured information. The set of values ​​can be determined for each carrier frequency range.

[0435] In a second example of this approach, the sidelink carrier bandwidth is expressed from a set of values ​​defined in MHz, which can be determined for each carrier frequency range.

[0436] In a third approach, the preconfigured system information may include synchronization raster entries where the SS / PBCH blocks are located in the frequency domain.

[0437] As an example, the synchronization entries can be selected from a set of predefined frequency locations for a given band.

[0438] In a fourth approach, the preconfigured system information may include a frequency offset, where the frequency offset may include at least one of an RE-level offset and an RB-level offset, where the RE or RB is related to the neurology in the preconfigured information.

[0439] In a first example of this approach, the frequency offset denotes the difference between the lowest RE of S-SSB and the lowest RE of PSCCH.

[0440] In a second example of this approach, the frequency offset denotes the difference between the lowest RE of the S-SSB and the lowest RE of the carrier.

[0441] In a third example of this approach, the frequency offset denotes the difference between the lowest RE of S-SSB and the lowest RE of PSSCH.

[0442] In a fourth example of this approach, the frequency offset refers to the difference between the lowest RE of the S-SSB and the lowest RE of the BWP in which the S-SSB is located.

[0443] In the fifth approach, the preconfigured system information may include a BWP configuration. If there is additional configuration of the neurology, all NR sidelink signals and channels are assumed to use the preconfigured BWP until further configuration.

[0444] In a sixth approach, the pre-configured system information may include an indication of the S-SSBs that will actually be transmitted within the burst set.

[0445] As an example, the S-SSBs actually transmitted in a burst set are a bitmap having a length equal to the maximum number of S-SSBs in a period supported for a given band or carrier frequency range.

[0446] In the seventh approach, the preconfigured system information may include the period of the S-SSB burst set.

[0447] In one embodiment, one sidelink SS / PBCH block (S-SSB) includes 2 OFDM symbols mapped for the sidelink primary synchronization signal (S-PSS), 2 OFDM symbols mapped for the sidelink secondary synchronization signal (S-SSS), and X OFDM symbols mapped for the physical sidelink broadcast channel (PSBCH) and associated demodulation reference signal (DMRS). Thus, overall, the S-SSB spans X+4 OFDM symbols, and the X+4 OFDM symbols are contiguous in the time domain.

[0448] In one approach, X is fixed for all S-SSBs. One of the examples of this embodiment can be applied to the configuration of S-SSBs when X is fixed.

[0449] In another approach, X may be variable / configurable and pre-configured known to the V2X UE attempting to synchronize to the synchronization source. If X is variable / configurable, at least one of the examples of this embodiment may be applied to the configuration of S-SSB for a given X.

[0450] In this example approach, X may vary depending on the S-SSB's numerology (e.g., cyclic prefix length), e.g., for a general CP, one S-SSB has X_1 symbols mapped for PSBCH and DMRS, while for an extended CP, one S-SSB has X_2 symbols mapped for PSBCH and DMRS, where X_1 is different from X_2 (e.g., X_1>X_2), and the S-SSB configuration may be different for the general CP and the extended CP (e.g., one example of this embodiment having X_1 symbols for PSBCH and DMRS is used for the general CP, and another example of this embodiment having X_2 symbols for PSBCH and DMRS is used for the extended CP). As an example, the S-SSB for the extended CP is truncated from the S-SSB for the general CP by about the last symbol (e.g., the last two symbols, where X_1=X_2+2). In one particular consideration for this instance, X_1=12 and X_2=10. Another specific consideration for this instance is that X_1=13 and X_2=11.

[0451] In one approach, the S-SSB consists of 8 OFDM symbols (eg, X=4).

[0452] FIG. 31 is a diagram illustrating an exemplary S-SSB 3100 according to an embodiment of the present disclosure. The embodiment of the S-SSB 3100 illustrated in FIG. 31 is for illustrative purposes only. FIG. 31 does not limit the scope of the present disclosure to any particular implementation.

[0453] As an example (e.g., 3101 in FIG. 31), symbols #2 and #3 of S-SSB are mapped for S-PSS, symbols #5 and #7 of S-SSB are mapped for S-SSS, and symbols #1, #4, #6 and #8 of S-SSB are mapped for PSBCH and DMRS.

[0454] As another example (e.g., 3102 in FIG. 31), symbols #2 and #3 of S-SSB are mapped for S-PSS, symbols #7 and #8 of S-SSB are mapped for S-SSS, and symbols #1, #4, #5 and #6 of S-SSB are mapped for PSBCH and DMRS.

[0455] As another example (e.g., 3103 in FIG. 31), symbols #2 and #3 of S-SSB are mapped for S-PSS, symbols #5 and #6 of S-SSB are mapped for S-SSS, and symbols #1, #4, #7 and #8 of S-SSB are mapped for PSBCH and DMRS.

[0456] As another example (e.g., 3104 in FIG. 31), symbols #2 and #3 of S-SSB are mapped for S-PSS, symbols #6 and #7 of S-SSB are mapped for S-SSS, and symbols #1, #4, #5 and #8 of S-SSB are mapped for PSBCH and DMRS.

[0457] As another example (e.g., 3105 in FIG. 31), symbols #1 and #2 of S-SSB are mapped for S-PSS, symbols #4 and #7 of S-SSB are mapped for S-SSS, and symbols #3, #5, #6 and #8 of S-SSB are mapped for PSBCH and DMRS.

[0458] As another example (e.g., 3106 in FIG. 31), symbols #1 and #2 of S-SSB are mapped for S-PSS, symbols #7 and #8 of S-SSB are mapped for S-SSS, and symbols #3, #4, #5 and #6 of S-SSB are mapped for PSBCH and DMRS.

[0459] As another example (3107 in FIG. 31), symbols #1 and #2 of S-SSB are mapped for S-PSS, symbols #5 and #6 of S-SSB are mapped for S-SSS, and symbols #3, #4, #7 and #8 of S-SSB are mapped for PSBCH and DMRS.

[0460] In another approach, the S-SSB consists of 9 OFDM symbols (eg, X=5).

[0461] FIG. 32 is a diagram illustrating another exemplary S-SSB 3200 according to an embodiment of the present disclosure. The embodiment of the S-SSB 3200 illustrated in FIG. 32 is for illustrative purposes only. FIG. 32 does not limit the scope of the present disclosure to any particular implementation.

[0462] As an example (e.g., 3201 in FIG. 32), symbols #2 and #3 of S-SSB are mapped for S-PSS, symbols #5 and #7 of S-SSB are mapped for S-SSS, and symbols #1, #4, #6, #8 and #9 of S-SSB are mapped for PSBCH and DMRS.

[0463] As another example (e.g., 3202 in FIG. 32), symbols #2 and #3 of S-SSB are mapped for S-PSS, symbols #8 and #9 of S-SSB are mapped for S-SSS, and symbols #1, #4, #5, #6 and #7 of S-SSB are mapped for PSBCH and DMRS.

[0464] As another example (e.g., 3203 in FIG. 32), symbols #2 and #3 of S-SSB are mapped for S-PSS, symbols #6 and #7 of S-SSB are mapped for S-SSS, and symbols #1, #4, #5, #8 and #9 of S-SSB are mapped for PSBCH and DMRS.

[0465] As another example (e.g., 3204 in FIG. 32), symbols #2 and #3 of S-SSB are mapped for S-PSS, symbols #5 and #8 of S-SSB are mapped for S-SSS, and symbols #1, #4, #6, #7 and #9 of S-SSB are mapped for PSBCH and DMRS.

[0466] As another example (e.g., 3205 in FIG. 32), symbols #1 and #2 of S-SSB are mapped for S-PSS, symbols #4 and #8 of S-SSB are mapped for S-SSS, and symbols #3, #5, #6, #7 and #9 of S-SSB are mapped for PSBCH and DMRS.

[0467] As another example (e.g., 3206 in FIG. 32), symbols #1 and #2 of S-SSB are mapped for S-PSS, symbols #8 and #9 of S-SSB are mapped for S-SSS, and symbols #3, #4, #5, #6 and #7 of S-SSB are mapped for PSBCH and DMRS.

[0468] As another example (e.g., 3207 in FIG. 32), symbols #1 and #2 of S-SSB are mapped for S-PSS, symbols #5 and #6 of S-SSB are mapped for S-SSS, and symbols #3, #4, #7, #8 and #9 of S-SSB are mapped for PSBCH and DMRS.

[0469] As another example (e.g., 3208 in FIG. 32), symbols #1 and #2 of S-SSB are mapped for S-PSS, symbols #6 and #7 of S-SSB are mapped for S-SSS, and symbols #3, #4, #5, #8 and #9 of S-SSB are mapped for PSBCH and DMRS.

[0470] As another example (e.g., 3209 in FIG. 32), symbols #1 and #2 of S-SSB are mapped for S-PSS, symbols #5 and #7 of S-SSB are mapped for S-SSS, and symbols #3, #4, #6, #8 and #9 of S-SSB are mapped for PSBCH and DMRS.

[0471] In another approach, the S-SSB consists of 10 OFDM symbols (eg, X=6).

[0472] FIG 33A is a diagram illustrating yet another exemplary S-SSB 3300 according to an embodiment of the present disclosure. The embodiment of the S-SSB 3300 illustrated in FIG 33A is for illustrative purposes only. FIG 33A does not limit the scope of the present disclosure to any particular implementation.

[0473] As an example (e.g., 3301 in FIG. 33A), symbols #2 and #3 of S-SSB are mapped for S-PSS, symbols #6 and #8 of S-SSB are mapped for S-SSS, and symbols #1, #4, #5, #7, #9 and #10 of S-SSB are mapped for PSBCH and DMRS.

[0474] As another example (e.g., 3302 in FIG. 33A), symbols #2 and #3 of S-SSB are mapped for S-PSS, symbols #9 and #10 of S-SSB are mapped for S-SSS, and symbols #1, #4, #5, #6, #7 and #8 of S-SSB are mapped for PSBCH and DMRS.

[0475] As another example (e.g., 3303 in FIG. 33A), symbols #2 and #3 of S-SSB are mapped for S-PSS, symbols #6 and #7 of S-SSB are mapped for S-SSS, and symbols #1, #4, #5, #8, #9 and #10 of S-SSB are mapped for PSBCH and DMRS.

[0476] As another example (e.g., 3304 in FIG. 33A), symbols #2 and #3 of S-SSB are mapped for S-PSS, symbols #5 and #9 of S-SSB are mapped for S-SSS, and symbols #1, #4, #6, #7, #8 and #10 of S-SSB are mapped for PSBCH and DMRS.

[0477] As another example (e.g., 3305 in FIG. 33A), symbols #2 and #3 of S-SSB are mapped for S-PSS, symbols #5 and #6 of S-SSB are mapped for S-SSS, and symbols #1, #4, #7, #8, #9 and #10 of S-SSB are mapped for PSBCH and DMRS.

[0478] As another example (e.g., 3306 in FIG. 33A), symbols #1 and #2 of S-SSB are mapped for S-PSS, symbols #9 and #10 of S-SSB are mapped for S-SSS, and symbols #3, #4, #5, #6, #7 and #8 of S-SSB are mapped for PSBCH and DMRS.

[0479] As another example (3307 in FIG. 33A), symbols #1 and #2 of S-SSB are mapped for S-PSS, symbols #6 and #7 of S-SSB are mapped for S-SSS, and symbols #3, #4, #5, #8, #9 and #10 of #S-SSB are mapped for PSBCH and DMRS.

[0480] As another example (e.g., 3308 in FIG. 33A), symbols #1 and #2 of S-SSB are mapped for S-PSS, symbols #5 and #8 of S-SSB are mapped for S-SSS, and symbols #3, #4, #6, #7, #9 and #10 of S-SSB are mapped for PSBCH and DMRS.

[0481] As another example (e.g., 3309 in FIG. 33A), symbols #1 and #2 of S-SSB are mapped for S-PSS, symbols #4 and #9 of S-SSB are mapped for S-SSS, and symbols #3, #5, #6, #7, #8 and #10 of S-SSB are mapped for PSBCH and DMRS.

[0482] FIG. 33B is a diagram illustrating yet another exemplary S-SSB 3320 according to an embodiment of the present disclosure. The embodiment of the S-SSB 3320 illustrated in FIG. 33B is for illustrative purposes only. FIG. 33B does not limit the scope of the present disclosure to any particular embodiment.

[0483] As another example (e.g., 3310 in FIG. 33B), symbols #1 and #2 of S-SSB are mapped for S-PSS, symbols #3 and #4 of S-SSB are mapped for S-SSS, and symbols #5, #6, #7, #8, #9 and #10 of S-SSB are mapped for PSBCH and DMRS.

[0484] As another example (e.g., 3311 in FIG. 33B), symbols #1 and #2 of S-SSB are mapped for S-PSS, symbols #4 and #5 of S-SSB are mapped for S-SSS, and symbols #3, #6, #7, #8, #9 and #10 of S-SSB are mapped for PSBCH and DMRS.

[0485] As another example (e.g., 3312 in FIG. 33B), symbols #1 and #2 of S-SSB are mapped for S-PSS, symbols #5 and #6 of S-SSB are mapped for S-SSS, and symbols #3, #4, #7, #8, #9 and #10 of S-SSB are mapped for PSBCH and DMRS.

[0486] As another example (e.g., 3313 in FIG. 33B), symbols #1 and #2 of S-SSB are mapped for S-PSS, symbols #7 and #8 of S-SSB are mapped for S-SSS, and symbols #3, #4, #5, #6, #9 and #10 of S-SSB are mapped for PSBCH and DMRS.

[0487] As another example (e.g., 3314 in FIG. 33B), symbols #1 and #2 of S-SSB are mapped for S-PSS, symbols #8 and #9 of S-SSB are mapped for S-SSS, and symbols #3, #4, #5, #6, #7 and #10 of S-SSB are mapped for PSBCH and DMRS.

[0488] As another example (e.g., 3315 in FIG. 33B), symbols #1 and #2 of S-SSB are mapped for S-PSS, symbols #4 and #10 of S-SSB are mapped for S-SSS, and symbols #3, #5, #6, #7, #8 and #9 of S-SSB are mapped for PSBCH and DMRS.

[0489] As another example (e.g., 3316 in FIG. 33B), symbols #1 and #2 of S-SSB are mapped for S-PSS, symbols #5 and #10 of S-SSB are mapped for S-SSS, and symbols #3, #4, #6, #7, #8 and #9 of S-SSB are mapped for PSBCH and DMRS.

[0490] As another example (e.g., 3317 in FIG. 33B), symbols #1 and #2 of S-SSB are mapped for S-PSS, symbols #6 and #10 of S-SSB are mapped for S-SSS, and symbols #3, #4, #5, #7, #8 and #9 of S-SSB are mapped for PSBCH and DMRS.

[0491] As another example (e.g., 3318 in FIG. 33B), symbols #2 and #3 of S-SSB are mapped for S-PSS, symbols #1 and #4 of S-SSB are mapped for S-SSS, and symbols #5, #6, #7, #8, #9 and #10 of S-SSB are mapped for PSBCH and DMRS.

[0492] In another approach, the S-SSB consists of 11 OFDM symbols (eg, X=7).

[0493] FIG. 34A is a diagram illustrating another exemplary S-SSB 3400 according to an embodiment of the present disclosure. The embodiment of the gNB 102 illustrated in FIG. 34A is for illustrative purposes only. FIG. 34A does not limit the scope of the present disclosure to any particular implementation.

[0494] As an example (e.g., 3401 in FIG. 34A), the #2 and #3 symbols of the S-SSB are mapped for the S-PSS, the #6 and #9 symbols of the S-SSB are mapped for the S-SSS, and the #1, #4, #5, #7, #8, #10 and #11 symbols of the S-SSB are mapped for the PSBCH and DMRS.

[0495] As another example (e.g., 3402 in FIG. 34A), the #2 and #3 symbols of S-SSB are mapped for S-PSS, the #10 and #11 symbols of S-SSB are mapped for S-SSS, and the #1, #4, #5, #6, #7, #8 and #9 symbols of S-SSB are mapped for PSBCH and DMRS.

[0496] As another example (e.g., 3403 in FIG. 34A), symbols #2 and #3 of S-SSB are mapped for S-PSS, symbols #7 and #8 of S-SSB are mapped for S-SSS, and symbols #1, #4, #5, #6, #9, #10 and #11 of S-SSB are mapped for PSBCH and DMRS.

[0497] As another example (e.g., 3404 in FIG. 34A), symbols #2 and #3 of S-SSB are mapped for S-PSS, symbols #5 and #9 of S-SSB are mapped for S-SSS, and symbols #1, #4, #6, #7, #8, #10 and #11 of S-SSB are mapped for PSBCH and DMRS.

[0498] As another example (e.g., 3405 in FIG. 34A), symbols #2 and #3 of S-SSB are mapped for S-PSS, symbols #6 and #7 of S-SSB are mapped for S-SSS, and symbols #1, #4, #5, #8, #9, #10 and #11 of S-SSB are mapped for PSBCH and DMRS.

[0499] As another example (e.g., 3406 in FIG. 34A), symbols #1 and #2 of S-SSB are mapped for S-PSS, symbols #10 and #11 of S-SSB are mapped for S-SSS, and symbols #3, #4, #5, #6, #7, #8 and #9 of S-SSB are mapped for PSBCH and DMRS.

[0500] As another example (e.g., 3407 in FIG. 34A), symbols #1 and #2 of S-SSB are mapped for S-PSS, symbols #6 and #7 of S-SSB are mapped for S-SSS, and symbols #3, #4, #5, #8, #9, #10 and #11 of S-SSB are mapped for PSBCH and DMRS.

[0501] As another example (e.g., 3408 in FIG. 34A), symbols #1 and #2 of S-SSB are mapped for S-PSS, symbols #5 and #9 of S-SSB are mapped for S-SSS, and symbols #3, #4, #6, #7, #8, #10 and #11 of S-SSB are mapped for PSBCH and DMRS.

[0562]

[0502] As another example (e.g., 3409 in FIG. 34A), symbols #1 and #2 of S-SSB are mapped for S-PSS, symbols #7 and #8 of S-SSB are mapped for S-SSS, and symbols #3, #4, #5, #6, #9, #10 and #11 of S-SSB are mapped for PSBCH and DMRS.

[0563]

[0503] FIG. 34B is a diagram illustrating yet another exemplary S-SSB 3420 according to an embodiment of the present disclosure. The embodiment of the S-SSB 3420 illustrated in FIG. 34B is for illustrative purposes only. FIG. 34B does not limit the scope of the present disclosure to any particular embodiment.

[0504] As another example (e.g., 3410 in FIG. 34B), symbols #2 and #3 of S-SSB are mapped for S-PSS, symbols #4 and #5 of S-SSB are mapped for S-SSS, and symbols #1, #6, #7, #8, #9, #10 and #11 of S-SSB are mapped for PSBCH and DMRS.

[0505] As another example (e.g., 3411 in FIG. 34B), symbols #2 and #3 of S-SSB are mapped for S-PSS, symbols #5 and #6 of S-SSB are mapped for S-SSS, and symbols #1, #4, #7, #8, #9, #10 and #11 of S-SSB are mapped for PSBCH and DMRS.

[0506] As another example (e.g., 3412 in FIG. 34B), symbols #2 and #3 of S-SSB are mapped for S-PSS, symbols #8 and #9 of S-SSB are mapped for S-SSS, and symbols #1, #4, #5, #6, #7, #10 and #11 of S-SSB are mapped for PSBCH and DMRS.

[0507] As another example (e.g., 3413 in FIG. 34B), symbols #2 and #3 of S-SSB are mapped for S-PSS, symbols #9 and #10 of S-SSB are mapped for S-SSS, and symbols #1, #4, #5, #6, #7, #8 and #11 of S-SSB are mapped for PSBCH and DMRS.

[0508] As another example (e.g., 3414 in FIG. 34B), symbols #2 and #3 of S-SSB are mapped for S-PSS, symbols #5 and #11 of S-SSB are mapped for S-SSS, and symbols #1, #4, #6, #7, #8, #9 and #10 of S-SSB are mapped for PSBCH and DMRS.

[0509] As another example (e.g., 3415 in FIG. 34B), symbols #2 and #3 of S-SSB are mapped for S-PSS, symbols #5 and #10 of S-SSB are mapped for S-SSS, and symbols #1, #4, #6, #7, #8, #9 and #11 of S-SSB are mapped for PSBCH and DMRS.

[0510] As another example (e.g., 3416 in FIG. 34B), symbols #2 and #3 of S-SSB are mapped for S-PSS, symbols #6 and #11 of S-SSB are mapped for S-SSS, and symbols #1, #4, #5, #7, #8, #9 and #10 of S-SSB are mapped for PSBCH and DMRS.

[0511] As another example (e.g., 3417 in FIG. 34B), symbols #3 and #4 of S-SSB are mapped for S-PSS, symbols #2 and #5 of S-SSB are mapped for S-SSS, and symbols #1, #6, #7, #8, #9, #10 and #11 of S-SSB are mapped for PSBCH and DMRS.

[0512] As another example (e.g., 3418 in FIG. 34B), symbols #2 and #3 of S-SSB are mapped for S-PSS, symbols #1 and #4 of S-SSB are mapped for S-SSS, and symbols #5, #6, #7, #8, #9, #10 and #11 of S-SSB are mapped for PSBCH and DMRS.

[0513] In another approach, the S-SSB consists of 12 OFDM symbols (eg, X=8).

[0514] FIG 35A is a diagram illustrating yet another exemplary S-SSB 3500 according to an embodiment of the present disclosure. The embodiment of the S-SSB 3500 illustrated in FIG 35B is for illustrative purposes only. FIG 35B does not limit the scope of the present disclosure to any particular implementation.

[0515] As an example (e.g., 3501 in FIG. 35A), the #2 and #3 symbols of S-SSB are mapped for S-PSS, the #6 and #10 symbols of S-SSB are mapped for S-SSS, and the #1, #4, #5, #7, #8, #9, #11 and #12 symbols of S-SSB are mapped for PSBCH and DMRS.

[0516] As another example (e.g., 3502 in FIG. 35A), symbols #2 and #3 of S-SSB are mapped for S-PSS, symbols #11 and #12 of S-SSB are mapped for S-SSS, and symbols #1, #4, #5, #6, #7, #8, #9 and #10 of S-SSB are mapped for PSBCH and DMRS.

[0517] As another example (e.g., 3503 in FIG. 35A), symbols #2 and #3 of S-SSB are mapped for S-PSS, symbols #7 and #8 of S-SSB are mapped for S-SSS, and symbols #1, #4, #5, #6, #9, #10, #11 and #12 of S-SSB are mapped for PSBCH and DMRS.

[0518] As another example (e.g., 3504 in FIG. 35A), the #2 and #3 symbols of S-SSB are mapped for S-PSS, the #8 and #9 symbols of S-SSB are mapped for S-SSS, and the #1, #4, #5, #6, #7, #10, #11 and #12 symbols of S-SSB are mapped for PSBCH and DMRS.

[0519] As another example (e.g., 3505 in FIG. 35A), the #2 and #3 symbols of the S-SSB are mapped for the S-PSS, the #5 and #9 symbols of the S-SSB are mapped for the S-SSS, and the #1, #4, #6, #7, #8, #10, #11 and #12 symbols of the S-SSB are mapped for the PSBCH and DMRS.

[0520] As another example (e.g., 3506 in FIG. 35A), symbols #1 and #2 of S-SSB are mapped for S-PSS, symbols #11 and #12 of S-SSB are mapped for S-SSS, and symbols #3, #4, #5, #6, #7, #8, #9 and #10 of S-SSB are mapped for PSBCH and DMRS.

[0521] As another example (e.g., 3507 in FIG. 35A), the #1 and #2 symbols of S-SSB are mapped for S-PSS, the #6 and #9 symbols of S-SSB are mapped for S-SSS, and the #3, #4, #5, #7, #8, #10, #11 and #12 symbols of S-SSB are mapped for PSBCH and DMRS.

[0522] As another example (e.g., 3508 in FIG. 35A), symbols #1 and #2 of S-SSB are mapped for S-PSS, symbols #5 and #10 of S-SSB are mapped for S-SSS, and symbols #3, #4, #6, #7, #8, #9, #11 and #12 of S-SSB are mapped for PSBCH and DMRS.

[0523] As another example (e.g., 3509 in FIG. 35A), symbols #1 and #2 of S-SSB are mapped for S-PSS, symbols #7 and #8 of S-SSB are mapped for S-SSS, and symbols #3, #4, #5, #6, #9, #10, #11 and #12 of S-SSB are mapped for PSBCH and DMRS.

[0524] FIG. 35B is a diagram illustrating yet another exemplary S-SSB 3520 according to an embodiment of the present disclosure. The embodiment of the S-SSB 3520 illustrated in FIG. 35B is for illustrative purposes only. FIG. 35B does not limit the scope of the present disclosure to any particular embodiment.

[0525] As another example (e.g., 3510 in FIG. 35B), symbols #1 and #2 of S-SSB are mapped for S-PSS, symbols #3 and #4 of S-SSB are mapped for S-SSS, and symbols #5, #6, #7, #8, #9, #10, #11 and #12 of S-SSB are mapped for PSBCH and DMRS.

[0526] As another example (e.g., 3511 in FIG. 35B), symbols #1 and #2 of S-SSB are mapped for S-PSS, symbols #4 and #5 of S-SSB are mapped for S-SSS, and symbols #3, #6, #7, #8, #9, #10, #11 and #12 of S-SSB are mapped for PSBCH and DMRS.

[0527] As another example (e.g., 3512 in FIG. 35B), symbols #1 and #2 of S-SSB are mapped for S-PSS, symbols #5 and #6 of S-SSB are mapped for S-SSS, and symbols #3, #4, #7, #8, #9, #10, #11 and #12 of S-SSB are mapped for PSBCH and DMRS.

[0528] As another example (e.g., 3513 in FIG. 35B), symbols #1 and #2 of S-SSB are mapped for S-PSS, symbols #6 and #7 of S-SSB are mapped for S-SSS, and symbols #3, #4, #5, #8, #9, #10, #11 and #12 of S-SSB are mapped for PSBCH and DMRS.

[0529] As another example (e.g., 3514 in FIG. 35B), symbols #1 and #2 of S-SSB are mapped for S-PSS, symbols #9 and #10 of S-SSB are mapped for S-SSS, and symbols #3, #4, #5, #6, #7, #8, #11 and #12 of S-SSB are mapped for PSBCH and DMRS.

[0530] As another example (e.g., 3515 in FIG. 35B), symbols #1 and #2 of S-SSB are mapped for S-PSS, symbols #6 and #9 of S-SSB are mapped for S-SSS, and symbols #3, #4, #5, #7, #8, #10, #11 and #12 of S-SSB are mapped for PSBCH and DMRS.

[0531] As another example (e.g., 3516 in FIG. 35B), symbols #1 and #2 of S-SSB are mapped for S-PSS, symbols #6 and #10 of S-SSB are mapped for S-SSS, and symbols #3, #4, #5, #7, #8, #9, #11 and #12 of S-SSB are mapped for PSBCH and DMRS.

[0532] As another example (e.g., 3517 in FIG. 35B), symbols #1 and #2 of S-SSB are mapped for S-PSS, symbols #5 and #8 of S-SSB are mapped for S-SSS, and symbols #3, #4, #6, #7, #9, #10, #11 and #12 of S-SSB are mapped for PSBCH and DMRS.

[0533] As another example (e.g., 3518 in FIG. 35B), symbols #2 and #3 of S-SSB are mapped for S-PSS, symbols #1 and #4 of S-SSB are mapped for S-SSS, and symbols #5, #6, #7, #8, #9, #10, #11 and #12 of S-SSB are mapped for PSBCH and DMRS. In another approach, the S-SSB consists of 13 OFDM symbols (eg, X=9).

[0534] FIG 36A is a diagram illustrating yet another exemplary S-SSB 3600 according to an embodiment of the present disclosure. The embodiment of the S-SSB 3600 illustrated in FIG 36A is for illustrative purposes only. FIG 36A does not limit the scope of the present disclosure to any particular implementation.

[0535] As an example (e.g., 3601 in FIG. 36A), symbols #2 and #3 of S-SSB are mapped for S-PSS, symbols #6 and #11 of S-SSB are mapped for S-SSS, and symbols #1, #4, #5, #7, #8, #9, #10, #12 and #13 of S-SSB are mapped for PSBCH and DMRS.

[0536] As another example (e.g., 3602 in FIG. 36A), symbols #2 and #3 of S-SSB are mapped for S-PSS, symbols #12 and #13 of S-SSB are mapped for S-SSS, and symbols #1, #4, #5, #6, #7, #8, #9, #10 and #11 of S-SSB are mapped for PSBCH and DMRS.

[0537] As another example (e.g., 3603 in FIG. 36A), the #2 and #3 symbols of S-SSB are mapped for S-PSS, the #8 and #9 symbols of S-SSB are mapped for S-SSS, and the #1, #4, #5, #6, #7, #10, #11, #12 and #13 symbols of S-SSB are mapped for PSBCH and DMRS.

[0538] As another example (e.g., 3604 in FIG. 36A), symbols #2 and #3 of S-SSB are mapped for S-PSS, symbols #7 and #10 of S-SSB are mapped for S-SSS, and symbols #1, #4, #5, #6, #8, #9, #11, #12 and #13 of S-SSB are mapped for PSBCH and DMRS.

[0539] As another example (e.g., 3605 in FIG. 36A), symbols #2 and #3 of S-SSB are mapped for S-PSS, symbols #7 and #8 of S-SSB are mapped for S-SSS, and symbols #1, #4, #5, #6, #9, #10, #11, #12 and #13 of S-SSB are mapped for PSBCH and DMRS.

[0540] As another example (e.g., 3606 in FIG. 36A), symbols #1 and #2 of S-SSB are mapped for S-PSS, symbols #12 and #13 of S-SSB are mapped for S-SSS, and symbols #3, #4, #5, #6, #7, #8, #9, #10 and #11 of S-SSB are mapped for PSBCH and DMRS.

[0541] As another example (e.g., 3607 in FIG. 36A), symbols #1 and #2 of S-SSB are mapped for S-PSS, symbols #6 and #10 of S-SSB are mapped for S-SSS, and symbols #3, #4, #5, #7, #8, #9, #11, #12 and #13 of S-SSB are mapped for PSBCH and DMRS.

[0542] As another example (e.g., 3608 in FIG. 36A), the #1 and #2 symbols of S-SSB are mapped for S-PSS, the #8 and #9 symbols of S-SSB are mapped for S-SSS, and the #3, #4, #5, #6, #7, #10, #11, #12 and #13 symbols of S-SSB are mapped for PSBCH and DMRS.

[0543] As another example (e.g., 3609 in FIG. 36A), symbols #1 and #2 of S-SSB are mapped for S-PSS, symbols #7 and #8 of S-SSB are mapped for S-SSS, and symbols #3, #4, #5, #6, #9, #10, #11, #12 and #13 of S-SSB are mapped for PSBCH and DMRS.

[0544] FIG. 36B is a diagram illustrating yet another exemplary S-SSB 3620 according to an embodiment of the present disclosure. The embodiment of the S-SSB 3620 illustrated in FIG. 36B is for illustrative purposes only. FIG. 36B does not limit the scope of the present disclosure to any particular embodiment.

[0545] As another example (e.g., 3610 in FIG. 36B), symbols #2 and #3 of S-SSB are mapped for S-PSS, symbols #4 and #5 of S-SSB are mapped for S-SSS, and symbols #1, #6, #7, #8, #9, #10, #11, #12 and #13 of S-SSB are mapped for PSBCH and DMRS.

[0546] As another example (e.g., 3611 in FIG. 36B), symbols #2 and #3 of S-SSB are mapped for S-PSS, symbols #5 and #6 of S-SSB are mapped for S-SSS, and symbols #1, #4, #7, #8, #9, #10, #11, #12 and #13 of S-SSB are mapped for PSBCH and DMRS.

[0547] As another example (e.g., 3612 in FIG. 36B), symbols #2 and #3 of S-SSB are mapped for S-PSS, symbols #6 and #7 of S-SSB are mapped for S-SSS, and symbols #1, #4, #5, #8, #9, #10, #11, #12 and #13 of S-SSB are mapped for PSBCH and DMRS.

[0548] As another example (e.g., 3613 in FIG. 36B), symbols #2 and #3 of S-SSB are mapped for S-PSS, symbols #10 and #11 of S-SSB are mapped for S-SSS, and symbols #1, #4, #5, #6, #7, #8, #9, #12 and #13 of S-SSB are mapped for PSBCH and DMRS.

[0549] As another example (e.g., 3614 in FIG. 36B), symbols #2 and #3 of S-SSB are mapped for S-PSS, symbols #6 and #9 of S-SSB are mapped for S-SSS, and symbols #1, #4, #5, #7, #8, #10, #11, #12 and #13 of S-SSB are mapped for PSBCH and DMRS.

[0550] As another example (e.g., 3615 in FIG. 36B), symbols #2 and #3 of S-SSB are mapped for S-PSS, symbols #5 and #9 of S-SSB are mapped for S-SSS, and symbols #1, #4, #6, #7, #8, #10, #11, #12 and #13 of S-SSB are mapped for PSBCH and DMRS.

[0551] As another example (e.g., 3616 in FIG. 36B), symbols #2 and #3 of S-SSB are mapped for S-PSS, symbols #5 and #11 of S-SSB are mapped for S-SSS, and symbols #1, #4, #6, #7, #8, #9, #10, #12 and #13 of S-SSB are mapped for PSBCH and DMRS.

[0552] As another example (e.g., 3617 in FIG. 36B), symbols #2 and #3 of S-SSB are mapped for S-PSS, symbols #5 and #10 of S-SSB are mapped for S-SSS, and symbols #1, #4, #6, #7, #8, #9, #11, #12 and #13 of S-SSB are mapped for PSBCH and DMRS.

[0553] As another example (e.g., 3618 in FIG. 36B), symbols #2 and #3 of S-SSB are mapped for S-PSS, symbols #4 and #5 of S-SSB are mapped for S-SSS, and symbols #1, #6, #7, #8, #9, #10, #11, #12 and #13 of S-SSB are mapped for PSBCH and DMRS. In one embodiment, the mapping of S-SSBs within a slot is fixed.

[0554] In one approach, the first symbol of the S-SSB (e.g., S-SSB symbol #1 in the example first embodiment of the present disclosure) is aligned with the first OFDM symbol of the slot. For example, if the total number of symbols for the S-SSB is less than or equal to the total number of OFDM symbols of the slot (e.g., 14 symbols for a normal CP or 12 symbols for an extended CP), the S-SSB starts with the first OFDM symbol of the slot and the remaining symbols (e.g., the last one or more symbols in the slot) can be used for other purposes (e.g., TX / RX switch gap and / or multiplexing with other signals / channels).

[0555] In another approach, the first symbol of the S-SSB (e.g., S-SSB symbol #1 in the example first embodiment of the present disclosure) is aligned with the second OFDM symbol of the slot. For example, the S-SSB starts with the second OFDM symbol of the slot, and the first symbol of the slot is reserved (e.g., for AGC purposes) and the remaining symbols (e.g., the last one or more symbols in the slot) can be used for other purposes (e.g., TX / RX switch gap and / or multiplexing with other signals / channels).

[0556] In yet another approach, the last symbol of the S-SSB is aligned with the second last OFDM symbol of the slot. For example, if the total number of symbols for the S-SSB is less than or equal to the total number of OFDM symbols of the slot (e.g., 14 symbols for the normal CP or 12 symbols for the extended CP), the S-SSB is terminated from the second last symbol of the slot (e.g., the 13th symbol of the slot for the normal CP or the 11th symbol of the slot for the extended CP), the last symbol of the slot is reserved (e.g., for a TX / RX switch gap), and the remaining symbols (e.g., the first one or more symbols in the slot) (if any) can be used for other purposes (e.g., AGC and / or multiplexing with other signals / channels).

[0557] In another embodiment, the mapping of S-SSBs to slots is variable / configurable.

[0558] In one approach, if the total number of symbols for the S-SSB is less than or equal to the total number of OFDM symbols in the slot (e.g., 14 symbols for the general CP or 12 symbols for the extended CP), the S-SSB can start at any symbol in the slot (e.g., the last symbol is reserved for TX / RX switch gap purposes) or at a subset of the slot. In one aspect, one of the starting positions in the slot where the S-SSB starts is pre-configured in the V2X UE attempting to synchronize to the synchronization source. In another aspect, one of the starting positions in the slot where the S-SSB starts is indicated to the V2X UE attempting to synchronize to the synchronization source. An example of this approach is illustrated in FIG. 37.

[0559] Figure 37 is a diagram illustrating an example S-SSB location within a slot 3700 according to an embodiment of the present disclosure. The embodiment of the S-SSB location within the slot 3700 shown in Figure 37 is for illustration only. Figure 37 does not limit the scope of the present disclosure to any particular implementation.

[0560] At least one of the following examples may be supported for indicating / pre-configuring the variation / configuration of S-SSB mapping within a slot (e.g., by indicating the starting position of the S-SSB within a slot):

[0561] As an example, an indication of the variation / configuration of the S-SSB mapping may consist of a PSBCH payload, e.g., a field in the PSBCH payload indicating the starting position of the S-SSB within a slot.

[0562] In another example, the S-SSB mapping variation / configuration is pre-configured in the V2X UE attempting to synchronize to the synchronization source.

[0563] In yet another example, an indication of the S-SSB mapping variation / configuration is conveyed by a DMRS sequence of the PSBCH within the S-SSB.

[0564] In yet another example, an indication of the S-SSB mapping variation / configuration may be conveyed by a combination of the PSBCH payload and the PSBCH DMRS sequence within the S-SSB.

[0565] In one embodiment, an S-SSB burst set may include at least one S-SSB and operates on a periodically transmitted unit in the time domain.

[0566] In a first approach for burst set configuration, an S-SSB burst set can include a single S-SSB. For example, the S-SSB can be transmitted using a single beam operation, such as a carrier frequency below 6 GHz. In one consideration, a time domain location of the single S-SSB can be configured, and this location is indicated in the signal / channel (e.g., the contents of the PSBCH) of the S-SSB.

[0567] In a second approach for burst set configuration, an S-SSB burst set can include many S-SSBs, and the maximum number of S-SSBs in an S-SSB burst set can be determined based on the carrier frequency range and / or the SCS of the S-SSBs. For example, the S-SSBs can be transmitted in a multiple beam operation, a repetition operation mode, or a combination of multiple beam operation and repetition operation.

[0568] In an example of the second approach, many S-SSBs in an S-SSB burst set have the same configuration method, e.g., the S-SSB structure is the same within an S-SSB burst set, and slots containing S-SSBs are repeated to configure the S-SSB burst set.

[0569] In another example of the second approach, many S-SSBs in an S-SSB burst set have different configuration methods from each other, for example, the S-SSB structures can be different within an S-SSB burst set, and different examples of the present disclosure are connected together to configure the S-SSB burst set.

[0570] In the first approach for the S-SSBs actually transmitted in a burst set, the number of S-SSBs actually transmitted in a burst set is equal to the maximum number of S-SSBs in the burst set, and when the number of S-SSBs in a burst set is defined accordingly, all burst sets must contain the maximum number of S-SSBs for transmission.

[0571] In a second approach for S-SSBs actually transmitted in a burst set, the number of S-SSBs actually transmitted in a burst set is less than or equal to the maximum number of S-SSBs in the burst set, and the number of S-SSBs actually transmitted in the burst set is indicated or known to the V2X UE. As an example of the information related to the number of S-SSBs actually transmitted in a burst set, the number of S-SSBs actually transmitted in a burst set may be explicitly indicated. One consideration for this example is that the start position and / or end position of the S-SSBs in the burst set may be fixed or indicated, where the number of S-SSBs in the burst set is as indicated.

[0572] Another example of the information regarding the number of S-SSBs actually transmitted in the burst set can be implicitly indicated from a bitmap indicating the S-SSBs actually transmitted in the burst set. In one example of an indication method, the indication can comprise PSBCH content. In another example of an indication method, the indication can comprise preconfigured information regarding, for example, a preconfigured BWP.

[0573] In a third approach to S-SSBs actually transmitted in a burst set, the number of S-SSBs actually transmitted in a burst set is fixed, regardless of the maximum number of S-SSBs in the burst set. One consideration of this approach is that the fixed number of S-SSBs actually transmitted can vary depending on the carrier frequency range and / or the SCS of the S-SSB. For example, the fixed number of S-SSBs actually transmitted in a burst set is 1.

[0574] Although the present disclosure has been described in exemplary embodiments, various changes and modifications may be suggested to those skilled in the art, and the present disclosure is intended to include such changes and modifications that fall within the scope of the appended claims.

[0575] Nothing in this application should be construed as indicating any particular element, step, or function as a required element to be included in the claim. The scope of the invention is defined solely by the claims. Also, no claim is intended to be construed under 35 U.S.C. § 112(f) unless the precise words "means for" are joined to a participle. [Explanation of symbols]

[0576] 100 Wireless Network 101, 102, 103 gNB 111~116UE 120 Coverage Area 125 Coverage Area 130 Network

Claims

1. A first user equipment (UE) of a wireless communication system, comprising: As a processor, a sidelink primary synchronization signal (S-PSS) based on the first sequence; and and identifying a sidelink secondary synchronization signal (S-SSS) based on the second sequence; the processor configured to identify a physical sidelink broadcast channel (PSBCH) and a demodulation reference signal (DMRS) for the PSBCH; a transceiver operatively connected to the processor and configured to transmit a sidelink synchronization signal and a physical broadcast channel block (S-SSB) including the S-PSS, the S-SSS, the PSBCH, and the DMRS for the PSBCH to a second UE; The first sequence for the S-PSS is defined by d_SPSS(n)=1-2*x(m), m=(n+22+43*N_GID^SL) mod 127, (0≦n<127); The x(m) is x(i+7)=(x(i+4)+x(i)) mod 2 (i=0, 1, ..., 119), and the initial condition of x(m) is given by x(6:0)=[1110110], The N_GID^SL is a SL synchronization ID group index, having a value of 0 or 1, for the first user equipment (UE).

2. The two symbols for the S-PSS are a second symbol and a third symbol in the S-SSB; the two symbols for the S-SSS are the fourth and fifth symbols in the S-SSB; The symbols for the PSBCH and the DMRS for the PSBCH are the first symbol, the sixth symbol, the seventh symbol, the eighth symbol, the ninth symbol, the tenth symbol, and the eleventh symbol in the S-SSB. A first user equipment (UE) according to claim 1, characterised in that

3. the length of the first sequence is 127; The length of the second sequence is 127. A first user equipment (UE) according to claim 1, characterised in that

4. 2. The first user equipment (UE) of claim 1, wherein the second sequence for the S-SSS is defined by d_SSSS(n)=(1-2*x_0(n_0))*(1-2*x_1(n_1)), n_0=(n+m_0) mod 127, n_1=(n+m_1) mod 127, m_0=15*|_N_ID / 112_|, m_1=N_ID mod 112, 0≦n<127.

5. A second user equipment (UE) of a wireless communication system, a transceiver configured to receive, from a first UE, a sidelink synchronization signal and physical broadcast channel block (S-SSB) including a sidelink primary synchronization signal (S-PSS) based on a first sequence, a sidelink secondary synchronization signal (S-SSS) based on a second sequence, a physical sidelink broadcast channel (PSBCH), and a demodulation reference signal (DMRS) for the PSBCH; a processor operatively connected to the transceiver, the processor configured to identify the S-PSS, the S-SSS, the PSBCH, and the DMRS from the S-SSB; Including, The first sequence for the S-PSS is defined by d_SPSS(n)=1-2*x(m), m=(n+22+43*N_GID^SL) mod 127, (0≦n<127); The x(m) is x(i+7)=(x(i+4)+x(i)) mod 2 (i=0, 1, ..., 119), and the initial condition of x(m) is given by x(6:0)=[1110110], The N_GID^SL is a SL synchronization ID group index, having a value of 0 or 1, for a second user equipment (UE).

6. The two symbols for the S-PSS are a second symbol and a third symbol in the S-SSB; the two symbols for the S-SSS are the fourth and fifth symbols in the S-SSB; The symbols for the PSBCH and the DMRS for the PSBCH are the first symbol, the sixth symbol, the seventh symbol, the eighth symbol, the ninth symbol, the tenth symbol, and the eleventh symbol in the S-SSB. A second user equipment (UE) according to claim 5, characterised in that

7. the length of the first sequence is 127; The second user equipment (UE) of claim 5, wherein the second sequence has a length of 127.

8. 6. The second user equipment (UE) of claim 5, wherein the second sequence for the S-SSS is defined by d_SSSS(n)=(1-2*x_0(n_0))*(1-2*x_1(n_1)), n_0=(n+m_0) mod 127, n_1=(n+m_1) mod 127, m_0=15*|_N_ID / 112_|, m_1=N_ID mod 112, 0≦n<127.

9. 1. A method in a first user equipment (UE) in a wireless communication system, comprising: identifying a sidelink primary synchronization signal (S-PSS) based on a first sequence and a sidelink secondary synchronization signal (S-SSS) based on a second sequence; identifying a physical sidelink broadcast channel (PSBCH) and a demodulation reference signal (DMRS) for the PSBCH; transmitting a sidelink synchronization signal and physical broadcast channel block (S-SSB) including the S-PSS, the S-SSS, the PSBCH, and the DMRS for the PSBCH to a second UE; Including, The first sequence for the S-PSS is defined by d_SPSS(n)=1-2*x(m), m=(n+22+43*N_GID^SL) mod 127, (0≦n<127); The x(m) is x(i+7)=(x(i+4)+x(i)) mod 2 (i=0, 1, ..., 119), and the initial condition of x(m) is given by x(6:0)=[1110110], The N_GID^SL is a SL synchronization ID group index and has a value of 0 or 1.

10. The two symbols for the S-PSS are a second symbol and a third symbol in the S-SSB; determining a set of SL-SID and resources, the two symbols for the S-SSS being the fourth and fifth symbols in the S-SSB; and identifying the S-SSB based on the SL-SID and the set of resources; The method of claim 9, wherein the symbols for the PSBCH and the DMRS for the PSBCH are the first symbol, the sixth symbol, the seventh symbol, the eighth symbol, the ninth symbol, the tenth symbol and the eleventh symbol in the S-SSB.

11. the length of the first sequence is 127; The method of claim 9 , wherein the second sequence has a length of 127.

12. 10. The method of claim 9, wherein the second sequence for the S-SSS is defined by d_SSSS(n)=(1-2*x_0(n_0))*(1-2*x_1(n_1)), n_0=(n+m_0) mod 127, n_1=(n+m_1) mod 127, m_0=15*|_N_ID / 112_|, m_1=N_ID mod 112, 0≦n<127.

Images