Display substrate and its manufacturing method, display device

Abstract

The present disclosure relates to a display substrate, a manufacturing method thereof, and a display device. The display substrate includes a base substrate, a shift register unit, a first clock signal line, and a second clock signal line. The shift register unit includes an input circuit, an output circuit, a first control circuit, a second control circuit, and a voltage regulator circuit. A first pole of a first noise reduction transistor of the second control circuit of the shift register unit and a first pole of a voltage regulator transistor of the voltage regulator circuit of the shift register unit are located on a first source-drain electrode layer. The first source-drain electrode layer includes a first transfer electrode. The first transfer electrode has a first portion and a second portion. The first portion is connected to the first pole of the first noise reduction transistor and the first pole of the voltage regulator transistor, and the second portion is connected to the gate of the first control transistor of the first control circuit. The wiring of the shift register unit is more simplified, which is advantageous for improving the space utilization of the display substrate and making it easier to achieve a narrow frame on the display substrate.

Description

[Technical field]

[0001] The embodiments of the present disclosure relate to a display substrate, a manufacturing method thereof, and a display device. [Background technology]

[0002] In recent years, display devices have been developing rapidly, and AMOLED (active-matrix organic light-emitting diode) display devices have attracted attention due to their bright colors, good viewing angles, high contrast, fast response speed, low power consumption, and other advantages. AMOLED display devices have a wide application space in multiple display fields such as mobile display, in-vehicle display, medical display, etc., and flexible AMOLED display devices are mainly applied in the deformable screen display field. With the gradual development of technology and the update of people's needs for display devices, screen shape design faces more and more new challenges. Summary of the Invention [Means for solving the problem]

[0003] At least one embodiment of the present disclosure provides a display substrate, the display substrate comprising: a base substrate having a display region and a peripheral region located on at least one side of the display region; and a shift register unit disposed in the peripheral region of the base substrate, a first clock signal line and a second clock signal line, the first clock signal line and the second clock signal line extending along a first direction on the base substrate and configured to provide a first clock signal and a second clock signal to the shift register unit, respectively; the shift register unit comprises an input circuit, an output circuit, a first control circuit, a second control circuit and a voltage regulator circuit, the input circuit being configured to input an input signal to a first node in response to the first clock signal; the first control circuit being connected to the first node and the second node and configured to control a level of the second node in response to the first clock signal; the second control circuit being connected to the first node and the second node and configured to control a level of the second node in response to the first clock signal; a gate of the first control transistor, a first pole of the first noise reduction transistor, and a first pole of the voltage regulator transistor are all connected to the first node, the first pole of the first noise reduction transistor, and the first pole of the voltage regulator transistor are located in a first source-drain electrode layer having a first transfer electrode, the first transfer electrode having a first portion extending in parallel to a second direction different from the first direction, and a second portion integrally formed with the first portion and extending in the first direction,A first end of the first portion is connected to a first pole of the first noise reduction transistor, a second end of the first portion is connected to a first pole of the voltage regulator transistor, and the second portion is connected to a gate of the first control transistor that is not in the same layer.

[0004] For example, in a display substrate according to at least one embodiment of the present disclosure, the first transfer electrode further includes a third portion extending parallel to the second direction, the third portion being connected to the second portion and arranged alongside the first portion in the first direction, the input circuit includes an input transistor, the orthogonal projection of an active layer of the input transistor on the base substrate is located between the orthogonal projection of an active layer of the first control transistor on the base substrate and the orthogonal projection of an active layer of the first noise reduction transistor on the base substrate, and a first pole of the input transistor is connected to an end of the third portion.

[0005] For example, in a display substrate according to at least one embodiment of the present disclosure, the first transfer electrode comprises the first node.

[0006] For example, a display substrate according to at least one embodiment of the present disclosure further includes a second transfer electrode, the first control circuit further includes a second control transistor, the second transfer electrode includes a first portion and a second portion parallel to the second direction, an end of the first portion of the second transfer electrode is connected to a first pole of the second control transistor, a second portion of the second transfer electrode is connected to a first pole of the first control transistor, and the second transfer electrode includes the second node.

[0007] For example, in a display substrate according to at least one embodiment of the present disclosure, the orthogonal projection of the active layer of the second control transistor on the base substrate is located on the side away from the display area of ​​the orthogonal projection of the active layer of the first control transistor on the base substrate.

[0008] For example, in a display substrate according to at least one embodiment of the present disclosure, the second control circuit further includes a second noise reduction transistor, an active layer of the second noise reduction transistor and an active layer of the first noise reduction transistor are located in a continuous first semiconductor layer, and the first semiconductor layer extends along a first direction, a gate of the second noise reduction transistor and a gate of the first noise reduction transistor extend in the second direction and are arranged side by side in the first direction, and the display substrate further includes the first connection wiring and the second connection wiring extending along the second direction. the first connection wiring and the second connection wiring are arranged in parallel, the first connection wiring and the second connection wiring each overlap the first transfer electrode, a first end of the first connection wiring is connected to a gate of the second noise reduction transistor, a second end of the first connection wiring is connected to an end of a second portion of the second transfer electrode which is not in the same layer, a first end of the second connection wiring is connected to the gate of the first noise reduction transistor, and a second end of the second connection wiring is connected to the second clock signal line to receive the second clock signal.

[0009] For example, in a display substrate according to at least one embodiment of the present disclosure, the orthogonal projections of the active layer of the second noise reduction transistor and the active layer of the first noise reduction transistor on the base substrate are located on a side closer to the display area than the orthogonal projection of the active layer of the first control transistor on the base substrate.

[0010] For example, in a display substrate according to at least one embodiment of the present disclosure, the shift register unit further includes a first insulating layer, a second insulating layer, and a third insulating layer, the first insulating layer being located between an active layer of the first control transistor and a gate of the first control transistor, the second insulating layer and the third insulating layer being located between the first transfer electrode and the gate of the first control transistor, the gate of the first control transistor being connected to a second portion of the first transfer electrode via a via hole penetrating the second insulating layer and the third insulating layer, and a second end of the first connection wiring being connected to an end of the second portion of the second transfer electrode via a via hole penetrating the second insulating layer and the third insulating layer.

[0011] For example, in a display substrate according to at least one embodiment of the present disclosure, the orthogonal projection of the active layer of the voltage regulator transistor on the base substrate is located on the side away from the display area of ​​the orthogonal projection of the active layer of the first control transistor on the base substrate.

[0012] For example, in a display substrate according to at least one embodiment of the present disclosure, the included angle between the first direction and the second direction is between 70° and 90°.

[0013] For example, in a display substrate according to at least one embodiment of the present disclosure, the first clock signal and the second clock signal line are located on a side of the shift register unit away from the display area.

[0014] For example, a display substrate according to at least one embodiment of the present disclosure further includes a first power supply line configured to provide a first voltage to the shift register unit, the first power supply line extending in the first direction on the base substrate and connected to the second control circuit, and a positive projection of the first power supply line on the base substrate is located on a side closer to the display area than a positive projection of the shift register unit on the base substrate.

[0015] For example, a display substrate according to at least one embodiment of the present disclosure further includes a second power supply line, the second power supply line extending in the first direction on the base substrate and configured to provide a second voltage to the shift register unit, a positive projection of the second power supply line on the base substrate being located between a positive projection of the first clock signal line and the second clock signal line on the base substrate and a positive projection of the shift register unit on the base substrate, and a gate of the voltage regulator transistor being connected to the second power supply line to receive the second voltage.

[0016] For example, in a display substrate according to at least one embodiment of the present disclosure, the second power supply line has a protrusion protruding in the second direction, and a second electrode of the second control transistor is connected to the protrusion in the second power supply line to receive the second voltage.

[0017] For example, in a display substrate according to at least one embodiment of the present disclosure, the input transistor has a first gate and a second gate arranged side by side, the first gate and the second gate of the input transistor are connected to a gate of the second control transistor, and the gate of the second control transistor is further connected to the first clock signal line, and the first clock signal line provides the first clock signal to the gate of the second control transistor and the first gate and the second gate of the input transistor.

[0018] For example, a display substrate according to at least one embodiment of the present disclosure further includes a third transfer electrode extending in the first direction, a first end of the third transfer electrode being connected to a gate of the second control transistor and a first gate and a second gate of the input transistor through a via hole penetrating an insulating layer, and a second end of the third transfer electrode being connected to a second pole of the first control transistor.

[0019] For example, in a display substrate according to at least one embodiment of the present disclosure, the shift register unit further includes an output control circuit, which is configured to control the level of the output terminal by controlling the level of the second node, and the output control circuit includes an output control transistor and a first capacitor, the orthogonal projection of the first capacitor on the base substrate is located on a side closer to the display area than the orthogonal projection of the active layer of the output control transistor on the base substrate, and the orthogonal projection of the first capacitor on the base substrate at least partially overlaps with the orthogonal projection of the first power line on the base substrate.

[0020] For example, in a display substrate according to at least one embodiment of the present disclosure, the first capacitor has a rectangular shape.

[0021] For example, a display substrate according to at least one embodiment of the present disclosure further includes a fourth transfer electrode, the fourth transfer electrode being connected to a first pole of the second noise reduction transistor and a first pole of the output control transistor, a gate of the second noise reduction transistor being connected to a gate of the output control transistor, and the fourth transfer electrode also including the second node.

[0022] For example, a display substrate according to at least one embodiment of the present disclosure further includes a fifth transfer electrode, the output circuit includes an output transistor and a second capacitor, the orthogonal projection of the second capacitor on the base substrate is located on the side away from the display area of ​​the orthogonal projection of the first power line on the base substrate, a first pole of the output transistor is connected to a first end of the fifth transfer electrode, and a gate of the first noise reduction transistor is connected to the fifth transfer electrode through a via hole penetrating an insulating layer.

[0023] For example, in a display substrate according to at least one embodiment of the present disclosure, the second capacitor is rectangular.

[0024] For example, a display substrate according to at least one embodiment of the present disclosure further includes a sixth transfer electrode extending along the second direction, wherein a gate of the output transistor is connected to a first end of the sixth transfer electrode through a via hole penetrating an insulating layer, a second end of the sixth transfer electrode is connected to a second pole of the voltage regulator transistor, and the sixth transfer electrode includes the third node.

[0025] For example, a display substrate according to at least one embodiment of the present disclosure further includes a seventh transfer electrode, a first end of the seventh transfer electrode being connected to a second pole of the output control transistor, a second end of the seventh transfer electrode being connected to a second pole of the output transistor, and the second pole of the output transistor being connected to a second pole of an input transistor of a lower-stage shift register unit adjacent to the shift register unit.

[0026] For example, in a display substrate according to at least one embodiment of the present disclosure, an active layer of the output control transistor and at least a portion of an active layer of the output transistor are located in a continuous second semiconductor layer, and the second semiconductor layer extends in the first direction, a gate of the output control transistor and a gate of the output transistor extend in the second direction and are arranged side by side in the first direction, and a first pole of the output control transistor is connected to the first power supply line to receive the first voltage.

[0027] At least one embodiment of the present disclosure further provides a display device including the display substrate according to any of the above embodiments.

[0028] At least one embodiment of the present disclosure further provides a method for manufacturing a display substrate, the method including the steps of: providing a base substrate having a display region and a peripheral region surrounding at least the display region; and forming a shift register unit, a first clock signal line, a second clock signal line, a first power supply line and a second power supply line in the peripheral region of the base substrate, the steps including: forming a semiconductor layer on the base substrate, and patterning the semiconductor layer to form active layers of a plurality of transistors in each circuit of the shift register; forming a first insulating material layer on a side of the active layers of the plurality of transistors away from the base substrate, and patterning the first insulating material layer to form a first insulating layer having via holes; forming a first conductive material layer on a side of the first insulating layer away from the base substrate, and patterning the first conductive material to form gates of the plurality of transistors, a plurality of connection wirings and first poles of a plurality of capacitors in each circuit; forming a second insulating material layer on a side of the gates of the plurality of transistors away from the base substrate, and patterning the second insulating material layer to form via holes. forming a second insulating layer comprising: a second conductive material layer on a side of the second insulating layer away from the base substrate and patterning the second conductive material to form second poles of the plurality of capacitors; forming a third insulating material layer on a side of the second insulating layer and a side of a second capacitor plate of the plurality of capacitors away from the base substrate and patterning the third insulating material layer to form a third insulating layer comprising a via hole; forming a third conductive material layer on a side of the third insulating layer away from the base substrate and patterning the third insulating material layer to form a third insulating layer comprising a via hole; and patterning a third conductive material to form first and second poles of the plurality of transistors, a plurality of transfer electrodes, the first clock signal line, the second clock signal line, the first power supply line, and the second power supply line, wherein the first and second poles of the transistors are connected to an active layer of the transistor through a via hole penetrating the first insulating layer, the second insulating layer, and the third insulating layer, and each of the transistors and each of the capacitors are connected to each other through the plurality of connection wirings or the plurality of transfer electrodes,They are connected to each other through via holes penetrating the second insulating layer and the third insulating layer, and are also connected to the first power supply line, the second power supply line, the first clock signal line, and the second clock signal line.

[0029] In order to clearly explain the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments are briefly described below. It is obvious that the drawings in the following description are only related to some embodiments of the present disclosure, and do not limit the present disclosure. [Brief description of the drawings]

[0030] [Figure 1A] FIG. 2 is a schematic diagram of the overall circuit structure of a display panel. [Figure 1B] FIG. 2 is a circuit diagram of a shift register unit. [Figure 1C] FIG. 1C is a signal timing diagram when the shift register unit shown in FIG. 1B is operating. [Figure 1D] FIG. 1C is a schematic layout diagram of the shift register unit shown in FIG. 1B on a display substrate. [Diagram 2] FIG. 2 is a schematic diagram of a display substrate layout in accordance with at least one embodiment of the present disclosure. [Diagram 3] FIG. 2 is a plan view of a semiconductor layer of a display substrate in accordance with at least one embodiment of the present disclosure. [Figure 4] 2 is a plan view of a first conductive layer of a display substrate in accordance with at least one embodiment of the present disclosure. [Diagram 5] FIG. 2 is a plan view of a second conductive layer of a display substrate in accordance with at least one embodiment of the present disclosure. [Figure 6] 2 is a distribution diagram of via holes in a display substrate in accordance with at least one embodiment of the present disclosure. [Figure 7] FIG. 2 is a plan view of a third conductive layer of a display substrate in accordance with at least one embodiment of the present disclosure. [Figure 8] 3 is a cross-sectional view taken along the AB direction of the display substrate shown in FIG. 2. [Figure 9]1 is a schematic diagram of a display device in accordance with at least one embodiment of the present disclosure. [Figure 10] 1 is a flowchart of a method for manufacturing a display substrate in accordance with at least one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0031] In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the following will clearly and completely describe the technical solutions of the embodiments of the present disclosure with reference to the drawings of the embodiments of the present disclosure. It is obvious that the described embodiments are only some embodiments of the present disclosure, and are not all embodiments. Based on the described embodiments of the present disclosure, all other embodiments that a person skilled in the art can obtain without creative labor belong to the protection scope of the present disclosure.

[0032] Unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meaning that one skilled in the art can understand. The terms "first", "second" and similar terms used in this disclosure do not indicate any order, number or importance, but are merely used to distinguish different components. Similarly, similar terms such as "one", "1" or "the" do not limit the number, but mean that there is at least one. Similar terms such as "comprise" or "include" mean that the element or member described before the term includes the element or member listed after the term and their equivalents, but does not exclude other elements or members. Similar terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but also include electrical connections, whether direct or indirect connections. "Top", "bottom", "left", "right", etc. are only used to indicate relative positional relationships, and if the absolute position of the object being described changes, the relative positional relationships may change correspondingly.

[0033] The present disclosure will be described below by means of some specific embodiments. In order to ensure that the following description of the embodiments of the present invention is clear and concise, detailed descriptions of known functions and known components may be omitted. When any component of the embodiments of the present invention appears in more than one drawing, the component is represented by the same reference number in each drawing.

[0034] In the display technology field, for example, a pixel array of a liquid crystal display panel or an organic light emitting diode (OLED) display panel usually includes a number of rows of grid lines and a number of columns of data lines intersecting with the grid lines. The grid lines can be driven by a bound integrated driving circuit. In recent years, with the continuous improvement of the manufacturing process of amorphous silicon thin film transistors or oxide thin film transistors, the grid line driving circuit can be directly integrated on the thin film transistor array substrate to form a GOA (Gate driver On Array) to drive the grid lines. For example, a GOA including a number of cascaded shift register units is used to provide switching state voltage signals (scanning signals) to the grid lines of the number of rows in the pixel array, for example, to control the number of rows of grid lines to be turned on in sequence, and the data lines provide data signals to the pixel units of the corresponding rows in the pixel array to form the gray scale voltages required for each gray scale of the display image formed in each pixel unit, and thus display one frame image. The size of the GOA has a direct impact on the size of the frame of the display panel. The smaller the frame of the display panel, the higher the screen occupancy rate, and therefore the better the display effect.The overall circuit structure of the display panel will be described below with reference to the drawings.

[0035] 1A is a schematic diagram of the overall circuit structure of a display panel. For example, as shown in FIG. 1A, the display panel includes a base substrate 101, which includes a display area (i.e., pixel array area) 102 and a peripheral area 106 located around the display area 102. For example, the peripheral area 106 surrounds the display area 102. The display area 102 includes pixel units 103 arranged in an array, and the peripheral area 106 includes a shift register unit 104, and a plurality of cascaded shift register units 104 form a gate driving circuit to provide gate scanning signals, for example, shifted row by row, to the pixel units 103 arranged in the array in the display area 102 of the display panel. The peripheral area 106 further includes a light-emitting control unit 105, and a plurality of cascaded light-emitting control units 105 form a light-emitting control array to provide light-emitting control signals, for example, shifted row by row, to the pixel units 103 arranged in the array in the display area 102 of the display panel.

[0036] As shown in Fig. 1A, the display panel further includes a data driving chip IC located in the peripheral area 106, and the data driving chip IC is configured to provide data signals to the pixel units 103 arranged in the array. Data lines D1-DN (N is an integer greater than 1) connected to the data driving chip IC pass through the display area 102 in a vertical direction (e.g., vertical direction in the figure) to respectively provide data signals to the pixel units 103 in each column. Grid lines G1-GM (M is an integer greater than 1) connected to the shift register unit 104 pass through the display area 102 in a horizontal direction (e.g., horizontal direction in the figure), and emission control lines E1-EM (M is an integer greater than 1) connected to the emission control unit 105 pass through the display area 102 in a horizontal direction to provide gate scanning signals and emission control signals to the pixel units 103 arranged in the array.

[0037] For example, each pixel unit 103 may include a pixel circuit having a circuit structure such as 7T1C, 8T2C or 4T1C in the art and a light-emitting element, and the pixel circuit operates to drive the light-emitting element to emit light under the control of the data signal transmitted by the data line, the gate scanning signal transmitted by the grid line and the light-emitting control signal transmitted by the light-emitting control line E1-EM to realize operations such as display. The light-emitting element may be, for example, an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED).

[0038] Fig. 1B is a circuit diagram of the shift register unit. Fig. 1C is a signal timing diagram when the shift register unit shown in Fig. 1B is operating. Hereinafter, the operation process of the shift register unit will be briefly described with reference to Figs. 1B and 1C.

[0039] As shown in FIG. 1B, the shift register unit 104 includes eight transistors (an input transistor T1, a first control transistor T2, a second control transistor T3, an output control transistor T4, an output transistor T5, a first noise reduction transistor T7, a second noise reduction transistor T6 and a voltage regulator transistor T8) and two capacitors (a first capacitor C1 and a second capacitor C2). For example, when multiple shift register units 104 are cascaded, the second pole of the input transistor T1 in the first stage shift register unit is connected to an input terminal IN that is connected to a trigger signal line GSTV (not shown) and configured to receive a trigger signal as an input signal, and the input terminal IN connected to the second pole of the input transistor T1 in each other stage shift register unit 104 (e.g., except for the first stage shift register unit) is electrically connected to the output terminal of the previous stage shift register unit 104 to receive the output signal output by the output terminal GOUT of the previous stage shift register unit 104 as an input signal, thereby realizing shift output to scan the array of pixel units 103 in the display area 102, for example, row by row.

[0040] In addition, in the example shown in FIG. 1B, the shift register unit 104 further includes a first clock signal end CK and a second clock signal end CB, where GCK represents the first clock signal line and GCB represents the second clock signal line. For example, the first clock signal end CK is connected to the second clock signal line GCB or the first clock signal line GCK to receive the first clock signal. For example, when the first clock signal end CK is connected to the first clock signal line GCK, the first clock signal line GCK provides the first clock signal, and when the first clock signal end CK is connected to the second clock signal line GCB, the second clock signal line GCB provides the first clock signal, and the specifics are determined according to the actual situation, and the embodiment of the present disclosure does not limit this. The second clock signal end CB is connected to the second clock signal line GCB or the first clock signal line GCK to receive the second clock signal. Hereinafter, the first clock signal terminal CK is connected to the first clock signal line GCK to receive the first clock signal, and the second clock signal terminal CB is connected to the second clock signal line GCB to receive the second clock signal, but the embodiment of the present disclosure is not limited thereto. For example, the first clock signal line GCK and the second clock signal line GCB can use a pulse signal with a duty cycle greater than 50%, and the two are spaced apart by, for example, half a cycle, VGH represents the first power line and the first voltage provided by the first power line, for example, the first voltage is a DC high level, VGL represents the second power line and the second voltage provided by the second power line, for example, the second voltage is a DC low level, and the first voltage is greater than the second voltage, and N1, N2 and N3 respectively represent the first node, the second node and the third node in the circuit schematic diagram.

[0041] 1B, the gate of the input transistor T1 is connected to a first clock signal terminal CK (the first clock signal terminal CK is connected to a first clock signal line GCK) to receive a first clock signal, the second pole of the input transistor T1 is connected to an input terminal IN, and the first pole of the input transistor T1 is connected to a first node N1. For example, if the shift register unit 104 is a first-stage shift register unit, the input terminal IN is connected to a trigger signal line GSTV (not shown) to receive a trigger signal, and if the shift register unit 104 is a shift register unit of each stage other than the first-stage shift register, the input terminal IN is connected to the output terminal GOUT of the upper shift register unit.

[0042] The gate of the first control transistor T2 is connected to the first node N1, the second pole of the first control transistor T2 is connected to the first clock signal terminal CK (the first clock signal terminal CK is connected to the first clock signal line GCK) to receive the first clock signal, and the first pole of the first control transistor T2 is connected to the second node N2.

[0043] The gate of the second control transistor T3 is connected to the first clock signal terminal CK (the first clock signal terminal CK is connected to the first clock signal line GCK) to receive the first clock signal, the second electrode of the second control transistor T3 is connected to the second power supply line VGL to receive the second voltage, and the first electrode of the second control transistor T3 is connected to the second node N2.

[0044] The gate of the output control transistor T4 is connected to the second node N2, the first electrode of the output control transistor T4 is connected to the first power supply line VGH to receive the first voltage, and the second electrode of the output control transistor T4 is connected to the output terminal GOUT.

[0045] A first pole of the first capacitor C1 is connected to the second node N2, and a second pole of the first capacitor C1 is connected to the first power supply line VGH.

[0046] The gate of the output transistor T5 is connected to the third node N3, the first pole of the output transistor T5 is connected to the second clock signal terminal CB (the second clock signal terminal CB is connected to the second clock signal line GCB), and the second pole of the output transistor T5 is connected to the output terminal GOUT.

[0047] A first pole of the second capacitor C2 is connected to the third node N3, and a second pole of the second capacitor C2 is connected to the output terminal GOUT.

[0048] The gate of the first noise reduction transistor T7 is connected to the second clock signal terminal CB (the second clock signal terminal CB is connected to the second clock signal line GCB) to receive the second clock signal, and the first electrode of the first noise reduction transistor T7 is connected to the first node N1.

[0049] The gate of the second noise reduction transistor T6 is connected to the second node N2, the first electrode of the second noise reduction transistor T6 is connected to the first power supply rail VGH to receive a first voltage, and the second electrode of the second noise reduction transistor T6 is connected to the second electrode of the first noise reduction transistor T7.

[0050] A gate of the voltage regulator transistor T8 is connected to the second power supply rail VGL to receive a second voltage, a first electrode of the voltage regulator transistor T8 is connected to the first node N1, and a second electrode of the voltage regulator transistor T8 is connected to a third node N3.

[0051] 1B, the transistors in the shift register unit 104 are all P-type transistors, that is, each transistor is turned on (on level) when its gate is connected to a low level, and turned off (off level) when its gate is connected to a high level. In this case, the first pole of the transistor can be the source electrode, and the second pole of the transistor can be the drain electrode, and in other embodiments, the first pole and the second pole of the transistor can be exchanged.

[0052] The shift register unit may have a layout including, but not limited to, that of FIG. 1B, for example, each transistor in the shift register unit 104 may use an N-type transistor, or may use a mixture of P-type and N-type transistors, with the polarity of the ports of the selected type of transistor being connected according to the polarity of the ports of the corresponding transistor in the embodiment of the present disclosure.

[0053] However, the transistors used in the shift register unit may be thin film transistors or field effect transistors or other switching devices having the same characteristics. Here, thin film transistors are used as an example, and the active layer (channel region) of the transistor may be made of a semiconductor material such as polysilicon (e.g., low-temperature polysilicon or high-temperature polysilicon), amorphous silicon, indium gallium zinc oxide (IGZO), and the gate, source electrode, drain electrode, etc. may be made of a metal material such as aluminum metal or an aluminum alloy. The source electrode and drain electrode of the transistor used here may be symmetrical in structure, so there may be no distinction in structure. In the embodiment of the present disclosure, in order to distinguish between two poles other than the gate of the transistor, it is directly described that one pole is a first pole and the other pole is a second pole. In addition, in the embodiment of the present disclosure, the electrodes of the capacitor may be metal electrodes, or one of the electrodes may be made of a semiconductor material (e.g., doped polysilicon).

[0054] FIG. 1C is a signal timing diagram when the shift register unit 104 shown in FIG. 1B is operating. Hereinafter, the operation process of the shift register will be described in detail with reference to FIG. 1B and FIG. 1C. For example, the operation principle of the shift register unit 104 is described as an example, and the operation principle of the remaining shift register units 104 (except the first stage shift register unit) is similar thereto, and detailed description here is omitted. However, the difference between the operation principle of the first stage shift register unit and the shift register unit 104 is that the input end of the first stage shift register unit is connected to the trigger signal line GSTV, and the input end of the shift register unit 104 is connected to the output end of the previous stage shift register unit. As shown in FIG. 1C, the operation process of the shift register unit 104 includes four stages, which are the first stage t1, the second stage t2, the third stage t3 and the fourth stage t4, and FIG. 1C shows the timing waveforms of each signal in each stage.

[0055] At the input stage t1, as shown in FIG. 1C, the first clock signal provided at the first clock signal end CK is a low level signal, the second clock signal provided at the second clock signal end CB is a high level signal, and the input end IN receives a trigger signal (for example, the input signal Vin) provided by the output end of the previous stage shift register unit, for example, the input signal Vin is equal to the low level signal VL provided by the second power line VGL. Since the first clock signal is a low level signal, the input transistor T1 is turned on, and the input signal is transmitted to the first node N1 through the input transistor T1. Since the input transistor T1 generates a threshold loss when transmitting a low level signal, the voltage of the first node N1 is Vin-Vth1, i.e., VL-Vth1, where Vth1 represents the threshold voltage of the input transistor T1. The gate of the voltage regulator transistor T8 receives the low-level signal VL provided by the second power line VGL, so that the voltage regulator transistor T8 is in an on state, and thus the voltage VL-Vth1 is transmitted to the third node N3 through the voltage regulator transistor T8. For example, the threshold voltage of the voltage regulator transistor T8 is represented by Vth8, and similarly, the voltage of the third node N3 is VL-VthN1, where VthN1 is the smaller one of Vth1 and Vth8, because the threshold loss occurs when the voltage regulator transistor T8 transmits the low-level signal. The voltage of the third node N3 controls the output transistor T5 to be on, and the second clock signal is written to the output terminal GOUT through the output transistor T5 to be used as the output signal, that is, in the input stage t1, the output signal is the high-level second clock signal, that is, the high-level signal VH provided by the first power line VGH.

[0056] In the input stage t1, since the first clock signal is a low-level signal, the second control transistor T3 is turned on, and the low-level signal VL provided by the second power supply line VGL is transmitted to the second node N2 through the second control transistor T3. Since the voltage of the first node N1 is VL - Vth1, the first control transistor T2 is turned on, and the low-level first clock signal is transmitted to the second node N2 through the first control transistor T2. For example, the threshold voltage of the first control transistor T2 is represented by Vth2, the threshold voltage of the second control transistor T3 is represented by Vth3. When Vth3 < Vth2 + Vth1, the voltage of the second node N2 is VL - Vth2 - Vth1; when Vth3 > Vth2 + Vth1, the voltage of the second node N2 is VL - Vth3. In this case, both the output control transistor T4 and the first noise reduction transistor T6 are turned on. Since the second clock signal is a high-level signal, the second noise reduction transistor T7 is turned off.

[0057] In the output stage t2, the first clock signal provided at the first clock signal end CK is a high-level signal, the second clock signal provided at the second clock signal end CB is a low-level signal, and the input signal Vin received by the input end IN and provided by the output end of the previous shift register unit is a high-level signal. The output transistor T5 is turned on, and the second clock signal is written to the output end GOUT through the output transistor T5 to be used as the output signal. At the input stage t1, the voltage of one end connected to the output end GOUT of the second capacitor C2 is the high-level signal VH provided by the first power supply line VGH, and the voltage of one end connected to the third node N3 of the second capacitor C2 is VL-VthN1; at the output stage t2, the voltage of one end connected to the output end GOUT of the second capacitor C2 becomes the low-level signal VL provided by the second power supply line VGL, and due to the bootstrap effect of the second capacitor C2, the voltage of one end connected to the third node N3 of the second capacitor C2 becomes 2VL-VthN1-VH, that is, the voltage of the third node N3 becomes 2VL-VthN1-VH. In this case, the voltage regulator transistor T8 is turned off, the output transistor T5 can be turned on more effectively, and the output signal is the low-level signal VL provided by the second power supply line VGL.

[0058] In the output stage t2, the first clock signal is a high-level signal, so that the input transistor T1 and the second control transistor T3 are both turned off. The voltage of the first node N1 is still VL-VthN1, so that the first control transistor T2 is turned on, and the high-level first clock signal is transmitted to the second node N2 through the first control transistor T2, i.e., the voltage of the second node N2 is a high-level signal VH, so that the output control transistor T4 and the second noise reduction transistor T6 are both turned off. The second clock signal is a low-level signal, so that the first noise reduction transistor T7 is turned on.

[0059] In the buffer stage t3, the first clock signal provided at the first clock signal end CK and the second clock signal provided at the second clock signal end CB are both high level signals, and the input signal Vin provided by the output end of the previous shift register unit, which is received by the input end IN, is a high level signal. The output transistor T5 is turned on, and the second clock signal is written to the output end GOUT through the output transistor T5 and used as the output signal, in this case, the output signal is the high level second clock signal, i.e., the high level signal VH. Due to the bootstrap action of the second capacitor C2, the voltage of the third node N3 becomes VL-VthN1.

[0060] In the buffer stage t3, the first clock signal is a high level signal, so the input transistor T1 and the second control transistor T3 are both turned off. The voltage of the third node N3 becomes VL-VthN1, in this case, the voltage regulator transistor T8 is turned on, the voltage of the first node N1 is also VL-VthN1, the first control transistor T2 is turned on, and the high level of the first clock signal is transmitted to the second node N2 through the first control transistor T2, that is, the voltage of the second node N2 is a high level signal VH, so that the second noise reduction transistor T6 and the output control transistor T4 are both turned off. Since the second clock signal is a high level signal, the second noise reduction transistor T7 is turned off.

[0061] In the first sub-stage t41 of the stable stage t4, the first clock signal provided at the first clock signal end CK is a low level signal, the second clock signal provided at the second clock signal end CB is a high level signal, and the input signal Vin provided by the output end of the previous stage shift register unit received by the input end IN is a high level signal, for example, the input signal Vin is equal to the high level signal VH provided by the first power line VGH. Since the first clock signal is a low level signal, the input transistor T1 is turned on, and the input signal Vin is transmitted to the first node N1 through the input transistor T1, and since no threshold loss occurs when the input transistor T1 transmits a high level signal, the voltage of the first node N1 is the input signal Vin (i.e., the high level signal VH), and the first control transistor T2 is turned off. Since the voltage regulator transistor T8 is in an on state, the voltage of the third node N3 is the same as the first node N1, that is, the voltage of the third node N3 is VH, and the output transistor T5 is turned off. Because the first clock signal is a low-level signal, the second control transistor T3 is turned on, the voltage of the second node N2 is VL-Vth1, the second noise reduction transistor T6 and the output control transistor T4 are both turned on, and the high-level signal VH is transmitted to the output terminal GOUT through the output control transistor T4, that is, the output signal is the high-level signal VH.

[0062] In the second sub-stage t42 of the stable stage t4, the first clock signal provided at the first clock signal end CK is a high level signal, the second clock signal provided at the second clock signal end CB is a low level signal, and the input signal Vin provided by the output end of the previous stage shift register unit, which is received by the input end IN, is a high level signal. The voltages of the first node N1 and the third node N3 are the input signal Vin (i.e., the high level signal VH provided by the first power line VGH), and the first control transistor T2 and the output transistor T5 are both turned off. Since the first clock signal is a high level signal, the input transistor T1 and the second control transistor T3 are both turned off, and due to the maintaining action of the first capacitor C1, the voltage of the second node N2 is still VL-Vth3, and the output control transistor T4 and the first noise reduction transistor T6 are both turned on, and the high level signal VH is transmitted to the output end GOUT through the output control transistor T4, and the output signal is the high level signal VH.

[0063] In the second sub-stage t42, since the second clock signal is a low-level signal, the second noise reduction transistor T7 is turned on, and a high-level signal VH is transmitted to the third node N3 and the first node N1 via the first noise reduction transistor T6 and the second noise reduction transistor T7 so that the voltages of the first node N1 and the third node N3 are maintained at high levels.

[0064] In the third sub-stage t43 of the stable stage t4, the first clock signal provided at the first clock signal end CK and the second clock signal provided at the second clock signal end CB are both high level signals, and the input signal Vin provided by the output end of the previous stage shift register unit received by the input end IN is also high level signal. The voltages of the first node N1 and the third node N3 are high level signals VH, and the first control transistor T2 and the output transistor T5 are turned off. Since the first clock signal is a high level signal, the input transistor T1 and the second control transistor T3 are both turned off, the voltage of the second node N2 is still VL-Vth3, and the output control transistor T4 and the first noise reduction transistor T6 are both turned on. The high level signal VH is transmitted to the output end GOUT through the output control transistor T4, and the output signal is the high level signal VH.

[0065] Fig. 1D is a schematic layout diagram of the shift register unit 104 shown in Fig. 1B on a display substrate. As shown in Fig. 1D, the display substrate includes an input transistor T1 to a voltage regulator transistor T8 of the shift register unit 104, a first capacitor C1, a second capacitor C2, a first clock signal line GCK, a second clock signal line GCB, a first power supply line VGH, and a second power supply line VGL.

[0066] For example, as shown in Fig. 1D, the voltage regulator transistor T8 is located near the display area of ​​the first control transistor T2 and the second power line VGL (for example, the output terminal GOUT in Fig. 1D extends to the display area 102), and the first noise reduction transistor T7 and the second noise reduction transistor T6 are located away from the display area of ​​the first control transistor T2 and the second power line VGL, so that it is necessary to use one connection wiring and two transfer lines to connect the first pole of the voltage regulator transistor T8 and the first pole of the first noise reduction transistor T7, and the connection wiring further overlaps with multiple wirings (for example, the second power line VGL, the active layer of the first control transistor T2, etc.), so that the circuit parasitic capacitance increases and the space utilization rate is very low. Note that the parasitic capacitance may include planar parasitic capacitance, spatial parasitic capacitance, etc. In the display substrate, when the orthogonal projections of, for example, the transfer electrodes, the connection wiring, and the gates located in different layers overlap in a direction perpendicular to the base substrate, a planar parasitic capacitance can be formed, and when, for example, the transfer electrodes, the connection wiring, and the gates located in the same layer face each other in a planar direction, a spatial parasitic capacitance (also called 3D parasitic capacitance) can be formed. The gate of the first noise reduction transistor T7 is connected to the first pole of the output transistor T5 and overlaps with multiple wirings (for example, the first power supply line VGL, the transfer line between the first pole of the first control transistor T2 and the gate of T6), so that the circuit parasitic capacitance and the complexity of the wiring are increased. Therefore, the arrangement and connection method of each transistor of the display substrate shown in FIG. 1D increases the overlap of the wirings and increases the number of connection wirings, which increases the circuit parasitic capacitance and the complexity of the wiring, reduces the space utilization rate, and increases the space occupied by the gate driving circuit, which is disadvantageous to the realization of a narrow frame design of the display panel, and the unnecessary overlaps cause excessive parasitic capacitance, which is likely to cause problems such as signal interference, which affects the display quality of the display panel. Therefore, a simpler wiring layout of the gate driving circuit is beneficial for improving the space utilization rate of the display panel, which makes it easier to realize a narrower frame of the display panel, increase the screen occupancy rate, and achieve a better display effect.

[0067] At least one embodiment of the present disclosure provides a display substrate, which includes a base substrate having a display area and a peripheral area located on at least one side of the display area, and a shift register unit, a first clock signal line, and a second clock signal line disposed on the peripheral area of ​​the base substrate.The first clock signal line and the second clock signal line extend along a first direction on the base substrate and are configured to provide a first clock signal and a second clock signal to the shift register unit, respectively. The shift register unit includes an input circuit, an output circuit, a first control circuit, a second control circuit and a voltage regulator circuit. The input circuit is configured to input an input signal to a first node in response to the first clock signal. The first control circuit is connected to the first node and the second node and configured to control a level of the second node in response to the level of the first node and the first clock signal. The second control circuit is connected to the first node and the second node and configured to control the level of the first node under control of the level of the second node and the second clock signal. The voltage regulator circuit is connected to the first node and a third node and configured to stabilize the level of the third node. The output circuit is connected to the third node and configured to stabilize the level of the third node under control of the level of the third node. a first control circuit including a first control transistor, a second control circuit including a first noise reduction transistor, and a voltage regulator circuit including a voltage regulator transistor, a gate of the first control transistor, a first pole of the first noise reduction transistor, and a first pole of the voltage regulator transistor are all connected to a first node, the first pole of the first noise reduction transistor and the first pole of the voltage regulator transistor are located on a first source-drain electrode layer, the first source-drain electrode layer including a first transfer electrode, the first transfer electrode including a first portion extending parallel to a second direction different from the first direction, and a second portion integrally formed with the first portion and extending in the first direction, a first end of the first portion connected to the first pole of the first noise reduction transistor, a second end of the first portion connected to the first pole of the voltage regulator transistor, and the second portion connected to a gate of a first control transistor not in the same layer.

[0068] At least one embodiment of the present disclosure further provides a display device corresponding to the display substrate and a method for manufacturing the display substrate.

[0069] The optimized circuit connection and structural layout of the shift register unit of the display substrate provided by the above embodiments of the present disclosure can reduce, to a certain extent, the number of overlapping wires and the wiring complexity of the shift register unit, increase the space utilization rate of the shift register unit, and be favorable for realizing a narrow-bezel design of the display panel while ensuring the display quality of the display panel.

[0070] Hereinafter, embodiments and examples of the present disclosure will be described in detail with reference to the drawings.

[0071] At least one embodiment of the present disclosure provides a display substrate. Figure 2 is a schematic layout diagram of the shift register unit 104 shown in Figure 1B on the display substrate.

[0072] 2, the display substrate 1 includes a base substrate 101, a shift register unit 104, a first power supply line VGH, a second power supply line VGL, and a plurality of clock signal lines (for example, a first clock signal line GCK and a second clock signal line GCB shown in the figure) disposed on the base substrate 101. For example, the first power supply line VGH, the second power supply line VGL, and the plurality of clock signal lines extend on the base substrate 10 along a first direction X, and are configured to provide a first voltage, a second voltage, and a plurality of clock signals (for example, the above-mentioned first clock signal or second clock signal, etc.) to the shift register unit 104, respectively.

[0073] In addition, the first power line VGH, the second power line VGL, and the multiple clock signal lines may all be installed in parallel along the first direction X, or may intersect with each other at a predetermined angle (for example, 20° or less), and the embodiments of the present disclosure are not limited thereto.

[0074] However, extending in a first direction refers to the extension direction of the main lines of the first power supply line, the second power supply line, and the multiple clock signal lines, and does not include protrusions or corners, etc. branching off from the main line of each signal line.

[0075] For example, the first power supply line VGH is configured to provide a first voltage to the plurality of cascaded shift register units 104 included in the gate drive circuit, and the second power supply line VGL is configured to provide a second voltage to the plurality of cascaded shift register units 104 included in the gate drive circuit. For example, the first voltage is greater than the second voltage, e.g., the first voltage is a DC high level and the second voltage is a DC low level.

[0076] For example, the base substrate 101 can be made of, for example, glass, plastic, steel, or other suitable materials, and embodiments of the present disclosure are not limited in this respect.

[0077] For example, the display substrate 1 includes a pixel array region (i.e., a display region 102 shown in FIG. 1A, hereinafter referred to as the pixel array region 102) and a peripheral region 106 (shown in FIG. 1A) other than the pixel array region. For example, the first power line VGH, the second power line VGL, the plurality of clock signal lines and the shift register unit 104 are located in the peripheral region 106 and are located on one side of the base substrate 101 (as shown in FIG. 1A, they are located between the pixel array region 102 and the side of the base substrate 101), for example, on the left side of the base substrate 101 as shown in FIG. 1A. However, they may be located on the right side or both the left and right sides of the base substrate 101, and the embodiment of the present disclosure is not limited thereto.

[0078] For example, the first clock signal line GCK and the second clock signal line GCB are located on the side of the shift register unit 104 that is farther from the display area 102. For example, the orthogonal projection of the first power supply line VGH on the base substrate 101 is located on the side closer to the display area 102 of the orthogonal projection of the shift register unit 104 on the base substrate 101. For example, the orthogonal projection of the second power supply line VGL on the base substrate 101 is located between the orthogonal projection of the first clock signal line CGK and the second clock signal line CGB on the base substrate 101 and the orthogonal projection of the shift register unit 104 on the base substrate 101. By arranging the wiring as described above, it is possible to easily connect other wiring of the shift register 104 to the first clock signal line GCK, the second clock signal line GCB, the first power supply line VGL, and the second power supply line VGH.

[0079] It should be noted that the above-mentioned wiring positions are merely exemplary, and the embodiments of the present disclosure are not limited thereto as long as the wiring positions are advantageous for connection to the shift register unit 104.

[0080] For example, the pixel array region 102 includes a plurality of pixel units 103 arranged in an array. For example, each of the plurality of pixel units 103 includes a pixel driving circuit, and may further include, for example, a light emitting element (not shown).

[0081] For example, a plurality of cascaded shift register units 104 constitute a gate driving circuit. For example, the output terminals GOUT of the plurality of shift register units 104 are respectively connected to the gate scanning signal terminals of the pixel driving circuits of each row located in the pixel array region 102 to provide output signals (for example, gate scanning signals) to the pixel circuits of each row, thereby realizing driving the light emitting elements to emit light. For example, the pixel driving circuits may be pixel circuits having circuit structures such as 7T1C, 2T1C, 4T2C, 8T2C, etc. in the art, and detailed description thereof is omitted here.

[0082] FIG. 2 shows only one stage of the shift register unit 104 in the gate driving circuit. For example, as shown in FIG. 2, the first clock end CK (shown in FIG. 1B) of the shift register unit 104 is connected to the first clock signal line GCK to receive the first clock signal, the second clock signal end CB (shown in FIG. 1B) of the shift register unit 104 is connected to the second clock signal line GCB to receive the second clock signal, the first clock signal end CK of the next stage shift register unit of the shift register unit 104 is connected to the second clock signal line GCB to receive the first clock signal, and the second clock signal end CB is connected to the first clock signal line GCK to receive the second clock signal, and so on in the same manner. For example, when the shift register unit 104 is used as the shift register unit of the next stage of the first stage shift register unit, the first clock signal end CK of the Xth (X is an even number greater than 1) stage shift register unit is connected to the first clock signal line GCK to receive the first clock signal, the second clock signal end CB of the Xth stage shift register unit is connected to the second clock signal line GCB to receive the second clock signal, the first clock end CK of the X-1th stage shift register unit 104 is connected to the second clock signal line GCB to receive the first clock signal, and the second clock signal end CB of the X-1th stage shift register unit 104 is connected to the first clock signal line GCK to receive the second clock signal. However, the connection manner between the shift register units of each stage and the clock signal line may also use other connection manners in the present field, and the embodiments of the present disclosure are not limited thereto. For example, the input end of the first-stage shift register unit is connected to the trigger signal line GSTV to receive the trigger signal as an input signal, and the input end of the other-stage shift register unit is connected to the output end GOUT of the previous-stage shift register unit (for example, the input end of the second-stage shift register unit is connected to the output end GOUT of the first-stage shift register unit). The following description will be given taking the structure of the shift register unit 104 shown in FIG. 2 as an example, and the embodiments of the present disclosure are not limited thereto.

[0083] 1B, in some examples, the shift register unit 104 includes an input circuit 1041, an output circuit 1043, a first control circuit 1042, a second control circuit 1045, and a voltage regulator circuit 1046. In other examples, the shift register unit 104 further includes an output control circuit 1044.

[0084] The input circuit 1041 is configured to input an input signal to the first node N1 in response to a first clock signal. For example, the input circuit 1041 is connected to an input terminal IN, a first node N1, and a first clock signal terminal CK, and the first clock signal terminal CK is configured to be turned on under the control of the received first clock signal to connect the input terminal IN to the first node N1, thereby inputting an input signal to the first node N1. For example, the input circuit 1041 is implemented as the input transistor T1 described above, and the connection manner of the input transistor T1 can refer to the above description, and detailed description here is omitted.

[0085] The output circuit 1043 is connected to the third node N3 and configured to output an output signal to the output terminal GOUT. For example, the output circuit 1043 is connected to the third node N3, the output terminal GOUT and the second clock signal terminal CB, and is turned on under the control of the level of the third node N3, connects the second clock signal terminal CB and the output terminal GOUT, and outputs a second clock signal to the output terminal GOUT, for example, configured to output a low level of the second clock signal. For example, the output circuit 1043 is implemented as the above-mentioned output transistor T5 and the second capacitor C2, and the connection manner between the output transistor T5 and the second capacitor C2 can refer to the above description, and detailed description here is omitted.

[0086] The first control circuit 1042 is connected to the first node N1 and the second node N2, and is configured to control the level of the second node N2 in response to the level of the first node N1 and the first clock signal. For example, the first control circuit is connected to the first node N1, the second node N2, and the first clock signal end CK, and is configured to be turned on under the control of the level of the first node N1 to connect the second node N2 to the first clock signal end CK, thereby providing the first clock signal provided by the first clock signal end CK to the second node N2. For example, the first control circuit 1042 is implemented as the above-mentioned first control transistor T2 and second control transistor T3, and the connection manner between the first control transistor T2 and the second control transistor T3 can be referred to the above description, and detailed description here is omitted. However, the first control circuit 1042 is not limited to being connected to the first node N1, and may be connected to another independent voltage terminal (providing the same voltage as the voltage of the first node N1) or to a separate circuit that is connected to the same circuit as the input circuit, and the embodiment of the present disclosure is not limited thereto. The connections of other circuits of the shift register unit are similar thereto, and detailed descriptions are omitted here.

[0087] The second control circuit 1045 is connected to the first node N1 and the second node N2, and is configured to control the level of the first node N1 under the control of the level of the second node N2 and the second clock signal. For example, the second control circuit 1045 is connected to the first node N1, the second node N2, the first power line VGH, and the second clock signal terminal CB, and the level of the second node N2 and the second clock signal terminal CB are turned on under the control of the received second clock signal to connect the first power line VGH to the first node N1, thereby charging the potential of the first node N1 to a high level, and preventing the output circuit 1042 from turning on in the non-output stage, thereby preventing erroneous output. For example, the second control circuit 1045 is implemented as the above-mentioned first noise reduction transistor T6 and the second noise reduction transistor T7, and the connection method between the first noise reduction transistor T6 and the second noise reduction transistor T7 can be referred to the above description, and detailed description here is omitted.

[0088] The voltage regulator circuit 1046 is connected to the first node N1 and the third node N3, and is configured to stabilize the level of the third node N3. For example, the voltage regulator circuit 1046 is connected to the first node N1, the third node N3, and the second power line VGL, and is configured to be turned on under control of the second voltage provided by the second power line VGL to connect the first node N1 and the third node N3. For example, the voltage regulator circuit 1046 is implemented as a voltage regulator transistor T8, and a specific description can be referred to the description of the voltage regulator transistor T8 in FIG. 1B above, and a detailed description thereof will be omitted here.

[0089] The output control circuit 1044 is configured to control the level of the output terminal GOUT under the control of the level of the second node N2. For example, the output control circuit 1044 is connected to the second node N2, the first power line VGH, and the output terminal GOUT, and is configured to connect the output terminal GOUT to the first power line VGH under the control of the level of the second node N2, output the first voltage provided by the first power line VGH to the output terminal GOUT, and control the output terminal GOUT to a high level, thereby avoiding erroneous output at the non-output stage of the shift register unit. For example, the output control circuit 1044 is implemented as the above-mentioned output control transistor T4 and the first capacitor C1, and the connection manner between the output control transistor T4 and the first capacitor C1 can be referred to the above description, and detailed description here is omitted.

[0090] For example, the voltage regulator transistor T8 is always on under the control of the second voltage provided by the second power line VGL, and connects the third node N3 to the first node N1 via the voltage regulator transistor T8, preventing the level of the third node N3 from leaking through the input transistor T1, the first control transistor T2 and the second noise reduction transistor T7 connected to the first node N1, and is advantageous in reducing the stress of the level of the third node N3 on the first control transistor T1 to maintain the level of the third node N3, so that the output transistor T5 can be fully turned on in the output stage.

[0091] Figures 3, 4, 5, and 7 respectively show plan views of each layer wiring of the shift register unit of the display substrate shown in Figure 2, and Figure 6 shows a distribution map of via holes of the shift register unit of the display substrate shown in Figure 2. Figure 3 is a plan view of a semiconductor layer of the display substrate according to at least one embodiment of the present disclosure, Figure 4 is a plan view of a first conductive layer of the display substrate according to at least one embodiment of the present disclosure, Figure 5 is a plan view of a second conductive layer of the display substrate according to at least one embodiment of the present disclosure, Figure 6 is a distribution map of via holes of the display substrate according to at least one embodiment of the present disclosure, Figure 7 is a plan view of a third conductive layer of the display substrate according to at least one embodiment of the present disclosure, and Figure 8 is a cross section along the AB direction of the display substrate shown in Figure 2.

[0092] For example, the display substrate 1 further includes a first insulating layer 350 (for example, a first gate insulating layer), a second insulating layer 360 (for example, a second gate insulating layer), and a third insulating layer 370 (for example, an interlayer insulating layer), and is located between the layer structures shown in Figures 3, 4, 5, and 7. For example, the first insulating layer 350 (shown in Figure 8) is located between the semiconductor layer 310 shown in Figure 3 and the first conductive layer 320 shown in Figure 4, the second insulating layer 360 (shown in Figure 8) is located between the first conductive layer 320 shown in Figure 4 and the second conductive layer 330 shown in Figure 5, and the third insulating layer 370 (shown in Figure 8) is located between the second conductive layer 330 shown in Figure 5 and the third conductive layer 340 shown in Figure 7.

[0093] For example, as shown in FIG. 8 , the display substrate 1 further includes a fourth insulating layer 380, which is located on the third conductive layer 340 and is used to protect the third conductive layer 340.

[0094] 8, the display substrate 1 further includes a barrier layer 390 and a buffer layer 3100. The buffer layer 3100 is located on a side of the first insulating layer 350 close to the base substrate 101, and the barrier layer 390 is located between the buffer layer 3100 and the base substrate 101. The barrier layer 390 and the buffer layer 3100 can provide a flat surface for forming a gate driving circuit, and can prevent impurities that may be present in the base substrate 101 from diffusing into the gate driving circuit and adversely affecting the performance of the display substrate.

[0095] For example, one or more materials of the first insulating layer 350, the second insulating layer 360, the third insulating layer 370, the fourth insulating layer 380, the barrier layer 390, and the buffer layer 3100 may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials, and the materials of the first insulating layer 350, the second insulating layer 360, the third insulating layer 370, the fourth insulating layer 380, the barrier layer 390, and the buffer layer 3100 may be the same or different, and the embodiments of the present disclosure are not limited in this regard.

[0096] In addition, the display substrate shown in Fig. 2 is described as an example of the layout design of a shift register of a certain stage in a gate driving circuit and the first power line, the second power line, and the signal line connected thereto, but the layout embodiment of the remaining stages of the shift registers can refer to the layout aspect shown in Fig. 2, and detailed description is omitted here. Of course, other layout aspects may be used, and the embodiment of the present disclosure does not limit this. Of course, the layout aspect of each stage of the shift registers in the remaining gate driving circuits may refer to the layout aspect shown in Fig. 2, and other layout aspects may be used, and the embodiment of the present disclosure does not limit this.

[0097] Hereinafter, a display substrate according to at least one embodiment of the present disclosure will be described in detail with reference to FIGS.

[0098] For example, the active layer A1 of the input transistor T1 to the active layer A8 of the voltage regulator transistor T8 of the shift register unit 104 shown in FIG. 2 may be formed by the semiconductor layer 310 shown in FIG. 3. The semiconductor layer 310 may be formed by patterning a semiconductor material. For example, as shown in FIG. 3, the semiconductor layer 310 may be in a short bar shape or a curved or bent shape as required, and is used to manufacture the active layer A1 of the input transistor T1 to the active layer A8 of the voltage regulator transistor T8. Each active layer may include a source electrode region, a drain electrode region, and a channel region located between the source electrode region and the drain electrode region. For example, the channel region has semiconductor properties, and the source electrode region and the drain electrode region are located on both sides of the channel region and are doped with impurities, so that they are conductive. For example, the source electrode region is part of the active layer, and the metal electrode (e.g., located in the third conductive layer 340) contacting the source electrode region corresponds to the source electrode (or called the first pole) of the transistor, and the drain electrode region is part of the active layer, and the metal electrode (e.g., located in the third conductive layer 340) contacting the drain electrode region corresponds to the drain electrode (or called the second pole) of the transistor. For example, the source electrode region is connected to its corresponding metal electrode (first pole) through a via hole passing through the first insulating layer 350, the second insulating layer 360 and the third insulating layer 370, and the drain electrode region is connected to its corresponding metal electrode (second pole) through a via hole passing through the first insulating layer 350, the second insulating layer 360 and the third insulating layer 370.

[0099] For example, as shown in FIG. 3, taking the first control transistor T2 as an example, the active layer A2 of the first control transistor T2 includes a source electrode region S2, a drain electrode region D2, and a channel region P2. For example, as shown in FIG. 4, the first control transistor T2 further includes a gate G2, where the gate G2 is located in the first conductive layer 320. For example, taking the voltage regulator transistor T8 as an example, as shown in FIG. 3, the active layer A8 of the voltage regulator transistor T8 includes a source electrode region S8, a drain electrode region D8, and a channel region P8. For example, as shown in FIG. 4, the voltage regulator transistor T8 further includes a gate G8, where the gate G8 is located in the first conductive layer 320. Other transistors are similar, and detailed descriptions are omitted here.

[0100] For example, the material of the semiconductor layer 310 may include an oxide semiconductor, an organic semiconductor, or amorphous silicon, polysilicon, etc., for example, the oxide semiconductor includes a metal oxide semiconductor (e.g., indium gallium zinc oxide (IGZO)), and the polysilicon includes low-temperature polysilicon or high-temperature polysilicon, etc., and the embodiments of the present disclosure are not limited thereto. However, the source electrode region and the drain electrode region may be regions doped with n-type impurities or p-type impurities, and the embodiments of the present disclosure are not limited thereto.

[0101] In addition, in some other examples, the first pole and the second pole of each transistor may be located in other conductive layers and connected to the corresponding active layer through a via hole in an insulating layer located between the semiconductor layer, and the embodiments of the present disclosure are not limited in this regard.

[0102] 4 shows the first conductive layer 320 of the display substrate, and the first conductive layer 320 is disposed on the first insulating layer 350, and is therefore insulated from the semiconductor layer 310. For example, the first conductive layer 320 may include the first electrode CE11 of the first capacitor C1, the first electrode CE21 of the second capacitor C2, the gate G1 of the input transistor T1 to the gate G8 of the voltage regulator transistor T8, and each wiring (for example, the first connection wiring L1 and the second connection wiring L2) directly connected to the gate. As shown in FIG. 4, the gate G1 of the input transistor T1 to the gate G8 of the voltage regulator transistor T8 are the parts surrounded by the dashed lines, that is, the parts where the semiconductor layer structure of each transistor overlaps with the wiring on the first conductive layer 320.

[0103] For example, the material of the first conductive layer 320 may include a metal material or an alloy material, such as a metal single layer or multi-layer structure formed by molybdenum, aluminum, titanium, etc., for example, the multi-layer structure is a structure in which multiple metal layers are stacked (for example, a structure in which three metal layers, titanium, aluminum, and titanium, are stacked (Ti / Al / Ti)).

[0104] 5 shows a second conductive layer 330 of the display substrate. The second conductive layer 330 is disposed on a second insulating layer 360, thereby being insulated from the first conductive layer 320. The second conductive layer 330 includes a second electrode CE12 of the first capacitor C1 to a second electrode CE22 of the second capacitor C2. The second electrode CE12 at least partially overlaps with the first electrode CE11 to form the first capacitor C1, and the second electrode CE22 at least partially overlaps with the first electrode CE21 to form the second capacitor C2.

[0105] For example, the material of the second conductive layer 330 may include a metal material or an alloy material, such as a metal single layer or multilayer structure formed by molybdenum, aluminum, titanium, etc., for example, the multilayer structure is a stacked structure in which multiple metal layers are stacked (for example, a structure in which three metal layers, titanium, aluminum, and titanium, are stacked (Ti / Al / Ti)).

[0106] 7 shows a third conductive layer 340 of the display substrate, in which the second conductive layer 330 is disposed on a third insulating layer 360, thereby being insulated from other conductive layers. The third conductive layer 340 includes a plurality of signal lines (e.g., a first clock signal line GCK and a second clock signal line GCB), a first power supply line VGH, a second power supply line VGL, etc. However, the third conductive layer 340 further includes a first pole (e.g., a source electrode connected to a source electrode region of the active layer) and a second pole (e.g., a drain electrode connected to a drain electrode region of the active layer) of each transistor, and is connected to a first transfer electrode E1, a second transfer electrode E2, a third transfer electrode E3, a fourth transfer electrode E4, a fifth transfer electrode E5, a sixth transfer electrode E6, a seventh transfer electrode E7, etc. between each transistor, a capacitor, and the signal lines.

[0107] For example, the material of the third conductive layer 340 may include a metal material or an alloy material, such as a metal single layer or multi-layer structure formed by molybdenum, aluminum, titanium, etc., and the multi-layer structure is, for example, a stacked structure in which a plurality of metal layers are stacked (for example, a structure in which three metal layers, titanium, aluminum, and titanium, are stacked (Ti / Al / Ti)). The embodiments of the present disclosure are not specifically limited to the material of each functional layer.

[0108] As shown in Figures 3, 4, 5 and 7, a plurality of signal lines, a first power supply line VGH, and a second power supply line VGL are connected to the transistors and capacitors in each remaining layer that need to be connected thereto through at least one via hole shown in Figure 6, and each transistor and capacitor is also connected through at least one via hole or bridged through a transfer electrode, and detailed description thereof is omitted here.

[0109] FIG. 2 is a schematic diagram showing the stacking positional relationship of the semiconductor layer 310 shown in FIG. 3, the first conductive layer 320 shown in FIG. 4, the second conductive layer 330 shown in FIG. 5, and the third conductive layer 340 shown in FIG. 7, and how they are connected via multiple via holes shown in FIG. 6.

[0110] As shown in Fig. 2, the gate G2 (shown in Fig. 4) of the first control transistor T2, the first pole SD71 (shown in Fig. 7) of the first noise reduction transistor T7, and the first pole SD81 (shown in Fig. 7) of the voltage regulator transistor T8 are all connected to the first node N1. The first pole SD71 (shown in Fig. 7) of the first noise reduction transistor T7 and the first pole SD81 (shown in Fig. 7) of the voltage regulator transistor T8 are all located on the first source-drain electrode layer, which comprises the first transfer electrode E1 (shown in Fig. 7), that is, the first pole SD71 (shown in Fig. 7) of the first noise reduction transistor T7 and the first pole SD81 (shown in Fig. 7) of the voltage regulator transistor T8 are located on one continuous first source-drain electrode layer and are integrally formed with the first transfer electrode E1 (shown in Fig. 7), thereby reducing the number of wirings and improving the space occupation rate of the display substrate.

[0111] 3, 6 and 7, the first pole SD71 of the first noise reduction transistor T7 is connected to the active layer A7 of the first noise reduction transistor T7 through a via hole H71 that penetrates the first insulating layer 350, the second insulating layer 360 and the third insulating layer 370. The first pole SD81 of the voltage regulator transistor T8 is connected to the active layer A8 of the voltage regulator transistor T8 through a via hole H81 that penetrates the first insulating layer 350, the second insulating layer 360 and the third insulating layer 370.

[0112] For example, as shown in FIG. 7, the first source-drain electrode layer is located on the third conductive layer 340 of the display substrate.

[0113] For example, as shown in Fig. 7, the first transfer electrode E1 comprises a first portion E11 extending parallel to a second direction Y different from the first direction X, and a second portion E12 integrally formed with the first portion and extending in the first direction, the first end of the first portion E11 is connected to a first pole SD71 of the first noise reduction transistor T7, the second end of the first portion E11 is connected to a first pole SD81 of the voltage regulator transistor T8, and the second portion E12 is connected to a gate G2 of the first control transistor T2 not in the same layer (shown in Fig. 4). However, the positions of the first end of the first portion E11 and the first pole SD71 of the first noise reduction transistor T7 are considered to be the same, i.e., are integrally formed, and therefore the reference numeral of the first end of the first portion E11 is not shown in Fig. 7, and similarly, the reference numeral of the second end of the first portion E11 is not shown in Fig. 7.

[0114] For example, as shown in Figures 4, 6 and 7, the second portion E12 of the first transfer electrode E1 is connected to the gate G2 of the first control transistor T2 through a via hole GH1 that penetrates the second insulating layer 360 and the third insulating layer 370.

[0115] For example, as shown in FIGS. 2 and 7, the first transfer electrode E1 is a broken line located between the first noise reduction transistor T7, the voltage regulator transistor T8, and the first control transistor T2 and extending along the first direction X and the second direction Y, and one end of the first portion E11 extending in the second direction Y of the first transfer electrode E1 (i.e., the first end of the first portion E11) is the first pole SD71 of the first noise reduction transistor T7, and the other end of the first portion E11 extending in the second direction Y of the first transfer electrode E1 (i.e., the second end of the first portion E11) is the first pole SD81 of the voltage regulator transistor T8. The second portion E12 of the first transfer electrode E1 extending along the first direction X is drawn out from the first portion of the first transfer electrode E1, and the second portion of the first transfer electrode E1 is connected to the gate of the first control transistor T2, so that the first portion E11 and the second portion E12 form a substantially inverted "T" shape. The first portion E11 of the first transfer electrode E1 extending in the second direction Y is connected to the first pole SD71 of the first noise reduction transistor T7 and the first pole SD81 of the voltage regulator transistor T8, and the second portion E12 of the first transfer electrode E1 is connected to the gate G2 of the first control transistor T2, thereby reducing the number of transfer electrodes and the complexity of the wiring, improving the space utilization rate of the display substrate, and reducing the occurrence of parasitic capacitance of the display substrate. As shown in FIG. 2, the first transfer electrode E1 can reduce the occurrence of parasitic capacitance (e.g., spatial parasitic capacitance) by separating the first pole SD71 of the first noise reduction transistor T7 and the first pole SD81 of the voltage regulator transistor T8 farther apart in the second direction Y, and the first transfer electrode E1 reduces the occurrence of parasitic capacitance (e.g., spatial parasitic capacitance) by separating the gate of the first control transistor T2 from the first noise reduction transistor T7 and the voltage regulator transistor T8 farther apart in the first direction X.

[0116] For example, in another embodiment, as shown in FIG. 2 and FIG. 7, the position of the voltage regulator transistor T8 can be moved closer to the first noise reduction transistor T7, and if necessary, the length of the output transistor T5 in the second direction Y can be shortened to position the first pole SD81 of the voltage regulator transistor T8 and the second part E12 of the first transfer electrode E1 in a straight line along the first direction X. In this case, the second part E12 and the first part E11 of the first transfer electrode E1 can be formed in an "L" shape, which can reduce the number of transfer electrodes and the complexity of the wiring, and improve the space utilization rate of the display substrate. However, since the distance between the voltage regulator transistor T8 and the first noise reduction transistor T7 and the output transistor T5 is shortened, the spatial parasitic capacitance between the voltage regulator transistor T8 and the first noise reduction transistor T7 and the output transistor T5 may increase compared to the structure shown in FIG. 2. The first transfer electrode E1 of the embodiment of the present disclosure is not limited to the inverted "T" shape shown in FIG. 2.

[0117] For example, the included angle between the first direction and the second direction is between 70° and 90°, including 70° and 90°. For example, the included angle between the first direction and the second direction is 70°, 90°, or 80°, etc., and can be set according to the actual situation, and the embodiments of the present disclosure are not limited thereto. For example, the included angle between the first direction and the second direction may further be 75°, 85°, etc.

[0118] For example, as shown in Fig. 3, the orthogonal projection of the active layer A7 of the first noise reduction transistor T7 on the base substrate 101 is located on the side closer to the display area 102 of the orthogonal projection of the active layer A2 of the first control transistor T2 on the base substrate 101, that is, in the first direction Y, the active layer A7 of the first noise reduction transistor T7 is located on the right side of the active layer A2 of the first control transistor T2. For example, the orthogonal projection of the active layer A8 of the voltage regulator transistor T8 on the base substrate 101 is located on the side farther from the display area 102 of the orthogonal projection of the active layer A2 of the first control transistor T2 on the base substrate 101, that is, in the first direction Y, the active layer A8 of the voltage regulator transistor T8 is located on the left side of the active layer A2 of the first control transistor T2. This can reduce the complexity of the wiring of the first transfer electrode E1, improve the space utilization rate of the display substrate, and reduce the overlap between the first transfer electrode E1 and other wiring.

[0119] For example, in other embodiments, the orthogonal projection of the active layer A8 of the voltage regulator transistor T8 on the base substrate 101 may be further located between the orthogonal projection of the active layer A2 of the first control transistor T2 on the base substrate 101 and the orthogonal projection of the active layer A7 of the first noise reduction transistor T7 on the base substrate 101, and the embodiments of the present disclosure are not limited thereto.

[0120] For example, as shown in FIG. 7, the first transfer electrode E1 further includes a third portion E13 extending parallel to the second direction Y. The third portion E13 is connected to the second portion E12 (i.e., the third portion E13 extends from the second portion E12 toward the input transistor T1 along the second direction Y), and the third portion E13 and the first portion E11 are arranged side by side in the first direction. The first pole SD11 of the input transistor T1 is connected to an end of the third portion E13. However, the end of the third portion E13 and the first pole SD11 of the input transistor T1 are considered to be in the same position, i.e., are integrally formed, and therefore, the reference numeral of the end of the third portion E13 is not shown in FIG. 7.

[0121] For example, the third portion E13 of the first transfer electrode E1 does not have to be parallel to the second direction Y, and for example, the third portion E13 of the first transfer electrode E1 intersects with the second direction Y at a predetermined angle. For example, the intersecting angle is 20° or less.

[0122] For example, in another embodiment, as shown in Figures 2 and 7, the input transistor T1 may be moved closer to the first control transistor T2, and the first pole SD11 of the input transistor T1 and the second part E12 of the first transfer electrode E1 are located in a straight line along the first direction X. In this case, the first pole SD11 of the input transistor T1 can be directly connected to the second part E12 of the first transfer electrode E1, and there is no need to design the third part E13 of the first transfer electrode E1, which can also reduce the complexity of the wiring of the first transfer electrode E1, improve the space utilization rate of the display substrate, and reduce the overlap between the first transfer electrode E1 and other wiring. However, when the distance between the input transistor T1 and the first control transistor T2 and the second control transistor T3 is shortened, the spatial parasitic capacitance between the input transistor T1 and the first control transistor T2 and the second control transistor T3 may increase compared to the structure shown in Figure 2.

[0123] For example, as shown in Figures 3, 6 and 7, the first pole SD11 of the input transistor T1 is connected to the active layer A1 of the input transistor T1 through a via hole H11 that penetrates the first insulating layer 350, the second insulating layer 360 and the third insulating layer 370.

[0124] 3, the orthogonal projection of the active layer A1 of the input transistor T1 on the base substrate 101 is located between the orthogonal projection of the active layer A2 of the first control transistor T2 on the base substrate 101 and the orthogonal projection of the active layer A7 of the first noise reduction transistor T7 on the base substrate 101, that is, the active layer A1 of the input transistor T1 is located between the active layer A2 of the first control transistor T2 and the active layer A7 of the first noise reduction transistor T7 in the second direction Y. This reduces the overlap between the third portion E13 of the first transfer electrode E1 and other wirings, and reduces the complexity of the wirings, so that the wirings of the shift register unit are more compact, saving space and reducing the occurrence of parasitic capacitance.

[0125] 2 and 7, the first transfer electrode E1 comprises a first node N1. For example, the first transfer electrode E1 is implemented as a first node N1 and is used to connect a first pole SD71 of the first noise reduction transistor T7, a first pole SD81 of the voltage regulator transistor T8, and a gate G2 of the first control transistor T2 (shown in FIG. 4). For example, the first transfer electrode E1 is located on the third conductive layer 340.

[0126] For example, as shown in FIG. 2 and FIG. 7, the display substrate further includes a second transfer electrode E2. The second transfer electrode E2 includes a first portion E21 extending along a first direction X and a second portion E22 parallel to a second direction Y. The second portion E22 extends from the first portion E21, and the second portion E22 and the first portion E21 form an approximately "L" shape, whereby an end of the first portion E21 of the second transfer electrode E2 is connected to the first pole SD31 of the second control transistor T3, and the second portion E22 of the second transfer electrode E2 is connected to the first pole SD21 of the first control transistor T2. The installation form of the second transfer electrode E2 does not need to overlap with other wiring, thereby reducing the occurrence of parasitic capacitance. However, the position of the end of the first portion E21 and the position of the first pole SD31 of the second control transistor T3 are considered to be the same, i.e., are integrally formed, and therefore the reference numeral of the end of the first portion E21 is not shown in FIG. 7.

[0127] For example, the second portion E22 of the second transfer electrode E2 does not have to be parallel to the second direction Y, and for example, the second portion E22 of the second transfer electrode E2 intersects with the second direction Y at a predetermined angle. For example, the intersecting angle is 20° or less.

[0128] 3, 6 and 7, the first pole SD31 of the second control transistor T3 is connected to the active layer A3 of the second control transistor T3 through a via hole H31 that penetrates the first insulating layer 350, the second insulating layer 360 and the third insulating layer 370. The first pole SD21 of the first control transistor T2 is connected to the active layer A2 of the first control transistor T2 through a via hole H21 that penetrates the first insulating layer 350, the second insulating layer 360 and the third insulating layer 370.

[0129] 2 and 7, the second transfer electrode E2 comprises a second node N2. For example, the second transfer electrode E2 is implemented as a second node N2 and is used to connect the first pole SD31 of the second control transistor T3 and the first pole SD31 of the second control transistor T3. For example, the second transfer electrode E2 is located on the third conductive layer 340.

[0130] 3, the orthogonal projection of the active layer A3 of the second control transistor T3 on the base substrate 101 is located on the side away from the display area 101 of the orthogonal projection of the active layer A2 of the first control transistor T2 on the base substrate 101, that is, the active layer A3 of the second control transistor T3 is located on the left side of the active layer A2 of the first control transistor T2 in the second direction Y. This can reduce the complexity of the wiring of the second transfer electrode E2, improve the space utilization rate of the display substrate, and reduce the overlap between the second transfer electrode E2 and other wiring.

[0131] For example, as shown in Fig. 3, the active layer A6 of the second noise reduction transistor T6 and the active layer A7 of the first noise reduction transistor T7 are located in one continuous first semiconductor layer, and the first semiconductor layer extends along a first direction, that is, the active layer A6 of the second noise reduction transistor T6 and the active layer A7 of the first noise reduction transistor T7 are integrally formed. For example, as shown in Fig. 2 and Fig. 3, the active layer A6 of the second noise reduction transistor T6 may be offset from the active layer A7 of the first noise reduction transistor T7 by a certain distance in the first direction, as long as it does not affect the layout of other structures and does not increase the width of the shift register unit excessively, and the embodiments of the present disclosure are not limited thereto.

[0132] 2 and 4, the gate G6 of the second noise reduction transistor T6 and the gate G7 of the first noise reduction transistor T7 extend along the second direction Y and are arranged side by side in the first direction X. For example, the gate G6 of the second noise reduction transistor T6 and the gate G7 of the first noise reduction transistor T7 may be parallel, for example, both extend along the second direction Y, and the extending direction of the gate G6 of the second noise reduction transistor T6 and the extending direction of the gate G7 of the first noise reduction transistor T7 may not be parallel, for example, they may intersect at a predetermined angle, for example, the intersecting angle is 20° or less, or the angle between both and the horizontal line is 20° or less, but the embodiment of the present disclosure is not limited thereto, and it is sufficient that the second noise reduction transistor T6 and the first noise reduction transistor T7 are integrally installed and arranged vertically.

[0133] For example, as shown in FIG. 4, the display substrate further includes a first connecting line L1 and a second connecting line L2 extending along the second direction Y. The first connecting line L1 and the second connecting line L2 are arranged in parallel and overlap the first transfer electrode E1 (shown in FIG. 7). The first end L11 of the first connecting line L1 is connected to the gate G6 of the second noise reduction transistor T6, and the second end L12 of the first connecting line L1 is connected to the end E221 of the second part E22 of the second transfer electrode E2, which is not in the same layer. The first end L21 of the second connecting line L2 is connected to the gate G7 of the first noise reduction transistor T7, and the second end L22 of the second connecting line L2 is connected to the second clock signal line GCB to receive the second clock signal. Therefore, both the first connecting line L1 and the second connecting line L2 are linear structures without bending, which makes the wiring structure of the display substrate more simple and saves wiring space.

[0134] For example, in other embodiments, the extension directions of the first connection wiring L1 and the second connection wiring L2 do not need to be parallel, and for example, the first connection wiring L1 and the second connection wiring L2 cross at a certain angle, for example, the crossing angle is 20° or less, or the angle between both of them and the horizontal line is 20° or less.

[0135] 4, 6 and 7, the second end L12 of the first connection wiring L1 is connected to the end E221 of the second portion E22 of the second transfer electrode E2 through a via hole GH2 that penetrates the second insulating layer 360 and the third insulating layer 370. The second end L22 of the second connection wiring L2 is connected to the second clock signal line GCB through a via hole GH7 that penetrates the second insulating layer 360 and the third insulating layer 370.

[0136] For example, as shown in Figure 2, the gate G8 of the voltage regulator transistor T8 is connected to the second power supply line VGL to receive the second voltage. For example, as shown in Figures 4, 6 and 7, the gate G8 of the voltage regulator transistor T8 is connected to the second power supply line VGL through a via hole GH8 that penetrates the second insulating layer 360 and the third insulating layer 370.

[0137] For example, as shown in FIG. 7, the second power line VGL has a protrusion E01 protruding in the second direction Y. For example, the second power line VGL and the protrusion E01 are integrally formed, and the protrusion E01 is located on the third conductive layer 340. The second pole SD32 of the second control transistor T3 is connected to the protrusion E01 of the second power line VGL to receive the second voltage. For example, the protrusion E01 of the second power line VGL is integrally formed with the second pole SD32 of the second control transistor T3. Also, for example, the protrusion E01 of the second power line VGL is used as the second pole SD32 of the second control transistor T3. For example, as shown in FIG. 3, FIG. 6 and FIG. 7, the second pole SD32 of the second control transistor T3 is connected to the active layer A3 of the second control transistor T3 through a via hole H32 penetrating the first insulating layer 350, the second insulating layer 360 and the third insulating layer 370.

[0138] For example, as shown in FIG. 4, the gate G1 of the input transistor T1 includes a first gate G11 and a second gate G12 arranged side by side to form a substantially "U"-shaped double-gate structure, so that the input transistor T1 is tightly closed when it is turned off to reduce leakage current. In this case, the active layer A1 of the input transistor T1 extends along a first direction X and has a strip shape (shown in FIG. 3), and the first gate G11 and the second gate G12 of the input transistor T1 are connected to the gate G3 of the second control transistor T3. The gate G3 of the second control transistor T3 is further connected to a first clock signal line GCK to provide a first clock signal to the gate G3 of the second control transistor T3 and the first gate G11 and the second gate G12 of the input transistor T1. This enhances the tightness of wiring and saves wiring space. Of course, the gate of the input transistor T1 may include only a single gate and overlap the active layer of the input transistor T1, and the embodiments of the present disclosure are not limited thereto.

[0139] For example, the structure having the source layer A1 of the input transistor T1 may be replaced with the structure of the gate G1 of the input transistor T1, and the input transistor T1 may be formed with a double-gate structure, for example, the active layer A1 is an approximately "U" shaped structure and the gate G1 is a strip shape along the second direction Y.

[0140] For example, as shown in Figures 4, 6 and 7, the gate G3 of the second control transistor T3 is connected to the first clock signal line GCK through a via hole GH6 that penetrates the second insulating layer 360 and the third insulating layer 370.

[0141] For example, as shown in FIG. 7, the display substrate further includes a third transfer electrode E3. The third transfer electrode E3 extends along the first direction X, and a first end E31 of the third transfer electrode E3 is connected to the gate G3 of the second control transistor T3 (shown in FIG. 4) and the first gate G11 and the second gate G12 of the input transistor T1. A second end of the third transfer electrode E3 is connected to the second pole SD22 of the first control transistor T2 and is integrally formed. In the first direction X, the second pole SD22 of the first control transistor T2 is adjacent to the gate G3 of the second control transistor T3 (shown in FIG. 4), so that the length of the third transfer electrode E3 is shorter than that of other transfer electrodes (e.g., the first transfer electrode E1 and the second transfer electrode E2), thereby increasing the compactness of the wiring of the display substrate, reducing the occupied space of the third transfer electrode E3 and the overlap with other wiring, and reducing the complexity of the wiring of the display substrate. However, the position of the second end of the third transfer electrode E3 and the second pole SD22 of the first control transistor T2 are considered to be the same, that is, are integrally formed, and therefore no reference numerals are shown in the figure.

[0142] For example, the third transfer electrode E3 does not have to be parallel to the first direction X, and for example, the third transfer electrode E3 and the first direction X intersect at a predetermined angle. For example, the intersecting angle is 20° or less.

[0143] For example, as shown in Figures 4, 6 and 7, the first end E31 of the third transfer electrode E3 is connected to the gate G3 of the second control transistor T3 and the first gate G11 and the second gate G12 of the input transistor T1 through a via hole GH3 that penetrates the second insulating layer 360 and the third insulating layer 370.

[0144] For example, as shown in Figures 3, 6 and 7, the second pole SD22 of the first control transistor T2 is connected to the active layer A2 of the first control transistor T2 through a via hole H22 that penetrates the first insulating layer 350, the second insulating layer 360 and the third insulating layer 370.

[0145] 2 and 3, the orthogonal projection of the first capacitor C1 on the base substrate 101 is located on the side closer to the display area 102 of the orthogonal projection of the active layer A4 of the output control transistor T4 on the base substrate 101, and the orthogonal projection of the first capacitor C1 on the base substrate 101 and the orthogonal projection of the first power line VGH on the base substrate 101 at least partially overlap. That is, the first capacitor C1 is located on the right side of the output control transistor T4 in the second direction Y, which brings the first capacitor C1 closer to the display area so as to leave more space for other parts in the shift register unit 104, such as transistors, transfer electrodes, power lines, etc., thereby reducing the overlap of wiring. This reduces the space occupied by the first capacitor C1.

[0146] For example, in another embodiment, if permitted by the design space of the shift register unit, the orthogonal projection of the first capacitor C1 on the base substrate 101 and the orthogonal projection of the first power supply line VGH on the base substrate 101 may not overlap. However, if the orthogonal projection of the first capacitor C1 on the base substrate 101 and the orthogonal projection of the first power supply line VGH on the base substrate 101 at least partially overlap, normal operation of the first capacitor C1 is not affected.

[0147] For example, as shown in Fig. 2, the first capacitor C1 has a rectangular shape. As shown in Fig. 4 and Fig. 5, the first pole CE11 and the second pole CE12 of the first capacitor C1 are both rectangular. A second insulating layer 360 is provided between the first pole CE11 and the second pole CE12.

[0148] 4, 6, and 7, the first pole CE11 of the first capacitor C1 is connected to the gate G4 of the output control transistor T4. For example, the first pole CE11 of the first capacitor C1 and the gate G4 of the output control transistor T4 may be integrally formed. The second pole CE12 of the first capacitor C1 is connected to the first power supply line VGH through a via hole GH9 that penetrates the third insulating layer 370.

[0149] For example, in another example, the second pole CE12 of the first capacitor C1 may further be located on a third conductive layer 340, in which case a second insulating layer 360 and a third insulating layer 370 are provided between the first pole CE11 and the second pole CE12.

[0150] Also, for example, in another example, the first pole CE11 of the first capacitor C1 may further be located on the first conductive layer 320, in which case a first insulating layer 350 and a second insulating layer 360 are provided between the first pole CE11 and the second pole CE12.

[0151] For example, as shown in Fig. 7, the display substrate further includes a fourth transfer electrode E4. The fourth transfer electrode E4 is connected to the first pole SD61 of the second noise reduction transistor T6 and the first pole SD41 of the output control transistor T4. For example, the fourth transfer electrode E4 extends from the first pole SD61 of the second noise reduction transistor T6 toward the output control transistor T4 along the first direction X, and then bends in the second direction Y to be connected to the first pole SD41 of the output control transistor T4, thereby reducing the complexity of wiring and the occupied space.

[0152] For example, as shown in FIG. 4, the gate G6 of the second noise reduction transistor T6 is connected to and integrally formed with the gate G4 of the output control transistor T4. For example, the connection wiring between the gate G6 of the second noise reduction transistor T6 and the gate G4 of the output control transistor T4 extends from the gate G6 of the second noise reduction transistor T6 toward the output control transistor along the first direction X, then bends in the second direction Y and connects to the gate G4 of the output control transistor T4. The orthogonal projection of the connection wiring between the gate G6 of the second noise reduction transistor T6 and the gate G4 of the output control transistor T4 on the base substrate does not overlap with the orthogonal projection of the fourth transfer electrode E4 (shown in FIG. 7) on the base substrate. This reduces the overlap of the connection wiring between the second noise reduction transistor T6 and the output control transistor T4 with other wiring, thereby reducing the complexity of the wiring and improving the space utilization rate.

[0153] 2 and 7, the fourth transfer electrode E4 also includes a second node N2. The fourth transfer electrode E4 is used to connect the first pole SD61 of the second noise reduction transistor T6 and the first pole SD41 of the output control transistor T4. The fourth transfer electrode E4 is located on the third conductive layer 340.

[0154] 3, 6 and 7, the first pole SD61 of the second noise reduction transistor T6 is connected to the active layer A6 of the second noise reduction transistor T6 through a via hole H61 that penetrates the first insulating layer 350, the second insulating layer 360 and the third insulating layer 370. The first pole SD41 of the output control transistor T4 is connected to the active layer A4 of the output control transistor T4 through a via hole H41 that penetrates the first insulating layer 350, the second insulating layer 360 and the third insulating layer 370.

[0155] 2, the orthogonal projection of the second capacitor C2 on the base substrate 101 is located between the orthogonal projection of the first power line VGH on the base substrate 101 and the orthogonal projection of the active layer A4 (shown in FIG. 3) of the output control transistor T4 and the active layer A5 (shown in FIG. 3) of the output transistor T5 on the base substrate 101. This brings the second capacitor C2 closer to the display area and reduces overlapping of wiring, so as to leave more space for other parts in the shift register unit 104, such as transistors, transfer electrodes, power lines, etc.

[0156] 4, the first pole CE21 of the second capacitor C2 is connected to the gate G5 of the output transistor T5. For example, the first pole CE21 of the second capacitor C2 and the gate G5 of the output transistor T5 may be integrally formed.

[0157] For example, as shown in Fig. 2, the second capacitor C2 has a rectangular shape. For example, as shown in Fig. 4 and Fig. 5, the first pole CE21 and the second pole CE22 of the second capacitor C2 both have rectangular shapes. A second insulating layer 360 is provided between the first pole CE21 and the second pole CE22.

[0158] For example, in another example, the second pole CE22 of the second capacitor C2 may further be located on a third conductive layer 340, in which case a second insulating layer 360 and a third insulating layer 370 are provided between the first pole CE21 and the second pole CE22.

[0159] Also, for example, in another example, the first pole CE21 of the second capacitor C2 may further be located on the first conductive layer 320, in which case a first insulating layer 350 and a second insulating layer 360 are provided between the first pole CE21 and the second pole CE22.

[0160] For example, as shown in Figures 4 and 7, the display substrate further includes a fifth transfer electrode E5. The first pole SD51 of the output transistor T5 is connected to the first end E51 of the fifth transfer electrode E5, and the gate G7 of the first noise reduction transistor T7 is connected to the fifth transfer electrode E5. For example, the orthogonal projection of the fifth transfer electrode E5 on the base substrate 101 does not overlap with the orthogonal projections of the first transfer electrode E1 and the fourth transfer electrode E4 on the base substrate 101, so that the fifth transfer electrode E5 does not overlap with other wirings, thereby reducing the complexity of wiring and improving space utilization.

[0161] For example, as shown in Figures 3, 6 and 7, the first pole SD51 of the output transistor T5 is connected to the active layer A5 of the output transistor T5 through a via hole H51 that penetrates the first insulating layer 350, the second insulating layer 360 and the third insulating layer 370.

[0162] For example, as shown in Figures 4, 6 and 7, the gate G7 of the first noise reduction transistor T7 is connected to the fifth transfer electrode E5 through a via hole GH4 that penetrates the second insulating layer 360 and the third insulating layer 370.

[0163] For example, as shown in FIG. 7, the display substrate further includes a sixth transfer electrode E6 extending in parallel along the second direction Y. The gate G5 of the output transistor T5 is connected to a first end E61 of the sixth transfer electrode E6, and a second end of the sixth transfer electrode E6 is connected to a second pole SD82 of the voltage regulator transistor T8. For example, the orthogonal projection 101 of the sixth transfer electrode E6 on the base substrate does not overlap with the orthogonal projection of the first transfer electrode E1 on the base substrate 101. This reduces the space occupied by the sixth transfer electrode E6, reduces the overlap with other wiring, and reduces the occurrence of parasitic capacitance. However, the positions of the second end of the sixth transfer electrode E6 and the second pole SD82 of the voltage regulator transistor T8 are considered to be the same, are integrally formed, and are not indicated with a symbol in the figure.

[0164] For example, the sixth transfer electrode E6 does not have to be parallel to the second direction Y, and for example, the sixth transfer electrode E6 and the second direction Y intersect at a predetermined angle. For example, the intersecting angle is 20° or less.

[0165] For example, as shown in Figures 4, 6 and 7, the gate G5 of the output transistor T5 is connected to the first end E61 of the sixth transfer electrode E6 through a via hole GH5 that penetrates the second insulating layer 360 and the third insulating layer 370.

[0166] For example, as shown in FIGS. 3, 6 and 7, the second pole SD82 of the voltage regulator transistor T8 is connected to the active layer A8 of the voltage regulator transistor T8 through a via hole H82 that penetrates the first insulating layer 350, the second insulating layer 360 and the third insulating layer 370.

[0167] 2 and 7, the sixth transfer electrode E6 comprises a third node N3. For example, the sixth transfer electrode E6 is implemented as a third node N3 and configured to connect to the second pole SD82 of the voltage regulator transistor T8 and the gate G5 of the output transistor T5 (shown in FIG. 4). The sixth transfer electrode E6 is located on the third conductive layer 340.

[0168] For example, as shown in FIG. 7, the display substrate further includes a seventh transfer electrode E7, and a first end E71 of the seventh transfer electrode E7 is connected to the second pole SD42 of the output control transistor T4, and a second end E72 of the seventh transfer electrode E7 is connected to the second pole SD52 of the output transistor T5. For example, the seventh transfer electrode E7 extends along the first direction X. For example, the orthogonal projection of the seventh transfer electrode E7 on the base substrate is located between the first power line VGH and the orthogonal projection of the active layer A4 (shown in FIG. 3) of the output control transistor T4 and the active layer A5 of the output transistor T5 (shown in FIG. 3) on the base substrate. This reduces the occupied space of the seventh transfer electrode E7 and reduces the overlap with other wiring, thereby reducing the occurrence of parasitic capacitance and reducing the complexity of the wiring of the display substrate.

[0169] For example, as shown in FIGS. 4, 6 and 7, the seventh transfer electrode E7 is connected to the second pole CE22 of the second capacitor C2 through a via hole GH10 that penetrates the third insulating layer 370.

[0170] 3, 6 and 7, the second pole SD42 of the output control transistor T4 is connected to the active layer A4 of the output control transistor T4 through a via hole H42 penetrating the first insulating layer 350, the second insulating layer 360 and the third insulating layer 370. The second pole SD52 of the output transistor T5 is connected to the active layer A5 of the output transistor T5 through a via hole H52 penetrating the first insulating layer 350, the second insulating layer 360 and the third insulating layer 370.

[0171] For example, as shown in FIG. 7, the second pole SD52 of the output transistor T5 is connected to the second pole SD12 of the input transistor T1 of the lower-stage shift register unit adjacent to the shift register unit 104, so that the output signal of the second pole SD52 of the output transistor T5 serves as the input signal of the second pole SD12 of the input transistor T1 of the lower-stage shift register unit.

[0172] For example, as shown in Figures 3, 6 and 7, the second pole SD12 of the input transistor T1 is connected to the active layer A1 of the input transistor T1 through a via hole H12 that penetrates the first insulating layer 350, the second insulating layer 360 and the third insulating layer 370.

[0173] For example, as shown in Figures 4, 6 and 7, the second pole SD12 of the input transistor T1 and the second pole SD42 of the output control transistor T4 are connected to the output end GOUT of the shift register unit through a via hole GH11 penetrating the second insulating layer 360 and the third insulating layer 370, and output an output signal to the output end.

[0174] 3, the active layer A4 of the output control transistor T4 and a part of the active layer A5 of the output transistor T5 (the part of the active layer A5 located in the same column as the active layer A4 in the first direction X) are located in one continuous second semiconductor layer, and the second semiconductor layer extends along the first direction X. As long as it does not affect the layout of other structures and does not excessively increase the width of the shift register unit, the active layer A4 of the output control transistor T4 may be offset from the part of the active layer A5 of the output transistor T5 by a certain distance in the first direction, and the embodiments of the present disclosure are not limited thereto.

[0175] 3 and 7, the active layer A5 of the output transistor T5 includes two portions, one of which and the active layer A4 of the output control transistor T4 are located in a continuous second semiconductor layer extending in one first direction X, and the other portion is located on the side of the active layer A4 of the output control transistor T4 close to the voltage regulator transistor T8 (for example, located below the active layer A7 of the first noise reduction transistor T7 in FIG. 3), and the length of the part of the first pole SD51 and the part of the second pole SD52 close to the voltage regulator transistor T8 of the output transistor T5 (for example, the two first poles SD51 and second poles SD52 extending along the second direction Y away from the output control transistor T4 in FIG. 7) is greater than the length of the first pole SD51 and the second pole SD52 at other positions. This increases the width of the output transistor T5 in the second direction Y, thereby improving the signal output capability of the output transistor T5.

[0176] For example, in another embodiment, a portion of the active layer A5 of the output transistor T5 located on the side of the active layer A4 of the output control transistor T4 closer to the voltage regulator transistor T8 (for example, located below the active layer A7 of the first noise reduction transistor T7 in FIG. 3) extends toward the active layer A4 of the output control transistor T4 and is connected to another portion of the active layer A5. For example, as shown in FIG. 4, the gate G4 of the output control transistor T4 and the gate G5 of the output transistor T5 extend along the second direction Y and are arranged side by side in the first direction X. For example, the gate G4 of the output control transistor T4 and the gate G5 of the output transistor T5 may be parallel, for example, both extending along the second direction Y, and the extension direction of the gate G4 of the output control transistor T4 and the extension direction of the gate G5 of the output transistor T5 do not have to be parallel, for example, they may intersect at a predetermined angle, for example, the intersecting angle is 20° or less, or the angle between both of them and the horizontal line is 20° or less, but the embodiments of the present disclosure are not limited to this, and it is sufficient that the output control transistor T4 and the output transistor T5 are integrally installed and arranged one above the other.

[0177] For example, as shown in FIG. 7, the first pole SD41 of the output control transistor T4 is connected to the first power supply line VGH to receive the first voltage, thereby reducing the space occupied by the connecting wiring and the complexity of the wiring.

[0178] In addition, in the embodiment of the present disclosure, for example, the first transfer electrode E1, the second transfer electrode E2, the third transfer electrode E3, the fourth transfer electrode E4, the fifth transfer electrode E5, the sixth transfer electrode E6, and the seventh transfer electrode E7 are all located on the third conductive layer 340. The first transfer electrode E1 is used to connect the electrodes of the first noise reduction transistor T7, the voltage regulator transistor T8, and the first control transistor T2, and has a first node N1. The second transfer electrode E2 is used to connect the electrodes of the first control transistor T2 and the second control transistor T3. The second transfer electrode E2 has a second node N2. The third transfer electrode E3 is used to connect the electrodes of the second control transistor T3, the input transistor T1, and the first control transistor T2. The fourth transfer electrode E4 is used to connect the electrodes of the second noise reduction transistor T6 and the output control transistor T4. The fifth transfer electrode E5 is used to connect the electrodes of the first noise reduction transistor T7 and the output transistor T5. The sixth transfer electrode E6 is used to connect the electrodes of the output transistor T5 and the voltage regulator transistor T8. The sixth transfer electrode E6 comprises a third node N3. The seventh transfer electrode E7 is used to connect the electrodes of the output transistor T5 and the output control transistor T4. Depending on the needs of the wiring layout in the shift register 104, the first transfer electrode E1, the second transfer electrode E2, the third transfer electrode E3, the fourth transfer electrode E4, the fifth transfer electrode E5, the sixth transfer electrode E6 and the seventh transfer electrode E7 may be disposed in other layers without affecting the circuit function, for example, the seventh transfer electrode E7 is disposed in the second conductive layer 330.

[0179] For example, in some embodiments of the present disclosure, the line width of each layer wiring is, for example, generally 3 microns, and the interval between wirings located on the same layer is, for example, greater than 3 microns. For example, the interval between the wirings is, for example, related to the precision of the exposure device, and the higher the precision of the exposure device, the smaller the interval, and can be specifically determined according to the actual situation, and the embodiments of the present disclosure are not limited thereto. In the embodiments of the present disclosure, in order to avoid adhesion of wiring and signal short circuit in the actual process, it is necessary to provide a necessary interval between wirings on the same layer.

[0180] For example, as shown in Fig. 4, the interval between the orthogonal projection of each wire of the first conductive layer 320 on the base substrate 101 and the orthogonal projection of each wire of the second conductive layer 330 on the base substrate 101 is, for example, typically 1.5 microns, and the gate of the transistor in the first conductive layer 320 must exceed the active layer of the semiconductor layer 310 by, for example, 2 microns or more. For example, as shown in Figs. 2, 3 and 4, the orthogonal projection of the first gate and the second gate of the first transistor T1 on the base substrate 101 exceeds both sides of the orthogonal projection of the active layer A1 of the first transistor T1 on the base substrate 101 in the second direction Y by, for example, 2 microns or more, and the embodiment of the present disclosure is not limited in this regard.

[0181] For example, as shown in FIG. 3 to FIG. 5, the interval between the orthogonal projection of the active layer (e.g., active layer A1 to active layer A8) of each transistor in the semiconductor layer 310 on the base substrate 10 and the orthogonal projection of each connection wiring (e.g., the first connection line L1 and the second connection line L2) in the first conductive layer 320 on the base substrate 101 is 1.5 microns or more, thereby making it possible to avoid the occurrence of a channel effect between the connection wiring and the active layer of each transistor in the semiconductor layer 310. For example, the interval between the orthogonal projection of the semiconductor layer 310 on the base substrate 10 and the orthogonal projection of the second conductive layer 330 on the base substrate 10 is not limited, and they may be placed overlapping each other. For example, in some embodiments of the present disclosure, a predetermined interval (this interval is smaller than the interval between the wirings of the same layer) is ensured as much as possible between the wirings of different layers, reducing unnecessary overlap and avoiding interference due to excessive parasitic capacitance.

[0182] For example, as shown in Figures 2 and 6, for via holes connecting the source or drain electrodes of the transistors and the active layers of the input transistor T1 through the voltage regulator transistor T8, for example, via holes H11, H12 through via holes H81, H82, the numbers of the via holes H11, H12 through via holes H81, H82 are different in Figure 6. The via holes H41 and H42 of the output control transistor T4 are multiple in the second direction Y (for example, six each in Figure 6), and the via holes H51 and H52 of the output transistor T5 are arranged in multiple rows in the first direction X and multiple in the second direction Y, thereby increasing the strength and density of the connection between the source or drain electrodes of the transistors and the active layers, and reducing the possibility of leakage current generation. For example, the first poles (e.g., SD11, SD21, etc. in FIG. 7) or second poles (e.g., SD12, SD22, etc. in FIG. 7) of the input transistor T1, the first control transistor T2, the second control transistor T3, the first noise reduction transistor T7 and the second noise reduction transistor T6 are each connected to a corresponding active layer (e.g., A1, A2, etc. in FIG. 3) through one via hole (e.g., H11, H12, etc.). For example, two via holes H81 connect the drain electrode region D8 (shown in FIG. 3) of the voltage regulator transistor T8 to the first pole SD81 (shown in FIG. 7) of the voltage regulator transistor T8, and two via holes H82 connect the source electrode region S8 (shown in FIG. 3) of the voltage regulator transistor T8 to the second pole SD82 (shown in FIG. 7) of the voltage regulator transistor T8, and the provision of two via holes H81 and two via holes H82 can increase the strength and tightness of the connection between the source electrode or drain electrode of the transistor and the active layer, and reduce the possibility of leakage current. For example, the number of via holes GH1-GH11 connecting the first conductive layer 320 and the third conductive layer 340 is not the same, and each of the via holes GH1-GH3 is one, each of the via holes GH4-GH9 and GH11 is two, and the number of GH10 is six.For example, when two via holes GH4 connect the gate G7 of the first noise reduction transistor T7 to the fifth transfer electrode E5, the strength and density of the connection between the gate G7 and the fifth transfer electrode E5 can be increased, and the possibility of leakage current can be reduced. That is, if the arrangement space of the shift register unit allows, increasing the number of via holes can increase the strength and density of the connection between the electrodes, and reduce the possibility of leakage current.

[0183] However, the number of via holes (e.g., via holes H11, H12 to H81, H82, and via holes GH1 to GH11) shown in FIG. 3 can be changed according to the design needs of the transistors, connecting wiring, etc. of the shift register unit, and the embodiments of the present disclosure are not limited in this regard.

[0184] For example, as shown in FIG. 6 and FIG. 7, the width of each wiring in the third conductive layer 340 needs to cover the corresponding via hole (for example, via holes H11, H12 to H81, H82, and via holes GH1 to GH11), and for example, exceeds the size of the via hole (for example, the diameter of the via hole) by 1 micron or more, for example, the size of the via hole is 2.0 to 2.5 microns, and the width of each wiring covering the via hole in the third conductive layer 340 is 4 to 5 microns. For example, the width of the wiring corresponding to the via holes (H41, H42, H51, H52) of the output control transistor T4 and the output transistor T5 exceeds the via hole by 1 micron above and below, for example, 4.0 to 4.5 microns. Since there are many corresponding via holes of the output control transistor T4 and the output transistor T5, the width of the wiring connected to other transistors and located in the third conductive layer 340 only needs to satisfy the requirement of covering the via hole by more than 1 micron at the position of the via hole, and for example, the width of the wiring between the via holes may be narrow.

[0185] For example, as shown in FIG. 7 , the spacing between the wirings such as the first clock signal line GCK, the second clock signal line GCB, the first power supply line VGH, the second power supply line VGL, etc. located on the third conductive layer 340 is 3 microns or more, the line width of the first clock signal line GCK and the second clock signal line GCB is 9 microns or more to meet the requirements of driving capability, the line width of the second power supply line VGL may be 6, 9 or 10 microns, the line width of the first power supply line VGH is, for example, 10 microns, and the second voltage provided by the second power supply line VGL is, for example, generally −7V.

[0186] For example, in some examples, the first conductive layer 320 and the second conductive layer 330 have a thickness of 2000-300 angstroms, and the third conductive layer 340 has a thickness of 5000-8000 angstroms, although embodiments of the present disclosure are not limited in this respect.

[0187] At least one embodiment of the present disclosure further provides a display device. Figure 9 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in Figure 9, the display device 2 includes a display substrate 1 according to any embodiment of the present disclosure, for example, the display substrate 1 shown in Figure 2.

[0188] However, the display device 2 may be any product or component having a display function, such as an OLED panel, an OLED TV, a QLED panel, a QLED TV, a mobile phone, a tablet PC, a notebook computer, a digital frame, a navigator, etc. The display device 2 may further include other components, such as a data driving circuit, a timing controller, etc., and the embodiments of the present disclosure are not limited thereto.

[0189] However, for the sake of clarity and conciseness, the embodiments of the present disclosure do not disclose all the components of the display device, and those skilled in the art can provide and install other structures not shown according to specific needs to realize the substrate function of the display device, and the embodiments of the present disclosure are not limited thereto.

[0190] The technical effects of the display device 2 according to the above embodiment may refer to the technical effects of the display substrate 1 according to the embodiment of the present disclosure, and detailed description thereof will be omitted here.

[0191] At least one embodiment of the present disclosure further provides a method for producing a display substrate. Figure 10 is a flow chart of a method for producing a display substrate according to at least one embodiment of the present disclosure. For example, the method can be applied to the manufacture of a display substrate according to any embodiment of the present disclosure. For example, the method can be applied to the manufacture of the display substrate shown in Figure 2.

[0192] As shown in FIG. 10, the method for manufacturing the display substrate includes steps S100 to S200.

[0193] Step S100, a base substrate having a display area and at least a peripheral area surrounding the display area is provided.

[0194] Step S200: forming a shift register unit, a first clock signal line, a second clock signal line, a first power supply line and a second power supply line on a peripheral region of a base substrate.

[0195] In step S100, for example, the base substrate 101 may be made of, for example, glass, plastic, quartz, or other suitable materials, and the embodiments of the present disclosure are not limited thereto. For example, an insulating material is deposited on the base substrate 101 and a barrier layer 390 is formed by a patterning process. For example, the insulating material may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, etc., and the patterning process includes coating a photoresist layer on the insulating material, exposing the photoresist layer using a mask, developing the exposed photoresist layer to obtain a photoresist pattern, and etching the insulating material using the photoresist pattern, and then selectively removing the photoresist pattern. Also, for example, an insulating material is deposited on the barrier layer 390 and a buffer layer 3100 is formed by a patterning process.

[0196] In step S200, the step of forming a shift register unit, a first clock signal line, a second clock signal line, a first power supply line and a second power supply line in the peripheral region of the base substrate includes forming a semiconductor layer on the base substrate and patterning the semiconductor layer to form active layers (active layer A1 to active layer A8) of a plurality of transistors (input transistor T1 to voltage regulator transistor T8) in each circuit of the shift register. A first insulating material layer is formed on a side of active layers of a plurality of transistors that is away from the base substrate, the first insulating material layer is patterned to form a first insulating layer 350 having via holes, a first conductive material layer is formed on a side of the first insulating layer that is away from the base substrate, the first conductive material is patterned to form gates (gate G1 to gate G8) of a plurality of transistors, a plurality of connection wirings (first connection wiring L1, second connection wiring L2) and first poles (first pole CE11 and first pole CE21) of a plurality of capacitors (first capacitor C1 and second capacitor C2) of each circuit (input circuit 1041, output circuit 1043, first control circuit 1042, output control circuit 1044, second control circuit 1045 and voltage regulator circuit 1046), a second insulating material layer is formed on a side of the gates of the plurality of transistors that is away from the base substrate, and the second insulating material layer is patterned to form via holes. a second insulating layer 360 having via holes, a second conductive material layer is formed on a side of the second insulating layer away from the base substrate, the second conductive material is patterned to form second poles (second pole CE12 and second pole CE22) of the plurality of capacitors, a third insulating material layer is formed on the second insulating layer and sides of second capacitor plates of the plurality of capacitors away from the base substrate, the third insulating material layer is patterned to form a third insulating layer 370 having via holes, a third conductive material layer is formed on the side of the third insulating layer away from the base substrate, and the third conductive material is patterned to form first poles (first pole SD11 to first pole SD81) and second poles (second pole SD12 to second pole SD82) of the plurality of transistors, a plurality of transfer electrodes (first transfer electrode E1 to seventh transfer electrode E7), a first clock signal line GCK, a second clock signal line GCB, a first power supply line VGH, and a second power supply line VGL.

[0197] For example, the material of the semiconductor layer may include polysilicon or an oxide semiconductor (e.g., indium gallium zinc oxide), etc. The materials of the first insulating material, the second insulating material, and the third insulating material may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc. The first conductive material, the second conductive material, and the third conductive material may include metal materials or alloy materials.

[0198] For example, the first pole sum of the second pole of each transistor is connected to the active layer (active layer A1 to active layer A8) of each transistor through a via hole (e.g., via hole H11, via hole H12 to via hole H81, via hole H82) that penetrates the first insulating layer, the second insulating layer, and the third insulating layer, and each transistor and each capacitor is connected to each other through a plurality of connection wirings or a plurality of transfer electrodes and through via holes (e.g., via hole GH1 to via hole GH11) that penetrate the second insulating layer and the third insulating layer, and is connected to the first clock signal line GCK, the second clock signal line GCB, the first power supply line VGH, and the second power supply line VGL.

[0199] For example, a fourth insulating material layer is formed on the side of the third conductive layer 340 away from the base substrate, and then patterned to form the fourth insulating layer 380. For example, the fourth insulating material may include an inorganic insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable material.

[0200] Regarding the establishment of the connection structure between each transistor and capacitor of the shift register unit 104 and the first power supply line VGH, the second power supply line VGL, the multiple clock signal lines, the connection wiring, and the transfer electrodes, the explanations of Figures 2 to 8 can be referred to, and detailed explanations will be omitted here.

[0201] However, in various embodiments of the present disclosure, the manufacturing method flow of the display substrate may include more or less operations, and the operations may be performed sequentially or in parallel. Although the manufacturing method flow described above includes operations that appear in a specific order, it should be clearly understood that the order of the operations is not limited. The manufacturing method described above may be performed only once, or may be performed multiple times under certain conditions.

[0202] The technical effects of the manufacturing method for a display substrate according to the above embodiment may be referred to the technical effects of the display substrate according to the embodiment of the present disclosure, and detailed description thereof will be omitted here.

[0203] A few points need to be explained:

[0204] (1) The drawings of the embodiments of the present disclosure only relate to structures related to the embodiments of the present disclosure, and for other structures, reference may be made to conventional designs.

[0205] (2) Where no contradiction exists, the embodiments and features of the embodiments of the present disclosure may be combined with each other to obtain new embodiments.

[0206] The above are merely exemplary embodiments of the present disclosure, and do not limit the protection scope of the present disclosure, which is defined by the appended claims.

Claims

1. A display substrate, a base substrate having a display area and a peripheral area located on at least one side of the display area; a shift register unit disposed in a peripheral region of the base substrate, a first clock signal line, and a second clock signal line; the first clock signal line and the second clock signal line extend along a first direction in the base substrate and are configured to provide a first clock signal and a second clock signal to the shift register unit, respectively; the shift register unit includes an input circuit, an output circuit, a first control circuit, a second control circuit, and a voltage regulator circuit; the input circuit is configured to input an input signal to a first node in response to the first clock signal; the first control circuit is connected to the first node and the second node and configured to control a level of the second node in response to a level of the first node and the first clock signal; the second control circuit is connected to the first node and the second node, and is configured to control the level of the first node by control of the level of the second node and the second clock signal; the voltage regulator circuit is connected to the first node and a third node and configured to stabilize a level of the third node; the output circuit is connected to the third node and is configured to output an output signal to an output terminal under control of a level of the third node; the first control circuit comprises a first control transistor, the second control circuit comprises a first noise reduction transistor, the voltage regulator circuit comprises a voltage regulator transistor, a gate of the first control transistor, a first pole of the first noise reduction transistor and a first pole of the voltage regulator transistor are all connected to the first node; a first pole of the first noise reduction transistor and a first pole of the voltage regulator transistor are located in a first source-drain electrode layer having a first transfer electrode; the first transfer electrode comprises a first portion extending parallel to a second direction different from the first direction, and a second portion integrally formed with the first portion and extending in the first direction, a first end of the first portion being connected to a first pole of the first noise reduction transistor, a second end of the first portion being connected to a first pole of the voltage regulator transistor, and the second portion being connected to a gate of the first control transistor not in the same layer; a second transfer electrode, and the first control circuit further comprises a second control transistor; the second transfer electrode includes a first portion and a second portion parallel to the second direction, an end of the first portion of the second transfer electrode is connected to a first pole of the second control transistor, and the second portion of the second transfer electrode is connected to a first pole of the first control transistor; The second transfer electrode comprises the second node.

2. the first transfer electrode further includes a third portion extending parallel to the second direction, the third portion being connected to the second portion, and the third portion being arranged side by side with the first portion in the first direction; the input circuit includes an input transistor, an orthogonal projection of an active layer of the input transistor on the base substrate is located between an orthogonal projection of an active layer of the first control transistor on the base substrate and an orthogonal projection of an active layer of the first noise reduction transistor on the base substrate; 2. The display substrate according to claim 1, wherein a first electrode of the input transistor is connected to an end of the third portion.

3. The display substrate according to claim 1 , wherein the first transfer electrode comprises the first node.

4. The display substrate according to claim 1 , wherein an orthogonal projection of an active layer of the second control transistor on the base substrate is located on a side away from the display region of an orthogonal projection of an active layer of the first control transistor on the base substrate.

5. the second control circuit further comprises a second noise reduction transistor; an active layer of the second noise reduction transistor and an active layer of the first noise reduction transistor are located in a continuous first semiconductor layer, and the first semiconductor layer extends in a first direction, and a gate of the second noise reduction transistor and a gate of the first noise reduction transistor extend in a second direction and are arranged side by side in the first direction; the display substrate further includes a first connection wiring and a second connection wiring extending in the second direction, the first connection wiring and the second connection wiring being arranged in parallel, and the first connection wiring and the second connection wiring each overlap with the first transfer electrode; a first end of the first connection wiring is connected to a gate of the second noise reduction transistor, and a second end of the first connection wiring is connected to an end of a second portion of the second transfer electrode that is not in the same layer; 2. The display substrate of claim 1, wherein a first end of the second connection wiring is connected to a gate of the first noise reduction transistor, and a second end of the second connection wiring is connected to the second clock signal line to receive the second clock signal.

6. 6. The display substrate according to claim 5, wherein the orthogonal projections of the active layer of the second noise reduction transistor and the active layer of the first noise reduction transistor on the base substrate are located on a side closer to the display area than the orthogonal projection of the active layer of the first control transistor on the base substrate.

7. the shift register unit further includes a first insulating layer, a second insulating layer, and a third insulating layer; the first insulating layer is located between an active layer of the first control transistor and a gate of the first control transistor, the second insulating layer and the third insulating layer are located between the first transfer electrode and the gate of the first control transistor, a gate of the first control transistor is connected to a second portion of the first transfer electrode through a via hole penetrating the second insulating layer and the third insulating layer; and 7. The display substrate according to claim 5, wherein a second end of the first connection wiring is connected to an end of a second portion of the second transfer electrode through a via hole penetrating the second insulating layer and the third insulating layer.

8. 8. The display substrate according to claim 1, wherein the orthogonal projection of the active layer of the voltage regulator transistor on the base substrate is located on a side away from the display area of ​​the orthogonal projection of the active layer of the first control transistor on the base substrate.

9. The display substrate of claim 1 , wherein an included angle between the first direction and the second direction is between 70° and 90°.

10. The display substrate according to claim 1 , wherein the first clock signal line and the second clock signal line are located on a side of the shift register unit that is away from the display area.

11. a first power supply line configured to provide a first voltage to the shift register unit; the first power supply line extends in the first direction on the base substrate and is connected to the second control circuit; The display substrate according to claim 5 , wherein an orthogonal projection of the first power supply line on the base substrate is located on a side closer to the display area than an orthogonal projection of the shift register unit on the base substrate.

12. Further comprising a second power supply line; the second power supply line extends in the first direction on the base substrate and is configured to provide a second voltage to the shift register unit; an orthogonal projection of the second power supply line on the base substrate is located between an orthogonal projection of the first clock signal line and the second clock signal line on the base substrate and an orthogonal projection of the shift register unit on the base substrate; The display substrate of claim 1 , wherein a gate of the voltage regulator transistor is connected to the second power line to receive the second voltage.

13. the second power line includes a protruding portion protruding in the second direction, The display substrate of claim 12 , wherein a second electrode of the second control transistor is connected to a protrusion of the second power line to receive the second voltage.

14. the input transistor comprises a first gate and a second gate arranged side by side; a first gate and a second gate of the input transistor are connected to a gate of the second control transistor; 3. The display substrate of claim 2, wherein the gate of the second control transistor is further connected to the first clock signal line, the first clock signal line providing the first clock signal to the gate of the second control transistor and the first gate and the second gate of the input transistor.

15. a third transfer electrode extending in the first direction; 15. The display substrate of claim 14, wherein a first end of the third transfer electrode is connected to a gate of the second control transistor and a first gate and a second gate of the input transistor through a via hole penetrating an insulating layer, and a second end of the third transfer electrode is connected to a second electrode of the first control transistor.

16. The shift register unit further includes an output control circuit; the output control circuit is configured to control a level of the output terminal by control based on a level of the second node; the output control circuit comprises an output control transistor and a first capacitor; 12. The display substrate of claim 11, wherein the orthogonal projection of the first capacitor on the base substrate is located on a side closer to the display area than the orthogonal projection of the active layer of the output control transistor on the base substrate, and the orthogonal projection of the first capacitor on the base substrate at least partially overlaps with the orthogonal projection of the first power supply line on the base substrate.

17. The display substrate of claim 16, wherein the first capacitor is rectangular in shape.

18. Further comprising a fourth transfer electrode; the fourth transfer electrode is connected to a first electrode of the second noise reduction transistor and a first electrode of the output control transistor; a gate of the second noise reduction transistor is connected to a gate of the output control transistor; 18. A display substrate according to claim 16 or 17, wherein the fourth transfer electrode also comprises the second node.

19. Further comprising a fifth transfer electrode; the output circuit includes an output transistor and a second capacitor, and an orthogonal projection of the second capacitor on the base substrate is located on a side away from the display area of ​​an orthogonal projection of the first power line on the base substrate; 19. A display substrate according to claim 16, wherein a first electrode of the output transistor is connected to a first end of the fifth transfer electrode, and a gate of the first noise reduction transistor is connected to the fifth transfer electrode through a via hole penetrating an insulating layer.

20. 20. The display substrate of claim 19, wherein the second capacitor is rectangular.

21. a sixth transfer electrode extending in the second direction; a gate of the output transistor is connected to a first end of the sixth transfer electrode through a via hole penetrating an insulating layer, and a second end of the sixth transfer electrode is connected to a second pole of the voltage regulator transistor; 21. The display substrate of claim 19, wherein the sixth transfer electrode comprises the third node.

22. Further comprising a seventh transfer electrode; a first end of the seventh transfer electrode is connected to a second pole of the output control transistor, and a second end of the seventh transfer electrode is connected to a second pole of the output transistor; 22. The display substrate of claim 19, wherein a second electrode of the output transistor is connected to a second electrode of an input transistor of a lower-stage shift register unit adjacent to the shift register unit.

23. an active layer of the output control transistor and at least a portion of an active layer of the output transistor are located in a continuous second semiconductor layer, and the second semiconductor layer extends in the first direction; 23. A display substrate according to claim 19, wherein a gate of the output control transistor and a gate of the output transistor extend in the second direction and are arranged side by side in the first direction, and a first electrode of the output control transistor is connected to the first power supply line to receive the first voltage.

24. A display device comprising the display substrate according to claim 1 .

25. 25. The display device according to claim 24, further comprising pixel units arranged in an array, wherein an output signal output by an output circuit of the shift register unit serves as a gate scanning signal to drive the pixel units to emit light.

26. A method for manufacturing a display substrate according to claim 1, comprising the steps of: providing a base substrate comprising a display area and a peripheral area surrounding at least the display area; forming a shift register unit, a first clock signal line, a second clock signal line, a first power supply line, and a second power supply line in a peripheral region of the base substrate, forming a semiconductor layer on a base substrate, and patterning the semiconductor layer to form active layers of a plurality of transistors in each circuit of the shift register unit; forming a first insulating material layer on a side of the active layers of the plurality of transistors away from the base substrate, and patterning the first insulating material layer to form a first insulating layer having via holes; forming a first conductive material layer on a side of the first insulating layer away from the base substrate, and patterning the first conductive material layer to form gates of the plurality of transistors, a plurality of connecting wires, and first poles of a plurality of capacitors in each circuit; forming a second insulating material layer on a side of the gates of the plurality of transistors away from the base substrate, and patterning the second insulating material layer to form a second insulating layer having via holes. forming a second conductive material layer on a side of the second insulating layer away from the base substrate and patterning the second conductive material layer to form second poles of the plurality of capacitors; forming a third insulating material layer on a side of the second insulating layer and second capacitor plates of the plurality of capacitors away from the base substrate and patterning the third insulating material layer to form a third insulating layer having via holes; forming a third conductive material layer on a side of the third insulating layer away from the base substrate and patterning the third conductive material layer to form first and second poles of the plurality of transistors, a plurality of transfer electrodes, the first clock signal line, the second clock signal line, the first power supply line and the second power supply line, a first pole and a second pole of each transistor are connected to an active layer of each transistor through a via hole penetrating the first insulating layer, the second insulating layer, and the third insulating layer, and each transistor and each capacitor are connected to each other through the plurality of connection wirings or the plurality of transfer electrodes and through a via hole penetrating the second insulating layer and the third insulating layer, and are connected to the first power supply line, the second power supply line, the first clock signal line, and the second clock signal line.

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