Ion beam etching with sidewall cleaning

Abstract

A patterned magnetoresistive random access memory (MRAM) stack is formed by performing a main etch through multiple MRAM layers disposed on a substrate, the main etch including the use of ion beam etching (IBE). After the main etch, a gap fill dielectric material is deposited in spaces between the patterned MRAM stacks, and the gap fill dielectric material is selectively etched or formed to an etch depth above the depth of the underlying layer. After the gap fill dielectric material is formed, at least a portion of the gap fill dielectric material and conductive material deposited on the sidewalls of the patterned MRAM stack is removed by performing an IBE trim etch.

Description

[Technical field]

[0001] [Incorporated by reference] A PCT application is being filed contemporaneously herewith as a part of this application, and each application identified in that contemporaneously filed PCT application to which this application claims benefit or priority is hereby incorporated by reference in its entirety for all purposes. [Background technology]

[0002] Magnetic random access memory (MRAM) is a non-volatile memory that utilizes magnetoresistance effects such as tunneling magnetoresistance (TMR). MRAM has high integration density comparable to static random access memory (SRAM) and high speed performance comparable to dynamic random access memory (DRAM). Because the materials in MRAM stacks are highly non-volatile and sensitive to reactive chemicals, ion beam etching techniques are typically used to etch the MRAM stacks.

[0003] The background description provided herein is intended to provide a general overview of the contents of the present disclosure. Work by the currently named inventors within the scope of what is described in this Background section, as well as aspects of the description that may not otherwise be regarded as prior art at the time of filing, are not admitted, expressly or impliedly, as prior art against the present disclosure. Summary of the Invention

[0004] A method of ion beam etching is provided herein. The method includes etching through a plurality of magnetoresistive random access memory (MRAM) layers disposed on a substrate to form a patterned MRAM stack, the plurality of MRAM layers including one or more magnetic layers and a tunnel barrier layer, and the etching through the plurality of MRAM layers includes ion beam etching (IBE) through at least the tunnel barrier layer. The method further includes forming a gap fill dielectric material in a space between the patterned MRAM stacks and performing an IBE trim etch to remove at least a portion of the gap fill dielectric material and the conductive material deposited on the sidewalls of the patterned MRAM stack.

[0005] In some embodiments, the gap-fill dielectric material is formed to a sufficient depth above an underlayer disposed between the substrate and the plurality of MRAM layers such that performing the IBE trim etch does not recess the underlayer. In some embodiments, the sufficient depth above the underlayer is between about 1 nm and about 20 nm from a top surface of the underlayer. In some embodiments, forming the gap-fill dielectric material in the spaces between the patterned MRAM stacks comprises depositing the gap-fill dielectric material in the spaces between the patterned MRAM stacks and above the patterned MRAM stacks. In some embodiments, forming the gap-fill dielectric material in the spaces between the patterned MRAM stacks comprises selectively etching the gap-fill dielectric material to an etch depth above a depth of the tunnel barrier layer. In some embodiments, the gap-fill dielectric material comprises silicon nitride, silicon oxide, silicon oxycarbide, germanium oxide, magnesium oxide, germanium nitride, or a combination thereof. In some embodiments, the operations of etching through the plurality of MRAM layers, forming the gap-fill dielectric material, and performing the IBE trim etch are performed without introducing a vacuum break between the operations. In some embodiments, the ion beam etching through at least the tunnel barrier layer includes applying a first ion beam having an energy between about 200 eV and about 10,000 eV to the substrate, and performing the IBE trim etch includes applying a second ion beam having an energy between about 20 eV and about 400 eV to the substrate. In some embodiments, performing the IBE trim etch is performed without etching through an underlayer disposed below the plurality of MRAM layers.

[0006] Another aspect involves an apparatus for performing ion beam etching. The apparatus includes an ion beam source chamber, a process chamber coupled to the ion beam source chamber, and a controller. The controller is configured to provide instructions to perform the following operations: disposing a substrate in the process chamber, disposing a plurality of MRAM layers on the substrate, the plurality of MRAM layers including one or more magnetic layers and a tunnel barrier layer, etching through the plurality of MRAM layers disposed on the substrate to form a patterned MRAM stack, the etching through the plurality of MRAM layers including an ion beam etch (IBE) through at least the tunnel barrier layer, forming a gap fill dielectric material in spaces between the patterned MRAM stacks, and performing an IBE trim etch to remove at least a portion of the gap fill dielectric material and the conductive material deposited on sidewalls of the patterned MRAM stack.

[0007] In some implementations, the controller configured to provide instructions to form the gap-fill dielectric material is further configured to provide instructions to perform the following operation: depositing the gap-fill dielectric material in spaces between and over the patterned MRAM stacks. In some implementations, the controller configured to provide instructions to form the gap-fill dielectric material is further configured to provide instructions to perform the following operation: selectively etching the gap-fill dielectric material to an etch depth above a depth of the tunnel barrier layer. In some implementations, the gap-fill dielectric material is formed to a sufficient depth over an underlying layer disposed between the substrate and the plurality of MRAM layers such that performing an IBE trim etch does not recess the underlying layer. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a cross-sectional schematic diagram of an exemplary MRAM stack on a substrate according to some embodiments.

[0009] [Diagram 2] FIG. 2 is a cross-sectional schematic diagram of MRAM layers undergoing ion beam etching (IBE) and sidewall redeposition.

[0010] [Diagram 3] FIG. 3 is a schematic diagram of an exemplary ion beam etching apparatus according to some embodiments.

[0011] [Figure 4A] FIG. 4A is a cross-sectional schematic diagram of ion beam etching through multiple MRAM layers and underlying layers. [Figure 4B] FIG. 4B is a cross-sectional schematic diagram of ion beam etching through multiple MRAM layers and underlying layers.

[0012] [Diagram 5] FIG. 5 is a flow diagram of an exemplary method of ion beam etching according to some embodiments.

[0013] [Figure 6A] FIG. 6A is a cross-sectional schematic diagram of a process for performing a main etch operation according to some embodiments. [Figure 6B] FIG. 6B is a cross-sectional schematic diagram of a process for performing a gap-fill operation according to some embodiments. [Figure 6C] FIG. 6C is a cross-sectional schematic diagram of a process for performing a planarization operation according to some embodiments. [Figure 6D] FIG. 6D is a cross-sectional schematic diagram of a process for performing an etch-back operation according to some embodiments. [Figure 6E] FIG. 6E is a cross-sectional schematic diagram of a process for performing an IBE trim etch operation in accordance with some embodiments. [Figure 6F] FIG. 6F is a cross-sectional schematic diagram of a process for performing an encapsulation operation according to some embodiments.

[0014] [Figure 7] FIG. 7 is a block diagram of an exemplary processing system for performing deposition and ion beam etching processes, according to some embodiments.

[0015] [Figure 8] FIG. 8 is an alternative block diagram of an exemplary processing system for performing deposition and ion beam etching processes, according to some embodiments.

[0016] [Figure 9] FIG. 9 is a block diagram of an exemplary processing system for performing planarization and / or etching processes according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] In this disclosure, the terms "semiconductor wafer," "wafer," "substrate," "wafer substrate," and "partially fabricated integrated circuit" are used interchangeably. Those skilled in the art will understand that the term "partially fabricated integrated circuit" can refer to a silicon wafer at any of the many stages of fabricating an integrated circuit. Wafers or substrates used in the semiconductor device industry typically have diameters of 200 mm, or 300 mm, or 450 mm. The following detailed description assumes that the disclosure is practiced on a wafer. However, the disclosure is not so limited. Workpieces can be of various shapes, sizes, and materials. In addition to semiconductor wafers, other workpieces that may utilize the disclosure include various products such as printed circuit boards.

[0018] Introduction Electronic devices use integrated circuits, including memory, to store data. One type of memory commonly used in electronic circuits is DRAM. DRAM stores each bit of data in a separate capacitor on the integrated circuit. The capacitor can be either charged or discharged, representing the two states of the bit. The charge on the capacitor slowly leaks away, so data is gradually lost unless the charge on the capacitor is periodically refreshed. DRAM is a type of volatile memory, as opposed to non-volatile memory, because data is lost when the power is removed.

[0019] Unlike traditional RAM chip technology, data in MRAM is stored by magnetic storage elements, not as a flow of electric charge or current. The magnetic storage elements may be formed from two ferromagnetic plates, each capable of retaining magnetization, separated by a thin non-magnetic insulating layer. One of the two ferromagnetic plates may be a permanent magnet set to a specific polarity, and the other of the two ferromagnetic plates may be changed to match that of an external magnetic field to store memory. Such a configuration with two ferromagnetic plates and a thin non-magnetic insulating layer is known as a magnetic tunnel junction. MRAM is a type of non-volatile memory, as it is capable of retaining stored data even when power is removed.

[0020] 1 is a cross-sectional schematic diagram of an exemplary MRAM stack on a substrate, according to some embodiments. The MRAM stack 100 includes a dielectric layer 110, e.g., SiO 2The MRAM stack 100 may be arranged on top of the dielectric layer 110, which is deposited on a silicon or glass substrate (not shown). In the case of embedded MRAM, there are various structures (not shown) including the transistor level of logic circuits, as well as three to five metallization layers between the substrate and the MRAM stack 100, since the embedded MRAM may be MRAM embedded in non-memory circuits such as metallization layers. All of these structures are covered by or inserted within the dielectric layer 110. The MRAM stack 100 may include a top electrode layer 120 and a bottom electrode layer 130. The bottom electrode layer 130 is arranged on top of the dielectric layer 110 and may include a single layer metal, or a multi-layer stack including multiple metal layers and other material layers (e.g., dielectric materials). The top electrode layer 120 is arranged on top of the bottom electrode layer 130 and may include a single layer metal, or a multi-layer stack including multiple metal layers and other material layers (e.g., dielectric materials). The MRAM stack 100 may be arranged in an array of MRAM cells connected by metal word and bit lines. In some implementations, the bottom electrode layer 130 is connected to a word line and the top electrode layer 120 is connected to a bit line.

[0021] The MRAM stack 100 can include a memory element or magnetoresistance effect element, which can be disposed between the top electrode layer 120 and the bottom electrode layer 130. The memory element or magnetoresistance effect element can be a multilayer or magnetic tunnel junction (MTJ) stack 140. The MTJ stack 140 can include magnetic layers 150, 160 with a barrier layer 170 between the magnetic layers 150, 160. Furthermore, the MTJ stack 140 can include multiple MTJ stacks and multiple barrier layers, each barrier layer disposed between a pair of magnetic layers. It will be understood that the MTJ stack 140 is illustrative and not limiting and can include many other layers not shown in FIG. 1. The first magnetic layer 150 is designed to function as a free magnetic layer, and the second magnetic layer 160 has a fixed magnetization direction. In some implementations, the first magnetic layer 150 and the second magnetic layer 160 each include a magnetic material such as cobalt (Co), nickel (Ni), iron (Fe), or a combination thereof (e.g., CoNi, CoFe, NiFe, CoNiFe). The first magnetic layer 150 and the second magnetic layer 160 each may further include a non-magnetic material such as boron (B), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), aluminum (Al), silicon (Si), germanium (Ge), gallium (Ga), oxygen (O), nitrogen (N), carbon (C), platinum (Pt), palladium (Pd), ruthenium (Ru), or phosphorus (P) to form a magnetic compound (e.g., CoFeB). It should be understood that each of the first magnetic layer 150 and the second magnetic layer 160 may include one or more sublayers. In some implementations, the second magnetic layer 160 may be coupled to and disposed above an antiferromagnetic layer (not shown). The MTJ stack 140 further includes a tunnel barrier layer or barrier layer 170 between the first magnetic layer 150 and the second magnetic layer 160, and the barrier layer 170 may include a non-magnetic insulating material such as magnesium oxide (MgO).Thus, the MTJ stack 140 can include a pair of ferromagnetic layers (i.e., the first magnetic layer 150 and the second magnetic layer 160) sandwiching a non-magnetic intermediate layer (i.e., the barrier layer 170) that collectively produce a magnetoresistance effect. The resistivity of the MTJ stack 140 changes when the magnetization of the first magnetic layer 150 changes direction relative to the magnetization of the second magnetic layer 160, exhibiting a low resistance state when the magnetization orientations of the pair of ferromagnetic layers are substantially parallel and a high resistance state when the magnetization orientations of the pair of ferromagnetic layers are substantially anti-parallel. Thus, the MRAM stack 100 can have two stable states, enabling the MRAM stack 100 to function as a non-volatile memory.

[0022] In some implementations, the top electrode layer 120 can function as a hard mask layer. During processing, the top electrode layer 120 can be deposited on the first magnetic layer 150 and the underlying MTJ stack 140 can be patterned. However, it should be understood that the positions of the first magnetic layer 150 and the second magnetic layer 160 can be reversed and the top electrode layer 120 can be deposited on the second magnetic layer 160. In some implementations, the top electrode layer 120 comprises tungsten (W), tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), or other refractory metals. The MTJ stack 140 can be formed on the bottom electrode layer 130, which comprises a conductive material such as Ta, Ti, W, TiN, TaN, Pt, Ru, etc.

[0023] It should be understood that MRAM stack 100 may include several other layers not necessarily shown in Figure 1. The layers in MRAM stack 100 are not necessarily limited to metal or conductive materials, but may also include one or more layers of dielectric material.

[0024] Etching materials in MRAM stacks, including the MRAM stack 100 of FIG. 1, can present many challenges. Hard materials are typically etched with chemical etching processes such as reactive ion etching (RIE). However, reactive ion etching of materials such as cobalt, iron, nickel, and other magnetic elements is difficult because these materials do not readily become volatile when exposed to typical etchant chemistries. Thus, many materials in the MRAM stack require more aggressive etchant chemistries. On the other hand, certain materials in the MRAM stack cannot tolerate such aggressive etchant chemistries. For example, a tunnel barrier layer such as MgO cannot tolerate reactive chemistries, which may include radicals, ions, and neutral species containing fluorine, chlorine, iodine, oxygen, or hydrogen. These chemicals can cause reactions with the tunnel barrier layer, thereby damaging it and adversely affecting the electrical and magnetic properties of the MRAM stack. In some cases, the tunnel magnetoresistance (TMR) effect in the MRAM stack is impaired.

[0025] Ion beam etching (IBE) is widely used in various industries to pattern thin films. Ion beam etching, which may also be called ion milling, provides a highly directional beam of charged particles to etch features on a substrate. Ion beam etching can be applied using inert gases for a purely physical etching process, but in some cases, ion beam etching can be applied using reactive species to augment material etching with chemical / reactive components. Generally speaking, ion beam etching can physically etch through hard materials by using individual particles to ablate the exposed target to remove atoms and molecules. Using ion beam etching, it is possible to etch materials in MRAM stacks while avoiding reactive chemicals that can degrade sensitive layers such as the tunnel barrier layer.

[0026] Features in the MRAM stack can be patterned with ion beam etching. Ion beam etching can generally be chemically reactive and physically etches layers and materials exposed by the hard mask. This causes atoms and molecules to be sputtered from the target. The sputtered atoms and molecules can be directed to and redeposited on the exposed sidewalls of the MRAM stack. Thus, etching and redeposition can occur simultaneously. The redeposited material can be cleaned from the sidewalls of the MRAM stack by performing the ion beam etching at a lower energy and a different impact angle than the ion beam etching to pattern the MRAM stack.

[0027] FIG. 2 is a cross-sectional schematic diagram of an MRAM layer undergoing ion beam etching and sidewall redeposition. MRAM stacks 220a, 220b are formed on a substrate 210. Each of the MRAM stacks 220a, 220b may include a pair of magnetic layers, and a tunnel barrier layer (e.g., MgO) may be sandwiched between the magnetic layers. It should be understood that in some implementations, each of the MRAM stacks 220a, 220b may include multiple tunnel barrier layers, each sandwiched between a pair of magnetic layers. Examples of layers and materials in the MRAM stacks 220a, 220b are described above with respect to the MRAM stack 100 of FIG. 1. Conventional MRAM patterning processes include hard mask patterning, top electrode patterning, MTJ patterning, and bottom electrode patterning. It should be understood that ion beam etching may be used in some or all of the aforementioned patterning processes, and ion beam etching may be used in MTJ patterning. Reactive ion etching or ion beam etching may be used for top electrode patterning and bottom electrode patterning. To pattern the MRAM stacks 220a, 220b, an ion beam 225 can be applied to the substrate 210 to physically etch the layers and materials exposed by the hard mask. The ion beam 225 sputters atoms and molecules from the surface exposed to the ion beam 225. As shown in FIG. 2, the sputtered atoms and molecules 275 can be directed to and redeposited on the sidewalls of the MRAM stacks 220a, 220b. Some layers on the substrate 210, such as layers of the MTJ stacks, can include metal atoms, such as Fe, Co, and Ni atoms. As the ion beam etch progresses through the MTJ stacks, such metal atoms can be removed and redeposited on the sidewalls of the MRAM stacks 220a, 220b. When a conductive material is redeposited on the sidewalls of the tunnel barrier layers, which can be only a few nanometers thick, the magnetic layers are shorted in the MRAM stacks 220a, 220b.

[0028] The ion beam 225 applied to the substrate 210 can be oriented at an angle. The incidence angle of the ion beam 225 can be adjusted to control parameters such as the etch rate, uniformity, shape, topography, and composition of the target surface. In some cases, the incidence angle of the ion beam 225 is adjusted to clean the sidewalls of redeposited material. A lower incidence angle (i.e., more vertical) of the ion beam 225 can result in more redeposition of material, while an optimized higher incidence angle (i.e., less vertical) of the ion beam 225 can result in a cleaner sidewall surface by removing the redeposited material. Furthermore, as device density increases and aspect ratios increase, the feasibility of using higher incidence angles for cleaning sidewall surfaces becomes even more limited.

[0029] Ion Beam Etching Equipment FIG. 3 is a schematic diagram of an exemplary ion beam etching apparatus according to some embodiments. The ion beam etching apparatus 310 includes a process chamber 312 with a substrate holder 314 for supporting a substrate 316. The substrate 316 can be a semiconductor wafer. A plurality of MRAM layers, as described above, can be formed on the substrate 316. The plurality of MRAM layers can include one or more magnetic layers and a single tunnel barrier layer or multiple tunnel barrier layers. The plurality of MRAM layers can further include a top electrode layer and a bottom electrode layer. The substrate 316 can be attached to the substrate holder 314 using any suitable technique. For example, the substrate 316 is mechanically or electrostatically connected to the substrate holder 314. In some embodiments, the substrate holder 314 can include an electrostatic chuck (ESC) for providing precise tilt and rotation and engaging the substrate 316.

[0030] The ion beam etching apparatus 310 further includes an ion beam source chamber 322, and the processing chamber 312 may be outside and coupled to the ion beam source chamber 322. The ion beam source chamber 322 may be separated from the processing chamber 312 by an ion extractor 340 and / or a mechanical shutter 348. An inductive coil 332 may be disposed around an outer wall of the ion beam source chamber 322. A plasma generator 334 supplies RF power to the inductive coil 332. The plasma generator 334 may include an RF source 336 and a matching network 338. In use, a gas mixture is introduced into the ion beam source chamber 322, and RF power is supplied to the inductive coil 332 to generate a plasma in the ion beam source chamber 322, which generates ions.

[0031] The ion beam etching apparatus 310 further includes a gas delivery system 350 fluidly coupled to the ion beam source chamber 322. The gas delivery system 350 delivers one or more gas mixtures to the ion beam source chamber 322. The gas delivery system 350 may include one or more gas sources 352 in fluid communication with the ion beam source chamber 322, a valve 354, a mass flow controller (MFC) 356, and a mixing manifold 358. In some implementations, the gas delivery system 350 is configured to deliver an inert gas, such as helium (He), neon (Ne), argon (Ar), xenon (Xe), or krypton (Kr). In some implementations, the gas delivery system 350 delivers a gas mixture further including a reactive chemical along with the inert gas.

[0032] The ion extractor 340 extracts positive ions from the plasma and accelerates the positive ions in a beam towards the substrate 316. The ion extractor 340 may include multiple electrodes forming a grid or grid system. As shown in FIG. 3, the ion extractor 340 includes three electrodes, a first electrode 342, a second electrode 344, and a third electrode 346, in that order, from a gas delivery system 350. A positive voltage is applied to the first electrode 342 and a negative voltage is applied to the second electrode 344, so that the ions are accelerated by the difference in their potentials. The third electrode 346 is grounded. Controlling the potential difference between the second electrode 344 and the third electrode 346 controls the energy and divergence of the ion beam. A mechanical shutter 348 may be adjacent to the ion extractor 340. A neutralizer 360 can provide electrons to the process chamber 312 to neutralize the charge of the ion beam passing through the ion extractor 340 and mechanical shutter 348, and can have its own gas delivery system using an inert gas such as argon or xenon. In some implementations, the ion extractor 340 and / or the mechanical shutter 348 can be controlled so that the ion beam is delivered to the substrate 316 continuously or in pulses.

[0033] A position controller 366 can be used to control the position of the substrate holder 314. In particular, the position controller 366 can control the tilt angle about the tilt axis and the rotation of the substrate holder 314 to position the substrate 316. In some implementations, an endpoint detector 368 can be used to sense the location of the ion beam relative to the substrate 316 and / or the substrate holder 314. A pump 370, such as a turbomolecular pump, can be used to control the pressure in the process chamber 312 and to evacuate reactants from the process chamber 312.

[0034] The ion beam etching apparatus 310 may further include a controller 390. The controller 390, which may include one or more physical or logical controls, controls some or all of the operations of the ion beam etching apparatus 310. In some implementations, the controller 390 may be used to control the plasma generator 334, the gas delivery system 350, the neutralizer 360, the position control 366, and the pump 370. The controller 390 may include one or more memory devices and one or more processors. The processor may include a central processing unit (CPU) or computer, analog and / or digital input / output connections, stepper motor controller boards, and other similar components. Instructions for implementing appropriate control operations are executed on the processor. These instructions may be stored in a memory device associated with the controller 390 and may be provided over a network. In certain implementations, the controller 390 executes system control software. The system control software may include instructions for controlling the timing and / or magnitude of application of any one or more of the following chamber operating conditions: mixture and / or composition of gases, flow rate of gases, chamber pressure, chamber temperature, substrate / substrate holder temperature, substrate position, substrate holder tilt, substrate holder rotation, voltage applied to the grid, frequency and power applied to coils or other plasma generating components, and other parameters of the particular process being performed by the tool. The system control software may further control purging and cleaning operations through pump 370. The system control software may be configured in any suitable manner. For example, various process tool component subroutines or control objects may be written to control the operation of process tool components necessary to perform various process tool processes. The system control software may be coded in any suitable computer readable programming language.

[0035] In some implementations, the system control software includes input / output control (IOC) sequence instructions for controlling the various parameters described above. For example, each stage of a semiconductor fabrication process may include one or more instructions for execution by the controller 390. Instructions for setting process conditions for a stage may be included in a corresponding recipe stage, for example. In some implementations, recipe stages may be sequenced such that the steps of an ion beam etching process are performed in a particular order for that process stage. For example, a recipe may be configured to perform a separation etch using an ion beam etch at a high energy and a trim etch using an ion beam etch at a low energy.

[0036] Other computer software and / or programs may be used in some embodiments. Examples of programs or sections of programs for this purpose include a substrate positioning program, a process gas composition control program, a pressure control program, a heater control program, and an RF power supply control program.

[0037] The controller 390 can control these and other aspects based on sensor outputs (e.g., when power, potential, pressure, gas levels, etc. reach certain thresholds), timing of actions (e.g., when to open a valve at a particular time in the process), or based on instructions received from a user.

[0038] Broadly, the controller 390 may be defined as electronic equipment having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, etc. The integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors, i.e., microcontrollers, that execute the program instructions (e.g., software). The program instructions may be instructions communicated to the controller 390 in the form of various individual settings (or program files) that define operational parameters for performing a particular process on or for a semiconductor substrate or for a system. The operational parameters may, in some implementations, be part of a recipe defined by a process engineer to accomplish one or more processing steps in the patterning of MRAM stacks on a substrate.

[0039] The controller 390 may in some embodiments be part of, coupled to, or a combination of a computer that is integrated or coupled with the system or otherwise networked to the system. For example, the controller 390 may be in the "cloud" or may be all or part of a fab host computer system. This allows for remote access of substrate processing. The computer may allow remote access to the system to monitor the current progress of a fabrication operation, review the history of past fabrication operations, review trends or performance criteria from multiple fabrication operations, modify parameters of a current process, set processing steps following a current process, or start a new process. In some examples, a remote computer (e.g., a server) may provide a process recipe to the system over a network. Such a network may include a local network or the Internet. The remote computer may include a user interface that allows entry or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some examples, the controller 390 receives instructions in the form of data. Such data identifies parameters for each processing step performed during one or more operations. It should be understood that the parameters may be specific to the type of process being performed and the type of tool that the controller 390 is configured to interface with or control. Thus, as discussed above, the controller 390 may be distributed, for example, by having one or more individual controllers networked together and working together toward a common purpose (such as the processes and controls described herein). An example of a distributed controller 390 for such purposes would include one or more integrated circuits on the chamber in communication with one or more integrated circuits located remotely (e.g., at the platform level or as part of a remote computer) and coupled to control the process in the chamber.

[0040] As mentioned above, depending on the processing step or steps being performed by the tool, the controller 390 may communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used in material transport to and from tool locations and / or load ports within a semiconductor manufacturing factory. Examples of the foregoing are described in Figures 7-9 with which the controller 390 may communicate.

[0041] Ion beam etching with sidewall cleaning In the present disclosure, a dielectric gap fill material is deposited between an IBE isolation etch process for patterning the MRAM stack and an IBE trim etch process for cleaning the sidewalls of the patterned MRAM stack. Typically, the IBE trim etch process for cleaning the sidewalls of the patterned MRAM stack causes sputtering of metal or conductive material that can be redeposited on the sidewalls. If the etch front of the IBE trim etch process includes metal or conductive material, sputtering of the metal or conductive material can occur. One approach to avoid such sputtering is to use a silicon oxide (SiO) as the etch front. 2One approach is to provide a thick layer of dielectric material, such as a ferroelectric thin film (FE) or a ferroelectric thin film (FE) below the MRAM layer. The thick layer of dielectric material can be provided below the MRAM layer or below the magnetic layer in the MTJ stack. The thick layer of dielectric material can be at least about 40 nm thick, at least about 50 nm thick, at least about 75 nm thick, or at least about 100 nm thick. In this way, the material that redeposits on the sidewalls during ion beam etching is a dielectric material rather than a conductive material. However, providing a thick layer of dielectric material below the magnetic layer of the MTJ stack is impractical and can increase operational overhead, complicate the manufacturing process, increase costs, and even reduce performance. For example, many MRAM devices are embedded memories that reside between metallization layers of an integrated circuit (IC), and the thickness of the dielectric layer in which the MRAM device resides cannot be easily altered.

[0042] 4A and 4B show cross-sectional schematics of ion beam etching through multiple MRAM layers and underlayers. The MRAM stack 400 may include a first magnetic layer 450, a tunnel barrier layer 470, and a second magnetic layer 460, with the tunnel barrier layer 470 being between the first magnetic layer 450 and the second magnetic layer 460. The first magnetic layer 450 may be called a free layer and is designed to function as a free magnetic layer, and the second magnetic layer 460 may be called a reference layer and is designed to have a fixed magnetization direction. In some implementations, the first magnetic layer 450 and the second magnetic layer 460 may include a magnetic material such as Co, Ni, Fe, Pt, or a combination thereof. The tunnel barrier layer 470 may include a non-magnetic insulating material such as MgO. The combination of the first magnetic layer 450, the tunnel barrier layer 470, and the second magnetic layer 460 generates a magnetoresistance effect. The MRAM stack 400 is disposed on a substrate 410 with an underlayer 430 between the substrate 410 and the MRAM stack 400. The underlayer 430 is a silicon oxide (SiO 2) may include one or more layers of a dielectric material such as a hard mask layer (not shown). In some implementations, a hard mask layer or electrode layer (not shown) may be disposed above the MRAM stack 400. In some implementations, the electrode layer (not shown) may be disposed between the underlayer 430 and the substrate 410. In some implementations, the MRAM stack 400 may include multiple tunnel barrier layers, each sandwiched between a first magnetic layer and a second magnetic layer.

[0043] Ion beam etching through the layers of the MRAM stack 400 can be performed to form a patterned MRAM stack, which can include lines, pillars, or other patterned features. The ion beam etching to form the patterned MRAM stack can be performed at high power and a relatively low angle of incidence. In addition, ion beam etching can be performed to clean the sidewalls of the patterned MRAM stack to remove unwanted material redeposited on the sidewalls after forming the patterned MRAM stack. The ion beam etching to clean the sidewalls of the patterned MRAM stack can be performed at lower power and a relatively high angle of incidence from the normal of the substrate surface.

[0044] In FIG. 4A, the ion beam 425 can be directed at an angle to clean the sidewalls of the patterned MRAM stack. For example, the substrate 410 can be tilted or rotated to adjust the ion impact angle of the ion beam 425. The ion beam 425 impacts the sidewalls of the patterned MRAM stack and removes unwanted material. The ion beam 425 also impacts the bottom surface of the MRAM stack 400 and sputters atoms and molecules on the bottom surface. The sputtered atoms and molecules 475 can be directed at the sidewalls of the patterned MRAM stack and are thus redeposited on the sidewalls of the patterned MRAM stack. When the etching front of the ion beam 425 has a conductive material (e.g., metal), at least a portion of the conductive material can be redeposited on the sidewalls of the patterned MRAM stack. In FIG. 4A, when the etch front of the ion beam 425 includes the second magnetic layer 460, magnetic elements having Co, Ni, Pt, or Fe may redeposit on the sidewalls of the patterned MRAM stack, which may degrade the electrical and magnetic performance of the MRAM stack 400.

[0045] Rather than having an etch front of a conductive material, the etch front may include a dielectric material. In FIG. 4B, an ion beam 425 strikes the bottom surface of the MRAM stack 400, directing sputtered atoms and molecules 475 toward the exposed surface of the patterned MRAM stack. The etch front of the ion beam 425 includes the underlayer 430, which is SiO 2A dielectric material such as a SiO 2 film can be redeposited on the sidewalls of the patterned MRAM stack. Sputtered atoms and molecules 475 from the dielectric material in the underlayer 430 are unlikely to degrade the electrical and magnetic performance of the MRAM stack 400. Thus, overetching can be performed through the underlayer 430 while providing harmless backsputtering to the patterned MRAM stack. The thickness of the underlayer 430 may be sufficient to act as an etch front for ion beam etching to adequately clean the sidewalls of the patterned MRAM stack. However, as discussed above, it may not be desirable to incorporate a sufficiently thick underlayer 430 between the substrate 410 and the MRAM stack 400, and having a particularly thick underlayer 430 may be impractical in various devices.

[0046] In the present disclosure, the underlayer having a dielectric material with a sufficient thickness to allow removal of the redeposited sidewall material before the dielectric material is etched away does not comprise the MRAM stack to act as an etch front during cleaning. In the present disclosure, an IBE main etch process is performed to form the patterned MRAM stacks, followed by depositing a gap-fill dielectric material in the spaces between the patterned MRAM stacks. The gap-fill dielectric material may be etched back or formed to a sufficient depth such that the deposited gap-fill dielectric material remains through all or most of the subsequent IBE trim etch cleaning steps. In some implementations, the thickness of the deposited gap-fill dielectric material extends above the depth of the tunnel barrier layer. Following the deposition of the gap-fill dielectric material, an IBE over etch or trim etch process is performed to clean the sidewalls of the patterned MRAM stacks, and the etch front during the IBE trim etch process includes the gap-fill dielectric material.

[0047] FIG. 5 illustrates a flow diagram of an exemplary method of ion beam etching according to some embodiments. The operations of process 500 of FIG. 5 may include additional, fewer, or different operations. In conjunction with the description of process 500 of FIG. 5, a series of cross-sectional schematic diagrams illustrating main etch, gap fill, planarization, etch back, IBE trim etch, and encapsulation operations are illustrated in FIG. 6A-6F. The operations of process 500 may be performed using an ion beam etcher, such as ion beam etcher 310 of FIG. 3.

[0048] At block 510 of process 500, a plurality of MRAM layers disposed on a substrate are etched through to form a patterned MRAM stack, the plurality of MRAM layers including one or more magnetic layers and a tunnel barrier layer. The etching through the plurality of MRAM layers includes ion beam etching (IBE) through at least the tunnel barrier layer. In some implementations, the etching through the plurality of MRAM layers includes ion beam etching through the plurality of MRAM layers. In some implementations, the etching through the plurality of MRAM layers includes reactive ion etching (RIE) through some of the plurality of MRAM layers and ion beam etching through at least the tunnel barrier layer. In some implementations, the plurality of MRAM layers includes two or more tunnel barrier layers, and the ion beam etching is performed through the two or more tunnel barrier layers. To pattern the MRAM stack, a hard mask can be formed on the plurality of MRAM layers. The hard mask can be made of, for example, W, Ti, Ta, TiN, or other refractory metals. The etch through the multiple MRAM layers in block 510 may also be referred to as the "main etch," "cut etch," "isolation etch," "first etch," or "IBE isolation etch."

[0049] The etching through the multiple MRAM layers may include etching through the MTJ stack including the first magnetic layer, the second magnetic layer, and a tunnel barrier layer between the first magnetic layer and the second magnetic layer. The first magnetic layer may be disposed above the tunnel barrier layer, and the second magnetic layer may be disposed below the tunnel barrier layer. The tunnel barrier layer may include a non-magnetic insulating material such as MgO. Each of the first magnetic layer and the second magnetic layer may include a magnetic element such as Co, Ni, Pt, Fe, or a combination thereof. In some implementations, the etching through the MTJ stack may include ion beam etching through the MTJ stack. The etching may stop at an underlayer or dielectric layer after etching through at least the second magnetic layer. The etching through the multiple MRAM layers may include ion beam etching through the first magnetic layer, the tunnel barrier layer, and the second magnetic layer without etching through the underlayer. Thus, the main etch or isolation etch can be performed up to the interface between the underlayer to be etched and the multiple MRAM layers, the underlayer being SiO 2 The main etch can be performed on the top surface of the underlayer, and the main etch can be stopped on the underlayer using optical emission spectroscopy or an endpoint detector.

[0050] When performing ion beam etching through at least some of the MRAM layers, an ion beam of an inert gas can be generated from an ion beam source chamber. The ion beam source chamber can be coupled to a process chamber in which the substrate is located. The ion beam can be generated in the ion beam source chamber using a gas mixture including an inert gas. The inert gas can include helium (He), neon (Ne), argon (Ar), xenon (Xe), krypton (Kr), or combinations thereof. In some implementations, the gas mixture can include one or more reactive gases to increase material etching by chemical / reactive components. In some implementations, the gas mixture is free or substantially free of reactive gases. RF power can be applied to a coil surrounding the ion beam source chamber to generate a plasma, and ions are extracted from the plasma to form an ion beam. A voltage is applied to an ion extractor (e.g., a grid) to extract the ions to form an ion beam, and the ion beam can be accelerated toward the process chamber. Control of the voltage applied to the ion extractor can be used to control the etch rate when performing ion beam etching. The high voltage ion beam may be about 400V to about 2000V to perform a "fast" etch with a high etch rate, and the low voltage ion beam may be about 30V to about 400V to perform a "soft" etch with a low etch rate. The ion beam etch (main etch or isolation etch) that penetrates at least some of the MRAM layers, including the tunnel barrier layers, to form the patterned MRAM stack may be performed at a relatively high voltage. Thus, the main etch used to etch through the MRAM layers to form the patterned MRAM stack may be performed at a high voltage of about 400V to about 2000V. On the other hand, the trim etch or over etch used to clean the sidewalls of the patterned MRAM stack may be performed at a low voltage of about 30V to about 400V.

[0051] In some implementations, etching through at least some of the multiple MRAM layers may include applying an ion beam to the substrate having an ion energy of about 200 eV to about 10,000 eV. The main etch may be performed at a higher ion energy to efficiently etch material in the MRAM layers as compared to the trim etch. In some implementations, the main etch or isolation etch may be performed in 10 minutes or less, 3 minutes or less, or 1 minute or less. In some implementations, the main etch may be performed in an ion beam etcher having an ion beam source chamber coupled to the process chamber. An exemplary ion beam etcher is described in FIG. 3 above.

[0052] In some implementations, some of the MRAM layers may be etched using reactive ion etching. Specifically, reactive ion etching may be applied to layers other than the tunnel barrier layer, since reactive species from the reactive ion etching may damage the tunnel barrier layer. The reactive ion etching may be followed by ion beam etching to etch through the tunnel barrier layer. In some implementations, the reactive ion etching may be applied to a hard mask layer or an electrode layer disposed above the tunnel barrier layer. In some implementations, the reactive ion etching may be applied to a first magnetic layer disposed above the tunnel barrier layer. In some implementations, the reactive ion etching may be applied to a second magnetic layer disposed below the tunnel barrier layer. In some implementations, the reactive ion etching may be applied to an electrode layer disposed below the second magnetic layer. Nonetheless, any of the aforementioned MRAM layers may be etched using ion beam etching rather than reactive ion etching. Thus, the sequence of main etches in etching through multiple MRAM layers may include RIE followed by IBE, RIE followed by IBE and IBE followed by RIE, IBE followed by RIE, or IBE throughout.

[0053] The main etch may redeposit conductive material on the sidewalls of the patterned MRAM stack. The redeposited conductive material may come from one or more magnetic layers in the multiple MRAM layers. Typically, when etching one or more magnetic layers of the multiple MRAM layers, etch by-products are generated that may redeposit on the exposed surfaces. The etch by-products may include atoms or molecules of metal or conductive material. These etch by-products are sputtered when the ion beam is applied to the multiple MRAM layers. The one or more magnetic layers may include a non-volatile material, which may include magnetic materials such as Co, Ni, Pt, Fe, etc. If such etch by-products redeposit on the sidewall surfaces of the tunnel barrier layer, the MTJ stack may be compromised, leading to short circuits.

[0054] Etching through the multiple MRAM layers forms patterned MRAM stacks, where the patterned MRAM stacks are lines, pillars, or other patterned features. The main etch forms spaces between the patterned MRAM stacks. In some implementations, the patterned MRAM stacks are pillars with high aspect ratios, where the aspect ratio of the height to width of the patterned MRAM stacks is at least 5:1, at least 7:1, at least 10:1, or at least 20:1. In some implementations, the pitch between adjacent MRAM stacks can be about 300 nm or less, about 10 nm to about 300 nm, or about 30 nm to about 250 nm.

[0055] In some implementations, prior to block 510 of process 500, a substrate may be placed in a processing chamber of an ion beam etcher. Multiple MRAM layers may be disposed on the substrate, the multiple MRAM layers including one or more magnetic layers and a tunnel barrier layer.

[0056] FIG. 6A shows a cross-sectional schematic diagram of an exemplary main etch according to some embodiments. The MRAM layers 650, 660, and 670 are disposed on the substrate 610, and the underlayer 630 is disposed between the MRAM layers 650, 660, and 670 and the substrate 610. The MRAM layers 650, 660, and 670 and the underlayer 630 are described in FIGS. 1 and 2. The MRAM layers 650, 660, and 670 include at least a first magnetic layer 650, a second magnetic layer 660, and a tunnel barrier layer 670 between the first magnetic layer 650 and the second magnetic layer 660. As described above, the MRAM layers 650, 660, and 670 may each include a tunnel barrier layer sandwiched between the first magnetic layer and the second magnetic layer. A main etch is performed to form the patterned MRAM stacks 620a, 620b. The main etch can stop on the top surface of the underlayer 630. In some implementations, the main etch or separation etch is performed through at least the tunnel barrier layer 670 in forming the patterned MRAM stack 620a, 620b. The ion beam of the main etch or separation etch can be provided at a relatively high ion energy and at a relatively low angle of incidence to the normal of the substrate surface. Residue 605, including metal or conductive material, is formed on the sidewalls of the patterned MRAM stack 620a, 620b as a result of the main etch. Sputtered atoms and / or molecules from the ion beam etching of the multiple MRAM layers 650, 660, and 670 can cause the accumulation of the residue 605. The residue 605 can form on the tunnel barrier layer 670 and degrade the performance of the tunnel barrier layer 670.

[0057] Returning to FIG. 5, in block 520 of process 500, a gap-fill dielectric material is formed in the spaces between the patterned MRAM stacks. In some implementations, the gap-fill dielectric material may be formed along the sidewalls and on the bottom surface of the patterned MRAM stacks. In some implementations, the gap-fill dielectric material may be deposited using chemical vapor deposition (CVD), physical vapor deposition (PVD), or plasma-enhanced chemical vapor deposition (PECVD). However, it should be understood that the gap-fill dielectric material may be deposited using any other suitable deposition technique, such as atomic layer deposition (ALD). For example, the gap-fill dielectric material may be deposited in the spaces between the patterned MRAM stacks using a deposition technique to achieve bottom-up filling.

[0058] In some implementations, the gap-fill dielectric material includes any suitable dielectric material, such as silicon nitride, silicon oxide, silicon oxycarbide, germanium oxide, germanium nitride, magnesium oxide, or combinations thereof. For example, the gap-fill dielectric material includes one or both of silicon nitride and silicon oxide. The gap-fill dielectric material may include a layer of silicon nitride and a layer of silicon oxide, or may include only a layer of silicon nitride. In some implementations, it is desirable to avoid silicon oxide directly contacting the patterned MRAM stack. The aforementioned dielectric material may fill the space between the patterned MRAM stacks, or at least fill the space above the underlying layer. Forming the gap-fill dielectric material in the space between the patterned MRAM stacks may be referred to as a "gap fill" or "dielectric gap fill" process.

[0059] In some implementations, the gap fill may be performed in a deposition chamber, such as a CVD, PVD, or PECVD chamber. The gap fill may be performed after the main etch and before the IBE trim etch. In some implementations, the main etch and gap fill may be performed by an integrated tool or a multi-station processing tool. The main etch at block 510 and the gap fill at block 520 operations may be performed without introducing a vacuum break between the operations.

[0060] In some implementations, forming a gap-fill dielectric material in the spaces between the patterned MRAM stacks includes depositing a gap-fill dielectric material in the spaces between the patterned MRAM stacks and over the patterned MRAM stacks, and selectively etching the gap-fill dielectric material to a sufficient depth above the underlayer. In some implementations, the sufficient depth above the underlayer may correspond to a sufficient thickness such that at least a portion of the gap-fill dielectric material remains after a subsequent trim etch at block 530. The gap-fill dielectric material may be deposited first over the patterned MRAM stacks to form an overburden. The gap-fill deposition process is typically somewhat conformal, with material being deposited along the sidewalls, bottom, and top surfaces of the patterned MRAM stacks. Because deposition rates may vary between the top surface of the patterned MRAM stacks and the bottom surface of the patterned MRAM stacks, the gap-fill deposition process may result in some "bread-loafing." This typically leads to non-uniform topography from the gap-fill. Thus, an overburden of gap-fill dielectric material may be deposited when filling the spaces between the patterned MRAM stacks, and the overburden of gap-fill dielectric material may be non-uniform in thickness across the top surface of the gap-fill dielectric material, in other words, some portions of the gap-fill dielectric material are thicker than other portions.

[0061] After depositing the overburden of gap-fill dielectric material on the patterned MRAM stack, the overburden can be removed. In some implementations, the process 500 further includes planarizing the gap-fill dielectric material deposited on the patterned MRAM stack. For example, the overburden can be removed using chemical mechanical polishing (CMP) or etching.

[0062] In addition to or instead of planarizing the overburden, the deposited gap-fill dielectric material may be selectively etched using dry or wet etching techniques, where the gap-fill dielectric material is selectively etched to a depth above the underlayer. In some implementations, the depth may be between the top surface of the tunnel barrier layer and the top surface of the first magnetic layer, between the bottom surface of the tunnel barrier layer and the bottom surface of the second magnetic layer, or between the bottom surface of the second magnetic layer and the top surface of the underlayer. In cases where the multiple MRAM layers include multiple tunnel barrier layers with multiple first / second magnetic layers, the depth may be measured relative to the lowest tunnel barrier layer and the lowest first / second magnetic layer. In some implementations, the selective etch is a plasma etch that selectively removes the gap-fill dielectric material without removing or substantially removing the hard mask or MRAM layers. The etch may have an etch selectivity of greater than about 10:1 between the gap-fill dielectric material and the hard mask or MRAM layers, meaning that the gap-fill dielectric material is etched at an etch rate greater than 10 times that of the hard mask or MRAM layers. For example, the gap-fill dielectric material can be etched using fluorine plasma in a reactive ion etching (RIE) or chemical downstream etching (CDE) chamber. If the dielectric material is silicon oxide, it can also be removed with hydrogen fluoride (HF) vapor. The sufficient depth above the underlayer can be between about 1 nm and about 20 nm from the depth of the underlayer, between about 2 nm and about 15 nm from the depth of the underlayer, or between about 3 nm and about 10 nm from the depth of the underlayer. In some embodiments, the selective etching can proceed to remove the gap-fill dielectric material without exposing the underlayer. In some embodiments, the selective etching can proceed to remove the gap-fill dielectric material without significantly etching through the underlayer. As used herein, "significantly etching" through the underlayer can constitute etching through at least 3 nm or at least 5 nm of the underlayer. In some embodiments, the sufficient depth above the underlayer can be above the tunnel barrier layer.As mentioned above, exposure of the tunnel barrier layer to reactive chemicals can damage the tunnel barrier layer. The selective etch leaves the remaining gap-fill dielectric material to act as an etch front during the IBE trim etch to clean the sidewalls of the patterned MRAM stack. In some implementations, the selective etch can be stopped at an etch depth just above the depth of the tunnel barrier layer or at a sufficient depth above the underlying layer using a suitable endpoint detection technique, such as optical emission spectroscopy (OES) or interferometric endpoint detection (IEP). The selective etch is sometimes referred to as an "etch-back" or "isotropic etch-back" process.

[0063] FIG. 6B illustrates a cross-sectional schematic of an exemplary gap-fill process following the main etch of FIG. 6A, according to some embodiments. After the main etch, a gap-fill dielectric material 680 is deposited in the spaces between the patterned MRAM stacks 620a, 620b using a suitable deposition technique, such as CVD, PVD, or PECVD. In some embodiments, the gap-fill dielectric material 680 is conformally deposited along the exposed surfaces (e.g., sidewalls) of the patterned MRAM stacks 620a, 620b to perform gap-fill. Thus, the recesses, gaps, trenches, openings, or spaces are filled by the gap-fill dielectric material 680. An overburden of the gap-fill dielectric material 680 is deposited on top of the patterned MRAM stacks 620a, 620b. In some embodiments, the gap-fill dielectric material 680 includes silicon nitride, or a combination of silicon nitride and silicon oxide.

[0064] 6C shows a cross-sectional schematic diagram of an exemplary planarization process following the gap-fill process of FIG. 6B, according to some embodiments. After the overburden of gap-fill dielectric material 680 is deposited, the top surface of the overburden may be non-uniform. For example, a non-uniform topography may result in more dielectric gap-fill material 680 in the magnetic field region compared to the gap-fill region, which may lead to bread-loafing. A planarization process, such as CMP or etching, may be performed to smooth the topography and remove the overburden.

[0065] FIG. 6D shows a cross-sectional schematic diagram of an exemplary etch-back process following the planarization process of FIG. 6C according to some embodiments. After the planarization process or the gap-fill process, an etch-back process is performed to remove the gap-fill dielectric material 680 selectively to the multiple MRAM layers 650, 660, and 670, or at least to the first magnetic layer 650. In some embodiments, the etch-back process removes the gap-fill dielectric material 680 selectively to the hard mask layer. The etch-back process can be a dry etch or a wet etch. The dry etch can be a plasma etch. The etch-back process can be performed to remove the gap-fill dielectric material 680 to an etch depth above the underlayer 630. In some embodiments, the etch-back process can be performed to remove the gap-fill dielectric material 680 to an etch depth slightly above the depth of the tunnel barrier layer 670. In particular, the etch-back process can be performed to an etch depth slightly above the interface between the tunnel barrier layer 670 and the first magnetic layer 650. For example, the remaining gap-fill dielectric material 680 may be at an etch depth of a few nanometers above the top surface of the tunnel barrier layer 670. In this manner, the tunnel barrier layer 670 is not exposed to an etch-back process. However, it will be understood that some embodiments involving a conformal deposition process may not require this etch-back or planarization process.

[0066] Returning to FIG. 5, in block 530 of process 500, an ion beam etch is performed to remove at least a portion of the gap fill dielectric material and conductive material deposited on the sidewalls of the patterned MRAM stack. The ion beam etch after forming the gap fill dielectric material over the underlayer serves to clean the sidewalls of the patterned MRAM stack. The ion beam etch to clean the sidewalls of the patterned MRAM stack can remove the gap fill dielectric material to an etch depth below the depth of the tunnel barrier layer. In some implementations, the etch depth below the depth of the tunnel barrier layer does not reach the depth of the underlayer. The ion beam etch to clean the sidewalls of the patterned MRAM stack may also be referred to as an "over etch," "trim etch," "IBE trim etch," "sidewall clean etch," or "low power trim etch."

[0067] The material deposited on the sidewalls of the patterned MRAM stack may include a metal or a conductive material. The metal or conductive material may be sputtered and redeposited on the sidewalls of the patterned MRAM stack when performing the main etch in block 510. In other words, after the main etch, materials that may be backsputtered and damaged may be located on the sidewalls of the patterned MRAM stack. In some implementations, some metals may include W, Ta, Ti, or TiN from the hard mask layer or the electrode layer, and some metals may include Co, Ni, Pt, or Fe from the first or second magnetic layer. The metal or conductive material may form unwanted residues on the sidewalls of the patterned MRAM stack and degrade the electrical and magnetic properties of the MTJ stack. An ion beam etch is performed in block 530, and the ion beam etch is performed at a low power and an optimized incidence angle to remove the unwanted residues.

[0068] For ion beam etching to remove redeposited material on the sidewalls of the patterned MRAM stack, a gas mixture including an inert gas can be used to generate the ion beam from the ion beam source chamber. In some implementations, the gas mixture can include one or more reactive gases to increase material etching by chemical / reactive components. In some implementations, the gas mixture is free of or substantially free of reactive gases. The ion beam etching to remove redeposited material on the sidewalls of the patterned MRAM stack can be performed at a relatively low voltage. In some implementations, the etching to remove redeposited material on the sidewalls of the patterned MRAM stack can include applying an ion beam having an energy of about 20 eV to about 400 eV to the substrate. The IBE trim etch can be performed at a low ion energy to remove unwanted residues compared to the main etch. In some implementations, the IBE trim etch can be performed for about 1 minute or more, 3 minutes or more, 5 minutes or more, or 10 minutes or more. In some implementations, the IBE trim etch can be performed alternating between first and second directions with or without substrate rotation. Low ion energies are desirable for trimming to reduce the effects of ion-induced intermixing of the MTJ layer.

[0069] In some implementations, the IBE trim etch may be performed in an ion beam etcher, such as the ion beam etcher described in FIG. 3. The IBE trim etch may be performed following gap fill, following planarization, or following etch back. In some implementations, the IBE trim etch and gap fill may be performed by an integrated tool or a multi-station processing tool. The operations of gap fill at block 520 and IBE trim etch at block 530 may be performed without introducing a vacuum break between the operations. In some implementations, the operations of main etch at block 510, gap fill at block 520, and IBE trim etch at block 530 may be performed without introducing a vacuum break between the operations.

[0070] Metals and other conductive materials are preferably not exposed during the IBE trim etch. The remaining gap-fill dielectric material acts as an etch front during the IBE trim etch, thus significantly reducing backsputtering of metal or conductive material. Using the etch front of the gap-fill dielectric material instead, backsputtering of the dielectric material does not adversely affect the electrical and magnetic properties of the MTJ stack. The IBE trim etch can remove the gap-fill dielectric material to an etch depth below the interface between the tunnel barrier layer and the second magnetic layer without etching into the underlying layers. This maintains the initial etch front from the main etch in block 510 and prevents recessing or significant recession into the underlying layers.

[0071] In some implementations, the IBE trim etch removes material deposited on the exposed sidewalls of the patterned MRAM stack. The exposed sidewalls of the patterned MRAM stack are free or substantially free of metal or conductive material deposited on the sidewalls of the patterned MRAM stack. The threshold for when the sidewalls are considered sufficiently clean can be set by the shorting performance of the MRAM device. This is measured as the percentage of shorted devices among all devices. Typically, only one device in a million or less will short. Thus, any remaining residue is thin enough to minimize its impact on the off-state resistance of the MRAM device. For example, "substantially free" with respect to redeposited conductive material can refer to a deposition thickness of less than about 1.5 nm, less than about 1.0 nm, or less than about 0.5 nm. Thus, the conductive material redeposited on the tunnel barrier layer after the IBE trim etch can be negligible or zero. The IBE trim etch can be performed for a time sufficient to remove unwanted material so that the exposed sidewalls of the patterned MRAM stack are free or substantially free of redeposited conductive material.

[0072] FIG. 6E illustrates a cross-sectional schematic diagram of an exemplary IBE trim etch process following the etch back process of FIG. 6D, according to some embodiments. The remaining gap-fill dielectric material 680 serves as an etch front during the IBE trim etch process. During the IBE trim etch process, an ion beam 625 is provided with a relatively low ion energy and an optimized angle of incidence to clean the sidewalls of the patterned MRAM stacks 620a, 620b. The ion beam 625 removes residues 605 from the sidewalls of the patterned MRAM stacks 620a, 620b as the IBE trim etch process progresses. Sputtered atoms and / or molecules 675 from the ion beam 625 may be directed at the sidewalls of the patterned MRAM stacks 620a, 620b. However, the sputtered atoms and / or molecules 675 include dielectric material from the remaining gap-fill dielectric material 680 that does not adversely affect the properties of the patterned MRAM stacks 620a, 620b. The IBE trim etch process proceeds to an etch depth that is below the depth of the tunnel barrier layer 670 and above the underlayer 630. In some implementations, the IBE trim etch process does not proceed significantly into the underlayer 630. The exposed sidewalls of the patterned MRAM stacks 620a, 620b are free of residue 605 comprising conductive or magnetic materials.

[0073] In some implementations, the process 500 further includes conformally depositing an encapsulant material on at least the exposed sidewalls of the patterned MRAM stack after performing the IBE trim etch at block 530. The encapsulant material may include a suitable dielectric material, such as silicon nitride. The encapsulant material may be deposited to prevent or minimize damage to the tunnel barrier layer that may be exposed to air.

[0074] FIG 6F illustrates a cross-sectional schematic diagram of an exemplary encapsulation process following the IBE trim etch process of FIG 6E, according to some embodiments. An encapsulation layer 690, comprising a dielectric material such as silicon nitride, is conformally deposited on the exposed surfaces of the patterned MRAM stacks 620a, 620b. The encapsulation layer 690 is conformally deposited along the sidewalls of the patterned MRAM stacks 620a, 620b and serves to at least protect the tunnel barrier layer 670 from exposure to the ambient environment.

[0075] FIG. 7 illustrates a block diagram of an exemplary processing system for performing deposition and ion beam etching processes, according to some embodiments. The processing system 700 may be a multi-station processing tool with one or more process stations. The processing system 700 may include an inbound load lock 702 and an outbound load lock 704, either or both of which may include a plasma generating source. A robot 706 is configured to move a substrate from a cassette loaded through a pod 708 at atmospheric pressure to the inbound load lock 702 through an atmospheric pressure port 710. The substrate is placed by the robot 706 on a pedestal 712 in the inbound load lock 702, the atmospheric pressure port 710 is closed, and the load lock 702 is pumped down. A chamber transfer port 716 to a processing chamber 714 is opened, and another substrate handling system 718, functioning as another robot, places the substrate in one of the processing stations 780, 782, or a loading station to the processing station 790 for processing. Although the embodiment illustrated in FIG. 7 includes a load lock, it should be understood that in some embodiments, substrates may enter the processing stations directly.

[0076] The illustrated processing chamber 714 includes three processing stations 780, 782, and 790. Processing station 790 may be a removable module and may be suitable for processing multiple substrates at once. In this example, processing station 790 includes four substations, numbered 1 through 4 in the embodiment shown in FIG.

[0077] Each processing station (780, 782, and each of 1, 2, 3, and 4) may have a heated pedestal and a gas line inlet. It should be understood that in some implementations, each processing station may have a different or multiple purpose. For example, in some implementations, processing station 780 may be used to deposit a gap fill dielectric material on a substrate, and the deposition technique may be CVD, PECVD, or other suitable deposition technique. In some implementations, processing station 782 may be used to perform a main etch by IBE, and processing station 790 may be used to perform an IBE trim etch. In some other implementations, processing station 790 may be used to perform an ion beam etch of both the main etch and the IBE trim etch. Processing station 782 may be used to perform other processes, such as CMP, selective etch back, or CVD / PECVD / PVD. In some implementations, processing station 790 may have multiple substations 1-4 for performing multiple IBE trim etch processes or other processes. The IBE trim etch may take longer than the main etch and deposition processes. While the illustrated processing station 790 includes four substations, it will be understood that a processing station according to the present disclosure may include any suitable number of substations. Additionally, while the processing system 700 includes three processing stations (780, 782, and 790), it will be understood that in some implementations, each station may be a removable or modifiable module, such that the apparatus may include more or less than three stations. For example, in some implementations, the processing system 700 may have four or more stations, while in some other implementations, the processing system 700 may have two or fewer stations. In some implementations, additional processing stations may be used to perform planarization processes, such as CMP.In some implementations, an additional processing station may be used to perform a selective etch back to remove the gap-fill dielectric material.

[0078] In some implementations, the processing system 700 can be an integrated multi-station processing tool for performing IBE (main etch and trim etch) and CVD / PECVD / PVD. For example, the processing stations 780, 782, and 790 can be used to perform main etch, gap fill, trim etch, and encapsulation operations. The main etch, gap fill, trim etch, and encapsulation operations can be performed without introducing a vacuum break between the operations. Additional operations of planarization (e.g., CMP) and / or selective etch back (e.g., plasma etch) can be performed in separate tools or in the integrated multi-station processing tool. It is understood that such operations can be performed in separate tools because the tunnel barrier layer of the MTJ stack is not exposed to air or ambient environment during planarization or selective etch back. The tunnel barrier layer is protected by the gap fill dielectric material during planarization or selective etch back.

[0079] 7 shows a substrate handling system 718 for transferring substrates within the processing system 700. In some implementations, the substrate handling system 718 can transfer substrates between various processing stations and / or between processing stations and load locks. Additionally, the processing station 790 can include a separate substrate handling system 760 that is used to move substrates from another loading station 762 to the processing station 790. It should be understood that any suitable substrate handling system can be used. Non-limiting examples include a substrate carousel and a substrate handling robot.

[0080] In various embodiments, the integration of the various stations can address footprint reduction concerns and can efficiently transfer substrates between operations without introducing vacuum breaks. FIG. 7 also illustrates one embodiment of a system controller 750 used to control process conditions and hardware states of the processing system 700. The system controller 750 can include one or more memory devices 756, one or more mass storage devices 754, and one or more processors 752. Aspects of the system controller 750 are described above with respect to FIG. 3. Depending on one or more processing steps performed by the tool, the system controller 950 may communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used for material transport to and from the tool location to transport containers of substrates.

[0081] FIG. 8 illustrates an alternative block diagram of an exemplary processing system for performing deposition and ion beam etching processes, according to some embodiments. Processing system 800 includes a transfer module 803. The transfer module 803 provides a clean pressurized environment to minimize the risk of contamination of the substrate being processed as the substrate moves between various reactor modules. Attached to the transfer module 803 are multi-station reactors 807, 808, and 809, referred to in this context as reactors or tool modules or simply modules, each capable of performing ion beam etching and / or deposition. Reactors 807, 808, and 809 can include multiple stations 811, 813, 815, and 817 that can perform operations sequentially or non-sequentially according to the disclosed embodiments. Stations 811, 813, 815, and 817 can each include a heated pedestal or substrate support, one or more gas inlets or showerheads, or a distribution plate. One or more of modules 807, 808, and 809 may be capable of performing ion beam etching, which may be used to perform the main etch and / or trim etch. Thus, one or more of modules 807, 808, and 809 may include an ion beam etcher with an ion beam source chamber and a processing chamber, as described above in FIG. 3. Another one or more of modules 807, 808, and 809 may be capable of performing deposition operations such as CVD / PECVD / PVD. Thus, the main etch, gap fill, trim etch, and encapsulation operations may be performed without introducing a vacuum break between operations.

[0082] The processing system 800 may also include one or more substrate source modules 801, where substrates are stored before or after processing. An atmospheric pressure robot 804 and atmospheric transfer chamber 819 can initially remove and transfer the substrate from the source module 801 to a load lock 821. A second substrate transfer device (generally a robot arm unit) 805 in a transfer module 803 moves the substrate from the load lock 821 to and between modules attached to the transfer module 803 in a pressurized (e.g., vacuum) environment.

[0083] In various embodiments, a system controller 829 is used to control process conditions and activities during processing. The system controller 829 typically includes one or more memory devices and one or more processors. Aspects of the system controller 829 are described above with respect to FIG. 3. Depending on the processing step or steps performed by the tool, the system controller 829 may communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used for material transport to and from the tool location to transport containers of substrates.

[0084] 9 shows a block diagram of an exemplary processing system for performing planarization and / or etching processes according to some embodiments. Processing systems 700 and 800 may be integrated multi-station processing tools for performing ion beam etching and deposition, and may transfer substrates to processing system 900 for performing planarization and / or selective etching processes.

[0085] The processing system 900 may include a vacuum transfer module 938 (VTM). The arrangement of transfer modules for transferring substrates between multiple storage facilities and processing modules is sometimes referred to as a "cluster tool architecture" system. An airlock 930, also known as a load lock or transfer module, is shown in the vacuum transfer module 938 with four processing modules 920a, 920b, 920c, and 920d that may be individually optimized to perform various operations. As an example, one or more of the processing modules 920a, 920b, 920c, and 920d may be implemented to perform selective etching. One or more of the processing modules 920a, 920b, 920c, and 920d may be implemented to perform a planarization process such as CMP. In some implementations, one or more of the processing modules 920a, 920b, 920c, and 920d may be implemented to perform ion beam etching or deposition. Airlock 930 and processing modules 920a, 920b, 920c, and 920d are sometimes referred to as "stations." Each station has a facet 936 that interfaces the station to a vacuum transfer module 938. Inside each facet 936, sensors 1-18 are used to detect the passage of substrates 926 as they move between the respective stations.

[0086] A robot 922 can be used to transfer substrates 926 between stations. In one embodiment, the robot 922 has one arm, and in another embodiment, the robot 922 has two arms, each arm having an end effector 924 for selecting a substrate, such as substrate 926, for transfer. A front-end robot 932 in an atmospheric transfer module (ATM) 940 is used to transfer substrates 926 from a cassette or from a front-opening unified pod (FOUP) 934 in a load port module (LPM) 942 to the airlock 930. A module center 928 in the process modules 920a, 920b, 920c, and 920d is one location for placing the substrate 926. An aligner 944 in the ATM 940 is used to align the substrate.

[0087] In an exemplary processing method, the substrate is placed in one of the FOUPs 934 in the LPM 942. The front-end robot 932 transfers the substrate from the FOUP 934 to an aligner 944, which allows the substrate 926 to be properly centered before being etched or processed. After being aligned, the substrate 926 is moved into the airlock 930 by the front-end robot 932. The airlock module can match the environment between the ATM and the VTM so that the substrate 926 can move between the two pressure environments without being damaged. From the airlock 930, the substrate 926 is moved by the robot 922 through a vacuum transfer module 938 to one of the processing modules 920a, 920b, 920c, and 920d. To accomplish this substrate movement, the robot 922 uses an end effector 924 on each of its arms. Once the substrate 926 has been processed, it is moved from the processing modules 920a, 920b, 920c, and 920d to an airlock 930 by the robot 922. From here, the substrate 926 may be moved by the front end robot 932 to one of the FOUPs or to the aligner 944. The controller described above with respect to Figure 3 may be implemented using the tool of Figure 9. Depending on one or more processing steps performed by the tool, the controller may communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used for material transport to and from the tool location to transport containers of substrates.

[0088] conclusion In the foregoing description, numerous specific details are set forth in order to provide a thorough understanding of the presented embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail so as not to unnecessarily obscure the disclosed embodiments. While the disclosed embodiments are described in conjunction with specific embodiments, it will be understood that they are not intended to limit the disclosed embodiments.

[0089] Although the foregoing embodiments have been described in some detail for clarity of understanding, it will be apparent that certain changes and modifications may be implemented within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the process, system, and apparatus of the present embodiments. Thus, the present embodiments should be considered as illustrative rather than restrictive, and the embodiments should not be limited to the details set forth herein. The present invention can be realized, for example, in the following manner. Application example 1: 1. A method of ion beam etching comprising the steps of: etching through a plurality of magnetoresistive random access memory (MRAM) layers disposed on a substrate to form a patterned MRAM stack, the plurality of MRAM layers including one or more magnetic layers and a tunnel barrier layer, and etching through the plurality of MRAM layers including ion beam etching (IBE) through at least the tunnel barrier layer; forming a gap fill dielectric material in spaces between the patterned MRAM stacks; performing an IBE trim etch to remove at least a portion of the gap-fill dielectric material and conductive material deposited on sidewalls of the patterned MRAM stack; A method comprising: Application example 2: The method according to Application Example 1, the gap-fill dielectric material is formed to a sufficient depth above an underlayer disposed between the substrate and the plurality of MRAM layers such that performing the IBE trim etch does not recess the underlayer. Application example 3: The method according to Application Example 2, The method, wherein the sufficient depth above the underlayer is between about 1 nm and about 20 nm from a top surface of the underlayer. Application example 4: The method according to Application Example 1, forming the gap-fill dielectric material in spaces between the patterned MRAM stacks; depositing the gap-fill dielectric material in the spaces between and over the patterned MRAM stacks. A method comprising: Application example 5: The method according to Application Example 4, forming the gap-fill dielectric material in spaces between the patterned MRAM stacks; Selectively etching the gap-fill dielectric material to an etch depth above a depth of the tunnel barrier layer. The method further comprising: Application example 6: The method according to Application Example 5, planarizing the gap-fill dielectric material deposited over the patterned MRAM stack; The method further comprising: Example 7: The method according to any one of Application Examples 1 to 6, The method, wherein the gap-fill dielectric material comprises silicon nitride, silicon oxide, silicon oxycarbide, germanium oxide, magnesium oxide, germanium nitride, or a combination thereof. Application example 8: The method according to Application Example 7, The method, wherein the gap-fill dielectric material comprises one or both of silicon nitride and silicon oxide. Example 9: The method according to any one of Application Examples 1 to 6, The method, wherein the operations of etching through the plurality of MRAM layers, forming the gap-fill dielectric material, and performing the IBE trim etch are performed without introducing a vacuum break between operations. Example 10: The method according to any one of Application Examples 1 to 6, the plurality of MRAM layers including a first magnetic layer, a second magnetic layer, the tunnel barrier layer between the first magnetic layer and the second magnetic layer, and an underlayer disposed below the second magnetic layer, the underlayer including a dielectric material and the tunnel barrier layer including a non-magnetic insulating material. Example 11: The method according to Application Example 10, The method, wherein etching through the plurality of MRAM layers comprises ion beam etching through the first magnetic layer, the tunnel barrier layer, and the second magnetic layer without etching through the underlayers. Application example 12: The method according to Application Example 10, The method, wherein etching through the plurality of MRAM layers includes reactive ion etching (RIE) through the first magnetic layer and ion beam etching through the tunnel barrier layer. Application example 13: The method according to Application Example 10, 21. The method of claim 20, wherein etching through the plurality of MRAM layers includes etching through the first magnetic layer, the tunnel barrier layer, and the second magnetic layer, and wherein etching through the plurality of MRAM layers is stopped on the underlayer. Example 14: The method according to any one of Application Examples 1 to 6, 1. The method of claim 1, wherein ion beam etching through at least the tunnel barrier layer comprises applying a first ion beam to the substrate having an energy between about 200 eV and about 10,000 eV, and performing an IBE trim etch comprises applying a second ion beam to the substrate having an energy between about 20 eV and about 400 eV. Application example 15: The method according to any one of Application Examples 1 to 6, The method, wherein performing an IBE trim etch is performed without etching through an underlayer disposed below the plurality of MRAM layers. Application example 16: The method according to any one of Application Examples 1 to 6, the conductive material comprises tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), cobalt (Co), nickel (Ni), iron (Fe), platinum (Pt), ruthenium (Ru), or a combination thereof, and the sidewalls of the patterned MRAM stack are substantially free of the conductive material deposited on the sidewalls of the patterned MRAM stack after performing the IBE trim etch. method. Example 17: The method according to any one of Application Examples 1 to 6, conformally depositing an encapsulant material on at least the sidewalls of the patterned MRAM stack after performing the IBE trim etch. The method further comprising: Application example 18: 1. An apparatus for performing ion beam etching, comprising: an ion beam source chamber; a process chamber coupled to the ion beam source chamber; A control unit, The control unit: disposing a plurality of MRAM layers on a substrate in the processing chamber, the plurality of MRAM layers including one or more magnetic layers and a tunnel barrier layer; etching through the plurality of MRAM layers disposed on the substrate to form a patterned MRAM stack, the etching through the plurality of MRAM layers including ion beam etching (IBE) through at least the tunnel barrier layer; forming a gap fill dielectric material in spaces between the patterned MRAM stacks; and performing an IBE trim etch to remove at least a portion of the gap-fill dielectric material and conductive material deposited on sidewalls of the patterned MRAM stack; An apparatus configured to provide instructions for performing the steps of: Example 19: The device according to application example 18, The controller configured to provide instructions to form the gap-fill dielectric material includes: depositing the gap-fill dielectric material in the spaces between and over the patterned MRAM stacks. The apparatus is further configured to provide instructions for performing the steps of: Example 20: The device according to application example 19, The controller configured to provide instructions to form the gap-fill dielectric material includes: Selectively etching the gap-fill dielectric material to an etch depth above a depth of the tunnel barrier layer. The apparatus is further configured to provide instructions for performing the steps of: Example 21: The device according to application example 20, The control unit is planarizing the gap-fill dielectric material deposited over the patterned MRAM stack prior to selectively etching the gap-fill dielectric material. The apparatus is further configured to provide instructions for performing the steps of: Example 22: The device according to any one of Application Examples 18 to 21, The device, wherein the gap-fill dielectric material comprises one or both of silicon nitride and silicon oxide. Application example 23: The device according to any one of Application Examples 18 to 21, the controller configured to provide instructions for performing an IBE trim etch is further configured to apply a first ion beam having an energy between about 200 eV and about 10,000 eV to the substrate, and the controller configured to provide instructions for performing an IBE trim etch is further configured to apply a second ion beam having an energy between about 20 eV and about 400 eV to the substrate. Application 24: The device according to any one of Application Examples 18 to 21, the gap-fill dielectric material is formed to a sufficient depth above an underlying layer disposed between the substrate and the plurality of MRAM layers such that performing the IBE trim etch does not recess the underlying layer.

Claims

1. 1. A method of ion beam etching comprising the steps of: etching through a plurality of magnetoresistive random access memory (MRAM) layers disposed on a substrate to form a patterned MRAM stack, the plurality of MRAM layers including one or more magnetic layers and a tunnel barrier layer, and etching through the plurality of MRAM layers including ion beam etching (IBE) through at least the tunnel barrier layer; forming a gap fill dielectric material in spaces between the patterned MRAM stacks; performing an IBE trim etch to remove a portion of the gap-fill dielectric material and conductive material deposited on sidewalls of the patterned MRAM stack, wherein a remaining gap-fill dielectric material after the IBE trim etch is at a depth below the tunnel barrier layer and above an underlayer disposed between the substrate and the plurality of MRAM layers; A method comprising:

2. 2. The method of claim 1 , The method of claim 1, wherein the gap-fill dielectric material is formed over the underlayer to a depth such that performing the IBE trim etch does not recess the underlayer.

3. 3. The method of claim 2, The method, wherein a depth of the gap-fill dielectric material above the underlayer is between about 1 nm and about 20 nm from a top surface of the underlayer.

4. 2. The method of claim 1 , forming the gap-fill dielectric material in spaces between the patterned MRAM stacks; depositing the gap-fill dielectric material in the spaces between and over the patterned MRAM stacks. A method comprising:

5. 5. The method of claim 4, forming the gap-fill dielectric material in spaces between the patterned MRAM stacks; Selectively etching the gap-fill dielectric material to an etch depth above a depth of the tunnel barrier layer. The method further comprising:

6. 6. The method of claim 5, planarizing the gap-fill dielectric material deposited over the patterned MRAM stack; The method further comprising:

7. The method according to any one of claims 1 to 6, The method, wherein the gap-fill dielectric material comprises silicon nitride, silicon oxide, silicon oxycarbide, germanium oxide, magnesium oxide, germanium nitride, or a combination thereof.

8. 8. The method of claim 7, The method, wherein the gap-fill dielectric material comprises one or both of silicon nitride and silicon oxide.

9. The method according to any one of claims 1 to 6, The method, wherein the operations of etching through the plurality of MRAM layers, forming the gap-fill dielectric material, and performing the IBE trim etch are performed without introducing a vacuum break between operations.

10. The method according to any one of claims 1 to 6, the plurality of MRAM layers including a first magnetic layer, a second magnetic layer, the tunnel barrier layer between the first magnetic layer and the second magnetic layer, and the underlayer disposed below the second magnetic layer, the underlayer including a dielectric material and the tunnel barrier layer including a non-magnetic insulating material.

11. 11. The method of claim 10, The method, wherein etching through the plurality of MRAM layers comprises ion beam etching through the first magnetic layer, the tunnel barrier layer, and the second magnetic layer without etching through the underlayers.

12. 11. The method of claim 10, The method, wherein etching through the plurality of MRAM layers includes reactive ion etching (RIE) through the first magnetic layer and ion beam etching through the tunnel barrier layer.

13. 11. The method of claim 10, The method of claim 1, wherein etching through the plurality of MRAM layers includes etching through the first magnetic layer, the tunnel barrier layer, and the second magnetic layer, and wherein etching through the plurality of MRAM layers is stopped on the underlayer.

14. The method according to any one of claims 1 to 6, 11. The method of claim 10, wherein ion beam etching through at least the tunnel barrier layer comprises applying a first ion beam to the substrate having an energy of about 200 eV to about 10,000 eV, and performing an IBE trim etch comprises applying a second ion beam to the substrate having an energy of about 20 eV to about 400 eV.

15. The method according to any one of claims 1 to 6, The method, wherein performing an IBE trim etch is done without etching through an underlying layer disposed below the plurality of MRAM layers.

16. The method according to any one of claims 1 to 6, the conductive material comprises tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), cobalt (Co), nickel (Ni), iron (Fe), platinum (Pt), ruthenium (Ru), or a combination thereof, and the sidewalls of the patterned MRAM stack are substantially free of the conductive material deposited on the sidewalls of the patterned MRAM stack after performing the IBE trim etch. method.

17. The method according to any one of claims 1 to 6, conformally depositing an encapsulant material on at least the sidewalls of the patterned MRAM stack after performing the IBE trim etch. The method further comprising:

18. 1. An apparatus for performing ion beam etching, comprising: an ion beam source chamber; a process chamber coupled to the ion beam source chamber; A control unit, The control unit: disposing a plurality of MRAM layers on a substrate in the processing chamber, the plurality of MRAM layers including one or more magnetic layers and a tunnel barrier layer; etching through the plurality of MRAM layers disposed on the substrate to form a patterned MRAM stack, the etching through the plurality of MRAM layers including ion beam etching (IBE) through at least the tunnel barrier layer; forming a gap-fill dielectric material in spaces between the patterned MRAM stacks; and performing an IBE trim etch to remove a portion of the gap-fill dielectric material and conductive material deposited on sidewalls of the patterned MRAM stack, wherein a remaining gap-fill dielectric material after the IBE trim etch is at a depth below the tunnel barrier layer and above an underlayer disposed between the substrate and the plurality of MRAM layers; An apparatus configured to provide instructions for performing the steps of:

19. 20. The apparatus of claim 18, The controller configured to provide instructions to form the gap-fill dielectric material includes: depositing the gap-fill dielectric material in the spaces between and over the patterned MRAM stacks. The apparatus is further configured to provide instructions for performing the steps of:

20. 20. The apparatus of claim 19, The controller configured to provide instructions to form the gap-fill dielectric material includes: Selectively etching the gap-fill dielectric material to an etch depth above the depth of the tunnel barrier layer. The apparatus is further configured to provide instructions for performing the steps of:

21. 21. The apparatus of claim 20, The control unit is planarizing the gap-fill dielectric material deposited over the patterned MRAM stack prior to selectively etching the gap-fill dielectric material. The apparatus is further configured to provide instructions for performing the steps of:

22. An apparatus according to any one of claims 18 to 21, comprising: The device, wherein the gap-fill dielectric material comprises one or both of silicon nitride and silicon oxide.

23. An apparatus according to any one of claims 18 to 21, comprising: the controller configured to provide instructions to perform an IBE trim etch is further configured to apply a first ion beam having an energy between about 200 eV and about 10,000 eV to the substrate, and the controller configured to provide instructions to perform an IBE trim etch is further configured to apply a second ion beam having an energy between about 20 eV and about 400 eV to the substrate.

24. An apparatus according to any one of claims 18 to 21, comprising: the gap-fill dielectric material is formed over the underlayer to a depth such that performing the IBE trim etch does not recess the underlayer.

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