Semiconductor storage device and control device for semiconductor storage device

Abstract

To provide a semiconductor storage device and a control device for the semiconductor storage device which reduce influence of wiring parasitic resistance at reading information, and expand an area where memory cells can be arranged.SOLUTION: A semiconductor storage device includes: a memory cell array having a plurality of memory cells (MC1 to MCm) including a resistance variable memory element capable of storing a resistance state and a switch; a reading determination circuit (25) that compares a measurement signal from the memory cell selected in the memory cell array and a reference signal and determines the resistance state so as to read information from the resistance variable memory element; and a reference signal correction unit (81) that corrects a level of the reference signal based on the selected position of the memory cell in the memory cell array.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present invention relates to a semiconductor memory device using a resistance change type memory element and a control device for the semiconductor memory device. [Background technology]

[0002] In recent years, in semiconductor memory devices, the use of non-volatile memory (e.g., MRAM (Magneto-resistive Random Access Memory)), which does not require a power source to retain recorded information, has been considered in place of volatile memory (e.g., DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory)), which requires a power source to retain recorded information.

[0003] MRAM has ferromagnetic elements as resistance-change memory elements, and stores information by utilizing the difference in the resistance state of the ferromagnetic elements. To read information from such a resistance-change memory element, a specific ferromagnetic element is selected and the resistance value of the selected ferromagnetic element is measured. The stored information can then be read by determining whether the ferromagnetic element is in a high-resistance state or a low-resistance state.

[0004] Patent Document 1 discloses a technique relating to a semiconductor memory element that uses a ferromagnetic element as the memory element.

[0005] According to this technology, in a memory cell array consisting of memory cells arranged two-dimensionally, stored information is read by determining the resistance state of a specific memory cell. The resistance state is determined by a read determination circuit (e.g., a sense amplifier) ​​provided at the end of the column direction of the memory cell array, which receives two inputs, a measurement signal and a reference signal, compares them, and determines a read value.

[0006] Specifically, memory cells set to a reference level are arranged in the same row of the memory array, and the read determination circuit receives a measurement signal from the memory cell from which information is to be read at one terminal. At the same time, a reference signal from a memory cell set to the reference level in the same row of the memory array is received at the other terminal. The magnitude of the measurement signal and the reference signal are compared. As a result, the resistance state of the memory cell can be determined and the stored information can be read.

[0007] Similarly, Patent Documents 2 and 3 disclose techniques relating to semiconductor memory elements using ferromagnetic elements. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Patent No. 3873055 [Patent Document 2] Patent No. 6749021 [Patent Document 3] Patent No. 2856848 Summary of the Invention [Problem to be solved by the invention]

[0009] In a resistance-change memory element, the parasitic resistance of the wiring in the current path during resistance measurement is relatively large (e.g., several kΩ), which may affect the determination of the resistance state. Furthermore, as semiconductor manufacturing processes become more miniaturized, the smaller the memory element, the greater the influence of the parasitic resistance of the wiring. Therefore, if we try to suppress the influence of the parasitic resistance of the wiring in order to measure the resistance, this will limit the miniaturization of the overall configuration and size of the semiconductor memory device.

[0010] For example, when the technology disclosed in Patent Document 1 is applied to a one-cell system, i.e., a configuration in which a memory cell operates independently, both the measurement signal and the reference signal are affected by the wiring parasitic resistance of the data line DL and the source line SL.

[0011] The difference in measured current between the high-resistance and low-resistance states of a ferromagnetic element is extremely small. Therefore, even if the resistance of the reference memory cell is set to a level that can be compared by the read / write circuit, it is difficult to accurately determine the resistance state of the memory cell due to the influence of parasitic resistance of the wiring.

[0012] Furthermore, when the technology disclosed in Patent Document 1 is applied to a two-cell configuration in which memory cells operate in pairs, the reference memories are also set in pairs. Specifically, the resistance values ​​of the paired reference memory cells are set to a high resistance state and a low resistance state, and the intermediate value of the outputs from these reference memory cells is used as the reference signal.

[0013] However, to set the reference memory cell to two resistance states, a high resistance state and a low resistance state, a data line and a source line must be provided for each pair of reference memory cells. Furthermore, since the data line and the source line are connected in parallel to obtain an intermediate value between the high resistance state and the low resistance state, the overall wiring parasitic resistance is reduced. Therefore, the influence of the wiring parasitic resistance on the measurement signal and the reference signal input to the read determination circuit is not equal, which may require correction of the measurement signal.

[0014] In this way, in a semiconductor memory device using a ferromagnetic element as a memory element, the difference in measurement current between the high resistance state and the low resistance state is extremely small, so that the level range of the reference signal used to determine the resistance state is more susceptible to the influence of wiring parasitic resistance, which limits the area in which the memory cell can be arranged.

[0015] The present invention has been made to solve such problems, and aims to provide a semiconductor memory device and a control device for a semiconductor memory device that reduce the effect of wiring parasitic resistance when reading information and expand the area in which memory cells can be arranged. [Means for solving the problem]

[0016] A semiconductor memory device according to one aspect of the present invention includes a memory cell array having a plurality of memory cells each including a resistance-change memory element capable of storing a resistance state and a switch; a read determination circuit that determines the resistance state by comparing a measurement signal from a memory cell selected in the memory cell array with a reference signal in order to read information from the resistance-change memory element; and a reference signal correction unit that corrects the level of the reference signal based on the selected position of the memory cell in the memory cell array.

[0017] A control device for a semiconductor memory device according to another aspect of the present invention reads the contents stored in a memory cell from a semiconductor memory device including a memory cell array having a plurality of memory cells each including a resistance-change memory element capable of storing a resistance state and a switch, and a read determination circuit that compares a measurement signal from a memory cell selected in the memory cell array with a reference signal. The control device corrects the level of a reference signal output from a reference signal generator based on the selected position of the memory cell in the memory cell array, causes the read determination circuit to compare the measurement signal from the memory cell selected in the memory cell array with the reference signal, and determines the resistance state of the resistance-change memory element based on the comparison result by the read determination circuit. [Effects of the Invention]

[0018] In a semiconductor memory device according to one aspect of the present invention, a reference signal correction unit corrects the level of a reference signal according to the selected position of a memory cell. Here, the measurement signal, which is one input of the read determination circuit, is affected by a wiring parasitic resistance according to the selected position of the memory cell. In contrast, the reference signal, which is the other input of the read determination circuit, is corrected by the reference signal correction unit according to the selected position of the memory cell, and is therefore affected by a wiring parasitic resistance according to the selected position.

[0019] In this way, both the measurement signal and the reference signal input to the read determination circuit contain the same influence of the wiring parasitic resistance depending on the selected position of the memory cell. As a result, the influence of the wiring parasitic resistance when comparing the measurement signal and the reference signal can be reduced, thereby expanding the area in which memory cells can be arranged. [Brief explanation of the drawings]

[0020] [Figure 1] FIG. 1 is a schematic diagram of a memory cell constituting a semiconductor memory device of a comparative example. [Figure 2A] FIG. 2A is a schematic circuit diagram of a memory cell array composed of a plurality of memory cells and its peripherals. [Figure 2B] FIG. 2B shows an example of a specific configuration of the read determination circuit. [Figure 2C] FIG. 2C shows an example of a specific configuration of the read determination circuit. [Figure 2D] FIG. 2D shows an example of a specific configuration of the read determination circuit. [Figure 2E] FIG. 2E shows an example of a specific configuration of the read determination circuit. [Figure 3] FIG. 3 is a schematic circuit configuration diagram of the periphery of the memory cell array. [Figure 4] FIG. 4 is a schematic diagram of a semiconductor memory device. [Figure 5] FIG. 5 is a schematic circuit configuration diagram of the periphery of the read determination circuit. [Figure 6] FIG. 6 is a graph showing the relationship between read current and the position of a selected memory cell. [Figure 7] FIG. 7 is a graph showing the relationship between read voltage and the location of a selected memory cell. [Figure 8] FIG. 8 is a schematic circuit configuration diagram of the periphery of the read determination circuit in the first embodiment. [Figure 9] FIG. 9 is a graph showing the relationship between read current and the position of a selected memory cell. [Figure 10]FIG. 10 is a schematic circuit configuration diagram of the periphery of the read determination circuit in the second embodiment. [Figure 11] FIG. 11 shows the logic circuit of the row decoder. [Figure 12] FIG. 12 is a logic correspondence table showing the relationship between the areas where word lines are arranged and the inputs and outputs of the row decoders. [Figure 13] FIG. 13 is a detailed circuit diagram of the variable resistor section. [Figure 14] FIG. 14 is a graph showing the relationship between read current and the position of a selected memory cell. [Figure 15] FIG. 15 is a graph showing the relationship between read voltage and the position of a selected memory cell. [Figure 16] FIG. 16 is a diagram showing the overall configuration of a sub-array type memory cell array in the third embodiment. [Figure 17] FIG. 17 is a circuit configuration diagram of a memory cell array. [Figure 18] FIG. 18 is a graph showing an example of the relationship between the read current and the position of the selected memory cell. [Figure 19] FIG. 19 is a graph showing an example of the relationship between the read voltage and the position of the selected memory cell. [Figure 20] FIG. 20 is a graph showing another example of the relationship between the read current and the position of the selected memory cell. [Figure 21] FIG. 21 is a graph showing another example of the relationship between the read voltage and the position of the selected memory cell. [Figure 22] FIG. 22 is a schematic diagram showing the configuration of a dummy cell used in the fourth embodiment. [Figure 23] FIG. 23 is an explanatory diagram of a read operation of a memory cell. [Figure 24] FIG. 24 is an example of a circuit configuration diagram of a memory cell array. [Figure 25] FIG. 25 is another example of a circuit configuration diagram of a memory cell array. [Figure 26]FIG. 26 is a schematic configuration diagram of a semiconductor memory device according to the fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0021] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the description of the embodiments, unless numbers, quantities, etc. are mentioned or otherwise specified, the scope of the present invention is not necessarily limited to those numbers, quantities, etc. In the drawings showing the embodiments, the same names indicate the same or equivalent parts. Furthermore, in the description of the embodiments, duplicated descriptions of parts with the same names will be omitted and will not be repeated.

[0022] First, before describing the embodiment of the present invention, the configuration and operation of a semiconductor memory device of a comparative example that does not include a reference signal correction unit according to the present invention will be described.

[0023] (Comparative Example) 1 is a schematic diagram of a memory cell constituting a semiconductor memory device of a comparative example. This diagram shows a resistance change type memory cell MC (Memory Cell) composed of a MOS type transistor 11 (Metal-Oxide-Semiconductor Transistor) and a ferromagnetic element 12 (MTJ: Magnetic Tunneling Junction).

[0024] The transistor 11 is a semiconductor switch having a gate (G), a source (S), and a drain (D). Application of a voltage to the gate (G) controls conduction between the source (S) and the drain (D). The transistor 11 has a gate (G) connected to a word line WL (Word Line), a source (S) connected to a source line SL (Source Line), and a drain (D) connected to one end of the ferromagnetic element 12. The other end of the ferromagnetic element 12 is connected to a data line DL (Date Line). The MOS transistor 11 is an example of a switch provided in the memory cell MC, but is not limited to this and may be any of various switches used in semiconductor memory devices.

[0025] The ferromagnetic element 12 corresponds to a magnetoresistive random access memory (MRAM) type storage element and is configured to be able to store a variable magnetization direction. The resistance state of the ferromagnetic element 12 changes to a low resistance state (parallel state) or a high resistance state (antiparallel state) depending on the magnetization direction. The storage contents of the memory cell MC can be read by measuring the resistance value of the ferromagnetic element 12 and determining the resistance state.

[0026] 2A is a schematic circuit diagram of a memory cell array composed of a plurality of memory cells MC and its peripheral circuit configuration. This diagram shows a memory cell array 21 composed of a plurality of memory cells MC arranged two-dimensionally, and its peripheral circuit configuration. In the two-dimensionally arranged memory cells MC, memory cells MC in the same row are connected to the same word line WL, and memory cells MC in the same column are connected to the same data line DL and source line SL. Word lines WL0 to WLm-1 are provided from right to left in the diagram, and data lines DL0 to DLn-1 and source lines SL0 to SLn-1 are provided from bottom to top in the diagram.

[0027] The word lines WL0 to WLm-1 are connected to a row control unit 22, and the data lines DL0 to DLn-1 and source lines SL0 to SLn-1 are connected to a column control unit 23. The row control unit 22 and the column control unit 23 select a memory cell MC to be read or written by controlling any one of the word lines WL, any one of the data lines DL, and any one of the source lines SL.

[0028] The row control unit 22 includes a row decoder and a word drive. When the row decoder receives a signal indicating a memory cell MC to be read or written, it determines the word line WL of the memory cell MC to be read or written. Here, the word drive includes an address bus connected to the word lines WL to WLm-1, and receives input of an address signal corresponding to the address bus. Therefore, when the row decoder outputs an address signal corresponding to the determined word line WL to the word drive, a voltage is applied to a predetermined address bus in the word drive. By this operation, a predetermined word line WL is selected.

[0029] The column control unit 23 includes a column decoder and a column switch. The column switch controls the connection between the data line DL and source line SL on the memory cell array 21 side and the terminals (DL terminal and SL terminal) on the opposite side (the write drive 24 or the read determination circuit 25). When the column control unit 23 receives a signal indicating a memory cell MC to be read or written, the column decoder determines the data line DL and source line SL of the memory cell MC to be read or written. Then, the column decoder turns on the column switch connected to the determined data line DL and source line SL. Through this operation, the data line DL and source line SL connected to the memory cell MC selected on the memory cell array 21 side are connected to the terminals on the opposite side (the write drive 24 or the read determination circuit 25).

[0030] In this way, the row control unit 22 applies a voltage to a predetermined word line WL, and the column control unit 23 connects the data line DL and the source line SL between the memory cell array 21 side and the opposite side (the write drive 24 or the read determination circuit 25). As a result, a predetermined memory cell MC is selected, and information is read / written.

[0031] Writing data to a specific memory cell MC is controlled as follows: First, the row control unit 22 applies a voltage to the word line WL connected to the memory cell MC to be written, causing the transistor 11 in the selected memory cell MC to become conductive. Then, the column control unit 23 connects one of the data lines DL and source lines SL on the memory cell array 21 to the data line DL and source line SL of the write drive 24, respectively.

[0032] In this state, the write drive 24 sets the data line DL to a higher level than the source line SL, thereby placing the ferromagnetic element 12 of the selected memory cell MC in a high resistance state. The write drive 24 sets the data line DL to a lower level than the source line SL, thereby placing the ferromagnetic element 12 of the selected memory cell MC in a low resistance state. In this way, the write drive 24 performs a write process of information to the selected memory cell MC. Note that the relationship between the potential relationship between the data line DL and the source line SL and the resistance state (high resistance state / low resistance state) of the ferromagnetic element 12 is not limited to the above description. Since the resistance state of the ferromagnetic element 12 is determined by the connection relationship between the ferromagnetic element 12 and the data line DL and source line SL, the relationship between the potential relationship between the data line DL and the source line SL and the resistance state (high resistance state / low resistance state) may be reversed from the above description.

[0033] Next, the control of reading data from a specified memory cell MC will be described. When the row control unit 22 applies a voltage to the word line WL connected to the memory cell MC to be written, the transistor 11 in the selected memory cell MC becomes conductive. Then, the column control unit 23 connects the measurement signal input terminal of the read determination circuit 25 to the data line DL connected to the selected memory cell MC in the memory cell array 21. The reference signal input terminal of the memory cell array 21 is connected to the reference signal generation unit 26.

[0034] In this state, the read determination circuit 25 receives a measurement signal input from the selected memory cell MC and a reference signal input from the reference signal generator 26. The read determination circuit 25 compares the levels of the measurement signal and the reference signal, and determines the resistance state of the ferromagnetic element 12 of the memory cell MC based on the comparison result. This makes it possible to read information stored in the memory cell MC. Note that the read determination circuit 25 may acquire and compare either a voltage value or a current value.

[0035] Here, the optimum voltages (currents) for the word lines WL, data lines DL, and source lines SL are different between write and read operations, so that the transistors 11 arranged around the memory cell array 21 must be designed to be used for high voltages or low voltages so that the optimum range of voltages (currents) is used.

[0036] In this way, the read determination circuit 25 is used to compare either the current value or the voltage value output from the memory cell MC with a reference value (reference current or reference voltage) to determine the resistance state of the memory cell MC. Hereinafter, the case where a current value is used is referred to as a current mode, and the case where a voltage value is used is referred to as a voltage mode. A sense amplifier can be considered as an example of the configuration of the read determination circuit 25 in the current mode. For example, the sense amplifier outputs a high-level / low-level voltage depending on the magnitude relationship between the current of the measurement signal and the reference signal received via the input terminal. As a result, the resistance state of the memory cell MC can be determined based on this voltage level.

[0037] The read determination circuit 25 is not limited to a sense amplifier, and may have the configurations shown in Figures 2B to 2E, for example. The read determination circuit 25 shown in Figures 2B and 2D is a circuit used in the current mode and compares input current values, while the read determination circuit 25 shown in Figures 2C and 2E is a circuit used in the voltage mode and compares input voltage values.

[0038] 2B, the read determination circuit 25 may be a current comparison circuit 251. The current comparison circuit 251 compares the input current values ​​of input 1 and input 2, and outputs a high-level voltage if, for example, the current value of input 1 is greater than the current value of input 2.

[0039] 2C, the read determination circuit 25 may be a voltage comparison circuit 252. The voltage comparison circuit 252 compares the input voltage values ​​of input 1 and input 2, and outputs a high-level voltage if, for example, the voltage value of input 1 is greater than the voltage value of input 2.

[0040] 2D, the read determination circuit 25 is configured by connecting a current comparison circuit 253 and a voltage comparison circuit 254 in series. The current comparison circuit 253 outputs voltage values, maintaining a magnitude relationship, to two output terminals according to current values ​​input via two input terminals. The voltage comparison circuit 254 outputs a high-level / low-level voltage according to the magnitude relationship between the voltage values ​​input via the two input terminals.

[0041] 2E, the read determination circuit 25 is configured by connecting three voltage comparison circuits 255 to 257 in series. The voltage comparison circuits 255 and 256 each output voltage values ​​that maintain a magnitude relationship from two output terminals in accordance with voltage values ​​input via two input terminals. The voltage comparison circuit 257 outputs a high-level / low-level voltage in accordance with the magnitude relationship between the voltage values ​​input via the two input terminals.

[0042] In this way, the read determination circuit 25 shown in FIGS. 2D and 2E is configured by combining multiple stages of comparison circuits, and as a determination circuit configuration that compares two input values ​​and outputs them, it is possible to improve and optimize the comparison sensitivity, operating speed, power consumption, etc.

[0043] FIG. 3 is a schematic circuit diagram of the periphery of the memory cell array 21. For readability, this diagram representatively shows one memory cell MC selected as the memory cell array 21. As will be explained below, in the high-voltage element region 31 around the memory cell array 21, indicated by the dotted line, high-voltage semiconductor elements with high voltage resistance must be used. Outside the high-voltage element region 31, low-voltage semiconductor elements may be used. The boundary between the high-voltage element region 31, where high-voltage semiconductor elements are used, and the region where low-voltage semiconductor elements are used is determined by rational and efficient factors, such as the circuit system and circuit configuration, and is not limited to the example shown in this diagram.

[0044] On the right side of the high-voltage element region 31 in the figure, a column switch of the column control unit 23 is provided, connected to the output terminal indicated by a white circle. Controlling the column control unit 23 (column switch) controls the connection between the data line DL connected to the selected memory cell MC and the input terminal of the measurement signal of the read determination circuit 25. A latch circuit 32 is provided at the output terminal of the read determination circuit 25. The latch circuit 32 is a holding circuit provided to make the output result of the read determination circuit 25 available in a subsequent stage. Although an amplifier is not provided in the example in this figure, an amplifier may also be provided.

[0045] On the left side of the figure, the high-voltage element region 31 is provided with three terminals indicated by white circles, specifically, a terminal for receiving a control signal and two write terminals used for write processing. While the control terminal is receiving the control signal, data is read from or written to the selected memory cell MC. Write data Din and inverted data Sin of the write data Din are input to the two write terminals. During data write processing, the resistance state of the ferromagnetic element 12 of the memory cell MC is changed according to the input to these two write terminals.

[0046] More specifically, a latch circuit 331 and two AND logic units 332 and 333 are provided in front of the two write terminals (on the left side of the figure), and receive inputs of write data Din and a write enable signal WE. The AND logic unit 332 receives the write data Din and the write enable signal WE input via the latch circuit 331 and performs a logical OR operation. In this way, when the write enable signal WE is on, the write data Din is input to the data line DL.

[0047] The logical AND operator 333 receives the inverted write data Din and the write enable signal WE and performs a logical OR operation. In this way, when the write enable signal WE is on, the inverted data Sin of the write data Din is input to the source line SL.

[0048] A level shifter 34D, a controlled inverter 35D (clock inverter), and a control switch 36D are provided on the data line DL inside the high-voltage element region 31. By providing the level shifter 34D and the controlled inverter 35D, a signal of an optimum level can be input to the data line DL regardless of the magnitude of the write data Din, and the generation of a reverse current can be suppressed.

[0049] Similarly, the source line SL is provided with a level shifter 34S, an inverter 35S, and a control switch 36S, and the word line WL is provided with a level shifter 34W and an inverter 35W.

[0050] A level shifter 34C and inverters 351C and 352C are provided on the control line CL, which transmits the control signal. Here, the control switches 36D and 36S provided on the data line DL and source line SL are configured by combining an N-type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) that turns on when a positive voltage is applied to its gate and a P-type MOSFET that turns on when a negative voltage is applied to its gate. The control signal output from the inverter 351C is input to the N-type MOSFET, and the control signal output from the inverter 352C is inverted and input to the P-type MOSFET, so that the control switches 36D and 36S are conductive when the control signal is high.

[0051] Furthermore, a transistor switch 37D is provided between the data line DL and the column control unit 23, and a transistor switch 37S is provided at the ground end of the source line SL. The transistor switches 37D and 37S are controlled by a control signal output from the inverter 352C. When the control signal is on, a measurement signal is input to the measurement signal input terminal of the read determination circuit 25 via the column control unit 23, and the read determination circuit 25 compares the measurement signal with a reference signal, thereby performing information read processing.

[0052] Here, when attention is paid to the configuration of the high-voltage element region 31, level shifters 34D, 34S, 34C, and 34W must be used to adjust the levels of the data lines DL, source lines SL, word lines WL, and control lines CL. In the high-voltage element region 31, the voltage levels are increased by the level shifters 34D, 34S, 34C, and 34W, so high-voltage components must be used as semiconductor elements. On the other hand, low-voltage semiconductor elements may be used outside the high-voltage element region 31. In this way, the overall size and operating characteristics of the semiconductor memory device must be designed according to the arrangement of the level shifters 34.

[0053] 4 is a schematic diagram of a semiconductor memory device. The semiconductor memory device 41 includes a memory cell array 21, a row control unit 22, a column control unit 23, a write drive 24, a read determination circuit 25, a reference signal generation unit 26, and an input / output buffer 42. The input / output buffer 42 temporarily stores input / output data exchanged with a host controller that controls the entire semiconductor memory device 41. As described above, the row control unit 22 includes a row decoder and a word drive, and the column control unit 23 includes a column decoder and a column switch.

[0054] Here, the storage contents of the memory cell MC are read by determining whether the ferromagnetic element 12 of the memory cell MC is in a low resistance state or a high resistance state. However, when the resistance state is determined by measuring the resistance value of the ferromagnetic element 12, it is necessary to take into account the wiring parasitic resistance depending on the arrangement of the selected memory cell MC in the memory cell array 21.

[0055] 5 is a schematic circuit configuration diagram of the periphery of the read decision circuit 25. In this diagram, a memory cell MC1 in the first row located at the end closest to the read decision circuit 25 (near end) and a memory cell MCm in the mth row located at the end farthest from the read decision circuit 25 (far end) are shown as representative examples.

[0056] As shown by the thick arrow, when reading from the far-end memory cell MCm, a current flows from the read decision circuit 25 through the data line DL and the memory cell MCm to the ground part at the near end of the source line SL. That is, the resistance value R from the near end of the data line DL to the far-end memory cell MCm is DLm and the resistance value R from the near end of the source line SL to the memory cell MCm at the far end. SLm Tonowa "R DLm +R SLm " is the wiring parasitic resistance.

[0057] Here, when reading from the memory cell MCm, the measured resistance value R MCis calculated to determine whether the memory cell MC is in a high resistance state or a low resistance state. MC In addition to the resistance of the ferromagnetic element 12, the wiring parasitic resistance "R DL +R SL " is included.

[0058] Furthermore, when measuring the near-end memory cell MC1, the wiring parasitic resistance of the data line DL and the source line SL is zero. As such, since the magnitude of the wiring parasitic resistance varies depending on the arrangement of the memory cell MC, there is a risk that the resistance state of the memory cell MC cannot be determined appropriately.

[0059] 6 is a graph showing the relationship between the read current input to the read decision circuit 25 and the position of the selected memory cell MC in the current mode. This graph shows the current value I CELL and the distance from the read decision circuit 25 of the selected memory cell MC.

[0060] The horizontal axis represents the current value I CELL 5 is shown. The vertical axis indicates the distance from the read determination circuit 25 to the memory cell MC to be read. Note that on the vertical axis, the near end of FIG. 5 corresponds to the lower part, and the far end of FIG. 5 corresponds to the middle part. The upper part indicates the farthest end (farthest end) of the arrangement of memory cells MC that can theoretically be read.

[0061] In this graph, when the selected memory cell MC is in a high resistance state, the current value input to the read decision circuit 25 is I CELL1 The current value in the low resistance state is I CELL0 Since the current value is inversely proportional to the resistance value, the current value I CELL1 is the current value I in the low resistance state CELL0The further away from the read determination circuit 25 (the higher up in the figure), the larger the wiring parasitic resistance. Therefore, the current value I CELL1 and the current value I in the low resistance state CELL0 The greater the distance from the read determination circuit 25, the smaller the .lambda..times ...

[0062] Here, the read current value I CELL is the reference current I ref The resistance state of the memory cell MC is determined based on whether the reference current I ref is the current value I in the high resistance state CELL1 (Point A) and the current value I in the low resistance state CELL0 (point B). Similarly, at the far end, the reference current I ref is the current value I in the high resistance state CELL1 (Point C) and the current value I in the low resistance state CELL0 (Point D).

[0063] Also, the same reference current I ref When the resistance state of the memory cell MC is determined using the reference current I ref is the current value I in the high resistance state CELL1 and the current value I in the low resistance state CELL0 Therefore, the current value I CELL1 (Point A) is the theoretically readable current value I CELL0 If the memory cell MC is placed further away from the position thus determined (above point E), the current value I CELL0 is the current value I at the near end in the high resistance state CELL1 becomes smaller than the same reference current I ref It will no longer be possible to determine the resistance state using

[0064] And the same reference current I ref When determining the resistance state usingMC1 -R MC0 " is equal to "R DLf +R DSf " is the farthest point in the ideal state (theoretical farthest point). Also, the same reference current I ref When determining the resistance state using DLf +R DSf " is the parasitic resistance of the wiring at the farthest end that can be logically designed.

[0065] Furthermore, in order to stably read the memory cell MC, the wiring parasitic resistance "R DL +R SL " is the measured resistance value R MC The difference between the high resistance state and the low resistance state of MC1 -R MC0 " is desirable. Therefore, "(R MC1 -R MC0 ) / 2=R DLm +R SLm " is defined as the far end where the memory cell MC can be placed. Note that the wiring parasitic resistance at the near end can be considered to be zero, so "R DL1 +R SL1 =0".

[0066] where the reference current I ref The upper and lower limits of the current I CELL1 (Point A) and the current value I in the low resistance state CELL0 (Point B) and the reference current I ref must exist between points A and B. In addition, in the memory cell located at the far end, the current value I CELL1 (Point C) and the current value I in the low resistance state CELL0 (Point D) and the reference current I ref must lie between points C and D.

[0067] Therefore, in order to determine the resistance state of the memory cells MC arranged in parallel from the near end to the far end, the upper limit reference current I ref_max is determined by point D, and the lower limit reference current I ref_minis determined by point A. And the upper limit reference current I ref_max and the lower limit reference current I ref_min The intermediate value between these is used as the reference current I ref It is defined as follows.

[0068] This results in a reference current I ref is the current value I CELL1 and the current value I in the low resistance state CELL0 By being positioned between the reference current I ref and the current value I in the high resistance state CELL1 and the current value I in the low resistance state CELL0 The difference between this and the specified value ("I ref_max -I ref " or "I ref -I ref_min This makes it possible to improve the accuracy in determining the resistance state of the memory cell MC.

[0069] The reference current I ref If we consider the case where the memory cells MC are arranged beyond the far end to the farthest end using the reference current I, the result is as follows: ref and the current value I in the low resistance state CELL0 However, for memory cells MC located beyond point F, the resistance state can be determined based on the reference current I ref is the current value I CELL1 and the current value I in the low resistance state CELL0 , the resistance state cannot be determined.

[0070] 7 is a graph showing the relationship between the read voltage and the position of the selected memory cell MC in the voltage mode. This graph corresponds to the graph shown in FIG. 6 and shows an example in which the read decision circuit 25 reads a voltage value instead of a current value. The horizontal axis represents the current value I CELL Instead, the voltage value V of the data line DL input to the read decision circuit 25 is DLThe reference signal used in the read decision circuit 25 is a reference voltage V ref is.

[0071] As shown in this figure, the voltage V DL is a value that depends on the resistance value, so overall, the voltage value V in the high resistance state is DL1 is the voltage value in the low resistance state, V DL0 Furthermore, the greater the distance from the read determination circuit 25, the greater the wiring parasitic resistance, and the greater the voltage value V DL1 and the voltage value V in the low resistance state DL0 becomes larger.

[0072] Similarly, the reference voltage V ref The upper and lower limits of the voltage V DL1 (Point A) and the voltage value V in the low resistance state DL0 (Point B) and the reference voltage V ref must exist between points A and B. In addition, in the memory cell MC located at the far end, the voltage value V DL1 (Point C) and the voltage value V in the low resistance state DL0 (Point D) and the reference voltage V ref must lie between points C and D.

[0073] Therefore, in order to determine the resistance state of the memory cells MC arranged in parallel from the near end to the far end, the upper limit reference voltage V ref_max is determined by point A, and the lower limit reference voltage V ref_min is determined by point D. Also, the upper limit reference voltage V ref_max and the lower limit reference voltage V ref_min The intermediate value between these is the reference voltage V ref It is used as.

[0074] If we consider the case where the memory cells MC are arranged beyond the far end to the farthest end, the following will be considered. ref and the voltage value V in the high resistance state DL0The resistance state of memory cells MC located within a distance determined by the intersection point F with the reference voltage V ref is the voltage value V DL1 and the voltage value V in the low resistance state DL0 Since the resistance is below 0.01, the resistance state cannot be determined.

[0075] The above is a description of the read process of the memory cell MC in the comparative example. According to the embodiment of the present invention described below, a reference signal correction unit is provided to reduce the influence of the wiring parasitic resistance of the data line DL and the source line SL. This makes it possible to determine the resistance state of the memory cell MC located farther from the read determination circuit 25.

[0076] (First embodiment) In the comparative example, as shown in FIGS. 6 and 7, memory cells MC can only be arranged up to the far end of the middle row, and cannot be arranged up to the farthest end of the upper row. In the first embodiment, by providing a reference signal correction unit, memory cells MC can be arranged up to the farthest end of the upper row in the comparative example. Note that the semiconductor memory device according to this embodiment has a basic configuration substantially equivalent to that of the semiconductor memory device 41 described in the comparative example, and therefore, the following description will be made assuming that the semiconductor memory device 41 shown in FIG. 4 is the semiconductor memory device 41 according to this embodiment, focusing mainly on the circuit configuration around the read determination circuit 25 provided in the semiconductor memory device 41.

[0077] FIG. 8 is a schematic circuit diagram of the periphery of the read determination circuit 25 in the semiconductor memory device 41 according to the first embodiment. This diagram shows a variable resistance unit 81, which is a reference signal correction unit, in addition to the configuration of the comparative example shown in FIG. 5. As will be described later, since memory cells MC can be arranged up to the farthest end in the comparative example shown in FIG. 7, the farthest end in this embodiment corresponds to the farthest end in the comparative example. The illustrated example operates in voltage mode. That is, the read determination circuit 25 outputs a high-level / low-level voltage value depending on the magnitude relationship of the input voltages input from the two input terminals.

[0078] When the variable resistance unit 81 receives position information (selection position information) L of the selected memory cell MC, it changes its resistance value according to the position of the selected memory cell MC indicated in the selection position information L. The selection position information L is, for example, information indicating the word line WL. The resistance value of the variable resistance unit 81 changes so as to increase as the distance from the read determination circuit 25 to the selected memory cell MC increases. The selection position information L is, for example, an address signal of the word line WL used to control the row control unit 22.

[0079] Note that all or part of the components other than the memory cells, i.e., the row control unit 22, the read determination circuit 25, the reference signal generation unit 26, the variable resistance unit 81, and other control-related components, may be realized by a single control device 82. Note that the control device 82 may include, for example, a general-purpose microcomputer equipped with a CPU (Central Processing Unit), memory, and input / output units, and may be realized by controlling the electronic components such as the read determination circuit 25 and the variable resistance unit 81. In order to make the microcomputer function as a controller for the electronic components, a computer program (control program) is installed in and executed by the microcomputer. As a result, the general-purpose microcomputer functions as a controller that executes a predetermined program in the control device 82.

[0080] 9 is a graph showing the relationship between the read current input to the read determination circuit 25 and the position of the selected memory cell MC, and corresponds to FIG. 6 of the comparative example. In this figure, the position shown as the farthest end in the upper part of FIG. 6 is shown as the far end. This is because in this embodiment, the memory cell MC can be read at that position.

[0081] As shown in this figure, the reference current I ref is the current value I in the high resistance state CELL1 and the current value I in the low resistance state CELL0 The magnitude of the reference current I changes depending on the distance from the read decision circuit 25 so that it is an intermediate value between refThis is because the resistance value of the variable resistance section 81 changes so that

[0082] Thus, the reference current I ref By setting ref is the current value I in the high resistance state CELL1 (Point G) and the current value I in the low resistance state CELL0 (point E). Therefore, the read current value I CELL and the reference current I ref By comparing the resistance state of the memory cell MC with the resistance state of the memory cell MC, the resistance state of the memory cell MC can be determined.

[0083] As a result, the memory cells MC can be arranged farther from the read decision circuit 25, so that the wiring parasitic resistance (R DL ) and the wiring parasitic resistance of the source line SL (R SL 6 (corresponding to the far end in FIG. 9), where memory cells MC could not be arranged in the comparative example, can be arranged, and the area of ​​the memory cell array can be increased.

[0084] Furthermore, the reference current I ref However, the current value I CELL1 and the current value I in the low resistance state CELL0 By being positioned between the reference current I ref and the current value I in the high resistance state CELL1 and the current value I in the low resistance state CELL0 This makes it possible to improve the accuracy in determining the resistance state of the memory cell MC.

[0085] In this embodiment, the read determination circuit 25 operates in a current mode to determine the magnitude relationship between the output current from the memory cell MC and the reference current in order to determine the resistance state of the memory cell MC. Specifically, as the read determination circuit 25, a read determination circuit 25 including a current comparison circuit 251 as shown in FIG. 2B and a two-stage read determination circuit 25 as shown in FIG. 2D have been described. In such a configuration, the value of the reference current input to the read determination circuit 25 is changed by the variable resistance unit 81.

[0086] The read determination circuit 25 may operate in a voltage mode to determine the magnitude relationship between the output voltage from the memory cell MC and a reference voltage in order to determine the resistance state of the memory cell MC. Specifically, the read determination circuit 25 may be a read determination circuit 25 including a voltage comparison circuit 253 as shown in FIG. 2C, or a three-stage read determination circuit 25 as shown in FIG. 2E. In such a configuration, the reference voltage input to the read determination circuit 25 is changed.

[0087] In the current mode, the variable resistance unit 81 may be disposed inside the read determination circuit 25, thereby being configured as one unit with the read determination circuit 25. That is, in the example of FIG. 2B, it may be configured as one unit with the current comparison circuit 251, and in the example of FIG. 2D, it may be configured as one unit with the current comparison circuit 253 connected to the input terminal. In the voltage mode, the configuration for changing the reference voltage input to the read determination circuit 25 may be configured as one unit with the voltage comparison circuit 252 in the example of FIG. 2C, and may be configured as one unit with the voltage comparison circuit 255 connected to the input terminal in the example of FIG. 2E.

[0088] (Second embodiment) 8, in the first embodiment, an address signal indicating the position of the word line WD was used as the selection position information L used to control the variable resistance unit 81. However, in order to use this address signal, a configuration including an address bus equivalent to the word drive of the row control unit 22 is required as a source of the selection position information L, which increases the wiring and circuit scale. Therefore, in the second embodiment, the memory cell array 21 is divided into multiple regions, and the resistance value of the variable resistance unit 81 is switched in stages depending on the region containing the selected memory cell MC, thereby simplifying the source of the selection position information L and the configuration of the variable resistance unit 81.

[0089] 10 is a schematic circuit diagram of the periphery of the read determination circuit 25 in the second embodiment. According to this diagram, the memory cell array 21 is divided into four regions, and the resistance value of the variable resistance unit 81 is changed depending on the region in which the selected memory cell MC exists. The method of selecting the region will be explained using FIGS. 11 and 12, and the configuration of the variable resistance unit 81 will be explained using FIG. 13.

[0090] In this example, 2048 memory cells MC are arranged in a row in the memory cell array 21, and word lines WL (WL0 to WL2047) are provided to connect to the respective memory cells MC. The numbers assigned to the word lines WL increase from the near end to the far end.

[0091] The arrangement area of ​​the memory cells MC is divided in the column direction into four areas 101 to 104. The first area 101 includes word lines WL0 to WL511, the second area 102 includes word lines WL512 to WL1023, the third area 103 includes word lines WL1024 to WL1535, and the fourth area 104 includes word lines WL1536 to WL2047.

[0092] The wiring parasitic resistance of the data line DL and the source line SL is expressed as "R DL / 4" and "R SL / 4". Note that a109[0] to a109[3] shown corresponding to the areas 101 to 104 are address buses used to select the areas 101 to 104, and details will be explained using FIG. 11 and FIG. 12.

[0093] When a memory cell MC is selected, the row control unit 22 (not shown in FIG. 10) determines the word line WL connected to the selected memory cell MC, which is uniquely determined based on the corresponding address input signal, and applies a voltage from the word drive corresponding to the word line WL. Such a series of processes by the row decoder is called a decoding process.

[0094] In this embodiment, a part of a signal (pre-decode signal) generated in the decoding process is used as a signal for selecting one of the regions 101 to 104. In detail, a part of information (pre-decode signal) from a circuit obtained by hierarchically dividing the decoding process is used as selection position information L to control the resistance value of the variable resistance unit 81. The process using such a pre-decode signal will be described below with reference to FIGS. 11 to 13.

[0095] 11 shows the logic circuit of the row decoder. In the row decoder 111, the word line WL connected to the selected memory cell MC is determined according to the input value from the address bus a0 to a10 of the upper control unit. In this figure, the upper control unit is provided with complementary address signals a0b to a10b in addition to the address bus a0 to a10, but the operation of the complementary address signals a0b to a10b will not be described below.

[0096] The row decoder 111 outputs all combinations (2) of address signals a0 to a10 having two values, high level (H) and low level (L). 11 ) is a circuit that generates a signal that uniquely selects one word line from 2048. This circuit is divided into two layers that include AND operators 112 to 116.

[0097] Eight three-input AND operators 112 are required in the first layer to handle all combinations (2x2x2) of input addresses a0 / a0b to a2 / a2b, and eight output signals are required. Operators 113 and 114 have a similar configuration. Four two-input AND operators 115 handle all combinations (2x2) of input addresses a9 / a9b to a10 / a10b, and four output signals are required.

[0098] The number of the 4-input AND operators 116 in the second layer is 2048, due to all combinations of input signals (8x8x8x4). This decoding process makes it possible to uniquely select a word line.

[0099] Here, a109 (pre-decode signal) output from the calculator 115 is used to control the variable resistor unit 81 as selected position information L. The parameter a109 (pre-decode signal) output from the calculator 115 satisfies the relationship shown in FIG.

[0100] 12 is a logical correspondence table showing the relationship between the regions 101 to 104 in which the selected word line WL is arranged and the input / output of the row decoder 111. This table shows the logical relationship between the address bus on the input side of the row decoder 111 and the selected word line WL. Note that one of the regions 101 to 104 is selected using four signals a109[0]-[3] output from the logical AND operator 115.

[0101] When the fourth region 104 is selected, a10 and a9 become high level at the inputs of the AND operator 115. Note that a8-a0 become levels indicating the arrangement of the selected memory cell MC in the fourth region 104. In such a case, in a109 output from the AND operator 115, a109[3] becomes high level and the others (a109[0]-a109[3]) become low level.

[0102] When the third region 103 is selected, a10 is at high level and a9 is at low level at the input of the AND operator 115. In this case, a109[2] is at high level and the others (a109[0], a109[1] and a109[3]) are at low level.

[0103] When the second region 102 is selected, a10 is at low level and a9 is at high level at the input of the AND operator 115. In this case, a109[1] is at high level and the others (a109[0], a109[2], and a109[3]) are at low level.

[0104] When the first region 101 is selected, a10 and a9 are at low levels at the inputs of the AND operator 115. In this case, a109[0] is at high level, and the others (a109[1]-a109[3]) are at low level.

[0105] In this way, the 4-bit information a109[0] to [3] output from the AND operator 115 corresponds to the areas 101 to 104. Therefore, the variable resistance unit 81 receives a109[0] to [3] as selected position information L, and the resistance value of the variable resistance unit 81 is controlled according to the selected position information L.

[0106] 13 is a detailed circuit diagram of the variable resistor unit 81. According to this diagram, four resistor elements 131 to 134 are connected in series, and switches 135 to 138 are provided in parallel with the resistor elements 131 to 134, respectively. STEP is the data line parasitic resistance R DL and the source line parasitic resistance R SL The sum of (R DL +R SL ) / 4".

[0107] Here, switches 135 to 138 are processed according to the 4-bit information included in a109 output from AND operator 115. In particular, when a109[0] is at a high level, switches 135 to 138 are turned on. When a109[1] is at a high level, switches 136 to 138 are turned on and switch 135 is turned off. When a109[2] is at a high level, switches 137 and 138 are turned on and switches 135 and 136 are turned off. When a109[3] is at a high level, switch 138 is turned on and switches 135 to 137 are turned off.

[0108] When a109[0] is at a high level, that is, when the selected memory cell MC is included in the first region 101, the switches 135 to 138 are turned on. In this case, the reference signal is input to the read determination circuit 25 without passing through the resistance elements 131 to 134. Therefore, the overall resistance value of the variable resistance unit 81 becomes zero.

[0109] When a109[1] is at a high level, that is, when the selected memory cell MC is included in the second region 102, the switches 136 to 138 are turned on. In this case, the reference signal passes through the resistance element 131 without passing through the resistance elements 132 to 134, and is input to the read determination circuit 25. Therefore, the overall resistance value of the variable resistance unit 81 is "R STEP "

[0110] When a109[2] is at a high level, that is, when the selected memory cell MC is included in the third region 103, the switches 137 and 138 are turned on. In this case, the reference signal passes through the resistance elements 131 and 132 without passing through the resistance elements 133 and 134, and is input to the read determination circuit 25. Therefore, the total resistance value of the variable resistance unit 81 is "2R STEP "

[0111] When a109[3] is at a high level, that is, when the selected memory cell MC is included in the fourth region 104, the switch 138 is turned on. In this case, the reference signal passes through the resistance elements 131 to 133 without passing through the resistance element 134, and is input to the read determination circuit 25. Therefore, the total resistance value of the variable resistance unit 81 is "3R STEP "

[0112] Here, the larger the resistance value of the variable resistor 81, the larger the reference current I ref is small, and the reference voltage V ref Therefore, when the selected memory cell MC is located in the first region 101, the resistance value is large and the reference current I ref is small, and the reference voltage V ref When the selected memory cell MC is located in the fourth region 104, the resistance value is small and the reference current I ref is large, and the reference voltage V ref becomes smaller.

[0113] Furthermore, the selection position information L received by the variable resistance unit 81 is not 2048 different values ​​for word lines WL0 to WL2047 as in the first embodiment, but four different values ​​a109[0] to [3], and the resistance value of the variable resistance unit 81 is controlled in four stages. This reduces the amount of address bus information used to control the variable resistance unit 81, allowing for a simplification of the configuration of the variable resistance unit 81 and its peripheral circuits.

[0114] The variable resistance section 81 is not limited to a configuration in which multiple resistance elements 131 to 134 are connected in series as shown in this figure, but may also be configured with resistance elements that can achieve equivalent resistance changes or with a circuit that can perform equivalent correction to a reference signal.

[0115] FIG. 14 is a graph showing the relationship between the read current input to the read determination circuit 25 and the position of the selected memory cell MC in the current mode, and corresponds to FIG. 6 of the comparative example and FIG. 9 of the first embodiment.

[0116] When the selected memory cell MC is included in one of the regions 101 to 104, the reference current I ref Furthermore, the reference current I ref decreases in the order of the first region 101, the second region 102, the third region 103, and the fourth region 104. This is because when the selected memory cell MC is included in the first region 101, the resistance value of the variable resistance unit 81 is small, and when the selected memory cell MC is included in the fourth region 104, the resistance value of the variable resistance unit 81 is large.

[0117] In this way, the pre-decoded signal output from the AND logic unit 115 of the row decoder 111 is used as the selection position information L indicating the area including the selected memory cell MC, and the reference current I ref The reference current I ref In any of the first to fourth regions 101 to 104, the current value I CELL1 and the current value I in the low resistance state CELL0 Therefore, the read current value I CELL and the reference current I ref By comparing it with the resistance state of the memory cell MC, the resistance state of the memory cell MC can be determined.

[0118] 15 is a graph showing the relationship between the read voltage input to the read decision circuit 25 and the position of the selected memory cell MC in the voltage mode, and corresponds to FIG. 7 of the comparative example. It also corresponds to FIG. 14 showing the read current described above, and since the read decision circuit 25 reads out a voltage value instead of a current value, the horizontal axis shows the voltage value V DL is shown.

[0119] When the selected memory cell MC is included in any one of the regions 101 to 104, the reference voltage V ref Furthermore, the reference voltage V refincreases in the order of the first region 101, the second region 102, the third region 103, and the fourth region 104. This is because when the selected memory cell MC is included in the first region 101, the resistance value of the variable resistance unit 81 is small, and when the selected memory cell MC is included in the fourth region 104, the resistance value of the variable resistance unit 81 is large.

[0120] In this way, the pre-decoded signal output from the AND operator 115 of the row decoder 111 is used as the selection position information L indicating the area including the selected memory cell MC, and is input to the reference voltage V ref The reference voltage V ref In any of the first to fourth regions 101 to 104, the voltage value V DL1 and the voltage value V in the low resistance state DL0 Therefore, the read voltage value V DL and the reference voltage V ref By comparing it with the resistance state of the memory cell MC, the resistance state of the memory cell MC can be determined.

[0121] In this embodiment, the variable resistance unit 81 corrects the level of the reference signal using a109[0] to [3] a109, which are pre-decoded signals in the row decoder 111. In the first embodiment, an example was described in which the resistance value of the variable resistance unit 81 is controlled using an address signal connected to the address bus on the input side of the row decoder 111, but this is not limitative. In this embodiment, it is also possible to use a decoded signal indicating the word lines (WL0 to WL2047) output from the logical AND operator 116 shown in FIG.

[0122] (Third embodiment) In the third embodiment, a case where a memory cell array is configured from a plurality of subarrays will be described. Note that configuring a memory cell array from a plurality of subarrays is sometimes called a subarray system.

[0123] 16 is a diagram showing the overall configuration of a sub-array type memory cell array according to the third embodiment. In this diagram, the column control unit 23, write drive 24, read determination circuit 25, reference signal generation unit 26, and input / output buffer 42 on the right side of the diagram are the same as those shown in FIGS. 2A and 4, and therefore their description will be omitted. A variable resistance unit 81 is provided together with the reference signal generation unit 26.

[0124] The memory cell array 161 includes four subarrays 162A to 162D. Each of the subarrays 162A to 162D is composed of a plurality of memory cells MC arranged two-dimensionally. The memory cells MC are connected to local data lines LDL and local source lines LSL in the column direction and to word lines WL in the row direction. Row control units 163A to 163D are provided in the subarrays 162A to 162D, respectively, and the word lines WL are selected by the row control units 163A to 163D in any of the subarrays 162A to 162D.

[0125] In the column direction, the subarrays 162A and 162B are arranged in pairs via a hierarchical switch 164A, and the subarrays 162C and 162D are arranged in pairs via a hierarchical switch 164B. The column control unit 23 and the hierarchical switches 164A and 164B are connected via a global data line GDL and a global source line GSL.

[0126] The hierarchical switch 164A controls the connection between the global data line GDL and the local data line LDL of the subarray 162A or 162B, and the connection between the global source line GSL and the local source line LSL of the subarray 162A or 162B. Similarly, the hierarchical switch 164B controls the connection between the global data line GDL and the local data line LDL of the subarray 162C or 162D, and the connection between the global source line GSL and the local source line LSL of the subarray 162C or 162D.

[0127] By controlling the hierarchical switches 164A and 164B, the connection between the global data line GDL and the local data line LDL of one of the subarrays 162A to 162D, and the connection between the global source line GSL and the local source line LSL of one of the subarrays 162A to 162D are controlled.

[0128] In this way, the subarray 162 including the selected memory cell MC is selected by connecting the global data line GDL and the global source line GSL to the local data line LDL and the local source line LSL of any of the subarrays 162A to 162D. Then, the row control unit 163 provided adjacent to the subarray 162 connected by the hierarchical switches 164A and 164B applies a voltage to a predetermined word line WL to select the memory cell MC.

[0129] The multiple subarrays 162 may be stacked in the height direction to form a hierarchical structure. For example, subarrays 162A and 162B, and subarrays 162C and 162D may be stacked. By using a hierarchical structure, the wiring lengths of the global data lines GDL and global source lines GSL can be shortened, and wiring parasitic resistance can be reduced.

[0130] 17 is a circuit diagram of the memory cell array 161 shown in FIG. 16. Here, in the global data lines GDL arranged in the column direction, the resistance value of the wiring parasitic resistance of the line arranged in the column direction in each of the subarrays 162A to 162D is R GDL The resistance value of the wiring parasitic resistance of the local data lines LDL and the local source lines LSL provided in the subarrays 162A to 162D is R LDL and R LSL It is assumed that

[0131] The hierarchical switch 164A is configured to be connectable to an intermediate point of the global data line GDL and to the ends of the local data lines LDL of the subarrays 162A and 162B that face the hierarchical switch 164A (the left end of the subarray 162A in the figure and the right end of the subarray 162B in the figure). The intermediate point of the global data line GDL connected to the hierarchical switch 164A is located between the subarrays 162A and 162B.

[0132] Similarly, the hierarchical switch 164B is configured to be connectable to the end of the global data line GDL on the side where the read determination circuit 25 is not provided (the left end in the figure) and the ends of the local data lines LDL of the subarrays 162C and 162D that face the hierarchical switch 164B (the left end in the figure of the subarray 162C and the right end in the figure of the subarray 162D).

[0133] In this diagram, a memory cell MC in subarray 162A is selected, so that hierarchical switch 164A is connected to subarray 162A, and hierarchical switch 164B is not connected to either subarray 162C or 162D.

[0134] The resistance value of the wiring parasitic resistance of the global data line GDL is determined according to the wiring distance from the read decision circuit 25 to the hierarchical switches 164A and 164B. Therefore, in the global data line GDL, the resistance value of the wiring parasitic resistance between the read decision circuit 25 and the hierarchical switch 164A is R GDL The resistance value of the wiring parasitic resistance between the hierarchical switches 164A and 164B is 2R GDL is.

[0135] In the subarrays 162A to 162D, a plurality of memory cells MC are arranged in parallel between a local data line LDL and a local source line LSL, which is grounded on the side where the hierarchical switches 164A and 164B are provided.

[0136] Here, for the subarray 162A, of the region Xm formed by dividing the array length in half, the side connected to the hierarchical switch 164A will be referred to as region Xm000, and the opposite side will be referred to as region Xm001. Similarly, for the subarray 162B, the side connected to the hierarchical switch 164A will be referred to as region Xm010, and the opposite side will be referred to as region Xm011. For the subarray 162C, the side connected to the hierarchical switch 164B will be referred to as region Xm100, and the opposite side will be referred to as Xm101. For the subarray 162D, the side connected to the hierarchical switch 164B will be referred to as region Xm110, and the opposite side will be referred to as region Xm111.

[0137] The wiring parasitic resistance according to the selected position of the memory cell MC in the subarrays 162A to 162D is as follows: When the selected memory cell MC is included in the subarray 162A, the wiring parasitic resistance decreases as the selected position of the memory cell MC approaches the end (left end) connected to the hierarchical switch 164A in the region Xm000. The wiring parasitic resistance increases as the selected position approaches the end (right end) not connected to the hierarchical switch 164A in the region Xm001.

[0138] Similarly, in the subarray 162B, the closer the selected position of the memory cell MC is to the end (right end) connected to the hierarchical switch 164A in the region Xm010, the smaller the wiring parasitic resistance.The closer the selected position is to the end (left end) not connected to the hierarchical switch 164A in the region Xm011, the larger the wiring parasitic resistance.

[0139] In subarray 162C, the closer the selected position of memory cell MC is to the connection end (left end) with hierarchical switch 164B in region Xm100, the smaller the wiring parasitic resistance, and the closer the selected position is to the end (right end) on the side not connected to hierarchical switch 164B in region Xm101, the larger the wiring parasitic resistance. In subarray 162D, the closer the selected position of memory cell MC is to the connection end (right end) with hierarchical switch 164B in region Xm110, the smaller the wiring parasitic resistance, and the closer the selected position is to the end (left end) on the side not connected to hierarchical switch 164B in region Xm111, the larger the wiring parasitic resistance.

[0140] In other words, the distance from the read decision circuit 25 of the memory cell MC selected based on the wiring parasitic resistance is not the distance due to the physical placement position, but the distance of the current path to ground. Considering the far end and near end, the following can be obtained: The connection end of the region Xm000 of the subarray 162A with the hierarchical switch 164A and the connection end of the region Xm010 of the subarray 162B with the hierarchical switch 164A are near ends. On the other hand, the end of the region Xm101 of the subarray 162C that is not connected to the hierarchical switch 164B and the end of the region Xm111 of the subarray 162D that is not connected to the hierarchical switch 164B are far ends.

[0141] FIG. 18 is a graph showing the relationship between the read current input to the read determination circuit 25 and the position of the selected memory cell MC in the current mode, and corresponds to FIG. 6 of the comparative example, FIG. 9 of the first embodiment, and FIG. 14 of the second embodiment.

[0142] In this figure, the vertical axis indicates the positions at which memory cells MC are arranged, with subarrays 162A and 162B that are relatively close to the read decision circuit 25 shown at the bottom, and subarrays 162C and 162D that are relatively far from the read decision circuit 25 shown at the top.

[0143] The distance from the read determination circuit 25 increases in the following order from bottom to top in the figure: area Xm000 (subarray 162A) and area Xm010 (subarray 162B), area Xm001 (subarray 162A) and area Xm011 (subarray 162B), area Xm100 (subarray 162C) and area Xm110 (subarray 162D), and area Xm101 (subarray 162C) and area Xm111 (subarray 162D).

[0144] For simplicity of explanation, the configuration will be explained below using the subarrays 162A and 162C. The explanations for the subarrays 162A and 162C can be applied to the subarrays 162B and 162D, respectively.

[0145] As shown in this figure, in each of the subarrays 162A (areas Xm000, Xm001) and 162C (areas Xm100, Xm101), the longer the distance from the read decision circuit 25 (the higher up in the figure), the larger the wiring parasitic resistance. CELL1 and the current value I in the low resistance state CELL0 becomes smaller.

[0146] As shown in the middle of the figure, the current value I CELL1 and the current value I in the low resistance state CELL0 This is because, as shown in FIG. 17, when a memory cell MC is selected on the far end side of the region Xm001 (subarray 162A), the wiring parasitic resistance is "R GDL +R LDL +R LSL ", and the wiring parasitic resistance when the memory cell MC is selected on the near end side of the region Xm100 (subarray 162C) is "3R GDL " This is due to the fact that the parasitic resistances of the two wirings are not continuous.

[0147] In the example of Figure 18, LDL +R LSL >2R GDL ” (i.e., “R GDL +R LDL +R LSL >3R GDL ") holds, and when a memory cell MC is selected on the far end side of Xm001 (subarray 162A), the wiring parasitic resistance is larger than when a memory cell MC is selected on the near end side of Xm100 (subarray 162C). Therefore, the current value I CELL1 and the current value I in the low resistance state CELL0 In both cases, the far end side of Xm001 (subarray 162A) is smaller than the near end side of Xm100 (subarray 162C).

[0148] Even with this configuration, the resistance value of the variable resistance unit 81 is changed depending on which of the regions Xm000 to Xm111 the selected memory cell MC is located in, thereby controlling the reference current I ref The current value I in the high resistance state is changed. CELL1 and the current value I when in the low resistance state CELL0 The reference current I ref By making the reference current I ref changes in three levels (Xm000, Xm001 to Xm100, Xm101), and variable resistance section 81 is required to have at least three resistance sections.

[0149] 19 is a diagram showing the relationship between the read voltage and the memory cell selection position in the voltage mode in this embodiment, and corresponds to FIG. 7 of the comparative example and FIG. 15 of the second embodiment. Note that the current value I CELL was inversely proportional to the wiring parasitic resistance, but the voltage value V DL is proportional to the parasitic resistance of the wiring.

[0150] Therefore, when a memory cell MC is selected in the subarray 162A shown in the upper part of the figure, and when a memory cell MC is selected in the subarray 162C shown in the lower part of the figure, the longer the distance from the read decision circuit 25 (the higher up in the figure), the larger the wiring parasitic resistance becomes, and therefore the read voltage value V DL becomes larger.

[0151] When a memory cell MC is selected on the far end side of the region Xm001 (subarray 162A), the wiring parasitic resistance is larger than when a memory cell MC is selected on the near end side of the region Xm100 (subarray 162C). Therefore, the voltage value V DL becomes larger.

[0152] Fig. 20 is another diagram showing the relationship between the read current and the memory cell selection position in the current mode, and Fig. 21 is another diagram showing the relationship between the read voltage and the memory cell selection position in the voltage mode. Figs. 20 and 21 correspond to Figs. 18 and 19.

[0153] In the example shown in FIGS. 20 and 21, "R LDL +R LSL <2R GDL ” (i.e., “R GDL +R LDL +R LSL <3R GDL Therefore, as shown in the middle of the figure, when the memory cell MC is provided at the far end of the region Xm001 (subarray 162A), the wiring parasitic resistance is smaller than when the memory cell MC is provided at the near end of the region Xm100 (subarray 162C).

[0154] As a result, in FIG. 20, when a memory cell MC is selected on the far end side of the region Xm001 (subarray 162A), the wiring parasitic resistance is smaller than when a memory cell MC is selected on the near end side of the region Xm100 (subarray 162C), and therefore the read current value I CELL For the same reason, in FIG. 21, when a memory cell MC is selected at the far end of the region Xm001 (subarray 162A), the read voltage value V is larger than when a memory cell MC is selected at the near end of the region Xm100 (subarray 162C). DL is small.

[0155] As an example other than Figures 18 to 21, LDL +R LSL =2R GDL ” (i.e., “R GDL +R LDL +R LSL =3R GDL14 and 15, the case where the read current value I CELL and the read voltage value V DL is continuous.

[0156] In this way, the resistance value of the variable resistance unit 81 is changed stepwise depending on which of the regions Xm000 to Xm111 the selected memory cell MC is located in, thereby controlling the reference current I ref and voltage value V DL1 is corrected step by step. Then, the current value I CELL1 and the current value I when in the low resistance state CELL0 The reference current I ref If there exists a voltage V, the resistance state of the memory cell MC in any arrangement can be determined. DL1 and the voltage value V when in the low resistance state DL0 between the reference voltage V ref If there exists, the resistance state of memory cells MC in any arrangement can be determined.

[0157] Furthermore, the resistance value R of the local data line LDL LDL and R of the local source line LSL LSL The sum of "R LDL +R LSL " and "2R GDL ", the read current value I when the selected memory cell MC is included in the near-end subarray 162A and the far-end subarray 162C is calculated. CELL and read voltage value V DL The continuity with the

[0158] Therefore, the reference current I ref and reference voltage V ref If there is a limit to the setting value of RLDL +R LSL " and "2R GDL By changing the relationship between the current and the resistance, the current value I CELL1 and the current value I in the low resistance state CELL0 , and the voltage value V in the high resistance state DL1 and the voltage value V in the low resistance state DL0 By changing the characteristics of the resistance state of the memory cell MC, the resistance state of the memory cell MC can be determined.

[0159] (Fourth embodiment) In the first to third embodiments, the reference signal is corrected by changing the resistance value of the variable resistance unit 81 depending on the selected position of the selected memory cell MC, but this is not limiting. In the fourth embodiment, an example will be described in which the reference signal is corrected using a dummy cell that does not include a ferromagnetic element 12 as a variable resistance unit.

[0160] 22 is a schematic diagram of a dummy cell used in the fourth embodiment. Compared to the memory cell MC shown in FIG. 1, the dummy cell DC does not have a ferromagnetic element 12, and the data line DL and the drain (D) of the transistor 11 are directly connected. Therefore, when the transistor 11 is on, the dummy cell DC is conductive between the data line DL and the source line SL, and the resistance value is zero.

[0161] 23 is an explanatory diagram of a read operation of a memory cell MC when a dummy cell DC is used. According to this diagram, a dummy cell DC is provided in addition to the memory cell MC connected to the data line DL and the source line SL. The dummy cell DC is connected to a dummy data line DDL and a dummy source line DSL. Furthermore, like the memory cell MC, a plurality of dummy cells DC are arranged in parallel in the column direction. These plurality of dummy cells DC operate as a variable resistance unit 231.

[0162] The read determination circuit 25 has an input terminal for a measurement signal connected to the data line DL of the memory cell MC, and an input terminal for a reference signal connected to the dummy data line DDL of the variable resistance unit 231. An end of the dummy source line DSL of the variable resistance unit 231 on the read determination circuit 25 side is connected to the reference signal generation unit 26. Therefore, the reference signal output from the reference signal generation unit 26 is input to the read determination circuit 25 via the variable resistance unit 231 (dummy source line DSL, dummy cell DC, and dummy data line DDL). Note that the connections of the dummy source line DSL and the dummy data line DDL may be reversed.

[0163] When a voltage is applied to a predetermined word line WL, the transistors 11 of the corresponding memory cells MC and dummy cells DC are turned on. In this case, the reference signal generated by the reference signal generator 26 is input to the other end of the read determination circuit 25 via the conductive dummy cells DC.

[0164] Since the selected memory cell MC and the conductive dummy cell DC are connected to the same word line WL, the wiring parasitic resistance of the data line DL and the source line SL that affects the measurement signal and the wiring parasitic resistance of the dummy data line DDL and the dummy source line DSL that affects the reference signal are both R DL and R SL In this way, the wiring parasitic resistances that affect the measurement signal and reference signal input to the read determination circuit 25 become approximately the same, and the influence of the wiring parasitic resistance on the comparison between the measurement signal and the reference signal can be suppressed.

[0165] 24 is an example of a circuit configuration diagram of a memory cell array when dummy cells DC are used. Memory cell array 241 is composed of subarrays 242A and 242B. Each of subarrays 242A and 242B includes two-dimensionally arranged memory cells MC, row control units 22A and 22B, column control units 23A and 23B, and read determination circuits 25A and 25B. Both subarrays 242A and 242B are provided with variable resistance units 231A and 231B, each of which is composed of dummy cells DC arranged in parallel in the column direction.

[0166] The reference signal generation unit 26 is connected to the dummy source lines DSLA and DSLB of the subarrays 242A and 242B. The dummy data lines DDLA and DDLB of the subarrays 242A and 242B are connected to the reference signal input terminals of the read determination circuits 25A and 25B, respectively.

[0167] When reading the memory cells MC in the subarray 242A, the row control unit 22A applies a voltage to a predetermined word line WL. This selects the predetermined memory cell MC and turns on the dummy cells DC in the same row as the selected memory cell MC. As a result, the wiring parasitic resistances of the measurement signal and the reference signal input to the read determination circuit 25A can be made approximately the same, thereby suppressing the influence of the wiring parasitic resistance on the determination of the resistance state. The same control is also applied when reading the memory cells MC in the subarray 242B.

[0168] Here, the method for determining the resistance state of the memory cell MC is to input a current value I CELL The current detection method is input, and the voltage value V DL and a voltage detection method in which a current is input. Generally, the current value is more susceptible to the arrangement of the variable resistance unit 231 than the voltage value. In the example of FIG. 24, variable resistance units 231A and 231B are provided in the subarrays 242A and 242B, respectively, and the selected memory cell MC and the dummy cell DC to be conducted are arranged in the same subarray 242. Therefore, even with the current detection method, the influence of wiring parasitic resistance on the determination of the resistance state can be suppressed. Also, different word lines can be read simultaneously for each subarray 242.

[0169] 25 is another example of a circuit configuration diagram of a memory cell array when dummy cells DC are used. Compared to the configuration shown in FIG. 24, the variable resistance unit 231A of the subarray 242A is deleted. Therefore, the dummy data line DDLB of the variable resistance unit 231B of the subarray 242B is further connected to the read determination circuit 25A of the subarray 242A.

[0170] The operation when reading the memory cells MC in the subarray 242B is the same as the operation in the example of FIG. 24. On the other hand, when reading the memory cells MC in the subarray 242A, the row control unit 21B of the subarray 242B applies a voltage to a predetermined word line WL to make a predetermined dummy cell DC in the variable resistance unit 231B conductive. This makes it possible to make the wiring parasitic resistance of the memory cell MC selected in the subarray 242A and the dummy cell DC made conductive in the subarray 242B equivalent. As a result, the wiring parasitic resistance of the measurement signal and the reference signal input to the read determination circuit 25A becomes approximately the same, thereby suppressing the influence of the wiring parasitic resistance on the determination of the resistance state.

[0171] As described above, current values ​​are less affected by the arrangement of the variable resistance unit 231 than voltage values, so by using a voltage detection method, the resistance state of the memory cell MC can be appropriately determined even in the configuration of Fig. 25. Furthermore, in the example of Fig. 25, it is not necessary to provide a variable resistance unit 231 for each subarray 242, and it is sufficient to provide one for each memory cell array 241, which simplifies the configuration of the memory cell array 241. However, the subarrays 242 must select word lines in the same position.

[0172] 22, the dummy cells DC may be configured with a transistor 11 different from the transistor 11 that is a switch element included in the memory cells MC. When compared with the configuration of the memory cells MC, such dummy cells DC do not include a ferromagnetic element 12. Therefore, as shown in FIGS. 24 and 25, by forming cells that do not include a ferromagnetic element 12 in a predetermined column in the memory cell array 241, it is possible to configure the dummy cells DC in that column.

[0173] (Fifth embodiment) In the third embodiment, an example was described in which a memory cell array is configured with a plurality of sub-configurations (sub-arrays) and a reference signal is corrected according to the arrangement of the sub-arrays, but this is not limiting. In the fifth embodiment, an example will be described in which each sub-configuration includes a correction unit that corrects a reference signal according to the arrangement of the sub-configuration.

[0174] 26 is a schematic diagram of a semiconductor memory device according to the fifth embodiment. According to this diagram, a semiconductor memory device 261 includes four submodules 262. The submodules 262 have substantially the same configuration as the semiconductor memory device 41 shown in FIG. 4, and instead of the reference signal generation unit 26, they include a reference signal correction unit 263 that has a function of correcting the reference signal according to the arrangement.

[0175] Each of the reference signal correction units 263 is connected to a reference signal generation unit 26 provided outside the sub-module 262. The reference signal correction unit 263 corrects the reference signal output from the reference signal generation unit 26 in accordance with the magnitude of the wiring parasitic resistance between the sub-module 262 and the reference signal generation unit 26.

[0176] With this configuration, the reference signal generation unit 26 is shared, and further, the reference signal output from the reference signal generation unit 26 is corrected by the reference signal correction unit 263 in each of the submodules 262. In detail, the reference signal correction unit 263 corrects the reference signal based on the arrangement position of the submodule 262 in the semiconductor memory device 261 and the wiring parasitic resistance between the submodule 262 and the reference signal generation unit 26.

[0177] In this way, by providing a reference signal correction unit 263 for each sub-module 262, the reference signal generation unit 26 only needs to transmit the same correction signal regardless of the arrangement position of the sub-module 262, thereby simplifying the overall configuration.

[0178] Furthermore, due to encryption of address signals, scrambling of physical layout, etc., the logical order of the decoded signals may not match the physical layout of the selected memory. However, by providing a reference signal correction unit 263 for each submodule 262, and the reference signal correction unit 263 having a decoding circuit used to decode the encrypted signal and a descrambling circuit, it is possible to correct the reference signal so that the logical order matches the physical layout.

[0179] Generally, in the semiconductor memory device 261, characteristic dependencies (PVT dependencies) that optimize process variations (P), voltage dependency (V), and temperature dependency (T) differ for each submodule 262 and each memory cell MC. The reference signal correction unit 263 provided for each submodule 262 performs correction based on these characteristic dependencies, thereby reducing the number of steps required for settings caused by the characteristic dependencies, checking the read operation range during correction setting tests, and checking the operation limits.

[0180] The above-described semiconductor memory devices 41 and 261 may be implemented on a semiconductor integrated circuit on which electronic circuits such as a CPU (Central Processing Unit) and an RF (Radio Frequency) circuit are implemented. In this case, the semiconductor memory devices 41 and 261 may be integrated together with other electronic circuits on a single semiconductor integrated circuit, or may be implemented later as a separate unit on an existing semiconductor integrated circuit on which other electronic circuits are provided. Similarly, the control device 82 provided in the semiconductor memory device may be implemented later as a separate unit on an existing semiconductor integrated circuit on which memory cells are provided.

[0181] The present invention allows various embodiments and modifications without departing from the broad spirit and scope of the present invention. Furthermore, the above-described embodiments are intended to explain the present invention and do not limit the scope of the present invention. That is, the scope of the present invention is defined by the claims, not the embodiments. Various modifications made within the scope of the claims and within the scope of the meaning of the invention equivalent thereto are considered to be within the scope of the present invention. [Explanation of symbols]

[0182] 11 Transistor 12 Ferromagnetic elements 21, 161, 241 memory cell array 25 Readout determination circuit 41, 261 Semiconductor memory device 81, 231 Variable resistor section (reference signal correction section) 263 Reference signal correction unit

Claims

1. a memory cell array having a plurality of memory cells each including a resistance change type memory element capable of storing a resistance state and a switch; a read determination circuit that compares a measurement signal from the memory cell selected in the memory cell array with a reference signal to determine a resistance state in order to read information from the resistance change type memory element; a reference signal correcting unit that corrects a level of the reference signal based on a selected position of the memory cell in the memory cell array; the memory cell array comprises a plurality of regions; the reference signal correcting unit corrects a level of the reference signal in accordance with a position of the region in which a selected memory cell exists; The reference signal correction unit A variable resistance unit is provided, The semiconductor memory device corrects the level of the reference signal by changing the resistance value of the variable resistor section based on the selected position of the memory cell.

2. A memory cell array having a plurality of memory cells each including a resistance change type memory element capable of storing a resistance state and a switch; a read determination circuit that compares a measurement signal from the memory cell selected in the memory cell array with a reference signal to determine a resistance state in order to read information from the resistance change type memory element; a reference signal correcting unit that corrects a level of the reference signal based on a selected position of the memory cell in the memory cell array; the memory cell array comprises a plurality of regions; the reference signal correcting unit corrects a level of the reference signal in accordance with a position of the region in which a selected memory cell exists; The reference signal correction unit A plurality of dummy cells whose conduction state can be switched are provided, The semiconductor memory device selects the dummy cell based on the selected position of the memory cell, and corrects the level of the reference signal by inputting the reference signal to the read determination circuit via the selected dummy cell.

3. 3. The semiconductor memory device according to claim 2, When the dummy cells are arranged along one of the word lines and the source lines, The reference signal correction unit corrects the level of the reference signal by bringing the selected memory cell and the dummy cell connected to the other of the word line and source line into a conductive state.

4. 4. The semiconductor memory device according to claim 3, The dummy cell is a switch different from the switch included in the memory cell.

5. The semiconductor memory device according to claim 1, wherein: The reference signal correction unit corrects the level of the reference signal so that it is between the measurement signal when the resistance change type memory element is in a high resistance state and the measurement signal when the resistance change type memory element is in a low resistance state.

6. 6. The semiconductor memory device according to claim 1, The selected position of the memory cell is a physical location of the selected memory cell within the memory cell array.

7. 7. The semiconductor memory device according to claim 6, The semiconductor memory device, wherein the selected position of the memory cell is indicated by at least one of an address signal, a pre-decode signal, and a decode signal used to select the memory cell.

8. A memory cell array having a plurality of memory cells each including a resistance change type memory element capable of storing a resistance state and a switch; a read determination circuit that compares a measurement signal from the memory cell selected in the memory cell array with a reference signal to determine a resistance state in order to read information from the resistance change type memory element; a reference signal correcting unit that corrects a level of the reference signal based on a selected position of the memory cell in the memory cell array; the selected location of the memory cell is a physical location of the selected memory cell within the memory cell array; In the memory cell array, the physical layout and logical layout of the memory cells do not match, The reference signal correction unit further converts the logical arrangement into the physical arrangement for the selected position of the memory cell, and corrects the level of the reference signal based on the physical arrangement obtained by the conversion.

9. 9. The semiconductor memory device according to claim 1, The semiconductor memory device, wherein the reference signal correction section further corrects the reference signal in accordance with individual differences of the memory cells.

10. 10. The semiconductor memory device according to claim 9, The individual differences include either voltage-dependent characteristics or temperature-dependent characteristics.

11. A memory cell array having a plurality of memory cells each including a resistance change type memory element capable of storing a resistance state and a switch; a read determination circuit that compares a measurement signal from the memory cell selected in the memory cell array with a reference signal to determine a resistance state in order to read information from the resistance change type memory element; a reference signal correcting unit that corrects a level of the reference signal based on a selected position of the memory cell in the memory cell array; the memory cell array is made up of a plurality of sub-modules, The reference signal correction unit a plurality of sub-modules are provided corresponding to the sub-modules, a semiconductor memory device that corrects the reference signal based on a selected position of the memory cell in the submodule and a positional relationship between the submodule and a generator of the reference signal provided outside the submodule;

12. 12. The semiconductor memory device according to claim 1, A semiconductor memory device implemented in a semiconductor integrated circuit.

13. A control device for a semiconductor memory device, comprising: a memory cell array having a plurality of memory cells each including a resistance change type memory element capable of storing a resistance state and a switch; and a read determination circuit that compares a measurement signal from a memory cell selected in the memory cell array with a reference signal, The control device correcting the level of the reference signal output from a reference signal generating unit based on the selected position of the memory cell in the memory cell array; causing the read determination circuit to compare the measurement signal from the memory cell selected in the memory cell array with the reference signal; determining a resistance state of the resistance change type storage element based on a comparison result by the read determination circuit; the memory cell array includes a plurality of regions, and a reference signal correcting unit corrects a level of the reference signal in accordance with a position of the region in which a selected memory cell is present; The control device for a semiconductor memory device, wherein the reference signal correction unit includes a variable resistance unit and corrects the level of the reference signal by changing a resistance value of the variable resistance unit based on a selected position of the memory cell.

14. A control device for a semiconductor memory device, comprising: a memory cell array having a plurality of memory cells each including a resistance change type memory element capable of storing a resistance state and a switch; and a read determination circuit for comparing a measurement signal from a memory cell selected in the memory cell array with a reference signal, The control device correcting the level of the reference signal output from a reference signal generating unit based on the selected position of the memory cell in the memory cell array; causing the read determination circuit to compare the measurement signal from the memory cell selected in the memory cell array with the reference signal; determining a resistance state of the resistance change type storage element based on a comparison result by the read determination circuit; the memory cell array includes a plurality of regions, and a reference signal correcting unit corrects a level of the reference signal in accordance with a position of the region in which a selected memory cell is present; The reference signal correction unit is a control device for a semiconductor memory device that has a plurality of dummy cells whose conduction state can be switched, selects the dummy cells based on the selected position of the memory cell, and corrects the level of the reference signal by inputting the reference signal to the read judgment circuit via the selected dummy cells.

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