Semiconductor memory device

Abstract

An embodiment of the present application provides a semiconductor storage device capable of reading out a plurality of pages of data at high speed. The semiconductor storage device (2) includes a memory cell array (110), a sequencer (41) that controls the operation of the memory cell array (110), and an input / output circuit (21) that receives a command. After the input / output circuit (21) receives a command (RD), the sequencer (41) switches the voltage of a word line (WL) in each sub-period corresponding to a page to be read out, thereby causing the data of the page corresponding to the sub-period to be determined. In each sub-period, the sequencer (41) switches the voltage of the word line (WL) in such a manner that the voltage passes through all voltages required for determining the data of the page corresponding to the sub-period, but does not switch the voltage of the word line (WL) to a voltage required for determining the data of a page different from the page corresponding to the sub-period.

Description

[0001] [Related Applications]

[0002] This application enjoys priority based on Japanese Patent Application No. 2021-116312 (filed on July 14, 2021). This application incorporates the entire contents of the basic application by reference to that basic application. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor memory device. Background Technology

[0004] Semiconductor memory devices such as NAND (Not And) flash memory have multiple memory cell transistors for storing data. The collection of one-bit data stored in multiple memory cell transistors is called a "page". In recent years, it has become common practice for each memory cell transistor to store data consisting of multiple bits. That is, data consisting of multiple pages is typically stored in the memory cell transistors. Summary of the Invention

[0005] According to the disclosed embodiments, a semiconductor memory device capable of reading multiple pages of data at high speed is provided.

[0006] The semiconductor memory device of the embodiment includes: a memory cell array having a plurality of memory cell transistors; word lines connected to the gates of the memory cell transistors; a control circuit for controlling the operation of the memory cell array; and an input circuit for receiving instructions. After receiving an instruction instructing the input circuit to continuously read multiple pages of data from the memory cell transistors, the control circuit switches the voltage of the word lines during a short period corresponding to the page to be read, thereby determining the data of the page corresponding to that short period. During each short period, the control circuit switches the voltage of the word lines in such a manner that all voltages are required to determine the data of the page corresponding to that short period are used, but does not switch the voltage of the word lines to the voltage required to determine the data of a page different from the page corresponding to that short period. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating a configuration example of the storage system according to the first embodiment.

[0008] Figure 2 This is a block diagram illustrating the configuration of the semiconductor memory device according to the first embodiment.

[0009] Figure 3 It is an equivalent circuit diagram representing the structure of a memory cell array.

[0010] Figure 4 It is a cross-sectional view showing the structure of a storage cell array.

[0011] Figure 5 This is a diagram showing the circuit configuration of the sensing amplification unit.

[0012] Figure 6 This is a diagram showing an example of the threshold distribution of transistors in a memory cell.

[0013] Figure 7 It is a graph showing the potential changes of each wiring during a write operation.

[0014] Figure 8 This is a graph showing the relationship between the number of loops during the write operation and the verification operation.

[0015] Figure 9 It is a graph showing the potential changes of each wiring during a write operation.

[0016] Figure 10 It is a graph showing the potential changes of the word line during a write operation.

[0017] Figure 11 It is a graph showing the potential changes of each wiring during the readout operation.

[0018] Figure 12 It is a diagram showing the potential changes of each wiring during the readout operation of the lower page.

[0019] Figure 13 (A) to (C) are diagrams showing the potential changes of each wiring during a normal read.

[0020] Figure 14 (A) to (D) are diagrams showing the potential changes of each wiring during cache read.

[0021] Figure 15 (A) to (D) are diagrams showing the potential changes of each wiring during sequential reads of the comparison examples.

[0022] Figure 16 (A) to (D) are diagrams showing the potential changes of each wiring during sequential reading of the comparison examples.

[0023] Figure 17 (A) to (F) are diagrams showing the potential changes of each wiring during sequential reading in the first embodiment.

[0024] Figure 18 (A)~ Figure 18 (D) is a graph used to illustrate the time required for the entire readout process.

[0025] Figure 19 (A) to (F) are diagrams showing the potential changes of each wiring during sequential reading in the second embodiment.

[0026] Figure 20 (A) to (F) are diagrams showing the potential changes of each wiring during sequential reading in the third embodiment.

[0027] Figure 21 (A) to (F) are diagrams showing the potential changes of each wiring during sequential reading in the fourth embodiment.

[0028] Figure 22 (A) to (F) are diagrams showing the potential changes of each wiring during sequential reading in the fifth embodiment.

[0029] Figure 23 (A) to (F) are diagrams showing the potential changes of each wiring during sequential reading in the variation example. Detailed Implementation

[0030] Hereinafter, this embodiment will be described with reference to the accompanying drawings. To facilitate understanding, the same symbols will be used to label the same components in each drawing as much as possible, and repeated descriptions will be omitted.

[0031] The first embodiment will be described. The semiconductor memory device 2 in this embodiment is a non-volatile memory device configured as a NAND flash memory. Figure 1 The diagram illustrates a configuration example of a memory system including a semiconductor memory device 2. This memory system includes a memory controller 1 and a semiconductor memory device 2. Furthermore, although the semiconductor memory device 2... Figure 1 The storage system actually has multiple [systems], but Figure 1 Only one of them is shown in the figure. The specific configuration of semiconductor memory device 2 will be described below. This memory system can be connected to a host device (not shown). The host device is, for example, an electronic device such as a personal computer or a mobile terminal.

[0032] The memory controller 1 controls the writing of data to the semiconductor memory device 2 according to write requests from the host. Additionally, the memory controller 1 controls the reading of data from the semiconductor memory device 2 according to read requests from the host.

[0033] The memory controller 1 and the semiconductor storage device 2 transmit and receive various signals, including chip enable signal / CE, ready-busy signal R / B, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signal / RE, RE, write protection signal / WP, data signal DQ<7:0>, data strobe signal DQS, and / DQS.

[0034] The chip enable signal / CE is used to enable semiconductor memory device 2. The ready-busy signal R / B is used to indicate whether semiconductor memory device 2 is in a ready or busy state. "Ready state" means it can accept commands from external sources. "Busy state" means it cannot accept commands from external sources. The instruction latch enable signal CLE indicates that the signal DQ<7:0> represents an instruction. The address latch enable signal ALE indicates that the signal DQ<7:0> represents an address. The write enable signal / WE is used to fetch the received signal to semiconductor memory device 2. In Single Data Rate (SDR) mode, the rising edge of the signal / WE indicates that the signal DQ<7:0>, which is to be sent to semiconductor memory device 2, will be fetched. In Double Data Rate (DDR) mode, the rising edge of the signal / WE indicates that the signal DQ<7:0>, which is to be sent to semiconductor memory device 2, will be fetched. Whenever an instruction, address, or data is received, the memory controller 1 will assert it.

[0035] The read enable signal / RE is used to enable the memory controller 1 to read data from the semiconductor memory device 2. Signal RE is the complementary signal to signal / RE. They are used, for example, to control the timing of the operation of the semiconductor memory device 2 when outputting signal DQ<7:0>. More specifically, in single data rate mode, the falling edge of signal / RE indicates the output of signal DQ<7:0> as data to the semiconductor memory device 2. Additionally, in double data rate mode, the falling and rising edges of signal / RE indicate the output of signal DQ<7:0> as data to the semiconductor memory device 2. The write protect signal / WP is used to instruct the semiconductor memory device 2 to prohibit data writing and deletion. Signal DQ<7:0> represents the data transmitted and received between the semiconductor memory device 2 and the memory controller 1, including instructions, addresses, and data. The data strobe signal DQS is used to control the input / output timing of signal DQ<7:0>. Signal / DQS is the complementary signal to signal DQS. More specifically, in double data rate mode, the falling and rising edges of the signal DQS indicate the signal DQ<7:0>, which is used as data, to be fetched into the semiconductor memory device 2. Furthermore, in double data rate mode, the signal DQS is generated based on the falling and rising edges of the signal / RE, and is output from the semiconductor memory device 2 along with the signal DQ<7:0>, which is used as data.

[0036] The memory controller 1 includes RAM (Random Access Memory) 11, a processor 12, a host interface 13, an ECC (Error Check and Correction) circuit 14, and a memory interface 15. The RAM 11, processor 12, host interface 13, ECC circuit 14, and memory interface 15 are interconnected via an internal bus 16.

[0037] The host interface 13 outputs requests received from the host, user data (write data), etc., to the internal bus 16. Additionally, the host interface 13 sends user data read from the semiconductor storage device 2, responses from the processor 12, etc., to the host.

[0038] The memory interface 15 controls, based on instructions from the processor 12, processes such as writing user data to the semiconductor storage device 2 and reading user data from the semiconductor storage device 2.

[0039] Processor 12 provides overall control of memory controller 1. Processor 12 may be, for example, a CPU (Central Processing Unit) or an MPU (Micro Processing Unit). Upon receiving a request from the host via host interface 13, processor 12 performs control according to that request. For example, processor 12, upon receiving a request from the host, instructs memory interface 15 to write user data and parity check codes to semiconductor storage device 2. Additionally, processor 12, upon receiving a request from the host, instructs memory interface 15 to read user data and parity check codes from semiconductor storage device 2.

[0040] Processor 12 determines the storage area (storage area) on semiconductor memory device 2 for user data stored in RAM 11. User data is stored in RAM 11 via internal bus 16. Processor 12 determines the storage area for data in page units (page data) as write units. User data stored in one page of semiconductor memory device 2 is hereinafter also referred to as "cell data". Cell data is generally encoded and stored in semiconductor memory device 2 in codeword form. In this embodiment, encoding is not mandatory. Memory controller 1 may also store cell data in semiconductor memory device 2 without encoding, but... Figure 1 The example shown is an encoding configuration. When the memory controller 1 does not perform encoding, the page data and the cell data are identical. Furthermore, a codeword can be generated based on a single cell data unit, or based on segmented data formed from cell data. Alternatively, a codeword can be generated using multiple cell data units.

[0041] Processor 12 determines the storage region of semiconductor memory device 2 as the write destination on a unit-by-unit basis. The storage regions of semiconductor memory device 2 are assigned physical addresses. Processor 12 uses physical addresses to manage the storage regions as write destinations for unit-by-unit data. Processor 12 specifies the determined storage region (physical address) and instructs memory interface 15 to write user data to semiconductor memory device 2. Processor 12 manages the correspondence between the logical address (the logical address managed by the host) of user data and its physical address. Upon receiving a read request containing a logical address from the host, processor 12 specifies the physical address corresponding to the logical address and instructs memory interface 15 to read the user data.

[0042] The ECC circuit 14 encodes the user data stored in RAM 11 to generate codewords. Additionally, the ECC circuit 14 decodes the codewords read from the semiconductor memory device 2. The ECC circuit 14 uses, for example, a checksum assigned to the user data to detect and correct errors in the data.

[0043] RAM11 temporarily stores user data received from the host until it needs to be stored in the semiconductor memory device 2, or temporarily stores data read from the semiconductor memory device 2 until it needs to be sent to the host. RAM11 is, for example, a general-purpose memory such as SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory).

[0044] Figure 1 The diagram shows an example configuration where the memory controller 1 includes an ECC circuit 14 and a memory interface 15. However, the ECC circuit 14 can also be integrated into the memory interface 15. Alternatively, the ECC circuit 14 can be integrated into the semiconductor memory device 2. Figure 1 The specific composition and configuration of the elements shown are not particularly limited.

[0045] In the event that a write request is received from the host Figure 1 The storage system operates as follows: Processor 12 temporarily stores the data to be written into RAM 11. Processor 12 reads the data stored in RAM 11 and inputs it into ECC circuit 14. ECC circuit 14 encodes the input data and inputs the codeword into memory interface 15. Memory interface 15 writes the input codeword into semiconductor memory device 2.

[0046] In the event that a read request is received from the host Figure 1The storage system operates as follows: The memory interface 15 inputs the codewords read from the semiconductor storage device 2 to the ECC circuit 14. The ECC circuit 14 decodes the input codewords and stores the decoded data in the RAM 11. The processor 12 sends the data stored in the RAM 11 to the host via the host interface 13.

[0047] Main reference Figure 2 The configuration of the semiconductor memory device 2 will be described below. As shown in the figure, the semiconductor memory device 2 includes two planes PL1 and PL2, an input / output circuit 21, a logic control circuit 22, a sequencer 41, a register 42, a voltage generation circuit 43, an input / output pad group 31, a logic control pad group 32, and a power input terminal group 33.

[0048] Surface PL1 includes a memory cell array 110, a sense amplifier 120, and a line decoder 130. Surface PL2 includes a memory cell array 210, a sense amplifier 220, and a line decoder 230. The configurations of surface PL1 and surface PL2 are identical. That is, the configurations of memory cell array 110 and 210 are identical, the configurations of sense amplifier 120 and 220 are identical, and the configurations of line decoder 130 and 230 are identical. The number of surfaces provided in the semiconductor memory device 2 can be two, one, or three or more, as shown in this embodiment.

[0049] Memory cell arrays 110 and 210 are the data storage portions. Each of memory cell arrays 110 and 210 contains multiple memory cell transistors associated with word lines and bit lines. Their specific configuration will be described below.

[0050] The input / output circuit 21 transmits and receives signals DQ<7:0> and data strobe signals DQS and / DQS with the memory controller 1. The input / output circuit 21 transmits the instructions and address contained in the signals DQ<7:0> to the register 42. Additionally, the input / output circuit 21 transmits and receives write data and read data with the sense amplifier 120 or sense amplifier 220. The input / output circuit 21 has two functions: receiving instructions from the memory controller 1 as an "input circuit" and outputting data to the memory controller 1 as an "output circuit." Alternatively, different circuit configurations for the input and output circuits can be used instead of the configuration described above.

[0051] The logic control circuit 22 receives the chip enable signal / CE, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signal RE, / RE, and write protect signal / WP from the memory controller 1. Additionally, the logic control circuit 22 transmits the ready-busy signal R / B to the memory controller 1, thus notifying the outside world of the status of the semiconductor memory device 2.

[0052] Both the input / output circuit 21 and the logic control circuit 22 are configured as circuits that can input and output signals with the memory controller 1. In other words, both the input / output circuit 21 and the logic control circuit 22 are provided as interface circuits for the semiconductor memory device 2.

[0053] The sequencer 41 controls the operation of various components, such as the memory controller 1, PL1, PL2, and voltage generation circuit 43, based on the control signals input from the memory controller 1 to the semiconductor memory device 2. The sequencer 41 is equivalent to a "control circuit" that controls the operation of the memory cell arrays 110, 210, etc. The sequencer 41 and the logic control circuit 22 can also be regarded as the "control circuit".

[0054] Register 42 is the part that temporarily stores instructions and addresses. Register 42 also stores status information indicating the status of planes PL1 and PL2 respectively. The status information is output as a status signal from input / output circuit 21 to memory controller 1 according to the request from memory controller 1.

[0055] The voltage generation circuit 43 generates the voltages required for write, read, and delete operations of data in the memory cell arrays 110 and 210, based on instructions from the sequencer 41. These voltages include, for example, the voltages VPGM, VPASS_PGM, and VPASS_READ applied to the word line WL, and the voltage applied to the bit line BL. The voltage generation circuit 43 can apply voltages individually to each word line WL and bit line BL, enabling planes PL1 and PL2 to operate in parallel.

[0056] The input / output pad group 31 is a part that has multiple terminals (pads) for transmitting and receiving signals between the memory controller 1 and the input / output circuit 21. Each terminal is individually configured to correspond to the signal DQ<7:0> and the data strobe signals DQS and / DQS respectively.

[0057] The logic control pad group 32 is a portion provided with multiple terminals (pads) for transmitting and receiving signals between the memory controller 1 and the logic control circuit 22. Each terminal is individually configured to correspond to the chip enable signal / CE, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signal RE, / RE, write protect signal / WP, and ready-busy signal R / B, respectively.

[0058] The power input terminal group 33 is a portion provided with multiple terminals for receiving the applied voltages required for the operation of the semiconductor memory device 2. The voltages applied to each terminal include the power supply voltages Vcc, VccQ, Vpp, and the ground voltage Vss.

[0059] The power supply voltage Vcc is the circuit power supply voltage provided externally as the operating power source, for example, a voltage of approximately 3.3V. The power supply voltage VccQ is, for example, a voltage of 1.2V. The power supply voltage VccQ is the voltage used when transmitting and receiving signals between the memory controller 1 and the semiconductor memory device 2. The power supply voltage Vpp is a power supply voltage higher than the power supply voltage Vcc, for example, a voltage of 12V.

[0060] Writing or deleting data to or from memory cell arrays 110 and 210 requires a voltage of approximately 20V (VPGM). In this case, boosting the approximately 12V power supply voltage Vpp via the boost circuit of voltage generation circuit 43, compared to boosting the approximately 3.3V power supply voltage Vcc, allows for faster and lower power consumption to generate the desired voltage. On the other hand, if the semiconductor memory device 2 is used in an environment where a high voltage cannot be supplied, then a voltage supply to the power supply voltage Vpp may not be required. Even without a power supply voltage Vpp, the semiconductor memory device 2 can perform various operations as long as it is supplied with the power supply voltage Vcc. In other words, the power supply voltage Vcc is the standard power supply required to be supplied to the semiconductor memory device 2, while the power supply voltage Vpp is an additional, arbitrary power supply supplied depending on, for example, the operating environment.

[0061] The configurations of surfaces PL1 and PL2 will be explained. Furthermore, as mentioned above, the configurations of surfaces PL1 and PL2 are identical. Therefore, only the configuration of surface PL1 will be explained below; illustrations and explanations regarding the configuration of surface PL2 will be omitted.

[0062] Figure 3 The configuration of the memory cell array 110 disposed on plane PL1 is shown in the form of an equivalent circuit diagram. The memory cell array 110 is composed of multiple blocks BLK, but... Figure 3 The diagram only shows one block BLK. The configuration of the other block BLKs in the storage cell array 110 is similar to... Figure 3 The structures shown are the same.

[0063] like Figure 3 As shown, a block BLK contains, for example, four serial units SU (SU0 to SU3). Each serial unit SU contains multiple NAND strings NS. Each NAND string NS contains, for example, eight memory cell transistors MT (MT0 to MT7), and select transistors ST1 and ST2.

[0064] Furthermore, the number of memory cell transistors MT is not limited to 8; for example, it can be 32, 48, 64, or 96. For instance, to improve cut-off characteristics, selection transistors ST1 and ST2 can each be composed of multiple transistors instead of a single transistor. Moreover, dummy cell transistors can also be placed between the memory cell transistor MT and the selection transistors ST1 and ST2.

[0065] The memory cell transistor MT is connected in series between the select transistor ST1 and the select transistor ST2. The memory cell transistor MT7 on one side is connected to the source of the select transistor ST1, and the memory cell transistor MT0 on the other side is connected to the drain of the select transistor ST2.

[0066] The gates of the select transistor ST1 for each of the serial cells SU0 to SU3 are all connected to the selectable gate lines SGD0 to SGD3. The gates of the select transistor ST2 are all connected to the same selectable gate line SGS among multiple serial cells SU located in the same BLK. The gates of the memory cell transistors MT0 to MT7 located in the same BLK are all connected to the word lines WL0 to WL7. That is to say, the word lines WL0 to WL7 and the selectable gate line SGS are common among multiple serial cells SU0 to SU3 in the same BLK, while the selectable gate line SGD is set individually for each of the serial cells SU0 to SU3, even within the same BLK.

[0067] The memory cell array 110 has m bit lines BL (BL0, BL1, ..., BL(m-1)). "m" is an integer representing the number of NAND strings NS contained in one string cell SU. In each NAND string NS, the drain of the select transistor ST1 is connected to the corresponding bit line BL. The source of the select transistor ST2 is connected to the source line SL. The source line SL is a common connection relative to the sources of the multiple select transistors ST2 in the block BLK.

[0068] Data stored in multiple memory cell transistors MT located within the same BLK is deleted all at once. On the other hand, data reading and writing are performed simultaneously on multiple memory cell transistors MT connected to one word line WL and belonging to one string unit SU. Each memory cell can store 3 bits of data consisting of the upper bit, the middle bit, and the lower bit.

[0069] In other words, the semiconductor memory device 2 of this embodiment uses a TLC (Triple Level Cell) method, which stores 3 bits of data in one memory cell transistor MT, as the method for writing data to the memory cell transistor MT. Alternatively, a MLC (Multi Level Cell) method, which stores 2 bits of data in one memory cell transistor MT, can also be used to write data to the memory cell transistor MT, thus replacing the state described above. The number of bits of data stored in one memory cell transistor MT is not particularly limited.

[0070] Furthermore, in the following explanation, the collection of 1-bit data stored by multiple memory cell transistors MT connected to a word line WL and belonging to a string unit SU is called a "page". Figure 3 In the text, one of the sets consisting of multiple memory cell transistors MT as described above is labeled with the symbol "MG".

[0071] As shown in this embodiment, when 3 bits of data are stored in one memory cell transistor MT, a set of multiple memory cell transistors MT connected to a common word line WL within one string cell SU can store 3 pages of data. The page consisting of the set of lower-order bits is also called the "lower page," and the data of the lower page is also called the "lower page data." Similarly, the page consisting of the set of middle-order bits is also called the "middle page," and the data of the middle page is also called the "middle page data." The page consisting of the set of upper-order bits is also called the "upper page," and the data of the upper page is also called the "upper page data."

[0072] Figure 4 The configuration of the memory cell array 110 is shown in a schematic cross-sectional view. As shown in the figure, multiple NAND strings NS are formed on the p-well region of the semiconductor substrate 300 in the memory cell array 110.

[0073] Above the p-type well region, the stacked layer has multiple wiring layers 333 that function as optional gate lines (SGS), multiple wiring layers 332 that function as word lines (WL), and multiple wiring layers 331 that function as optional gate lines (SGD). An insulating layer (not shown) is disposed between the wiring layers 333, 332, and 331 of the stacked layer.

[0074] Multiple storage vias 334 are formed in the storage cell array 110. Each storage via 334 is formed by penetrating the wiring layers 333, 332, and 331 and the insulating layer (not shown) located between them in a vertical direction, reaching the p-type well region. A bulk insulating film 335, a charge storage layer 336, and a gate insulating film 337 are sequentially formed on the side of each storage via 334, and a semiconductor pillar 338 is embedded inside it. The semiconductor pillar 338 is formed, for example, from polysilicon, and functions as a channel forming area when the storage cell transistors MT and select transistors ST1 and ST2 in the NAND string NS are activated. Thus, a pillar-shaped body composed of the bulk insulating film 335, the charge storage layer 336, the gate insulating film 337, and the semiconductor pillar 338 is formed inside the storage via 334. This pillar-shaped body is hereinafter referred to as the "storage pillar MP".

[0075] In the memory pillar MP formed inside the memory hole 334, the portions that intersect with the stacked wiring layers 333, 332, and 331 function as transistors. Among these transistors, the portion intersecting with wiring layer 331 functions as selection transistor ST1. The portion intersecting with wiring layer 332 functions as memory cell transistors MT (MT0 to MT7). The portion intersecting with wiring layer 333 functions as selection transistor ST2. With this configuration, each memory pillar MP formed inside the memory hole 334 serves as a reference. Figure 3 The NAND string NS described above performs its function.

[0076] A wiring layer, functioning as a bit line BL, is formed at a position above the semiconductor pillar 338. A contact plug 339, connecting the semiconductor pillar 338 to the bit line BL, is formed at the upper end of the semiconductor pillar 338.

[0077] Furthermore, an n+ type impurity diffusion layer and a p+ type impurity diffusion layer (not shown) are formed within the surface of the p-type well region. A contact plug 340 is formed on the n+ type impurity diffusion layer, and a wiring layer 341 is formed on the contact plug 340. The wiring layer 341 is a wiring used to adjust the potential of the source line SL, and during readout, it is connected to the NAND string NS through an inverting layer formed in the p-type well region directly below the optional gate line SGS. The p+ type impurity diffusion layer (not shown) is a wiring used to adjust the potential of the p-type well region.

[0078] Along Figure 4 The depth direction of the paper has multiple [symbols / parallels]. Figure 4 The configuration shown is the same. Along Figure 4A collection of multiple NAND strings NS arranged in a row along the depth direction of the paper forms a single string unit SU.

[0079] Furthermore, in this embodiment, as described above, the p-type well region of the semiconductor substrate 300 is used as the source line SL. Alternatively, a configuration can be adopted in which a conductor layer formed at a position above the semiconductor substrate 300 is used as the source line SL, thus replacing the configuration described above. In this case, a configuration can also be adopted in which peripheral circuitry such as the sense amplifier 120 is disposed in the portion between the semiconductor substrate 300 and the conductor layer.

[0080] return Figure 2 To continue the explanation. As mentioned above, in addition to the memory cell array 110, surface PL1 also includes a sense amplifier 120 and a line decoder 130.

[0081] The sense amplifier 120 is a circuit used to adjust the voltage applied to the bit line BL, or to read the voltage of the bit line BL and convert it into data. When reading data, the sense amplifier 120 acquires the read data read from the memory cell transistor MT to the bit line BL and transmits the acquired read data to the input / output circuit 21. When writing data, the sense amplifier 120 transmits the write data written via the bit line BL to the memory cell transistor MT.

[0082] The line decoder 130 is a circuit configured as a group of switches (not shown) to apply voltages to word lines WL. The line decoder 130 receives the block address and the line address from register 42, selects the corresponding block BLK based on the block address, and selects the corresponding word line WL based on the line address. The line decoder 130 toggles the switch group on and off to apply voltage from the voltage generation circuit 43 to the selected word line WL.

[0083] Figure 5 An example configuration of a sense amplifier 120 is shown. The sense amplifier 120 includes a plurality of sense amplification units (SAUs) associated with a plurality of bit lines BL, respectively. Figure 5 The detailed circuit configuration of one of the sensing amplification units, SAU, is extracted and illustrated.

[0084] like Figure 5 As shown, the sensing amplification unit SAU includes a sensing amplification section SA, latching circuits SDL, ADL, BDL, CDL, and XDL. The sensing amplification section SA, latching circuits SDL, ADL, BDL, CDL, and XDL are connected via a bus LBUS to transmit and receive data with each other.

[0085] The sensing amplification unit SA, for example, senses the data read from the corresponding bit line BL during the readout operation and determines whether the read data is "0" or "1". The sensing amplification unit SA includes, for example, a transistor TR1 that is a p-channel MOS (Metal Oxide Semiconductor) transistor, transistors TR2 to TR9 that are n-channel MOS transistors, and a capacitor C10.

[0086] Transistor TR1 is connected to the power supply line at one end and to transistor TR2 at the other end. The gate of transistor TR1 is connected to node INV within the latch circuit SDL. Transistor TR2 is connected to transistor TR1 at one end and to node COM at the other end. The gate of transistor TR2 is connected to the input signal BLX. Transistor TR3 is connected to node COM at one end and to transistor TR4 at the other end. The gate of transistor TR3 is connected to the input signal BLC. Transistor TR4 is a high-voltage MOS transistor. Transistor TR4 is connected to transistor TR3 at one end and to the corresponding bit line BL at the other end. The gate of transistor TR4 is connected to the input signal BLS.

[0087] Transistor TR5 is connected at one end to node COM and at the other end to node SRC. Its gate is connected to node INV. Transistor TR6 is connected at one end between transistors TR1 and TR2 and at the other end to node SEN. Its gate is connected to the input signal HLL. Transistor TR7 is connected at one end to node SEN and at the other end to node COM. Its gate is connected to the input signal XXL.

[0088] One end of transistor TR8 is grounded, and the other end is connected to transistor TR9. The gate of transistor TR8 is connected to node SEN. One end of transistor TR9 is connected to transistor TR8, and the other end is connected to the bus LBUS. The gate of transistor TR9 is fed by the input signal STB. One end of capacitor C10 is connected to node SEN. The other end of capacitor C10 is fed by the input clock CLK.

[0089] Signals BLX, BLC, BLS, HLL, XXL, and STB are generated, for example, by sequencer 41. Additionally, a voltage Vdd, for example, the internal power supply voltage of the semiconductor memory device 2, is applied to the power line connected to one end of transistor TR1, and a voltage Vss, for example, the ground voltage of the semiconductor memory device 2, is applied to node SRC.

[0090] Latch circuits SDL, ADL, BDL, CDL, and XDL temporarily store the read data. Latch circuit XDL is connected to input / output circuit 21 and is used for data input / output between sensing amplifier unit SAU and input / output circuit 21. The read data, stored in latch circuit XDL, becomes output from input / output circuit 21 to memory controller 1. For example, data read from sensing amplifier unit SAU is stored in any of latch circuits ADL, BDL, or CDL, then transferred to latch circuit XDL, and finally output from latch circuit XDL to input / output circuit 21. Alternatively, data input from memory controller 1 to input / output circuit 21 is transferred from input / output circuit 21 to latch circuit XDL, and then from latch circuit XDL to any of latch circuits ADL, BDL, or CDL.

[0091] The latch circuit SDL includes, for example, inverters IV11 and IV12, and transistors TR13 and TR14, which are n-channel MOS transistors. The input node of inverter IV11 is connected to node LAT. The output node of inverter IV11 is connected to node INV. The input node of inverter IV12 is connected to node INV. The output node of inverter IV12 is connected to node LAT. One end of transistor TR13 is connected to node INV, and the other end of transistor TR13 is connected to the bus LBUS. The gate of transistor TR13 is fed by the input signal STI. One end of transistor TR13 is connected to node LAT, and the other end of transistor TR14 is connected to the bus LBUS. The gate of transistor TR14 is fed by the input signal STL. For example, the data stored in node LAT is equivalent to the data stored in the latch circuit SDL. Furthermore, the data stored in node INV is equivalent to the inverted data stored in node LAT. The circuit configurations of latch circuits ADL, BDL, CDL, and XDL are, for example, the same as the circuit configuration of latch circuit SDL, and therefore are omitted from the description.

[0092] Figure 6 This is a schematic diagram illustrating the threshold distribution, etc., of the transistor MT in a memory cell. Located in... Figure 6 The middle section of the graph shows the relationship between the threshold voltage of the memory cell transistor MT (horizontal axis) and the number of memory cell transistors MT (vertical axis).

[0093] As shown in this embodiment, when using the TLC method, multiple memory cell transistors MT are as follows: Figure 6 As shown in the middle section, eight threshold distributions are formed. These eight threshold distributions (write levels) are named in ascending order of threshold voltage as "ER" level, "A" level, "B" level, "C" level, "D" level, "E" level, "F" level, and "G" level.

[0094] lie in Figure 6The table above shows examples of data assigned to each of the threshold voltage levels. As shown in the table, the "ER" level, "A" level, "B" level, "C" level, "D" level, "E" level, "F" level, and "G" level are assigned different 3-bit data as shown below.

[0095] "ER" level: "111" ("lower bit / middle bit / higher bit")

[0096] "A" level: "011"

[0097] "B" level: "001"

[0098] "C" level: "000"

[0099] "D" level: "010"

[0100] "E" level: 110

[0101] "F" level: 100

[0102] "G" level: 101

[0103] The verification voltage used in the write operation is set between each pair of adjacent threshold distributions. Specifically, verification voltages VfyA, VfyB, VfyC, VfyD, VfyE, VfyF, and VfyG are set corresponding to the "A", "B", "C", "D", "E", "F", and "G" levels, respectively.

[0104] The verification voltage VfyA is set between the maximum threshold voltage of the "ER" level and the minimum threshold voltage of the "A" level. If the verification voltage VfyA is applied to the word line WL, the memory cell transistors MT connected to the word line WL will be in the ON state if their threshold voltage is within the "ER" level, and in the OFF state if their threshold voltage is within the threshold distribution of the "A" level or higher.

[0105] The other verification voltages VfyB, VfyC, VfyD, VfyE, VfyF, and VfyG are set in the same way as the verification voltage VfyA. Verification voltage VfyB is set between the "A" and "B" levels, verification voltage VfyC is set between the "B" and "C" levels, verification voltage VfyD is set between the "C" and "D" levels, verification voltage VfyE is set between the "D" and "E" levels, verification voltage VfyF is set between the "E" and "F" levels, and verification voltage VfyG is set between the "F" and "G" levels.

[0106] For example, the verification voltages VfyA, VfyB, VfyC, VfyD, VfyE, VfyF, and VfyG can be set to 0.8V, 1.6V, 2.4V, 3.1V, 3.8V, 4.6V, and 5.6V, respectively. However, this is not a limitation; the verification voltages VfyA, VfyB, VfyC, VfyD, VfyE, VfyF, and VfyG can also be set in appropriate stages within the range of 0V to 7.0V.

[0107] Furthermore, the read voltage used in the read operation is set between adjacent threshold distributions. The "read voltage" refers to the voltage applied to the word line WL (select word line) connected to the memory cell transistor MT to be read during the read operation. During the read operation, data is determined based on whether the threshold voltage of the memory cell transistor MT to be read is higher than the applied read voltage.

[0108] like Figure 6 As illustrated in the diagram below, specifically, the threshold voltage VrA for determining whether the memory cell transistor MT is within the "ER" level or within the "A" level is set between the maximum threshold voltage of the "ER" level and the minimum threshold voltage of the "A" level.

[0109] The other readout voltages VrB, VrC, VrD, VrE, VrF, and VrG are set in the same way as the readout voltage VrA. Readout voltage VrB is set between the "A" and "B" levels, readout voltage VrC is set between the "B" and "C" levels, readout voltage VrD is set between the "C" and "D" levels, readout voltage VrE is set between the "D" and "E" levels, readout voltage VrF is set between the "E" and "F" levels, and readout voltage VrG is set between the "F" and "G" levels.

[0110] Furthermore, the read-through voltage VPASS_READ is set to a voltage higher than the maximum threshold voltage of the highest threshold distribution (e.g., "G" level). The memory cell transistor MT, with the read-through voltage VPASS_READ applied to its gate, becomes ON regardless of the data stored.

[0111] Furthermore, the verification voltages VfyA, VfyB, VfyC, VfyD, VfyE, VfyF, and VfyG are, for example, set to be higher than the readout voltages VrA, VrB, VrC, VrD, VrE, VrF, and VrG, respectively. In other words, the verification voltages VfyA, VfyB, VfyC, VfyD, VfyE, VfyF, and VfyG are set to be near the lower edge of the threshold distributions for "A," "B," "C," "D," "E," "F," and "G" levels, respectively.

[0112] When the data allocation described above is applied, during the read operation, one page of data for the lower bit (lower page data) can be determined using the read results of read voltages VrA and VrE. One page of data for the middle bit (middle page data) can be determined using the read results of read voltages VrB, VrD, and VrF. One page of data for the upper bit (upper page data) can be determined using the read results of read voltages VrC and VrG. Thus, the lower page data, middle page data, and upper page data are determined through 2, 3, and 2 read operations respectively. Therefore, the data allocation described above is called a "2-3-2 code".

[0113] Furthermore, the data allocation described above is merely an example, and actual data allocation is not limited to this. For example, 2 bits or more of data can be stored in a single memory cell transistor MT. Additionally, the number of threshold distributions for the allocated data can be 7 or less, or 9 or more. For example, a "1-3-3 code" or "1-2-4 code" can be used instead of a "2-3-2 code". Furthermore, the allocation of lower-level bits / middle-level bits / higher-level bits can be changed. More specifically, for example, in a "2-3-2 code", data can be allocated by determining the lower-level page data using the readout results of readout voltages VrC and VrB, determining the middle-level page data using the readout results of readout voltages VrB, VrD, and VrF, and determining the higher-level page data using the readout results of readout voltages VrA and VrE. That is, the allocation of lower-level bits and higher-level bits can be interchanged, for example. In this case, data is allocated according to the following description, corresponding to each level of the threshold voltage.

[0114] "ER" level: "111" ("lower bit / middle bit / higher bit")

[0115] Level "A": 110

[0116] "B" level: 100

[0117] "C" level: "000"

[0118] "D" level: "010"

[0119] "E" level: "011"

[0120] "F" level: "001"

[0121] "G" level: 101

[0122] The write operation performed in the semiconductor memory device 2 will be described. The write operation includes programming and verification. The "programming operation" refers to the action of increasing the threshold voltage of the memory cell transistor MT by injecting electrons into the charge storage layer 336 of the memory cell transistor MT. Furthermore, the programming operation also includes the action of maintaining the threshold voltage of the memory cell transistor MT by preventing the injection of electrons into the charge storage layer 336 of the memory cell transistor MT.

[0123] The so-called "verification action" refers to the action taken during the write operation, after the programming operation, to read data and determine whether the threshold voltage of the memory cell transistor MT has reached the target level. If the threshold voltage of the memory cell transistor MT has reached the target level, writing to it will be disabled. If the threshold voltage of the memory cell transistor MT has not reached the target level, writing to it will be performed again.

[0124] During the write operation, the combination of the programming and verification operations described above is repeated. As a result, the threshold voltage of the memory cell transistor MT rises to the target level.

[0125] Figure 7 This indicates the potential changes of each wiring during programming. The following example illustrates programming in plane PL1, but programming in plane PL2 is performed in the same way as in plane PL1.

[0126] During programming, the sense amplifier 120 causes the potential of each bit line BL to change according to the programming data. A ground voltage Vss (e.g., 0V) is applied as an "L" level to the bit line BL connected to the memory cell transistor MT, which is the target of programming (and should raise the threshold voltage). An example of 2.5V is applied as an "H" level to the bit line BL connected to the memory cell transistor MT, which is not the target of programming (and should maintain the threshold voltage). The bit line BL described above... Figure 7 The middle part is marked as "BL(0)". The bit line BL mentioned later is in Figure 7 The Chinese character is marked as "BL(1)".

[0127] The line decoder 130 selects any block of BLK as the write target, and then selects any string cell SU. More specifically, the voltage generation circuit 43 applies, for example, 5V to the selectable gate line SGD (selectable gate line SGDsel) in the selected string cell SU via the line decoder 130. This turns on the selection transistor ST1. On the other hand, the voltage generation circuit 43 applies, for example, a voltage Vss to the selectable gate line SGS via the line decoder 130. This turns off the selection transistor ST2.

[0128] Additionally, a voltage of, for example, 5V is applied from the voltage generation circuit 43 to the selectable gate line SGD (non-selectable selectable gate line SGDusel) of the non-selectable string unit SU in the select block BLK via the line decoder 130. This turns on the selectable transistor ST1. Furthermore, the selectable gate line SGS is common to all string units SU contained in each BLK. Therefore, in the non-selectable string unit SU, the selectable transistor ST2 is also turned off.

[0129] Furthermore, voltage Vss is applied, for example, to the selectable gate line SGD and selectable gate line SGS in the non-selectable block BLK via the voltage generation circuit 43 and the line decoder 130. As a result, select transistors ST1 and ST2 are turned off.

[0130] The source line SL becomes a higher potential than the optional gate line SGS. This potential is, for example, 1V.

[0131] Then, the potential of the selectable gate line SGDsel in the select block BLK is set to, for example, 2.5V. This potential is the voltage that turns on the select transistor ST1 corresponding to the bit line BL(0), which is given 0V in the example, and turns off the select transistor ST1 corresponding to the bit line BL(1), which is given 2.5V. Thus, in the select string unit SU, the select transistor ST1 corresponding to the bit line BL(0) is turned on, and the select transistor ST1 corresponding to the bit line BL(1), which is given 2.5V, is turned off. On the other hand, the potential of the non-selectable gate line SGDusel is set to, for example, voltage Vss. Thus, in the non-select string unit SU, the select transistor ST1 is turned off regardless of the potentials of the bit lines BL(0) and BL(1).

[0132] Then, the line decoder 130 selects any word line WL as the write target in the selection block BLK. A voltage, for example, VPGM is applied from the voltage generation circuit 43 to the word line WL (selected word line WLsel) that is the write target via the line decoder 130. On the other hand, a voltage, for example, VPASS_PGM is applied from the voltage generation circuit 43 to other word lines WL (non-selected word lines WLusel) via the line decoder 130. The voltage VPGM is a high voltage used to inject electrons into the charge storage layer 336 through tunneling. The voltage VPASS_PGM is a voltage that turns on the memory cell transistor MT connected to the word line WL, but does not change the threshold voltage. VPGM is a voltage higher than VPASS_PGM.

[0133] In the NAND string NS corresponding to the bit line BL(0) which is being programmed, the select transistor ST1 is turned on. Therefore, the channel potential of the memory cell transistor MT connected to the select word line WLsel becomes 0V. The potential difference between the control gate and the channel increases, resulting in electron injection into the charge storage layer 336, thus raising the threshold voltage of the memory cell transistor MT.

[0134] In the NAND string NS corresponding to the bit line BL(1) of the non-programmed object, the selection transistor ST1 is turned off. Therefore, the channel voltage of the memory cell transistor MT connected to the selection word line WLsel floats, and through capacitive coupling with word lines WL, the channel potential rises to near the voltage VPGM. The potential difference between the control gate and the channel decreases, resulting in no electron injection into the charge storage layer 336, thus the threshold voltage of the memory cell transistor MT remains unchanged. More precisely, the threshold voltage does not change as if the threshold distribution level were shifting to a higher distribution.

[0135] During the write operation, the programming and verification actions are repeated until it is confirmed that the data has been written correctly. Figure 8 The example illustrates how data is written by repeating a combination of programming and verification actions 19 times. These repeated actions are hereinafter referred to as a "loop".

[0136] Figure 8 The diagram shows the target levels for the verification actions performed in each loop. As shown, in the first and second loops, only the "A" level is verified. That is, during the verification action, voltage VfyA is applied to the select word line WLsel, but voltages VfyB to VfyG are not applied. In the following third and fourth loops, both the "A" and "B" levels are verified. That is, during the verification action, verification voltages VfyA and VfyB are applied sequentially to the select word line WLsel, but verification voltages VfyC to VfyG are not applied.

[0137] In the 5th and 6th loops, verification is performed on the "A", "B", and "C" levels. That is, during verification, verification voltages VfyA, VfyB, and VfyC are applied sequentially to the select word line WLsel, but verification voltages VfyD to VfyG are not applied. Then, in the 6th loop, verification is performed on the "A" level. This is because, empirically, programming for the "A" level can be roughly completed in, for example, 6 loops.

[0138] Furthermore, in the 7th and 8th loops, verification is performed on the "B", "C", and "D" levels. That is, during the verification operation, verification voltages VfyB, VfyC, and VfyD are sequentially applied to the select word line WLsel. Then, in the 8th write operation, the verification operation targeting the "B" level is completed. Subsequently, in the 9th and 10th loops, verification is performed on the "C", "D", and "E" levels. That is, during the verification operation, verification voltages VfyC, VfyD, and VfyE are sequentially applied to the select word line WLsel. Then, in the 10th loop, the verification operation targeting the "C" level is completed.

[0139] Then, the same steps are repeated up to the "G" level, repeating the cycle up to 19 times.

[0140] Figure 9 The diagram shows the potential of each wiring during the write operation as described above. Figure 9 This indicates that in the 1st to 6th cycles, the potential of the word line WLsel is selected, and the bit line BL corresponding to the memory cell transistor MT that should maintain the "Er" level is selected. Figure 9 The potential marked BL (“Er”) in the middle, and the bit line BL (in the middle) corresponding to the storage cell transistor MT that should cause the threshold to rise to the level between “A” and “G”. Figure 9 The time-varying potentials are labeled BL(“A”), BL(“B”), BL(“C”), BL(“D”), BL(“E”), BL(“F”) and BL(“G”) respectively.

[0141] As shown in the figure, in the first loop, the memory cell transistors MT connected to bit lines BL(“A”) to BL(“G”) are programmed. Specifically, a voltage VPGM is applied to the select word line WLsel, for example, 2.5V is applied to the bit line BL(“Er”), and a voltage VSS (=0V) is applied to the bit lines BL(“A”) to BL(“G”). As a result, the threshold voltage of the select memory cell transistors MT connected to the bit lines BL(“A”) to BL(“G”) rises.

[0142] Following this programming action, a verification operation is performed regarding the "A" level. Specifically, the bit line BL ("A") is pre-charged to, for example, 0.7V, and a verification voltage VfyA is applied to the select word line WLsel. Other bit lines BL ("Er"), BL ("B") to BL ("G") are fixed to, for example, 0V, and excluded from the verification process. The result is as described above. Figure 8 As stated, in the first loop, only the "A" level is used as the object for verification.

[0143] In the second loop, the memory cell transistors MT connected to the bit lines BL(“A”) and BL(“B”) through BL(“G”) that failed the verification operation related to the “A” level in the first loop are targeted for programming. At this time, the voltage VPGM applied to the select word line WLsel is increased slightly higher than the voltage VPGM in the first loop. Then, the verification operation related to the “A” level is performed in the same manner as in the first loop. In other words, in the second loop, the verification operation is performed only on the “A” level.

[0144] In the third loop, similar to the second loop, the memory cell transistors MT connected to the bit lines BL(“A”) and BL(“B”) through BL(“G”) that failed the verification operation related to the “A” level are targeted for programming. At this time, the voltage VPGM applied to the select word line WLsel is further increased by a slightly larger amount than the voltage VPGM in the second loop. Then, similar to the first and second loops, the verification operation related to the “A” level is performed first.

[0145] Next, a verification operation is performed regarding the "B" level. Specifically, bit lines BL("A") and BL("B") are pre-charged to, for example, 0.7V, and verification voltages VfyA and VfyB are sequentially applied to the select word line WLsel. Other bit lines BL("Er") and BL("C") through BL("G") are fixed to, for example, 0V and excluded from the verification process. The result is as described above. Figure 8 The verification operation is performed in the third cycle, using the "A" level and the "B" level as objects.

[0146] In the fourth cycle, the voltage VPGM is increased further, and the same action is performed as in the third cycle.

[0147] In the 5th loop, the memory cell transistor MT connected to bit lines BL(“A”), BL(“B”), and BL(“C”) is programmed. Then, verification of the “A”, “B”, and “C” levels is performed. In the 6th loop, the voltage VPGM is increased, and the same actions as in the 5th loop are performed.

[0148] In the 7th and subsequent loops, the same programming and verification actions described above are repeated. As a result, the voltage VPGM and the verification voltage VfyA are applied alternately and repeatedly to the select word line WLsel.

[0149] like Figure 9 As shown, in each cycle, the application of the verification voltage VfyA, etc., following the application of voltage VPGM, is repeated one or more times. The number of times the verification voltage VfyA, etc., is applied repeatedly within each cycle is as follows: Figure 9 In the example, the number of times is in the range of 1 to 3, but it could also be a different number of times than in this example. Figure 10 The graph schematically illustrates the repeated application of voltage VPGM to the select word line WLsel and verification voltage VfyA, etc.

[0150] Provide a summary of the readout action (verification action). Figure 11 This indicates the potential change of each wiring during the readout operation. The following explanation describes an example of a readout operation performed in plane PL1, but the readout operation in plane PL2 is performed in the same way as in plane PL1.

[0151] During a read operation, select the NAND string NS containing the memory cell transistor MT that is the object of the read operation. Alternatively, select the string cell SU containing the page that is the object of the read operation.

[0152] First, a voltage of, for example, 5V is applied from the voltage generation circuit 43 to the selectable gate line SGDsel, the non-selectable gate line SGDusel, and the selectable gate line SGS via the row decoder 130. This turns on the select transistors ST1 and ST2 contained in the select block BLK. Next, a read pass voltage, VPASS_READ, is applied from the voltage generation circuit 43 to the select word line WLsel and the non-selectable word line via the row decoder 130. The read pass voltage VPASS_READ is a voltage that turns on the memory cell transistor MT regardless of its threshold voltage and does not cause a change in the threshold voltage. Therefore, current is conducted in all NAND strings NS contained in the select block BLK, whether it is the select string cell SU or the non-selectable string cell SU.

[0153] Next, a read voltage Vr, such as VrA, is applied from the voltage generation circuit 43 to the word line WL (select word line WLsel) connected to the memory cell transistor MT that is the target of the read operation, via the line decoder 130. A read pass voltage VPASS_READ is applied to the other word lines WL (non-select word lines WLusel).

[0154] Additionally, while maintaining the voltage applied to the selectable gate line SGDsel and the selectable gate line SGS, a voltage, for example Vss, is applied from the voltage generation circuit 43 to the non-selectable gate line SGDusel via the line decoder 130. As a result, the select transistor ST1 contained in the select string unit SU remains on, while the select transistor ST1 contained in the non-selectable string unit SU becomes off. Furthermore, in both the select string unit SU and the non-selectable string unit SU, the select transistor ST2 contained in the select block BLK becomes on.

[0155] Therefore, in the NAND string NS contained in the non-selection string cell SU, at least the selection transistor ST1 is in the off state, and thus no current path is formed. On the other hand, the NAND string NS contained in the selection string cell SU forms or does not form a current path depending on the relationship between the read voltage Vr applied to the selection word line WLsel and the threshold voltage of the memory cell transistor MT.

[0156] The sense amplifier 120 applies a voltage to the bit line BL connected to the selected NAND string NS. In this state, the sense amplifier 120 reads data based on the value of the current flowing through the bit line BL. Specifically, it determines whether the threshold voltage of the memory cell transistor MT, which is the target of the read operation, is higher than the read voltage applied to the memory cell transistor MT. Alternatively, data readout may be based on the time-varying potential in the bit line BL, rather than on the value of the current flowing through the bit line BL. In the latter case, the bit line BL is pre-charged to a pre-specified potential.

[0157] The verification operation described above is performed in the same way as the read operation described above. In the verification operation, a verification voltage, such as VfyA, is applied from the voltage generation circuit 43 to the word line WL connected to the memory cell transistor MT that is being verified, via the line decoder 130.

[0158] For ease of understanding, the above explanation... Figure 11 The example shown is when a single voltage is applied as the readout voltage Vr. In actual readout operations, multiple voltages are applied in stages as the readout voltage Vr. That is, the readout voltage Vr switches through multiple values.

[0159] In this embodiment, as described above, the data of one page of the lower bit (lower page data) can be determined by using the readout results of the readout voltages VrA and VrE. Therefore, in the readout operation targeting the lower page data, the readout voltage Vr is switched sequentially by assigning the two values ​​VrA and VrE.

[0160] Figure 12 The diagram illustrates an example of the relationship between the voltage applied to the select word line WLsel and the signal STB of the sense amplifier unit SAU during a lower-page readout operation. The signal STB is a control signal used to read data based on the value of the current flowing through the bit line BL corresponding to the sense amplifier unit SAU.

[0161] like Figure 11 As illustrated in the example, the read pass voltage VPASS_READ is first applied to the select word line WLsel. Then, the voltage applied to the select word line WLsel is sequentially switched to the read voltages VrA and VrE. While the voltage of the select word line WLsel is at the read voltages VrA and VrE, data is read during the timing sequence with the input signal STB, and it is confirmed whether the memory cell transistor MT is turned on. The voltage of the select word line WLsel will eventually return to 0V (ground voltage Vss).

[0162] Thus, the voltage applied to the select word line WLsel is the read pass voltage VPASS_READ in the initial period T1, the read voltages VrA and VrE in the following period T2, and then 0V in the subsequent period T3. The read pass voltage VPASS_READ is applied in period T1 to pre-remove potential unevenness within the semiconductor pillar 338 by turning on all the memory cell transistors MT contained in the NAND string NS. This suppresses erroneous determination of the threshold voltage in each memory cell transistor MT.

[0163] The reading actions for the middle and upper pages are performed in the same way as described above. During the reading action of the middle page, in... Figure 12 During period T2, the voltage of the select word line WLsel sequentially switches to the read voltages VrB, VrD, and VrF. Additionally, during the read operation of the upper page, in... Figure 12 During the period T2, the voltage of the select word line WLsel is switched sequentially to the read voltage VrC and VrG.

[0164] like Figure 12 As illustrated in the example, a read operation can be performed by selecting only a specific page (e.g., the next lower page) from the multiple pages stored by a group of memory cell transistors MT.

[0165] Various methods have been prepared for performing readout operations on the semiconductor memory device 2. For example... Figure 12 For example, as a method for reading data from a specific page only, two methods, referred to as "normal read" and "buffered read," which will be explained below, have been prepared. In addition, as a method for reading data from multiple pages consecutively, a method referred to as "sequential read," which will be explained later, has also been prepared.

[0166] Reference Figure 13 This section explains how to read data normally. Figure 13 (A) illustrates an example of the time variation of the ready-busy signal R / B sent from the logic control pad group 32 of the semiconductor memory device 2 to the memory controller 1. The ready-busy signal R / B becomes "H (High)" when the semiconductor memory device 2 is in a ready state and "L (Low)" when the semiconductor memory device 2 becomes busy. Figure 13 (A) further illustrates the timing of inputting instructions such as “RD1” or “DO1” from memory controller 1 to semiconductor storage device 2.

[0167] Figure 13 (B) shows an example of the time variation of the voltage applied to the select word line WLsel. Figure 13 (B) illustrates the case where the voltage of the selected word line WLsel is switched to, for example, the read voltage VrA or VrE during the read operation. Furthermore, although the voltage of the selected word line WLsel is, for example, like... Figure 12 In the example, during period T1, the read operation is pre-set to the read voltage VPASS_READ, but Figure 13 (B) omits the illustration of this voltage change.

[0168] Figure 13 (C) represents an example of the time variation of data stored in the latch circuit XDL of the sensing amplification unit SAU. In this figure, "L" represents the period during which the lower page data is stored in the latch circuit XDL, "M" represents the period during which the middle page data is stored in the latch circuit XDL, and "U" represents the period during which the upper page data is stored in the latch circuit XDL.

[0169] exist Figure 13 In the example shown, instruction RD1 is first input from memory controller 1 to input / output circuit 21. Instruction RD1 is an instruction that instructs the lower page to be read. For example, instruction RD1 is an instruction set that includes an instruction signal instructing semiconductor memory device 2 to perform a read operation and an address signal indicating the address to be read. In addition to address signals, prefix instructions can also be used.

[0170] After inputting instruction RD1 to input / output circuit 21, semiconductor storage device 2 changes the ready-busy signal R / B from H to L and begins reading the next page. Figure 13 As shown in (B), the sequencer 41 sequentially switches the voltage of the select word line WLsel to the read voltages VrA and VrE, thereby determining the data of the next page.

[0171] In addition, Figure 13 The period marked "R" in (B) is the period during which the voltage of the selection word line WLsel is set to the read pass voltage VPASS_READ (not shown), and then to the initial read voltage (e.g., VrA). This period is hereinafter also referred to as the "Setup Period R". Figure 13 The period marked "RWL" in (B) is the period during which the voltage of the selection word line WLsel becomes the next read voltage (e.g., VrE). This period is also referred to below as the "read period RWL". Because the voltage of the selection word line WLsel is not pre-set to the read pass voltage VPASS_READ, the read period RWL is generally shorter than the setting period R. Figure 13 The period marked "RR" in (B) is the period during which the voltage of the select word line WLsel recovers to 0V (voltage Vss). This period is also referred to below as the "recovery period RR".

[0172] like Figure 13 As shown in (C), at the point in time when the read operation is performed by applying the read voltage VrE to the select word line WLsel, the next page data is determined. The determined data is stored, for example, in the latch circuit XDL. Thus, the next page data can be output from the input / output circuit 21.

[0173] After the transfer of the next page data to the latch circuit XDL is completed and the recovery period RR ends, the semiconductor memory device 2 changes the ready-busy signal R / B from L to H. However, the timing of the semiconductor memory device 2 changing the ready-busy signal R / B from L to H may not strictly coincide with the timing of the completion of the transfer of the next page data to the latch circuit XDL and / or the end of the recovery period RR. For example, the semiconductor memory device 2 may also change the ready-busy signal R / B from L to H at a slightly earlier timing than the completion of the transfer of the next page data to the latch circuit XDL, or at a slightly earlier timing than the end of the recovery period RR.

[0174] When the ready-busy signal R / B changes from L to H, the memory controller 1 recognizes that the next page of data can be output from the semiconductor memory device 2. Therefore, after the ready-busy signal R / B changes to H, the memory controller 1 immediately inputs the instruction DO1 to the input / output circuit 21. For example, the instruction DO1 is an instruction set that includes an instruction signal instructing the semiconductor memory device 2 to perform a data output operation and an address signal indicating the address to which the data output operation is to be performed.

[0175] After the instruction DO1 is input to the input / output circuit 21, the semiconductor storage device 2 performs the process of outputting the lower page data stored in the latch circuit XDL from the input / output circuit 21 to the memory controller 1. During this period, the ready-busy signal R / B is always H.

[0176] After the memory controller 1 completes the process of retrieving the lower page data, it inputs instruction RD2 to the input / output circuit 21. Instruction RD2 is an instruction that instructs the read operation of the middle page. For example, instruction RD2 is an instruction set that includes an instruction signal instructing the semiconductor memory device 2 to perform a read operation and an address signal indicating the address to be read.

[0177] After the instruction RD2 is input to the input / output circuit 21, the semiconductor storage device 2 changes the ready-busy signal R / B from H to L and begins the read operation of the middle page. For example... Figure 13 As shown in (B), the sequencer 41 sequentially switches the voltage of the select word line WLsel to the read voltages VrB, VrD, and VrF, thereby determining the middle page data.

[0178] Similar to reading the next page of data, the period during which the initial read voltage VrB is applied to the select word line WLsel is part of the setting period R. Additionally, the periods during which read voltages VrD and VrF are applied to the select word line WLsel are both read periods RWL, followed by the recovery period RR after the final read period RWL.

[0179] like Figure 13 As shown in (C), at the time point when the read operation is performed by applying the read voltage VrF to the select word line WLsel, the middle page data is determined. The determined data is stored, for example, in the latch circuit XDL. This results in a state where the middle page data can be output from the input / output circuit 21. Furthermore, Figure 13 In the example, at the moment the instruction RD2 is input to the input / output circuit 21, the storage of the lower page data in the latch circuit XDL is released. Alternatively, the state described above can be replaced by keeping the lower page data stored in the latch circuit XDL for the period up to the time before the middle page data is transmitted to the latch circuit XDL.

[0180] After the transfer of the intermediate page data to the latch circuit XDL is completed and the recovery period RR ends, the semiconductor memory device 2 changes the ready-busy signal R / B from L to H. This allows the memory controller 1 to recognize that intermediate page data can be output from the semiconductor memory device 2. Therefore, immediately after the ready-busy signal R / B becomes H, the memory controller 1 inputs instruction DO2 to the input / output circuit 21. For example, instruction DO2 is an instruction set containing an instruction signal instructing the semiconductor memory device 2 to perform a data output operation and an address signal indicating the address to which the data output operation is performed.

[0181] After the instruction DO2 is input to the input / output circuit 21, the semiconductor storage device 2 performs the process of outputting the middle page data stored in the latch circuit XDL from the input / output circuit 21 to the memory controller 1. During this period, the ready-busy signal R / B is always H.

[0182] After the memory controller 1 completes the process of retrieving the middle page data, it inputs instruction RD3 to the input / output circuit 21. Instruction RD3 is an instruction that instructs the upper page to be read. For example, instruction RD3 is an instruction set that includes an instruction signal instructing the semiconductor memory device 2 to perform a read operation and an address signal indicating the address to be read.

[0183] After the instruction RD3 is input to the input / output circuit 21, the semiconductor storage device 2 changes the ready-busy signal R / B from H to L and begins the read operation of the upper page. For example... Figure 13 As shown in (B), the sequencer 41 sequentially switches the voltage of the select word line WLsel to the read voltages VrC and VrG, thereby determining the data of the upper page.

[0184] Similar to reading the next page of data, the period during which the initial read voltage VrC is applied to the select word line WLsel is part of the setting period R. Additionally, the period during which the read voltage VrG is applied to the select word line WLsel is the read period RWL, followed by the recovery period RR.

[0185] like Figure 13 As shown in (C), at the point in time when the read operation is performed by applying the read voltage VrG to the select word line WLsel, the upper page data is determined. The determined data is stored, for example, in the latch circuit XDL. Thus, the upper page data can be output from the input / output circuit 21.

[0186] After the transfer of the upper-page data to the latch circuit XDL is completed and the recovery period RR ends, the semiconductor memory device 2 changes the ready-busy signal R / B from L to H. This allows the memory controller 1 to recognize that upper-page data can be output from the semiconductor memory device 2. Therefore, immediately after the ready-busy signal R / B becomes H, the memory controller 1 inputs instruction DO3 to the input / output circuit 21. For example, instruction DO1 is an instruction set containing an instruction signal instructing the semiconductor memory device 2 to perform a data output operation and an address signal indicating the address to which the data output operation is performed.

[0187] After the instruction DO3 is input to the input / output circuit 21, the semiconductor storage device 2 performs the process of outputting the upper page data stored in the latch circuit XDL from the input / output circuit 21 to the memory controller 1. During this period, the ready-busy signal R / B is always H.

[0188] As described above, during a read operation performed in normal read mode, the voltage of the select word line WLsel is switched while the operation of determining specific page data corresponding to the address signal contained in the instruction set is first performed. Then, the operation of outputting this data from the input / output circuit 21 to the memory controller 1 is performed. The former operation is also referred to as the "Core operation" below, and the latter operation is also referred to as the "Dout operation".

[0189] In a normal read operation, the Core action and Dout action are executed sequentially for each page specified by the instruction set. Furthermore, to read data from multiple pages, even if multiple normal read instruction sets are input, the read operation from the next page will not begin until the read operation from page 1 is completely completed. Therefore, as... Figure 13 For example, when data is read continuously from the lower page, middle page, and upper page through normal reading, the time required until the memory controller 1 obtains all the data becomes relatively long.

[0190] In contrast, in cache reads, by executing a portion of Core operations and Dout operations simultaneously or in parallel, multiple pages of data can be read in a shorter time than in normal reads. (See reference...) Figure 14 This section explains how to read from the high-speed buffer.

[0191] Figure 14 (A) China and Israel Figure 13 (A) The same method is shown as an example of the time variation of the ready-busy signal R / B sent from the logic control pad group 32 of the semiconductor memory device 2 to the memory controller 1. Figure 14 (B) China and Israel Figure 13 (B) The same method is used to show an example of the time variation of the voltage applied to the select word line WLsel. Figure 14 (C) China and Israel Figure 13 (C) The same method is used to illustrate an example of the time variation of data stored in the latch circuit XDL of the sensing amplification unit SAU. Figure 14 (D) China and Israel Figure 14 (C) The same method is used to illustrate an example of the time variation of data stored in the latch circuit ADL of the sensing amplification unit SAU.

[0192] exist Figure 14 In the example shown, it is also related to Figure 13 Similarly, in this example, the memory controller 1 first inputs instruction RD1 to the input / output circuit 21. According to instruction RD1, the sequencer 41 sequentially switches the voltage of the select word line WLsel to the read voltages VrA and VrE, thereby determining the next page data. The determined next page data is stored, for example, in the latch circuit ADL, and then transferred to the latch circuit XDL. After the transfer of the next page data to the latch circuit XDL is completed and the recovery period RR ends, the semiconductor memory device 2 changes the ready-busy signal R / B from L to H. Up to this point, all... Figure 13 The situation shown is the same as the normal read scenario.

[0193] exist Figure 14 In the example, after the ready-busy signal R / B changes to H, the instruction RD2' is input from the memory controller 1 to the input / output circuit 21. Although instruction RD2' is the same as instruction RD2 that instructs a read operation of a middle page, it instructs a read operation to be performed in a cached read mode. For example, instruction RD2' is an instruction set that includes an instruction signal instructing the semiconductor memory device 2 to perform a read operation and an address signal indicating the address to be read.

[0194] After the instruction RD2' is input to the input / output circuit 21, the semiconductor storage device 2 begins the Core operation to read the middle page data. Specifically, the sequencer 41 sequentially switches the voltage of the select word line WLsel to the read voltages VrB, VrD, and VrF, thereby determining the middle page data.

[0195] When the instruction RD2' is input to the input / output circuit 21, the semiconductor memory device 2 changes the ready-busy signal R / B from H to L. However, at this point, the next page data can be output from the input / output circuit 21, so the semiconductor memory device 2 will immediately change the ready-busy signal R / B back from L to H.

[0196] After the ready-busy signal R / B changes to H, the memory controller 1 inputs the instruction DO1 to the input / output circuit 21.

[0197] After the instruction DO1 is input to the input / output circuit 21, the semiconductor memory device 2 performs the process of outputting the lower page data stored in the latch circuit XDL from the input / output circuit 21 to the memory controller 1. During this period, the ready-busy signal R / B is always H. At this time, the semiconductor memory device 2 is performing a Core operation to read the middle page data. That is to say, in Figure 14 In the high-speed buffer read, the Dout action used to output the lower page data and the Core action used to read the middle page data are performed in parallel.

[0198] After the memory controller 1 completes the process of retrieving the lower page data, it inputs instruction RD3' to the input / output circuit 21. Although instruction RD3' is also an instruction to read the upper page, just like instruction RD3, it is an instruction to perform the read operation using a cache read method. For example, instruction RD3' is an instruction set that includes an instruction signal instructing the semiconductor memory device 2 to perform a read operation and an address signal indicating the address to be read.

[0199] When the instruction RD3' is input to the input / output circuit 21, the semiconductor memory device 2 changes the ready-busy signal R / B from H to L. At this point, a core operation for reading the middle page data is in progress in the semiconductor memory device 2. Therefore, the sequencer 41 continues this core operation, but does not begin a core operation for reading the upper page data at this point.

[0200] At the moment when the read operation is performed by applying the read voltage VrF to the select word line WLsel, the middle page data is determined. The determined middle page data is then transmitted to the latch circuit ADL for storage.

[0201] The timing of the Core action used to read the middle page data is when the voltage on the select word line WLsel returns to 0V from the read voltage VrF. Figure 14 In the example, the output of the lower page data according to instruction DO1 is completed. Therefore, semiconductor memory device 2 transfers the middle page data from latch circuit ADL to latch circuit XDL. After the middle page data is stored in latch circuit XDL, i.e., the middle page data is output from input / output circuit 21, semiconductor memory device 2 changes the ready-busy signal R / B from L to H.

[0202] Therefore, memory controller 1 recognizes that mid-page data can be output from semiconductor memory device 2. Thus, after the ready-busy signal R / B changes to H, instruction DO2 is immediately input from memory controller 1 to input / output circuit 21.

[0203] After the instruction DO2 is input to the input / output circuit 21, the semiconductor storage device 2 performs the process of outputting the middle page data stored in the latch circuit XDL from the input / output circuit 21 to the memory controller 1. During this period, the ready-busy signal R / B is always H.

[0204] After the Core operation to read the middle page data is completed, the sequencer 41 begins the Core operation to read the upper page data according to the pre-input instruction RD3'. Figure 14 As shown in (B), the sequencer 41 sequentially switches the voltage of the select word line WLsel to the read voltages VrC and VrG, thereby determining the data of the upper page. Thus, in Figure 14 During the high-speed buffer read, the Dout operation used to output the middle page data and the Core operation used to read the upper page data are performed in parallel.

[0205] After the memory controller 1 completes the process of obtaining the middle page data, it inputs the instruction TR to the input / output circuit 21. The instruction TR is an instruction that instructs the data read by the last read instruction (in this example, instruction RD3') to be transferred to the latch circuit XDL.

[0206] After the instruction TR is input to the input / output circuit 21, the semiconductor memory device 2 changes the ready-busy signal R / B from H to L. At this point, the semiconductor memory device 2 is performing a Core operation to read the data from the upper page. Therefore, the sequencer 41 continues this Core operation and does not begin the processing corresponding to the instruction TR (the processing of transferring the upper page data to the latch circuit XDL) at this point.

[0207] At the moment when the read operation is performed by applying the read voltage VrG to the select word line WLsel, the upper page data is determined. The determined upper page data is then transmitted to the latch circuit ADL for storage.

[0208] The timing of the Core action used to read the upper page data is when the voltage on the select word line WLsel returns to 0V from the read voltage VrG. Figure 14 In the example, the output of the middle page data according to instruction DO2 is completed. Therefore, semiconductor memory device 2 transfers the upper page data from latch circuit ADL to latch circuit XDL. After the upper page data is stored in latch circuit XDL, i.e., the upper page data is output from input / output circuit 21, semiconductor memory device 2 changes the ready-busy signal R / B from L to H.

[0209] Therefore, memory controller 1 recognizes that upper-level page data can be output from semiconductor memory device 2. Thus, after the ready-busy signal R / B changes to H, instruction DO3 is immediately input from memory controller 1 to input / output circuit 21.

[0210] After the instruction DO3 is input to the input / output circuit 21, the semiconductor storage device 2 performs the process of outputting the upper page data stored in the latch circuit XDL from the input / output circuit 21 to the memory controller 1. During this period, the ready-busy signal R / B is always H.

[0211] As described above, in a read operation performed using a cache read method, the Core operation and the Dout operation are performed in parallel for a portion of the time. Therefore, when data is read continuously from the lower page, middle page, and upper page, the time required until the memory controller 1 has obtained all the data is shorter than in a normal read operation.

[0212] Whether in normal reads or cache reads, the Core operation is divided into reading data from the lower page, reading data from the middle page, and reading data from the upper page. Therefore, idle time occurs between each Core operation, thus increasing the overall read operation time. Furthermore, each Core operation corresponding to each page initially requires setting the period R, further increasing the overall read operation time.

[0213] Therefore, in the semiconductor memory device 2 of this embodiment, a method called sequential read is also provided as a method for reading data from multiple pages at once. Before describing the sequential read of this embodiment, please refer to... Figure 15 The sequential reading pattern of the same comparative examples as before will be explained. Figure 15 China and Israel Figure 14 The same method was used to demonstrate the time changes of voltages, etc., in the case of sequential readings of the comparison examples.

[0214] exist Figure 15 In the example shown, the instruction RD is first input from the memory controller 1 to the input / output circuit 21. The instruction RD is an instruction that instructs data to be read sequentially from the lower page, the middle page, and the upper page. For example, the instruction RD is a set of instructions that includes an instruction signal instructing the semiconductor memory device 2 to perform a read operation and an address signal indicating the address to be read.

[0215] After the instruction RD is input to the input / output circuit 21, the semiconductor storage device 2 changes the ready-busy signal R / B from H to L and begins a sequential read operation. For example... Figure 15 As shown in (B), the sequencer 41 will select the voltage of the word line WLsel to undergo... Figure 6The seven readout voltages shown are switched sequentially from low to high as readout voltages VrA, VrB, ..., VrF, VrG. Furthermore, the sequencer 41 obtains data from the select memory cell transistor MT by performing a readout operation in each case where each readout voltage is applied to the select word line WLsel.

[0216] In sequential reads, the period during which the initial read voltage VrA is applied to the select word line WLsel is part of the setup period R. Then, the periods during which read voltages VrB, VrC, ..., VrG are applied to the select word line WLsel are all read periods RWL, followed by a recovery period RR. Thus, in sequential reads, there is only one setup period R and only one recovery period RR.

[0217] As mentioned above, the lower page data can be determined using the readout results of the readout voltages VrA and VrE. Therefore, Figure 15 In the comparative example, at the time when the read operation is performed by applying the read voltage VrE to the select word line WLsel, the next page data is determined. The determined data is stored, for example, in the latch circuit ADL, and then the data is transferred to the latch circuit XDL. Thus, the state becomes such that the next page data can be output from the input / output circuit 21.

[0218] Once the semiconductor memory device 2 reaches a state where it can output the next page of data from the input / output circuit 21, the ready-busy signal R / B changes from L to H. As a result, the memory controller 1 recognizes that the next page of data can be output from the semiconductor memory device 2. Therefore, immediately after the ready-busy signal R / B changes to H, the memory controller 1 inputs the instruction DO1 to the input / output circuit 21.

[0219] After the instruction DO1 is input to the input / output circuit 21, the semiconductor storage device 2 performs the process of outputting the lower page data stored in the latch circuit XDL from the input / output circuit 21 to the memory controller 1, i.e., the Dout operation. During this period, the ready-busy signal R / B is always H. Figure 15 In (A), the period during which the Dout action for lower page data is performed as described above is marked as "DoutL".

[0220] During the Dout operation as described above, the voltage switching operation of the select word line WLsel continues. As mentioned above, the median page data can be determined using the readout results of the readout voltages VrB, VrD, and VrF. Therefore, Figure 15 In the comparative example, the middle page data is determined at the time point when the read operation is performed by applying the read voltage VrF to the select word line WLsel. The determined middle page data is then transmitted to the latch circuit ADL for storage.

[0221] Additionally, the data on the upper page can be determined using the readout results of the readout voltages VrC and VrG. Therefore, Figure 15 In the comparative example, the upper page data is determined at the time point when the read operation is performed by applying the read voltage VrG to the select word line WLsel. The determined upper page data is then transmitted to the latch circuit ADL for storage.

[0222] In addition, the following text addresses Figure 15 As illustrated in the example, before the time point when transmitting the upper page data to the latch circuit ADL, the middle page data is transmitted from the latch circuit ADL to the latch circuit XDL in advance. Therefore, even if the upper page data is transmitted to the latch circuit ADL, the middle page data will not disappear. Alternatively, the determined upper page data can be transmitted to the latch circuit BDL or the latch circuit CDL instead of the latch circuit ADL, so that the Dout operation of each page can be performed at any timing.

[0223] The action of obtaining the next page data through memory controller 1 ( Figure 15 After the DoutL is completed, the instruction TR is input from the memory controller 1 to the input / output circuit 21. The instruction TR is used as an instruction to instruct the semiconductor memory device 2 to transfer the data of the next page (the middle page in this example) to the latch circuit XDL.

[0224] After the instruction TR is input to the input / output circuit 21, the semiconductor storage device 2 changes the ready-busy signal R / B from H to L. Figure 15 In this example, at this point in time, the median page data has been determined and stored in the latch circuit ADL. The sequencer 41 transfers the median page data from the latch circuit ADL to the latch circuit XDL. Once the median page data is stored in the latch circuit XDL, i.e., the median page data is output from the input / output circuit 21, the semiconductor storage device 2 changes the ready-busy signal R / B from L to H.

[0225] Therefore, memory controller 1 recognizes that mid-page data can be output from semiconductor memory device 2. Thus, after the ready-busy signal R / B changes to H, instruction DO2 is immediately input from memory controller 1 to input / output circuit 21.

[0226] After the instruction DO2 is input to the input / output circuit 21, the semiconductor storage device 2 performs the process of outputting the middle page data stored in the latch circuit XDL from the input / output circuit 21 to the memory controller 1, i.e., the Dout operation. During this period, the ready-busy signal R / B is always H. Figure 15 In (A), the period during which the Dout action for median page data is performed as described above is marked as "DoutM". Figure 15In the example, the Core action was completed before the period was completed.

[0227] The action of obtaining the middle page data through memory controller 1 ( Figure 15 After the DoutL is completed, the instruction TR is input from the memory controller 1 to the input / output circuit 21. As described above, the instruction TR is used as an instruction to instruct the semiconductor memory device 2 to transfer the data of the next page (the previous page in this example) to the latch circuit XDL.

[0228] After the instruction TR is input to the input / output circuit 21, the semiconductor storage device 2 changes the ready-busy signal R / B from H to L. Figure 15 In this example, at this point in time, the upper-page data has been determined and stored in the latch circuit ADL. The sequencer 41 transfers the upper-page data from the latch circuit ADL to the latch circuit XDL. After the upper-page data is stored in the latch circuit XDL, i.e., the upper-page data is output from the input / output circuit 21, the semiconductor storage device 2 changes the ready-busy signal R / B from L to H.

[0229] Therefore, memory controller 1 recognizes that upper-level page data can be output from semiconductor memory device 2. Thus, after the ready-busy signal R / B changes to H, instruction DO3 is immediately input from memory controller 1 to input / output circuit 21.

[0230] After the instruction DO3 is input to the input / output circuit 21, the semiconductor storage device 2 performs the process of outputting the upper page data stored in the latch circuit XDL from the input / output circuit 21 to the memory controller 1, i.e., the Dout operation. During this period, the ready-busy signal R / B is always H. Figure 15 In (A), the period during which the upper page data is processed using the Dout operation as described above is marked as "DoutU". After this period is completed, the read operation performed in a sequential reading manner is completed.

[0231] As described above, in the sequential read of the comparative example, the sequencer 41 switches the voltage of the select word line WLsel sequentially from low to high to the read voltages VrA, VrB, ..., VrF, VrG. The Core operations used to read data from each page are performed within a continuous period, so there is no idle time between Core operations. Furthermore, when reading multiple pages of data, the setting period R can be set once, and the recovery period RR can also be set once. Therefore, in sequential reads, the time required for Core operations can be shortened particularly.

[0232] Furthermore, in sequential reads, the Core action and the Dout action are executed in parallel for a portion of the time. In other words, a portion of the time for the Dout action is implicit within the time for the Core action. Therefore, similar to cache reads, the overall time required for a read operation can be shorter than that for a normal read.

[0233] However, in Figure 15 In the sequential read example shown, the timing of outputting the initial page data (lower page data) from input / output circuit 21, i.e., the timing of the action of reading data using the read voltage VrE, is the timing when the Core action is about to end. Therefore, the period during which the Core action and Dout action are executed in parallel is relatively short, and the final Dout action will not end until after the Core action has ended and a relatively long period TM has elapsed.

[0234] Additionally, for example, if the duration (DoutL) of the Dout action that outputs data from the lower page is longer than... Figure 15 In even longer cases, the Dout action, which outputs data from the middle page, will only begin after the Core action has finished. In this case, the time required until the entire read action is complete is further extended.

[0235] Figure 16 China and Israel Figure 15 The same method is used to illustrate the time changes of voltages, etc., in the case of sequential reading in another comparative example. In this comparative example, the sequencer 41 selects the voltage of the word line WLsel by going through... Figure 6 The example shown is an example of switching all 7 readout voltages, such as VrA, in descending order to readout voltages VrG, VrF, ..., VrB, VrA.

[0236] In this case, firstly, the upper page data is determined when the action of reading data using the read voltage VrC is completed. Then, the middle page data is determined when the action of reading data using the read voltage VrB is completed, and the lower page data is determined when the action of reading data using the read voltage VrA is completed. In this example, similarly, the timing at which the initial page data (upper page data) can be output from the input / output circuit 21 is the timing when the Core action is about to end. Therefore, the period TM from the end of the Core action to the end of the final Dout action is... Figure 15 Similarly, the examples become relatively long.

[0237] Therefore, in the sequential read performed in this embodiment, the order in which the voltage applied to the select word line WLsel is changed to a different order than that in the comparative example described above, thereby shortening the period TM, and thus shortening the entire period required for the read operation.

[0238] Reference Figure 17 The sequential reading pattern performed in this embodiment will be explained. Figure 17 (A) China and Israel Figure 15 (A) The same method is shown as an example of the time variation of the ready-busy signal R / B sent from the logic control pad group 32 of the semiconductor memory device 2 to the memory controller 1. Figure 17 (B) China and Israel Figure 15 (B) The same method is used to show an example of the time variation of the voltage applied to the select word line WLsel. Figure 17 (C) China and Israel Figure 15 (C) The same method is used to illustrate an example of the time variation of data stored in the latch circuit XDL of the sensing amplification unit SAU. Figure 17 (D) China and Israel Figure 15 (D) The same method is shown as an example of the time variation of the data stored in the latch circuit ADL of the sensing amplification unit SAU. Figure 17 (E) China and Israel Figure 17 (D) The same method is used to show an example of the time variation of the data stored in the latch circuit BDL of the sensing amplification unit SAU. Figure 17 (F) in and Figure 17 (D) The same method is used to show an example of the time variation of the data stored in the latch circuit CDL of the sensing amplification unit SAU.

[0239] exist Figure 17 In the example, with Figure 15 Similarly, in this example, the memory controller 1 first inputs the instruction RD to the input / output circuit 21. After inputting the instruction RD, the semiconductor storage device 2 changes the ready-busy signal R / B from H to L and begins a sequential read operation. Figure 17 As shown in (B), the sequencer 41 selects the voltage of the word line WLsel in the order of the read voltages VrA, VrE, VrB, VrD, VrF, VrC, and VrG, so that it ultimately goes through the process of... Figure 6 The seven readout voltages VrA shown are switched in a manner. In addition, the sequencer 41 obtains data from the selection memory cell transistor MT by performing a readout operation in each case where each readout voltage is applied to the selection word line WLsel.

[0240] like Figure 17As shown in (B), the period during which the Core operation is performed, i.e., the period of switching the voltage of the select word line WLsel, can be divided into three sub-periods: TML, TMM, and TMU. In the initial sub-period TML, the voltage of the select word line WLsel switches sequentially according to the read voltages VrA and VrE. In the next sub-period TMM, the voltage of the select word line WLsel switches sequentially according to the read voltages VrB, VrD, and VrF. In the final sub-period TMU, the voltage of the select word line WLsel switches sequentially according to the read voltages VrC and VrG.

[0241] During the short period TML, the read voltages VrA and VrE applied to the select word line WLsel are the voltages required to determine the next page data. During the short period TML, all the read voltages required to determine the next page data, such as VrA, are applied to the select word line WLsel, but the read voltages required to determine data other than the next page data, such as VrB, are not applied to the select word line WLsel. Therefore, at the end of the short period TML, the next page data is determined earlier. As described above, the short period TML is the period during which the voltages required to read the next page data are applied to the select word line WLsel; it can be called the "short period corresponding to the next page".

[0242] During the short period TMM, the read voltages VrB, VrD, and VrF applied to the select word line WLsel are all the voltages required to determine the median page data. During the short period TMM, all the read voltages required to determine the median page data, such as VrB, are applied to the select word line WLsel, but the read voltages required to determine data other than the median page data, such as VrA, are not applied to the select word line WLsel. Therefore, at the end of the short period TMM, the median page data is determined after the next page data. As described above, the short period TMM is the period during which the voltages required to read the median page data are applied to the select word line WLsel; this period can be called the "short period corresponding to the median page".

[0243] During the short-period TMU, the read voltages VrC and VrG applied to the select word line WLsel are the voltages required to determine the data of the upper-level page. During the short-period TMU, all the read voltages required to determine the data of the upper-level page, such as VrC, are applied to the select word line WLsel, but the read voltages required to determine data other than the data of the upper-level page, such as VrA, are not applied to the select word line WLsel. Therefore, at the end of the short-period TMU, the upper-level page data is determined after the lower-level page data and the middle-level page data. As described above, the short-period TMU is the period during which the voltages required to read the data of the upper-level page are applied to the select word line WLsel; this period can be called the "short period corresponding to the upper-level page".

[0244] After the TML period ends and the next page data is determined, the determined next page data is stored in the latch circuit ADL. After the next page data stored in the latch circuit ADL is transferred to the latch circuit XDL, the semiconductor memory device 2 changes the ready-busy signal R / B from L to H. Thus, the memory controller 1 recognizes that the next page data can be output from the semiconductor memory device 2. Therefore, after the ready-busy signal R / B becomes H, the memory controller 1 immediately inputs the instruction DO1 to the input / output circuit 21. Furthermore, although... Figure 17 (D) shows the case where the data in latch circuit ADL is deleted after the lower page data is transferred from latch circuit ADL to latch circuit XDL. However, it is also possible to transfer the lower page data from latch circuit ADL to latch circuit XDL and still keep the lower page data in latch circuit ADL.

[0245] After the instruction DO1 is input to the input / output circuit 21, the semiconductor memory device 2 performs the process of outputting the lower page data stored in the latch circuit XDL from the input / output circuit 21 to the memory controller 1, i.e., the Dout operation. During this period, the ready-busy signal R / B is always H. At this time, the semiconductor memory device 2 continues the core operation of the small period TMM. Figure 17 In (A), with Figure 15 In case (A), the period during which the Dout action for lower page data is performed, as described above, is marked as "DoutL".

[0246] After the operation of retrieving the next page data (DoutL) by the memory controller 1 is completed, the instruction TR is input from the memory controller 1 to the input / output circuit 21. This instruction TR is used as an instruction to instruct the semiconductor memory device 2 to transfer the data of the next page (the middle page in this example) to the latch circuit XDL.

[0247] After the instruction TR is input to the input / output circuit 21, the semiconductor storage device 2 changes the ready-busy signal R / B from H to L. Figure 17 In this example, at this point in time, the median page data is not yet determined and is in the middle of the small period TMM. Therefore, the median page data is not transmitted to the latch circuit XDL at this point in time.

[0248] Then, after the TMM period ends and the median page data is determined, the determined median page data is stored in the latch circuit BDL. At this timing, if the instruction TR has been input from the memory controller 1 as in this embodiment, the semiconductor memory device 2 transfers the median page data from the latch circuit BDL to the latch circuit XDL. Once the median page data is stored in the latch circuit XDL, and the median page data is output from the input / output circuit 21, the semiconductor memory device 2 changes the ready-busy signal R / B from L to H. Furthermore, although... Figure 17 (E) shows the case where the data in latch circuit BDL is deleted after the middle page data is transferred from latch circuit BDL to latch circuit XDL. However, it is also possible to transfer the middle page data from latch circuit BDL to latch circuit XDL and still keep the middle page data in latch circuit BDL.

[0249] Therefore, memory controller 1 recognizes that mid-page data can be output from semiconductor memory device 2. Thus, after the ready-busy signal R / B changes to H, instruction DO2 is immediately input from memory controller 1 to input / output circuit 21.

[0250] After the instruction DO2 is input to the input / output circuit 21, the semiconductor memory device 2 performs the process of outputting the middle page data stored in the latch circuit XDL from the input / output circuit 21 to the memory controller 1, i.e., the Dout operation. During this period, the ready-busy signal R / B is always H. At this time, the semiconductor memory device 2 continues the core operation of the small-period TMU. Figure 17 In (A), with Figure 15 In case (A), the period during which the Dout action for median page data is performed, as described above, is marked as "DoutM".

[0251] After the operation of obtaining the middle page data (DoutM) by the memory controller 1 is completed, the instruction TR is input from the memory controller 1 to the input / output circuit 21. This instruction TR is used as an instruction to instruct the semiconductor memory device 2 to transfer the data of the next page (the upper page in this example) to the latch circuit XDL.

[0252] After the instruction TR is input to the input / output circuit 21, the semiconductor storage device 2 changes the ready-busy signal R / B from H to L. Figure 17 In this example, at this point in time, the data for the upper page has not yet been determined, and it is in the middle of the small period TMU. Therefore, at this point in time, the data for the upper page is not transmitted to the latch circuit XDL.

[0253] Then, after the TMU (Time Management Unit) ends and the upper page data is determined, the determined upper page data is stored in the latch circuit CDL. At this time, if the instruction TR has been input from the memory controller 1 as in this embodiment, the semiconductor memory device 2 transfers the upper page data from the latch circuit CDL to the latch circuit XDL. Once the upper page data is stored in the latch circuit XDL, and the upper page data is output from the input / output circuit 21, the semiconductor memory device 2 changes the ready-busy signal R / B from L to H. Furthermore, although... Figure 17(F) shows the case where the data in latch circuit CDL is deleted after the upper page data is transferred from latch circuit CDL to latch circuit XDL. However, it is also possible to transfer the upper page data from latch circuit CDL to latch circuit XDL and still keep the upper page data in latch circuit CDL.

[0254] Therefore, memory controller 1 recognizes that upper-level page data can be output from semiconductor memory device 2. Thus, after the ready-busy signal R / B changes to H, instruction DO3 is immediately input from memory controller 1 to input / output circuit 21.

[0255] After the instruction DO3 is input to the input / output circuit 21, the semiconductor storage device 2 performs the process of outputting the upper page data stored in the latch circuit XDL from the input / output circuit 21 to the memory controller 1, i.e., the Dout operation. During this period, the ready-busy signal R / B is always H. Figure 17 In (A), with Figure 15 In case (A), the period during which the upper page data Dout action is performed as described above is marked as "DoutU".

[0256] After the short period TMU ends, the sequencer 41 restores the voltage of the select word line WLsel from the read voltage VrG to 0V (voltage Vss). That is, the short period TMU is followed by the recovery period RR. After the recovery period RR ends, the operation of retrieving the upper page data through the memory controller 1 (DoutU) is completed.

[0257] As described above, in the semiconductor memory device 2 of this embodiment, after the input / output circuit 21 receives the instruction RD, the sequencer 41 performs the following processing: during the periods TML, TMM, and TMU corresponding to each page to be read, the voltage of the selection word line WLsel is switched respectively, thereby determining the data of the page corresponding to that period. During each period TML, TMM, and TMU, the sequencer 41 switches the voltage of the selection word line WLsel in such a way that it covers all the voltages required to determine the data of the page corresponding to that period, but does not switch the voltage of the selection word line WLsel to the voltage required to determine the data of a page different from the page corresponding to that period.

[0258] Furthermore, in this embodiment, whenever the data of a portion of the lower, middle, and upper pages is determined, the sequencer 41 saves the data to the latch circuit XDL, thereby creating a state that can be output from the input / output circuit 21. As a result, the sequencer 41 enables at least a portion of the processing of data output from the input / output circuit 21 (i.e., Dout operation) to be performed in parallel with the processing of switching the voltage of the selection word line WLsel (i.e., Core operation).

[0259] In sequential reading using this method, the initial page data (lower page data) can be output from the input / output circuit 21 at a relatively early timing after the start of the Core operation.

[0260] Because the Dout operation starts at an earlier timeframe than in the comparison example, in this embodiment, the duration of the Dout operation (DoutL) for outputting data from the lower page and the duration of the Dout operation (DoutM) for outputting data from the middle page are implicitly included in the duration of the Core operation. As a result, the duration TM from the end of the Core operation to the end of the final Dout operation is shorter than in the comparison example, thus reducing the overall read operation time.

[0261] Reference Figure 18 The time required to continuously read the data from the next lower page, the middle page, and the upper page is explained. Figure 18 (A) shows Figure 13 This is an example of the time required for a normal read. The "Core Actions" shown in the graph represent the total time of Core actions performed during a normal read. Figure 13 As shown, a normal read operation consists of 3 setup periods (R), 4 read periods (RWL), and 3 recovery periods (RR). The total time for a normal read operation is as follows: Figure 18 As shown in (A), this represents the sum of these periods.

[0262] Figure 18 The "Dout action" shown in (A) is the total time of the portion of the Dout action executed during normal reads that does not overlap with Core actions. During normal reads, the entire Dout action is executed during periods that do not overlap with Core actions. Therefore, Figure 18 The “Dout action” shown in (A) is equal to the total time of the Dout actions performed during normal reading.

[0263] Figure 18 (B) shows Figure 14 This is an example of the time required for a cache read. The definitions of "Core Action" and "Dout Action" shown in this diagram are the same as described above. The duration of a Core Action for a cache read is also the same as for a normal read, consisting of 3 setup periods (R), 4 read periods (RWL), and 1 recovery period (RR). Therefore, the total time for a Core Action during a cache read is as follows: Figure 18 (B) shows the sum of these periods. It is related to... Figure 18 (A) shows the timing of the Core action during normal reading.

[0264] On the other hand, a portion of the Dout operation performed during a cache read is executed in parallel with the Core operation. Therefore, as... Figure 18 As shown in (B), the time required for cache read is longer than... Figure 18 (A) requires a short time to read normally.

[0265] Figure 18 (C) shows Figure 15 Examples of comparisons showing the time required to read sequentially. For example... Figure 15 As shown, the core actions during the sequential read of the comparison example include 1 setup period (R), 6 read periods (RWL), and 1 recovery period (RR). Therefore, the total core action time during the sequential read of the comparison example is as follows: Figure 18 As shown in (C), compared to Figure 18 (A) shows that the Core action in a normal read is short.

[0266] In the comparative example, a portion of the Dout action performed during sequential reads is executed in parallel with the Core action. While the length of the period during which the two actions are executed in parallel varies depending on the conditions, the total time for the portion executed during the period not overlapping with the Core action is as follows: Figure 18 As shown in (C), compared to Figure 18 (A) shows that the Dout action in normal reading is short.

[0267] Figure 18 (D) shows Figure 17 An example of the time required for sequential reading in this implementation. For example... Figure 17 As shown, the duration of the Core operation for sequential reading in this embodiment is the same as in the comparative example, including one setup period R, six read periods RWL, and one recovery period RR. Therefore, the total time for the Core operation during sequential reading in this embodiment is as follows: Figure 18 As shown in (D), compared to Figure 18 (A) shows that the Core action in a normal read is short.

[0268] In the sequential read operation of this embodiment, two of the three Dout actions are executed in parallel with the Core actions. As a result, the total time for the portion of the Dout action that is executed during the period not overlapping with the Core action is as follows: Figure 18 As shown in (D), compared to Figure 18 (C) shows that the Dout action in the sequential reading of the comparative example is shorter.

[0269] As described above, in the sequential reading of this embodiment, the time required for the entire read operation is minimized compared to other methods. Furthermore, the times described above are merely examples and will vary depending on the conditions. However, after comparing various read methods while ensuring that conditions such as the time required for the Dout operation are consistent, it was found that, for example… Figure 18 As the example shows, the sequential reading in this implementation takes the shortest time.

[0270] In this embodiment, after the input / output circuit 21 receives the instruction RD from the memory controller 1, the sequencer 41 will execute. Figure 17 The sequential reading is as described above. The instruction RD is an instruction to continuously read all pages stored in the memory cell transistor MT, i.e., the lower page, middle page, and upper page. Alternatively, if the input / output circuit 21 receives an instruction to continuously read multiple pages, not all of the lower, middle, and upper pages, but only a portion thereof, it can also perform the same sequential reading as in this embodiment, thus replacing the state described above.

[0271] For example, when the input / output circuit 21 receives an instruction to execute only the lower and middle pages sequentially, the sequencer 41 can determine the lower and middle data sequentially by applying read voltages VrA, VrE, VrB, VrD, and VrF sequentially to the select word line WLsel. Similarly, when the input / output circuit 21 receives an instruction to execute only the middle and upper pages sequentially, the sequencer 41 can determine the middle and upper data sequentially by applying read voltages VrB, VrD, VrF, VrC, and VrG sequentially to the select word line WLsel. In either case, the instruction instructed by the memory controller 1 to read sequentially is an instruction to continuously read multiple pages of data from the memory cell transistor MT. Therefore, the Dout operation for the initial page data can begin earlier than usual after the start of Core operation.

[0272] The second embodiment will be described below. Hereinafter, the differences from the first embodiment will be mainly described, while the common points with the first embodiment will be omitted as appropriate.

[0273] Figure 19 China and Israel Figure 17 The same method was used to demonstrate the time changes in voltage, etc., of each part when performing sequential readings in this embodiment. (Comparison) Figure 19 and Figure 17 It was later discovered that this embodiment differs from the first embodiment in the order in which the readout voltages VrA, etc., are applied to the select word line WLsel during sequential reading.

[0274] During the initial small period TML, the sequencer 41 switches the voltage applied to the select word line WLsel in the order of read voltages VrE and VrA, thereby determining the next page data. During the small period TMM following TML, the sequencer 41 switches the voltage applied to the select word line WLsel in the order of read voltages VrF, VrD, and VrB, thereby determining the middle page data. During the small period TMU following TMM, the sequencer 41 switches the voltage applied to the select word line WLsel in the order of read voltages VrG and VrC, thereby determining the previous page data.

[0275] Thus, regardless of whether it is the small period TML, TMM, or TMU, the sequencer 41 will switch the voltage of the selected word line WLsel in a phased manner.

[0276] Although Figure 19 (B) The illustration is omitted, but during the setting period R of applying the initial read voltage VrE in the small period TML, the read pass voltage VPASS_READ is applied to the select word line WLsel first, and then the read voltage VrE is applied.

[0277] The readout voltage VPASS_READ is a voltage larger than the readout voltages VrA to VrG. Therefore, if the readout voltage VrE is applied after the readout voltage VPASS_READ as in this embodiment, the readout voltage value can reach the target value earlier compared to the case where the readout voltage VrA is applied after the readout voltage VPASS_READ as in the first embodiment. In other words, the length of the setting period R can be shorter than in the first embodiment.

[0278] Thus, in this embodiment, the sequencer 41 reduces the voltage of the select word line WLsel in stages during the initial short period TML after the input / output circuit 21 receives the instruction RD. This shortens the setting period R, allowing the entire readout operation to be completed in a shorter time.

[0279] The third embodiment will be described below. Hereinafter, the differences from the second embodiment will be mainly described, while points common to the second embodiment will be omitted as appropriate.

[0280] Figure 20 China and Israel Figure 19 The same method is used to illustrate the time changes of voltages, etc., of each part when performing sequential reading in this embodiment. Similar to the second embodiment, this embodiment differs from the first embodiment in the order in which the readout voltages VrA, etc., are applied to the select word line WLsel during sequential reading.

[0281] During the initial small period TML, the order of the read voltages applied to the select word line WLsel is the same as in the second embodiment. Furthermore, during the small periods TMM and TMU, the order of the read voltages applied to the select word line WLsel is the same as in the first embodiment.

[0282] Thus, in this embodiment, the sequencer 41 reduces the voltage of the select word line WLsel in stages only during the initial short period TML, which includes the setting period R. The short period during which the voltage of the select word line WLsel is reduced in stages can be only a portion of the short period TML, as in this embodiment, or it can be all the short periods TML, TMM, and TMU, as in the second embodiment. However, to achieve the effect of shortening the setting period R, it is preferable to reduce the voltage of the select word line WLsel in stages at least during the initial short period.

[0283] The fourth embodiment will be described below. Hereinafter, the differences from the first embodiment will be mainly described, while the common points with the first embodiment will be omitted as appropriate.

[0284] Figure 21 China and Israel Figure 17 The same method is used to illustrate the time changes of voltages, etc., of each part when performing sequential reading in this embodiment. This embodiment also differs from the first embodiment in the order in which the readout voltages VrA, etc., are applied to the select word line WLsel during sequential reading.

[0285] During the initial period TML, the order of the read voltages applied to the select word line WLsel is the same as in the second embodiment. Similarly, during the period TMM, the order of the read voltages applied to the select word line WLsel is the same as in the first embodiment. During the period TMU, the order of the read voltages applied to the select word line WLsel is the same as in the second embodiment. Therefore, the voltages applied to the select word line WLsel are switched sequentially according to the read voltages VrE, VrA, VrB, VrD, VrF, VrG, and VrC.

[0286] Similar to the second embodiment, this embodiment also reduces the voltage of the select word line WLsel in stages during the initial short period TML. This results in a shorter setting period R.

[0287] Furthermore, in this embodiment, the effect of shortening the setting period R is achieved, while ensuring that the period during which the read voltage gradually increases, i.e., the period during which the read voltage switches sequentially in the order of VrA, VrB, VrD, VrF, and VrG, is as long as possible. As a result, the read voltage can stabilize earlier at the values ​​of VrB, VrD, VrF, and VrG, thus completing the entire readout operation in a shorter time.

[0288] The fifth embodiment will be described below. Hereinafter, the differences from the first embodiment will be mainly described, while the common points with the first embodiment will be omitted as appropriate.

[0289] Figure 22 China and Israel Figure 17 The same method is used to illustrate the time changes of voltages, etc., of each part when performing sequential reading in this embodiment. This embodiment also differs from the first embodiment in the order in which the readout voltages VrA, etc., are applied to the select word line WLsel during sequential reading.

[0290] In this embodiment, the voltage applied to the select word line WLsel is switched sequentially according to the read voltages VrG, VrC, VrB, VrD, VrF, VrE, and VrA. In this embodiment, the sequencer 41 switches the voltage applied to the select word line WLsel in such a manner that the initial short period becomes the short period TMU used to determine the upper-level data, the next short period becomes the short period TMM used to determine the middle-level data, and the final short period becomes the short period TMU used to determine the upper-level data.

[0291] In this implementation, during the Core operation, data is determined sequentially according to the order of upper page, middle page, and lower page. Therefore, the data output implemented through the Dout operation also follows this order. Thus, the order in which the data of each page is read can be appropriately changed.

[0292] The above description, with reference to specific examples, illustrates this embodiment. However, the present invention is not limited to these specific examples. Products obtained by making appropriate design modifications to these specific examples, as long as they possess the features of the present invention, are also included within the scope of the present invention. The elements, their configurations, conditions, shapes, etc., of each specific example are not limited to those illustrated, but can be appropriately modified. The elements of each specific example can be appropriately combined as long as no technical contradiction occurs. For example, such as... Figure 23 As shown, it can also be performed more than twice consecutively. Figure 17 The sequential read operation is shown. In this case, relative to instruction RD1, which indicates the first sequential read operation, it can also be done as follows: Figure 14 As shown in the comparative example, the instruction RD2', which indicates the second sequential read operation, is used as an instruction to indicate a read operation performed in a buffered read mode.

[0293] [Explanation of Symbols]

[0294] 2 Semiconductor memory devices

[0295] 21 Input / Output Circuit

[0296] 41 Sequencer

[0297] 110,210 memory cell array

[0298] MT memory cell transistor

[0299] WL lettering.

Claims

1. A semiconductor memory device, comprising: an array of memory cells having a plurality of memory cell transistors; a word line connected to a gate of each of the memory cell transistors; and a control circuit to control operation of the array of memory cells; an input circuit; and upon receipt of an instruction indicating an operation of sequentially reading out data of a plurality of pages from the memory cell transistors, the control circuit determines the data of the plurality of pages by sequentially applying, to the word line during a first time period, a read voltage corresponding to the plurality of pages as a read target, in each of the sequential time periods within the first time period, the control circuit applies, to the word line, a read voltage for determining the data of one of the plurality of pages, the control circuit not applying, to the word line, a read voltage for determining the data of any other of the plurality of pages.

2. The semiconductor memory device according to claim 1, wherein an output circuit that outputs data is further provided, and the control circuit causes the data of one of the pages to be outputtable from the output circuit and applies, to the word line, a read voltage for determining the data of another of the pages.

3. The semiconductor memory device according to claim 2, wherein the control circuit causes at least a part of a process of outputting data from the output circuit to be performed in parallel with a process of applying the read voltage to the word line. ​

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