Semiconductor device and manufacturing method therefor, and electronic device

Abstract

A semiconductor device and a manufacturing method therefor, and an electronic device. The semiconductor device comprises: at least one memory cell, wherein the memory cell comprises a first transistor (P1) and a second transistor (P2), which are vertically stacked, and the first transistor (P1) and the second transistor (P2) are vertical channel transistors. A second semiconductor layer (23b) of the second transistor (P2) is connected to a first gate electrode (26a) of the first transistor (P1); a first semiconductor layer (23a) of the first transistor (P1) comprises a first vertical portion that extends vertically; the second semiconductor layer (23b) of the second transistor (P2) comprises a second vertical portion that extends vertically; and the first gate electrode (26a) is distributed on the side wall of the first vertical portion, a first electrode (51) and a third electrode (53) extend in a first direction parallel to a substrate (1), and a second gate electrode (26b) and a third gate electrode (26c) extend in a second direction parallel to the substrate (1), wherein the first direction intersects the second direction.

Description

A semiconductor device and its manufacturing method, and an electronic device.

[0001] This application claims priority to Chinese Patent Application No. 202411571674.7, filed on November 5, 2024, entitled "A Semiconductor Device and a Method for Manufacturing the Same Thereof, and an Electronic Device", the contents of which shall be construed as incorporated herein by reference. Technical Field

[0002] This disclosure relates to, but is not limited to, device design and manufacturing in the field of semiconductor technology, and particularly to a semiconductor device and its manufacturing method, and electronic equipment. Background Technology

[0003] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that any slight difference in the manufacturing process can affect the performance of the devices.

[0004] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0005] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0006] This disclosure provides a semiconductor device, including: at least one memory cell, the memory cell including a first transistor and a second transistor stacked on a substrate in a direction perpendicular to the substrate, the second transistor being disposed on a side of the first transistor facing away from the substrate; the first transistor including: a first gate electrode, a second gate electrode, a first electrode, a second electrode, and a first semiconductor layer, the first semiconductor layer being connected to the first electrode and the second electrode respectively, the second electrode being disposed on a side of the first electrode facing away from the substrate; the second transistor including a third gate electrode, a third electrode, and a second semiconductor layer; the second semiconductor layer being connected to the third electrode and the first gate electrode respectively, the third electrode being disposed on a side of the first gate electrode facing away from the substrate; the second semiconductor layer including a metal oxide.

[0007] The first semiconductor layer includes a first vertical portion extending in a direction perpendicular to the substrate; the second semiconductor layer includes a second vertical portion extending in a direction perpendicular to the substrate; the first gate electrode is distributed on the sidewall of the first vertical portion;

[0008] The second gate electrode is distributed on the side wall of the first vertical part, and the third gate electrode is distributed on the side wall of the second vertical part;

[0009] The first electrode and the third electrode extend along a first direction parallel to the substrate, and the second gate electrode and the third gate electrode extend along a second direction parallel to the substrate, wherein the first direction and the second direction intersect.

[0010] In some embodiments, the first semiconductor layer further includes a first horizontal portion extending in a direction parallel to the substrate, the first horizontal portion being connected to the end of the first vertical portion facing the substrate, the second semiconductor layer further includes a second horizontal portion extending in a direction parallel to the substrate, the second horizontal portion being connected to the end of the second vertical portion facing the substrate, and the first gate electrode being distributed on the side of the first horizontal portion away from the substrate.

[0011] In some embodiments, the first horizontal portion and the first vertical portion are distributed along the first direction, the second horizontal portion and the second vertical portion are distributed along the first direction, the orthographic projection of the first horizontal portion on the substrate overlaps with the orthographic projection of the second horizontal portion on the substrate, and the first vertical portion and the second vertical portion are disposed on the same side of the second horizontal portion.

[0012] In some embodiments, the second electrode is disposed on the side of the second gate electrode away from the substrate, on the sidewall of the first vertical portion, and the second electrode extends along the second direction.

[0013] In some embodiments, the orthographic projection of the second electrode onto the substrate overlaps with the orthographic projection of the third gate electrode onto the substrate.

[0014] In some embodiments, the first electrode is connected to the first horizontal portion on the side facing the substrate, and the third electrode is connected to the second vertical portion on the side away from the substrate.

[0015] In some embodiments, the memory cell further includes a first gate insulating layer disposed between the first semiconductor layer and the first gate electrode, extending continuously on the side of the first horizontal portion away from the substrate, the sidewall of the first vertical portion facing the first horizontal portion, and the side of the first vertical portion away from the substrate, and extending to cover the sidewall of the second vertical portion away from the second horizontal portion.

[0016] In some embodiments, the orthogonal projections of the first gate electrode, the first gate insulating layer, and the second semiconductor layer onto the substrate are located within the orthogonal projection of the first semiconductor layer onto the substrate.

[0017] In some embodiments, the memory cell further includes a second gate insulating layer disposed on the sidewall of the first vertical portion, the second gate insulating layer forming a trench with an opening direction parallel to the substrate and away from the first semiconductor layer, and the second gate electrode filling the trench.

[0018] In some embodiments, the semiconductor device includes at least one layer of memory cell array, each layer of the memory cell array including a plurality of memory cells arrayed along the first direction and the second direction, the first electrodes of the first transistors of the memory cells in the same row of the same layer along the first direction are connected to form a first bit line of an integrated structure; the third electrodes of the second transistors of the memory cells in the same row of the same layer are connected to form a second bit line of an integrated structure; the second gate electrodes of the first transistors of the memory cells in the same column of the same layer along the second direction are connected to form a first word line of an integrated structure; the third gate electrodes of the second transistors of the memory cells in the same column of the same layer are connected to form a second word line of an integrated structure; and the second electrodes of the first transistors in the same column of the same layer are connected to form a reference signal line of an integrated structure.

[0019] In some embodiments, the second gate insulating layers of the first transistors of the memory cells in the same layer and column are connected to form an integral structure.

[0020] In some embodiments, the storage cells of each pair of adjacent columns are distributed in a mirror-symmetric manner along the first direction.

[0021] This disclosure provides a method for manufacturing a semiconductor device, including:

[0022] A first electrode is formed on the substrate, extending in a first direction parallel to the substrate;

[0023] A first semiconductor layer connected to the first electrode is formed on the side of the first electrode away from the substrate. The first semiconductor layer includes a first vertical portion extending in a direction perpendicular to the substrate.

[0024] A first gate electrode is formed, spaced apart from the first semiconductor layer and distributed on the sidewall of the first vertical portion;

[0025] A second semiconductor layer connected to the first gate electrode is formed on the side of the first gate electrode facing away from the substrate; the second semiconductor layer includes a second vertical portion extending in a direction perpendicular to the substrate;

[0026] A third electrode is formed on the side of the second semiconductor layer away from the substrate and is connected to the second semiconductor layer and extends along the first direction;

[0027] A second electrode connected to the first semiconductor layer is formed on the side of the first electrode away from the substrate. A second gate electrode extending in a second direction parallel to the substrate is formed on the sidewall of the first vertical portion. A third gate electrode extending in the second direction is formed on the sidewall of the second vertical portion. The first direction and the second direction intersect.

[0028] In some embodiments, forming a first electrode on the substrate extending in a first direction parallel to the substrate includes:

[0029] Multiple first bit lines extending along the first direction and spaced apart along the second direction are formed on the substrate, and each first bit line includes multiple first electrodes;

[0030] The step of forming a first semiconductor layer connected to the first electrode on the side of the first electrode away from the substrate, forming a first gate electrode spaced apart from the first semiconductor layer and distributed on the sidewall of the first vertical portion, and forming a second semiconductor layer connected to the first gate electrode on the side of the first gate electrode away from the substrate includes:

[0031] A first dummy layer, a second dummy layer, and a third dummy layer are formed on the side of the first bit line away from the substrate, stacked sequentially and spaced apart along a direction perpendicular to the substrate; the first dummy layer, the second dummy layer, and the third dummy layer extend along a second direction parallel to the substrate, and the orthographic projections of the first dummy layer, the second dummy layer, and the third dummy layer on the substrate overlap with the orthographic projections of multiple first bit lines on the substrate;

[0032] A first isolation trench is formed that penetrates the first dummy layer, the second dummy layer, and the third dummy layer in a direction perpendicular to the substrate and extends in a second direction. The bottom wall of the first isolation trench exposes multiple first bit lines, and the two oppositely arranged sidewalls of the first isolation trench expose the first dummy layer, the second dummy layer, and the third dummy layer.

[0033] A first semiconductor structure layer is formed covering the bottom wall and part of the sidewall of the first isolation trench. The first semiconductor structure layer covers a region on the sidewall of the first isolation trench that is less than or equal to a first preset height from the substrate. The first preset height is greater than the distance between the surface of the second dummy layer away from the substrate and the substrate, and less than the distance between the surface of the third dummy layer facing the substrate and the substrate.

[0034] A first gate insulating structure layer and a first gate electrode structure layer are formed to sequentially cover the bottom wall and side wall of the first isolation trench on which the first semiconductor structure layer is formed. A first isolation layer is filled into the first isolation trench. The first gate electrode structure layer and the first isolation layer are etched back to a position at a distance of a second preset height from the substrate to form a first sub-trench. The second preset height is greater than the first preset height and less than the distance between the surface of the third dummy layer facing the substrate and the substrate.

[0035] A second semiconductor structure layer is formed covering the bottom and sidewalls of the first sub-trench;

[0036] A second isolation trench is formed, the second isolation trench including a second sub-trench extending along a second direction and a plurality of third sub-trenches extending along a first direction and spaced apart along the second direction. The second sub-trench divides the first semiconductor structure layer, the first gate insulating structure layer, the first gate electrode structure layer and the second semiconductor structure layer into two independent parts along the second direction. The third sub-trench divides each part into multiple segments spaced apart along the second direction. Each segment includes a first semiconductor layer, a first gate insulating layer, a first gate electrode and a second semiconductor layer of a memory cell.

[0037] In some embodiments, forming a second electrode connected to the first semiconductor layer on the side of the first electrode opposite to the substrate includes:

[0038] Remove the second dummy layer to form a second lateral trench, and form a reference signal line disposed in the second lateral trench and connected to a plurality of first semiconductor layers, the reference signal line including a plurality of second electrodes;

[0039] The method of forming a second gate electrode extending in a second direction on the sidewall of the first vertical portion and forming a third gate electrode extending in a second direction on the sidewall of the second vertical portion includes: removing the third dummy layer, forming a first transverse trench, forming a second word line disposed in the first transverse trench, the second word line including a plurality of the third gate electrodes;

[0040] The first dummy layer is removed to form a third lateral trench, a second gate insulating layer is formed to cover the inner wall of the third lateral trench, and a first word line is formed to fill the third lateral trench. The first word line includes a plurality of second gate electrodes.

[0041] This disclosure provides an electronic device, including any of the semiconductor devices described above, or a semiconductor device formed by a manufacturing method of any of the semiconductor devices described above.

[0042] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings.

[0043] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0044] Overview of the attached figures

[0045] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0046] Figure 1A is a perspective view of a semiconductor device provided in some embodiments; Figure 1B is a top view of a portion of the film layer of a semiconductor device provided in some embodiments; Figure 1C is a side view of a semiconductor device provided in some embodiments; Figure 1D is a cross-sectional view of a semiconductor device provided in some embodiments along the direction aa' perpendicular to the substrate in Figure 1A.

[0047] Figure 1E is an equivalent circuit diagram of a memory cell provided in some embodiments;

[0048] Figure 2A is a top view after the formation of the first line according to some embodiments, and Figure 2B is a cross-sectional view along the direction aa' perpendicular to the substrate according to some embodiments after the formation of the first line.

[0049] Figures 3A and 3B are cross-sectional views along the cc' direction parallel to the substrate and the aa' direction perpendicular to the substrate, respectively, provided in some embodiments after the formation of the first dummy layer, the second dummy layer and the third dummy layer.

[0050] Figures 4A and 4B are cross-sectional views along the cc' direction parallel to the substrate and the aa' direction perpendicular to the substrate after the formation of the first isolation trench according to some embodiments;

[0051] Figure 5 is a cross-sectional view along the aa' direction perpendicular to the substrate after the formation of the first semiconductor layer according to some embodiments;

[0052] Figure 6 is a cross-sectional view along the aa' direction perpendicular to the substrate after the formation of the first gate insulating layer and the first gate electrode according to some embodiments;

[0053] Figure 7 is a cross-sectional view along the aa' direction perpendicular to the substrate after the formation of the second semiconductor layer according to some embodiments;

[0054] Figures 8A and 8B are cross-sectional views along the dd' direction parallel to the substrate and the aa' direction perpendicular to the substrate, respectively, after disconnecting multiple second semiconductor layers of multiple second transistors in the same row according to some embodiments.

[0055] Figures 9A and 9B are cross-sectional views along the aa' direction perpendicular to the substrate and the ee' direction perpendicular to the substrate, respectively, after disconnecting the multiple first semiconductor layers and multiple first gate electrodes of multiple first transistors in the same row according to some embodiments.

[0056] Figure 10 is a cross-sectional view along the direction perpendicular to the substrate after the third dummy layer is exposed, according to some embodiments;

[0057] Figure 11 is a cross-sectional view along the direction perpendicular to the substrate after the second word line is formed, according to some embodiments;

[0058] Figure 12 is a cross-sectional view along the aa' direction perpendicular to the substrate after forming the reference signal line, the second gate insulating layer and the first word line according to some embodiments;

[0059] Figure 13A is a top view of the second bit line after formation according to some embodiments, and Figure 13B is a cross-sectional view of the second bit line after formation according to some embodiments along the aa' direction perpendicular to the substrate.

[0060] Detailed Explanation

[0061] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the embodiments of this disclosure and the features thereof can be combined arbitrarily with each other.

[0062] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains.

[0063] The embodiments disclosed herein are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this disclosure are not limited to the shapes or values ​​shown in the drawings.

[0064] The ordinal numbers “first,” “second,” “third,” etc., used in this disclosure are provided to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0065] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the disclosure is not limited to the terms used herein and may be appropriately replaced as appropriate.

[0066] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to physical or signal connections, contact or integral connections; direct connections, indirect connections via intermediate components, or internal communication between two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure according to the specific circumstances.

[0067] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0068] In this disclosure, the first electrode may be the drain electrode and the second electrode may be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0069] In this disclosure, "connection" includes the situation where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0070] In this disclosure, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0071] In this embodiment of the disclosure, "A and B are an integral structure" can refer to a structure without obvious boundaries such as discontinuities or gaps in its microstructure. Generally, an integral structure is formed by patterning interconnected membrane layers on a single membrane layer. For example, A and B may be formed using the same material as a single membrane layer and simultaneously created through the same patterning process, resulting in a structure with interconnected relationships.

[0072] In this embodiment of the disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0073] Figure 1A is a perspective view of a semiconductor device provided in some embodiments; Figure 1B is a top view of a portion of the film layer of a semiconductor device provided in some embodiments; Figure 1C is a side view of a semiconductor device provided in some embodiments; and Figure 1D is a cross-sectional view of a semiconductor device provided in some embodiments along the direction aa' perpendicular to the substrate in Figure 1B. As shown in Figures 1A, 1B, 1C, and 1D, embodiments of this disclosure provide a semiconductor device, which may include: at least one memory cell, the memory cell including a first transistor P1 and a second transistor P2 stacked on a substrate along a direction perpendicular to the substrate, the second transistor P2 being disposed on the side of the first transistor P1 facing away from the substrate; the first transistor P1 may include: a first gate electrode 26a, a first electrode 51, a second electrode 52, and a first semiconductor layer 23a, the first semiconductor layer 23a being connected to the first electrode 51 and the second electrode 52 respectively; the second transistor P2 includes a third electrode 53 and a second semiconductor layer 23b; the second semiconductor layer 23b is connected to the third electrode 53 and the first gate electrode 26a respectively.

[0074] The first semiconductor layer 23a includes a first vertical portion extending in a direction perpendicular to the substrate 1; the second semiconductor layer 23b includes a second vertical portion extending in a direction perpendicular to the substrate 1; the first gate electrode 26a may be distributed on the sidewall of the first vertical portion.

[0075] In some embodiments, the first semiconductor layer 23a may further include a first horizontal portion extending in a direction parallel to the substrate 1, and the end of the first vertical portion facing the substrate 1 is connected to the first horizontal portion, that is, the first semiconductor layer 23a may form an L-shaped structure; the second semiconductor layer 23b may further include a second horizontal portion extending in a direction parallel to the substrate 1; the second horizontal portion is connected to the end of the second vertical portion facing the substrate 1, that is, the second semiconductor layer 23b may form an L-shaped structure, and the first gate electrode 26a may also be distributed on the side of the first horizontal portion away from the substrate 1 and connected to the side of the second horizontal portion facing the substrate 1.

[0076] The solution provided in this disclosure includes two vertically stacked vertical channel transistors in the memory cell, which can reduce the memory cell area to achieve high-density integration.

[0077] In some embodiments, the first horizontal portion and the first vertical portion are distributed along a first direction X parallel to the substrate 1, and the second horizontal portion and the second vertical portion are distributed along the first direction X. The orthographic projection of the first horizontal portion onto the substrate 1 overlaps with the orthographic projection of the second horizontal portion onto the substrate 1. The first vertical portion and the second vertical portion can be disposed on the same side of the first horizontal portion. The solution provided in this embodiment allows the first transistor P1 and the second transistor P2 to be arranged as compactly as possible, reducing the area of ​​the memory cell.

[0078] The first horizontal portion can form a strip-shaped film extending along a second direction Y parallel to the substrate 1, and the first vertical portion can form a planar film extending along the second direction Y and a third direction Z (i.e., perpendicular to the substrate 1). The second horizontal portion can form a strip-shaped film extending along the second direction Y, and the second vertical portion can form a planar film extending along the second direction Y and a third direction Z.

[0079] In some embodiments, the first electrode 51 may be disposed on the side of the first semiconductor layer 23a facing the substrate 1, and the first electrode 51 extends along the first direction X and may be connected to the side of the first horizontal portion facing the substrate 1. However, the embodiments disclosed herein are not limited to this, and the first electrode 51 may also be connected to the side of the first vertical portion away from the first horizontal portion, that is, the first electrode 51 may be connected to the sidewall of the first vertical portion away from the first horizontal portion.

[0080] In some embodiments, the first transistor P1 may further include a second gate electrode 26b, which may be distributed on the sidewall of the first vertical portion, for example, on the sidewall of the first vertical portion opposite to the first horizontal portion. In the solution provided in this embodiment, the first transistor is a dual-gate transistor. The second gate electrode can turn off the first transistor when the memory cell is not selected, thus avoiding the current sharing problem that exists in the memory cell array when using the memory cell.

[0081] In some embodiments, the second gate electrode 26b may extend along a second direction Y, where the first direction X and the second direction Y intersect. In some embodiments, the first direction X and the second direction Y may be perpendicular.

[0082] In some embodiments, the second electrode 52 may be disposed on the side of the second gate electrode 26b away from the substrate 1, on the sidewall of the first vertical portion, for example, on the sidewall of the first vertical portion away from the first horizontal portion.

[0083] In some embodiments, the second electrode 52 may extend along a second direction Y. The second electrode 52 is connected to the sidewall of the first vertical portion opposite to the first horizontal portion. Extending the second electrode 52 along the second direction Y can minimize the space occupied by the storage cell along the first direction X.

[0084] In some embodiments, the dimension of the first electrode 51 along the second direction Y may be smaller than the dimension of the first horizontal portion along the second direction Y.

[0085] In some embodiments, the second transistor P2 may further include a third gate electrode 26c, which may be distributed on the sidewall of the second vertical portion, for example, on the sidewall of the second vertical portion away from the second horizontal portion.

[0086] In some embodiments, the third gate electrode 26c may extend along the second direction Y. Extending the third gate electrode 26c along the second direction Y can minimize the space occupied by the memory cell along the first direction X.

[0087] In some embodiments, the orthographic projection of the second electrode 52 onto the substrate 1 and the orthographic projection of the third gate electrode 26c onto the substrate 1 may overlap. The solution provided in this embodiment, where the orthographic projections of the second electrode 52 and the third gate electrode 26c overlap, can minimize the memory cell area.

[0088] In some embodiments, the memory cell may further include a first gate insulating layer 24a, which is disposed between the first semiconductor layer 23a and the first gate electrode 26a. The first gate insulating layer 24a extends continuously along the side of the first horizontal portion away from the substrate 1, the sidewall of the first vertical portion facing the first horizontal portion, and the side of the first vertical portion away from the substrate 1, and extends to cover the sidewall of the second vertical portion away from the second horizontal portion. That is, the first gate insulating layer 24a simultaneously serves as the gate insulating layer for both the first transistor and the second transistor, eliminating the need to fabricate separate gate insulating layers for the first and second transistors, simplifying the process and reducing costs. The first gate insulating layer 24a may cover the side of the first horizontal portion away from the substrate 1, the side of the first vertical portion facing the first horizontal portion, and the side of the first vertical portion away from the substrate 1.

[0089] In some embodiments, the first gate electrode 26a may include a third horizontal portion extending in a direction parallel to the substrate 1, a third vertical portion extending in a direction perpendicular to the substrate 1, and a fourth horizontal portion extending in a direction parallel to the substrate 1, which are connected sequentially. The third horizontal portion and the fourth horizontal portion are disposed on opposite sides of the third vertical portion along the first direction X, and the third horizontal portion, the third vertical portion, and the fourth horizontal portion are distributed along the first direction X. The side of the fourth horizontal portion facing away from the substrate 1 is connected to the side of the second horizontal portion facing the substrate 1. The third horizontal portion covers the side of the first gate insulating layer 24a facing away from the first horizontal portion, and the third vertical portion covers the side of the first gate insulating layer 24a facing away from the first vertical portion.

[0090] In some embodiments, the orthographic projection of the first gate electrode 26a, the first gate insulating layer 24a, and the second semiconductor layer 23b onto the substrate 1 can be located within the orthographic projection of the first semiconductor layer 23a onto the substrate. The solution provided in this embodiment eliminates the need for additional area occupied by the first gate electrode 26a, the first gate insulating layer 24a, and the second semiconductor layer 23b, thus reducing the area of ​​the memory cell.

[0091] In some embodiments, the third electrode 53 may extend along the first direction X and be connected to the side of the second vertical portion away from the substrate 1.

[0092] In some embodiments, the memory cell may further include a second gate insulating layer 24b disposed on a sidewall of the first vertical portion, for example, on a sidewall of the first vertical portion away from the first horizontal portion. The second gate insulating layer 24b may form a trench with an opening direction parallel to the substrate 1 and away from the first semiconductor layer 23a, and the second gate electrode 26b may fill the trench. The trench may include a bottom wall in contact with the first vertical portion and two opposing sidewalls parallel to the substrate 1.

[0093] In some embodiments, the semiconductor device may include at least one layer of memory cell array, and the multilayer memory cell array may be stacked along a direction perpendicular to the substrate 1. Each layer of the memory cell array may include a plurality of memory cells distributed along a first direction X and a second direction Y. The first electrodes 51 of the first transistors P1 of the memory cells distributed in the same row along the first direction X of the same layer are connected to form a first bit line 31 of an integrated structure, and the first bit line 31 extends along the first direction X. The third electrodes 53 of the second transistors P2 of the memory cells in the same row of the same layer are connected to form a second bit line 32 of an integrated structure, and the second bit line 32 extends along the first direction X. The second gate electrodes 26b of the first transistors P1 of the memory cells distributed in the same column along the second direction Y of the same layer are connected to form a first word line 41 of an integrated structure, and the first word line 41 extends along the second direction Y. The third gate electrodes 26c of the second transistors P2 of the memory cells in the same column of the same layer are connected to form a second word line 42 of an integrated structure, and the second word line 42 extends along the second direction Y.

[0094] In some embodiments, the second electrodes 52 of the first transistor P1 in the same layer and column can be connected to a reference signal line SL to form an integrated structure. The solution provided in this embodiment can form multiple second electrodes 52 of the first transistor P1 at once, simplifying the process. However, this disclosure is not limited to this embodiment; multiple second electrodes 52 can be manufactured separately.

[0095] In some embodiments, the second gate insulating layers 24b of the first transistors P1 in the same layer and column of the memory cells can be connected to form a single structure. The solution provided in this embodiment allows for the one-time formation of the second gate insulating layers 24b of a column of first transistors P1, simplifying the process and reducing costs.

[0096] In some embodiments, the memory cells in each pair of adjacent columns can be mirror-symmetrically distributed along the first direction X. The solution provided in this embodiment facilitates the fabrication of two columns of memory cells in a single trench, simplifying the process. However, this embodiment is not limited to this; the arrangement of components in adjacent columns of memory cells can be identical.

[0097] In some embodiments, the orthographic projections of the third gate electrode 26c and the second electrode 52 onto the substrate 1 may be located within the orthographic projection of the second gate insulating layer 24b onto the substrate 1. The solution provided in this embodiment can minimize the size of the memory cell along the first direction X.

[0098] Figure 1E is an equivalent circuit diagram of a memory cell provided in some embodiments. As shown in Figure 1E, the memory cell may include a first transistor P1 and a second transistor P2. The second gate electrode 26b of the first transistor P1 is connected to a first word line 41, the first gate electrode 26a is connected to the fourth electrode 54 of the second transistor P2, the first electrode 51 of the first transistor P1 is connected to a first bit line 31, the second electrode 52 of the first transistor P1 is connected to a reference signal line SL, the third electrode 53 of the second transistor P2 is connected to a second bit line 32, and the third gate electrode 26c of the second transistor P2 is connected to the second word line 42. The memory cell also includes a memory node SN, which contains the first gate electrode 26a of the first transistor P1. The threshold voltage of the first transistor P1 is different when different data is stored in the memory node SN. A storage node SN can store one or more bits of data. For example, when storing 1 bit of data, the threshold voltage of the first transistor P1 is Vth1 when the data stored in the storage node SN is "1" and the threshold voltage of the first transistor P1 is Vth2 when the data stored in the storage node is "0", and Vth2>Vth1. Therefore, a read voltage greater than Vth1 and less than Vth2 can be applied to the first word line RWL. When the data stored in the storage node SN is "0", the first transistor P1 is turned off, and when the data stored in the storage node SN is "1", the first transistor P1 is turned on. Different voltages or currents can be detected on the first word line RBL to determine the data stored in the storage node.

[0099] In some embodiments, the first transistor P1 can be a read transistor, and the second transistor P2 can be a write transistor. The first word line 41 can be a read word line RWL, the first bit line 31 can be a read bit line RBL, the second word line 42 can be a write word line WWL, and the second bit line 32 can be a write bit line WBL.

[0100] This disclosure provides a method for manufacturing a semiconductor device, which may include:

[0101] A first electrode 51 extending along the first direction X is formed on the substrate 1;

[0102] A first semiconductor layer 23a is formed on the side of the first electrode 51 away from the substrate 1 and connected to the first electrode 51. The first semiconductor layer 23a may include a first vertical portion extending in a direction perpendicular to the substrate 1.

[0103] A first gate electrode 26a is formed, spaced from the first semiconductor layer 23a and distributed on the sidewall of the first vertical portion;

[0104] A second semiconductor layer 23b is formed on the side of the first gate electrode 26a away from the substrate 1 and is connected to the first gate electrode 26a; the second semiconductor layer 23b may include a second vertical portion extending in a direction perpendicular to the substrate 1;

[0105] A third electrode 53 is formed on the side of the second semiconductor layer 23b away from the substrate 1 and is connected to the second semiconductor layer 23b and extends along the first direction;

[0106] A second electrode 52, connected to the first semiconductor layer 23a, is formed on the side of the first electrode 51 facing away from the substrate 1. A second gate electrode 26b, extending along the second direction Y, is formed on the sidewall of the first vertical portion. A third gate electrode 26c, extending along the second direction Y, is formed on the sidewall of the second vertical portion. The second gate electrode 26b can extend to a region outside the sidewall of the first vertical portion, and the third gate electrode 26c can extend to a region outside the sidewall of the second vertical portion.

[0107] In some embodiments, forming the first electrode 51 on the substrate 1 may include:

[0108] Multiple first bit lines 31 extending along a first direction X and spaced apart along a second direction Y are formed on the substrate 1. Each first bit line includes multiple first electrodes 51.

[0109] The formation of a first semiconductor layer 23a connected to the first electrode 51 on the side of the first electrode 51 away from the substrate 1, the formation of a first gate electrode 26a spaced from the first semiconductor layer 23a and distributed on the sidewall of the first vertical portion, and the formation of a second semiconductor layer 23b connected to the first gate electrode 26a on the side of the first gate electrode 26a away from the substrate 1 may include:

[0110] A first dummy layer, a second dummy layer, and a third dummy layer are formed on the side of the first bit line 31 facing away from the substrate 1, stacked sequentially and spaced apart along a direction perpendicular to the substrate; the first dummy layer, the second dummy layer, and the third dummy layer extend along the second direction Y, and the orthographic projection of the first dummy layer on the substrate 1, the orthographic projection of the second dummy layer on the substrate 1, and the orthographic projection of the third dummy layer on the substrate 1 overlap with the orthographic projection of multiple first bit lines 31 on the substrate 1;

[0111] A first isolation trench is formed that penetrates the first dummy layer, the second dummy layer, and the third dummy layer in a direction perpendicular to the substrate 1 and extends in a second direction. The bottom wall of the first isolation trench exposes multiple first bit lines 31, and the two oppositely arranged sidewalls of the first isolation trench expose the first dummy layer, the second dummy layer, and the third dummy layer.

[0112] A first semiconductor structure layer is formed covering the bottom wall and part of the sidewall of the first isolation trench. The first semiconductor structure layer covers the area on the sidewall of the first isolation trench that is less than or equal to the distance from the substrate 1. The first preset height is greater than the distance between the surface of the second dummy layer away from the substrate 1 and the substrate, and less than the distance between the surface of the third dummy layer facing the substrate 1 and the substrate 1.

[0113] A first gate insulating structure layer and a first gate electrode structure layer are formed to sequentially cover the bottom wall and side wall of the first isolation trench on which the first semiconductor structure layer is formed, and a first isolation layer is filled in the first isolation trench. The first gate electrode structure layer and the first isolation layer are etched back to a position at a distance of a second preset height from the substrate 1 to form a first sub-trench. The second preset height is greater than the first preset height and less than the distance between the surface of the third dummy layer facing the substrate and the substrate.

[0114] A second semiconductor structure layer is formed covering the bottom and sidewalls of the first sub-trench;

[0115] A second isolation trench is formed, the second isolation trench including a second sub-trench extending along the second direction Y and a plurality of third sub-trenches extending along the first direction X and spaced apart along the second direction. The second sub-trench divides the first semiconductor structure layer, the first gate insulating structure layer, the first gate electrode structure layer and the second semiconductor structure layer into two independent parts along the second direction Y. The third sub-trench divides each part into multiple segments spaced apart along the second direction Y. Each segment includes a first semiconductor layer 23a, a first gate insulating layer 24a, a first gate electrode 26a and a second semiconductor layer 23b of a memory cell.

[0116] In some implementations, the formation of a second electrode 52 connected to the first semiconductor layer 23a on the side of the first electrode 51 opposite to the substrate 1 includes:

[0117] Remove the second dummy layer to form a second lateral trench, and form a reference signal line SL disposed in the second lateral trench and connected to a plurality of first semiconductor layers 23a. The reference signal line SL includes a plurality of second electrodes 52.

[0118] The formation of a second gate electrode 26b extending in the second direction Y on the sidewall of the first vertical portion and the formation of a third gate electrode 26c extending in the second direction Y on the sidewall of the second vertical portion may include:

[0119] Remove the third dummy layer to form a first transverse trench, and form a second word line 42 disposed in the first transverse trench. The second word line 42 includes a plurality of the third gate electrodes 26c.

[0120] The first dummy layer is removed to form a third lateral trench, and a second gate insulating layer 24b is formed to cover the inner wall of the third lateral trench and a first word line 41 is formed to fill the third lateral trench. The first word line 41 includes a plurality of second gate electrodes 26b.

[0121] The technical solution of this embodiment is further illustrated below through the manufacturing process of the semiconductor device in this embodiment. The "patterning process" mentioned in this embodiment includes processes such as film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, which are mature manufacturing processes in related technologies. The "photolithography process" mentioned in this embodiment includes film coating, mask exposure, and development, which are mature manufacturing processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations. In the description of this embodiment, it should be understood that a "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or photolithography process during the entire manufacturing process, it can also be called a "layer." If the "thin film" requires a patterning process or photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or photolithography process contains at least one "pattern."

[0122] In one exemplary embodiment, the manufacturing process of the semiconductor device may include:

[0123] 1) Forming the first line 31;

[0124] A substrate 1 is provided, and a first conductive thin film is deposited on the substrate 1 to form a plurality of first bit lines 31. The first bit lines 31 extend along a first direction X, and the plurality of first bit lines 31 are distributed at intervals along a second direction Y. A first trench extending along the first direction X exists between adjacent first bit lines 31, and the bottom wall of the first trench is exposed on the substrate 1. The first bit lines 31 may be strip electrodes.

[0125] A first insulating film is deposited and smoothed to form a first insulating layer 11. The first insulating layer 11 fills the first trench. The side of the first insulating layer 11 facing away from the substrate 1 is flush with the side of the first bit line 31 facing away from the substrate 1, as shown in Figures 2A and 2B. Figure 2A is a top view after the formation of the first bit line 31 provided in some embodiments, and Figure 2B is a cross-sectional view along the direction aa' perpendicular to the substrate 1 after the formation of the first bit line 31 provided in some embodiments.

[0126] In some embodiments, substrate 1 may be a semiconductor substrate, a base semiconductor layer on a support structure, a metal electrode, or a semiconductor substrate having one or more layers, structures, or regions formed thereon. Substrate 1 may be a conventional silicon substrate or other bulk substrate including a semiconductor material layer.

[0127] In some embodiments, the first insulating film may be a low-K dielectric layer, i.e., a dielectric layer with a dielectric constant K < 3.9, including but not limited to silicon oxide, such as silicon dioxide (SiO2). The materials of the subsequent second to sixth insulating films, and the eighth to sixteenth insulating films are similar and will not be described again.

[0128] In some embodiments, the first conductive film may be one or more of the following different types of materials:

[0129] For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can be a metal alloy containing these metals.

[0130] Alternatively, it can be conductive metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as conductive metal oxide materials like indium tin oxide (ITO), indium zinc oxide (IZO), and indium oxide (InO); or conductive metal nitride materials like titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN).

[0131] Alternatively, it could be polycrystalline silicon, silicon, germanium, silicon-germanium, etc., which become conductive after doping.

[0132] The materials for the second to sixth conductive films are similar and will not be described in detail here.

[0133] 2) Forming a first virtual layer 61, a second virtual layer 62, and a third virtual layer 63;

[0134] A second insulating film, a first dummy layer film, a third insulating film, a second dummy layer film, a fourth insulating film, a third dummy layer film, and a fifth insulating film are sequentially deposited on the substrate 1 on which the aforementioned structure is formed.

[0135] The first dummy layer film, the third insulating film, the second dummy layer film, the fourth insulating film, the third dummy layer film, and the fifth insulating film are etched along a direction perpendicular to the substrate 1 (etching stops at the second insulating film; a portion of the second insulating film may be etched or no etching may be performed), forming multiple second trenches T2 spaced apart along the first direction X and extending along the second direction Y. The first dummy layer film is etched to form multiple first dummy layers 61, the second dummy layer film is etched to form multiple second dummy layers 62, and the third dummy layer film is etched to form multiple third dummy layers 63. The second insulating film, the third insulating film, the fourth insulating film, and the fifth insulating film sequentially form a second insulating layer 12, a third insulating layer 13, a fourth insulating layer 14, and a fifth insulating layer 15. The second trenches T2 are spaced apart by memory cells distributed along the first direction X; a group (two columns) of memory cells is defined between two adjacent second trenches T2 along the first direction X.

[0136] A sixth insulating film is deposited and smoothed to form a sixth insulating layer 16 filling the second trench T2; as shown in Figures 3A and 3B, which are cross-sectional views provided in some embodiments after the formation of the first dummy layer 61, the second dummy layer 62, and the third dummy layer 63, along the cc' direction parallel to the substrate 1 and the aa' direction perpendicular to the substrate 1. The cc' direction is parallel to the substrate 1 and passes through the film layer where the third dummy layer 63 is located.

[0137] In some embodiments, the first dummy layer film, the second dummy layer film, and the third dummy layer film may be film layers that have an etching selectivity ratio with the first insulating film, such as SiN.

[0138] 3) Form the first isolation groove T3;

[0139] A seventh insulating film is deposited to form a seventh insulating layer 17 covering the aforementioned structure. The seventh insulating layer 17 may be a film layer with an etching selectivity ratio to the first insulating film, such as SiN.

[0140] The seventh insulating layer 17, the fifth insulating layer 15, the third dummy layer 63, the fourth insulating layer 14, the second dummy layer 62, the third insulating layer 13, the first dummy layer 61, and the second insulating layer 12 are etched along a direction perpendicular to the substrate to form a plurality of first isolation trenches T3. The first isolation trenches T3 penetrate the aforementioned structure along the second direction Y, and the bottom wall of the first isolation trenches T3 exposes a plurality of first bit lines 31. The first isolation trenches T3 are disposed between adjacent second trenches T2 along the first direction X, and the length of the first isolation trenches T3 along the first direction X is less than the length of the first dummy layer 61, the second dummy layer 62, and the third dummy layer 63 along the first direction X. The two sidewalls of the first isolation trenches T3 distributed along the first direction X expose the first dummy layer 61, the second dummy layer 62, and the third dummy layer 63, as shown in Figures 4A and 4B. Figures 4A and 4B are cross-sectional views along the cc' direction parallel to the substrate 1 and the aa' direction perpendicular to the substrate 1 after the formation of the first isolation trenches T3 provided in some embodiments. That is, the first dummy layer 61, the second dummy layer 62, and the third dummy layer 63 are retained on both sides of the first isolation groove T3 so that the second word line 42, the reference signal line SL, and the first word line 41 can be formed at the locations of the third dummy layer 63, the second dummy layer 62, and the first dummy layer 61, respectively.

[0141] 4) Form the first semiconductor layer 23a;

[0142] A first semiconductor thin film and an eighth insulating thin film are sequentially deposited on the substrate 1 on which the aforementioned structure is formed. The first semiconductor thin film covers the bottom wall and side wall of the first isolation trench T3, and the eighth insulating thin film fills the first isolation trench T3.

[0143] In some embodiments, the first semiconductor thin film may be silicon, polycrystalline silicon, silicon germanium (SiGe), amorphous oxide semiconductor (AOS), etc.

[0144] In some embodiments, the first semiconductor film can be processed to improve its performance before depositing the eighth insulating film. For example, when the first semiconductor film is polycrystalline silicon, it can be subjected to high-temperature annealing, laser annealing, metal-induced annealing, etc.

[0145] The eighth insulating film is etched back to a first preset height, and the first semiconductor film is etched back to the first preset height to form an eighth insulating layer 18 and a first semiconductor layer 23a, as shown in FIG5. FIG5 is a cross-sectional view along the direction perpendicular to the substrate aa' after the formation of the first semiconductor layer 23a according to some embodiments. The first preset height can be located between the location of the second dummy layer 62 and the location of the third dummy layer 63. The first distance between the surface of the eighth insulating layer 18 facing away from the substrate 1 and the substrate 1 is located between the second distance between the surface of the second dummy layer 62 facing away from the substrate 1 and the substrate 1, and the third distance between the surface of the third dummy layer 63 facing the substrate 1 and the substrate 1. At this time, the two adjacent columns of the first semiconductor layers 23a are connected to each other to form a first semiconductor structure layer with an integral structure.

[0146] 5) Forming a first gate insulating layer 24a and a first gate electrode 26a;

[0147] The eighth insulating layer 18 is etched away, and a first gate insulating film, a second conductive film, and a ninth insulating film are sequentially deposited. The layers are then smoothed to form a first gate insulating layer 24a, a first gate electrode 26a, and a first isolation layer 19. The first gate insulating layer 24a and the first gate electrode 26a sequentially cover the bottom and sidewalls of the first isolation trench T3 where the first semiconductor layer 23a is formed. The first isolation layer 19 fills the first isolation trench T3. The side of the first isolation layer 19 facing away from the substrate 1 is flush with the side of the seventh insulating layer 17 facing away from the substrate 1, as shown in Figure 6. Figure 6 is a cross-sectional view along the direction aa' perpendicular to the substrate 1 after the formation of the first gate insulating layer 24a and the first gate electrode 26a according to some embodiments. At this time, two adjacent columns of the first gate insulating layers 24a are connected to each other to form a single first gate insulating structure layer. Two adjacent columns of the first gate electrodes 26a are connected to each other to form a single first gate electrode structure layer.

[0148] In some embodiments, the first gate insulating film may comprise one or more high-K dielectric materials, such as dielectric materials with a dielectric constant K ≥ 3.9. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, it may include, but is not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), etc., which are high-K materials. The subsequent second gate insulating film material is similar to the first gate insulating film and will not be described again. In this embodiment, the first gate insulating layer 24a serves as the gate insulating layer for the first transistor P1 and the second transistor P2.

[0149] 6) Form the second semiconductor layer 23b;

[0150] The first isolation layer 19 is etched back to the second preset height, and the first gate electrode 26a is etched back to the second preset height to form a first sub-trench T31. The sidewall of the first sub-trench T31 ​​exposes the first gate insulating layer 24a, and the bottom wall exposes the first gate electrode 26a and the first isolation layer 19. The second preset height can be located between the location of the second dummy layer 62 and the location of the third dummy layer 63, and the second preset height can be greater than the first preset height. That is, the distance between the side of the first gate electrode 26a away from the substrate 1 and the substrate 1 is greater than the distance between the side of the first semiconductor layer 23a away from the substrate 1 and the substrate 1.

[0151] A second semiconductor thin film and a tenth insulating thin film are deposited sequentially, and then smoothed to form a second semiconductor layer 23b and a tenth insulating layer 20. The second semiconductor layer 23b covers the bottom wall and sidewalls of the first sub-trench T31, and the tenth insulating layer 20 fills the first sub-trench T31. The side of the tenth insulating layer 20 facing away from the substrate 1 is flush with the side of the seventh insulating layer 17 facing away from the substrate 1, as shown in Figure 7. Figure 7 is a cross-sectional view along the direction aa' perpendicular to the substrate 1 after the formation of the second semiconductor layer 23b according to some embodiments. At this time, multiple second semiconductor layers 23b in two adjacent columns are connected to each other to form a second semiconductor structure layer with an integrated structure.

[0152] 7) Disconnect multiple second semiconductor layers 23b of multiple second transistors P2 in the same column;

[0153] The tenth insulating layer 20 and the second semiconductor layer 23b are etched to form a second isolation trench T4. The second isolation trench T4 includes a second sub-trench T41 extending along the second direction Y and a plurality of third sub-trench T42 extending along the first direction X and spaced apart along the second direction Y. The bottom wall of the second sub-trench T41 exposes the first isolation layer 19, and the side wall exposes the tenth insulating layer 20 and the second semiconductor layer 23b. The bottom wall of the third sub-trench T42 exposes the first gate electrode 26a and the first isolation layer 19, and the side wall exposes the first gate insulating layer 24a. The third sub-trench T42 disconnects the plurality of second semiconductor layers 23b of the plurality of second transistors P2 arranged in the same column along the second direction Y, as shown in Figures 8A and 8B. Figures 8A and 8B are cross-sectional views provided in some embodiments after disconnecting the plurality of second semiconductor layers 23b of the plurality of second transistors P2 arranged in the same column, along the dd' direction parallel to the substrate 1 and the aa' direction perpendicular to the substrate 1. The area shown by the dashed line in Figure 8A is the region where the first line 31 is located. The orthographic projection of the second sub-trench T42 onto the substrate 1 is outside the orthographic projection of the first line 31 onto the substrate 1. dd' is parallel to the first direction X and passes through the film layer where the seventh insulating layer 17 is located.

[0154] In some embodiments, the second semiconductor thin film may be a material such as silicon or polycrystalline silicon with a band gap of less than 1.65 eV, or it may be a wide band gap material, such as a metal oxide material with a band gap of greater than 1.65 eV.

[0155] For example, the material of the metal oxide semiconductor layer or channel may include metal oxides of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may also contain compounds of other elements, such as nitrogen (N) and silicon (Si); it may also contain trace amounts of other doping elements.

[0156] In some embodiments, the material of the metal oxide semiconductor layer or channel may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), and indium tungsten oxide (InWO4). Materials such as IWO, titanium oxide (TiO), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO) can be used. As long as the leakage current of the transistor meets the requirements, it is acceptable. The specific requirements can be adjusted according to the actual situation.

[0157] These materials have wide band gaps and low leakage current. For example, when the metal oxide material is IGZO, the transistor leakage current is less than or equal to 10. -15 A. This can improve the performance of dynamic memory.

[0158] The above-mentioned materials for metal oxide semiconductor layers or channels only emphasize the element type of the material, without emphasizing the atomic ratio or the film quality of the material.

[0159] 8) Disconnect the multiple first semiconductor layers 23a and multiple first gate electrodes 26a of the multiple first transistors P1 in the same column;

[0160] Based on the second sub-trench T41, the first isolation layer 19 is etched along a direction perpendicular to the substrate 1 to expose the first gate electrode 26a distributed on the bottom wall of the first isolation trench T3, the exposed first gate electrode 26a is etched, and the first gate insulating layer 24a and the first semiconductor layer 23a are etched to expose the first bit line 31 and the first insulating layer 11; based on the third sub-trench T42, the first gate insulating layer 24a is etched along a first direction X, and the first isolation layer 19, the first gate insulating layer 24a, the first gate electrode 26a, and the first semiconductor layer 23a are etched along a direction perpendicular to the substrate 1, such that the bottom wall of the third sub-trench T42 exposes the first insulating layer 11, and the sidewalls expose the first dummy layer 61, the second dummy layer 62 and the third dummy layer 63, the second insulating layer 12, the third insulating layer 13, and the fourth insulating layer 1. 4. The fifth insulating layer 15 and the seventh insulating layer 17, that is, the second sub-trench T41 expands along the direction toward the substrate 1 to expose the first line 31, the third sub-trench T42 expands along the direction toward the substrate 1 to expose the first insulating layer 11, and expands along the first direction X to expose the first dummy layer 61, the second dummy layer 62 and the third dummy layer 63, the second insulating layer 12, the third insulating layer 13, the fourth insulating layer 14, the fifth insulating layer 15 and the seventh insulating layer 17. At this time, the third sub-trench T42 disconnects the multiple first semiconductor layers 23a of the multiple first transistors P1 distributed in the same column along the second direction Y, and disconnects the multiple first gate electrodes 26a of the multiple first transistors P1 distributed in the same column along the second direction Y, and disconnects the multiple first gate insulating layers 24a of the multiple first transistors P1 distributed in the same column along the second direction Y. As shown in Figures 9A and 9B, Figures 9A and 9B are cross-sectional views along the aa' direction and the ee' direction perpendicular to the substrate 1, respectively, after disconnecting the multiple first semiconductor layers 23a and multiple first gate electrodes 26a of the multiple first transistors P1 in the same row according to some embodiments. The ee' direction is parallel to the first direction X and passes through the region where the third sub-trench T42 is located.

[0161] 9) Expose the third virtual layer 63;

[0162] An eleventh insulating film is deposited and smoothed to form an eleventh insulating layer 21 that fills the second isolation trench T4 (including the second sub-trench T41 and the third sub-trench T42);

[0163] The seventh insulating layer 17 is etched away, and the twelfth insulating film is deposited to form the twelfth insulating layer 22; the twelfth insulating layer 22 fills the cavity formed after the removal of the seventh insulating layer 17; the twelfth insulating layer 22 may be a film layer with an etching selectivity ratio to the third dummy layer 63, the second dummy layer 62, and the first dummy layer 61.

[0164] The twelfth insulating layer 22, the sixth insulating layer 16, and the third dummy layer 63 in the second trench T2 are etched along a direction perpendicular to the substrate 1, completely exposing the sidewalls on the side facing away from the first gate insulating layer 24a, but not exposing the second dummy layer 62, as shown in FIG10. FIG10 is a cross-sectional view along the aa' direction perpendicular to the substrate 1 after exposing the third dummy layer 63 according to some embodiments. The hard mask layer 71 deposited during the etching process can be retained on the side of the second semiconductor layer 23b facing away from the substrate 1 to protect the second semiconductor layer 23b.

[0165] 10) Forming the second character line 42;

[0166] The third dummy layer 63 is removed by lateral etching (etching along the direction parallel to the substrate 1) based on the second trench T2, forming a first lateral trench A1. A third conductive film is deposited, and a portion of the third conductive film in the second trench T2 and the first lateral trench A1 is etched away to form a second word line 42 disposed in the first lateral trench A1. A thirteenth insulating film is deposited, and the thirteenth insulating film in the second trench T2 is etched away, while the thirteenth insulating film in the first lateral trench A1 is retained to form a thirteenth insulating layer 10 disposed in the first lateral trench A1. The thirteenth insulating layer 10 covers the side of the second word line 42 away from the first gate insulating layer 24a to protect the second word line 42 in subsequent processes. As shown in FIG11, FIG11 is a cross-sectional view along the direction perpendicular to the substrate 1 after the formation of the second word line 42 provided in some embodiments.

[0167] In some embodiments, a high conformality process can be used to deposit a third conductive film, and the deposition medium acts as a mask to etch back the medium to expose the third conductive film on the sidewall of the second trench T2, and then the third conductive film is etched to form the second word line 42.

[0168] 11) Forming a reference signal line SL, a second gate insulating layer 24b, and a first word line 41;

[0169] The sidewall of the sixth insulating layer 16 to the second dummy layer 62 on the side away from the first gate insulating layer 24a is fully exposed in the second trench T2 etched along the direction perpendicular to the substrate 1, while the first dummy layer 61 is not exposed.

[0170] The second dummy layer 62 is removed by lateral etching (etching along the direction parallel to the substrate 1) based on the second trench T2, forming the second lateral trench A2. A fourth conductive film is deposited, and a portion of the fourth conductive film in the second trench T2 and the second lateral trench A2 is etched away to form a reference signal line SL disposed in the second lateral trench A2. A fourteenth insulating film is deposited, and the fourteenth insulating film in the second trench T2 is etched away, while the fourteenth insulating film in the second lateral trench A2 is retained to form a fourteenth insulating layer 9 disposed in the second lateral trench A2. The fourteenth insulating layer 9 covers the side of the reference signal line SL away from the first semiconductor layer 23a to protect the reference signal line SL in subsequent processes.

[0171] The sixth insulating layer 16 in the second trench T2 is etched along the direction perpendicular to the substrate 1 until the sidewall of the first dummy layer 61 on the side away from the first gate insulating layer 24a is fully exposed, but the first bit line 31 is not exposed.

[0172] The first dummy layer 61 is removed by lateral etching (etching along the direction parallel to substrate 1) based on the second trench T2, forming a third lateral trench A3. A second gate insulating film and a fifth conductive film are deposited sequentially. The fifth conductive film and the second gate insulating film in the second trench T2 are etched away to form a second gate insulating layer 24b and a first word line 41 disposed in the third lateral trench A3. The second gate insulating layer 24b covers the bottom wall and sidewalls of the third lateral trench A3, and the first word line 41 can fill the third lateral trench A3.

[0173] A fifteenth insulating film is deposited to form a fifteenth insulating layer 8 that fills the second trench T2;

[0174] Etching removes the hard mask layer 71; as shown in FIG12, FIG12 is a cross-sectional view along the aa' direction perpendicular to the substrate 1 after forming the reference signal line SL, the second gate insulating layer 24b and the first word line 41 according to some embodiments.

[0175] In some embodiments, the second word line 42 and the reference signal line SL can be formed simultaneously. Specifically, the twelfth insulating layer 22 and the sixth insulating layer 16 in the second trench T2 can be etched to expose the third dummy layer 63 and the second dummy layer 62. After etching away the third dummy layer 63 and the second dummy layer 62, the second word line 42 and the reference signal line SL are formed simultaneously. When manufacturing the second word line 42 and the reference signal line SL separately, different materials can be used for them.

[0176] 12) Forming the second position line 32;

[0177] A sixth conductive film is deposited on the substrate 1 forming the aforementioned structure. The sixth conductive film is patterned to form multiple second bit lines 32 extending along a first direction X and spaced apart along a second direction Y. The second bit lines 32 are connected to multiple second semiconductor layers 23b. Adjacent second bit lines 32 are separated by fifth trenches extending along the first direction X. The second bit lines 32 may be strip electrodes.

[0178] A sixteenth insulating film is deposited to form a sixteenth insulating layer 7 that fills the fifth trench, as shown in Figures 13A and 13B. Figure 13A is a top view after the formation of the second bit line 32 according to some embodiments, and Figure 13B is a cross-sectional view along the aa' direction perpendicular to the substrate 1 after the formation of the second bit line 32 according to some embodiments.

[0179] In some embodiments, the orthographic projection of the second bit line 32 onto the substrate 1 and the orthographic projection of the first bit line 31 onto the substrate 1 may overlap in order to minimize the area occupied by the device.

[0180] The solution provided in this disclosure can define the gate electrode length of the transistor by the thickness of the first dummy layer and the third dummy layer, which improves the uniformity of the process and realizes the self-aligned stacking of the first transistor and the second transistor. In addition, the parasitic removal between adjacent memory cells can be achieved by using the isolation region, without reserving extra space for parasitic removal, thereby further improving the memory cell density.

[0181] This disclosure also provides an electronic device, including the semiconductor device described in any of the foregoing embodiments, or a semiconductor device formed by the manufacturing method of the semiconductor device described in any of the foregoing embodiments. The electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0182] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A semiconductor device, comprising: At least one memory cell includes a first transistor and a second transistor stacked on a substrate in a direction perpendicular to the substrate, the second transistor being disposed on the side of the first transistor facing away from the substrate; the first transistor includes a first gate electrode, a second gate electrode, a first electrode, a second electrode, and a first semiconductor layer, the first semiconductor layer being connected to the first electrode and the second electrode respectively, the second electrode being disposed on the side of the first electrode facing away from the substrate; the second transistor includes a third gate electrode, a third electrode, and a second semiconductor layer; the second semiconductor layer is connected to the third electrode and the first gate electrode respectively, the third electrode being disposed on the side of the first gate electrode facing away from the substrate; the second semiconductor layer includes a metal oxide. The first semiconductor layer includes a first vertical portion extending in a direction perpendicular to the substrate; the second semiconductor layer includes a second vertical portion extending in a direction perpendicular to the substrate; the first gate electrode is distributed on the sidewall of the first vertical portion; The second gate electrode is distributed on the side wall of the first vertical part, and the third gate electrode is distributed on the side wall of the second vertical part; The first electrode and the third electrode extend along a first direction parallel to the substrate, and the second gate electrode and the third gate electrode extend along a second direction parallel to the substrate, wherein the first direction and the second direction intersect.

2. The semiconductor device according to claim 1, wherein, The first semiconductor layer further includes a first horizontal portion extending in a direction parallel to the substrate, the first horizontal portion being connected to the end of the first vertical portion facing the substrate. The second semiconductor layer further includes a second horizontal portion extending in a direction parallel to the substrate, the second horizontal portion being connected to the end of the second vertical portion facing the substrate. The first gate electrode is also distributed on the side of the first horizontal portion away from the substrate.

3. The semiconductor device according to claim 2, wherein, The first horizontal portion and the first vertical portion are distributed along the first direction, the second horizontal portion and the second vertical portion are distributed along the first direction, the orthographic projection of the first horizontal portion on the substrate overlaps with the orthographic projection of the second horizontal portion on the substrate, and the first vertical portion and the second vertical portion are disposed on the same side of the second horizontal portion.

4. The semiconductor device according to claim 1, wherein, The second electrode is disposed on the side of the second gate electrode away from the substrate, on the sidewall of the first vertical portion, and the second electrode extends along the second direction.

5. The semiconductor device according to claim 4, wherein, The orthographic projection of the second electrode onto the substrate overlaps with the orthographic projection of the third gate electrode onto the substrate.

6. The semiconductor device according to claim 2, wherein, The first electrode is connected to the side of the first horizontal portion facing the substrate, and the third electrode is connected to the side of the second vertical portion away from the substrate.

7. The semiconductor device according to claim 2 or 3, wherein, The memory cell further includes a first gate insulating layer disposed between the first semiconductor layer and the first gate electrode, extending continuously on the side of the first horizontal portion away from the substrate, the sidewall of the first vertical portion facing the first horizontal portion, and the side of the first vertical portion away from the substrate, and extending to cover the sidewall of the second vertical portion away from the second horizontal portion.

8. The semiconductor device according to claim 7, wherein, The orthographic projection of the first gate electrode, the first gate insulating layer, and the second semiconductor layer onto the substrate is located within the orthographic projection of the first semiconductor layer onto the substrate.

9. The semiconductor device according to any one of claims 1 to 6, wherein, The memory cell further includes a second gate insulating layer disposed on the sidewall of the first vertical portion. The second gate insulating layer forms a trench with an opening direction parallel to the substrate and away from the first semiconductor layer, and the second gate electrode fills the trench.

10. The semiconductor device according to claim 9, wherein, The semiconductor device includes at least one layer of memory cell array. Each layer of the memory cell array includes a plurality of memory cells distributed along the first direction and the second direction. The first electrodes of the first transistors of the memory cells in the same row of the same layer along the first direction are connected to form a first bit line of an integrated structure. The third electrodes of the second transistors of the memory cells in the same row of the same layer are connected to form a second bit line of an integrated structure. The second gate electrodes of the first transistors of the memory cells in the same column of the same layer along the second direction are connected to form a first word line of an integrated structure. The third gate electrodes of the second transistors of the memory cells in the same column of the same layer are connected to form a second word line of an integrated structure. The second electrodes of the first transistors in the same column of the same layer are connected to form a reference signal line of an integrated structure.

11. The semiconductor device according to claim 10, wherein, The second gate insulating layer of the first transistor of the memory cell in the same layer and column is connected to form an integral structure.

12. The semiconductor device according to claim 10, wherein, The storage cells of each pair of adjacent columns are distributed in a mirror-symmetric manner along the first direction.

13. A method for manufacturing a semiconductor device, comprising: A first electrode is formed on the substrate, extending in a first direction parallel to the substrate; A first semiconductor layer connected to the first electrode is formed on the side of the first electrode away from the substrate. The first semiconductor layer includes a first vertical portion extending in a direction perpendicular to the substrate. A first gate electrode is formed, spaced apart from the first semiconductor layer and distributed on the sidewall of the first vertical portion; A second semiconductor layer connected to the first gate electrode is formed on the side of the first gate electrode facing away from the substrate; the second semiconductor layer includes a second vertical portion extending in a direction perpendicular to the substrate; A third electrode is formed on the side of the second semiconductor layer away from the substrate, which is connected to the second semiconductor layer and extends along the first direction; A second electrode connected to the first semiconductor layer is formed on the side of the first electrode away from the substrate. A second gate electrode extending in a second direction parallel to the substrate is formed on the sidewall of the first vertical portion. A third gate electrode extending in the second direction is formed on the sidewall of the second vertical portion. The first direction and the second direction intersect.

14. The method for manufacturing a semiconductor device according to claim 13, wherein, The formation of the first electrode on the substrate, extending in a first direction parallel to the substrate, includes: Multiple first bit lines extending along the first direction and spaced apart along the second direction are formed on the substrate, and each first bit line includes multiple first electrodes; The step of forming a first semiconductor layer connected to the first electrode on the side of the first electrode away from the substrate, forming a first gate electrode spaced apart from the first semiconductor layer and distributed on the sidewall of the first vertical portion, and forming a second semiconductor layer connected to the first gate electrode on the side of the first gate electrode away from the substrate includes: A first dummy layer, a second dummy layer, and a third dummy layer are formed on the side of the first bit line away from the substrate, stacked sequentially and spaced apart along a direction perpendicular to the substrate; the first dummy layer, the second dummy layer, and the third dummy layer extend along the second direction, and the orthographic projections of the first dummy layer, the second dummy layer, and the third dummy layer on the substrate overlap with the orthographic projections of the multiple first bit lines on the substrate; A first isolation trench is formed that penetrates the first dummy layer, the second dummy layer, and the third dummy layer in a direction perpendicular to the substrate and extends in the second direction. The bottom wall of the first isolation trench exposes multiple first bit lines, and the two oppositely arranged sidewalls of the first isolation trench expose the first dummy layer, the second dummy layer, and the third dummy layer. A first semiconductor structure layer is formed covering the bottom wall and part of the sidewall of the first isolation trench. The first semiconductor structure layer covers a region on the sidewall of the first isolation trench that is less than or equal to a first preset height from the substrate. The first preset height is greater than the distance between the surface of the second dummy layer away from the substrate and the substrate, and less than the distance between the surface of the third dummy layer facing the substrate and the substrate. A first gate insulating structure layer and a first gate electrode structure layer are formed to sequentially cover the bottom wall and side wall of the first isolation trench on which the first semiconductor structure layer is formed. A first isolation layer is filled into the first isolation trench. The first gate electrode structure layer and the first isolation layer are etched back to a position at a distance of a second preset height from the substrate to form a first sub-trench. The second preset height is greater than the first preset height and less than the distance between the surface of the third dummy layer facing the substrate and the substrate. A second semiconductor structure layer is formed covering the bottom and sidewalls of the first sub-trench; A second isolation trench is formed, the second isolation trench including a second sub-trench extending along the second direction and a plurality of third sub-trenches extending along the first direction and spaced apart along the second direction. The second sub-trench divides the first semiconductor structure layer, the first gate insulating structure layer, the first gate electrode structure layer and the second semiconductor structure layer into two independent parts along the second direction. The third sub-trench divides each part into multiple segments spaced apart along the second direction. Each segment includes a first semiconductor layer, a first gate insulating layer, a first gate electrode and a second semiconductor layer of a memory cell.

15. The method for manufacturing a semiconductor device according to claim 14, wherein, The second electrode, which is connected to the first semiconductor layer, is formed on the side of the first electrode opposite to the substrate. Remove the second dummy layer to form a second lateral trench, and form a reference signal line disposed in the second lateral trench and connected to a plurality of first semiconductor layers, the reference signal line including a plurality of second electrodes; The method of forming a second gate electrode extending in a second direction parallel to the substrate on the sidewall of the first vertical portion and forming a third gate electrode extending in the second direction on the sidewall of the second vertical portion includes: removing the third dummy layer, forming a first transverse trench, forming a second word line disposed in the first transverse trench, the second word line including a plurality of the third gate electrodes; The first dummy layer is removed to form a third lateral trench, a second gate insulating layer is formed to cover the inner wall of the third lateral trench, and a first word line is formed to fill the third lateral trench. The first word line includes a plurality of second gate electrodes.

16. An electronic device comprising a semiconductor device as claimed in any one of claims 1 to 12, or a semiconductor device formed by a method of manufacturing a semiconductor device according to any one of claims 13 to 15.

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