Semiconductor memory device

Abstract

Embodiments provide a semiconductor storage device that can be appropriately manufactured. The semiconductor storage device of the embodiments includes a substrate, a plurality of first conductive layers arranged in a first direction intersecting a surface of the substrate, a first semiconductor layer extending in the first direction and facing the plurality of first conductive layers, a first gate insulating film extending in the first direction and covering an outer peripheral surface of the first semiconductor layer, a first insulating layer extending in the first direction and having an outer peripheral surface covered by the first semiconductor layer, and a second conductive layer connected to one end of the first semiconductor layer in the first direction and farther from the substrate than the plurality of first conductive layers. The first semiconductor layer includes a first region facing the plurality of first conductive layers and a second region farther from the substrate than the first region. The second conductive layer is connected to an inner peripheral surface and the outer peripheral surface of the second region of the first semiconductor layer and is in contact with one end of the first insulating layer in the first direction.

Description

[0001] [Related Applications]

[0002] This application claims priority to Japanese Patent Application No. 2020-146059 (filed on August 31, 2020). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] This embodiment relates to a semiconductor memory device. Background Technology

[0004] A known semiconductor memory device comprises: a substrate; a plurality of conductive layers stacked in a direction intersecting the surface of the substrate; a semiconductor layer opposite to the plurality of conductive layers; and a gate insulating layer disposed between the conductive layers and the semiconductor layer. The gate insulating layer may be, for example, a charge storage layer with insulating properties such as silicon nitride (Si3N4), a conductive charge storage layer such as a floating gate, or a memory section capable of storing data. Summary of the Invention

[0005] The embodiments provide a semiconductor memory device that can be suitably manufactured.

[0006] One embodiment of a semiconductor memory device includes: a substrate; a plurality of first conductive layers arranged in a first direction intersecting a surface of the substrate; a first semiconductor layer extending in the first direction and opposing the plurality of first conductive layers; a first gate insulating film extending in the first direction and covering an outer peripheral surface of the first semiconductor layer; a first insulating layer extending in the first direction, the outer peripheral surface of which is covered by the first semiconductor layer; and a second conductive layer located farther from the substrate than the plurality of first conductive layers and connected to one end of the first semiconductor layer in the first direction. The first semiconductor layer includes a first region opposing the plurality of first conductive layers and a second region located farther from the substrate than the first region. The second conductive layer is connected to the inner and outer peripheral surfaces of the second region of the first semiconductor layer and is in contact with one end of the first insulating layer in the first direction. Attached Figure Description

[0007] Figure 1 This is a schematic perspective view showing the structure of the memory die MD according to the first embodiment.

[0008] Figure 2 This indicates that chip C M A schematic bottom view of the structure.

[0009] Figures 3-9 This indicates that chip C M A schematic bottom view of part of the structure.

[0010] Figures 10-28This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0011] Figure 29 This is a schematic cross-sectional view used to illustrate the structure of the semiconductor memory device according to the second embodiment.

[0012] Figure 30 , Figure 31 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the second embodiment.

[0013] Figure 32 This is a schematic cross-sectional view used to illustrate the structure of the semiconductor memory device according to the third embodiment.

[0014] Figure 33 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0015] Figure 34 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the fourth embodiment.

[0016] Explanation of reference numerals in the attached figures

[0017] 110…conductive layer, 120…semiconductor layer, 125…insulating layer, 130…gate insulating film, 141…conductive layer, 150…conductive layer. Detailed Implementation

[0018] Next, the semiconductor memory device according to the embodiments will be described in detail with reference to the accompanying drawings. Furthermore, the following embodiments are merely examples and are not intended to limit the scope of the invention. Additionally, the following drawings are schematic, and for ease of explanation, some structures may be omitted. Furthermore, common parts in multiple embodiments are labeled with the same reference numerals, and descriptions may sometimes be omitted.

[0019] Additionally, when "semiconductor memory device" is mentioned in this specification, it sometimes means a memory die, and sometimes it means a memory system including a controller die, such as a memory chip, memory card, or SSD (Solid State Drive). Furthermore, it sometimes also means a structure including a mainframe computer, such as a smartphone, tablet, or personal computer.

[0020] Furthermore, in this specification, when it is said that the first structure and the second structure are "electrically connected," it can mean that the first structure and the second structure are directly connected, or that the first structure is connected to the second structure via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in the off state, the first transistor is still "electrically connected" to the third transistor.

[0021] In addition, in this specification, the direction parallel to the upper surface of the substrate is referred to as the X direction, the direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and the direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0022] Furthermore, in this specification, the direction along a specified surface is sometimes referred to as the first direction, the direction along the specified surface and intersecting the first direction is referred to as the second direction, and the direction intersecting the specified surface is referred to as the third direction. These first, second, and third directions may or may not correspond to any of the X, Y, and Z directions.

[0023] Furthermore, in this specification, the terms "upper" and "lower" are used with reference to the substrate. For example, the direction away from the substrate along the Z direction is called "upper," and the direction approaching the substrate along the Z direction is called "lower." Additionally, when referring to a certain structure as a lower surface or lower end, it means the surface or end of that structure on the substrate side; when referring to it as an upper surface or upper end, it means the surface or end of the side opposite to the substrate of that structure. Furthermore, surfaces intersecting the X or Y direction are called side surfaces, etc.

[0024] In addition, in this specification, the terms “width,” “length,” or “thickness” used to refer to a specified direction in relation to a component or part sometimes mean the width, length, or thickness of a cross-section or the like as observed using SEM (Scanning electron microscopy) or TEM (Transmission electron microscopy).

[0025] [First Implementation Method]

[0026] [Structure of memory die MD]

[0027] Figure 1 This is a schematic exploded perspective view showing a structural example of the semiconductor memory device according to this embodiment. The semiconductor memory device of this embodiment includes a memory die MD. The memory die MD includes a chip C containing an array of memory cells. M and chip C containing peripheral circuits P .

[0028] In chip C M The upper surface is provided with multiple bonding pad electrodes P X Additionally, in chip C... M Multiple first bonding electrodes P are provided on the lower surface. I1 Additionally, in chip C... P Multiple second bonding electrodes P are provided on the upper surface. I2 The following is about chip C. M Multiple first bonding electrodes P will be provided. I1 The surface is called the surface, and multiple bonding pad electrodes P will be provided thereon. X The side facing out is called the back side. Additionally, regarding chip C... P Multiple second bonding electrodes P will be provided. I2 The side facing out is called the surface, and the side opposite the surface is called the back surface. In the illustrated example, chip C P The surface is set on the chip C P On the back, near the top, chip C M The back is set on the chip C M The surface is on the upper part.

[0029] Chip C M and chip C P With chip C M Surface and chip C P The surfaces are arranged in an opposing manner. Multiple first bonding electrodes P I1 With multiple second bonding electrodes P I2 They are respectively set and configured to be able to attach to multiple second bonding electrodes P. I2 The bonding position. First bonding electrode P I1 Second bonding electrode P I2 As for using chip C M With chip C P The bonding electrodes, which are attached and electrically conductive, function by bonding. Bonding pad electrode P X It functions as an electrode for electrically connecting memory die MD to controller die (not shown).

[0030] In addition, Figure 1 In the example, chip C M The corners a1, a2, a3, and a4 are respectively connected to chip C P The corners b1, b2, b3, and b4 correspond.

[0031] Figure 2 This indicates that chip C M A schematic bottom view of the structure. Figure 3 It is Figure 2 The diagram shows a schematic bottom view of the enlarged structure of part A. Figure 4 It is Figure 3 The structure shown is a schematic cross-sectional view cut along line BB′ and viewed in the direction of the arrow. Figure 5 It is Figure 4 The diagram shows a schematic cross-sectional view of the enlarged structure of part C. Figure 6 It is Figure 3 The structure shown is a schematic cross-sectional view cut along line DD′ and viewed in the direction of the arrow. Figure 7 It is Figure 3 The structure shown is a schematic cross-sectional view cut along lines EE′ and FF′ and viewed in the direction of the arrows. Additionally, in Figure 7 The outer periphery R of the memory cell array, which will be described later, is also shown in the diagram. MCAE The structure. Figure 8 This is a schematic cross-sectional view showing a portion of the structure of the semiconductor memory device. Figure 9 It is Figure 2 The structure shown is a schematic cross-sectional view cut along line GG′ and viewed in the direction of the arrow.

[0032] [Chip C] M [Structure]

[0033] Chip C M For example, Figure 2 As shown, an array region R has four memory cells arranged along the X and Y directions. MCA Along the memory cell array region R MCA The outer periphery of the memory cell array is set in the outer periphery region R. MCAE , and multiple bonding pad electrodes P X The corresponding multiple bonding pad electrode regions R PX and along chip C M The outer edge sealing area R is provided E .

[0034] Storage cell array region R MCA It includes: multiple storage blocks (BLKs) arranged along the Y direction, and multiple inter-block structures (140) respectively disposed between these multiple storage blocks (BLKs). Figure 3 ), and a conductive layer 150 disposed on the upper surface of multiple storage blocks BLK and multiple inter-block structures 140. Figure 4 Additionally, a wiring layer 160 is provided below these multiple storage block BLKs. Furthermore, a wiring layer 170 is provided above the conductive layer 150.

[0035] Storage block BLK, for example Figure 3 As shown, it has: a storage hole area R MH , Set in the X direction at the storage hole area RMH Through contact area R at different locations 180 and in the X direction, it is positioned relative to the storage hole area R. MH and the through contact area R 180 Hook-up regions R at different locations 190 .

[0036] Storage hole area R of storage block BLK MH For example, Figure 4 As shown, it includes: a plurality of conductive layers 110 arranged along the Z direction, a plurality of semiconductor layers 120 extending along the Z direction, and a plurality of gate insulating films 130 disposed between the plurality of conductive layers 110 and the plurality of semiconductor layers 120.

[0037] The conductive layer 110 is a generally plate-shaped conductive layer extending along the X direction. The conductive layer 110 functions, for example, as a word line and the gate electrode of a plurality of memory cells connected thereto. The conductive layer 110 may comprise a laminate of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). Alternatively, the conductive layer 110 may also comprise, for example, polycrystalline silicon containing N-type impurities such as phosphorus (P) or P-type impurities such as boron (B). An insulating layer 101, such as silicon oxide (SiO2), is disposed between the plurality of conductive layers 110 arranged along the Z direction. Furthermore, an insulating layer 102, such as silicon oxide (SiO2), is disposed on the upper surface of the uppermost conductive layer 110. In the illustrated example, the thickness of the insulating layer 102 in the Z direction is greater than the thickness of the insulating layer 101 in the Z direction.

[0038] Semiconductor layer 120, for example Figure 3 As shown, the semiconductor layer 120 is arranged in a prescribed pattern along the X and Y directions. The semiconductor layer 120 functions, for example, as a channel region for multiple memory cells. The semiconductor layer 120 is, for example, a polysilicon (Si) semiconductor layer. The semiconductor layer 120 is, for example, as... Figure 4 As shown, it has a roughly cylindrical shape with a bottom, and an insulating layer 125 such as silicon oxide is provided in the central part. Figure 5 In addition, the outer peripheral surfaces of the semiconductor layer 120 are surrounded by conductive layers 110, which are opposite to the conductive layers 110.

[0039] An impurity region containing N-type impurities such as phosphorus (P) is provided at the lower end of the semiconductor layer 120. This impurity region covers the lower end of the insulating layer 125. Furthermore, this impurity region is electrically connected to the bit line BL in the wiring layer 160. The bit line BL is connected via the aforementioned first bonding electrode P. I1 And with chip C P Internal structural electrical connections.

[0040] An impurity region containing N-type impurities such as phosphorus (P) or P-type impurities such as boron (B) is formed at the upper end of the semiconductor layer 120. This impurity region is generally cylindrical, with its upper end positioned above the upper surface of the insulating layer 102 and the upper end of the insulating layer 125. A portion of the outer peripheral surface of this impurity region contacts the gate insulating film 130, and a portion positioned above it is bonded to the conductive layer 150. Similarly, a portion of the inner peripheral surface of the impurity region contacts the insulating layer 125, and a portion positioned above it is bonded to the conductive layer 150. The upper end of the impurity region is bonded to the conductive layer 150.

[0041] The gate insulating film 130 has a generally cylindrical shape that covers the outer peripheral surface of the semiconductor layer 120. The gate insulating film 130 is, for example, as shown in... Figure 5 As shown, a tunnel insulating film 131, a charge storage film 132, and a barrier insulating film 133 are stacked between a semiconductor layer 120 and a conductive layer 110. The tunnel insulating film 131 and the barrier insulating film 133 are, for example, insulating films such as silicon oxide (SiO2). The charge storage film 132 is, for example, a film capable of storing charge such as silicon nitride (Si3N4). The tunnel insulating film 131, the charge storage film 132, and the barrier insulating film 133 have a generally cylindrical shape and extend along the outer peripheral surface of the semiconductor layer 120 in the Z direction.

[0042] In addition, Figure 5 The example shown is a gate insulating film 130 having a charge storage film 132 such as silicon nitride. However, the gate insulating film 130 may also have a floating gate such as polysilicon containing N-type or P-type impurities.

[0043] Inter-block structure 140, for example, Figure 4 As shown, the system includes a conductive layer 141 extending along the Z and X directions, and an insulating layer 142, such as silicon oxide (SiO2), disposed on the Y-direction side surface of the conductive layer 141. The conductive layer 141 may, for example, comprise a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The conductive layer 141 functions as part of a source line, for example. Furthermore, the upper end of the conductive layer 141 is located above the upper surface of the insulating layer 102. Additionally, the upper end of the conductive layer 141 and its two side surfaces in the X direction are bonded to the conductive layer 150.

[0044] The conductive layer 150 may, for example, comprise a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). Alternatively, the conductive layer 150 may comprise polycrystalline silicon containing N-type impurities such as phosphorus (P) or P-type impurities such as boron (B). The conductive layer 150 functions as part of a source line, for example.

[0045] The conductive layer 150 contacts the upper surface of the insulating layer 102, the upper end of the semiconductor layer 120, the upper end of the insulating layer 125, and the upper end of the conductive layer 141. The portion of the conductive layer 150 covering the upper surface of the insulating layer 102 is formed to be generally flat along the upper surface of the insulating layer 102. Furthermore, the portion of the conductive layer 150 covering the upper end of the semiconductor layer 120 and the upper end of the insulating layer 125 protrudes upward along the shape of the upper end of the semiconductor layer 120. Multiple such protrusions are provided in the X and Y directions corresponding to the semiconductor layer 120. Additionally, the portion of the conductive layer 150 covering the upper end of the conductive layer 141 protrudes upward along the shape of the upper end of the conductive layer 141. Multiple such protrusions are provided in the Y direction corresponding to the conductive layer 141 and extend along the X direction.

[0046] Through contact area R of storage block BLK 180 For example Figure 3 As shown, it has two wiring regions R arranged along the Y direction. 181 , Set in these two wiring areas R 181 The small contact area R between them 182 and the wiring area R 181 With the small contact area R 182 The insulating layer 180 between the silicon oxide (SiO2) and other materials.

[0047] Wiring area R of storage block BLK 181 For example, Figure 6 As shown, the system includes a plurality of conductive layers 110 arranged along the Z-direction. The side surfaces of these conductive layers 110 in the Y-direction are respectively in contact with the insulating layer 180. These conductive layers 110 are, for example, as shown in the diagram. Figure 3 As shown, it is located in the storage hole area R MH A portion of the multiple conductive layers 110. Additionally, as... Figure 6 As shown, in the wiring area R 181 In this process, a portion of a conductive layer 150 is provided on the upper surface of the insulating layer 102.

[0048] The small contact area R of the storage block BLK 182 For example, Figure 6 As shown, it includes: multiple insulating layers 110A arranged along the Z direction, and contact elements 181 extending along the Z direction. Additionally, in the through-contact area R of the storage block BLK... 182 A conductive layer 151 is provided.

[0049] The insulating layer 110A is a generally plate-shaped insulating layer extending along the X direction. The side surfaces of these multiple insulating layers 110A in the Y direction are in contact with the insulating layer 180. The insulating layer 110A is, for example, an insulating layer of silicon nitride (Si3N4). An insulating layer 101, such as silicon oxide (SiO2), is provided between the multiple insulating layers 110A arranged along the Z direction. Furthermore, an insulating layer 102, such as silicon oxide (SiO2), is provided on the upper surface of the uppermost insulating layer 110A.

[0050] Contact 181, for example Figure 3 As shown, they are arranged at predetermined intervals along the X direction. Contacts 181 may also include, for example, a laminate of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). For example, as... Figure 6 As shown, contact 181 is connected via wiring 161 in wiring layer 160 and the first bonding electrode P. I1 And with chip C P The internal structure is electrically connected. Furthermore, the upper end of contact 181 is located above the upper surface of insulating layer 102. Additionally, the outer peripheral surface and upper end of the upper end of contact 181 are in contact with conductive layer 151. Contact 181 connects to, for example, bonding pad electrode P via conductive layer 151 and wiring 171 in wiring layer 170. X Equivalent electrical connection.

[0051] Conductive layer 151 is constructed in essentially the same manner as conductive layer 150. However, conductive layer 151 is electrically independent of conductive layer 150. Furthermore, conductive layer 151 contacts the upper surface of insulating layer 102 and the upper end of contact 181. The portion of conductive layer 151 covering the upper surface of insulating layer 102 is formed to be generally flat along the upper surface of insulating layer 102. Additionally, the portion of conductive layer 151 covering the upper end of contact 181 protrudes upward along the shape of the upper end of contact 181. Multiple conductive layers 151 and contacts 181 are provided correspondingly along the X-direction.

[0052] The connected region R of storage block BLK 190 For example, Figure 7 As shown, it includes: a plurality of conductive layers 110 arranged along the Z direction, and a contact 191 extending along the Z direction.

[0053] Connected region R 190 Multiple conductive layers 110 in, for example, Figure 3 As shown, it is in the storage hole area R MH A portion of the plurality of conductive layers 110 are provided. For example, such as Figure 7As shown, each layer has a region that overlaps with at least one of the lower conductive layers 110 when viewed from the Z direction, and a region that does not overlap with any of the lower conductive layers 110. Hereinafter, such a structure will sometimes be referred to as a generally stepped structure.

[0054] Contact 191, for example Figure 3 As shown, they are arranged at predetermined intervals in the X and Y directions. Contact 191 may also include, for example, a laminate of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). For example, as... Figure 7 As shown, the lower end of the contact 191 is connected to the wiring 161 in the wiring layer 160 and the first bonding electrode P. I1 And with chip C P The internal structure is electrically connected. In addition, the upper end of the contact 191 is in contact with a portion of the conductive layer 110.

[0055] outer perimeter region R of the memory cell array MCAE For example, Figure 7 As shown, it includes a portion of insulating layer 102. Insulating layer 102 is, for example, as shown in the diagram. Figure 7 As shown, it has a feature located in the storage cell array region R MCA The inner portion 102I and the portion located in the memory cell array region R MCA The outer portion 102O. The thickness of portion 102O in the Z direction is less than the thickness of portion 102I in the Z direction. Furthermore, a step 102S is formed at the connection between portion 102I and portion 102O. The step 102S, for example, runs along the memory cell array region R. MCA The outer edge setting.

[0056] Additionally, the outer periphery region R of the memory cell array MCAE For example, Figure 8 As shown, it includes a contact 185 extending along the Z direction. The contact 185 may, for example, comprise a laminate of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The contact 185 is connected to the first bonding electrode P via wiring 161 in the wiring layer 160. I1 And with chip C P The internal structure is electrically connected. Furthermore, the upper end of the contact 185 contacts the conductive layer 150. Additionally, the position of the contact 185 can be adjusted appropriately.

[0057] Bonding pad electrode area R PX For example, Figure 9 As shown, it includes: a contact 186 extending in the Z direction, a conductive layer 152 contacting the upper end of the contact 186, and a bonding pad electrode P electrically connected to the conductive layer 152. X .

[0058] Contact 186 may, for example, comprise a laminate of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). Contact 186 is connected via wiring 161 in wiring layer 160 and a first bonding electrode P. I1 And with chip C P The internal structure is electrically connected. Additionally, the upper end of contact 186 contacts the conductive layer 152.

[0059] Conductive layer 152 is constructed in essentially the same manner as conductive layer 150. However, conductive layer 152 is electrically independent of conductive layer 150. Furthermore, conductive layer 152 contacts the upper surface of insulating layer 102 and the upper end of contact 186. The portion of conductive layer 152 covering the upper surface of insulating layer 102 is formed to be generally flat along the upper surface of insulating layer 102. Additionally, the portion of conductive layer 152 covering the upper end of contact 186 protrudes upward along the shape of the upper end of contact 186. Conductive layer 152 connects to the bonding pad electrode P. X Correspondingly, multiple [items] are set along the X direction.

[0060] Bonding pad electrode P X Examples include laminated films containing barrier conductive films such as titanium nitride (TiN) and metal films such as aluminum (Al). Bonding pad electrode P X A portion of the upper surface is covered by an insulating layer 103 such as polyimide. Additionally, the bonding pad electrode P... X A portion of the upper surface is exposed to the outside of the memory die MD through an opening provided in the insulating layer 103. Additionally, the bonding pad electrode P... X A portion of the lower surface contacts wiring 171 in wiring layer 170. Bonding pad electrode P X The chip C is connected via wiring 171, conductive layer 152, and contact 186. P Internal structural electrical connections.

[0061] Edge sealing area R E For example, Figure 9 As shown, it includes a contact 187 extending along the Z direction, a conductive layer 153 contacting the upper end of the contact 187, and a dummy electrode P electrically connected to the conductive layer 153. XD Contact 187, conductive layer 153, and dummy electrode P XD Contact 186, conductive layer 152 and bonding pad electrode P respectively X They are constructed in a largely similar manner. However, the contact 187, conductive layer 153, and virtual electrode P are different. XDDesigned for ease of manufacturing, it functions neither as part of the memory cell array nor as part of the peripheral circuitry. Contact 187, conductive layer 153, and dummy electrode P XD It is also possible to not be connected to chip C P Internal structural electrical connections.

[0062] [Chip C] P [Structure]

[0063] Chip C P For example, Figure 4 As shown, it includes a semiconductor substrate 200 and a plurality of transistors Tr disposed on the surface of the semiconductor substrate 200. These plurality of transistors Tr are connected via the aforementioned second bonding electrode P. I2 With chip C M The internal structure is connected and functions as peripheral circuitry used in the control of the memory cell array. For example, during a read operation, this peripheral circuitry supplies voltage to the current path including bit line BL, semiconductor layer 120, conductive layer 150, and conductive layer 141, and determines the data recorded in the memory cell based on whether current flows through it.

[0064] [Manufacturing Method]

[0065] Next, refer to Figures 10-28 The manufacturing method of memory die MD is explained. Figures 10-28 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0066] Figure 12 , Figures 16-22 , Figure 24 , Figure 26 and Figure 28 Indicates and Figure 4 The corresponding cross section. Figure 10 , Figure 11 , Figures 13 to 15 , Figure 23 , Figure 25 and Figure 27 Indicates and Figure 7 The corresponding cross section.

[0067] When manufacturing the memory die MD of this embodiment, for example, Figure 10 As shown, in chip W M An insulating layer 104, such as silicon oxide (SiO2), is formed on a semiconductor substrate 100. In this process, the insulating layer 104 is formed, for example, by a method such as CVD (Chemical Vapor Deposition). Furthermore, the insulating layer 104 is deposited in the memory cell array region R using methods such as RIE (Reactive Ion Etching) or wet etching. MCARemove the insulation layer 104 from the outer region.

[0068] Next, for example, such as Figure 11 As shown, a conductive layer 111 and an insulating layer 102 are formed on the upper surfaces of the insulating layer 104 and the semiconductor substrate 100. The conductive layer 111 may, for example, comprise a laminate of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). Alternatively, the conductive layer 111 may also comprise, for example, polycrystalline silicon containing N-type impurities such as phosphorus (P) or P-type impurities such as boron (B). This process is performed, for example, by a method such as CVD.

[0069] Next, for example, Figure 12 and Figure 13 As shown, multiple insulating layers 110A and insulating layer 101 are formed on the upper surface of insulating layer 102. This process is performed, for example, by a method such as CVD.

[0070] Next, for example, Figure 14 As shown, multiple insulating layers 110A and a portion of insulating layer 101 are removed to form a generally stepped structure. In this process, for example, a region R covering the memory cell array is formed. MCA ( Figure 2 The photoresist is applied. Next, a portion of the insulating layer 110A is selectively removed using a method such as RIE with the photoresist as a mask or wet etching. Next, a portion of the insulating layer 101 is selectively removed using a method such as RIE with the photoresist as a mask or wet etching. Next, a portion of the photoresist is isotropically removed using a method such as wet etching. Similarly, a portion of the insulating layer 110A, a portion of the insulating layer 101, and a portion of the photoresist are removed sequentially thereafter.

[0071] Next, for example, Figure 15 As shown, in Figure 14 An insulating layer 105, such as silicon oxide (SiO2), is formed on the upper surface of the stepped structure shown. This process is performed, for example, by a method such as CVD.

[0072] Next, for example, Figure 16 As shown, a plurality of through holes 120A are formed at positions corresponding to the semiconductor layer 120. The through holes 120A are through holes that extend along the Z direction and penetrate the insulating layer 101 and the insulating layer 110A, exposing the upper surface of the conductive layer 111. This process is performed, for example, by a method such as RIE.

[0073] Next, for example, Figure 17 As shown, a gate insulating film 130, a semiconductor layer 120, and an insulating layer 125 are formed on the inner peripheral surface of the through-hole 120A. This process is performed, for example, by a method such as CVD.

[0074] Next, for example, Figure 18 As shown, a groove 140A is formed. The groove 140A extends along the Z and X directions and cuts off the insulating layer 101 and the insulating layer 110A along the Y direction, exposing the upper surface of the conductive layer 111. This process is performed, for example, by a method such as RIE.

[0075] Next, for example, Figure 19 As shown, a conductive layer 110 is formed. In this process, the insulating layer 110A is removed via the tank 140A by methods such as wet etching. Alternatively, the conductive layer 110 is formed by methods such as CVD.

[0076] Next, for example, Figure 20 As shown, an inter-block structure 140 is formed within the groove 140A. This process is performed, for example, by methods such as CVD and RIE.

[0077] Next, for example, Figure 21 As shown, wiring layer 160 (bit line BL) and first bonding electrode P are formed. I1 This process is carried out, for example, by methods such as CVD, photolithography, and etching.

[0078] Next, for example, Figure 22 and Figure 23 As shown, it will be connected to chip C M The corresponding chip W M and chip C P The corresponding chip W P Bonding. In this bonding process, for example, by bonding the wafer W... M Towards chip W P Pressing causes the chip W M With chip W P The parts are sealed together and subjected to heat treatment, etc. Thus, via the first bonding electrode P... I1 and the second bonding electrode P I2 chip W M Attached to chip W P .

[0079] Next, for example, Figure 24 as well as Figure 25 As shown, the chip W M The semiconductor substrate 100 and conductive layer 111 are removed. Additionally, the insulating layer 102, gate insulating film 130, and a portion of the semiconductor layer 120 are removed, exposing the upper ends of the semiconductor layer 120 and insulating layer 125. This process is performed, for example, by wet etching or RIE.

[0080] Next, for example, such as Figure 26 and Figure 27As shown, a portion of insulating layer 102 and insulating layer 125 are removed. This process is performed, for example, by performing RIE (Removal of Insulation Layer) under conditions where silicon oxide (SiO2) is easier to remove than silicon (Si) and tungsten (W). Through this process, the upper ends of semiconductor layer 120, conductive layer 141, and contacts (not shown) are positioned above the upper surface of insulating layer 102.

[0081] Next, in Figure 26 and Figure 27 The upper end of the semiconductor layer 120 in the structure shown is implanted with N-type impurities such as phosphorus (P) or P-type impurities such as boron (B). Furthermore, heat treatment or the like is performed to bond the implanted impurities with the silicon (Si) in the semiconductor layer 120.

[0082] Next, for example, Figure 28 As shown, in Figure 26 and Figure 27 A conductive layer 150A is formed on the upper surface of the structure shown. This process is performed, for example, by a method such as CVD.

[0083] Next, Figure 28 The conductive layer 150A of the structure shown is cut into multiple parts. This process is performed, for example, by a method such as RIE. Through this process, the conductive layer 150 ( Figure 4 ), conductive layer 151 ( Figure 6 ), conductive layer 152 ( Figure 9 ) and conductive layer 153 ( Figure 9 ).

[0084] Then, a wiring layer 170 is formed on top of this structure, and bonding pad electrodes P are formed. X Wait, and cut the chip W M W P The structure formed by bonding together thus creates the memory die (MD).

[0085] [Effect]

[0086] A semiconductor memory device can be formed by forming a memory cell array on one wafer, forming peripheral circuitry on other wafers, and then bonding these wafers together. In forming a semiconductor memory device in this way, for example, a portion of the semiconductor substrate contained in the wafer on the memory cell array side can be used as part of the source line.

[0087] When forming a semiconductor memory device using this method, sometimes through-holes need to be formed on the semiconductor substrate containing the wafer, for example, on the memory cell array side, during the formation of bonding pad electrodes, exposing wiring and other traces contained in the wafer. However, using this method requires forming through-holes with a large aspect ratio on the semiconductor substrate, which sometimes leads to increased manufacturing costs.

[0088] Therefore, in this embodiment, when referring to Figure 24 and Figure 25 In the described process, the semiconductor substrate 100 is removed, exposing the upper end of the semiconductor layer 120. Furthermore, in subsequent processes, a conductive layer 150 is formed that connects to the upper end of the semiconductor layer 120. According to this method, as described above, in forming the bonding pad electrode P... X In this case, it is not necessary to form through holes with a large aspect ratio. Therefore, it is possible to suppress the increase in manufacturing costs.

[0089] In addition, in this embodiment, when referring to Figure 26 and Figure 27 In the described process, a portion of insulating layer 102 and insulating layer 125 is removed to form a structure in which the upper end of semiconductor layer 120 is located above the upper surface of insulating layer 102 and the upper end of insulating layer 125. Additionally, in reference... Figure 28 In the described process, a conductive layer 150 is formed on the outer and inner peripheral surfaces of the upper end of the semiconductor layer 120. According to this method, compared to, for example, not performing... Figure 26 as well as Figure 27 Compared to the process shown, the contact area between the semiconductor layer 120 and the conductive layer 150 can be increased. Therefore, the contact resistance between the semiconductor layer 120 and the conductive layer 150 can be significantly reduced.

[0090] In addition, in this embodiment, when referring to Figure 11 In the described process, a conductive layer 111 is formed that contacts the upper surface of the semiconductor substrate 100. Additionally, in the reference... Figure 16 In the described process, the through-hole 120A is formed such that the conductive layer 111 is exposed on the bottom surface of the through-hole 120A. According to this method, when the through-hole 120A is formed, the charge accumulated on the inner peripheral surface of the through-hole 120A can be discharged through the conductive layer 111. Therefore, arc discharge that may occur due to such charge, and the resulting structural damage, can be suppressed, thereby enabling the proper manufacture of a semiconductor memory device.

[0091] [Second Implementation]

[0092] Next, refer to Figure 29 The structure of the semiconductor memory device according to the second embodiment will be described. Figure 29 This is a schematic cross-sectional view used to illustrate the structure of the semiconductor memory device according to the second embodiment.

[0093] The semiconductor memory device of the second embodiment is configured in basically the same way as the semiconductor memory device of the first embodiment. However, the semiconductor memory device of the second embodiment has a conductive layer 250 instead of a conductive layer 150.

[0094] The conductive layer 250 includes a plurality of conductive portions 251 disposed corresponding to the semiconductor layer 120, a plurality of conductive portions 252 disposed corresponding to the conductive layer 141, and conductive portions 253 covering the upper surfaces of the plurality of conductive portions 251 and 252. The conductive layer 250 functions, for example, as part of a source line.

[0095] The conductive portion 251 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). Alternatively, the conductive portion 251 may include, for example, polycrystalline silicon containing N-type impurities such as phosphorus (P) or P-type impurities such as boron (B). The conductive portion 251 is bonded to the upper end, outer peripheral surface, and inner peripheral surface of the upper end of the semiconductor layer 120, respectively. Furthermore, the conductive portion 251 is in contact with the upper end of the insulating layer 125.

[0096] The conductive portion 252 may, for example, be made of the same material as the conductive portion 251. The conductive portion 252 contacts the upper end of the upper end of the conductive layer 141 and the side surface in the X direction, and extends along the upper end of the conductive layer 141 in the X direction.

[0097] The conductive portion 253 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). Alternatively, the conductive portion 253 may also include polycrystalline silicon containing N-type impurities such as phosphorus (P) or P-type impurities such as boron (B). The conductive portion 253 may be made of the same material as the conductive portion 251, or it may be made of a different material. The conductive portion 253 may cover, for example, the upper surface of the insulating layer 102, the upper surface of the conductive portion 251, and the upper surface of the conductive portion 252.

[0098] Furthermore, although the illustration is omitted, the semiconductor memory device of this embodiment replaces the conductive layer 151 ( Figure 6 ), conductive layer 152 ( Figure 9 ) and conductive layer 153 ( Figure 9 It has multiple conductive layers having the same structure as conductive layer 250. These multiple conductive layers serve as a junction with conductive layer 151 ( Figure 6 ), conductive layer 152 ( Figure 9 ) and conductive layer 153 ( Figure 9 It functions by corresponding wiring.

[0099] Next, refer to Figure 30 and Figure 31 The manufacturing method of the semiconductor memory device according to the second embodiment will be described. Figure 30 as well as Figure 31 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the second embodiment.

[0100] The method for manufacturing a semiconductor memory device in this embodiment is basically the same as the method for manufacturing a semiconductor memory device in the first embodiment. However, in this embodiment, for example, when referring to... Figure 28 In the described process, after forming a conductive layer of 150 Å, for example... Figure 30 As shown, the portion of the conductive layer 150A formed on the upper surface of the insulating layer 102 is removed to form a plurality of conductive portions 251, 252. This process is performed, for example, by a method such as RIE (Reinforcing Interchange). Next, for example, as... Figure 31 As shown, in Figure 30 The upper surface of the structure shown has a conductive portion 253 formed. In this process, a conductive layer corresponding to the conductive portion 253 is formed by a method such as CVD, and the conductive layer is cut off by a method such as RIE.

[0101] [Third Implementation Method]

[0102] Next, refer to Figure 32 The structure of the semiconductor memory device according to the third embodiment will be described. Figure 32 This is a schematic cross-sectional view used to illustrate the structure of the semiconductor memory device according to the third embodiment.

[0103] The semiconductor memory device of the third embodiment is basically constructed in the same way as the semiconductor memory device of the first embodiment. However, the semiconductor memory device of the third embodiment has an insulating layer 302 instead of an insulating layer 102.

[0104] The insulating layer 302 is basically constructed in the same way as the insulating layer 102 in the first embodiment.

[0105] However, as referenced Figure 7 As described, the insulating layer 102 has a space in the memory cell array region R MCA The inner part 102I and the storage cell array region R are arranged on the inner side. MCA The outer portion 102O is provided. Furthermore, the thickness of portion 102O in the Z direction is less than the thickness of portion 102I in the Z direction. Additionally, a step 102S is formed at the connection between portion 102I and portion 102O.

[0106] like Figure 32 As shown, the insulating layer 302 has a space in the memory cell array region R MCA The inner part 302I and the storage cell array region R are arranged on the inner side. MCAThe outer portion 302O is provided. Furthermore, the thickness of portion 302O in the Z direction is greater than the thickness of portion 302I in the Z direction. Additionally, a step 302S is formed at the connection between portion 302I and portion 302O. The step 302S, for example, runs along the memory cell array region R. MCA The outer edge setting.

[0107] Alternatively, the semiconductor memory device of this embodiment may have a conductive layer 250 instead of a conductive layer 150.

[0108] Next, refer to Figure 33 The manufacturing method of the semiconductor memory device according to the third embodiment will be described. Figure 33 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0109] The manufacturing method of the semiconductor memory device in this embodiment is basically the same as that of the manufacturing method of the semiconductor memory device in the first embodiment.

[0110] However, in the first embodiment, for example in reference Figure 10 In the described process, on wafer W M After forming an insulating layer 104 on the semiconductor substrate 100, the memory cell array region R is then formed by methods such as RIE or wet etching. MCA ( Figure 2 The insulating layer 104 is removed from the outer region of the area.

[0111] On the other hand, in this embodiment, for example, Figure 33 As shown, in chip W M After forming an insulating layer 104 on the semiconductor substrate 100, the insulating layer is not formed in the memory cell array region R by methods such as RIE (ion etching) or wet etching. MCA ( Figure 2 The insulation layer 104 is removed from the outer region of the outer region, but from the inner region.

[0112] [Fourth Implementation Method]

[0113] Next, refer to Figure 34 The manufacturing method of the semiconductor memory device according to the fourth embodiment will be described. Figure 34 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the fourth embodiment.

[0114] The method for manufacturing the semiconductor memory device in this embodiment is basically the same as the method for manufacturing the semiconductor memory device in the first embodiment. However, in this embodiment, the method described above is not performed. Figure 10 and Figure 11 The described process. Additionally, in this embodiment, on wafer W...M A conductive layer 411 is formed on the dicing line DL of the included semiconductor substrate 100, which contacts the upper surface of the semiconductor substrate 100. In addition, an insulating layer 402 such as silicon oxide (SiO2) is formed in other areas.

[0115] [other]

[0116] Several embodiments of the present invention have been described, but these embodiments are given by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor storage device comprising: a first chip having a semiconductor substrate and a transistor provided on a surface of the semiconductor substrate; and an electrode, the second chip having: a plurality of first conductive layers arranged in a first direction; a first semiconductor layer which is cylindrical, extends in the first direction, and opposes the plurality of first conductive layers; a first insulating film which extends in the first direction and covers an outer peripheral surface of the first semiconductor layer; a first insulating layer which extends in the first direction, is provided inside the first semiconductor layer, and has an outer peripheral surface covered by the first semiconductor layer; and a second conductive layer which is farther from the semiconductor substrate than the plurality of first conductive layers in the first direction and is connected to one end of the first direction of the first semiconductor layer, the electrode being provided on a bonding surface of the first chip and the second chip, electrically connecting the other end of the first direction of the first semiconductor layer and the transistor, the first semiconductor layer having: a first region opposing the plurality of first conductive layers; and a second region farther from the semiconductor substrate than the first region and containing an impurity of a first conductivity type, the second conductive layer being in contact with an inner peripheral surface, an outer peripheral surface, and an upper end portion of the second region of the first semiconductor layer and in contact with one end of the first insulating layer, the second chip not containing a semiconductor substrate, the second conductive layer being a source layer, the second chip having: a second semiconductor layer which extends in the first direction, opposes the plurality of first conductive layers; a second insulating film which extends in the first direction and covers an outer peripheral surface of the second semiconductor layer; and a second insulating layer which extends in the first direction and has an outer peripheral surface covered by the second semiconductor layer, the second semiconductor layer having: a third region opposing the plurality of first conductive layers; and a fourth region farther from the semiconductor substrate than the third region, the second conductive layer being connected to an inner peripheral surface and an outer peripheral surface of the fourth region of the second semiconductor layer and being in contact with one end of the first direction of the second insulating layer, the semiconductor storage device having: a first bit line electrically connected to an end portion of the first semiconductor layer on the semiconductor substrate side in the first direction; and a second bit line electrically connected to an end portion of the second semiconductor layer on the semiconductor substrate side in the first direction.

4. The semiconductor storage device according to any one of claims 1 to 3, wherein the semiconductor storage device has a third insulating layer farther from the semiconductor substrate than the plurality of first conductive layers and closer to the semiconductor substrate than the second conductive layer, the third insulating layer having: a first portion overlapping the plurality of first conductive layers when viewed in the first direction; and a second portion not overlapping the plurality of first conductive layers when viewed in the first direction, a thickness of the second portion in the first direction being smaller than a thickness of the first portion in the first direction or larger than the thickness of the first portion in the first direction, the semiconductor storage device having: a bonding pad electrode farther from the semiconductor substrate than the second conductive layer; and ​ a second chip, bonded to the first chip; ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 2. The semiconductor storage device according to claim 1, wherein ​ ​ ​ ​ ​ ​ ​ ​ ​ 3. The semiconductor storage device according to claim 2, wherein ​ ​ ​ ​ ​ ​ ​ ​ ​ 5. The semiconductor storage device according to any one of claims 1 to 3, wherein, ​ ​ A first wiring is provided between the second conductive layer and the bonding pad electrode, and is connected to the bonding pad electrode.

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