Storage system

Abstract

The present invention provides a storage system capable of improving the reliability of error correction processing. A semiconductor storage device (10) includes a first storage unit and a second storage unit arranged in a first region and a second region, respectively. A controller (20) is configured to receive first data from the first storage unit based on a first read operation and second data from the second storage unit based on the first read operation, receive third data from the first storage unit based on a second read operation and fourth data from the second storage unit based on the second read operation, set a first value corresponding to the first data and the third data based on first information in which the first storage unit is arranged in the first region, set a second value corresponding to the second data and the fourth data based on second information in which the second storage unit is arranged in the second region, decode the first data and the third data using the first value, and decode the second data and the fourth data using the second value.

Description

[0001] This application enjoys priority based on Japanese Patent Application No. 2021-129061 (filed on August 5, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0002] Embodiments of the present invention relate to storage systems. Background Technology

[0003] Non-volatile semiconductor memory devices include, for example, NAND flash memory, which is obtained by arranging memory cells in two or three dimensions. A memory system consists of NAND flash memory and a controller that controls NAND flash memory. As an error correction method when reading data from a semiconductor memory device, soft bit decoding (or soft-determination decoding) is known. Summary of the Invention

[0004] One embodiment of the present invention provides a storage system capable of improving the reliability of error correction processing.

[0005] One embodiment of the storage system includes a semiconductor storage device and a controller. The semiconductor storage device includes a first storage cell disposed in a first region and a second storage cell disposed in a second region. The controller is configured to: receive first data based on a first read operation from the first storage cell and second data based on the first read operation from the second storage cell; receive third data based on a second read operation different from the first read operation from the first storage cell and fourth data based on the second read operation from the second storage cell; set a first value corresponding to the first data and the third data based on first information indicating that the first storage cell is disposed in the first region; set a second value corresponding to the second data and the fourth data based on second information indicating that the second storage cell is disposed in the second region; decode the first data and the third data using the first value; and decode the second data and the fourth data using the second value. Attached Figure Description

[0006] Figure 1 This is a block diagram showing the configuration of the storage system according to the first embodiment.

[0007] Figure 2 This is a block diagram illustrating the configuration of the semiconductor memory device in the first embodiment.

[0008] Figure 3 This is a circuit diagram of a block within the memory cell array in the first embodiment.

[0009] Figure 4 This is a graph showing the relationship between the acceptable threshold voltage distribution of the memory cell transistor in the first embodiment and the data.

[0010] Figure 5 This is a diagram showing the configuration of the sense amplifier within the semiconductor memory device in the first embodiment.

[0011] Figure 6 This is a functional block diagram of the ECC circuit within the memory controller in the first embodiment.

[0012] Figure 7 This is a diagram illustrating examples of hard bit data, soft bit data, index, and LLR values ​​in the first embodiment.

[0013] Figure 8 This is a top view showing the layout of the memory cell transistors within the memory cell array in the first embodiment.

[0014] Figure 9 It is along Figure 8 A sectional view of line A-A in the diagram.

[0015] Figure 10 This is a flowchart illustrating the soft bit decoding process in the storage system of the first embodiment.

[0016] Figure 11 This is a diagram used to illustrate Vth tracking in the first embodiment.

[0017] Figure 12 This is a diagram showing the external bit discrimination data used to distinguish between the outer cell and the inner cell in the first embodiment.

[0018] Figure 13 This is a diagram illustrating an example of an LLR table used for soft bit decoding in the first embodiment.

[0019] Figure 14 This is a diagram illustrating an example of hard bit data, soft bit data, and an index when the low-order page is the read-out object in the first embodiment.

[0020] Figure 15 This is a functional block diagram of the ECC circuit within the memory controller in the second embodiment.

[0021] Figure 16 This is a flowchart illustrating the soft bit decoding process in the storage system of the second embodiment.

[0022] Figure 17This is a diagram illustrating an example of the transformation table used in the transformation of soft bit data in the second embodiment.

[0023] Figure 18 This is a diagram illustrating an example of an LLR table used for soft bit decoding in the second embodiment.

[0024] Figure 19 This is a functional block diagram of the ECC circuit within the memory controller in the third embodiment.

[0025] Figure 20 This is a flowchart illustrating the soft bit decoding process performed in the storage system of the third embodiment.

[0026] Figure 21 This is a diagram illustrating an example of the soft bit data of the external bits, the soft bit data of the internal bits, and the soft bit data obtained by combining these in the third embodiment.

[0027] Figure 22 This is a diagram illustrating an example of an LLR table used for soft bit decoding in the third embodiment.

[0028] Label Explanation

[0029] 1. Storage system; 2. Host device; 10. Semiconductor storage device; 11. Memory cell array; 12. Input / output circuit; 13. Logic control circuit; 14. Ready / busy circuit; 15. Register set; 15A. Status register; 15B. Address register; 15C. Command register; 16. Sequencer; 17. Voltage generation circuit; 18. Driver; 19. Row decoder; 20. Storage controller; 21. CPU; 22. RAM; 23. ROM; 24. ECC circuit; 25. NAND interface circuit; 26. Host interface circuit; 27. Control unit; 28. Column decoder; 29. ​​Sensing amplifier; 30. Semiconductor substrate; 31-35. Conductive layers; 40. Block insulating layer; 41. Charge storage layer; 42. Tunnel insulating layer; 43. Semiconductor layer; 241. Error correction circuit; 271. Data storage unit; 272. Data generation unit; 273. LLR setting unit; 273A. LLR table; 273. BLLR table; 273C. LLR table, 274 data conversion unit, 274A conversion table, HB hard bit data, SB1~SB4 soft bit data, SB5 external bit discrimination data. Detailed Implementation

[0030] Hereinafter, embodiments will be described with reference to the accompanying drawings. In the following description, constituent elements having the same function and structure will be given common reference numerals. In addition, the embodiments shown below are illustrative of apparatuses and methods for embodying the technical concept of these embodiments, and do not specifically specify the materials, shapes, structures, and arrangements of the constituent parts as described below.

[0031] Function blocks can be implemented as hardware, computer software, or a combination of both. Function blocks do not necessarily need to be differentiated as in the following example. For instance, a portion of the functionality can be performed by a function block different from the one illustrated. Furthermore, the illustrated function block can be further subdivided into smaller functional sub-blocks.

[0032] 1. First Implementation Method

[0033] The storage system of the first embodiment will be described below.

[0034] 1.1 Configuration of the first embodiment

[0035] 1.1.1 Composition of the storage system

[0036] First, the configuration of the storage system in the first embodiment will be described.

[0037] Figure 1 This is a block diagram illustrating the configuration of the storage system according to the first embodiment. The storage system 1 includes a semiconductor storage device 10 and a storage controller 20. The storage system 1 is connected to an external host device 2 and can perform various actions in response to commands from the host device 2.

[0038] The semiconductor memory device 10 includes a NAND flash memory that stores data in a non-volatile manner. Details about the semiconductor memory device 10 will be described later.

[0039] The memory controller 20 is connected to the semiconductor memory device 10 via a NAND bus. The memory controller 20 controls the semiconductor memory device 10. The NAND bus performs signal transmission and reception according to the NAND interface. In addition, the memory controller 20 is connected to the host device 2 via a host bus. The memory controller 20 responds to commands received from the host device 2 and accesses the semiconductor memory device 10.

[0040] The semiconductor memory device 10 and the memory controller 20 can also be combined to form a semiconductor device, for example, including SD cards. TMThe card can be a memory card, an SSD (solid state drive), or something similar. Additionally, the storage controller 20 can also be, for example, a SoC (system-on-a-chip).

[0041] Host device 2 is, for example, a digital camera, a personal computer, etc., and the host bus follows, for example, SD card. TM The bus of the interface.

[0042] 1.1.2 Composition of Storage Controller 20

[0043] Next, use Figure 1 The configuration of the storage controller 20 is described below. The storage controller 20 includes a CPU (central processing unit) (or processor) 21, RAM (random access memory) 22, ROM (read only memory) 23, ECC (error checking and correcting) circuit 24, NAND interface circuit (NAND I / F) 25, and host interface circuit (host I / F) 26.

[0044] CPU 21 controls the overall operation of memory controller 20. For example, when CPU 21 receives a write command from host device 2, it responds to it and issues a write command to NAND interface circuit 25. Similarly, when it receives read and erase commands, it responds to those commands and issues read and erase commands to NAND interface circuit 25, respectively.

[0045] In addition, the CPU 21 performs various processes for managing the semiconductor memory device 10, such as wear leveling. Furthermore, the operation of the memory controller 20 described below can be implemented either by the CPU 21 executing software (or firmware) or by hardware.

[0046] RAM 22 is a semiconductor memory such as Dynamic Random Access Memory (DRAM) or Static Random Access Memory (SRAM), and is used as the working area of ​​CPU 21. Additionally, RAM 22 temporarily stores firmware, various management tables, and data used to manage the semiconductor memory device 10. In this embodiment, for example, RAM 22 stores a Log Likelihood Ratio (LLR) table used during error correction processing and external bit discrimination data. The LLR table is a table that shows the relationship between each range of the threshold voltage and the LLR value when the threshold voltage of a memory cell is divided into multiple ranges. The LLR table and external bit discrimination data will be described later.

[0047] ROM23, for example, stores firmware executed by CPU21.

[0048] ECC circuit 24 performs error detection and correction processing on write data written to and read data read from semiconductor memory device 10. Specifically, ECC circuit 24 generates redundant data (parity check) for error correction of write data written to semiconductor memory device 10. The generated redundant data and write data are written to semiconductor memory device 10. Therefore, the data read from semiconductor memory device 10 includes write data and the corresponding parity check.

[0049] Furthermore, the ECC circuit 24 detects errors in the data read from the semiconductor memory device 10 and corrects them if errors are present. The ECC circuit 24 is capable of hard-decision error correction based on BCH codes and Reed-Solomon codes, as well as soft-decision error correction based on LDPC (low-density parity check). The ECC circuit 24 will be described in detail later.

[0050] The NAND interface circuit 25 is connected to the semiconductor memory device 10 via the NAND bus and is responsible for communication with the semiconductor memory device 10. Based on commands received from the CPU 21, the NAND interface circuit 25 sends various signals, commands, and data to the semiconductor memory device 10. Additionally, the NAND interface circuit 25 receives various signals and data from the semiconductor memory device 10.

[0051] The host interface circuit 26 is connected to the host device 2 via the host bus and is responsible for communication with the host device 2. The host interface circuit 26 forwards commands and data received from the host device 2 to the CPU 21 and RAM 22, respectively. In addition, the host interface circuit 26 responds to commands from the CPU 21 and forwards data from RAM 22 to the host device 2.

[0052] 1.1.3 Configuration of Semiconductor Memory Device 10

[0053] Next, the configuration of the semiconductor memory device 10 will be described. The semiconductor memory device 10 includes, for example, a NAND flash memory capable of storing data in a non-volatile manner.

[0054] Figure 2 This is a block diagram showing the configuration of the semiconductor memory device 10.

[0055] The semiconductor memory device 10 includes a memory cell array 11, input / output circuitry 12, logic control circuitry 13, ready / busy circuitry 14, register group 15, sequencer (or control circuitry) 16, voltage generation circuitry 17, driver 18, row decoder 19, column decoder 28, and sense amplifier 29. Register group 15 includes a status register 15A, an address register 15B, and a command register 15C.

[0056] The memory cell array 11 includes one or more blocks BLK0, BLK1, BLK2, ..., BLKm (where m is a natural number greater than or equal to 0). Each of the blocks BLK0 to BLKm includes multiple memory cell transistors (hereinafter also referred to as memory cells) associated with rows and columns. A memory cell transistor is a non-volatile memory cell that can be electrically erased and programmed. The memory cell array 11 includes multiple word lines, multiple bit lines, and source lines for applying voltage to the memory cell transistors. The specific structure of block BLKm will be described later.

[0057] Input / output circuit 12 and logic control circuit 13 are connected to memory controller 20 via input / output terminals (or NAND bus). Input / output circuit 12 and memory controller 20 communicate and receive I / O signals DQ (e.g., DQ0, DQ1, DQ2, ..., DQ7) via input / output terminals. I / O signals DQ communicate commands, addresses, and data.

[0058] The logic control circuit 13 receives external control signals from the memory controller 20 via input / output terminals (or the NAND bus). These external control signals include, for example, the chip enable signal CEn, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal WEn, the read enable signal REn, and the write protect signal WPn. The "n" in the signal name indicates that the signal is active low.

[0059] The chip enable signal CEn enables the selection of semiconductor memory device 10, and is effective when semiconductor memory device 10 is selected. The command latch enable signal CLE latches the command sent as signal DQ into command register 15C. The address latch enable signal ALE latches the address sent as signal DQ into address register 15B. The write enable signal WEn holds the data sent as signal DQ in input / output circuit 12. The read enable signal REn outputs the data read from memory cell array 11 as signal DQ. The write protect signal WPn is effective when writing to and erasing of semiconductor memory device 10 is disabled.

[0060] The ready / busy circuit 14 generates a ready / busy signal R / Bn based on control from the sequencer 16. The ready / busy signal R / Bn indicates whether the semiconductor memory device 10 is in a ready state or a busy state. A ready state indicates that the semiconductor memory device 10 is capable of accepting commands from the memory controller 20. A busy state indicates that the semiconductor memory device 10 is unable to accept commands from the memory controller 20. The memory controller 20 can determine whether the semiconductor memory device 10 is in a ready state or a busy state by receiving the ready / busy signal R / Bn from the semiconductor memory device 10.

[0061] Status register 15A stores the status information STS required for the operation of semiconductor memory device 10. Status register 15A transfers the status information STS to input / output circuit 12 according to the instructions of sequencer 16.

[0062] Address register 15B stores the address ADD transferred from input / output circuit 12. The address ADD includes a row address and a column address. The row address includes, for example, the block address specifying the block BLKm of the action object, and the page address specifying the word line WL of the action object within the specified block.

[0063] Command register 15C stores commands (CMD) transferred from input / output circuit 12. Commands (CMD) include, for example, write commands for writing commands to sequencer 16 and read commands for reading commands.

[0064] Status register 15A, address register 15B, and command register 15C use SRAM, for example.

[0065] The sequencer 16 receives commands from the command register 15C and controls the semiconductor memory device 10 in a general manner according to the sequence of commands.

[0066] The sequencer 16 controls the row decoder 19, column decoder 28, sense amplifier 29, and voltage generation circuit 17 to perform write, read, and erase operations. Specifically, based on write commands received from the command register 15C, the sequencer 16 controls the row decoder 19, driver 18, and sense amplifier 29 to write data to multiple memory cell transistors specified by address ADD. Furthermore, based on read commands received from the command register 15C, the sequencer 16 controls the row decoder 19, driver 18, column decoder 28, and sense amplifier 29 to read data from the multiple memory cell transistors specified by address ADD. Finally, based on erase commands received from the command register 15C, the sequencer 16 controls the row decoder 19, driver 18, column decoder 28, and sense amplifier 29 to erase data stored in the block specified by address ADD.

[0067] The voltage generation circuit 17 receives a power supply voltage VDD (or VCC, VPP) and a ground voltage VSS from an external source of the semiconductor memory device 10 via a power supply terminal. The power supply voltage VDD is an external voltage supplied from outside the semiconductor memory device 10, for example, 3.3V. The ground voltage VSS is an external voltage supplied from outside the semiconductor memory device 10, for example, 0V.

[0068] The voltage generation circuit 17 uses the power supply voltage VDD to generate multiple voltages required for write, read, and erase operations. The voltage generation circuit 17 supplies the generated voltages to the memory cell array 11, the driver 18, and the sense amplifier 29.

[0069] Driver 18 receives multiple voltages from voltage generation circuit 17. Driver 18 supplies multiple voltages selected from the multiple voltages supplied from voltage generation circuit 17 to row decoder 19 via multiple signal lines, based on read, write, and erase operations. For example, during a read operation, driver 18 supplies the read voltage VCGRV and voltage VREAD supplied from voltage generation circuit 17 to the word lines.

[0070] The row decoder 19 receives the row address from the address register 15B and decodes the row address. Based on the decoding result of the row address, the row decoder 19 selects any one of multiple blocks, and further selects the word line WL within the selected block BLKm. Furthermore, the row decoder 19 transfers multiple voltages supplied from the driver 18 to the selected block BLKm.

[0071] Column decoder 28 receives the column address from address register 15B and decodes the column address. Column decoder 28 selects the bit lines based on the decoding result of the column address.

[0072] During data readout, the sensing amplifier 29 detects and amplifies the data read from the memory cell transistor to the bit line. Furthermore, the sensing amplifier 29 temporarily stores the readout data DAT from the memory cell transistor and transfers the stored readout data DAT to the input / output circuit 12. Additionally, during data writeout, the sensing amplifier 29 temporarily stores the write data DAT transferred from the input / output circuit 12. Furthermore, the sensing amplifier 29 transfers the write data DAT to the bit line.

[0073] 1.1.3.1 Composition of a Block

[0074] Next, the circuit structure of the memory cell array 11 within the semiconductor memory device 10 will be described. The memory cell array 11 has multiple blocks BLK0 to BLKm, as described above. The circuit structure of block BLKm will be described below.

[0075] Figure 3 This is a circuit diagram of a block BLKm within the memory cell array 11. The block BLKm, for example, has multiple string cells SU0, SU1, SU2, and SU3. Hereinafter, when described as a string cell SU, each of the string cells SU0 to SU3 will be used. Each string cell SU has multiple NAND strings (or memory strings) NS.

[0076] To make the explanation easier to understand, an example is shown where a NAND string NS has, for example, eight memory cell transistors MT0, MT1, MT2, ..., MT7 and two select transistors ST1 and ST2. Hereinafter, when describing a memory cell transistor MT, we will use "MT0" to "MT7" to represent each of them.

[0077] The memory cell transistor MT has a control gate and a charge accumulation layer to store data in a non-volatile manner. Memory cell transistors MT0 to MT7 are connected in series between the source of select transistor ST1 and the drain of select transistor ST2. The memory cell transistor MT can store 1 bit of data or more than 2 bits of data.

[0078] The gates of the multiple selection transistors ST1 included in the serial unit SU0 are connected to the selection gate line SGD0. Similarly, the gates of the selection transistors ST1 of each of the serial units SU1 to SU3 are respectively connected to the selection gate lines SGD1 to SGD3. Each of the selection gate lines SGD0 to SGD3 is independently controlled by the serial decoder 19.

[0079] The gates of the multiple selection transistors ST2 included in the string unit SU0 are connected to the selection gate line SGS. Similarly, the gates of the selection transistors ST2 of each of the string units SU1 to SU3 are connected to the selection gate line SGS. In addition, sometimes a single (independent) selection gate line SGS is connected to the gate of each selection transistor ST2 in the string units SU0 to SU3. Selection transistors ST1 and ST2 are used for selection of the string unit SU in various operations.

[0080] The control gates of the memory cell transistors MT0 to MT7 included in block BLKm are respectively connected to word lines WL0 to WL7. Each word line WL0 to WL7 is independently controlled by the line decoder 19.

[0081] Each of the bit lines BL0 to BL(p-1) (where p is a natural number greater than or equal to 1) is connected to multiple blocks BLK0 to BLKm, and to a NAND string NS within the string unit SU included in block BLKm. That is, each of the bit lines BL0 to BL(p-1) is connected to the drain of the selection transistor ST1 of multiple NAND strings NS arranged in a matrix within block BLKm, located in the same column. Additionally, the source line SL is connected to multiple blocks BLK0 to BLKm. That is, the source line SL is connected to the source of the multiple selection transistors ST2 included in block BLKm.

[0082] In summary, each string cell SU comprises multiple NAND strings NS connected to different bit lines BL and connected to the same select gate line SGD. Additionally, each block BLKm comprises multiple string cells SU sharing a word line WL. Furthermore, the memory cell array 11 comprises multiple blocks BLK0 to BLKm sharing a bit line BL.

[0083] A block BLKm is, for example, a unit for data erasure. That is, the data held by the memory cell transistors MT within the block BLKm is erased together. Furthermore, data can be erased either in units of serial cells SU or in units smaller than serial cells SU.

[0084] Multiple memory transistors MT sharing a word line WL within a single serial cell SU are called a cell unit (CU). The collection of 1-bit data stored by each of the multiple memory transistors MT within a cell unit CU is called a page. The storage capacity of a cell unit CU varies depending on the number of bits of data stored by each memory transistor MT. For example, a cell unit CU stores one page of data when each memory transistor MT stores 1 bit of data, two pages when storing 2 bits of data, and three pages when storing 3 bits of data.

[0085] Write and read operations for a group unit (CU) are performed on a page-by-page basis. In other words, multiple memory cell transistors (MT) connected to a word line (WL) in a single string unit (SU) are read and written simultaneously.

[0086] Furthermore, the number of string cells in the block BLKm is not limited to SU0 to SU3 and can be arbitrarily set. Additionally, the number of NAND strings NS included in the string cell SU, the number of memory cell transistors in the NAND string NS, and the number of select transistors can be arbitrarily set. Furthermore, the memory cell transistor MT can be either a MONOS (metal-oxide-nitride-oxide-silicon) type using an insulating film as the charge storage layer, or an FG (floating gate) type using a conductive layer as the charge storage layer.

[0087] 1.1.3.2 Threshold voltage distribution of memory cell transistors

[0088] Next, the relationship between the available threshold voltage distribution of the memory cell transistor MT and the data will be explained.

[0089] Figure 4 This is a graph showing the relationship between the acceptable threshold voltage distribution of the memory cell transistor MT and the data. Here, an example is shown where a TLC (Triple-Level Cell) method, capable of storing 3 bits of data in a single memory cell transistor MT, is used as the storage method for the memory cell transistor MT. Furthermore, this embodiment can also be applied to other storage methods, such as an SLC (Single-Level Cell) method capable of storing 1 bit of data in a single memory cell transistor MT, an MLC (Multi-Level Cell) method capable of storing 2 bits of data in a single memory cell transistor MT, and a QLC (Quad-Level Cell) method capable of storing 4 bits of data in a single memory cell transistor MT.

[0090] The 3 bits of data that a memory cell transistor MT can store are defined by the lower bit, middle bit, and upper bit. When storing 3 bits, the memory cell transistor MT can take any of eight states corresponding to multiple threshold voltages. Starting from the lowest value, these eight states are sequentially named "Er", "A", "B", "C", "D", "E", "F", and "G". Multiple memory cell transistors MT belonging to each of the states "Er", "A", "B", "C", "D", "E", "F", and "G" form a structure as follows: Figure 4 The distribution of threshold voltage is shown in the figure.

[0091] For the states "Er", "A", "B", "C", "D", "E", "F", and "G", data such as "111", "110", "100", "000", "010", "011", "001", and "101" are assigned respectively. When set as low-order bit "X", middle-order bit "Y", and high-order bit "Z", the bit arrangement is "Z, Y, X". Furthermore, the threshold voltage distribution and data allocation can be arbitrarily set.

[0092] To read the data stored in the memory cell transistor MT of the target readout, the state to which the threshold voltage of the memory cell transistor MT belongs is determined. To determine the state, readout voltages AR, BR, CR, DR, ER, FR, and GR are used. Hereinafter, the voltages applied to the memory cell transistor MT of the target readout, including readout voltages AR, BR, CR, DR, ER, FR, and GR, to determine the level are sometimes referred to as readout voltage VCGRV.

[0093] The state "Er" is equivalent to the state where data has been erased (erase state). The threshold voltage of the memory cell transistor MT belonging to the state "Er" is lower than the voltage AR, for example, it has a negative value.

[0094] States "A" through "G" represent states where charge is injected into the charge accumulation layer and data is written to the memory cell transistor MT. The threshold voltage of the memory cell transistor MT in states "A" through "G" is, for example, positive. The threshold voltage of the memory cell transistor MT in state "A" is higher than the read voltage AR and lower than the read voltage BR. The threshold voltage of the memory cell transistor MT in state "B" is higher than the read voltage BR and lower than the read voltage CR. The threshold voltage of the memory cell transistor MT in state "C" is higher than the read voltage CR and lower than the read voltage DR. The threshold voltage of the memory cell transistor MT in state "D" is higher than the read voltage DR and lower than the read voltage ER. The threshold voltage of the memory cell transistor MT in state "E" is higher than the read voltage ER and lower than the read voltage FR. The threshold voltage of the memory cell transistor MT in state "F" is higher than the read voltage FR and lower than the read voltage GR. The threshold voltage of the memory cell transistor MT, which belongs to state "G", is higher than the read voltage GR and lower than the voltage VREAD.

[0095] The voltage VREAD is the word line WL voltage applied to the memory cell transistor MT connected to the non-read group cell CU, and it is higher than the threshold voltage of the memory cell transistor MT in any state. Therefore, the memory cell transistor MT with the voltage VREAD applied to its control gate becomes in the ON state regardless of the data being held.

[0096] In addition, verification voltages used during the write operation are set between adjacent threshold distributions. Specifically, verification voltages AV, BV, CV, DV, EV, FV, and GV are set corresponding to states "A", "B", "C", "D", "E", "F", and "G", respectively. For example, verification voltages AV, BV, CV, DV, EV, FV, and GV are set to be slightly higher than read voltages AR, BR, CR, DR, ER, FR, and GR, respectively.

[0097] As described above, each memory cell transistor MT can be set to any of eight states to store 3 bits of data. Furthermore, writing and reading are performed on a page-by-page basis within a set of cells (CUs). When the memory cell transistor MT stores 3 bits of data, the three pages within a set of cells (CUs) are allocated low-order bits, middle-order bits, and high-order bits, respectively. The set of low-order bits, middle-order bits, and high-order bits held by the set of cells (CUs) that are written to in a single write operation or read out in a single read operation are respectively referred to as the lower page, middle page, and upper page.

[0098] With the data allocation described above applied, the low-order page is determined by reading out the read voltages AR and ER. The middle-order page is determined by reading out the read voltages BR, DR, and FR. The high-order page is determined by reading out the read voltages CR and GR.

[0099] 1.1.4 Configuration of Sensing Amplifier 29

[0100] Next, the configuration of the sensing amplifier 29 within the semiconductor memory device 10 will be described.

[0101] Figure 5 This diagram illustrates the configuration of the sense amplifier 29 within the semiconductor memory device 10. The sense amplifier 29 includes p sense amplifier circuits SAC, multiple data latches DL (DL0, DL1, DL2, ..., DLq (q is a natural number greater than or equal to 0)), p arithmetic circuits LC, and a data latch XDL.

[0102] Data latch DLq consists of p data latch circuits DLCq. Data latch XDL consists of p data latch circuits XDLC. Data latch circuits DLCq and XDLC temporarily store data.

[0103] Each line BL is connected to a sense amplifier circuit SAC, q+1 data latch circuits DLC0, DLC1, DLC2, ..., DLCq, an arithmetic circuit LC, and a data latch circuit XDLC.

[0104] During data readout, each sense amplifier circuit (SAC) is electrically connected to a memory cell transistor (MT) of the target memory cell via a bit line (BL) connected to it. Furthermore, each sense amplifier circuit (SAC) senses a voltage at a node within its own circuit, a voltage determined based on the threshold voltage of the memory cell transistor MT. Based on the sensing result, it determines which of two states the memory cell transistor MT, electrically connected to the sense amplifier circuit (SAC), belongs to. The two states of the memory cell transistor MT are represented as either "0" or "1" data. Each sense amplifier circuit (SAC) stores whether the readout data is "0" or "1" data in an arbitrary data latch (DLC) connected to it.

[0105] The operational circuit LC can perform logical operations on the data in the data latch circuits DLC and XDLC connected to it. The logical operations include NOT, OR, AND, XOR, and XNOR.

[0106] 1.1.5 Construction of ECC Circuit 24

[0107] Next, the ECC circuit 24 within the storage controller 20 in the first embodiment will be described.

[0108] Figure 6 This is a diagram showing the functional blocks associated with the ECC circuit 24 within the memory controller 20. The memory controller 20 has a control unit 27. The control unit 27 is implemented by a combination of a portion of the functions of the CPU 21, RAM 22, and ROM 23.

[0109] The control unit 27 controls the overall operation of the memory controller 20. The control performed by the control unit 27 includes processing related to the operation of the ECC circuit 24. When attempting to correct errors in read data from the semiconductor memory device 10, the control unit 27 instructs the semiconductor memory device 10 via the NAND interface circuit 25 to read the data required for error correction. The data required for error correction includes hard bit data HB and soft bit data SB.

[0110] The control unit 27 includes a data storage unit 271, a data generation unit 272, and an LLR setting unit 273.

[0111] The data storage unit 271 is implemented, for example, by the function of RAM 22, storing hard bit data HB, soft bit data SB1 to SB4, and external bit discrimination data SB5.

[0112] Hard-bit data HB is data read from a page (select page) of the read target group unit (select group unit) CU through low-order page read, middle-order page read, or high-order page read. Hard-bit data, for example, has a page size and includes columns of bits (hard bits) based on the data read results from each memory cell transistor (select cell transistor) MT in the select group unit CU.

[0113] Soft bit data SB1–SB4 each also includes columns of soft bits, each soft bit representing information related to a select transistor MT. Each of the soft bit data SB1–SB4 represents the result of a logical operation performed on multiple bit columns read from the select transistor MT corresponding to that bit under different conditions. Soft bit data includes various types based on the detail of the operations performed.

[0114] Here, the data storage unit 271 stores hard bit data HB and soft bit data SB1 to SB4. The hard bit data HB and soft bit data SB1 to SB4 will be described in detail later. Hereinafter, when hard bit data HB and soft bit data SB1 to SB4 are recorded together, they will be referred to as soft bit data {HB, SB1 to SB4}.

[0115] Additionally, the data storage unit 271 stores external bit discrimination data SB5. External bit discrimination data SB5 will be described in detail later.

[0116] The data generation unit 272 combines the least significant bit of the soft bit data {HB, SB1~SB4} with the external bit discrimination data SB5 to generate data {HB, SB1~SB4, SB5}. Hereinafter, the data obtained by combining the soft bit data {HB, SB1~SB4} and the external bit discrimination data SB5 will be referred to as the soft bit data {HB, SB1~SB5}.

[0117] The LLR setting unit 273 can store information in the LLR table 273A used for soft bit decoding. The LLR table 273A associates combinations of interrelated bits in the hard bit data and soft bit data with a corresponding LLR value. These combinations of bits are hereinafter referred to as indices. Furthermore, multiple indices with different values ​​are associated with multiple corresponding LLR values. Each LLR value represents information about the reliability (probability) of the data read through a certain readout voltage.

[0118] The conversion from index to LLR value can be performed, for example, according to LLR table 273A. LLR table 273A can be either pre-stored in storage system 1 or saved at the time storage system 1 was manufactured. Alternatively, it can be generated by control unit 27 before the conversion to LLR value is performed.

[0119] ECC circuit 24 includes error correction circuit 241. Error correction circuit 241 receives soft bit data {HB, SB1~SB5} and LLR table 273A from control unit 27 and performs soft bit decoding. Error correction circuit 241 can, for example, decode data according to a size called a frame.

[0120] Figure 7 Examples representing hard bit data HB, four soft bit data SB1, SB2, SB3, SB4, the index, and the LLR value. Figure 7 Each cell in the diagram represents one bit from the hard bit data HB and the soft bit data SB1 to SB4. Figure 7 The vertically arranged squares represent the bits for a specific selection cell transistor MT. One page of hard-bit data HB contains p bits, equal to the number of storage cell transistors MT in one group cell CU. Similarly, soft-bit data SB1–SB4 each contain p bits.

[0121] Soft bit data comprises columns of bits (soft bits) based on data read from each memory cell transistor MT of the select page under different conditions. Each soft bit carries information about a select cell transistor MT.

[0122] For a selector transistor MT, the hard bits in the hard bit data HB and the soft bits in the soft bit data SB1 to SB4 each constitute a group. A group consists of 5 bits of data, which is equivalent to an index value.

[0123] As described above, the corresponding LLR values ​​can be extracted from each index using LLR table 273A. Each LLR value can be positive or negative. For ease of understanding, the LLR values ​​are represented in decimal in the accompanying drawings and the following description.

[0124] 1.1.4 Structure of Semiconductor Memory Device 10

[0125] Next, an example of the construction of the semiconductor memory device 10 of the first embodiment will be described.

[0126] Figure 8 This is a top view showing the layout of the memory pillars MP (or memory cell transistors MT) within the memory cell array 11 of the semiconductor memory device 10. Figure 9 It is along Figure 8 A sectional view along line A-A. In Figure 8 and Figure 9 In this design, two directions parallel to and orthogonal to the surface of the semiconductor substrate 30 are designated as the X and Y directions, and the direction orthogonal to the surface encompassing these X and Y directions (XY surface) is designated as the Z direction. The X direction corresponds to the extension direction of the word line WL, the Y direction corresponds to the extension direction of the bit line BL, and the Z direction corresponds to the direction of the stacked word line WL. Furthermore, in Figure 9 The interlayer insulation layer between conductive layers is omitted.

[0127] like Figure 8 and Figure 9 As shown, the memory cell array 11 has multiple memory pillars MP, an insulating layer ST, and an insulating layer SHE. The insulating layer ST extends in the X and Z directions and is arranged in the Y direction. The insulating layer SHE extends in the X direction and is arranged in the Y direction. The insulating layers ST and SHE are arranged alternately in the Y direction.

[0128] Multiple storage columns (MPs) are configured between insulating layer ST and insulating layer SHE. For example, the multiple storage columns (MPs) are arranged in a staggered pattern along the X and Y directions in the region between adjacent insulating layers ST and SHE. This is not a limitation; the number and configuration of storage columns (MPs) between adjacent insulating layers ST and SHE can be appropriately varied.

[0129] The following is for reference Figure 9 The cross-sectional view shown provides a detailed description of the structure of the memory cell array 11.

[0130] like Figure 9 As shown, the memory cell array 11 includes conductive layers 31-34, memory pillars MP, and contact plugs CV1 disposed above the semiconductor substrate 30. Specifically, conductive layer 31 is disposed above the semiconductor substrate 30. Conductive layer 31 is formed as a flat plate parallel to the main surface (or XY plane) of the semiconductor substrate 30. This conductive layer 31 functions as a source line SL. Conductive layer 31 may contain, for example, polycrystalline silicon or tungsten (W) doped with impurities.

[0131] Multiple insulating layers ST along the XZ plane and insulating layers SHE extending in the X direction are alternately arranged on the conductive layer 31 along the Y direction. The structure (or stack) between adjacent insulating layers ST and SHE on the conductive layer 31 corresponds, for example, to a string unit SU.

[0132] A conductive layer 32, multiple conductive layers 33, a conductive layer 34, and a conductive layer 35 are sequentially disposed on the conductive layer 31 between adjacent insulating layers ST and SHE, starting from the bottom layer. Adjacent conductive layers in the Z-direction are stacked with an interlayer insulating film in between. Conductive layers 32-34 are each formed as a flat plate parallel to the XY plane. Conductive layer 32 functions as the select gate line SGS. The multiple conductive layers 33, starting from the bottom layer, sequentially function as word lines WL0-WL7. Conductive layer 34 functions as the select gate line SGD0. Conductive layers 32-34 may contain, for example, tungsten (W) or polysilicon.

[0133] Multiple memory pillars (MPs) extend (or penetrate) along the Z-direction within the stack between insulating layer ST and insulating layer SHE. Each memory pillar (MP) is positioned through conductive layers 34, 33, and 32 to reach the upper surface of conductive layer 31 from above conductive layer 34. Each memory pillar (MP) functions as a NAND string (NS).

[0134] The memory pillar MP, for example, has a block insulating layer 40, a charge storage layer 41, a tunnel insulating layer (also called a tunnel insulating film) 42, and a semiconductor layer 43. Specifically, the block insulating layer 40 is provided on the inner wall of the memory hole used to form the memory pillar MP. The charge storage layer 41 is provided on the inner wall of the block insulating layer 40. The tunnel insulating layer 42 is provided on the inner wall of the charge storage layer 41. Furthermore, the semiconductor layer 43 is provided inside the tunnel insulating layer 42. In addition, the memory pillar MP may also have a structure in which a core insulating layer is provided inside the semiconductor layer 43.

[0135] In this configuration of the memory pillar MP, the portion where the memory pillar MP intersects with the conductive layer 32 functions as the selection transistor ST2. The portions where the memory pillar MP intersects with the conductive layer 33 function as memory cell transistors MT0 to MT7, respectively. Furthermore, the portion where the memory pillar MP intersects with the conductive layer 34 functions as the selection transistor ST1.

[0136] Semiconductor layer 43 functions as the channel layer for the memory cell transistor MT and the selection transistors ST1 and ST2. The current path for the NAND string NS is formed within semiconductor layer 43.

[0137] The charge storage layer 41 has the function of storing the charge injected from the semiconductor layer 43 in the memory cell transistor MT. The charge storage layer 41 includes, for example, a silicon nitride film.

[0138] The tunnel insulating layer 42 functions as a potential barrier when charge is injected from the semiconductor layer 43 into the charge accumulation layer 41, or when charge accumulated in the charge accumulation layer 41 diffuses into the semiconductor layer 43. The tunnel insulating layer 42 includes, for example, a silicon oxide film.

[0139] The insulating layer 40 prevents the charge accumulated in the charge storage layer 41 from diffusing to the conductive layer 33 (word line WL). The insulating layer 40 may include, for example, an aluminum oxide layer, a silicon oxide layer, and a silicon nitride layer.

[0140] Multiple conductive layers 35 are disposed above the upper surface of the memory cylinder MP, separated by an interlayer insulating film. The multiple conductive layers 35 are arranged in the X direction. Each conductive layer 35 is a linear wiring layer extending in the Y direction, functioning as a bit line BL. Each conductive layer 35 is electrically connected to a memory cylinder MP corresponding to each string cell SU. Specifically, in each string cell SU, a contact plug CV1 is disposed on the semiconductor layer 43 within each memory cylinder MP, and a conductive layer 35 is disposed on the contact plug CV1. The conductive layer 35 comprises, for example, aluminum (Al) or tungsten (W). The contact plug CV1 comprises a conductive layer, for example, tungsten (W).

[0141] In addition, the number of word lines WL and select gate lines SGD and SGS are changed according to the number of memory cell transistors MT and select transistors ST1 and ST2, respectively.

[0142] In the above-described configuration of memory cell transistors MT (or memory pillars MP), the memory cell transistors MT are divided into external cells (or external bits) and internal cells (or internal bits). An external cell comprises multiple memory cell transistors MT arranged in a single row along the X-direction, close to the insulating layer ST. An internal cell is the memory cell transistor MT excluding the external cells. That is, an internal cell comprises multiple memory cell transistors MT arranged in three rows along the X-direction, close to the insulating layer SHE.

[0143] 1.2 Operation of the first embodiment

[0144] The following describes the soft bit decoding (or soft decision decoding) in the error correction processing of data reading in storage system 1.

[0145] Figure 10 This is a flowchart illustrating the soft bit decoding process in the storage system 1 of the first embodiment. The processes described below are commanded or executed by the storage controller 20.

[0146] First, such as Figure 10 As shown, the memory controller 20 performs a read operation (hereinafter referred to as Vth tracking) by searching for the optimal read voltage through multiple reads (S1). In Vth tracking, a better voltage value for the read voltage VCGRV used in the read operation is estimated. For example, when reading data from a memory cell transistor storing state "Er" or state "A", such as... Figure 11 As shown in (a), the threshold voltage distributions of preferred state "Er" and state "A" are separated. However, in reality... Figure 11 As shown in (b), sometimes the threshold voltage distribution of state "Er" and the threshold voltage distribution of state "A" intersect at the lower edge. In such cases, compared to using the readout voltage AR, using... Figure 11 When the read voltage ARop corresponds to the minimum position of the threshold voltage distribution curve as shown in (b), better readout (higher error correction success rate) can be achieved. Based on this, the memory controller 20 performs Vth tracking to infer the minimum position of the threshold voltage distribution curve. During Vth tracking, data readout is repeatedly performed while changing the magnitude of the readout voltage VCGRV. As a result of Vth tracking, the memory controller 20 obtains the voltages (minimum voltages) at multiple minimum positions of the threshold voltage distribution curve. Furthermore, the memory controller 20 estimates the optimal readout voltages AR, BR, CR, DR, ER, FR, and / or GR.

[0147] Vth tracking can be performed either to estimate the minimum voltage required for reading only from the selected page, or to estimate the minimum voltage required for all pages of the selected group unit CU. The result of Vth tracking is stored, for example, in RAM 22, as an offset (shift) relative to the default read voltage VCGRV. Furthermore, it can be used when reading subsequent data from the selected page or the selected group unit CU. The result of Vth tracking is stored, for example, per group unit CU.

[0148] Next, as Figure 10 As shown, the memory controller 20 generates soft bit data {HB, SB1 to SB4} (S2). Based on the soft bit decoding method employed by the error correction circuit 241, the memory controller 20 obtains all the soft bit data required for soft bit decoding of the hard bit data of the selected page. That is, the memory controller 20, for example, reads the hard bit data HB from the semiconductor memory device 10. Further, the memory controller 20 reads soft bit data SB1, soft bit data SB2, soft bit data SB3, and soft bit data SB4 from the semiconductor memory device 10. And, the soft bit data {HB, SB1 to SB4} is stored in the data storage unit 271.

[0149] Soft bit data can be obtained in any order. The type of soft bit data SB1 to SB4 required is based on the form of soft bit decoding employed by the error correction circuit 241. Examples of soft bit data will be described later. After obtaining all the required soft bit data, the storage controller 20 obtains the p indices of each of the p selection transistors MT.

[0150] Next, as Figure 10 As shown, the storage controller 20 generates external bit discrimination data SB5 (S3). The generated external bit discrimination data SB5 is stored in the data storage unit 271. Figure 8 As shown, the memory cell transistors MT disposed in the semiconductor memory device 10 are divided into external cells and internal cells. For example, the external cells include a plurality of memory cell transistors arranged in a single row in the X direction adjacent to the insulating layer ST. The internal cells are the memory cell transistors other than the external cells. That is, the internal cells include a plurality of memory cell transistors arranged in a single row in the X direction adjacent to the insulating layer SHE, and a plurality of memory cell transistors arranged in two rows in the Y direction of these single rows of memory cell transistors.

[0151] The distinction between external and internal cells is not limited to the above. In this example, an external cell is a plurality of memory cell transistors in one row in the X direction adjacent to the insulating layer ST, but for example, a plurality of memory cell transistors in multiple rows in the X direction adjacent to the insulating layer ST can also be used as an external cell.

[0152] Figure 12 This diagram represents the external bit discrimination data SB5 used to distinguish between external and internal cells. Here, the output of the storage cell array 11 is divided into bytes B0, B1, B2, ..., B4583, and the values ​​are used to distinguish between them. Figure 8 The number (IO number) assigned to the memory cell transistor MT shown indicates the memory cell transistor MT included in bytes B0 to B4583.

[0153] For memory cell transistors IO0 to IO7, "1" represents an external cell and "0" represents an internal cell. For example, the memory cell transistor IO3 in byte B0 is represented by "1", indicating it is an external cell. Similarly, the memory cell transistor IO7 in byte B0 is represented by "1", also indicating it is an external cell. On the other hand, memory cell transistors other than IO3 and IO7 in byte B0 are represented by "0", indicating they are internal cells. The memory controller 20 generates a value based on whether the memory cell transistor MT is an external or internal cell. Figure 12 The external bit discrimination data SB5 is shown in the figure.

[0154] Next, as Figure 10 As shown, the storage controller 20 generates soft bit data {HB, SB1 to SB5} including external bit discrimination data (S4). The storage controller 20 combines the soft bit data {HB, SB1 to SB4} generated in step S2 and the external bit discrimination data SB5 generated in step S3 through the data generation unit 272 to generate soft bit data {HB, SB1 to SB5}.

[0155] Next, the storage controller 20 sets the LLR table 273A for the LLR setting unit 273 (S5). The LLR table 273A is used for soft bit decoding in the following step S6. The LLR table 273A is a table used to distinguish the LLR values ​​of external bits and internal bits.

[0156] Figure 13This diagram illustrates an example of an LLR table 273A used in soft-bit decoding. The LLR table 273A associates soft-bit data {HB, SB1-SB5} with LLR values. LLR values ​​at indices 0-25 are valid for internal bits and are set corresponding to the internal bits. LLR values ​​at indices 26-31 are invalid for internal bits. Furthermore, LLR values ​​at indices 32-57 are valid for external bits and are set corresponding to the external bits. LLR values ​​at indices 58-63 are invalid for external bits. By using the LLR table 273A, LLR values ​​corresponding to the threshold voltage distribution characteristics of both external and internal bits can be obtained.

[0157] Next, as Figure 10 As shown, the storage controller 20 performs soft-bit decoding (S6). The storage controller 20 inputs the soft-bit data {HB, SB1~SB5} generated in step S4 and the LLR table 273A set in step S5 to the ECC circuit 24. The ECC circuit 24 uses the soft-bit data {HB, SB1~SB5} and the LLR values ​​extracted from the LLR table 273A to perform soft-bit decoding. The soft-bit decoding process is then complete.

[0158] 1.2.1 Generation of soft bit data {HB, SB1~SB4}

[0159] The generation of soft bit data {HB, SB1~SB4} in step S2 above will be explained below. Figure 14 This diagram illustrates an example of hard bit data HB, soft bit data SB1, soft bit data SB2, soft bit data SB3, soft bit data SB4, and the index when the lower-order page is the read target. The read voltages AR, BR, CR, DR, ER, FR, and GR are also shown, for example, with the data transmitted via... Figure 10 Step S1 involves Vth tracking to determine the voltage correspondence at the estimated minimum location.

[0160] As shown in the first row, the hard bit data HB of the low-order page has data "1" in the bit corresponding to the memory cell transistor MT with a threshold voltage that is less than voltage AR or greater than voltage ER, and data "0" in the bit corresponding to the memory cell transistor MT with a threshold voltage that is greater than voltage AR and less than voltage ER.

[0161] To acquire the soft bit data SB1, the memory controller 20 first acquires the data read out at a voltage slightly smaller than voltage AR and a voltage slightly smaller than voltage ER. The difference between the voltage used for reading and voltages AR and ER is, for example, -2Δ. That is, the memory controller 20 uses voltages AR-2Δ and ER-2Δ as readout voltages instead of AR and ER, respectively, to store the result of reading the lower-order page in any data latch DL. Δ can have any size. For example, Δ is equal to an integer multiple of the rise or fall of a predetermined readout voltage VCGRV that can instruct the semiconductor memory device 10.

[0162] When the semiconductor memory device 10 receives a data readout instruction, it performs the indicated data readout. The result of the low-order page readout using voltages AR-2Δ and ER-2Δ is displayed in the second row. The bits corresponding to the memory cell transistor MT with a threshold voltage less than or greater than AR-2Δ or ER-2Δ have data "1", and the bits corresponding to the memory cell transistor MT with a threshold voltage greater than or less than ER-2Δ have data "0". The data read into the data latch using a low-order page readout with a difference M (e.g., -2Δ) is hereinafter referred to as M low-order page data. The -2Δ low-order page data is stored in the data latch (e.g., data latch DL0) of the semiconductor memory device 10.

[0163] Similarly, the memory controller 20 instructs the semiconductor memory device 10 to perform a low-order page read using voltages AR+2Δ and ER+2Δ instead of voltages AR and ER, respectively. The read result is stored in another data latch group (e.g., data latch XDL) of the semiconductor memory device 10.

[0164] Next, the memory controller 20 instructs the semiconductor memory device 10 to perform an XOR operation on the data in data latch DL0 and data latch XDL. Upon receiving the instruction, the semiconductor memory device 10 performs the XNOR operation on the data in data latch DL0 and data latch XDL. Specifically, the sequencer 16 uses a total of two bits from the corresponding positions of the data in data latch DL0 and data latch XDL as input, and uses the arithmetic circuit LC to perform the XNOR operation on the two inputs. This operation is performed on all bits of the data in data latch DL0 and data latch XDL.

[0165] The result of the operation is stored in a data latch (e.g., data latch XDL). More specifically, the sequencer 16 performs an XNOR operation on the data in a certain data latch circuit DLC0 and the data in the data latch circuit XDLC connected to that data latch circuit DLC0 using an arithmetic circuit LC connected to those data latch circuits DLC0 and XDLC. The result of the operation is stored in the data latch circuit DLC0 that stores the input data of the logical operation and the data latch circuit XDLC connected to XDLC. Thus, the data stored in the data latch XDL is soft bit data SB1. Then, the soft bit data SB1 is sent to the storage controller 20 and stored in the data storage unit 271.

[0166] Similarly, the soft bit data SB2 is obtained by reading data from the select page to the data latch DL and performing logical operations. First, the result of the XNOR operation between -3Δ least significant page data and 3Δ least significant page data is obtained (XNOR1 data). Next, the result of the XNOR operation between XNOR1 data and -Δ least significant page data is obtained (XNOR2 data). Then, the result of the XNOR operation between XNOR2 data and Δ least significant page data is obtained (XNOR3 data). XNOR3 data is the soft bit data SB2, which is sent to the memory controller 20 and stored in the data storage unit 271.

[0167] The memory controller 20 further instructs the semiconductor memory device 10 to perform a middle page readout and a high page readout for the selection group unit CU, acquiring the middle page data and the high page data, respectively. The middle page data and the high page data are processed as soft bit data SB3 and soft bit data SB4, respectively.

[0168] An index is formed by groups of multiple bits derived from the data readout results of a single select transistor MT in both hard bit data and various soft bit data. The number of bits used to form an index depends on the error correction method performed by the ECC circuit 24. The implementation is not limited to using groups of several bits as indexes. In this example, a 5-bit group from the data readout results of a single select transistor MT in both hard bit data HB and soft bit data SB1-SB4 forms an index. Each index has a unique value for each combination of 5-bit values. As described above, the indexes are shown in decimal in the figure.

[0169] Furthermore, the example described above is the generation of soft bit data SB1 to SB4 in the sensing amplifier 29, but the soft bit data SB1 to SB4 can also be generated in the storage controller 20, and in particular the control unit 27.

[0170] 1.3 Effects of the first embodiment

[0171] According to the storage system 1 of the first embodiment, the correction capability of soft bit decoding can be improved. Therefore, the reliability of the error correction processing in the storage system 1 can be improved.

[0172] The effects of the first embodiment will be explained below.

[0173] In semiconductor memory devices, electrical characteristics sometimes differ depending on the location where the memory cell transistor MT is located. For example... Figure 8 As shown, the threshold voltage characteristics of the memory cell transistor MT will differ depending on whether it belongs to an external cell or an internal cell.

[0174] In the first embodiment, the memory controller 20 generates external bit discrimination data SB5 to distinguish between external and internal units. Using the external bit discrimination data SB5, the memory controller 20 sets LLR values ​​corresponding to the external and internal units respectively. That is, for soft bit data read from the memory cell transistor MT belonging to the external unit (e.g., the cell of IO3 in the serial cell SU0), an LLR value suitable for the external unit is set. On the other hand, for soft bit data read from the memory cell transistor MT belonging to the internal unit (e.g., the cell of IO0 in the serial cell SU0), an LLR value suitable for the internal unit is set. As a result, the correction capability of soft bit decoding using LLR values ​​can be improved. Consequently, the reliability of error correction processing in the memory system 1 can be improved.

[0175] 2. Second Implementation Method

[0176] The following describes the soft-bit decoding in the storage system 1 according to the second embodiment. In the first embodiment, the case where the ECC circuit 24 can accept soft-bit data with a width of 6 bits was described; however, in the second embodiment, the case where the bit width of the data that can be input to the ECC circuit 24 is limited is described. Here, the case where the bit width of the soft-bit data that can be input is 5 bits will be described. In the second embodiment, the differences from the first embodiment will be mainly described. Other configurations and operations not described are the same as in the first embodiment.

[0177] 2.1. Construction of ECC Circuit 24

[0178] Next, the ECC circuit 24 within the storage controller 20 in the second embodiment will be described.

[0179] Figure 15This is a diagram showing the functional blocks associated with the ECC circuit 24 within the memory controller 20. The memory controller 20 has a control unit 27. The control unit 27 is implemented by combining a portion of the functions of the CPU 21, RAM 22, and ROM 23.

[0180] The control unit 27 controls the processing related to the operation of the ECC circuit 24. The control unit 27 includes a data storage unit 271, a data conversion unit 274, and an LLR setting unit 273.

[0181] The data storage unit 271 is implemented, for example, by the function of RAM 22, storing hard bit data HB, soft bit data SB1 to SB4, and external bit discrimination data SB5.

[0182] The data conversion unit 274 combines the soft bit data {HB, SB1~SB4} and the external bit discrimination data SB5 to generate soft bit data {HB, SB1~SB5}. The data conversion unit 274 stores a conversion table 274A used for converting the soft bit data. The conversion table 274A contains indices for converting the soft bit data {HB, SB1~SB5} into soft bit data {HB, SB1~SB4}. The conversion table 274A can be either pre-stored in the storage system 1 or, for example, stored at the time the storage system 1 was manufactured. Alternatively, it can be generated by the control unit 27 before the soft bit data conversion is performed.

[0183] The LLR setting unit 273 can store the LLR table 273B used for soft bit decoding. The LLR table 273B associates indices corresponding to hard bit data and soft bit data with the corresponding LLR values. The conversion from indices to LLR values ​​can be performed according to the LLR table 273B. The LLR table 273B can be either pre-stored in the storage system 1, or it can be stored at the time the storage system 1 was manufactured. Alternatively, it can be generated by the control unit 27 before performing the conversion to LLR values.

[0184] ECC circuit 24 includes error correction circuit 241. Error correction circuit 241 receives soft bit data {HB, SB1 to SB4} and LLR table 273B from control unit 27 and performs soft bit (SB) decoding. Error correction circuit 241 can, for example, decode data according to a size called a frame.

[0185] 2.2 Operation of the second embodiment

[0186] The following describes the soft bit decoding in the error correction process of data reading in storage system 1.

[0187] Figure 16This is a flowchart illustrating the soft bit decoding process in the storage system 1 of the second embodiment. The processes described below are commanded or executed by the storage controller 20.

[0188] First, such as Figure 16 As shown, the memory controller 20 performs Vth tracking (S1). During Vth tracking, the memory controller 20 estimates the optimal read voltages AR, BR, CR, DR, ER, FR, and / or GR.

[0189] Next, the memory controller 20 generates soft bit data {HB, SB1 to SB4} (S2). That is, the memory controller 20 reads hard bit data HB from the semiconductor memory device 10, for example. Further, the memory controller 20 reads soft bit data SB1 to SB4 from the semiconductor memory device 10. And, the soft bit data {HB, SB1 to SB4} is stored in the data storage unit 271.

[0190] Next, the memory controller 20 generates external bit discrimination data SB5 (S3). The memory controller 20 generates data based on whether the memory cell transistor MT is an external or internal cell. Figure 12 The generated external bit discrimination data SB5 is shown. The generated external bit discrimination data SB5 is stored in the data storage unit 271.

[0191] Next, as Figure 10 As shown, the storage controller 20 generates soft bit data {HB, SB1~SB5} including external bit discrimination data, and uses transformation table 274A to transform the soft bit data {HB, SB1~SB5} into soft bit data {HB, SB1~SB4} (S11). That is, the storage controller 20 combines the soft bit data {HB, SB1~SB4} generated in step S2 and the external bit discrimination data SB5 generated in step S3 to generate soft bit data {HB, SB1~SB5}. Next, the storage controller 20 uses transformation table 274A to transform the 6-bit soft bit data {HB, SB1~SB5} into 5-bit soft bit data {HB, SB1~SB4}.

[0192] Figure 17 This is a diagram illustrating an example of transformation table 274A used in the transformation of soft bit data. In this diagram, the soft bit data {HB, SB1~SB5} as input data and the soft bit data {HB, SB1~SB4} as transformed output data are represented by their corresponding indices.

[0193] The transformation using transformation table 274A is performed as follows: Input data at indices 0-25 are not transformed and become output data at indices 0-25. Input data at indices 26-31 are transformed and become output data at indices 0-5. Input data at indices 32-51 are transformed and become output data at indices 0-19. Input data at indices 52-57 are transformed and become output data at indices 26-31. Furthermore, input data at indices 58-63 are transformed and become output data at indices 0-5. Through this transformation, all input data at indices 0-63 are transformed into output data at indices 0-31. Furthermore, the output data at indices 0-31, i.e., the soft bit data {HB, SB1-SB4}, is set as data for distinguishing between external and internal bits (S12).

[0194] Next, as Figure 16 As shown, the storage controller 20 sets the LLR table 273B for the LLR setting unit 273 (S5). The LLR table 273B is used for soft bit decoding in the next step S6. The LLR table 273B is a table used to distinguish the LLR values ​​of external bits and internal bits.

[0195] Figure 18 This diagram illustrates an example of an LLR table 273B used in soft-bit decoding. LLR table 273B associates the output data (soft-bit data {HB, SB1-SB4}) at indices 0-31 after transformation via transformation table 274A with the LLR values. The LLR values ​​at indices 0-19 are shared LLR values ​​valid for both internal and external bits, set accordingly to correspond with the internal and external bits. The LLR values ​​at indices 20-25 are LLR values ​​valid for internal bits, set accordingly to correspond with the internal bits. Furthermore, the LLR values ​​at indices 26-31 are LLR values ​​valid for external bits, set accordingly to correspond with the external bits. By using LLR table 273B, LLR values ​​corresponding to the characteristics of the threshold voltage distribution of each external and internal bit can be obtained.

[0196] Next, as Figure 16 As shown, the storage controller 20 performs soft-bit decoding (S6). The storage controller 20 inputs the soft-bit data {HB, SB1~SB4} set in step S12 and the LLR table 273B set in step S5 to the ECC circuit 24. The ECC circuit 24 uses the soft-bit data {HB, SB1~SB4} and the LLR values ​​extracted from the LLR table 273B to perform soft-bit decoding. The soft-bit decoding process is then complete.

[0197] 2.3 Effects of the second embodiment

[0198] The storage system 1 according to the second embodiment, like the one in the first embodiment, can improve the correction capability of soft bit decoding. Therefore, the reliability of the error correction processing in the storage system 1 can be improved.

[0199] Furthermore, in the second embodiment, even when there is a limitation on the bit width of the data that can be input to the ECC circuit 24, the same effect as in the first embodiment can be obtained by transforming the soft bit data into the number of bits that can be input.

[0200] 3. Third Implementation Method

[0201] The soft-bit decoding in the storage system 1 according to the third embodiment will be described below. In the first embodiment, after reading the soft-bit data, LLR values ​​corresponding to the external bits and internal bits are set respectively. However, in the third embodiment, the soft-bit data is read based on the readout voltages suitable for the external bits and internal bits respectively, and the LLR values ​​corresponding to the external bits and internal bits are set respectively. In the third embodiment, the differences from the first embodiment will be mainly described. Other configurations and operations not described are the same as in the first embodiment.

[0202] 3.1. Construction of ECC Circuit 24

[0203] Next, the ECC circuit 24 within the storage controller 20 in the third embodiment will be described.

[0204] Figure 19 This is a diagram showing the functional blocks associated with the ECC circuit 24 within the memory controller 20. The memory controller 20 has a control unit 27. The control unit 27 is implemented by combining a portion of the functions of the CPU 21, RAM 22, and ROM 23.

[0205] The control unit 27 controls the processing related to the operation of the ECC circuit 24. The control unit 27 includes a data storage unit 271, a data generation unit 272, and an LLR setting unit 273.

[0206] The data storage unit 271 is implemented, for example, by the function of RAM 22, storing hard bit data HB and soft bit data SB1 to SB4 for internal bits and external bit discrimination data SB5, and hard bit data HB and soft bit data SB1 to SB4 and external bit discrimination data SB5 for external bits.

[0207] The data generation unit 272 synthesizes the soft bit data {HB, SB1~SB5} used for internal bits and the soft bit data {HB, SB1~SB5} used for external bits to generate soft bit data {HB, SB1~SB5}.

[0208] The LLR setting unit 273 can store the LLR table 273C used for soft bit decoding. The LLR table 273C associates indices corresponding to hard bit data and soft bit data with the corresponding LLR values. The conversion from indices to LLR values ​​can be performed by the LLR table 273C. The LLR table 273C can be either pre-stored in the storage system 1, or it can be stored at the time the storage system 1 was manufactured. Alternatively, it can be generated by the control unit 27 before performing the conversion to LLR values.

[0209] ECC circuit 24 includes error correction circuit 241. Error correction circuit 241 receives soft bit data {HB, SB1 to SB5} and LLR table 273C from control unit 27 and performs soft bit (SB) decoding. Error correction circuit 241 can, for example, decode data according to a size called a frame.

[0210] 3.2 Operation of the third embodiment

[0211] The following describes the soft bit decoding in the error correction process of data reading in storage system 1.

[0212] Figure 20 This is a flowchart illustrating the soft bit decoding process performed in the storage system 1 of the third embodiment. The processes described below are commanded or executed by the storage controller 20.

[0213] First, such as Figure 20 As shown, the memory controller 20 performs Vth tracking (S31) on the memory cell transistor MT, which corresponds to the internal bit. During Vth tracking, the memory controller 20 estimates the optimal read voltage VCGRV in the internal bit.

[0214] Next, the memory controller 20 generates external bit discrimination data SB5 (S32). The memory controller 20 generates data based on whether the memory cell transistor MT is an external or internal cell. Figure 12 The generated external bit discrimination data SB5 is shown. The generated external bit discrimination data SB5 is stored in the data storage unit 271.

[0215] Next, the memory controller 20 generates soft bit data {HB, SB1 to SB5} for the internal bits (S33). That is, the memory controller 20 reads the hard bit data HB from the semiconductor memory device 10, for example, using the optimal readout voltage VCGRV for the internal bits obtained in step S31. Further, the memory controller 20 reads the soft bit data SB1 to SB4 from the semiconductor memory device 10 using a voltage based on the readout voltage VCGRV. The memory controller 20 then combines the generated soft bit data {HB, SB1 to SB4} with the external bit discrimination data SB5 to generate soft bit data {HB, SB1 to SB5}. The generated soft bit data {HB, SB1 to SB5} is stored in the data storage unit 271.

[0216] Figure 21 Figure (a) is a diagram showing an example of soft-bit data used for internal bits. Here, the soft-bit data is represented in decimal. Figure 21 The data enclosed by dashed lines in (a) is data read from the storage cell transistors that are equivalent to internal bits.

[0217] Next, the memory controller 20 performs Vth tracking on the memory cell transistor MT, which corresponds to the external bit (S34). During Vth tracking, the memory controller 20 estimates the optimal read voltage VCGRV in the external bit.

[0218] Next, the memory controller 20 generates soft bit data {HB, SB1 to SB5} for the external bits (S35). That is, the memory controller 20 reads hard bit data HB from the semiconductor memory device 10, for example, using the optimal readout voltage VCGRV for the external bits obtained in step S34. Further, the memory controller 20 reads soft bit data SB1 to SB4 from the semiconductor memory device 10 using a voltage based on the readout voltage VCGRV. The memory controller 20 then combines the generated soft bit data {HB, SB1 to SB4} with the external bit discrimination data SB5 to generate soft bit data {HB, SB1 to SB5}. The generated soft bit data {HB, SB1 to SB5} is stored in the data storage unit 271.

[0219] Figure 21 Figure (b) is a diagram showing an example of soft-bit data used for external bits. The soft-bit data is represented in decimal. Figure 21 The data enclosed by the dashed line in (b) is the data read from the storage cell transistor, which is equivalent to an external bit.

[0220] Next, the storage controller 20 synthesizes the soft bit data {HB, SB1~SB5} for external bits and the soft bit data {HB, SB1~SB5} for internal bits via the data generation unit 272 (S36). Furthermore, the storage controller 20 sets the synthesized soft bit data {HB, SB1~SB5} to the data generation unit 272 (S37).

[0221] Figure 21 Figure (c) is a diagram showing an example of soft bit data {HB, SB1~SB5} obtained by combining soft bit data for external bits and soft bit data for internal bits. The soft bit data is represented in decimal. Figure 21 The data enclosed by dashed lines in (c) is... Figure 21 The internal bit data in (a) and Figure 21 The data is obtained by extracting the external bits from (b).

[0222] Next, the storage controller 20 sets the LLR table 273C for the LLR setting unit 273 (S38). The LLR table 273C is used for soft bit decoding in the following step S39. The LLR table 273C is a table used to distinguish the LLR values ​​of external bits and internal bits.

[0223] Figure 22 This diagram illustrates an example of an LLR table 273C used in soft-bit decoding. The LLR table 273C associates the soft-bit data {HB, SB1-SB5} set in step S37 with the LLR values. LLR values ​​at indices 0-25 are valid for internal bits and are set corresponding to the internal bits. LLR values ​​at indices 26-31 are invalid for internal bits. Furthermore, LLR values ​​at indices 32-57 are valid for external bits and are set corresponding to the external bits. LLR values ​​at indices 58-63 are invalid for external bits. By using the LLR table 273C, LLR values ​​corresponding to the characteristics of the threshold voltage distribution of both external and internal bits can be obtained.

[0224] Next, the storage controller 20 performs soft-bit decoding (S39). The storage controller 20 inputs the soft-bit data {HB, SB1~SB5} set in step S37 and the LLR table 273C set in step S38 to the ECC circuit 24. The ECC circuit 24 uses the soft-bit data {HB, SB1~SB5} and the LLR values ​​extracted from the LLR table 273C to perform soft-bit decoding. The soft-bit decoding process is then complete.

[0225] 3.3 Effects of the third embodiment

[0226] The storage system 1 according to the third embodiment can improve the soft bit decoding correction capability in the same way as the first embodiment. Therefore, the reliability of the error correction processing in the storage system 1 can be improved.

[0227] Furthermore, in the third embodiment, Vth tracking and soft-bit data readout are performed for both external bits and internal bits. Specifically, Vth tracking is performed on the memory cell transistor MT corresponding to the external bit, and soft-bit data is read out based on the readout voltage VCGRV obtained through this Vth tracking. Furthermore, an LLR value corresponding to the external bit is set. Similarly, Vth tracking is performed on the memory cell transistor MT corresponding to the internal bit, and soft-bit data is read out based on the readout voltage VCGRV obtained through this Vth tracking. Furthermore, an LLR value corresponding to the internal bit is set. In this way, by obtaining appropriate readout voltages VCGRV for both the external and internal bits and reading out their respective soft-bit data, more accurate soft-bit decoding can be performed.

[0228] 4. Other variations, etc.

[0229] In the aforementioned embodiments, soft bit decoding was performed by setting LLR values ​​corresponding to each external cell (or external bit) or internal cell (or internal bit). However, the threshold voltage characteristics of the memory cell transistor MT sometimes exhibit predetermined regularity depending on the configuration location other than the external or internal cell. In such cases, the LLR value can also be set based on the characteristics of the memory cell transistor MT in that configuration location. For example, the configuration location of the memory cell transistor MT can also be distinguished by columns. Therefore, the LLR value can be set accordingly based on which column the memory cell transistor MT belongs to.

[0230] Furthermore, in the above embodiments, NAND flash memory was used as an example of a semiconductor memory device, but it is not limited to NAND flash memory. It can be applied to all other semiconductor memories, and further, it can be applied to various memory devices other than semiconductor memories. In addition, the order of processing in the flowcharts described in the above embodiments can be changed whenever possible.

[0231] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and likewise within the scope of the invention as described in the claims and its equivalents.

Claims

1. A storage system comprising: A semiconductor memory device, comprising a first memory cell disposed in a first region and a second memory cell disposed in a second region; and Controller The controller is configured as follows: Receive first data based on the first read operation from the first storage unit, and second data based on the first read operation from the second storage unit. Receive third data from the first storage unit based on a second read action different from the first read action, and fourth data from the second storage unit based on the second read action. A first value corresponding to the first data and the third data is set based on the first information, wherein the first information indicates that the first storage unit is configured in the first region. A second value corresponding to the second data and the fourth data is set based on the second information, wherein the second information indicates that the second storage unit is configured in the second region. The first data and the third data are decoded using the first value, and the second data and the fourth data are decoded using the second value. The semiconductor memory device has: Semiconductor substrate; The first conductive layer is disposed on the semiconductor substrate; A second conductive layer is disposed on the first conductive layer; A first insulating layer, disposed on the semiconductor substrate and extending in a first direction, separates the first conductive layer and the second conductive layer; and A second insulating layer, disposed on the first conductive layer and extending in the first direction, separates the second conductive layer. The first region and the second region are disposed between the first insulating layer and the second insulating layer. The second region is farther from the first insulating layer than the first region is from the first insulating layer.

2. A storage system comprising: A semiconductor memory device, comprising a first memory cell disposed in a first region and a second memory cell disposed in a second region; and Controller The controller is configured as follows: Receive first data based on the first read operation from the first storage unit, and second data based on the first read operation from the second storage unit. Receive third data from the first storage unit based on a second read action different from the first read action, and fourth data from the second storage unit based on the second read action. A first value corresponding to the first data and the third data is set based on the first information, wherein the first information indicates that the first storage unit is configured in the first region. A second value corresponding to the second data and the fourth data is set based on the second information, wherein the second information indicates that the second storage unit is configured in the second region. The first data and the third data are decoded using the first value, and the second data and the fourth data are decoded using the second value. The semiconductor memory device has: Semiconductor substrate; The first conductive layer is disposed on the semiconductor substrate; A second conductive layer is disposed on the first conductive layer; A first insulating layer, disposed on the semiconductor substrate and extending in a first direction, separates the first conductive layer and the second conductive layer; A second insulating layer, disposed on the first conductive layer and extending in the first direction, separates the second conductive layer; as well as The first pillar and the second pillar are disposed on the semiconductor substrate, and penetrate the first conductive layer and the second conductive layer. The intersection of the first pillar and the first conductive layer corresponds to the first memory cell. The intersection of the second pillar and the first conductive layer corresponds to the second memory cell. The distance between the second post and the first insulating layer is greater than the distance between the first post and the first insulating layer.

3. The storage system according to claim 1 or 2, The controller performs multiple data reads by changing the read voltage of the first storage cell, and obtains the first read voltage corresponding to the minimum position of the threshold voltage distribution of the first storage cell. In the first readout action, the first readout voltage is used to read out the first data.

4. The storage system according to claim 1 or 2, In the second read operation, the first storage cell is read using a voltage that is greater than the first read voltage and a voltage that is less than the first read voltage. The read result is then subjected to an XOR NOT operation to obtain the third data.

5. A storage system comprising: A semiconductor memory device, comprising a first memory cell disposed in a first region and a second memory cell disposed in a second region; and Controller The controller is configured as follows: Receive first data from the first storage unit based on a first read action, and second data from the first storage unit based on a second read action different from the first read action. Receive third data from the second storage unit based on a third read action, and fourth data from the second storage unit based on a fourth read action different from the third read action. A first value corresponding to the first data and the second data is set based on the first information, wherein the first information indicates that the first storage unit is configured in the first region. A second value corresponding to the third and fourth data is set based on the second information, wherein the second information indicates that the second storage unit is configured in the second region. The first value is used to decode the first data and the second data, and the second value is used to decode the third data and the fourth data. The semiconductor memory device has: Semiconductor substrate; The first conductive layer is disposed on the semiconductor substrate; A second conductive layer is disposed on the first conductive layer; A first insulating layer, disposed on the semiconductor substrate and extending in a first direction, separates the first conductive layer and the second conductive layer; as well as A second insulating layer, disposed on the first conductive layer and extending in the first direction, separates the second conductive layer. The first region and the second region are disposed between the first insulating layer and the second insulating layer. The second region is farther from the first insulating layer than the first region is from the first insulating layer.

6. A storage system comprising: A semiconductor memory device, comprising a first memory cell disposed in a first region and a second memory cell disposed in a second region; and Controller The controller is configured as follows: Receive first data from the first storage unit based on a first read action, and second data from the first storage unit based on a second read action different from the first read action. Receive third data from the second storage unit based on a third read action, and fourth data from the second storage unit based on a fourth read action different from the third read action. A first value corresponding to the first data and the second data is set based on the first information, wherein the first information indicates that the first storage unit is configured in the first region. A second value corresponding to the third and fourth data is set based on the second information, wherein the second information indicates that the second storage unit is configured in the second region. The first value is used to decode the first data and the second data, and the second value is used to decode the third data and the fourth data. The semiconductor memory device has: Semiconductor substrate; The first conductive layer is disposed on the semiconductor substrate; A second conductive layer is disposed on the first conductive layer; A first insulating layer, disposed on the semiconductor substrate and extending in a first direction, separates the first conductive layer and the second conductive layer; A second insulating layer, disposed on the first conductive layer and extending in the first direction, separates the second conductive layer; as well as The first pillar and the second pillar are disposed on the semiconductor substrate, and penetrate the first conductive layer and the second conductive layer. The intersection of the first pillar and the first conductive layer corresponds to the first memory cell. The intersection of the second pillar and the first conductive layer corresponds to the second memory cell. The distance between the second post and the first insulating layer is greater than the distance between the first post and the first insulating layer.

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