Semiconductor memory device

Abstract

An embodiment of the present application provides a semiconductor storage device capable of high-speed operation. The semiconductor storage device of an embodiment includes a memory cell, a bit line, and a sense amplifier including a first circuit and a latch circuit. The first circuit includes a first node capable of being electrically connected to the bit line and capable of transferring a charge to the bit line according to data of the memory cell in a read operation of the memory cell, a first transistor having a gate connected to the first node and capable of being connected to a second node connected to the latch circuit, a second transistor capable of connecting the second node to a third node, and a third transistor having a gate connected to the third node and capable of being connected to the first node. The sense amplifier senses a first voltage of the first node when the charge is transferred to the bit line in the read operation, applies a second voltage obtained by amplifying the first voltage to the third node, and applies a third voltage obtained by amplifying the second voltage to the first node.

Description

[0001] [Related Applications]

[0002] This application claims priority to Japanese Patent Application No. 2021-13139 (filed on January 29, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor memory device. Background Technology

[0004] Regarding semiconductor memory devices, there is a known type of NAND (not AND) flash memory. Summary of the Invention

[0005] One embodiment of the present invention provides a semiconductor memory device capable of high-speed operation.

[0006] A semiconductor memory device according to one embodiment includes: a memory cell capable of storing data; a bit line electrically connected to the memory cell; and a sense amplifier electrically connected to the bit line, and includes a first circuit and a latching circuit. The first circuit includes: a first node electrically connected to the bit line, which, during a readout operation of the memory cell, transfers charge to the bit line based on the data in the memory cell; a first transistor with its gate connected to the first node, and which can be connected to a second node connected to the latching circuit; a second transistor capable of connecting the second node to a third node; and a third transistor with its gate connected to the third node, and which can be connected to the first node. During a readout operation, the sense amplifier senses a first voltage at the first node when charge is transferred to the bit line, applies a second voltage amplified from the first voltage to the third node, and applies a third voltage amplified from the second voltage to the first node. Attached Figure Description

[0007] Figure 1 This is a block diagram of the NAND flash memory according to the first embodiment.

[0008] Figure 2 This is a circuit diagram of the memory cell array included in the NAND flash memory of the first embodiment.

[0009] Figure 3 This is a threshold distribution diagram of the memory cell transistors included in the NAND flash memory of the first embodiment.

[0010] Figure 4 This is a block diagram of the sensing amplifier included in the NAND flash memory of the first embodiment.

[0011] Figure 5This is a circuit diagram of the sense amplifier assembly included in the NAND flash memory of the first embodiment.

[0012] Figure 6 This is a flowchart illustrating the read operation of the NAND flash memory in the first embodiment.

[0013] Figure 7 This is a timing diagram showing the voltages of various signals during the read operation of the NAND flash memory in the first embodiment.

[0014] Figure 8 This is a timing diagram showing the voltages of various signals during the read operation of the NAND flash memory in the first embodiment.

[0015] Figure 9 This is a flowchart illustrating the read operation of the NAND flash memory in the second embodiment.

[0016] Figure 10 This is a timing diagram showing the voltages of various signals during the read operation of the NAND flash memory in the second embodiment.

[0017] Figure 11 This is a flowchart illustrating the read operation of the NAND flash memory in the third embodiment.

[0018] Figure 12 This is a timing diagram showing the voltages of various signals during the read operation of the NAND flash memory in the third embodiment.

[0019] Figure 13 This is a circuit diagram of the sense amplifier assembly included in the NAND flash memory of the fourth embodiment.

[0020] Figure 14 This is a flowchart illustrating the read operation of the NAND flash memory in the fourth embodiment.

[0021] Figure 15 This is a timing diagram showing the voltages of various signals during the read operation of the NAND flash memory in the fourth embodiment.

[0022] Figure 16 This is a timing diagram showing the voltages of various signals during the read operation of the NAND flash memory in the fourth embodiment. Detailed Implementation

[0023] Hereinafter, the embodiments will be described with reference to the accompanying drawings. In this description, common parts will be labeled with common reference numerals in all drawings.

[0024] 1. First Implementation Method

[0025] The semiconductor memory device according to the first embodiment will be described. Hereinafter, regarding semiconductor memory devices, NAND flash memory will be used as an example for description.

[0026] 1.1 Composition

[0027] 1.1.1 Overall Structure of NAND Flash Memory

[0028] use Figure 1 The overall configuration of the NAND flash memory in this embodiment will be described. Figure 1 This is a block diagram of the NAND flash memory in this embodiment.

[0029] The NAND flash memory 1 includes a memory cell array 2, a control circuit 3, a voltage generation circuit 4, a line decoder 5, and a sensing amplifier 6.

[0030] The memory cell array 2 has multiple blocks BLK (BLK0, BLK1, BLK2, ...), each block containing non-volatile memory cell transistors corresponding to rows and columns. Each BLK block contains, for example, four string components SU (SU0 to SU3). Each string component SU contains multiple NAND strings NS. The number of blocks BLK and the number of string components SU within each block BLK are arbitrary. Details about the memory cell array 2 will be described below.

[0031] Control circuit 3 controls the overall operation of NAND flash memory 1.

[0032] The voltage generation circuit 4 generates voltages for writing, reading and erasing data according to the control circuit 3, and applies the generated voltages to the line decoder 5 and the sensing amplifier 6.

[0033] Row decoder 5 decodes the row address. The row address is provided, for example, by an external controller (not shown) that controls the NAND flash memory 1. Based on the decoding result, row decoder 5 selects any block BLK, and then selects any string component SU. Row decoder 5 applies the voltage supplied from voltage generation circuit 4 to block BLK.

[0034] During data readout, the sensing amplifier 6 senses the data read from the memory cell array 2 and outputs the read data to the controller. During data writeout, the sensing amplifier 6 transmits the write data received from the controller to the memory cell array 2.

[0035] The NAND flash memory 1 is connected to the controller via a NAND interface (not shown). Specific examples of signals transmitted and received between the controller and the NAND flash memory 1 include the chip enable signal CEn, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal WEn, read enable signals REn and RE, write protection signal WPn, data strobe signals DQS and DQSn, input / output signal DQ, and ready / busy signal RBn. The controller uses these signals to control the NAND flash memory 1.

[0036] The signal CEn is used to enable NAND flash memory 1, for example, by being activated at a low ("L") level. Furthermore, "activated" means making the signal (or logic) active. The signal CLE indicates that signal DQ is an instruction, for example, by being activated at a high ("H") level. The signal ALE indicates that signal DQ is an address, for example, by being activated at an "H" level. The signal WEn is used to load received signals into NAND flash memory 1, for example, by being activated at an "L" level. Whenever WEn is triggered, NAND flash memory 1 loads signal DQ. The signals REn and RE are used to cause the controller to read data from NAND flash memory 1. The signal REn is the inverted signal of signal RE. Whenever signals REn and RE are triggered, NAND flash memory 1 outputs signal DQ to the controller. The signal WPn is used to disable writing or erasing of NAND flash memory 1, for example, by being activated at an "L" level. Signals CEn, CLE, ALE, WEn, REn, RE, and WPn are sent from the controller to NAND flash memory 1.

[0037] Signals DQS and DQSn are used to control the transmission and reception timing of signal DQ. Signal DQSn is the inverted signal of signal DQS. For example, during data writing, signals DQS and DQSn are sent from the controller to NAND flash memory 1 along with the write data DQ. NAND flash memory 1 receives the write data DQ synchronously with receive signals DQS and DQSn. Similarly, during data reading, signals DQS and DQSn are sent from NAND flash memory 1 to the controller along with the read data DQ. Signals DQS and DQSn are generated based on the signal REn. The controller receives the read data DQ synchronously with receive signals DQS and DQSn.

[0038] The input / output signal DQ is, for example, an 8-bit signal. The input / output signal DQ is a data entity that is transmitted and received between the NAND flash memory 1 and the controller, such as instruction CMD, address ADD, write data or read data DAT, and status information STS.

[0039] Signal RBn indicates whether the NAND flash memory 1 is in a busy or ready state. For example, it is set to a "L" level when the NAND flash memory 1 is in a busy state. When signal RBn is in a ready state, the NAND flash memory 1 can receive instructions from the controller; when signal RBn is in a busy state, the NAND flash memory 1 cannot receive instructions from the controller. Signal RBn is sent from the NAND flash memory 1 to the controller.

[0040] 1.1.2 Circuit configuration of memory cell array 2

[0041] use Figure 2 The circuit configuration of memory cell array 2 will be explained. Figure 2 This is a circuit diagram of the memory cell array 2 included in the NAND flash memory 1 of this embodiment.

[0042] Figure 2 One block BLK from the multiple blocks BLKs contained in memory cell array 2 is selected to represent an example of the circuit configuration of memory cell array 2. The other block BLKs also have... Figure 2 The structure shown.

[0043] Multiple NAND strings NS are associated with bit lines BL0 to BLm (where m is a natural number greater than or equal to 1). Each NAND string NS includes, for example, memory cell transistors MC0 to MC7, and select transistors ST1 and ST2. Memory cell transistors MC0 to MC7 include a control gate and a charge storage layer, storing data non-volatilely. Select transistors ST1 and ST2 are used to select the string assembly SU during various operations.

[0044] In each NAND string NS, the memory cell transistors MC0 to MC7 are connected in series. In the same BLK, the control gates of the memory cell transistors MC0 to MC7 in the string components SU0 to SU3 are respectively connected to word lines WL0 to WL7.

[0045] In each NAND string NS, the drain of the select transistor ST1 is connected to the bit line BL that establishes its association, and the source of the select transistor ST1 is connected to one end of the memory cell transistors MC0 to MC7 connected in series. In the same BLK, the gates of the select transistors ST1 in the string components SU0 to SU3 are respectively connected to the select gate lines SGD0 to SGD3.

[0046] In each NAND string NS, the drain of the select transistor ST2 is connected to the other end of the series-connected memory cell transistors MC0 to MC7. In the same BLK, the source of the select transistor ST2 in the string assembly SU0 to SU3 is connected to the source line SL, and the gate of the select transistor ST2 in the string assembly SU0 to SU3 is commonly connected to the select gate line SGS.

[0047] In the circuit configuration of the memory cell array 2 described above, the bit line BL is shared among the corresponding multiple NAND strings NS in each block BLK. The source line SL is shared among multiple blocks BLK.

[0048] 1.1.3 Threshold distribution of memory cell transistors MC

[0049] use Figure 3 The threshold distribution that can be obtained from the memory cell transistor MC is explained. Figure 3 This is a threshold distribution diagram of the memory cell transistor MC included in the NAND flash memory 1 of this embodiment. Hereinafter, the case where the memory cell transistor MC can store 8 values ​​(3 bits) of data will be described, but the data that can be stored is not limited to 8 values, and may also be 4 values ​​(2 bits) or 16 values ​​(4 bits).

[0050] The threshold voltage of each memory cell transistor MC is taken from any one of eight discrete distributions. These eight distributions are named "Er" level, "A" level, "B" level, "C" level, "D" level, "E" level, "F" level and "G" level in order of threshold from low to high.

[0051] The "Er" level is equivalent to the data erasure state, for example. The threshold voltage included in the "Er" level is less than the voltage VA, and can have positive or negative values.

[0052] The “A” to “G” levels correspond to the state of writing data by injecting charge into the charge storage layer. Each of the “A” to “G” levels contains a threshold voltage, for example, a positive value. The threshold voltage of the “A” level is above VA and below VB (>VA). The threshold voltage of the “B” level is above VB and below VC (>VB). The threshold voltage of the “C” level is above VC and below VD (>VC). The threshold voltage of the “D” level is above VD and below VE (>VD). The threshold voltage of the “E” level is above VE and below VF (>VE). The threshold voltage of the “F” level is above VF and below VG (>VF). The threshold voltage of the “G” level is above VG and below VREAD (>VG). Furthermore, VREAD is the voltage applied to the unselected word line WL during data read and write operations to turn on the memory cell transistor MC.

[0053] As described above, each memory cell transistor MC can acquire eight states by using any one of eight threshold distributions. These states are represented in binary and assigned as "000" to "111", thus each memory cell transistor MC can store 3 bits of data. These 3 bits of data are referred to as the lower bit, middle bit, and upper bit, starting from the lower bit.

[0054] In this embodiment, regarding the data allocation for the "Er" to "G" levels, the data for the "Er" level is set to "111", the data for the "A" level is set to "110", the data for the "B" level is set to "100", the data for the "C" level is set to "000", the data for the "D" level is set to "010", the data for the "E" level is set to "011", the data for the "F" level is set to "001", and the data for the "G" level is set to "101". Furthermore, the data allocation for each level can be arbitrarily set. Figure 3 In the example, only one of the three bits changes between the data corresponding to two adjacent threshold distributions. Therefore, when reading the lower bit, it is sufficient to use the voltage at the boundary where the value of the lower bit ("0" or "1") changes, and the same applies to the middle bit and the upper bit.

[0055] For reading the lower bit, the voltage VA, which distinguishes between "Er" level and "A" level, and the voltage VE, which distinguishes between "D" level and "E" level, are used as the readout voltages.

[0056] For reading the middle bit, the voltage VB that distinguishes between "A" level and "B" level, the voltage VD that distinguishes between "C" level and "D" level, and the voltage VF that distinguishes between "E" level and "F" level are used as the readout voltages.

[0057] For reading out the upper bit, the voltage VC, which distinguishes between the "B" level and the "C" level, and the voltage VG, which distinguishes between the "F" level and the "G" level, are used as the readout voltages.

[0058] 1.1.4 Composition of Sensing Amplifier 6

[0059] use Figure 4 The configuration of the sensing amplifier 6 will be explained. Figure 4 This is a block diagram of the sensing amplifier 6 included in the NAND flash memory 1 of this embodiment.

[0060] The sense amplifier 6 includes multiple sense amplifier components (SAU) and multiple latching circuits (XDL).

[0061] The sense amplifier component (SAU) is configured for each bit line (BL). During a data readout operation, it senses and reads the data to the corresponding bit line (BL). During a data write operation, it transmits the write data to the corresponding bit line (BL). Figure 4 In this configuration, eight sense amplifier units (SAUs) are commonly connected to a single bus (DBUS). Furthermore, the number of sense amplifier units (SAUs) connected to the single bus (DBUS) can be arbitrary. In the following description, when distinguishing the eight sense amplifier units (SAUs) commonly connected to the single bus (DBUS), they will be referred to as SAU<0> to SAU<7>.

[0062] The latch circuit XDL is configured for each sense amplifier component SAU and temporarily stores data associated with the corresponding bit line BL. Figure 4 In this configuration, the eight latch circuits XDL<7:0> corresponding to the sense amplifier components SAU<0> to SAU<7> are commonly connected to a single bus DBUS. Alternatively, each of the eight latch circuits XDL<7:0> can be individually connected to one of the eight buses DBUS. Furthermore, each latch circuit XDL is connected to a data line IO. The latch circuits XDL are used to transmit and receive data between the sense amplifier component SAU and external devices via the bus DBUS and data lines IO. That is, for example, data received from the controller is first stored in the latch circuit XDL via the data line IO, and then transmitted to the sense amplifier component SAU via the bus DBUS. The reverse is also true.

[0063] 1.1.5 Circuit configuration of the sense amplifier assembly SAU

[0064] use Figure 5The circuit configuration of the sensing amplifier component SAU will be explained. Figure 5 This is a circuit diagram of the sense amplifier assembly SAU included in the NAND flash memory 1 of this embodiment. Furthermore, in this embodiment, a current-sensing sense amplifier assembly SAU that senses the current flowing through the bit line BL is used as an example for explanation; however, a voltage-sensing sense amplifier assembly SAU can also be used.

[0065] Figure 5 One sense amplifier component SAU from the plurality of sense amplifier components SAUs included in sense amplifier 6 is selected to represent an example of the circuit configuration of sense amplifier component SAU. The other sense amplifier components SAUs also have... Figure 5 The structure shown.

[0066] The sense amplifier assembly SAU includes a sense circuit SA and three latch circuits (SDL, ADL and BDL).

[0067] When reading data, the sensing circuit SA senses the data read to bit line BL and determines whether the read data is "0" or "1". When writing data, the sensing circuit SA applies voltage to bit line BL based on the data to be written. In addition, the sensing circuit SA performs AND and OR operations on the data in the latch circuits SDL, ADL, and BDL.

[0068] The details of the sensing circuit SA are explained below. In the following description, one of the source or drain terminals of the transistor will be referred to as "one end of the current path", and the other of the source or drain terminal will be referred to as "the other end of the current path".

[0069] The sensing circuit SA includes n-channel MOS transistors 10-22, p-channel MOS transistor 23, and capacitor elements 24 and 25.

[0070] The gate of transistor 10 is fed by the input signal BLC. One end of the current path is connected to the corresponding bit line BL, and the other end of the current path is connected to the node SCOM. Transistor 10 is used to clamp the corresponding bit line BL at the voltage corresponding to the signal BLC.

[0071] Transistor 11 has its gate connected to the input signal BLX, with one end of the current path connected to node SCOM and the other end connected to node SSRC. Transistor 12 has its gate connected to the input signal NLO, with one end of the current path connected to node SCOM and the other end connected to node SRCGND. Node SRCGND is, for example, grounded by voltage VSS. Transistor 12 is used to charge or discharge the corresponding bit line BL. Transistor 13 has its gate connected to node INV_S, with one end of the current path connected to node SSRC and the other end connected to node SRCGND. Transistor 14 has its gate connected to the input signal XXL, with one end of the current path connected to node SCOM and the other end connected to node SEN. Transistor 14 is used to control the period during which data is sensed from the memory cell transistor MC. Node SEN functions as a sensing node, used to sense the data of the target memory cell transistor MC during data readout. More specifically, during readout, the pre-charged charge in node SEN (and capacitor element 24) is transferred to line BL based on the on or off state of the memory cell transistor MC. Data is read out by sensing the voltage of node SEN at this time.

[0072] The gate of transistor 15 is connected to node SEN, and one end of its current path is connected to one end of the current path of transistor 16. The other end of the current path is supplied with a voltage VLOP. VLOP is, for example, ground voltage VSS. The gate of transistor 16 is supplied with the input signal STB, and the other end of its current path is connected to the bus LBUS. The gate of transistor 17 is supplied with the input signal BLQ, and one end of its current path is connected to node SEN. The other end of its current path is connected to the bus LBUS. The gate of transistor 18 is connected to node TDC, and one end of its current path is connected to one end of the current path of transistor 19. The other end of its current path is supplied with the voltage VLOP. The gate of transistor 19 is supplied with the input signal LSL, and the other end of its current path is connected to node SEN.

[0073] The gate of transistor 20 is fed by the input signal LPC. One end of the current path is connected to the bus LBUS, and the other end of the current path is supplied with a voltage VHLB. The voltage VHLB is, for example, the power supply voltage VDD. By turning transistor 20 on, the voltage VHLB is transmitted to the bus LBUS, thus pre-charging the bus LBUS.

[0074] The gate of transistor 21 is connected to the input signal L2T, one end of the current path is connected to node TDC, and the other end of the current path is connected to the bus LBUS.

[0075] The gate of transistor 22 is fed by the input signal DSW, with one end of the current path connected to the LBUS bus and the other end connected to the DBUS bus. Transistor 22 is a bus switch used to connect the LBUS and DBUS buses. This bus switch is used to connect the sensing circuit SA and the latching circuit XDL.

[0076] The gate of transistor 23 is connected to node INV_S, one end of the current path is supplied with voltage VHSA, and the other end of the current path is connected to node SSRC. Voltage VHSA is, for example, the power supply voltage VDD.

[0077] One electrode of capacitor element 24 is connected to node SEN, and the other electrode is connected to node CLKSA. The clock input is sent to node CLKSA.

[0078] One electrode of capacitor element 25 is connected to node TDC, and the other electrode is connected to node CLKTD. The clock input is sent to node CLKTD.

[0079] The latch circuits SDL, ADL, and BDL temporarily store data. During data writing, the sensing circuit SA controls the bit line BL based on the data stored in the latch circuit SDL. Other latch circuits ADL and BDL are used, for example, to temporarily store individual bits of data when each memory cell transistor MC stores more than 2 bits of data. Furthermore, the number of latch circuits can be arbitrarily set, for example, based on the amount of data (number of bits) that the memory cell transistor MC can store.

[0080] The latching circuit SDL includes n-channel MOS transistors 50-53 and p-channel MOS transistors 54-57.

[0081] Transistor 50's gate is input with signal STI, one end of its current path is connected to bus LBUS, and the other end is connected to node INV_S. Transistor 51's gate is input with signal STL, one end of its current path is connected to bus LBUS, and the other end is connected to node LAT_S. Transistor 52's gate is connected to node LAT_S, one end of its current path is grounded, and the other end is connected to node INV_S. Transistor 53's gate is connected to node INV_S, one end of its current path is grounded, and the other end is connected to node LAT_S. Transistor 54's gate is connected to node LAT_S, and one end of its current path is connected to node INV_S. Transistor 55's gate is connected to node INV_S, and one end of its current path is connected to node LAT_S. Transistor 56's gate is input with signal SLI, one end of its current path is connected to the other end of transistor 54's current path, and the other end of its current path is supplied with power supply voltage VDD. The gate of transistor 57 is fed with the input signal SLL, one end of the current path is connected to the other end of the current path of transistor 55, and the other end of the current path is supplied with the power supply voltage VDD.

[0082] In the latch circuit SDL, transistors 53 and 55 form the first inverter, and transistors 52 and 54 form the second inverter. The output of the first inverter and the input of the second inverter (node ​​LAT_S) are connected to the bus LBUS via data transmission transistor 51, and the input of the first inverter and the output of the second inverter (node ​​INV_S) are connected to the bus LBUS via data transmission transistor 50. The latch circuit SDL stores data at node LAT_S and its inverted data at node INV_S.

[0083] The latch circuits ADL and BDL have the same structure as the latch circuit SDL, so their description is omitted, but the reference symbols and signal names of each transistor are as follows: Figure 5 The latch circuit SDL is shown below and will be distinguished from it. Specifically, transistors 30-37 in latch circuit ADL and transistors 40-47 in latch circuit BDL correspond to transistors 50-57 in latch circuit SDL, respectively. Furthermore, signals ATI and BTI, and signals ATL and BTL correspond to signals STI and STL, respectively; signals ALI and BLI, and signals ALL and BLL correspond to signals SLI and SLL, respectively. In each sense amplifier assembly SAU, the sense circuit SA and the three latch circuits SDL, ADL, and BDL are connected by the LBUS bus to enable data transmission and reception.

[0084] Furthermore, various signals in the constructed sensing amplifier assembly SAU are provided, for example, by the control circuit 3.

[0085] 1.2 Reading Action

[0086] use Figures 6-8 The read operation of the NAND flash memory 1 in this embodiment will be described. Figure 6 This is a flowchart illustrating the read operation of the NAND flash memory 1 in this embodiment. Figure 7 and Figure 8 This is a timing diagram showing the voltages of various signals during the read operation of the NAND flash memory 1 in this embodiment. In this embodiment, the read operation is performed by pre-charging the node SEN in the sensing circuit SA, transferring the pre-charged charge to the node SEN to the bit line BL, and then digitizing it. Furthermore, in this specification, "digitization" refers to the sensing amplifier 6 sensing the voltage of the node SEN (reading the data to the bit line BL) and converting the sensed analog voltage signal into logic data (digital signal) at the "L" or "H" level.

[0087] After selecting the memory cell transistor MC of the read-out object, the sense amplifier 6 precharges the bit line BL (S10). Figure 7 As shown, at time t1, control circuit 3 raises signal BLC from "L" level (VSS) to "H" level (VBLC), and raises signal BLX from "L" level (VSS) to "H" level (VBLX). Voltage VBLC is used to clamp the voltage of bit line BL. Voltage VBLX is the voltage that enables transistor 11 to transmit voltage VDD. Voltage VBLX is higher than voltage VBLC. Therefore, transistors 10 and 11 are turned on, and bit line BL is pre-charged. The pre-charging of bit line BL occurs during the period from time t1 to time t5.

[0088] During the pre-charging process of bit line BL, sense amplifier 6 pre-charges node SEN (S11). For example... Figure 7 As shown, at time t2, control circuit 3 raises signals LPC and BLQ from the "L" level (VSS) to the "H" level (VX2). Voltage VX2 is the voltage that enables transistors 17, 20, and 21 to transmit voltage VDD. Therefore, transistors 17 and 20 are turned on, and node SEN and bus LBUS are pre-charged to the "H" level (VDD). At time t3, control circuit 3 lowers signals LPC and BLQ from the "H" level (VX2) back to the "L" level (VSS). Therefore, transistors 17 and 20 are turned off, and node SEN and bus LBUS remain at the "H" level. Furthermore, during the period from time t1 to time t2, bus LBUS takes any value between VSS and VDD.

[0089] If node SEN is pre-charged, then control circuit 3 applies voltage VDDSA to node CLKSA (S12, hereinafter referred to as "clock rise"). Voltage VDDSA is, for example, the supply voltage VDD. Figure 7 As shown, at time t4, control circuit 3 raises the voltage of node CLKSA from the "L" level (VSS) to the "H" level (VDDSA). As a result, capacitor element 24 is charged, and the voltage of node SEN rises to voltage Vcu due to capacitive coupling. Voltage Vcu is the voltage of node SEN after the clock rises, and is higher than voltage VDD.

[0090] After the clock rises, the sensing amplifier 6 senses the voltage at node SEN (S13). Figure 7 As shown, at time t5, control circuit 3 raises signal XXL from "L" level (VSS) to "H" level (VXXL). Voltage VXXL is higher than voltage VBLX. In this state, when the threshold voltage of the memory cell transistor MC of the read target is higher than the read voltage (e.g., VA, VB, VC, ...), the memory cell transistor MC is in the off-cell state (hereinafter referred to as "off-cell"), and current hardly flows from the corresponding bit line BL to the source line SL. Therefore, the charge charged in node SEN is hardly discharged, and the voltage of node SEN hardly changes. On the other hand, when the threshold voltage of the memory cell transistor MC of the read target is lower than the read voltage, the memory cell transistor MC is in the on-cell state (hereinafter referred to as "on-cell"), and current flows from the corresponding bit line BL to the source line SL. Since voltage VXXL is higher than voltage VBLX, the charge charged in node SEN is discharged. That is, the voltage of node SEN drops. At time t6, control circuit 3 causes signal XXL to drop from “H” level (VXXL) to “L” level (VSS).

[0091] When the voltage at node SEN is sensed, control circuit 3 applies voltage VSS to node CLKSA (S14, hereinafter referred to as "clock drop"). For example... Figure 7 As shown, at time t7, control circuit 3 causes the voltage of node CLKSA to drop from the "H" level (VDDSA) to the "L" level (VSS). As a result, due to capacitive coupling, the voltage of node SEN drops. Specifically, if the threshold voltage of transistor 15 is set to Vth15, then as... Figure 7 As shown, the voltage corresponding to node SEN of the disconnected unit is Vsn1 (Vth15 or higher, VDD or lower). Conversely, the voltage corresponding to node SEN of the connected unit is Vsn1' (VSS or higher, but less than Vth15).

[0092] After the clock falls, the sensing amplifier 6 charges the node TDC (S15). Figure 8 As shown, at time t9, control circuit 3 raises signals LPC and L2T from the "L" level (VSS) to the "H" level (VX2). This turns transistors 20 and 21 on, and node TDC and bus LBUS are charged to the "H" level (VDD). At time t10, control circuit 3 lowers signals LPC and L2T from the "H" level (VX2) back to the "L" level (VSS). This turns transistors 20 and 21 off, and node TDC and bus LBUS remain at the "H" level. Furthermore, node TDC can take any value between VSS and VDD during the period from time t1 to time t9.

[0093] If node TDC is charged, then the sensing amplifier 6 applies a voltage to node TDC that is amplified from the voltage of node SEN (S16). Figure 8 As shown, at time t11, control circuit 3 raises signal L2T from "L" level (VSS) to "H" level (VX2) and signal STB from "L" level (VSS) to "H" level (VDD). This turns transistors 16 and 21 on. Consequently, transistor 15, corresponding to the off-state, becomes a weaker on-state based on the voltage difference between voltage Vth15 and voltage Vsn1, causing the voltages of bus LBUS and node TDC to drop. The voltage of bus LBUS at this time is set to Vlb1, and the voltage of node TDC is set to Vtd1. Voltage Vtd1 and voltage Vsn1 are in the relationship Vtd1 < Vsn1. On the other hand, transistor 15, corresponding to the on-state, becomes a weaker off-state based on the voltage difference between voltage Vsn1' and voltage Vth15, and bus LBUS and node TDC are maintained at approximately voltage VDD (or slightly reduced). The voltage of bus LBUS at this time is set to Vlb1', and the voltage of node TDC is set to Vtd1'. Voltages Vtd1' and Vsn1' are in a relationship where Vtd1' > Vsn1'. As a result, the voltage differences between Vth15 and Vsn1, and between Vth15 and Vsn1', are amplified. In other words, the voltage difference between Vsn1 and Vsn1' is amplified to the voltage difference between Vtd1 and Vtd1'. At time t12, control circuit 3 causes signal L2T to drop from "H" level (VX2) to "L" level (VSS), and signal STB to drop from "H" level (VDD) to "L" level (VSS). Consequently, transistors 16 and 21 are turned off, and the voltage at node TDC is maintained.

[0094] If a voltage amplified from the voltage of node SEN is applied to node TDC, then the sensing amplifier 6 will charge node SEN (S17). Figure 8 As shown, at time t13, control circuit 3 raises signals LPC and BLQ from the "L" level (VSS) to the "H" level (VX2). This turns transistors 17 and 20 on, and node SEN and bus LBUS are charged to the "H" level (VDD). At time t14, control circuit 3 lowers signals LPC and BLQ from the "H" level (VX2) back to the "L" level (VSS). This turns transistors 17 and 20 off, and node SEN and bus LBUS remain at the "H" level.

[0095] If node SEN is charged, then sense amplifier 6 applies a voltage to node SEN that is amplified from the voltage of node TDC (S18). Figure 8 As shown, at time t15, control circuit 3 raises signal LSL from "L" level (VSS) to "H" level (VDD). This turns transistor 19 on. Consequently, transistor 18, corresponding to the off-state, becomes on based on the voltage difference between voltage Vtd1 and the threshold voltage Vth18 of transistor 18, and the voltage at node SEN drops. Let the voltage at node SEN at this time be Vsn2. Voltage Vsn2 is in a relationship of Vsn2 > Vtd1. On the other hand, transistor 18, corresponding to the on-state, becomes off based on the voltage difference between voltage Vtd1' and voltage Vth18, and node SEN remains approximately at voltage VDD. Let the voltage at node SEN at this time be Vsn2'. Voltage Vsn2' is in a relationship of Vsn2' < Vtd1'. As a result, the voltage difference between voltages Vsn1 and Vsn1' is amplified to the voltage difference between voltages Vsn2 and Vsn2' (e.g., amplified by 100 times). Hereinafter, this action will be referred to as the "voltage amplification operation of node SEN," that is, applying the voltage obtained by amplifying the voltage of node SEN to node TDC, and then applying the voltage obtained by amplifying the voltage of node TDC to node SEN. At time t16, control circuit 3 causes signal LSL to drop from the "H" level (VDD) to the "L" level (VSS). As a result, transistor 19 becomes off, and the voltage of node SEN is maintained.

[0096] If a voltage amplified from the voltage of node TDC is applied to node SEN, then sense amplifier 6 will charge bus LBUS (S19). Figure 8As shown, at time t17, control circuit 3 raises the signal LPC from the "L" level (VSS) to the "H" level (VX2). This turns transistor 20 on, and the bus LBUS is charged to the "H" level (VDD). At time t18, control circuit 3 lowers the signal LPC from the "H" level (VX2) back to the "L" level (VSS). This turns transistor 20 off, and the bus LBUS remains at the "H" level.

[0097] If the bus LBUS is charged, then the sensing amplifier 6 applies a voltage to the bus LBUS that is amplified from the voltage of node SEN (S20). Figure 8 As shown, at time t19, control circuit 3 raises signal STB from "L" level (VSS) to "H" level (VDD). This turns transistor 16 on. Consequently, transistor 15, corresponding to the off unit, becomes on based on the voltage difference between voltage Vsn2 and voltage Vth15, and the bus LBUS voltage drops. Let the bus LBUS voltage at this time be Vlb2. Voltages Vlb1 and Vlb2 are in the relationship Vlb2 ≤ Vlb1. On the other hand, transistor 15, corresponding to the on unit, becomes off based on the voltage difference between voltage Vsn2' and voltage Vth15, and the bus LBUS is maintained at approximately voltage VDD. Let the bus LBUS voltage at this time be Vlb2'. Voltages Vlb1' and Vlb2' are in the relationship Vlb1' ≤ Vlb2'. At time t20, control circuit 3 lowers signal STB from "H" level (VDD) to "L" level (VSS). This turns transistor 16 off, and the bus LBUS voltage is maintained. As a result, the logic level of the read data is determined. If the LBUS bus voltage is Vlb2, it is determined that the LBUS bus stores data at the "L" level; if the LBUS bus voltage is Vlb2', it is determined that the LBUS bus stores data at the "H" level. In other words, the digitization of the read data is complete.

[0098] If the logic level of the read data is determined, then logical operations using the determined logic level are performed (e.g., AND or OR operation of the determined data with the data in latch circuit ADL, AND or OR operation of the determined data with the data in latch circuit BDL, etc.). Additionally, the determined logic level can also be transmitted to latch circuit XDL.

[0099] 1.3 Effects

[0100] In this embodiment, the sensing circuit SA includes a node TDC for temporarily storing data. During readout, the sensing amplifier 6 amplifies the voltage difference between the voltage of node SEN and the threshold voltage of the transistor 15 whose gate is connected to node SEN by amplifying the voltage of node SEN. The sensing amplifier 6 performs digitization based on the amplified voltage difference. By using the node TDC instead of the latch circuits (SDL, ADL, and BDL), digitization can be performed without controlling the latch circuits or transmitting and receiving data between the latch circuits and the sensing circuit SA. Therefore, the time spent on digitization can be reduced. Thus, the operation of the NAND flash memory 1 can be accelerated. In addition, since the node TDC can be used instead of the latch circuits, digitization can be performed without increasing the number of latch circuits, thereby suppressing the increase in the area of ​​the NAND flash memory 1.

[0101] Furthermore, since the voltage difference between the voltage at node SEN and the threshold voltage of transistor 15 whose gate is connected to node SEN can be amplified, erroneous decisions during digitization can be suppressed.

[0102] 2. Second Implementation Method

[0103] The second embodiment will be described. The NAND flash memory 1 of this embodiment has the same configuration as that of the first embodiment. In this embodiment, the voltage amplification operation of node SEN in the first embodiment is performed twice. Hereinafter, the description will focus on the differences from the first embodiment.

[0104] 2.1 Reading Action

[0105] use Figure 9 and Figure 10 The read operation of the NAND flash memory 1 in this embodiment will be described. Figure 9 This is a flowchart illustrating the read operation of the NAND flash memory 1 in this embodiment. Figure 10 This is a timing diagram showing the voltages of various signals during the read operation of the NAND flash memory 1 in this embodiment.

[0106] After selecting the memory cell transistor MC for the read-out target, the control circuit 3 sets i = 1 (S30). Next, the sensing amplifier 6 performs S10 to S18 in the same manner as in the first embodiment. The voltages of various signals, etc., in S10 to S18 are the same as those in the first embodiment. Figure 7 and Figure 8 The same control is performed during the period from time t1 to time t16.

[0107] After implementing S18, control circuit 3 determines whether i = 2 (S31). If i is not 2 (S31, No), control circuit 3 increments i to i = i + 1 (S32), and then implements S15. Figure 10 As shown, at time t17, control circuit 3 raises signals LPC and L2T from the "L" level (VSS) to the "H" level (VX2). This turns transistors 20 and 21 on, and node TDC and bus LBUS are charged to the "H" level (VDD). At time t18, control circuit 3 lowers signals LPC and L2T from the "H" level (VX2) back to the "L" level (VSS). This turns transistors 20 and 21 off, and node TDC and bus LBUS remain at the "H" level.

[0108] After implementing S15, the sensing amplifier 6 implements S16. For example... Figure 10 As shown, at time t19, control circuit 3 raises signal L2T from "L" level (VSS) to "H" level (VX2) and signal STB from "L" level (VSS) to "H" level (VDD). This turns transistors 16 and 21 on. Consequently, transistor 15, corresponding to the off unit, becomes on based on the voltage difference between voltage Vsn2 and voltage Vth15, and the voltages of bus LBUS and node TDC drop. The voltage of bus LBUS at this time is set to Vlb2, and the voltage of node TDC is set to Vtd2. Voltage Vtd2 and voltage Vsn2 are in the relationship Vtd2 < Vsn2. On the other hand, transistor 15, corresponding to the on unit, becomes off based on the voltage difference between voltage Vsn2' and voltage Vth15, and bus LBUS and node TDC are maintained at approximately voltage VDD. The voltage of bus LBUS at this time is set to Vlb2', and the voltage of node TDC is set to Vtd2'. Voltages Vtd2' and Vsn2' are in a relationship where Vtd2' > Vsn2'. As a result, the voltage differences between Vth15 and Vsn2, and between Vth15 and Vsn2', are amplified. In other words, the voltage difference between Vsn2 and Vsn2' is amplified to the voltage difference between Vtd2 and Vtd2'. At time t20, control circuit 3 causes signal L2T to drop from "H" level (VX2) to "L" level (VSS), and signal STB to drop from "H" level (VDD) to "L" level (VSS). Consequently, transistors 16 and 21 are turned off, and the voltage at node TDC is maintained.

[0109] After implementing S16, the sensing amplifier 6 implements S17. For example... Figure 10As shown, at time t21, control circuit 3 raises signals LPC and BLQ from the "L" level (VSS) to the "H" level (VX2). This turns transistors 17 and 20 on, and node SEN and bus LBUS are charged to the "H" level (VDD). At time t22, control circuit 3 lowers signals LPC and BLQ from the "H" level (VX2) back to the "L" level (VSS). This turns transistors 17 and 20 off, and node SEN and bus LBUS remain at the "H" level.

[0110] After implementing S17, the sensing amplifier 6 implements S18. For example... Figure 10 As shown, at time t23, control circuit 3 raises signal LSL from "L" level (VSS) to "H" level (VDD). This turns transistor 19 on. Consequently, transistor 18, corresponding to the off-state, becomes on based on the voltage difference between voltage Vtd2 and voltage Vth18, and the voltage at node SEN drops. Let the voltage at node SEN at this time be Vsn3. Voltage Vsn3 and voltage Vtd2 are in a relationship of Vsn3 > Vtd2. On the other hand, transistor 18, corresponding to the on-state, becomes off based on the voltage difference between voltage Vtd2' and voltage Vth18, and node SEN remains approximately at voltage VDD. Let the voltage at node SEN at this time be Vsn3'. Voltage Vsn3' and voltage Vtd2' are in a relationship of Vsn3' < Vtd2'. As a result, the voltage difference between voltages Vsn2 and Vsn2' is amplified to the voltage difference between voltages Vsn3 and Vsn3' (e.g., amplified by a factor of 100). At time t24, control circuit 3 causes signal LSL to drop from the "H" level (VDD) to the "L" level (VSS). Consequently, transistor 19 becomes off, and the voltage at node SEN is maintained.

[0111] On the other hand, when i = 2 (S31, Yes), the sensing amplifier 6 implements S19. Figure 10 As shown, at time t25, control circuit 3 raises the signal LPC from the "L" level (VSS) to the "H" level (VX2). This turns transistor 20 on, and the bus LBUS is charged to the "H" level (VDD). At time t26, control circuit 3 lowers the signal LPC from the "H" level (VX2) back to the "L" level (VSS). This turns transistor 20 off, and the bus LBUS remains at the "H" level.

[0112] After implementing S19, the sensing amplifier 6 implements S20. For example... Figure 10As shown, at time t27, control circuit 3 raises signal STB from "L" level (VSS) to "H" level (VDD). This turns transistor 16 on. Consequently, transistor 15, corresponding to the off unit, becomes on based on the voltage difference between voltage Vsn3 and voltage Vth15, and the bus LBUS voltage drops. Let the bus LBUS voltage at this time be Vlb3. Voltages Vlb2 and Vlb3 are in the relationship Vlb3 ≤ Vlb2. On the other hand, transistor 15, corresponding to the on unit, becomes off based on the voltage difference between voltage Vsn3' and voltage Vth15, and the bus LBUS is maintained at approximately voltage VDD. Let the bus LBUS voltage at this time be Vlb3'. Voltages Vlb2' and Vlb3' are in the relationship Vlb2' ≤ Vlb3'. At time t28, control circuit 3 lowers signal STB from "H" level (VDD) to "L" level (VSS). This turns transistor 16 off, and the bus LBUS voltage is maintained. As a result, the logic level of the read data is determined. When the voltage of the LBUS bus is Vlb3, it is determined that the LBUS bus stores data at the "L" level; when the voltage of the LBUS bus is Vlb3', it is determined that the LBUS bus stores data at the "H" level.

[0113] If the logic level of the read data is determined, then the logic operation using the determined logic level is performed in the same manner as in the first embodiment. Additionally, the determined logic level can also be transmitted to the latch circuit XDL.

[0114] 2.2 Effects

[0115] According to the configuration of this embodiment, the same effects as in the first embodiment are achieved. Furthermore, in the configuration of this embodiment, during the readout operation, the sense amplifier 6 amplifies the voltage at node SEN twice. Since the voltage difference between node SEN and the threshold voltage of the transistor 15 whose gate is connected to node SEN can be amplified twice, erroneous judgments during digitization can be suppressed.

[0116] 3. Third Implementation Method

[0117] The third embodiment will be described. The NAND flash memory 1 of this embodiment has the same configuration as that of the first embodiment. In this embodiment, during the first voltage amplification operation of node SEN in the second embodiment, when applying the voltage obtained by amplifying the voltage of node TDC to node SEN, the operation during the second voltage amplification operation of node SEN is performed; that is, the voltage obtained by amplifying the voltage of node SEN is applied to node TDC. Hereinafter, the description will focus on the differences from the first and second embodiments.

[0118] 3.1 Reading Action

[0119] use Figure 11 and Figure 12 The read operation of the NAND flash memory 1 in this embodiment will be described. Figure 11 This is a flowchart illustrating the read operation of the NAND flash memory 1 in this embodiment. Figure 12 This is a timing diagram showing the voltages of various signals during the read operation of the NAND flash memory 1 in this embodiment.

[0120] After selecting the memory cell transistor MC of the read-out target, the control circuit 3 sets i = 1 (S40). Next, the sensing amplifier 6 performs S10 to S17 in the same manner as in the first embodiment. The voltages of various signals, etc., in S10 to S17 are the same as those in the first embodiment. Figure 7 and Figure 8 The same control is performed during the period from time t1 to time t14.

[0121] After implementing S17, the sensing amplifier 6 implements S18. For example... Figure 12 As shown, at time t15, control circuit 3 raises signal LSL from "L" level (VSS) to "H" level (VDD). This turns transistor 19 on. Consequently, transistor 18, corresponding to the off-state, becomes on based on the voltage difference between voltage Vtd1 and the threshold voltage Vth18 of transistor 18, and the voltage at node SEN drops. Let the voltage at node SEN at this time be Vsn2. Voltage Vsn2 is in a relationship of Vsn2 > Vtd1. On the other hand, transistor 18, corresponding to the on-state, becomes off based on the voltage difference between voltage Vtd1' and voltage Vth18, and node SEN remains approximately at voltage VDD. Let the voltage at node SEN at this time be Vsn2'. Voltage Vsn2' is in a relationship of Vsn2' < Vtd1'. As a result, the voltage difference between voltages Vsn1 and Vsn1' is amplified to the voltage difference between voltages Vsn2 and Vsn2' (e.g., amplified by a factor of 100). At time t17, control circuit 3 causes signal LSL to drop from the "H" level (VDD) to the "L" level (VSS). Consequently, transistor 19 becomes off, and the voltage at node SEN is maintained.

[0122] After starting S18, control circuit 3 determines whether i = 2 (S41). If i is not 2 (S41, No), control circuit 3 increments i to i = i + 1 (S42), and then executes S16. For example... Figure 12As shown, at time t16, control circuit 3 raises signal L2T from "L" level (VSS) to "H" level (VX2) and signal STB from "L" level (VSS) to "H" level (VDD). This turns transistors 16 and 21 on. Consequently, transistor 15, corresponding to the off unit, becomes on based on the voltage difference between voltage Vth15 and voltage Vsn2, causing the bus LBUS voltage to drop and the node TDC voltage to rise. Let the bus LBUS voltage at this time be Vlb2, and the node TDC voltage be Vtd2. Voltage Vtd2 and voltage Vsn2 are in the relationship Vtd2 < Vsn2. On the other hand, transistor 15, corresponding to the on unit, becomes off based on the voltage difference between voltage Vsn2' and voltage Vth15, and the bus LBUS and node TDC are approximately maintained at voltage VDD. Let the bus LBUS voltage at this time be Vlb2', and the node TDC voltage be Vtd2'. Voltages Vtd2' and Vsn2' are in a relationship where Vtd2' > Vsn2'. As a result, the voltage differences between Vth15 and Vsn2, and between Vth15 and Vsn2', are amplified. In other words, the voltage difference between Vsn2 and Vsn2' is amplified to the voltage difference between Vtd2 and Vtd2'. At time t18, control circuit 3 causes signal L2T to drop from "H" level (VX2) to "L" level (VSS), and signal STB to drop from "H" level (VDD) to "L" level (VSS). Consequently, transistors 16 and 21 are turned off, and the voltage at node TDC is maintained.

[0123] After implementing S16, the sensing amplifier 6 implements S17. For example... Figure 12 As shown, at time t19, control circuit 3 raises signals LPC and BLQ from the "L" level (VSS) to the "H" level (VX2). This turns transistors 17 and 20 on, and node SEN and bus LBUS are charged to the "H" level (VDD). At time t20, control circuit 3 lowers signals LPC and BLQ from the "H" level (VX2) back to the "L" level (VSS). This turns transistors 17 and 20 off, and node SEN and bus LBUS remain at the "H" level.

[0124] After implementing S17, the sensing amplifier 6 implements S18. For example... Figure 12As shown, at time t21, control circuit 3 raises signal LSL from "L" level (VSS) to "H" level (VDD). This turns transistor 19 on. Consequently, transistor 18, corresponding to the off-state, becomes on based on the voltage difference between voltage Vtd2 and voltage Vth18, and the voltage at node SEN drops. Let the voltage at node SEN at this time be Vsn3. Voltage Vsn3 and voltage Vtd2 are in a relationship of Vsn3 > Vtd2. On the other hand, transistor 18, corresponding to the on-state, becomes off based on the voltage difference between voltage Vtd2' and voltage Vth18, and node SEN remains approximately at voltage VDD. Let the voltage at node SEN at this time be Vsn3'. Voltage Vsn3' and voltage Vtd2' are in a relationship of Vsn3' < Vtd2'. As a result, the voltage difference between voltages Vsn2 and Vsn2' is amplified to the voltage difference between voltages Vsn3 and Vsn3' (e.g., amplified by 100 times). At time t22, control circuit 3 causes signal LSL to drop from the "H" level (VDD) to the "L" level (VSS). Thus, transistor 19 becomes off, and the voltage at node SEN is maintained.

[0125] On the other hand, when i = 2 (S41, yes), the sensing amplifier 6 implements S19. Figure 12 As shown, at time t23, control circuit 3 raises the signal LPC from the "L" level (VSS) to the "H" level (VX2). This turns transistor 20 on, and the bus LBUS is charged to the "H" level (VDD). At time t24, control circuit 3 lowers the signal LPC from the "H" level (VX2) back to the "L" level (VSS). This turns transistor 20 off, and the bus LBUS remains at the "H" level.

[0126] After implementing S19, the sensing amplifier 6 implements S20. For example... Figure 12As shown, at time t25, control circuit 3 raises signal STB from "L" level (VSS) to "H" level (VDD). This turns transistor 16 on. Consequently, transistor 15, corresponding to the off unit, becomes on based on the voltage difference between voltage Vsn3 and voltage Vth15, and the bus LBUS voltage drops. Let the bus LBUS voltage at this time be Vlb3. Voltages Vlb2 and Vlb3 are in the relationship Vlb3 ≤ Vlb2. On the other hand, transistor 15, corresponding to the on unit, becomes off based on the voltage difference between voltage Vsn3' and voltage Vth15, and the bus LBUS is approximately maintained at voltage VDD. Let the bus LBUS voltage at this time be Vlb3'. Voltages Vlb2' and Vlb3' are in the relationship Vlb2' ≤ Vlb3'. At time t26, control circuit 3 lowers signal STB from "H" level (VDD) to "L" level (VSS). This turns transistor 16 off, and the bus LBUS voltage is maintained. As a result, the logic level of the read data is determined. When the voltage of the LBUS bus is Vlb3, it is determined that the LBUS bus stores data at the "L" level; when the voltage of the LBUS bus is Vlb3', it is determined that the LBUS bus stores data at the "H" level.

[0127] If the logic level of the read data is determined, then the logic operation using the determined logic level is performed in the same manner as in the first embodiment. Additionally, the determined logic level can also be transmitted to the latch circuit XDL.

[0128] 3.2 Effects

[0129] According to the configuration of this embodiment, the same effects as in the second embodiment are achieved. Furthermore, in the configuration of this embodiment, during the readout operation, while the sensing amplifier 6 applies the voltage obtained by amplifying the voltage of node TDC to node SEN during the first amplification operation of node SEN, it performs the following operation: during the second amplification operation of node SEN, it applies the voltage obtained by amplifying the voltage of node SEN to node TDC. Therefore, digitization can be performed without charging node TDC between the first and second amplification operations of node SEN. Thus, the time spent on digitization can be reduced.

[0130] 4. Fourth Implementation Method

[0131] The fourth embodiment will be described. In this embodiment, the sense amplifier assembly SAU included in the NAND flash memory 1 of the first embodiment is modified by removing the transistor 21 and the capacitor element 25, and adding an n-channel MOS transistor 26. Hereinafter, the description will focus on the differences from the first embodiment.

[0132] 4.1 Circuit configuration of the sensing amplifier component SAU

[0133] use Figure 13 The circuit configuration of the sensing amplifier component SAU will be explained. Figure 13 This is a circuit diagram of the sense amplifier assembly SAU included in the NAND flash memory 1 of this embodiment.

[0134] Figure 13 One sense amplifier component SAU from the plurality of sense amplifier components SAUs included in sense amplifier 6 is selected to represent an example of the circuit configuration of sense amplifier component SAU. The other sense amplifier components SAUs also have... Figure 13 The structure shown.

[0135] The sensing circuit SA includes n-channel MOS transistors 10-20, 22 and 26, p-channel MOS transistor 23, and capacitor element 24.

[0136] The gate of transistor 26 is input with the signal LSW, and one end of its current path is connected to the bus LBUS. The gate of transistor 17 is input with the signal BLQ, one end of its current path is connected to node SEN, and the other end of its current path is connected to the other end of the current path of transistor 26. The gate of transistor 18 is connected to the bus LBUS, one end of its current path is connected to one end of the current path of transistor 19, and the other end of its current path is subject to a voltage VLOP. The gate of transistor 20 is input with the signal LPC, one end of its current path is connected to the other end of the current path of transistor 26, and the other end of its current path is subject to a voltage VHLB. The gate of transistor 22 is input with the signal DSW, one end of its current path is connected to the other end of the current path of transistor 26, and the other end of its current path is connected to the bus DBUS. Other configurations of the sensing circuit SA are the same as in the first embodiment. Figure 5 same.

[0137] 4.2 Reading Action

[0138] use Figures 14-16 The read operation of the NAND flash memory 1 in this embodiment will be described. Figure 14 This is a flowchart illustrating the read operation of the NAND flash memory 1 in this embodiment. Figure 15 and Figure 16 This is a timing diagram showing the voltages of various signals during the read operation of the NAND flash memory 1 in this embodiment.

[0139] After selecting the memory cell transistor MC of the read-out object, the sense amplifier 6 precharges the bit line BL (S50). Figure 15As shown, at time t1, control circuit 3, in the same manner as in the first embodiment, raises signal BLC from "L" level (VSS) to "H" level (VBLC) and signal BLX from "L" level (VSS) to "H" level (VBLX). Consequently, transistors 10 and 11 are turned on, and bit line BL is pre-charged. The pre-charging of bit line BL occurs between time t1 and time t5.

[0140] During the pre-charging process of bit line BL, sense amplifier 6 pre-charges node SEN (S51). For example... Figure 15 As shown, at time t2, control circuit 3, in the same manner as in the first embodiment, raises signals LPC and BLQ from the "L" level (VSS) to the "H" level (VX2). Consequently, transistors 17 and 20 are turned on, and node SEN is pre-charged to the "H" level (VDD). At time t3, control circuit 3, in the same manner as in the first embodiment, lowers signals LPC and BLQ from the "H" level (VX2) to the "L" level (VSS). Consequently, transistors 17 and 20 are turned off, and node SEN remains at the "H" level.

[0141] If node SEN is pre-charged, then control circuit 3 applies voltage VDDSA to node CLKSA (S52). Figure 15 As shown, at time t4, control circuit 3, in the same manner as in the first embodiment, raises the voltage of node CLKSA from the "L" level (VSS) to the "H" level (VDDSA). As a result, capacitor element 24 is charged, and the voltage of node SEN rises to voltage Vcu due to capacitive coupling.

[0142] After the clock rises, sense amplifier 6 senses the voltage at node SEN (S53). Figure 15 As shown, at time t5, control circuit 3, in the same manner as in the first embodiment, raises signal XXL from the "L" level (VSS) to the "H" level (VXXL). In this state, if the threshold voltage of the memory cell transistor MC of the read target is higher than the read voltage (e.g., VA, VB, VC, ...), the memory cell transistor MC is in the off state (off cell), and the voltage of node SEN hardly changes. On the other hand, if the threshold voltage of the memory cell transistor MC of the read target is lower than the read voltage, the memory cell transistor MC is in the on state (on cell), and the voltage of node SEN drops. At time t6, control circuit 3, in the same manner as in the first embodiment, lowers signal XXL from the "H" level (VXXL) to the "L" level (VSS).

[0143] When the voltage at node SEN is sensed, control circuit 3 applies voltage VSS to node CLKSA (S54). For example... Figure 15As shown, at time t7, control circuit 3, in the same manner as in the first embodiment, causes the voltage of node CLKSA to drop from the "H" level (VDD) to the "L" level (VSS). As a result, due to capacitive coupling, the voltage of node SEN drops. Specifically, as... Figure 15 As shown, the voltage corresponding to node SEN of the disconnected unit is Vsn1 (Vth15 or higher, VDD or lower). Conversely, the voltage corresponding to node SEN of the connected unit is Vsn1' (VSS or higher, but less than Vth15).

[0144] After the clock falls, the sense amplifier 6 charges the LBUS bus (S55). For example... Figure 16 As shown, at time t9, control circuit 3 raises signals LPC and LSW from the "L" level (VSS) to the "H" level (VX2). This turns transistors 20 and 26 on, and the bus LBUS is charged to the "H" level (VDD). At time t10, control circuit 3 lowers signals LPC and LSW from the "H" level (VX2) back to the "L" level (VSS). This turns transistors 20 and 26 off, and the bus LBUS remains at the "H" level. Furthermore, the bus LBUS takes any value between VSS and VDD during the period from time t1 to time t2.

[0145] If the bus LBUS is charged, then the sensing amplifier 6 applies a voltage to the bus LBUS that is amplified from the voltage at node SEN (S56). Figure 16As shown, at time t11, control circuit 3 raises signal LSW from "L" level (VSS) to "H" level (VX2) and signal STB from "L" level (VSS) to "H" level (VDD). This turns transistors 16 and 26 on. Consequently, transistor 15, corresponding to the off unit, becomes a weaker on state based on the voltage difference between voltage Vsn1 and voltage Vth15, and the bus LBUS voltage drops. Let the bus LBUS voltage at this time be Vlb1. Voltage Vlb1 and voltage Vsn1 are in a relationship of Vlb1 < Vsn1. On the other hand, transistor 15, corresponding to the on unit, becomes a weaker off state based on the voltage difference between voltage Vsn1' and voltage Vth15, and the bus LBUS is approximately maintained at voltage VDD (or slightly reduced). Let the bus LBUS voltage at this time be Vlb1'. Voltage Vlb1' and voltage Vsn1' are in a relationship of Vlb1' > Vsn1'. As a result, the voltage difference between Vth15 and Vsn1, and the voltage difference between Vth15 and Vsn1', are amplified. In other words, the voltage difference between Vsn1 and Vsn1' is amplified to the voltage difference between Vlb1 and Vlb1'. At time t12, control circuit 3 causes signal LSW to drop from "H" level (VX2) to "L" level (VSS), and signal STB to drop from "H" level (VDD) to "L" level (VSS). Therefore, transistors 16 and 26 are turned off, and the voltage of the bus LBUS is maintained.

[0146] If a voltage amplified from the voltage at node SEN is applied to the bus LBUS, then the sensing amplifier 6 will charge node SEN (S57). Figure 16 As shown, at time t13, control circuit 3, in the same manner as in the first embodiment, raises signals LPC and BLQ from the "L" level (VSS) to the "H" level (VX2). Consequently, transistors 17 and 20 are turned on, and node SEN is charged to the "H" level (VDD). At time t14, control circuit 3, in the same manner as in the first embodiment, lowers signals LPC and BLQ from the "H" level (VX2) to the "L" level (VSS). Consequently, transistors 17 and 20 are turned off, and node SEN remains at the "H" level.

[0147] If node SEN is charged, then sense amplifier 6 applies a voltage to node SEN that is amplified from the voltage of bus LBUS (S58). Figure 16As shown, at time t15, control circuit 3, similar to the first embodiment, raises signal LSL from "L" level (VSS) to "H" level (VDD). This turns transistor 19 on. Consequently, transistor 18, corresponding to the off-state, becomes on based on the voltage difference between voltage Vtd1 and voltage Vth18, and the voltage at node SEN drops. Let the voltage at node SEN at this time be Vsn2. Voltage Vsn2 and voltage Vtd1 are in a relationship of Vsn2 > Vtd1. On the other hand, transistor 18, corresponding to the on-state, becomes off based on the voltage difference between voltage Vtd1' and voltage Vth18, and node SEN remains approximately at voltage VDD. Let the voltage at node SEN at this time be Vsn2'. Voltage Vsn2' and voltage Vtd1' are in a relationship of Vsn2' < Vtd1'. As a result, the voltage difference between voltages Vsn1 and Vsn1' is amplified to the voltage difference between voltages Vsn2 and Vsn2' (e.g., amplified by a factor of 100). At time t16, control circuit 3, in the same manner as in the first embodiment, causes signal LSL to drop from the "H" level (VDD) to the "L" level (VSS). Thus, transistor 19 becomes off, and the voltage at node SEN is maintained.

[0148] If a voltage amplified from the voltage of the bus LBUS is applied to node SEN, then the sensing amplifier 6 will charge the bus LBUS (S59). Figure 16 As shown, at time t17, control circuit 3, like S55, raises signals LPC and LSW from the "L" level (VSS) to the "H" level (VX2). This turns transistors 20 and 26 on, and the bus LBUS is charged to the "H" level (VDD). At time t18, control circuit 3, like S55, lowers signals LPC and LSW from the "H" level (VX2) to the "L" level (VSS). This turns transistors 20 and 26 off, and the bus LBUS remains at the "H" level.

[0149] If the bus LBUS is charged, then the sensing amplifier 6 applies a voltage to the bus LBUS that is amplified from the voltage at node SEN (S60). Figure 16As shown, at time t19, control circuit 3, like S56, raises signal LSW from "L" level (VSS) to "H" level (VX2) and signal STB from "L" level (VSS) to "H" level (VDD). This turns transistors 16 and 26 on. Consequently, transistor 15, corresponding to the off unit, becomes on based on the voltage difference between voltage Vsn2 and voltage Vth15, and the bus LBUS voltage drops. The bus LBUS voltage at this time is set to Vlb2. Voltages Vlb1 and Vlb2 are in a relationship of Vlb2 ≤ Vlb1. On the other hand, transistor 15, corresponding to the on unit, becomes off based on the voltage difference between voltage Vsn2' and voltage Vth15, and the bus LBUS is approximately maintained at voltage VDD. The bus LBUS voltage at this time is set to Vlb2'. Voltages Vlb1' and Vlb2' are in a relationship of Vlb1' ≤ Vlb2'. At time t20, control circuit 3, like S56, causes signal LSW to drop from "H" level (VX2) to "L" level (VSS), and signal STB to drop from "H" level (VDD) to "L" level (VSS). As a result, transistors 16 and 26 are turned off, and the voltage of the bus LBUS is maintained. Consequently, the logic level of the read data is determined. If the bus LBUS voltage is Vlb2, it is determined that the bus LBUS stores data at the "L" level; if the bus LBUS voltage is Vlb2', it is determined that the bus LBUS stores data at the "H" level.

[0150] If the logic level of the read data is determined, then the logic operation using the determined logic level is performed in the same manner as in the first embodiment. Additionally, the determined logic level can also be transmitted to the latch circuit XDL.

[0151] 4.3 Effects

[0152] According to the configuration of this embodiment, it achieves the same effect as the first embodiment.

[0153] 5. Examples of variations, etc.

[0154] As described above, the semiconductor memory device of the embodiment includes: a memory cell (MC) capable of storing data; a bit line (BL) electrically connected to the memory cell; and a sense amplifier (6) electrically connected to the bit line, and includes a first circuit (SA) and a latch circuit (S / A / BDL). The first circuit includes: a first node (SEN) electrically connected to the bit line, and transferring charge to the bit line according to the data of the memory cell during the read operation of the memory cell; a first transistor (15) with its gate connected to the first node, and the first transistor can be connected to a second node (LBUS) connected to the latch circuit; a second transistor (21) capable of connecting the second node to a third node (TDC); and a third transistor (18) with its gate connected to the third node, and the third transistor can be connected to the first node. During the readout operation, the sensing amplifier senses the first voltage at the first node (SEN) when charge is transferred to the bit line, applies a second voltage obtained by amplifying the first voltage to the third node (TDC), and applies a third voltage obtained by amplifying the second voltage to the first node (SEN).

[0155] Furthermore, the implementation method is not limited to the method described above, and various variations are possible.

[0156] 5.1 Example of the first variation

[0157] The first variation will be described. This variation is obtained by applying the fourth embodiment to the second embodiment. In this variation, the flowchart showing the readout operation is based on the second embodiment. Figure 9 S10 to S20 are changed to the fourth embodiment. Figure 14 The voltages of the various signals in S50 to S60 are obtained. Furthermore, in this variation, the voltages of the various signals in S30 and S50 to S58 are the same as those in the fourth embodiment. Figure 15 and Figure 16 Control is performed similarly during the period from time t1 to time t16. After implementing S58, the voltages of various signals in S31, S32, and S55 to S60 are the same as those in the second embodiment. Figure 10 Control is performed similarly from time t16 to time t28. After time t16, the signal LSW rises to VX2 at time t17 and falls to VSS at time t18 (charging of the bus LBUS). The signal LSW rises to VX2 at time t19 and falls to VSS at time t20 (applying a voltage amplified from the voltage of node SEN to the bus LBUS). The signal LSW rises to VX2 at time t25 and falls to VSS at time t26 (charging of the bus LBUS). The signal LSW rises to VX2 at time t27 and falls to VSS at time t28 (applying a voltage amplified from the voltage of node SEN to the bus LBUS). According to this variation, the same effects as in the second embodiment are achieved.

[0158] 5.2 Second Variation Example

[0159] The second variation will be described. This variation is obtained by applying the fourth embodiment to the third embodiment. In this variation, the flowchart showing the readout operation is based on the third embodiment. Figure 11 S10 to S20 are changed to the fourth embodiment. Figure 14 The voltages of the various signals in S50 to S60 are obtained. Furthermore, in this variation, the voltages of the various signals in S40 and S50 to S57 are the same as those in the fourth embodiment. Figure 15 and Figure 16 Control is performed similarly during the period from time t1 to time t14. After implementing S57, the voltages of various signals in S58, S41, S42, and S58-S60 are the same as those in the third embodiment. Figure 12 Control is performed similarly during the period from time t14 to time t25. After time t14, the signal LSW rises to VX2 at time t16 and falls to VSS at time t18 (applying a voltage amplified from the voltage of node SEN to the bus LBUS). The signal LSW rises to VX2 at time t23 and falls to VSS at time t24 (charging of the bus LBUS). The signal LSW rises to VX2 at time t25 and falls to VSS at time t26 (applying a voltage amplified from the voltage of node SEN to the bus LBUS). According to this variation, the same effects as in the third embodiment are achieved.

[0160] Furthermore, the processing order of the flowcharts described in the embodiments can be changed to the extent possible.

[0161] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in many other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and are also included within the scope of the invention as described in the claims and their equivalents.

[0162] [Explanation of Symbols]

[0163] 1: NAND flash memory

[0164] 2: Storage cell array

[0165] 3: Control Circuit

[0166] 4: Voltage generation circuit

[0167] 5: Line decoder

[0168] 6: Sensing Amplifier

[0169] 10~23, 26, 30~37, 40~47, 50~57: Transistors

[0170] 24, 25: Capacitor components.

Claims

1. A semiconductor memory device comprising: Storage unit, capable of storing data; Bit lines are electrically connected to the memory cells; and A sensing amplifier is electrically connected to the bit line and includes a first circuit and a latching circuit. The first circuit includes: The first node is electrically connected to the bit line and, during the read operation of the memory cell, transfers charge to the bit line according to the data of the memory cell; The first transistor has its gate connected to the first node, and the first transistor can be connected to the second node connected to the latch circuit; The second transistor is capable of connecting the second node to the third node; and The third transistor has its gate connected to the third node, and this third transistor can also be connected to the first node; and During the readout operation, the sensing amplifier senses the first voltage of the first node when charge is transferred to the bit line, applies a second voltage amplified from the first voltage to the third node, and applies a third voltage amplified from the second voltage to the first node.

2. The semiconductor memory device of claim 1, wherein the sensing amplifier applies a fourth voltage to the second node, which is obtained by amplifying the third voltage.

3. The semiconductor memory device according to claim 1, wherein the sensing amplifier applies a fourth voltage amplified from the third voltage to the third node and a fifth voltage amplified from the fourth voltage to the first node.

4. The semiconductor memory device of claim 1, wherein the sense amplifier applies a fifth voltage, amplified from the third voltage, to the first node while applying a fourth voltage, amplified from the third voltage, to the third node.

5. The semiconductor memory device according to claim 3 or 4, wherein the sensing amplifier applies a sixth voltage to the second node, which is an amplification of the fifth voltage.

6. A semiconductor memory device comprising: Storage unit, capable of storing data; Bit lines are electrically connected to the memory cells; and A sensing amplifier is electrically connected to the bit line and includes a first circuit and a latching circuit. The first circuit includes: The first node is electrically connected to the bit line and, during the read operation of the memory cell, transfers charge to the bit line according to the data of the memory cell; The first transistor has its gate connected to the first node, and the first transistor can be connected to the second node connected to the latch circuit; The second transistor is capable of connecting the second node to the first transistor; and The third transistor has its gate connected to the second node, and this third transistor can also be connected to the first node; and During the readout operation, the sensing amplifier senses the first voltage of the first node when charge is transferred to the bit line, applies a second voltage amplified from the first voltage to the second node, and applies a third voltage amplified from the second voltage to the first node. The sensing amplifier applies a fourth voltage to the second node, which is an amplification of the third voltage.

7. A semiconductor memory device comprising: Storage unit, capable of storing data; Bit lines are electrically connected to the memory cells; and A sensing amplifier is electrically connected to the bit line and includes a first circuit and a latching circuit. The first circuit includes: The first node is electrically connected to the bit line and, during the read operation of the memory cell, transfers charge to the bit line according to the data of the memory cell; The first transistor has its gate connected to the first node, and the first transistor can be connected to the second node connected to the latch circuit; The second transistor is capable of connecting the second node to the first transistor; and The third transistor has its gate connected to the second node, and this third transistor can also be connected to the first node; and During the readout operation, the sensing amplifier senses the first voltage of the first node when charge is transferred to the bit line, applies a second voltage amplified from the first voltage to the second node, and applies a third voltage amplified from the second voltage to the first node. The sensing amplifier applies a fourth voltage, which is an amplification of the third voltage, to the second node, and a fifth voltage, which is an amplification of the fourth voltage, to the first node.

8. The semiconductor memory device of claim 7, wherein the sensing amplifier applies a sixth voltage to the second node, which is an amplification of the fifth voltage.

9. A semiconductor memory device comprising: Storage unit, capable of storing data; Bit lines are electrically connected to the memory cells; and A sensing amplifier is electrically connected to the bit line and includes a first circuit and a latching circuit. The first circuit includes: The first node is electrically connected to the bit line and, during the read operation of the memory cell, transfers charge to the bit line according to the data of the memory cell; The first transistor has its gate connected to the first node, and the first transistor can be connected to the second node connected to the latch circuit; The second transistor is capable of connecting the second node to the first transistor; and The third transistor has its gate connected to the second node, and this third transistor can also be connected to the first node; and During the readout operation, the sensing amplifier senses the first voltage of the first node when charge is transferred to the bit line, applies a second voltage amplified from the first voltage to the second node, and applies a third voltage amplified from the second voltage to the first node. While the sensing amplifier applies a fourth voltage, which is amplified from the third voltage, to the second node, it applies a fifth voltage, which is amplified from the fourth voltage, to the first node.

10. The semiconductor memory device of claim 9, wherein the sensing amplifier applies a sixth voltage to the second node, which is an amplification of the fifth voltage.

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