Three-dimensional semiconductor device

Abstract

A three-dimensional semiconductor device can include a substrate; bit lines including a first bit line and a second bit line spaced apart from each other; a semiconductor pattern on the bit lines; a word line on the semiconductor pattern and extending in a second direction; a first global bit line on the first bit line and extending in a third direction; a second global bit line on the second bit line and extending in the third direction; and a first via on a top surface of the second bit line and between the second bit line and the second global bit line. A distance from a bottom surface of the substrate to a top surface of the first global bit line in a first direction can be different from a distance from the bottom surface of the substrate to a top surface of the second global bit line.

Description

Cross-references to related applications

[0001] This patent application claims priority to Korean Patent Application No. 10-2024-0166520, filed on November 20, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to three-dimensional semiconductor devices. Background Technology

[0003] Due to their small size, multiple functions, and / or low cost, semiconductor devices are essential components in the electronics industry. Semiconductor devices can be classified into semiconductor memory devices for storing data, semiconductor logic devices for processing data, and hybrid semiconductor devices that include both memory and logic elements.

[0004] With the trend towards high speed and low power consumption in electronic devices, semiconductor devices in these devices also need to have high operating speeds and / or low operating voltages. To meet this requirement, the integration density of semiconductor devices must be increased. However, with the increase in semiconductor device integration density, problems such as deterioration of electrical characteristics and low production yield may occur. Therefore, many studies are underway to improve the electrical characteristics and production yield of semiconductor devices. Summary of the Invention

[0005] Some embodiments of the present invention provide a semiconductor device with improved reliability.

[0006] According to some embodiments of the present invention, a three-dimensional (3D) semiconductor device may include: a substrate; bit lines on the substrate, extending along a first direction perpendicular to the bottom surface of the substrate, and including a first bit line and a second bit line, the first bit line and the second bit line being spaced apart from each other and adjacent to each other in a second direction parallel to the bottom surface of the substrate; a semiconductor pattern on the bit lines, extending along a third direction perpendicular to the first and second directions; word lines on the semiconductor pattern, extending along the second direction; a first global bit line on the first bit line, extending along the third direction; a second global bit line on the second bit line, extending along the third direction; and a first via on the top surface of the second bit line, and between the second bit line and the second global bit line. The distance from the bottom surface of the substrate to the top surface of the first global bit line in the first direction may be different from the distance from the bottom surface of the substrate to the top surface of the second global bit line in the first direction.

[0007] According to some embodiments of the present invention, a three-dimensional (3D) semiconductor device may include: a substrate; bit lines extending on the substrate along a first direction perpendicular to the bottom surface of the substrate, and including a first bit line and a second bit line, the first bit line and the second bit line being spaced apart from each other in a second direction parallel to the bottom surface of the substrate; a semiconductor pattern extending on the bit lines along a third direction perpendicular to the first and second directions; word lines extending on the semiconductor pattern in the second direction; a first global bit line extending on the first bit line in the third direction; a second global bit line extending on the second bit line in the third direction; and a via between the second bit line and the second global bit line, overlapping the second bit line and the second global bit line in the first direction. The distance from the bottom surface of the substrate to the bottom surface of the via in the first direction may be the same as the distance from the bottom surface of the substrate to the bottom surface of the first global bit line in the first direction, and the via may be adjacent to the first global bit line in the second direction, and the distance from the bottom surface of the substrate to the top surface of the via in the first direction may be greater than the distance from the bottom surface of the substrate to the top surface of the first global bit line in the first direction.

[0008] According to some embodiments of the present invention, a three-dimensional (3D) semiconductor device may include: a substrate; a first stack and a second stack on the substrate and adjacent to each other in a first direction parallel to the bottom surface of the substrate; and a data storage pattern between the first stack and the second stack. Each of the first stack and the second stack may include: a bit line extending along a second direction perpendicular to the bottom surface of the substrate and spaced apart from each other in a third direction perpendicular to the first and second directions; a semiconductor pattern on the bit line and extending along the first direction; and a word line on the semiconductor pattern and extending along a third direction. The 3D semiconductor device may further include: a global bit line extending along the first direction and electrically connecting at least one bit line of the first stack to at least one bit line of the second stack, the global bit lines being spaced apart from each other in a third direction. The global bit line may include: a first global bit line; and a second global bit line, wherein the distance from the bottom surface of the substrate to the top surface of the second global bit line in the second direction may be different from the distance from the bottom surface of the substrate to the top surface of the first global bit line in the second direction, at least one first global bit line may be adjacent to at least one second global bit line in the third direction, and the distance from the bottom surface of the substrate to the top surface of the data storage pattern in the second direction may be greater than the distance from the bottom surface of the substrate to the top surface of the word line in the second direction. Attached Figure Description

[0009] Figure 1 This is a schematic diagram illustrating a three-dimensional semiconductor device according to an embodiment of the present invention.

[0010] Figure 2A , Figure 2B and Figure 2C This is a schematic perspective view of a three-dimensional semiconductor device according to an embodiment of the present invention.

[0011] Figure 3 This is a perspective view illustrating the semiconductor pattern, word line, bit line, global bit line, and data storage pattern of a three-dimensional semiconductor device according to an embodiment of the present invention.

[0012] Figure 4 This is a plan view illustrating a three-dimensional semiconductor device according to an embodiment of the present invention.

[0013] Figure 5A It is along Figure 4 A cross-sectional view taken from line A-A'.

[0014] Figure 5B It is along Figure 4 The cross-sectional view taken by line B-B'.

[0015] Figure 5C It is along Figure 4 A cross-sectional view taken from line C-C'.

[0016] Figure 6 This is a plan view illustrating a three-dimensional semiconductor device according to an embodiment of the present invention.

[0017] Figure 7 It is along Figure 6 A cross-sectional view taken from line C-C'.

[0018] Figure 8 This is a plan view illustrating a three-dimensional semiconductor device according to an embodiment of the present invention.

[0019] Figure 9A It is along Figure 8 A cross-sectional view taken from line C-C'.

[0020] Figure 9B It is along Figure 8 The cross-sectional view taken by line D-D'.

[0021] Figure 10 This is a plan view illustrating a three-dimensional semiconductor device according to an embodiment of the present invention.

[0022] Figure 11 It is along Figure 10 The cross-sectional view taken by line D-D'.

[0023] Figure 12A , Figure 12B , Figure 12C , Figure 13A , Figure 13B , Figure 13C , Figure 14A , Figure 14B and Figure 14C This is a diagram illustrating a method for manufacturing a three-dimensional semiconductor device according to an embodiment of the present invention. Detailed Implementation

[0024] Exemplary embodiments of this disclosure will now be described more fully with reference to the accompanying drawings, which illustrate exemplary embodiments.

[0025] Throughout this specification, the terms “around,” “cover,” or “enclose” as used herein may not require complete surrounding, covering, or enclosing of the element or layer, but may, for example, refer to partially surrounding, covering, or enclosing the element or layer, e.g., having gaps or other spaces. The term “and / or” includes any and all combinations of one or more of the listed items. The term “connection” may be used herein to refer to physical and / or electrical connections.

[0026] Figure 1 This is a schematic diagram illustrating a three-dimensional semiconductor device according to an embodiment of the present invention.

[0027] Reference Figure 1 The three-dimensional semiconductor device may include a memory cell array 1, a row decoder 2, a sensing amplifier 3, a column decoder 4, and control logic 5.

[0028] The memory cell array 1 may include word lines WL, bit lines BL, source lines SL, and memory cells MC. The memory cells MC may be arranged in three dimensions, and each memory cell MC may be connected to one of the word lines WL, one of the bit lines BL, and one of the source lines SL. In some embodiments, each memory cell MC may consist of a transistor including a memory layer or a data storage layer.

[0029] The row decoder 2 can be configured to decode address information input from an external source and select one of the word lines WL of the memory cell array 1 based on the decoded address information. The address information decoded by the row decoder 2 can be provided to the row driver (not shown), and in this case, the row driver can, in response to the control of the control circuit, provide corresponding voltages to one of the selected word lines WL and the unselected word lines WL.

[0030] The sensing amplifier 3 can be configured to sense, amplify, and output the voltage difference between a bit line selected by the address information decoded by the column decoder 4 and a reference bit line in the bit line BL.

[0031] The column decoder 4 can establish a data transmission path between the sense amplifier 3 and an external device (e.g., a memory controller). The column decoder 4 can be configured to decode address information input from an external source and select one of the bit lines BL based on the decoded address information.

[0032] Control logic 5 can be configured to generate control signals, which are used to control data write operations or data read operations on storage cell array 1.

[0033] Figure 2A , Figure 2B and Figure 2C This is a schematic perspective view of a three-dimensional semiconductor device according to some embodiments of the present invention.

[0034] Reference Figure 2A The three-dimensional semiconductor device may include a substrate 100, a peripheral circuit structure PS on the substrate 100, and a cell array structure CS on the peripheral circuit structure PS.

[0035] The peripheral circuit structure PS may include core circuitry and peripheral circuitry formed on substrate 100. The core circuitry and peripheral circuitry may include reference... Figure 1 The row decoder 2 and column decoder 4, the sensing amplifier 3 and the control logic 5 are described.

[0036] The substrate 100 may be a plate-like structure extending parallel to a plane defined by a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 may be parallel to the bottom surface of the substrate 100 and may not be parallel to each other. In some embodiments, the first direction D1 and the second direction D2 may be horizontal directions orthogonal to each other. The peripheral circuit structure PS and the cell array structure CS may be sequentially stacked on the substrate 100 along a vertical direction D3 perpendicular to the bottom surface of the substrate 100.

[0037] The cell array structure CS may include bit lines BL, source lines SL, word lines WL, and memory cells MC in between. Each memory cell MC may be connected to one of the word lines WL, one of the bit lines BL, and one of the source lines SL.

[0038] Reference Figure 2B The semiconductor device may include a cell array structure CS on a substrate 100 and a peripheral circuit structure PS on the cell array structure CS. The cell array structure CS may be disposed between the substrate 100 and the peripheral circuit structure PS. The peripheral circuit structure PS may include core circuitry and peripheral circuitry.

[0039] Reference Figure 2C The semiconductor device can have a chip-to-chip (C2C) structure. The peripheral circuit structure PS can include a first substrate 100a. A lower metal pad LMP can be disposed at the top of the peripheral circuit structure PS. The lower metal pad LMP can be electrically connected to the core circuit and the peripheral circuit. The lower metal pad LMP can be bonded to the upper metal pad UMP of the cell array structure CS.

[0040] The cell array structure CS may include a second substrate 200a, and an upper metal pad UMP may be disposed at the bottom of the cell array structure CS. The upper metal pad UMP may be electrically connected to the bit line BL, the source line SL, and the word line WL. The upper metal pad UMP may be electrically connected to the memory cell MC.

[0041] Figure 3 This is a perspective view illustrating semiconductor patterns, word lines, bit lines, global bit lines, and data storage patterns of a three-dimensional semiconductor device according to some embodiments of the present invention. Figure 4 This is a plan view illustrating some embodiments of a three-dimensional semiconductor device according to the present invention. Figure 5A It is along Figure 4 A cross-sectional view taken from line A-A'. Figure 5B It is along Figure 4 The cross-sectional view taken by line B-B'. Figure 5C It is along Figure 4 A cross-sectional view taken from line C-C'.

[0042] Reference Figure 3 , Figure 4 , Figure 5A , Figure 5B and Figure 5C The three-dimensional semiconductor device 1000 may include a substrate 100. In some embodiments, the substrate 100 may be a semiconductor substrate, an insulating substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor substrate may be, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The substrate 100 may be a plate-like structure extending parallel to a plane defined by a first direction D1 and a second direction D2. In this specification, the first direction D1 and the second direction D2 may be parallel to the bottom surface of the substrate 100 and may not be parallel to each other. The third direction D3 may be a vertical direction D3 perpendicular to the bottom surface of the substrate 100. In some embodiments, the first direction D1, the second direction D2, and the third direction D3 may be orthogonal to each other.

[0043] A cell array structure CS can be disposed on the substrate 100. The cell array structure CS may include a plurality of stacked STs and a data storage pattern DSP between the plurality of stacked STs. Specifically, the cell array structure CS may include a first stacked ST1 and a second stacked ST2 spaced apart from each other in a first direction D1, and a data storage pattern DSP between the first stacked ST1 and the second stacked ST2. In some embodiments, although not shown, a plurality of cell array structures CS may be disposed. The cell array structures CS may be spaced apart from each other in the first direction D1. For the sake of brevity, only one cell array structure CS will be described below, but other cell array structures CS may also have substantially the same features as described below.

[0044] Each of the first stack ST1 and the second stack ST2 may include a semiconductor pattern SP, a word line WL, a bit line BL, a gate insulating layer Gox, a first capping pattern CP1, a second capping pattern CP2, and an insulating pattern ILD. In some embodiments, the first stack ST1 and the second stack ST2 may be configured to have mirror symmetry with respect to the data storage pattern DSP.

[0045] The semiconductor pattern SP can extend on the substrate 100 along a first direction D1. In some embodiments, the semiconductor pattern SP can be a strip pattern extending along the first direction D1. The semiconductor pattern SP can be spaced apart from the substrate 100. That is, the semiconductor pattern SP can float from the substrate 100.

[0046] A semiconductor pattern SP may include a first edge portion EA1 and a second edge portion EA2 spaced apart from each other in a first direction D1, and a channel region CH between the first edge portion EA1 and the second edge portion EA2. The channel region CH of the semiconductor pattern SP may be surrounded or at least partially surrounded by a word line WL. The first edge portion EA1 of the semiconductor pattern SP may be adjacent to a bit line BL. The first edge portion EA1 may contact and be electrically connected to the bit line BL. The second edge portion EA2 may be adjacent to a data storage pattern DSP. The second edge portion EA2 may contact and be electrically connected to the data storage pattern DSP.

[0047] The semiconductor pattern SP may have a first side surface and a second side surface that are opposite to each other in a first direction D1. The first side surface may be the side surface of a first edge portion EA1, and the second side surface may be the side surface of a second edge portion EA2. The first side surface of the semiconductor pattern SP may be in contact with a bit line BL, and the second side surface may be in contact with a data storage pattern DSP.

[0048] The semiconductor pattern SP can be formed from or include at least one of the following: a single-crystal semiconductor material, a polycrystalline semiconductor material, an oxide semiconductor material, and / or a two-dimensional material. In some embodiments, the single-crystal semiconductor material may be single-crystal silicon. In some embodiments, the polycrystalline semiconductor material may be polycrystalline silicon. In some embodiments, the oxide semiconductor material may be indium gallium zinc oxide (IGZO). In some embodiments, the two-dimensional material may be MoS2, WS2, MoSe2, or WSe2.

[0049] In some embodiments, each of the first edge portion EA1 and the second edge portion EA2 of the semiconductor pattern SP may include an impurity region doped with impurities (e.g., n-type or p-type impurities). The impurity region may constitute or include the source / drain region of a transistor.

[0050] In some embodiments, a plurality of semiconductor patterns SP can be provided. The semiconductor patterns SP can be adjacent to each other in the second direction D2 and the third direction D3. The semiconductor patterns SP that are adjacent to each other in the third direction D3 can vertically overlap each other. The semiconductor patterns SP that are adjacent to each other in the third direction D3 can have side surfaces aligned with each other.

[0051] A semiconductor pattern SP can be disposed in a first stack ST1 and a second stack ST2. The semiconductor pattern SP in the first stack ST1 can be adjacent to the semiconductor pattern SP in the second stack ST2 in a first direction D1. The first edge portion EA1 and the second edge portion EA2 of the semiconductor pattern SP in the first stack ST1 can be sequentially disposed along the first direction D1. The first edge portion EA1 and the second edge portion EA2 of the semiconductor pattern SP in the second stack ST2 can be sequentially disposed in a direction opposite to the first direction D1.

[0052] Word lines WL can be configured to surround or at least partially surround the channel region CH of a semiconductor pattern SP, and can extend along the second direction D2. In some embodiments, word lines WL can be configured to completely surround the channel region CH of the semiconductor pattern SP, and can have a certain structure (i.e., a gate-all-around structure). Each word line WL can be configured to surround the channel region CH of each semiconductor pattern SP that is adjacent to each other in the second direction D2. In some embodiments, multiple word lines WL can be provided. Each word line WL can be configured to surround the channel region CH of one of the semiconductor patterns SP that is adjacent to each other in the third direction D3 and can extend along the second direction D2.

[0053] Word lines WL can surround the channel region CH of the semiconductor pattern SP in the first stack ST1. Word lines WL can surround the channel region CH of the semiconductor pattern SP in the second stack ST2.

[0054] The word line WL can be formed from or include at least one of the following: doped polycrystalline silicon, metallic materials (e.g., Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, and / or Co), conductive metal nitride materials (e.g., TiN, TaN, WN, NbN, TiAlN, TiSiN, TaSiN, and / or RuTiN), conductive metal silicide materials, or conductive metal oxide materials (e.g., PtO, RuO2, IrO2, SrRuO3 (SRO), (Ba,Sr)RuO3 (BSRO), CaRuO3 (CRO), and / or LSCo), but the inventive concept is not limited to this example. The word line WL can be configured to have a single-layer or multi-layer structure formed from the above materials. In some embodiments, the word line WL can be formed from at least one of two-dimensional semiconductor materials (e.g., graphene, carbon nanotubes, or combinations thereof), or include at least one of two-dimensional semiconductor materials (e.g., graphene, carbon nanotubes, or combinations thereof).

[0055] Although not shown, word line pads (not shown) may be provided on the side surface of the cell array structure CS and may be electrically connected to word lines WL.

[0056] In the first stack ST1 and / or the second stack ST2, the gate insulating layer Gox may be located between the word line WL and the semiconductor pattern SP. The gate insulating layer Gox may surround the word line WL. The word line WL may be configured to surround the channel region CH of the semiconductor pattern SP on the gate insulating layer Gox. In some embodiments, multiple gate insulating layers Gox may be provided. Each gate insulating layer Gox may surround a corresponding semiconductor pattern SP.

[0057] The gate insulating layer Gox can be formed of or include at least one of the following: silicon oxide, silicon oxynitride, or a high-k dielectric material with a dielectric constant higher than that of silicon oxide. The high-k dielectric material can include metal oxide materials or metal oxynitride materials. For example, the high-k dielectric material of the gate insulating layer Gox can include at least one of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, or Al2O3, but the inventive concept is not limited to this example. A high-k dielectric material can be defined as a material with a dielectric constant higher than that of silicon oxide.

[0058] Bit lines BL can be disposed on a first side surface of the semiconductor pattern SP (i.e., the side surface of the first edge portion EA1). Bit lines BL can extend along a third direction D3 on the first side surface of the semiconductor pattern SP. Therefore, each bit line BL can contact and be electrically connected to the first side surface of each semiconductor pattern SP adjacent to each other in the third direction D3. In some embodiments, multiple bit lines BL can be disposed. Bit lines BL can be adjacent to each other in a second direction D2.

[0059] Bit line BL may include a first bit line BL1 and a second bit line BL2. The first bit line BL1 may be connected to a first global bit line GBL1, as described below. The second bit line BL2 may be connected to a second global bit line GBL2, as described below. The first bit line BL1 and the second bit line BL2 may be alternately set along a second direction D2.

[0060] Bit lines BL can be a single layer made of a single material, or a composite layer comprising two or more materials. In some embodiments, bit lines BL can be formed of or include at least one of the following: metallic materials (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir and / or Co), metal nitride materials (e.g., nitride materials containing Ti, Mo, W, Cu, Al, Ta, Ru, Ir and / or Co), or metal silicide materials (e.g., silicide materials containing Ti, Mo, W, Cu, Al, Ta, Ru, Ir and / or Co).

[0061] The data storage pattern DSP can be located between the first stack ST1 and the second stack ST2. The data storage pattern DSP can also be located between the first semiconductor pattern SP and the second semiconductor pattern SP. The data storage pattern DSP can contact the second side surface of the first semiconductor pattern SP (i.e., the side surface of the second edge portion EA2) and can be electrically connected to the first semiconductor pattern SP. The data storage pattern DSP can also contact the second side surface of the second semiconductor pattern SP and can be electrically connected to the second semiconductor pattern SP.

[0062] The data storage pattern DSP may include a storage electrode SE, a plate electrode PE, and a capacitor dielectric layer CIL between the storage electrode SE and the plate electrode PE. In some embodiments, the three-dimensional semiconductor device may be a dynamic random access memory (DRAM) device, and here, the data storage pattern DSP may function as a capacitor. The storage electrode SE may be spaced apart from the plate electrode PE by the capacitor dielectric layer CIL.

[0063] Each of the storage electrode SE and the plate electrode PE may include a conductive material. In some embodiments, each of the storage electrode SE and the plate electrode PE may be formed of or include at least one of the following: doped silicon (Si), doped silicon germanium (SiGe), metallic materials (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au and / or Ag), metal nitride materials (e.g., nitride materials containing Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au and / or Ag), titanium silicon nitrides (e.g., TiSiN), titanium aluminum nitrides (e.g., TiAlN), tantalum aluminum nitrides (e.g., TaAlN), conductive oxide materials (e.g., PtO, RuO2, IrO2, SrRuO3 (SRO), (Ba,Sr)RuO3 (BSRO), CaRuO3 (CRO) and / or LSCo), or metal silicide materials. Each of the storage electrode SE and the plate electrode PE can be a single layer made of a single material, or it can be a composite layer comprising two or more materials.

[0064] In some embodiments, the capacitor dielectric layer (CIL) may include at least one of a metal oxide material (e.g., HfO2, ZrO2, Al2O3, La2O3, Ta2O3 and / or TiO2) and a perovskite dielectric material (e.g., SrTiO3 (STO), (Ba,Sr)TiO3 (BST), BaTiO3, PZT and / or PLZT).

[0065] In some embodiments, the data storage pattern DSP can be a variable resistance pattern whose resistance can be switched to one of at least two states by an electrical pulse applied thereto. For example, the data storage pattern DSP can be formed of or include at least one of the following: a phase change material, perovskite compound, transition metal oxide, magnetic material, ferromagnetic material, or antiferromagnetic material whose crystal state can change according to the amount of current applied thereto.

[0066] The storage electrode SE can extend from the second side surface of the first semiconductor pattern SPB along the first direction D1. The storage electrode SE can also extend from the second side surface of the second semiconductor pattern SPb in a direction opposite to the first direction D1. Although not shown, silicide patterns (not shown) can be formed between the storage electrode SE and the first semiconductor pattern SPB, and between the storage electrode SE and the second semiconductor pattern SPb. The silicide pattern can be formed from at least one of a metal silicide material (e.g., comprising Ti, Mo, W, Cu, Al, Ta, Ru, Ir, and / or Co), or can include at least one of a metal silicide material (e.g., comprising Ti, Mo, W, Cu, Al, Ta, Ru, Ir, and / or Co). In some embodiments, multiple storage electrodes SE can be provided, and the storage electrodes SE can be adjacent to each other in the third direction D3.

[0067] The plate electrode PE may include a vertical portion extending along a third direction D3, and a horizontal portion extending from the vertical portion along a first direction D1 or the opposite direction of the first direction D1. The horizontal portion of the plate electrode PE may be located between storage electrodes SE that are adjacent to each other in the third direction D3.

[0068] An insulating pattern ILD can be disposed on the substrate 100. The insulating pattern ILD can cover, overlap with, or be on the side surface of the cell array structure CS. The insulating pattern ILD can be located between bit lines BL and word lines WL, between adjacent semiconductor patterns SP in the third direction D3, between the first edge portions EA1 of adjacent semiconductor patterns SP in the second direction D2, and between adjacent word lines WL in the third direction D3. The insulating pattern ILD can include a single layer or a composite layer containing insulating material.

[0069] A capping pattern CP can be disposed in the cell array structure CS. The capping pattern CP can be positioned between the word line WL and the data storage pattern DSP. The capping pattern CP can be positioned between adjacent semiconductor patterns SP on the third direction D3. The capping pattern CP can be positioned between the second edge portions EA2 of adjacent semiconductor patterns SP on the second direction D2.

[0070] A capping pattern CP may include a first capping pattern CP1 surrounding a second edge portion EA2 of a semiconductor pattern SP and a second capping pattern CP2 on the first capping pattern CP1. The first capping pattern CP1 may conformally cover the second edge portion EA2 of the semiconductor pattern SP and the side surface of the word line WL, or may overlap with the second edge portion EA2 of the semiconductor pattern SP and the side surface of the word line WL. Each of the first capping pattern CP1 and the second capping pattern CP2 may include an insulating material. The second capping pattern CP2 may include a single layer or a composite layer.

[0071] A Global Bit Line (GBL) can be set on a Bit Line (BL). A Global Bit Line (GBL) can be a higher-level Bit Line, which together process data from the Bit Line (BL) of the 3D device.

[0072] Global bit lines (GBLs) may extend along a first direction D1. In some embodiments, multiple global bit lines (GBLs) may be provided. Global bit lines (GBLs) may be spaced apart from each other in a second direction D2 and may be alternately arranged along the second direction D2. Global bit lines (GBLs) may include a first global bit line (GBL1) and a second global bit line (GBL2). Due to the height difference between the top surface of the first global bit line (GBL1) and the top surface of the second global bit line (GBL2), which will be described below, two adjacent global bit lines (GBLs) may have top surfaces located at different heights. As used herein, "height" may refer to the distance from a device in a particular direction, such as the distance from the substrate 100 in a third direction D3.

[0073] Specifically, a first global bit line GBL1 can be set on a first bit line BL1, and a second global bit line GBL2 can be set on a second bit line BL2. The first global bit line GBL1 can connect the first bit lines BL1 of a first stack ST1 and a second stack ST2 that are spaced apart from each other in the first direction D1. The second global bit line GBL2 can connect the second bit lines BL2 of the first stack ST1 and the second stack ST2 that are spaced apart from each other in the first direction D1.

[0074] The height of the top surface of the first global bit line GBL1 may be different from the height of the top surface of the second global bit line GBL2. The height of the bottom surface of the second global bit line GBL2 may be equal to or higher than the height of the top surface of the first global bit line GBL1. In some embodiments, the first via VI1 may be located between the first bit line BL1 and the first global bit line GBL1, and the first via VI1 and the second via VI2 may be located between the second bit line BL2 and the second global bit line GBL2. The second via VI2 may be located between the first via VI1 and the second global bit line GBL2.

[0075] The second via VI2 can be located at the same height as the first global bit line GBL1. The height of the top surface of the second via VI2 can be higher than the height of the top surface of the first global bit line GBL1. The second via VI2 can overlap with the second bit line BL2 and / or the second global bit line GBL2 on the third direction D3.

[0076] The first global bit line GBL1 and the second global bit line GBL2 can be set along the direction between the second direction D2 and the third direction D3, or they can be set in a zigzag pattern. That is, the rows and columns of the first global bit line GBL1 and the second global bit line GBL2 can be offset from each other in the cross-sectional view.

[0077] Reference Figure 5C Bit line BL can have a first width W1 in the second direction D2. Bit line BL can be arranged to have a first spacing P1 in the second direction D2 and can be spaced apart from each other by a first distance d1 in the second direction D2. The top surface of the second via VI2 can have a second width W2 in the second direction D2, and the bottom surface of the second via VI2 can have a third width W3 in the second direction D2. The second via VI2 can have a first thickness T1 in the third direction D3. The second via VI2 can be configured to have a second spacing P2 in the second direction D2. The first global bit line GBL1 can have a fourth width W4 in the second direction D2 and can have a second thickness T2 in the third direction D3. The first global bit line GBL1 can be configured to have a third spacing P3 in the second direction D2. The second via VI2 and the first global bit line GBL1 can be spaced apart from each other by a second distance d2 in the second direction D2. The second global bit line GBL2 can have a fifth width W5 in the second direction D2.

[0078] The fourth width W4 of the first global bit line GBL1 can be equal to or greater than the first width W1 of bit line BL. The fifth width W5 of the second global bit line GBL2 can be equal to or greater than the first width W1 of bit line BL.

[0079] The third width W3 of the bottom surface of the second via VI2 can be equal to or less than the fifth width W5 of the second global bit line GBL2. The third width W3 of the bottom surface of the second via VI2 can be equal to or less than the fourth width W4 of the first global bit line GBL1. The second width W2 of the top surface of the second via VI2 can be equal to or less than the fifth width W5 of the second global bit line GBL2. The second width W2 of the top surface of the second via VI2 can be equal to or less than the fourth width W4 of the first global bit line GBL1. In some embodiments, the width of the second via VI2 (e.g., the second width W2) can be equal to or less than the width of the global bit line GBL (e.g., the fourth width W4).

[0080] The first spacing P1 between bit lines BL can be less than the third spacing P3 between first global bit lines GBL1. In some embodiments, the first distance d1 between bit lines BL can be equal to or less than the second distance d2 between the first global bit line GBL1 and the second via VI2.

[0081] The first thickness T1 of the second via VI2 can be equal to or greater than the second thickness T2 of the first global bit line GBL1.

[0082] A protective layer PL may be disposed on the first stack ST1 and / or the second stack ST2. The protective layer PL may cover the top surface of the first stack ST1, the second stack ST2 and the data storage pattern DSP, and may overlap with the top surface of the first stack ST1, the second stack ST2 and the data storage pattern DSP, or may be on the top surface of the first stack ST1, the second stack ST2 and the data storage pattern DSP. The protective layer PL may include a single layer or a composite layer containing insulating material.

[0083] The protective layer PL can cover the side and bottom surfaces of the global bit line GBL and the side surfaces of the first via VI1 and the second via VI2. It can overlap with the side and bottom surfaces of the global bit line GBL and the side surfaces of the first via VI1 and the second via VI2, or it can be on the side and bottom surfaces of the global bit line GBL and the side surfaces of the first via VI1 and the second via VI2.

[0084] In some embodiments of the three-dimensional semiconductor device according to the present invention, adjacent global bit lines (GBLs) can be placed at different heights, and in this case, the distance between the global bit lines (GBLs) can be increased. For example, in Figure 5C In this configuration, the first global bit line GBL1 is located at a different height than the second global bit line GBL2. Accordingly, the capacitance of the bit lines can be reduced and the stacking density increased. As a result, a semiconductor device with improved reliability can be constructed.

[0085] Figure 6 This is a plan view illustrating some embodiments of a three-dimensional semiconductor device according to the present invention. Figure 7 It is along Figure 6 The cross-sectional view taken by line C-C'. For a concise description, refer to... Figures 3 to 5C The described elements can be identified using the same reference numerals, without repeating their redundant descriptions.

[0086] Reference Figure 6 and Figure 7 The three-dimensional semiconductor device 1100 may also include an air gap AG. In some embodiments, multiple air gaps AG may be provided. The air gap AG may be located between the first global bit line GBL1 and the second via VI2.

[0087] According to some embodiments of the present invention, an air gap AG can be disposed between the first global bit line GBL1 and the second via VI2 to enhance the insulation characteristics of the three-dimensional semiconductor device. In this case, the capacitance of the bit line can be reduced and the stacking density can be increased. As a result, a semiconductor device with improved reliability can be provided.

[0088] Figure 8 This is a plan view illustrating some embodiments of a three-dimensional semiconductor device according to the present invention. Figure 9A It is along Figure 8 A cross-sectional view taken from line C-C'. Figure 9B It is along Figure 8 The cross-sectional view taken by line D-D'. For a concise description, refer to... Figures 3 to 5C The described elements can be identified using the same reference numerals, without repeating their redundant descriptions.

[0089] Reference Figure 8 , Figure 9A and Figure 9B The bit line BL of the three-dimensional semiconductor device 2000 may also include a third bit line BL3, and the global bit line GBL of the three-dimensional semiconductor device 2000 may also include a third global bit line GBL3. The third bit line BL3 and the third global bit line GBL3 may be connected to each other, and the third global bit line GBL3 may be set on the third bit line BL3.

[0090] The third global bit line GBL3 can be configured to connect the third bit lines BL3 of the first stack ST1 and the second stack ST2, which are spaced apart from each other in the first direction D1. The height of the top surface of the third global bit line GBL3 can be different from the height of the top surface of the first global bit line GBL1 and the top surface of the second global bit line GBL2. Specifically, the height of the bottom surface of the third global bit line GBL3 can be equal to or higher than the height of the top surface of the second global bit line GBL2. The first via VI1 and the third via VI3 can be located between the third bit line BL3 and the third global bit line GBL3. The third via VI3 can be located between the first via VI1 and the third global bit line GBL3.

[0091] The third via VI3 can be located at the same height as the second global bit line GBL2. The height of the top surface of the third via VI3 can be higher than the height of the top surface of the second global bit line GBL2. The third via VI3 can overlap with the third bit line BL3 and / or the third global bit line GBL3 on the third direction D3.

[0092] In a three-dimensional semiconductor device 2000, two adjacent global bit lines GBLs in the second direction D2 can also be located at different heights. The inventive concept is not limited to the arrangement of bit lines BL or global bit lines GBLs, but rather that global bit lines GBLs located at different heights can be adjacent to each other in the second direction D2. In this case, bit lines BL connected to global bit lines GBLs can also be adjacent to each other in the second direction D2.

[0093] In some embodiments, the first bit line BL1 and the second bit line BL2 may be adjacent to each other in the second direction D2, the first bit line BL1 and the third bit line BL3 may be adjacent to each other in the second direction D2, and the second bit line BL2 and the third bit line BL3 may be adjacent to each other in the second direction D2. In some embodiments, the first global bit line GBL1 and the second global bit line GBL2 may be adjacent to each other in the second direction D2, the first global bit line GBL1 and the third global bit line GBL3 may be adjacent to each other in the second direction D2, and the second global bit line GBL2 and the third global bit line GBL3 may be adjacent to each other in the second direction D2.

[0094] Reference Figure 9B The third via VI3 may have a third thickness T3 in the third direction D3. The top surface of the third via VI3 may have a sixth width W6 in the second direction D2, and the bottom surface of the third via VI3 may have a seventh width W7 in the second direction D2. The second global bit line GBL2 may have a fourth thickness T4 in the third direction D3. The third global bit line GBL3 may have an eighth width W8 in the second direction D2.

[0095] The eighth width W8 of the third global bit line GBL3 can be equal to or greater than the first width W1 of bit line BL.

[0096] The seventh width W7 of the bottom surface of the third via VI3 can be equal to or less than the eighth width W8 of the third global bit line GBL3. The seventh width W7 of the bottom surface of the third via VI3 can be equal to or less than the fifth width W5 of the second global bit line GBL2. The sixth width W6 of the top surface of the third via VI3 can be equal to or less than the eighth width W8 of the third global bit line GBL3. The sixth width W6 of the top surface of the third via VI3 can be equal to or less than the fifth width W5 of the second global bit line GBL2. In some embodiments, the width of the third via VI3 (e.g., the sixth width W6) can be equal to or less than the width of the global bit line GBL (e.g., the fourth width W4).

[0097] The third thickness T3 of the third via VI3 can be greater than the first thickness T1 of the second via VI2. Specifically, the third thickness T3 of the third via VI3 can be equal to or greater than the sum of the first thickness T1 of the second via VI2 and the fourth thickness T4 of the second global bit line GBL2.

[0098] In some embodiments of the three-dimensional semiconductor device according to the present invention, adjacent global bit lines (GBLs) can be located at three or more heights, and in this case, the distance between the global bit lines (GBLs) can be further increased. Accordingly, the capacitance of the bit lines can be reduced and the stacking quantity can be increased. As a result, a semiconductor device with improved reliability can be provided.

[0099] Figure 10 This is a plan view illustrating some embodiments of a three-dimensional semiconductor device according to the present invention. Figure 11 It is along Figure 10 The cross-sectional view taken by line D-D'. For a concise description, refer to... Figures 8 to 9B The described elements can be identified using the same reference numerals, without repeating their redundant descriptions.

[0100] Reference Figure 10 and Figure 11 The three-dimensional semiconductor device 2100 may also include an air gap AG. In some embodiments, multiple air gaps AG may be provided. The air gap AG may be located between the first global bit line GBL1 and the second via VI2, between the first global bit line GBL1 and the third via VI3, and / or between the second global bit line GBL2 and the third via VI3.

[0101] In some embodiments, an air gap AG can be provided to enhance the insulation properties of the three-dimensional semiconductor device. In this case, the capacitance of the bit lines can be reduced and the number of stacks can be increased. As a result, a semiconductor device with improved reliability can be provided.

[0102] Figure 12A , Figure 12B , Figure 12C , Figure 13A , Figure 13B , Figure 13C , Figure 14A , Figure 14B and Figure 14C This is a diagram illustrating a method for manufacturing a three-dimensional semiconductor device according to some embodiments of the present invention. Figure 12A , Figure 13A and Figure 14A It corresponds to Figure 4 A cross-sectional view of line A-A'. Figure 12B , Figure 13B and Figure 14B It corresponds to Figure 4 A cross-sectional view of line B-B'. Figure 12C , Figure 13C and Figure 14C It corresponds to Figure 4 A cross-sectional view of line C-C'.

[0103] Reference Figure 12A , Figure 12B and Figure 12C A first stack ST1 and a second stack ST2 can be formed on the substrate 100. A first via VI1 can be formed on the bit line BL of the first stack ST1 and the bit line BL of the second stack ST2.

[0104] Forming the first via VI1 may include: forming a first insulating layer SPL1 on a first stack ST1 and a second stack ST2; patterning the first insulating layer SPL1 to form an opening that exposes the top surfaces of the first bit line BL1 and the second bit line BL2; and filling the opening with a metallic material.

[0105] Reference Figure 13A , Figure 13B and Figure 13C A first global bit line GBL1 can be formed on the first via VI1. Forming the first global bit line GBL1 may include: forming a first global bit line layer (not shown) on a first insulating layer SPL1; patterning the first global bit line layer (not shown); and forming a second insulating layer SPL2 on the first via VI1 on the second bit line BL2.

[0106] Reference Figure 14A , Figure 14B and Figure 14C A second via VI2 can be formed on the first via VI1 on the second bit line BL2. Forming the second via VI2 may include: forming a third insulating layer SPL3 on the first global bit line GBL1 and the second insulating layer SPL2; patterning the third insulating layer SPL3 to form an opening that exposes the top surface of the first via VI1; and filling the opening with a metallic material.

[0107] Return to reference Figure 5A , Figure 5B and Figure 5C A second global bit line GBL2 can be formed on the second via VI2. Forming the second global bit line GBL2 may include: forming a second global bit line layer (not shown) on the third protective layer material PL and the second via VI2; patterning the second global bit line layer (not shown); and forming a fourth insulating layer (not shown) on the third insulating layer SPL3 to form the protective layer PL.

[0108] According to some embodiments of the present invention, a semiconductor device may include global bit lines having top surfaces located at different heights. In this case, the number of stacked elements can be increased, and the capacitance of the bit lines can be improved. As a result, a semiconductor device with improved reliability can be provided.

[0109] While exemplary embodiments of the inventive concept have been specifically shown and described, those skilled in the art will understand that changes in form and detail may be made therein without departing from the scope of the appended claims.

Claims

1. A three-dimensional semiconductor device, comprising: Substrate; Bit lines, on the substrate, extend along a first direction perpendicular to the bottom surface of the substrate, and include a first bit line and a second bit line, the first bit line and the second bit line being spaced apart from each other and adjacent to each other in a second direction parallel to the bottom surface of the substrate; A semiconductor pattern is provided on the bit line and extends along a third direction perpendicular to the first direction and the second direction; Word lines, on the semiconductor pattern, and extending along the second direction; A first global bit line, on the first bit line, and extending along the third direction; A second global bit line, on the second bit line, and extending along the third direction; as well as The first via is located on the top surface of the second bit line, and between the second bit line and the second global bit line. The distance from the bottom surface of the substrate to the top surface of the first global bit line in the first direction is different from the distance from the bottom surface of the substrate to the top surface of the second global bit line in the first direction.

2. The 3D semiconductor device according to claim 1, wherein, The distance from the bottom surface of the substrate to the bottom surface of the second global bit line in the first direction is equal to or greater than the distance from the bottom surface of the substrate to the top surface of the first global bit line in the first direction.

3. The 3D semiconductor device according to claim 1, wherein, The width of the first global bit line in the second direction is equal to or greater than the width of the first bit line in the second direction.

4. The 3D semiconductor device according to claim 1, wherein, The distance from the bottom surface of the substrate to the bottom surface of the first via in the first direction is the same as the distance from the bottom surface of the substrate to the bottom surface of the first global bit line in the first direction, and Wherein, the thickness of the first via in the first direction is greater than the thickness of the first global bit line in the first direction.

5. The 3D semiconductor device according to claim 1, wherein, The width of the bottom surface of the first via in the second direction is equal to or less than the width of the second global bit line in the second direction.

6. The 3D semiconductor device according to claim 1, wherein, The width of the top surface of the first via in the second direction is equal to or less than the width of the second global bit line in the second direction.

7. The 3D semiconductor device according to claim 1, further comprising: An air gap is located between the first via and the first global bit line.

8. The 3D semiconductor device according to claim 1, wherein, The first via overlaps with the second bit line and the second global bit line in the first direction.

9. The 3D semiconductor device according to claim 1, wherein, The distance between the first global bit line and the first via in the second direction is equal to or less than the distance between the first bit line and the second bit line in the second direction.

10. The 3D semiconductor device according to claim 1, wherein, The bit line further includes: a third bit line extending along the first direction and spaced apart from the first bit line and the second bit line in the second direction. The 3D semiconductor device further includes: a third global bit line on the third bit line, and The distance from the bottom surface of the substrate to the top surface of the third global bit line in the first direction is different from the distance from the bottom surface of the substrate to the top surface of the first global bit line in the first direction, and is also different from the distance from the bottom surface of the substrate to the top surface of the second global bit line in the first direction.

11. The 3D semiconductor device according to claim 10, wherein, The distance from the bottom surface of the substrate to the bottom surface of the third global bit line in the first direction is equal to or greater than the distance from the bottom surface of the substrate to the top surface of the second global bit line in the first direction.

12. The 3D semiconductor device according to claim 10, further comprising: The second via is located between the third bit line and the third global bit line. Wherein, the distance from the bottom surface of the substrate to the bottom surface of the second global bit line in the first direction and the distance from the bottom surface of the substrate to the top surface of the second global bit line in the first direction are between the distance from the bottom surface of the substrate to the bottom surface of the second via in the first direction and the distance from the bottom surface of the substrate to the top surface of the second via in the first direction.

13. The 3D semiconductor device according to claim 12, wherein, The thickness of the second via in the first direction is greater than the thickness of the first via in the first direction.

14. A three-dimensional semiconductor device, comprising: Substrate; Bit lines, on the substrate, extend in a first direction perpendicular to the bottom surface of the substrate, and include a first bit line and a second bit line, the first bit line and the second bit line being spaced apart from each other in a second direction parallel to the bottom surface of the substrate; A semiconductor pattern is provided on the bit line and extends along a third direction perpendicular to the first direction and the second direction; Word lines, on the semiconductor pattern, and extending along the second direction; A first global bit line, on the first bit line, and extending along the third direction; A second global bit line, on the second bit line, and extending along the third direction; as well as A via is located between the second bit line and the second global bit line, and overlaps with both the second bit line and the second global bit line in the first direction. Wherein, the distance from the bottom surface of the substrate to the bottom surface of the via in the first direction is the same as the distance from the bottom surface of the substrate to the bottom surface of the first global bit line in the first direction, and the via is adjacent to the first global bit line in the second direction, and The distance from the bottom surface of the substrate to the top surface of the via in the first direction is greater than the distance from the bottom surface of the substrate to the top surface of the first global bit line in the first direction.

15. The 3D semiconductor device according to claim 14, wherein, The width of the via in the second direction is less than the width of the first global bit line in the second direction.

16. The 3D semiconductor device according to claim 14, further comprising: A protective layer is formed between the first global bit line and the via. as well as Air gap, within the protective layer.

17. A three-dimensional semiconductor device, comprising: Substrate; A first stack and a second stack are disposed on the substrate and are adjacent to each other in a first direction parallel to the bottom surface of the substrate, wherein each of the first stack and the second stack comprises: Bit lines extend along a second direction perpendicular to the bottom surface of the substrate, and are spaced apart from each other in a third direction perpendicular to both the first and second directions. Semiconductor patterns, on the bit lines, and extending along the first direction, and Word lines, on the semiconductor pattern, and extending along the third direction; Data storage pattern, between the first stack and the second stack; and A global bit line extends along the first direction and electrically connects at least one bit line of the first stack to at least one bit line of the second stack, wherein the global bit lines are spaced apart from each other in the third direction. The global bit line includes: First global bitline; and The second global bit line, wherein the distance from the bottom surface of the substrate to the top surface of the second global bit line in the second direction is different from the distance from the bottom surface of the substrate to the top surface of the first global bit line in the first direction. Wherein, at least one first global bit line is adjacent to at least one second global bit line in the third direction, and The distance from the bottom surface of the substrate to the top surface of the data storage pattern in the second direction is greater than the distance from the bottom surface of the substrate to the top surface of the word line in the second direction.

18. The 3D semiconductor device according to claim 17, wherein, The corresponding distance from the bottom surface of the substrate to the bottom surface of the second global bit line in the second direction is greater than the corresponding distance from the bottom surface of the substrate to the top surface of the first global bit line in the second direction.

19. The 3D semiconductor device according to claim 17, wherein, The global bit lines are arranged in a zigzag pattern in the plan view.

20. The 3D semiconductor device according to claim 17, wherein, The bit lines have a first spacing. Wherein, the first global bit line has a second spacing, and Wherein, the first spacing is smaller than the second spacing.

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