Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device and a preparation method thereof, which comprises a substrate, a bit line structure and a gate structure, the substrate comprises a core area and a peripheral area, a plurality of word lines are formed in the core area of the substrate; the bit line structure is located on the core area of the substrate, the bit line structure comprises a first semiconductor layer, a first metal layer and a first amorphous silicon layer which are stacked from bottom to top, and at least part of the first semiconductor layer is located in the substrate between two adjacent word lines; the gate structure is located on the peripheral area of the substrate, and the gate structure comprises a second semiconductor layer. The application can improve the temperature difference between the core area and the peripheral area, so as to improve the performance of the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is widely used in the semiconductor technology field. DRAM typically consists of different regions (core region and peripheral region). During the fabrication of DRAM, an annealing process is required to anneal these different regions. The device structures of these different regions differ, and during annealing, these structural differences can lead to significant temperature variations within each region, thus affecting the performance of the DRAM. Summary of the Invention

[0003] The purpose of this invention is to provide a semiconductor device and its fabrication method, which improves the temperature difference between the core region and the peripheral region to enhance the performance of the semiconductor device.

[0004] To achieve the above objectives, the present invention provides a semiconductor device comprising:

[0005] A substrate, the substrate comprising a core region and a peripheral region, wherein a plurality of word lines are formed in the core region of the substrate;

[0006] A bit line structure is located on the core region of the substrate. The bit line structure includes a first semiconductor layer, a first metal layer and a first amorphous silicon layer stacked from bottom to top. At least a portion of the first semiconductor layer is located in the substrate between two adjacent word lines.

[0007] A gate structure is located on the peripheral region of the substrate, and the gate structure includes a second semiconductor layer.

[0008] Optionally, the top of the second semiconductor layer is higher than the top of the first semiconductor layer.

[0009] Optionally, the gate structure further includes a second metal layer and a second amorphous silicon layer, wherein the second semiconductor layer, the second metal layer and the second amorphous silicon layer are stacked sequentially from bottom to top.

[0010] Optionally, the top of the gate structure is higher than the top of the bit line structure.

[0011] Optionally, the first semiconductor layer is located in a substrate between two adjacent word lines.

[0012] Optionally, it may also include a first oxide layer, which is located between the substrate and the bit line structure;

[0013] A portion of the first semiconductor layer is located in the substrate between two adjacent word lines, and another portion of the first semiconductor layer is located between the first oxide layer and the first metal layer.

[0014] This invention also provides a method for fabricating a semiconductor device, comprising:

[0015] A substrate is provided, the substrate including a core region and a peripheral region, wherein a plurality of word lines are formed in the core region of the substrate;

[0016] A bit line structure is formed on the core region of the substrate, and a gate structure is formed on the peripheral region of the substrate;

[0017] The bit line structure includes a first semiconductor layer, a first metal layer and a first amorphous silicon layer stacked sequentially from bottom to top, with at least a portion of the first semiconductor layer located in the substrate between two adjacent word lines, and the gate structure includes a second semiconductor layer.

[0018] Optionally, the steps of forming the bit line structure and the gate structure include:

[0019] A semiconductor layer is formed on the core region and the peripheral region of the substrate;

[0020] A patterning process is performed on the semiconductor layer on the peripheral region of the substrate. After the patterning process, the semiconductor layer on the core region of the substrate is used as the first semiconductor layer, and the semiconductor layer on the peripheral region of the substrate is used as the second semiconductor layer.

[0021] A first metal layer and a first amorphous silicon layer are sequentially formed on the first semiconductor layer.

[0022] Optionally, after the patterning process, an ion implantation process and an annealing process are performed on the peripheral region of the substrate.

[0023] Optionally, the gate structure further includes a second metal layer and a second amorphous silicon layer, wherein the second semiconductor layer, the second metal layer and the second amorphous silicon layer are stacked sequentially from bottom to top.

[0024] Optionally, the steps of forming the bit line structure and the gate structure include:

[0025] A semiconductor layer, a metal layer, and an amorphous silicon layer are sequentially formed on the core region and the peripheral region of the substrate;

[0026] A patterning process is performed on the semiconductor layer, metal layer, and amorphous silicon layer on the peripheral region of the substrate. After the patterning process, the semiconductor layer, metal layer, and amorphous silicon layer on the core region of the substrate serve as the first semiconductor layer, the first metal layer, and the first amorphous silicon layer, and the semiconductor layer, metal layer, and amorphous silicon layer on the peripheral region of the substrate serve as the second semiconductor layer, the second metal layer, and the second amorphous silicon layer.

[0027] Optionally, before forming the semiconductor layer, an oxide layer is formed to cover the core region and peripheral region of the substrate; when forming the semiconductor layer, the semiconductor layer covers the oxide layer and the substrate located between two adjacent word lines; after forming the semiconductor layer and before forming the metal layer, the semiconductor layer on the oxide layer of the core region is etched away, such that the semiconductor layer of the core region is located in the substrate between two adjacent word lines, or, a portion of the semiconductor layer on the oxide layer of the core region is etched away, such that a portion of the semiconductor layer of the core region is located in the substrate between two adjacent word lines, and another portion of the semiconductor layer of the core region is located on the oxide layer.

[0028] Optionally, after forming the bit line structure and the gate structure, the method further includes forming a contact hole structure electrically connected to the bit line structure and the gate structure, and performing an annealing process when forming the contact hole structure.

[0029] The semiconductor device and its fabrication method provided by this invention include: a substrate, a bit line structure, and a gate structure. The substrate includes a core region and a peripheral region. A plurality of word lines are formed in the core region of the substrate. The bit line structure is located on the core region of the substrate and includes a first semiconductor layer, a first metal layer, and a first amorphous silicon layer stacked sequentially from bottom to top. At least a portion of the first semiconductor layer is located in the substrate between two adjacent word lines. The gate structure is located on the peripheral region of the substrate and includes a second semiconductor layer. In this invention, a first amorphous silicon layer is disposed on the first metal layer in the core region. The optical properties of the first amorphous silicon layer are between those of the substrate and the first metal layer. In subsequent fabrication processes, the first amorphous silicon layer reduces heat reflection in the core region, thereby improving the temperature difference between the core region and the peripheral region and enhancing the performance of the semiconductor device. Attached Figure Description

[0030] Figure 1 This is a cross-sectional schematic diagram of a semiconductor device provided in Embodiment 1 of the present invention.

[0031] Figures 2-6 This is a cross-sectional schematic diagram of a corresponding step in the method for fabricating a semiconductor device provided in Embodiment 1 of the present invention.

[0032] Figure 7 This is a cross-sectional schematic diagram of the semiconductor device provided in Embodiment 2 of the present invention.

[0033] Figures 8-11 This is a cross-sectional schematic diagram of a corresponding step in the method for fabricating a semiconductor device according to Embodiment 2 of the present invention.

[0034] The attached figures are labeled as follows:

[0035] 10-Substrate; 11-Core region; 12-Peripheral region; 14-Trench isolation structure; 20-Word line; 21-Word line dielectric layer; 22-Word line conductive layer; 23-Word line capping layer; 30-Oxide layer; 31-First oxide layer; 32-Second oxide layer; 40-Semiconductor layer; 41-First semiconductor layer; 42-Second semiconductor layer; 50-Metal barrier layer; 51-First metal barrier layer; 52-Second metal barrier layer; 60-Metal layer; 61-First metal layer; 62-Second metal layer; 70-Amorphous silicon layer; 71-First amorphous silicon layer; 72-Second amorphous silicon layer; 81-First capping layer; 82-Second capping layer; 91-Sidewall material layer; 92-Spacer material layer. Detailed Implementation

[0036] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0037] Example 1

[0038] Figure 1 This is a cross-sectional schematic diagram of the semiconductor device provided in this embodiment. Please refer to... Figure 1This embodiment provides a semiconductor device, which may be a dynamic random access memory (DRAM), including: a substrate 10, a bit line structure, and a gate structure. The substrate 10 may be a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium-silicon substrate, or a fully depleted silicon-on-insulator substrate, but is not limited to these. The substrate 10 includes a core region 11 and a peripheral region 12. A plurality of word lines 20 are formed in the core region 11 of the substrate 10. The word lines 20 may have the same or different depths. Each word line 20 includes a word line dielectric layer 21, a word line conductive layer 22, and a word line capping layer 23. A plurality of word line grooves (not shown in the figure) are formed in the core region 11 of the substrate 10. The word line dielectric layer 21 covers the sidewalls and bottom of the word line grooves. The word line conductive layer 22 fills a portion of the depth of the word line grooves. The word line capping layer 23 is located on the word line conductive layer 22 and fills the remaining depth of the word line grooves. The word line dielectric layer 21 may be made of silicon oxide, the word line conductive layer 22 may be made of at least one of tungsten, titanium nitride, and polycrystalline silicon, and the word line capping layer 23 may be made of silicon nitride, but is not limited to the above materials. Furthermore, a plurality of trench isolation structures 14 are formed in the peripheral region 12 of the substrate 10.

[0039] The bit line structure is located on the core region 11 of the substrate 10. The bit line structure includes a first semiconductor layer 41, a first metal layer 61, and a first amorphous silicon layer 71 stacked sequentially from bottom to top. At least a portion of the first semiconductor layer 41 is located in the substrate 10 between two adjacent word lines 20. In this embodiment, the material of the first semiconductor layer 41 may be amorphous silicon, and the material of the first metal layer 61 may be tungsten, but is not limited to the above materials.

[0040] Furthermore, it also includes a first oxide layer 31, which is located between the substrate 10 and the bit line structure. In this embodiment, the first semiconductor layer 41 is located in the substrate 10 between two adjacent word lines 20, or, a portion of the first semiconductor layer 41 is located in the substrate 10 between two adjacent word lines 20, and another portion of the first semiconductor layer 41 is located between the first oxide layer 31 and the first metal layer 51 (e.g., Figure 1 (as shown in the diagram); the edge of the first semiconductor layer 41 in the substrate 10 located between two adjacent word lines 20 may extend to the edge of the word line 20.

[0041] Furthermore, the bit line structure also includes a first metal barrier layer 51 and a first capping layer 81. The first metal barrier layer 51 is located between the first semiconductor layer 41 and the first metal layer 61, and the first capping layer 81 is located on the first amorphous silicon layer 71. The material of the first metal barrier layer 51 may be titanium or titanium nitride, and the material of the first capping layer 81 may be silicon nitride, but is not limited to the above materials.

[0042] The gate structure is located on the peripheral region 12 of the substrate 10 (located on the substrate 10 between two adjacent trench isolation structures 14). The gate structure includes a second semiconductor layer 42, and the top of the second semiconductor layer 42 is higher than the top of the first semiconductor layer 41. The material of the second semiconductor layer 42 may be amorphous silicon, but is not limited thereto. In this embodiment, the gate structure also includes a second capping layer 82, which is located on the second semiconductor layer 42. The material of the second capping layer 82 may be silicon nitride, but is not limited thereto.

[0043] Furthermore, it also includes a second oxide layer 32, a sidewall material layer 91, and a spacer material layer 92. The second oxide layer 32 is located between the substrate 10 and the gate structure (second semiconductor layer 42). The sidewall material layer 91 covers the sidewalls of the gate structure and extends to cover the surface of the peripheral region 12. The spacer material layer 92 is located on the sidewall material layer 91 and fills the space between two adjacent gate structures. The sidewall material layer 91 can be made of at least one of silicon oxide, silicon nitride, and silicon oxynitride. The spacer material layer 92 can be made of silicon oxide or silicon nitride, and is not limited to the above materials. A doped region (not shown in the figure) is formed in the peripheral region 12, and the doped region can serve as a source region or a drain region.

[0044] Furthermore, it also includes an interlayer dielectric layer and a contact hole structure (not shown in the figure). The interlayer dielectric layer covers the gate structure and the bit line structure. The contact hole structure is located in the interlayer dielectric layer and penetrates part of the gate structure and part of the bit line structure, respectively, and is electrically connected to the first amorphous silicon layer 71 and the second semiconductor layer 42. When forming the contact hole structure, several contact holes are first formed, and the bottom of the several contact holes exposes the first amorphous silicon layer 71 and the second semiconductor layer 42, respectively. Then, in order to reduce contact resistance, a metal material layer is formed to cover the bottom and sidewalls of the contact holes. Then, an annealing process is performed to form a metal silicide layer at the bottom of the contact holes. Subsequently, a barrier layer is formed to cover the bottom and sidewalls of the contact holes, and a metal material is formed to fill the contact holes to complete the fabrication of the contact hole structure.

[0045] Because the core region 11 and the peripheral region 12 have different device structures, such as different bit line structures and gate structures, and the bit line structure includes a first metal layer 61 (the first metal layer 61 has a larger area), an annealing process is required when forming the contact hole structure. The first metal layer 61 will reflect some heat away, while the substrate 10 will absorb some heat. The first metal layer 61 is located on the core region 11, causing the heat of the core region 11 to be reflected away, resulting in a temperature difference between the core region 11 and the peripheral region 12. Therefore, in this embodiment, a first amorphous silicon layer 71 is provided on the first metal layer 61 of the core region 11. The optical properties of the first amorphous silicon layer 71 are between those of the substrate 10 and the first metal layer 61. In subsequent fabrication processes (the annealing process of the contact hole structure), the first amorphous silicon layer 71 reduces the heat reflection of the core region 11 and increases the heat absorption of the core region 11, thereby improving the temperature difference between the core region 11 and the peripheral region 12 and improving the performance of the semiconductor device.

[0046] Figures 2-6 This is a cross-sectional schematic diagram of a corresponding step in the fabrication method of the semiconductor device provided in this embodiment. This embodiment also provides a method for fabricating a semiconductor device, used to fabricate the aforementioned semiconductor device, comprising:

[0047] Step S1: Provide a substrate, which includes a core region and a peripheral region, and a number of word lines are formed in the core region of the substrate;

[0048] Step S2: Form a bit line structure on the core region of the substrate and form a gate structure on the peripheral region of the substrate;

[0049] The bit line structure includes a first semiconductor layer, a first metal layer and a first amorphous silicon layer stacked sequentially from bottom to top, with at least a portion of the first semiconductor layer located in the substrate between two adjacent word lines, and the gate structure includes a second semiconductor layer.

[0050] The following is combined Figures 2-6 The method for fabricating the semiconductor device provided in this embodiment will be described in detail.

[0051] Please refer to Figure 2 Step S1: A substrate 10 is provided, comprising a core region 11 and a peripheral region 12. A plurality of word lines 20 are formed in the core region 11 of the substrate 10. The steps for forming the word lines 20 include: etching the core region 11 of the substrate 10 to form a plurality of word line grooves (not shown in the figure); then forming a word line dielectric layer 21 covering the sidewalls and bottom of the word line grooves; subsequently forming a word line conductive layer 22 filling a portion of the depth of the word line grooves; and finally forming a word line capping layer 23 located on the word line conductive layer 22 and filling the remaining depth of the word line grooves. Furthermore, a plurality of trench isolation structures 14 are formed in the peripheral region 12 of the substrate 10; the materials of the above structures are as described above.

[0052] Step S2: Form a bit line structure on the core region of the substrate and form a gate structure on the peripheral region of the substrate.

[0053] The steps for forming the bit line structure and gate structure include: Please refer to Figure 3 First, an oxide layer is formed on the core region 11 and the peripheral region 12 of the substrate 10. Then, a semiconductor layer is formed on the core region 11 and the peripheral region 12 of the substrate 10 (located on the oxide layer). A portion of the semiconductor layer is located within the substrate 10 between two adjacent word lines 20. After forming the semiconductor layer, because a portion of the semiconductor layer is located within the substrate 10 between two adjacent word lines 20, the top of the semiconductor layer on the core region 11 will be uneven. Therefore, the semiconductor layer on the core region 11 is ground to bring the top of the semiconductor layer on the core region 11 to the same horizontal plane. Thus, the top of the semiconductor layer on the peripheral region 12 will be higher than the top of the semiconductor layer on the core region 11. Before forming the semiconductor layer, the oxide layer on the core region 11 and the portion of the substrate 10 between two adjacent word lines 20 are etched to form a groove. Subsequently, the semiconductor layer is formed so that a portion of the semiconductor layer is located within the substrate 10 between two adjacent word lines 20 (filling the groove). Then, a second capping layer 82 is formed on the semiconductor layer on the core region 11 and the peripheral region 12. The materials of the above-described process layers are as described above.

[0054] Further, a patterning process is performed on the semiconductor layer on the peripheral region 12 of the substrate 10. After the patterning process, the semiconductor layer on the core region 11 of the substrate 10 serves as the first semiconductor layer 41, and the semiconductor layer on the peripheral region 12 of the substrate 10 serves as the second semiconductor layer 42, with the top of the second semiconductor layer 42 higher than the top of the first semiconductor layer 41. During the patterning process, the oxide layer is simultaneously patterned, such that the oxide layer on the core region 11 of the substrate 10 serves as the first oxide layer 31, and the oxide layer on the peripheral region 12 of the substrate 10 serves as the second oxide layer 32; and the second capping layer 82 is simultaneously patterned. In this embodiment, at least a portion of the first semiconductor layer 41 is located in the substrate 10 between two adjacent word lines 20. Specifically, the first semiconductor layer 41 is located in the substrate 10 between two adjacent word lines 20, or a portion of the first semiconductor layer 41 is located in the substrate 10 between two adjacent word lines 20, and another portion of the first semiconductor layer 41 is located on the first oxide layer 31 (e.g., Figure 3 (as shown in the diagram); the edge of the first semiconductor layer 41 located in the substrate 10 between two adjacent word lines 20 may extend to the edge of the word line 20. In this embodiment, the gate structure includes a second semiconductor layer 42 and a second capping layer 82 above the second semiconductor layer 42.

[0055] Further, please refer to Figure 4After the patterning process, the process includes ion implantation and annealing of the peripheral region 12 of the substrate 10. Ion implantation forms a doped region within the peripheral region 12, including source and drain regions (arrows indicate the ion implantation direction; doped regions are not shown in the figure). Annealing follows ion implantation. During annealing, no metal layers are formed on either the second semiconductor layer 42 or the first semiconductor layer 41. This results in less heat reflection between the core region 11 and the peripheral region 12, and a smaller temperature difference between them, which is beneficial for improving device performance.

[0056] Further, please refer to Figure 5 After performing ion implantation and annealing processes on the peripheral region 12 of the substrate 10, the process further includes forming a sidewall material layer 91 and a spacer material layer 92. The sidewall material layer 91 covers the sidewalls of the gate structure and extends to cover the surface of the peripheral region 12. The spacer material layer 92 is located on the sidewall material layer 91 and fills the space between two adjacent gate structures. The materials of the above process layers are as described above.

[0057] Further, please refer to Figure 6 After forming the sidewall material layer 91 and the spacer material layer 92, the process also includes removing the second cover layer 82 on the core area 11.

[0058] Please continue to refer to this. Figure 1 A first metal layer 61 and a first amorphous silicon layer 71 are sequentially formed on the first semiconductor layer 41, such that the bit line structure includes the first semiconductor layer 41, the first metal layer 61 and the first amorphous silicon layer 71 stacked from bottom to top; and a first metal barrier layer 51 is formed between the first metal layer 61 and the first semiconductor layer 41, and a first capping layer 81 is formed on the first amorphous silicon layer 71; the materials of the above process layers are as described above.

[0059] Furthermore, after forming the bit line structure and the gate structure, the process also includes forming a contact hole structure (not shown in the figure) to electrically connect with the bit line structure and the gate structure. An annealing process is performed when forming the contact hole structure. Specifically, an interlayer dielectric layer is formed to cover the bit line structure and the gate structure. The interlayer dielectric layer, the first capping layer 81, and the second capping layer 82 are etched to form a plurality of contact holes. The bottom of the plurality of contact holes exposes the first amorphous silicon layer 71 and the second semiconductor layer 42, respectively. Then, in order to reduce contact resistance, a metal material layer is formed to cover the bottom and sidewalls of the contact holes. An annealing process is then performed to form a metal silicide layer at the bottom of the contact holes. The metal material layer that has not reacted with the first amorphous silicon layer 71 and the second semiconductor layer 42 is then removed. Subsequently, a barrier layer is formed to cover the bottom and sidewalls of the contact holes, and a metal material is formed to fill the contact holes to complete the fabrication of the contact hole structure. This allows the contact hole structure to penetrate part of the gate structure and part of the bit line structure and be electrically connected to the first amorphous silicon layer 71 and the second semiconductor layer 42, respectively.

[0060] In this embodiment, a first amorphous silicon layer 71 is disposed on the first metal layer 61 of the core region 11. The optical properties of the first amorphous silicon layer 71 are between those of the substrate 10 and the first metal layer 61. In subsequent fabrication processes (annealing process of contact hole structure), the first amorphous silicon layer 71 reduces heat reflection in the core region 11 and increases the heat absorbed by the core region 11, thereby improving the temperature difference between the core region 11 and the peripheral region 12 and improving the performance of the semiconductor device.

[0061] Example 2

[0062] Figure 7 This is a cross-sectional schematic diagram of the semiconductor device provided in this embodiment. Please refer to... Figure 7 This embodiment provides a semiconductor device, which can be a dynamic random access memory (DRAM). The difference between the semiconductor device provided in this embodiment and the semiconductor device provided in Embodiment 1 is that the gate structure further includes a second metal layer 62 and a second amorphous silicon layer 72. The second semiconductor layer 42, the second metal layer 62, and the second amorphous silicon layer 72 are stacked sequentially from bottom to top. A second metal barrier layer 52 is also formed between the second semiconductor layer 42 and the second metal layer 62, and the top of the gate structure is higher than the top of the bit line structure. The material of the second metal layer 62 can be tungsten, and the material of the second metal barrier layer 52 can be titanium or titanium nitride, but is not limited to these materials. A contact hole structure penetrates a portion of the gate structure and a portion of the bit line structure and is electrically connected to the first amorphous silicon layer 71 and the second amorphous silicon layer 72, respectively.

[0063] The semiconductor device provided in this embodiment is the same as that in Embodiment 1 in all other aspects, although... Figure 7 The diagram illustrates that the first semiconductor layer 41 is located in the substrate 10 between two adjacent word lines 20, but in reality it could also be... Figure 1 The arrangement of the first semiconductor layer 41 in the embodiment (described in Example 1).

[0064] In this embodiment, since a second metal layer 62 is disposed on the second semiconductor layer 42, the second metal layer 62 will reflect some heat away. By disposing a second amorphous silicon layer 72 on the second metal layer 62 in the peripheral region 12 and a first amorphous silicon layer 71 on the first metal layer 61 in the core region 11, the optical properties of the second amorphous silicon layer 72 and the first amorphous silicon layer 71 are between those of the substrate 10 and the first metal layer 61. In subsequent fabrication processes (annealing process of contact hole structure), the second amorphous silicon layer 72 and the first amorphous silicon layer 71 reduce heat reflection in the peripheral region 12 and the core region 11, respectively (especially since the area of ​​the first metal layer 61 in the core region 11 is larger than that of the second metal layer 62 in the peripheral region 12, the first amorphous silicon layer 71 reduces heat reflection in the core region 11 more). The heat absorbed by the peripheral region 12 and the core region 11 increases, which can improve the temperature difference between the core region 11 and the peripheral region 12, thereby improving the performance of the semiconductor device.

[0065] Figures 8-11 This is a cross-sectional schematic diagram of the corresponding steps in the semiconductor device fabrication method provided in this embodiment. The semiconductor device fabrication method provided in this embodiment differs from the semiconductor device fabrication method provided in Embodiment 1 in that some steps (i.e., step S2) for forming the bit line structure and the gate structure are different.

[0066] The following is combined Figures 8-11 The method for fabricating the semiconductor device provided in this embodiment will be described in detail. For step S1, please refer to the description in Embodiment 1. Step S2 will be described in detail below.

[0067] Step 2: Form a bit line structure on the core region of the substrate and form a gate structure on the peripheral region of the substrate. The gate structure also includes a second metal layer and a second amorphous silicon layer. The second semiconductor layer, the second metal layer and the second amorphous silicon layer are stacked sequentially from bottom to top, and the top of the gate structure is higher than the top of the bit line structure.

[0068] The steps for forming the bit line structure and gate structure include: Please refer to Figure 8First, an oxide layer 30 is formed on the core region 11 and the peripheral region 12 of the substrate 10. Then, a semiconductor layer 40 is formed on the core region 11 and the peripheral region 12 of the substrate 10 (located on the oxide layer 30). A portion of the semiconductor layer 40 is located within the substrate 10 between two adjacent word lines 20. After forming the semiconductor layer 40, because a portion of the semiconductor layer 40 is located within the substrate 10 between two adjacent word lines 20, the top of the semiconductor layer 40 on the core region 11 will be uneven. Therefore, the semiconductor layer 40 on the core region 11 is ground to bring its top to the same horizontal plane. The top of the semiconductor layer 40 on the peripheral region 12 can also be ground simultaneously to bring its top to the same horizontal plane as the top of the semiconductor layer 40 on the core region 11. Before forming the semiconductor layer 40, the oxide layer 30 on the core region 11 and a portion of the substrate 10 between two adjacent word lines 20 are etched to form a groove. Subsequently, the semiconductor layer 40 is formed so that a portion of the semiconductor layer 40 is located within the substrate 10 between two adjacent word lines 20 (filling the groove). Furthermore, a second cover layer 82 is formed on the semiconductor layer located on the core region 11 and the peripheral region 12; the material of the above-mentioned process layer is as described above.

[0069] Further, please refer to Figure 9 After forming the semiconductor layer 40, the semiconductor layer 40 on the oxide layer 30 of the core region 11 is etched away, so that the semiconductor layer 40 of the core region 11 is located in the substrate 10 between two adjacent word lines 20 (e.g., Figure 9 (as shown), or, etching away a portion of the semiconductor layer 40 on the oxide layer 30 of the core region 11, such that a portion of the semiconductor layer 40 of the core region 11 is located in the substrate 10 between two adjacent word lines 20, and another portion of the semiconductor layer 40 of the core region 11 is located on the oxide layer 30.

[0070] Please refer to Figure 10 A metal layer 60 and an amorphous silicon layer 70 are sequentially formed on the core region 11 and the peripheral region 12 of the substrate 10; and a metal barrier layer 50 is formed between the semiconductor layer 40 and the metal layer 60.

[0071] Please refer to Figure 11A patterning process is performed on the semiconductor layer, metal layer, and amorphous silicon layer on the peripheral region 12 of the substrate 10. After the patterning process, the semiconductor layer, metal layer, and amorphous silicon layer on the core region 11 of the substrate 10 serve as the first semiconductor layer 41, the first metal layer 61, and the first amorphous silicon layer 71, and the semiconductor layer, metal layer, and amorphous silicon layer on the peripheral region 12 of the substrate 10 serve as the second semiconductor layer 42, the second metal layer 62, and the second amorphous silicon layer 72. During the patterning process, the oxide layer and the metal barrier layer are patterned simultaneously, such that the oxide layer on the core region 11 of the substrate 10 serves as the first oxide layer 31, and the oxide layer on the peripheral region 12 of the substrate 10 serves as the second oxide layer 32; the metal barrier layer on the core region 11 of the substrate 10 serves as the first metal barrier layer 51, and the metal barrier layer on the peripheral region 12 of the substrate 10 serves as the second metal barrier layer 52.

[0072] For further information, please continue to refer to [link / reference]. Figure 7 A first capping layer 81 is formed on the first amorphous silicon layer 71, and a second capping layer 82 is formed on the second amorphous silicon layer 72, wherein the first capping layer 81 and the second capping layer 82 are formed simultaneously.

[0073] Furthermore, after forming the bit line structure and the gate structure, the process also includes forming a contact hole structure (not shown in the figure) to electrically connect with the bit line structure and the gate structure. An annealing process is performed when forming the contact hole structure. Specifically, an interlayer dielectric layer is formed to cover the bit line structure and the gate structure. The interlayer dielectric layer, the first capping layer 81, and the second capping layer 82 are etched to form a plurality of contact holes. The bottom of the plurality of contact holes exposes the first amorphous silicon layer 71 and the second amorphous silicon layer 72, respectively. Then, in order to reduce contact resistance, a metal material layer is formed to cover the bottom and sidewalls of the contact holes. An annealing process is then performed to form a metal silicide layer at the bottom of the contact holes. The metal material layer that has not reacted with the first amorphous silicon layer 71 and the second amorphous silicon layer 72 is then removed. Subsequently, a barrier layer is formed to cover the bottom and sidewalls of the contact holes, and a metal material is formed to fill the contact holes to complete the fabrication of the contact hole structure. This allows the contact hole structure to penetrate part of the gate structure and part of the bit line structure and be electrically connected to the first amorphous silicon layer 71 and the second amorphous silicon layer 72, respectively.

[0074] In summary, the semiconductor device and its fabrication method provided by this invention include: a substrate, a bit line structure, and a gate structure. The substrate includes a core region and a peripheral region, and a plurality of word lines are formed in the core region of the substrate. The bit line structure is located on the core region of the substrate and includes a first semiconductor layer, a first metal layer, and a first amorphous silicon layer stacked sequentially from bottom to top, with at least a portion of the first semiconductor layer located in the substrate between two adjacent word lines. The gate structure is located on the peripheral region of the substrate and includes a second semiconductor layer. In this invention, a first amorphous silicon layer is disposed on the first metal layer in the core region. The optical properties of the first amorphous silicon layer are between those of the substrate and the first metal layer. In subsequent fabrication processes, the first amorphous silicon layer reduces heat reflection in the core region, thereby improving the temperature difference between the core region and the peripheral region and enhancing the performance of the semiconductor device.

[0075] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that, include: A substrate, the substrate comprising a core region and a peripheral region, wherein a plurality of word lines are formed in the core region of the substrate; A bit line structure is located on the core region of the substrate. The bit line structure includes a first semiconductor layer, a first metal layer and a first amorphous silicon layer stacked from bottom to top. At least a portion of the first semiconductor layer is located in the substrate between two adjacent word lines. A gate structure is located on the peripheral region of the substrate, and the gate structure includes a second semiconductor layer; The contact hole structure is electrically connected to the first amorphous silicon layer and the second semiconductor layer, respectively. The formation of the contact hole structure includes performing an annealing process. The optical properties of the first amorphous silicon layer are between those of the substrate and the first metal layer. In the annealing process, the first amorphous silicon layer reduces heat reflection in the core region.

2. The semiconductor device as claimed in claim 1, characterized in that, The top of the second semiconductor layer is higher than the top of the first semiconductor layer.

3. The semiconductor device as described in claim 1, characterized in that, The gate structure further includes a second metal layer and a second amorphous silicon layer, wherein the second semiconductor layer, the second metal layer and the second amorphous silicon layer are stacked sequentially from bottom to top.

4. The semiconductor device as described in claim 3, characterized in that, The top of the gate structure is higher than the top of the bit line structure.

5. The semiconductor device as claimed in claim 1, characterized in that, The first semiconductor layer is located in the substrate between two adjacent word lines.

6. The semiconductor device as claimed in claim 1, characterized in that, It also includes a first oxide layer, which is located between the substrate and the bit line structure; A portion of the first semiconductor layer is located in the substrate between two adjacent word lines, and another portion of the first semiconductor layer is located between the first oxide layer and the first metal layer.

7. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided, the substrate including a core region and a peripheral region, wherein a plurality of word lines are formed in the core region of the substrate; A bit line structure is formed on the core region of the substrate, and a gate structure is formed on the peripheral region of the substrate; The bit line structure includes a first semiconductor layer, a first metal layer and a first amorphous silicon layer stacked sequentially from bottom to top, with at least a portion of the first semiconductor layer located in the substrate between two adjacent word lines, and the gate structure includes a second semiconductor layer. A contact hole structure is formed, wherein the contact hole structure is electrically connected to the first amorphous silicon layer and the second semiconductor layer respectively; the step of forming the contact hole structure includes: performing an annealing process, wherein the optical properties of the first amorphous silicon layer are between those of the substrate and the first metal layer, and in the annealing process, the first amorphous silicon layer reduces heat reflection in the core region.

8. The method for fabricating a semiconductor device as described in claim 7, characterized in that, The steps of forming the bit line structure and the gate structure include: A semiconductor layer is formed on the core region and the peripheral region of the substrate; A patterning process is performed on the semiconductor layer on the peripheral region of the substrate. After the patterning process, the semiconductor layer on the core region of the substrate is used as the first semiconductor layer, and the semiconductor layer on the peripheral region of the substrate is used as the second semiconductor layer. A first metal layer and a first amorphous silicon layer are sequentially formed on the first semiconductor layer.

9. The method for fabricating a semiconductor device as described in claim 8, characterized in that, Following the patterning process, the process further includes performing ion implantation and annealing processes on the peripheral region of the substrate.

10. The method for fabricating a semiconductor device as described in claim 7, characterized in that, The gate structure further includes a second metal layer and a second amorphous silicon layer, wherein the second semiconductor layer, the second metal layer and the second amorphous silicon layer are stacked sequentially from bottom to top.

11. The method for fabricating a semiconductor device as described in claim 10, characterized in that, The steps of forming the bit line structure and the gate structure include: A semiconductor layer, a metal layer, and an amorphous silicon layer are sequentially formed on the core region and the peripheral region of the substrate; A patterning process is performed on the semiconductor layer, metal layer, and amorphous silicon layer on the peripheral region of the substrate. After the patterning process, the semiconductor layer, metal layer, and amorphous silicon layer on the core region of the substrate serve as the first semiconductor layer, the first metal layer, and the first amorphous silicon layer, and the semiconductor layer, metal layer, and amorphous silicon layer on the peripheral region of the substrate serve as the second semiconductor layer, the second metal layer, and the second amorphous silicon layer.

12. The method for fabricating a semiconductor device as described in claim 11, characterized in that, Before forming the semiconductor layer, an oxide layer is formed to cover the core region and the peripheral region of the substrate; during the formation of the semiconductor layer, the semiconductor layer covers the oxide layer and the substrate located between two adjacent word lines; After the semiconductor layer is formed and before the metal layer is formed, the semiconductor layer on the oxide layer of the core region is etched away, such that the semiconductor layer of the core region is located in the substrate between two adjacent word lines; or, a portion of the semiconductor layer on the oxide layer of the core region is etched away, such that a portion of the semiconductor layer of the core region is located in the substrate between two adjacent word lines, and another portion of the semiconductor layer of the core region is located on the oxide layer.

13. The method for fabricating a semiconductor device as described in claim 7, characterized in that, In the annealing process, the first amorphous silicon layer reduces heat reflection in the core region compared to the first metal layer.

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