Integrated circuit device

Abstract

An integrated circuit device includes a substrate including a cell array region, a core region, and an interface region between the cell array region and the core region; an interface device isolation film arranged in the interface region and defining the cell array region; a plurality of dummy active regions spaced apart from each other in the interface region, each dummy active region being surrounded by the interface device isolation film; and a plurality of bit lines extending from the cell array region to the interface region, wherein each bit line of the plurality of bit lines includes a bit line extension in the interface region, and the bit line extension extends onto a selected dummy active region of the plurality of dummy active regions.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2025-0010674, filed with the Korean Intellectual Property Office on January 23, 2025, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to an integrated circuit (IC) device, and more specifically, to an IC device comprising multiple bit lines. Background Technology

[0004] In recent years, with the development of electronic technology, the size of integrated circuit (IC) devices has been rapidly and gradually shrinking, and the feature size of ICs has also decreased. Accordingly, it is necessary to develop a structure that can ensure the reliability of the cell devices arranged in the cell array area. Summary of the Invention

[0005] The present invention provides an integrated circuit (IC) device having a structure that prevents short circuits between adjacent bit lines arranged in the cell array region and the adjacent interface region, and improves reliability by increasing the contact area between each bit line and its corresponding contact plug.

[0006] According to one aspect of the present invention, an IC device is provided, comprising: a substrate including a cell array region, a core region, and an interface region between the cell array region and the core region; an interface device isolation film disposed in the interface region and defining the cell array region; a plurality of dummy active regions spaced apart from each other in the interface region, each dummy active region being surrounded by the interface device isolation film; and a plurality of bit lines extending from the cell array region to the interface region, wherein each of the plurality of bit lines includes a bit line extension located in the interface region, and the bit line extension extends to a selected dummy active region among the plurality of dummy active regions.

[0007] According to another aspect of the present invention, an IC device is provided, comprising: a substrate including a cell array region, a core region surrounding the cell array region, and an interface region between the cell array region and the core region; an interface device isolation film defining the cell array region in the interface region; and a plurality of bit lines on the substrate, spaced apart from each other in a first lateral direction and extending in a second lateral direction perpendicular to the first lateral direction, each bit line including a bit line extension located in the interface region; and a plurality of dummy active regions, in a first local region and a second local region, the plurality of dummy active regions being defined in the substrate by the interface device isolation film, wherein the first local region and the second local region are selected in the interface region and spaced apart from each other in the second lateral direction, the cell array region being between the first local region and the second local region, wherein the plurality of dummy active regions are spaced apart from each other in the first lateral direction in each of the first local region and the second local region and arranged as a line in the first lateral direction, and a portion of the end of the bit line extension of each of the plurality of bit lines away from the cell array region is disposed in the interface region at a position overlapping with a selected dummy active region of the plurality of dummy active regions in the vertical direction.

[0008] According to another aspect of the present invention, an IC device is provided, comprising: a substrate including a cell array region, a core region, and an interface region between the cell array region and the core region; an interface device isolation film disposed in the interface region and defining the cell array region; a plurality of bit lines on the substrate in the cell array region and the interface region, each bit line including a bit line extension located in the interface region; a plurality of dummy active regions in a first local region and a second local region, the plurality of dummy active regions being defined in the substrate by the interface device isolation film, wherein the first local region and the second local region are selected in the interface region and spaced apart from each other, and the cell array region is located between the first local region and the second local region; and Multiple contact plugs extend vertically from above multiple bit lines to the multiple bit lines respectively. The multiple contact plugs are respectively connected to bit line extensions of multiple bit lines on multiple dummy active regions. The multiple dummy active regions are spaced apart from each other in a first lateral direction in each of a first local region and a second local region. The multiple dummy active regions are arranged in a line in the first lateral direction. Each of the multiple dummy active regions is arranged at a position that overlaps with the bit line extension of the selected bit line in the multiple bit lines in the vertical direction. Each of the multiple contact plugs contacts at least four surfaces of the selected bit line extension of the multiple bit lines facing different directions. Attached Figure Description

[0009] The embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a block diagram illustrating an example configuration of an integrated circuit (IC) device according to an embodiment;

[0011] Figure 2 yes Figure 1 A diagram showing an example of the layout configuration of the IC device;

[0012] Figure 3 It shows Figure 2 A schematic planar layout of the main components of the memory cell array included in the cell array area shown;

[0013] Figure 4 yes Figure 2 An enlarged plan view of some components included in a portion of the area marked "EX2";

[0014] Figure 5 It is along Figure 3 A cross-sectional view taken along the centerline X1-X1';

[0015] Figure 6 It is along Figure 3 A cross-sectional view taken along the centerline X2-X2';

[0016] Figure 7 It is along Figure 4 A cross-sectional view taken along the centerline X3-X3';

[0017] Figure 8 It is along Figure 4 A cross-sectional view taken along the centerline X4-X4';

[0018] Figure 9 It is along Figure 4 A cross-sectional view of the centerline Y1-Y1' and its extension;

[0019] Figure 10 It is along Figure 4 A cross-sectional view of the midline Y2-Y2' and its extension;

[0020] Figure 11 An example of a planar layout of a cell array region, an adjacent interface device isolation film, and multiple dummy active regions in an IC device according to an embodiment is shown.

[0021] Figure 12A and Figure 12B A cross-sectional view of an IC device according to an embodiment; and

[0022] Figure 13A , Figure 13B , Figure 13C , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 15C , Figure 16A , Figure 16B , Figure 16C , Figure 17A , Figure 17B , Figure 17C , Figure 17D , Figure 18A , Figure 18B , Figure 18C , Figure 18D , Figure 19 , Figure 20 , Figure 21A , Figure 21B , Figure 22A , Figure 22B , Figure 22C , Figure 23A , Figure 23B and Figure 23C This is a diagram illustrating the process sequence of a method for manufacturing an IC device according to an embodiment, wherein, Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19 , Figure 20 , Figure 22A and Figure 23A It is based on the process sequence and Figure 3 A cross-sectional view of the portion corresponding to the section taken along line X1-X1'. Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B and Figure 18B It is based on the process sequence and Figure 3 A cross-sectional view of the portion corresponding to the section cut along line X2-X2'. Figure 17C , Figure 18C , Figure 21A , Figure 22B and Figure 23B It is based on the process sequence and Figure 4 A cross-sectional view of the portion corresponding to the section cut along line X3-X3', and Figure 13C , Figure 15C , Figure 16C , Figure 17D , Figure 18D , Figure 21B , Figure 22C and Figure 23C It is based on the process sequence and Figure 4 A cross-sectional view of the portion corresponding to the section cut along line Y1-Y1'. Detailed Implementation

[0023] In the following description, embodiments will be illustrated with reference to the accompanying drawings. The same reference numerals are used to denote the same elements, and repeated descriptions thereof are omitted.

[0024] Figure 1 This is a block diagram illustrating an example configuration of an integrated circuit (IC) device 100 according to an embodiment.

[0025] refer to Figure 1 The IC device 100 may include a first region 22 and a second region 24. The first region 22 may be a memory cell region of a dynamic random access memory (DRAM) device, and the second region 24 may include a region forming the peripheral circuitry of the DRAM device and a core region (hereinafter referred to as the "peripheral circuitry region"). The first region 22 may include a memory cell array 22A. The second region 24 may include a row decoder 52, a sense amplifier 54, a column decoder 56, a self-refresh control circuit 58, a command decoder 60, a mode register set / extended mode register set (MRS / EMRS) 62, an address buffer 64, and data input / output (I / O) circuitry 66. Figure 1 The second region 24 can also be used to form peripheral circuits such as inverter chains and I / O circuits.

[0026] Figure 2 yes Figure 1 A diagram showing an example of the layout configuration of the IC device 100.

[0027] refer to Figure 1 and Figure 2 The first region 22 of the IC device 100 may include multiple cell array regions (CELLs) and a core region 30 surrounding the multiple cell array regions (CELLs). The multiple cell array regions (CELLs) can be connected to... Figure 1 This corresponds to a portion of the first region 22 shown. The core region 30 may be... Figure 1 This is a portion of the second region 24 shown. The core region 30 may include a sub-word line driver region 32 adjacent to one side of the cell array region CELL and a sense amplifier region 34 adjacent to the other side of the cell array region CELL. Figure 2 In this context, "MCA" refers to a memory cell array located within the cell array region (CELL), and can be associated with... Figure 1 This corresponds to the storage cell array 22A shown. Figure 2 In this context, "SWD" represents the sub-word line driver block located in core region 30, and sub-word line driver region 32 can also be referred to as sub-word line driver region SWD. "SA" represents the sense amplifier block located in core region 30, and sense amplifier region 34 can also be referred to as sense amplifier region SA.

[0028] The interface region IF can be located between the cell array region CELL and the core region 30. The interface region IF may include a first interface region IF1 between the cell array region CELL and the sub-word line driver region SWD, and a second interface region IF2 between the cell array region CELL and the sense amplifier region SA.

[0029] The sub-word line driver region SWD may include circuitry configured to drive multiple word lines arranged in the cell array region CELL. The sense amplifier region SA may include sense amplifiers configured to sense and amplify signals from multiple bit lines arranged in the cell array region CELL.

[0030] In the core region 30, a junction block may be located at the intersection of the sub-word line driver region SWD and the sense amplifier region SA. The power driver and ground driver configured to drive the bit line sense amplifier may be arranged within this junction block.

[0031] Figure 3 It shows Figure 2 The diagram shows a schematic planar layout of the main components of the storage cell array (MCA) included in the cell array region (CELL). Figure 3 The planar layout shown can be compared with Figure 2 The part shown in "EX1" corresponds to a certain area.

[0032] refer to Figure 3 The memory cell array (MCA) may include multiple active cell regions A1. Each of the multiple active cell regions A1 may be arranged with a main axis inclined along a first lateral direction (X direction) and a second lateral direction (Y direction) perpendicular to each other. Multiple word lines WL may intersect the multiple active cell regions A1 and extend parallel to each other in the first lateral direction (X direction). On the multiple word lines WL, multiple bit lines BL may extend parallel to each other in the second lateral direction (Y direction). The first lateral direction (X direction) and the second lateral direction (Y direction) may be perpendicular to each other.

[0033] Multiple bit lines BL can be connected to multiple active cell regions A1 via direct contacts DC. Multiple buried contacts BC can be located between two adjacent bit lines in the multiple bit lines BL. In the memory cell array MCA, the multiple buried contacts BC can be arranged in a line in a first lateral direction (X direction) and a second lateral direction (Y direction). Multiple conductive bonding pads LP can be arranged on the multiple buried contacts BC. The multiple buried contacts BC and the multiple conductive bonding pads LP can connect the lower electrode (not shown) of a capacitor formed on the multiple bit lines BL to the active cell region A1. Each conductive bonding pad LP can partially overlap with a buried contact BC. The multiple conductive bonding pads LP can be configured to be connected to the active cell region A1 via the buried contacts BC.

[0034] Figure 4 yes Figure 2 An enlarged plan view of some components included in the section marked "EX2". Figure 5 and Figure 6 Each is a cross-sectional view of a portion of the cell array region. Figure 5 It shows the relationship with Figure 3 The configuration corresponding to the cross section intercepted along line X1-X1', and Figure 6 It shows the relationship with Figure 3 The configuration corresponding to the cross section taken along the X2-X2' line. Figure 7 It is along Figure 4 The cross-sectional view taken by line X3-X3'. Figure 8 It is along Figure 4 A cross-sectional view taken from line X4-X4'. Figure 9 It is along Figure 4 A cross-sectional view of line Y1-Y1' and its extension, and Figure 10 It is along Figure 4 A cross-sectional view of the line Y2-Y2' and its extension. Figure 11 An example of a planar layout of a cell array region CELL in an IC device 100, an adjacent interface device isolation film 112A, and a plurality of dummy active regions DAC defined by the interface device isolation film 112A is shown.

[0035] Reference Figures 3 to 11 The IC device 100 is described in more detail below. The IC device 100 may include a substrate 102. The substrate 102 may include a cell array region (CELL), a peripheral circuit region including a core region (CORE) surrounding the cell array region (CELL), and an interface region (IF) between the cell array region (CELL) and the core region (CORE). The core region (CORE) may be connected to... Figure 4This corresponds to the core region 30 shown. The core region CORE may include a sub-word line driver region SWD adjacent to the cell array region CELL in the first lateral direction (X direction) and a sense amplifier region SA adjacent to the cell array region CELL in the second lateral direction (Y direction). The interface region IF may include a first interface region IF1 between the cell array region CELL and the sub-word line driver region SWD, and a second interface region IF2 between the cell array region CELL and the sense amplifier region SA.

[0036] Substrate 102 may include silicon, such as monocrystalline silicon, polycrystalline silicon, or amorphous silicon. In some embodiments, substrate 102 may include at least one selected from germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). In some embodiments, substrate 102 may include conductive regions, such as doped wells or doped structures.

[0037] Device isolation film 112 may be located in substrate 102. In cell array region CELL, a plurality of cell active regions A1 may be defined in substrate 102 by device isolation film 112. Interface device isolation film 112A defining cell array region CELL may be located in interface region IF. In the region of core region CORE adjacent to interface region IF, peripheral active regions A2 may be defined in substrate 102 by interface device isolation film 112A. In the first lateral direction (X direction) and the second lateral direction (Y direction), interface device isolation film 112A may have a width greater than that of device isolation film 112 located in cell array region CELL. Interface device isolation film 112A may be located between cell array region CELL and core region CORE to separate cell array region CELL from core region CORE. Device isolation film 112 and interface device isolation film 112A may have various depths depending on their location. In embodiments, each of device isolation film 112 and interface device isolation film 112A may include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof. For example, the portion of the device isolation film 112 with a relatively small width in the lateral direction (e.g., the X or Y direction) may consist only of a silicon oxide film; and the portion of the device isolation film 112 with a relatively large width in the lateral direction (e.g., the X or Y direction) and the interface device isolation film 112A may include an outer silicon oxide film, a silicon nitride film surrounded by the outer silicon oxide film, and an inner silicon oxide film surrounded by the silicon nitride film.

[0038] like Figure 11As shown, in the plan view (XY plane), the interface device isolation film 112A can have a shape surrounding the cell array region CELL. A plurality of dummy active regions DAC, defined by the interface device isolation film 112A in the substrate 102, can be arranged in the interface region IF. In the plan view (XY plane), each of the plurality of dummy active regions DAC is surrounded by the interface device isolation film 112A. The plurality of dummy active regions DAC can be located only in two of the two first interface regions IF1 and two second interface regions IF2 included in the interface region IF adjacent to the cell array region CELL. In each of the local regions of the two second interface regions IF2 spaced apart from each other in the second lateral direction (Y direction) and in which the cell array region CELL is located, the plurality of dummy active regions DAC can be spaced apart from each other in the first lateral direction (X direction) and arranged in a line in the first lateral direction (X direction).

[0039] like Figure 6 , Figure 9 and Figure 10 As shown, the IC device 100 may include multiple word lines WL, which intersect with multiple cell active regions A1 and extend longitudinally in a first lateral direction (X direction), with a vertical height lower than the vertical height of the uppermost surface of the substrate 102 in the cell array region CELL. The multiple word lines WL may extend parallel to each other. The lower surface and sidewalls of each word line in the multiple word lines WL may be covered by a gate dielectric film 116, and the upper surface of each word line in the multiple word lines WL may be covered by a buried insulating film 120. Figure 6 As shown, multiple groove spaces 120R can be formed in the upper surface of the buried insulating film 120.

[0040] In embodiments, the multiple word lines WL may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), or combinations thereof, but are not limited thereto. The gate dielectric film 116 may include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an oxide / nitride / oxide (ONO) film, or a high-k dielectric film with a dielectric constant higher than that of a silicon oxide film. For example, the gate dielectric film 116 may include HfO2, Al2O3, HfAlO3, Ta2O3, or TiO2, but are not limited thereto. The buried insulating film 120 may include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or combinations thereof, but are not limited thereto.

[0041] A buffer film 122 may be formed on the substrate 102. The buffer film 122 may include a first insulating film 122A and a second insulating film 122B. Each of the first insulating film 122A and the second insulating film 122B may include, but is not limited to, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a metal oxide film, or a combination thereof.

[0042] Multiple direct contacts DC can be formed on substrate 102. Each of the multiple direct contacts DC can be connected to a selected active unit region in a plurality of active unit regions A1. The multiple direct contacts DC may include silicon (Si), germanium (Ge), tungsten (W), tungsten nitride (WN), cobalt (Co), nickel (Ni), aluminum (Al), molybdenum (Mo), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), copper (Cu), or combinations thereof.

[0043] Multiple bit lines BL can extend longitudinally in the second lateral direction (Y direction) on the substrate 102 and multiple direct contacts DC. The multiple bit lines BL can extend longitudinally from the cell array region CELL to the second interface region IF2 in the second lateral direction (Y direction). The multiple bit lines BL can be spaced apart from each other in the first lateral direction (X direction) within the cell array region CELL and the second interface region IF2. Each bit line in the multiple bit lines BL may include a bit line extension BLE disposed in the second interface region IF2.

[0044] like Figure 4 and Figure 9 As shown, the bit line extension BLE of each bit line in the multiple bit lines BL can extend to a selected dummy active region in one of the multiple dummy active regions DAC located in the second interface region IF2. In each bit line in the multiple bit lines BL, a portion of the end of the bit line extension BLE away from the cell array region CELL can be arranged to overlap with a selected dummy active region in the multiple dummy active regions DAC in the vertical direction (Z direction) in the second interface region IF2.

[0045] like Figure 4As shown, in the second lateral direction (Y direction), the first shortest distance LY1 from the cell array region CELL to the end of the bit line extension BLE of each bit line in the multiple bit lines BL can be less than the second shortest distance LY2 from the cell array region CELL to the farthest end of each dummy active region in the multiple dummy active regions DAC. In the portion where the multiple bit lines BL and the multiple dummy active regions DAC overlap in the vertical direction (Z direction), the width of each dummy active region in the multiple dummy active regions DAC in the first lateral direction (X direction) can be greater than the width of the bit line extension BLE of each bit line in the multiple bit lines BL in the first lateral direction (X direction). In the planar view (XY plane), in the first lateral direction (X direction), each dummy active region in the multiple dummy active regions DAC can extend further outward than the two sidewalls of the bit line extension BLE of the corresponding bit line in the multiple bit lines BL.

[0046] like Figure 5 As shown, in the cell array region CELL, each bit line in the multiple bit lines BL can be connected to the cell active region A1 via the direct contact DC. For example... Figure 9 and Figure 10 As shown, in the cell array region CELL and the second interface region IF2, each of the multiple bit lines BL may include a lower conductive layer 130, an intermediate conductive layer 132, and an upper conductive layer 134 sequentially stacked on the substrate 102. In an embodiment, the lower conductive layer 130, the intermediate conductive layer 132, and the upper conductive layer 134 may include different materials. In an embodiment, the lower conductive layer 130 may include doped polysilicon. Each of the intermediate conductive layer 132 and the upper conductive layer 134 may include TiN, TiSiN, W, tungsten silicide, or a combination thereof. In an embodiment, the intermediate conductive layer 132 may include TiN, TiSiN, or a combination thereof, while the upper conductive layer 134 may include W.

[0047] like Figure 9 As shown, in the second interface region IF2, in the bit line extension BLE of at least one of the multiple bit lines BL, the end of the upper conductive layer 134 may be closer to the cell array region CELL than the ends of each of the lower conductive layer 130 and the intermediate conductive layer 132. In this document, in the second interface region IF2, the end of each of the lower conductive layer 130, the intermediate conductive layer 132, and the upper conductive layer 134 may refer to the portion of each of the lower conductive layer 130, the intermediate conductive layer 132, and the upper conductive layer 134 that is furthest from the cell array region CELL in the second lateral direction (Y direction).

[0048] Each bit line in the multiple bit lines BL can be covered by an insulating capping structure. The insulating capping structure may include a lower insulating capping layer 142, an insulating film 146, and an upper insulating capping layer 148. Each of the lower insulating capping layer 142, the insulating film 146, and the upper insulating capping layer 148 may include a silicon nitride film.

[0049] The sidewalls of the multiple bit lines BL and the insulating cap structure may be covered by multiple insulating spacers 152. The multiple insulating spacers 152 may extend longitudinally in a second lateral direction (Y direction) parallel to the multiple bit lines BL. The multiple insulating spacers 152 may include oxide films, nitride films, air spacers, or combinations thereof. The term "air" as used herein may refer to a space including the atmosphere or other gases that may be present during the manufacturing process.

[0050] like Figure 5 and Figure 6 As shown, in the cell array region CELL, multiple buried contacts BC and multiple insulating barriers 154 can be located between multiple bit lines BL, respectively. The multiple buried contacts BC and multiple insulating barriers 154 can be alternately arranged between two adjacent bit lines in the multiple bit lines BL in the second lateral direction (Y direction). Each buried contact BC can be electrically connected to a selected cell active region in the multiple cell active regions A1. The multiple insulating barriers 154 can fill multiple recessed spaces 120R formed on the upper surface of the buried insulating film 120 and can be located between the multiple buried contacts BC, respectively. In the second lateral direction (Y direction), the two sidewalls of each buried contact BC can be covered by the multiple insulating barriers 154. Each buried contact BC can be spaced apart from the bit line BL in the first lateral direction (X direction), with an insulating spacer 152 between the buried contact and the bit line. In an embodiment, the plurality of buried contacts BC may include doped polysilicon, and the plurality of insulating fences 154 may each include a silicon nitride film.

[0051] In the cell array region CELL and the second interface region IF2, the width of each bit line in the multiple bit lines BL in the first lateral direction (X direction) can be approximately constant in the second lateral direction (Y direction). For example, for each bit line in the multiple bit lines BL, the width of the portion located in the cell array region CELL in the first lateral direction (X direction) can be equal to or similar to the width of the portion located in the second interface region IF2 in the first lateral direction (X direction).

[0052] like Figure 5 , Figure 9 and Figure 10As shown, multiple conductive bonding pads LP can be arranged on multiple bit lines BL within a cell array region (CELL). Among the multiple conductive bonding pads LP, some conductive bonding pads LP adjacent to the edge portion of the cell array region (CELL) may be dummy structures, not contributing to the operation of the memory cell array (MCA). In embodiments, the multiple conductive bonding pads LP may include metal, conductive metal nitride, or a combination thereof. For example, the multiple conductive bonding pads LP may include tungsten (W), but are not limited thereto. Figure 5 As shown, the buried contact portion BC can be connected to the conductive bonding pad LP via the conductive contact plug 162. The conductive contact plug 162 may include TiN, but is not limited thereto.

[0053] like Figure 4 , Figure 7 , Figure 8 and Figure 9 As shown, multiple contact plugs (BCPs) can be arranged in multiple bit lines (BLs) within the second interface region (IF2). In each of two second interface regions (IF2) spaced apart in the second lateral direction (Y direction), with a cell array region (CELL) located between them and adjacent to that cell array region (CELL), the multiple contact plugs (BCPs) can be connected only to every other bit line selected from the multiple bit lines (BLs) in the first lateral direction (X direction). Figure 4 , Figure 9 and Figure 10 Among the multiple bit lines BL shown, the bit line BL that is not connected to the contact plug BCP in a second interface region IF2 adjacent to the cell array region CELL may have a bit line extension BLE, which is connected to another contact plug BCP in another second interface region IF2 adjacent to the cell array region CELL in the second transverse (Y direction). Figure 10 As shown, among the multiple bit lines BL, the bit line BL that is not connected to the contact plug BCP in a second interface region IF2 adjacent to the cell array region CELL can have an end face covered by the insulating spacer 152 (i.e., the sidewall of the bit line BL farthest from the cell array region CELL).

[0054] like Figure 7 and Figure 9 As shown, the contact plug BCP can extend vertically (Z-direction) from above the corresponding selected bit line among multiple bit lines BL, and contact and connect with the bit line extension BLE of the corresponding bit line BL. Each of the multiple contact plugs BCP can contact at least four surfaces facing different directions among the surfaces included in the bit line extension BLE of the corresponding bit line in the bit line BL.

[0055] In the second interface region IF2, each of the plurality of contact plugs BCP can be arranged to overlap with a selected dummy active region in the plurality of dummy active regions DAC in the vertical direction (Z direction). In an embodiment, each of the plurality of contact plugs BCP can have a portion that contacts at least four surfaces facing different directions among the surfaces included in the bit line extension BLE of the corresponding bit line in the bit line BL, and a lower surface that contacts the selected dummy active region in the plurality of dummy active regions DAC.

[0056] like Figure 9 As shown, each of the multiple contact plugs BCP includes a portion that contacts the upper surface of the intermediate conductive layer 132 included in its corresponding bit line BL, a portion that contacts the corresponding sidewalls of the lower conductive layer 130 and the intermediate conductive layer 132 included in its corresponding bit line BL, and a portion that contacts the corresponding end face of the lower conductive layer 130, the intermediate conductive layer 132 and the upper conductive layer 134 included in its corresponding bit line BL that is furthest from the cell array region CELL.

[0057] like Figure 4 As shown, in the plan view (XY plane), each of the multiple contact plugs (BCPs) can be arranged within a selected dummy active region of the multiple dummy active regions (DACs). In the lateral directions (e.g., the X and Y directions), the width of each dummy active region of the multiple dummy active regions (DACs) can be greater than the width of each contact plug of the multiple contact plugs (BCPs).

[0058] like Figure 9 As shown, wiring layer 164P can be disposed on each of the plurality of contact plugs BCP in the second interface region IF2. Wiring layer 164P can be integrally connected to the corresponding contact plug in the plurality of contact plugs BCP. Wiring layer 164P can extend longitudinally in the longitudinal direction (i.e., the Y direction) of its corresponding bit line BL, and its height is substantially the same as that of the plurality of conductive bonding pads LP disposed in the cell array region CELL. In this document, the vertical height of each of wiring layer 164P and conductive bonding pad LP refers to the shortest distance from the uppermost surface of substrate 102 in the vertical direction (Z direction). In embodiments, the plurality of conductive bonding pads LP, the plurality of contact plugs BCP, and wiring layer 164P can comprise the same metal. For example, the plurality of conductive bonding pads LP, the plurality of contact plugs BCP, and wiring layer 164P can each comprise tungsten (W), but are not limited thereto.

[0059] like Figures 5 to 10 As shown, the corresponding spaces between the multiple conductive bonding pads LP and the multiple wiring layers 164P can be filled by an insulating film 170. The insulating film 170 may include a silicon nitride film, a silicon oxide film, or a combination thereof.

[0060] like Figure 9 and Figure 10 As shown, multiple peripheral transistors (PTRs) can be arranged on substrate 102 within the core region (CORE). Each PTR can include a gate dielectric film 128 on substrate 102 and a peripheral gate PG on the gate dielectric film 128. The gate dielectric film 128 can include a silicon oxide film, a high-k dielectric film, or a combination thereof. The high-k dielectric film can include, but is not limited to, HfO2, Al2O3, HfAlO3, Ta2O3, or TiO2. Similar to the multiple bit lines BL arranged in the cell array region (CELL), the peripheral gate PG can include a lower conductive layer 130, an intermediate conductive layer 132, and an upper conductive layer 134 sequentially stacked on the gate dielectric film 128. Each peripheral transistor in the multiple PTRs can also include a pair of source / drain regions formed on both sides of the peripheral gate PG in substrate 102. The upper surface of the peripheral gate PG can be covered by an insulating capping layer 142. The sidewalls of the peripheral gate PG can be covered by insulating spacers 144. Each of the insulating capping layer 142 and the insulating spacer 144 may include, but is not limited to, a silicon nitride film.

[0061] like Figure 9 and Figure 10 As shown, an insulating film 146 and a gap-filling insulating film 145 can be sequentially stacked on the interface device isolation film 112A in the second interface region IF2. The insulating film 146 may include a silicon nitride film, and the gap-filling insulating film 145 may include a silicon oxide film. The gap-filling insulating film 145 may be covered by an upper insulating capping layer 148, which may be covered by an insulating film 170.

[0062] To prevent short circuits between adjacent bit lines in the multiple bit lines BL arranged in the cell array region CELL and the second interface region IF2 of the interface region IF adjacent to the cell array region CELL, reference is made to... Figures 1 to 11The described IC device 100 may include a plurality of dummy active regions (DACs) defined in a substrate 102 and spaced apart from each other by an interface device isolation film 112A in a second interface region IF2. In each of the plurality of bit lines BL, a bit line extension BLE located in the second interface region IF2 may extend to a selected dummy active region among the plurality of dummy active regions DAC. Since the bit line extensions BLE of the plurality of bit lines BL are located on different dummy active regions DAC that are separated from each other, the possibility of short circuits between adjacent bit lines in the plurality of bit lines BL through the dummy active regions DAC can be eliminated. Furthermore, contact plugs BCP extending from above each of the plurality of bit lines BL to the bit line extension BLE of its corresponding bit line BL may be arranged on a selected dummy active region among the plurality of dummy active regions DAC and may have a structure that contacts at least four surfaces facing different directions on the selected dummy active region DAC of the bit line extension BLE of its corresponding bit line BL. Accordingly, the contact area between the contact plug BCP and the bit line BL can be increased, thereby reducing the contact resistance between the contact plug BCP and the bit line BL. Furthermore, according to the present invention, the length of each bit line in the multiple bit lines BL can be shortened, such that the distance the multiple bit lines BL extend from the cell array region CELL is no greater than the distance they extend from the multiple dummy active regions DAC. Therefore, warping defects that may occur in each bit line in the multiple bit lines BL due to their relatively large length can be suppressed, while reducing the area occupied by the cell array region CELL and the interface region IF. Therefore, during the manufacturing of the IC device 100, the number of dies implemented on a single wafer can be increased, thereby improving the productivity of the IC device 100.

[0063] Figure 12A and Figure 12B This is a cross-sectional view of the IC device according to an embodiment. More specifically, Figure 12A The IC device 200 is shown with the edge Figure 4 The cross-sectional configuration corresponding to the section intercepted by the centerline X3-X3', and Figure 12B The edge of IC device 200 is shown. Figure 4 The configuration of the cross-sections intercepted by the centerline Y1-Y1' and its extension. Figure 12A and Figure 12B In the figures, the same reference numerals are used to indicate the same as those in the figures below. Figures 1 to 11 The same elements are used in the same way, so any repeated descriptions of them are omitted.

[0064] refer to Figure 12A and Figure 12B IC device 200 may have the same characteristics as the reference. Figures 1 to 11The IC device 100 described has a substantially identical configuration. However, the IC device 200 may include a plurality of contact plugs BCP2 connected to a plurality of bit lines BL in a second interface region IF2. In the second interface region IF2 of the IC device 200, the lower conductive layer 130, the intermediate conductive layer 132, and the upper conductive layer 134 included in the bit line extension BLE of the bit line BL that contacts the contact plugs BCP2 may have the same or similar length in the second lateral direction (Y direction).

[0065] Multiple contact plugs BCP2 can have the same characteristics as the reference. Figure 4 , Figure 7 , Figure 8 and Figure 9 The described plurality of contact plugs BCP2 have substantially the same configuration. Each contact plug in the plurality of contact plugs BCP2 may include a portion that contacts at least four surfaces facing different directions among the surfaces included in the bit line extension BLE of the corresponding bit line in the bit line BL, and a lower surface that contacts a selected dummy active region in the plurality of dummy active regions DAC. However, each contact plug in the plurality of contact plugs BCP2 may include a portion that contacts the upper surface of the upper conductive layer 134 included in its corresponding bit line BL, a portion that contacts the corresponding sidewalls of the lower conductive layer 130, the intermediate conductive layer 132 and the upper conductive layer 134 included in its corresponding bit line BL, and a portion that contacts the corresponding end face of the lower conductive layer 130, the intermediate conductive layer 132 and the upper conductive layer 134 included in its corresponding bit line BL that is farthest from the cell array region CELL.

[0066] According to the reference Figure 12A and Figure 12B The described IC device 200, in conjunction with the reference Figures 1 to 11 Similar to the described IC device 100, the possibility of short circuits between adjacent bit lines in multiple bit lines BL through dummy active regions (DACs) can be eliminated, and the contact area between the contact plug BCP2 and the bit lines BL can be increased, thereby reducing the contact resistance between the contact plug BCP2 and the bit lines BL. Furthermore, the length of each bit line in the multiple bit lines BL can be shortened, such that the distance the multiple bit lines BL extend from the cell array region CELL is no greater than the distance they extend from the multiple dummy active regions (DACs). Therefore, warping defects that may occur in each bit line in the multiple bit lines BL due to their relatively large length can be suppressed, while reducing the area occupied by the cell array region CELL and the interface region IF including the second interface region IF2. Therefore, the productivity of IC device 200 can be improved.

[0067] Next, a method for manufacturing an IC device according to an embodiment will be described in detail.

[0068] Figures 13A to 23C This is a diagram illustrating the process sequence of a method for manufacturing an IC device according to an embodiment. More specifically, Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19 , Figure 20 , Figure 22A and Figure 23A It is based on the process sequence and Figure 3 A cross-sectional view of the portion corresponding to the section taken along line X1-X1'. Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B and Figure 18B It is based on the process sequence and Figure 3 A cross-sectional view of the portion corresponding to the section cut along line X2-X2'. Figure 17C , Figure 18C , Figure 21A , Figure 22B and Figure 23B It is based on the process sequence and Figure 4 A cross-sectional view of the portion corresponding to the section cut along line X3-X3', and Figure 13C , Figure 15C , Figure 16C , Figure 17D , Figure 18D , Figure 21B , Figure 22C and Figure 23C It is based on the process sequence and Figure 4 A cross-sectional view of the portion corresponding to the section taken along line Y1-Y1'. (Refer to...) Figures 13A to 23C describe Figures 3 to 11 An example of a method for manufacturing IC device 100 is shown. Figures 13A to 23C In the figures, the same reference numerals are used to indicate the same as those in the figures below. Figures 3 to 11 The same elements are used in the same way, so any repeated descriptions of them are omitted.

[0069] refer to Figure 13A , Figure 13B and Figure 13C Multiple device isolation trenches T1 can be formed in the substrate 102, and multiple device isolation films 112 and interface device isolation films 112A can be formed to fill the multiple device isolation trenches T1. Therefore, multiple cell active regions A1 can be defined in the cell array region CELL of the substrate 102, peripheral active regions A2 can be defined in the peripheral circuit region including the core region CORE, and multiple dummy active regions DAC can be defined in the second interface region IF2.

[0070] Multiple word line trenches extending parallel to each other can be formed on the substrate 102 in the cell array region CELL. Next, a gate dielectric film 116, a word line WL, and a buried insulating film 120 can be sequentially formed within each of the multiple word line trenches. Impurity ions can be implanted into portions of the multiple cell active regions A1 located on either side of the multiple word lines WL, thereby forming multiple source / drain regions in the upper portion of the multiple cell active regions A1. In an embodiment, the multiple source / drain regions can be formed before the multiple word lines WL are formed.

[0071] Subsequently, a buffer film 122 can be formed by sequentially forming a first insulating film 122A and a second insulating film 122B on the main surface 102M of the substrate 102 in the cell array region CELL and the second interface region IF2; and a gate dielectric film 128 is formed on the main surface 102M of the substrate 102 in the peripheral circuit region including the core region CORE.

[0072] refer to Figure 14A and Figure 14B ,exist Figure 13A , Figure 13B and Figure 13C In the final structure, a lower conductive layer 130 can be formed on substrate 102 to cover buffer film 122 and gate dielectric film 128. Then, a portion of the lower conductive layer 130 can be etched in the cell array region CELL to expose portions of substrate 102 and device isolation film 112. The exposed portions of substrate 102 and device isolation film 112 can be etched to form multiple direct contact holes DCH, thereby exposing the cell active regions A1 of substrate 102. Multiple direct contacts DC can be formed to fill the multiple direct contact holes DCH. In an example of the process for forming multiple direct contacts DC, a conductive layer with a thickness sufficient to fill the direct contact holes DCH can be formed inside the multiple direct contact holes DCH and on the lower conductive layer 130, and this conductive layer can be etched back so that the conductive layer remains only inside the direct contact holes DCH. The conductive layer may include doped polysilicon, Ge, W, WN, Co, Ni, Al, Mo, Ru, Ti, TiN, Ta, TaN, Cu, or combinations thereof.

[0073] refer to Figure 15A , Figure 15B and Figure 15CIn each of the cell array region CELL, the second interface region IF2, and the peripheral circuit region including the core region CORE, an intermediate conductive layer 132, an upper conductive layer 134, and an insulating capping layer 142 can be sequentially formed on the lower conductive layer 130 and multiple direct contacts DC. Then, the insulating capping layer 142, the upper conductive layer 134, the intermediate conductive layer 132, the lower conductive layer 130, the buffer film 122, and the gate dielectric film 128 can be patterned. Therefore, a cell stack pattern including the buffer film 122, the lower conductive layer 130, multiple direct contacts DC, the intermediate conductive layer 132, the upper conductive layer 134, and the insulating capping layer 142 can be formed in the cell array region CELL and the second interface region IF2, and a peripheral stack pattern including the gate dielectric film 128, the peripheral gate PG, and the insulating capping layer 142 can be formed in the peripheral circuit region including the core region CORE. Subsequently, an insulating spacer 144 can be formed to cover the sidewalls of each of the cell stack pattern and the peripheral stack pattern.

[0074] Multiple peripheral transistors (PTRs) can be formed in the peripheral circuit region, including the core region (CORE). To form multiple peripheral transistors (PTRs), impurity ions can be implanted into the substrate 102 on both sides of the peripheral gate (PG) to form multiple source / drain regions.

[0075] refer to Figure 16A , Figure 16B and Figure 16C In the reference already executed Figure 15A , Figure 15B and Figure 15C In the final structure of the process, an insulating film 146 can be formed to conformally cover the exposed surface, and a gap-filling insulating film 145 can be used to fill the groove spaces on the insulating film 146. An upper insulating capping layer 148 with a planarized upper surface can be formed on the insulating film 146 and the gap-filling insulating film 145.

[0076] refer to Figure 17A , Figure 17B , Figure 17C and Figure 17D In the reference that has been executed Figure 16A , Figure 16B ,and Figure 16CIn the cell array region CELL of the structure obtained by the process, the cell stack pattern and the insulating film 146 and upper insulating capping layer 148 covering the cell stack pattern can be patterned. Therefore, multiple bit lines BL can be formed in the cell array region CELL and the second interface region IF2. Furthermore, multiple insulating spacers 152 can be formed to cover the sidewalls of each bit line in the multiple bit lines BL and the sidewalls of each of the lower insulating capping layer 142, the insulating film 146, and the upper insulating capping layer 148 remaining on the upper surface of each bit line in the multiple bit lines BL. After forming the multiple insulating spacers 152, line spaces LS can be retained between and adjacent to the multiple bit lines BL. The height of the upper insulating capping layer 148 can be reduced by an etching process performed during the formation of the multiple bit lines BL and the multiple insulating spacers 152.

[0077] In the cell array region CELL, the buffer film 122 exposed by the line space LS between two adjacent bit lines in the multiple bit lines BL and the substrate 102 located below it can be partially etched to form multiple recessed spaces RS exposing the active cell region A1. During the formation of the multiple recessed spaces RS, a portion of the buried insulating film 120 can also be etched to form multiple recessed spaces 120R in the upper surface of the buried insulating film 120.

[0078] refer to Figure 18A , Figure 18B , Figure 18C and Figure 18D A conductive layer can be formed to fill the line space LS between two adjacent bit lines in a plurality of bit lines BL, as well as the line space LS adjacent to each bit line in the plurality of bit lines BL. The conductive layer can have line spaces between two adjacent bit lines in the plurality of bit lines BL (see reference). Figure 18A The conductive layer is a linear planar shape extending longitudinally in the second lateral direction (Y direction) of the LS. The conductive layer may include doped polycrystalline silicon.

[0079] Subsequently, in the line space LS, the conductive layer can be patterned and separated into multiple conductive patterns BP. Insulating fences 154 can be formed to fill the corresponding spaces between the multiple conductive patterns BP in the line space LS.

[0080] refer to Figure 19 In the case that has been executed Figure 18A , Figure 18B , Figure 18C and Figure 18D In the structure obtained by the process shown, a portion of the thickness can be removed from the upper surface of each of the multiple conductive patterns BP to form multiple buried contacts BC. After forming the multiple buried contacts BC, a space HS can be left on each of the multiple buried contacts BC.

[0081] refer to Figure 20 ,exist Figure 19 In the resulting structure, multiple conductive contact plugs 162 can be formed to cover multiple buried contact portions BC and fill multiple spaces HS left between multiple bit lines BL respectively.

[0082] refer to Figure 21A and Figure 21B In the reference that has been executed Figure 20 In the structure obtained by the process, multiple contact holes CH can be formed to expose the bit line extensions BLE of multiple bit lines BL arranged in two second interface regions IF, which are adjacent to the two sides of the cell array region CELL in the second lateral direction (Y direction). Figure 21A and Figure 21B Multiple contact holes CH formed in one of the two second interface regions IF2 are shown. Multiple contact holes CH can be formed in one of the two second interface regions IF2 to expose bit line extensions BLE of a first set of bit lines BL, the first set of bit lines BL being selected from a plurality of bit lines BL, every other bit line. Multiple contact holes CH can be formed in the other of the two second interface regions IF2 to expose bit line extensions BLE of another set of bit lines BL, the other set of bit lines BL being selected from a plurality of bit lines BL, every other bit line, and not included in the first set.

[0083] In the second interface region IF2, multiple contact holes CH can be formed at locations that overlap with multiple dummy active regions DAC in the vertical direction (Z direction). To form the multiple contact holes CH, a portion of each of the multiple insulating fences 154, a portion of each insulating film covering the bit line extensions BLE selected from the multiple bit lines BL, and a portion of the upper conductive layer 134 included in the bit line extensions BLE can be etched in the second interface region IF2. Therefore, the upper surface of the intermediate conductive layer 132 included in the bit line extensions BLE, the sidewalls of each of the lower conductive layer 130 and the intermediate conductive layer 132, and the end faces of each of the lower conductive layer 130, the intermediate conductive layer 132, and the upper conductive layer 134 that are furthest from the cell array region CELL can be exposed through each of the multiple contact holes CH.

[0084] refer to Figure 22A , Figure 22B and Figure 22C In the case that has been executed Figure 21A and Figure 21BIn the structure obtained by the process, an upper conductive layer 164 can be formed to fill the plurality of contact holes CH and cover the upper surface of the upper insulating capping layer 148. In an embodiment, the upper conductive layer 164 may include tungsten (W).

[0085] refer to Figure 23A , Figure 23B and Figure 23C In the case that has been executed Figure 22A , Figure 22B and Figure 22C In the structure obtained by the process shown, the upper conductive layer 164 can be patterned. Therefore, multiple conductive bonding pads LP can be formed from the upper conductive layer 164 in the cell array region CELL, and multiple contact plugs BCP and multiple wiring layers 164P can be formed from the upper conductive layer 164 in the second interface region IF2. The multiple contact plugs BCP can respectively fill multiple contact holes CH, and the multiple wiring layers 164P can be integrally connected to the multiple contact plugs BCP.

[0086] Subsequently, within the cell array region (CELL), portions of the underlying structure exposed between the multiple conductive bonding pads (LP) can be etched. This allows for the removal of a portion of each of the multiple conductive contact plugs 162 covering multiple bit lines (BL), a portion of each of the multiple upper insulating caps 148, and multiple insulating spacers 152, thereby creating a separation space around each of the multiple conductive bonding pads (LP).

[0087] Subsequently, as Figures 5 to 10 As shown, an insulating film 170 can be formed to fill the corresponding spaces between multiple conductive bonding pads LP and multiple wiring layers 164P, thereby manufacturing an insulating film 170. Figures 3 to 11 The IC device 100 shown is shown.

[0088] In order to manufacture Figure 12A and Figure 12B The IC device 200 shown can perform the same function as the reference. Figures 13A to 23C The described process is similar to that of a conventional process. However, in the reference... Figure 21A and Figure 21B In the described process, multiple contact holes can be formed instead of multiple contact holes CH to expose the upper surface of the upper conductive layer 134, the sidewalls of each of the lower conductive layer 130, the intermediate conductive layer 132, and the upper conductive layer 134, and the corresponding end faces of the lower conductive layer 130, the intermediate conductive layer 132, and the upper conductive layer 134 that are furthest from the cell array region CELL, in the bit line extension BLE of each bit line in the multiple bit lines BL. Subsequently, the above-described process can be performed. Figures 22A to 23C The described process allows for the manufacture of Figure 12A and Figure 12BThe IC device 200 shown is shown.

[0089] Although it has been referenced Figures 13A to 23C Describes manufacturing Figures 1 to 23C The methods of IC devices 100 and 200 shown are for illustrative purposes only; however, it should be understood that, within the scope of the inventive concept, methods based on references are possible. Figures 13A to 23C The provided description shows that IC devices with various varied structures can be manufactured by making various modifications and changes to IC devices 100 and 200.

[0090] While the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit device, comprising: The substrate includes a cell array region, a core region, and an interface region between the cell array region and the core region; An interface device isolation film is disposed in the interface region and defines the cell array region; Multiple dummy active regions are spaced apart from each other in the interface region, and each dummy active region is surrounded by the interface device isolation film; as well as Multiple bit lines extend from the cell array region to the interface region. Each of the plurality of bit lines includes a bit line extension located in the interface region, and the bit line extension extends to a selected dummy active region among the plurality of dummy active regions.

2. The integrated circuit device according to claim 1, wherein, The plurality of dummy active regions are spaced apart from each other in the first lateral direction of the integrated circuit device and are arranged in a line in the first lateral direction. The plurality of bit lines are spaced apart from each other in the first lateral direction and extend in a second lateral direction of the integrated circuit device, wherein the second lateral direction is perpendicular to the first lateral direction; and... In the second lateral direction, the first shortest distance from the cell array region to the end of the bit line extension of each of the plurality of bit lines is less than the second shortest distance from the cell array region to the end of each of the plurality of dummy active regions that is furthest from the cell array region.

3. The integrated circuit device according to claim 1, further comprising: A contact plug extends vertically from above a first bit line selected from the plurality of bit lines in the integrated circuit device, and the contact plug contacts the bit line extension of the first bit line. The contact plug contacts at least four surfaces of the bit line extension of the first bit line that face different directions.

4. The integrated circuit device according to claim 1, further comprising: Multiple contact plugs extend vertically from above the multiple bit lines of the integrated circuit device, each of the multiple contact plugs being connected to a selected bit line among the multiple bit lines. Each of the plurality of contact plugs is arranged to overlap with a selected dummy active region among the plurality of dummy active regions in the vertical direction.

5. The integrated circuit device according to claim 1, further comprising: A contact plug extends vertically from above a first bit line selected from the plurality of bit lines in the integrated circuit device, and the contact plug contacts the bit line extension of the first bit line. The contact plug has a portion that contacts at least four surfaces facing different directions among the surfaces included in the bit line extension of the first bit line, and a lower surface that contacts a selected dummy active region among the plurality of dummy active regions.

6. The integrated circuit device according to claim 1, wherein, The core region includes a sub-word line driver region and a sense amplifier region. The interface region includes a first interface region between the cell array region and the sub-word line driver region, and a second interface region between the cell array region and the sense amplifier region. Of the multiple dummy active regions, only the second interface region is arranged among the first interface region and the second interface region.

7. The integrated circuit device according to claim 1, wherein, Each of the multiple bit lines comprises a lower conductive layer, an intermediate conductive layer, and an upper conductive layer, which are sequentially stacked on the substrate and comprise materials different from each other. In the bit line extension of at least one of the plurality of bit lines, the end of the upper conductive layer is closer to the cell array region than the end of the lower conductive layer.

8. The integrated circuit device according to claim 1, further comprising: Multiple conductive bonding pads are arranged to overlap with multiple bit lines in the vertical direction of the integrated circuit device in the cell array region, and the multiple conductive bonding pads are configured to connect to multiple cell active regions included in the cell array region of the substrate; A contact plug extends in the vertical direction from above the first bit line selected from the plurality of bit lines to the first bit line, and the contact plug contacts the bit line extension of the first bit line; as well as A wiring layer, integrally connected to the contact plug, extends from the upper surface of the contact plug in the longitudinal direction of the first wiring layer and is at the same vertical height as the plurality of conductive bonding pads. The plurality of conductive bonding pads, the contact plugs, and the wiring layer comprise the same metal.

9. The integrated circuit device according to claim 1, wherein, The plurality of dummy active regions are spaced apart from each other in the first lateral direction of the integrated circuit device and are arranged in a line in the first lateral direction. The plurality of bit lines are spaced apart from each other in the first lateral direction and extend in the second lateral direction of the integrated circuit device, wherein the second lateral direction is perpendicular to the first lateral direction. The width of each of the plurality of dummy active regions in the first lateral direction is greater than the second width of the bit line extension of each of the plurality of bit lines in the first lateral direction.

10. The integrated circuit device according to claim 1, further comprising: Multiple contact plugs extend vertically from above the multiple bit lines of the integrated circuit device, and each of the multiple contact plugs is connected to a bit line extension of a selected bit line among the multiple bit lines. In the plan view, each of the plurality of contact plugs is arranged within a selected dummy active region of the plurality of dummy active regions, and The first width of each of the plurality of dummy active regions in the lateral direction perpendicular to the vertical direction is greater than the third width of each of the plurality of contact plugs in the lateral direction.

11. An integrated circuit device, comprising: The substrate includes a cell array region, a core region surrounding the cell array region, and an interface region between the cell array region and the core region. An interface device isolation film is disposed in the interface region and defines the cell array region; as well as Multiple bit lines are provided on the substrate in the cell array region and the interface region. The multiple bit lines are spaced apart from each other in a first lateral direction of the integrated circuit device and extend in a second lateral direction perpendicular to the first lateral direction. Each bit line includes a bit line extension located in the interface region. as well as Multiple dummy active regions are defined in the substrate by the interface device isolation film in a first local region and a second local region, wherein the first local region and the second local region are selected in the interface region and spaced apart from each other in the second lateral direction, and the cell array region is between the first local region and the second local region. Wherein, the plurality of dummy active regions are spaced apart from each other in the first lateral direction in each of the first local region and the second local region, and are arranged in a line in the first lateral direction, and In each of the plurality of bit lines, a portion of the end of the bit line extension that is away from the cell array region is arranged in the interface region at a position in the vertical direction of the integrated circuit device that overlaps with a selected dummy active region among the plurality of dummy active regions.

12. The integrated circuit device of claim 11, wherein, in the second lateral direction, a first shortest distance from the cell array region to the end of the bit line extension of each of the plurality of bit lines is less than a second shortest distance from the cell array region to the end of each of the plurality of dummy active regions that is furthest from the cell array region.

13. The integrated circuit device of claim 11, further comprising a plurality of contact plugs, the plurality of contact plugs extending vertically from above the plurality of bit lines to the plurality of bit lines, in, Each of the plurality of contact plugs contacts at least four surfaces facing different directions among the surfaces included in the bit line extension of the bit line of the plurality of bit lines.

14. The integrated circuit device according to claim 11, further comprising: A plurality of contact plugs extend vertically from above the plurality of bit lines, each of the plurality of contact plugs being connected to a bit line extension of a selected bit line among the plurality of bit lines. Each of the plurality of contact plugs is arranged to overlap with a selected dummy active region among the plurality of dummy active regions in the vertical direction.

15. The integrated circuit device according to claim 11, further comprising: A plurality of contact plugs extend vertically from above the plurality of bit lines, each of the plurality of contact plugs being connected to a bit line extension of a selected bit line among the plurality of bit lines. Each of the plurality of contact plugs has a portion that contacts at least four surfaces of the surface included in the bit line extension facing different directions, and a lower surface that contacts a selected dummy active region among the plurality of dummy active regions.

16. The integrated circuit device according to claim 11, further comprising: A plurality of contact plugs extend vertically from above the plurality of bit lines, each of the plurality of contact plugs being connected to a bit line extension of a selected bit line among the plurality of bit lines. The bit line extension of each of the plurality of bit lines includes a lower conductive layer, an intermediate conductive layer, and an upper conductive layer, which are sequentially stacked on the substrate and comprise materials different from each other. Each of the plurality of contact plugs includes a portion that contacts the upper surface of the intermediate conductive layer, a portion that contacts the corresponding sidewalls of the lower conductive layer and the intermediate conductive layer, and a portion that contacts the corresponding end face of the lower conductive layer, the intermediate conductive layer, and the upper conductive layer that is furthest from the unit array region.

17. The integrated circuit device according to claim 11, further comprising: A plurality of contact plugs extend vertically from above the plurality of bit lines, each of the plurality of contact plugs being connected to a bit line extension of a selected bit line among the plurality of bit lines. The bit line extension of each of the plurality of bit lines includes a lower conductive layer, an intermediate conductive layer, and an upper conductive layer, which are sequentially stacked on the substrate and comprise materials different from each other. Each of the plurality of contact plugs includes a portion that contacts the upper surface of the upper conductive layer, a portion that contacts the corresponding sidewall of the lower conductive layer, the intermediate conductive layer, and the upper conductive layer, and a portion that contacts the corresponding end face of the lower conductive layer, the intermediate conductive layer, and the upper conductive layer that is furthest from the unit array region.

18. The integrated circuit device according to claim 11, wherein, In the first lateral direction, the first width of each of the plurality of dummy active regions is greater than the second width of the bit line extension of each of the plurality of bit lines.

19. An integrated circuit device, comprising: The substrate includes a cell array region, a core region, and an interface region between the cell array region and the core region; An interface device isolation film is disposed in the interface region and defines the cell array region; Multiple bit lines are provided on the substrate in the cell array region and the interface region, each bit line including a bit line extension located in the interface region; Multiple dummy active regions are defined in a first local region and a second local region, the multiple dummy active regions being defined in the substrate by the interface device isolation film, wherein the first local region and the second local region are selected in the interface region and spaced apart from each other, and the cell array region is located between the first local region and the second local region; and Multiple contact plugs extend vertically from above the multiple bit lines of the integrated circuit device, and the multiple contact plugs are respectively connected to the bit line extensions of the multiple bit lines on the multiple dummy active regions. In this configuration, the plurality of dummy active regions are spaced apart from each other in each of the first and second local regions in a first lateral direction of the integrated circuit device. The plurality of dummy active regions are arranged in a line in the first lateral direction, and each of the plurality of dummy active regions is arranged at a position overlapping in the vertical direction with a bit line extension of a selected bit line among the plurality of bit lines. Each of the plurality of contact plugs contacts at least four surfaces of the bit line extensions of the bit lines, which are oriented in different directions.

20. The integrated circuit device according to claim 19, wherein, The plurality of bit lines are spaced apart from each other in the first lateral direction and extend in the second lateral direction of the integrated circuit device, wherein the second lateral direction is perpendicular to the first lateral direction. In the second lateral direction, the first shortest distance from the cell array region to the end of the bit line extension of each of the plurality of bit lines is less than the second shortest distance from the cell array region to the end of each of the plurality of dummy active regions that is furthest from the cell array region.

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