Method and apparatus for predicting kernel tuning parameters - Patents.com

Abstract

A processing device for improving processing performance is provided, the processing device comprising: a memory configured to store data; and a processor in communication with the memory. The processor is configured to receive tuning parameters, each having a numerical value, for executing a portion of a program on an identified hardware device, convert the numerical values ​​of the tuning parameters into words, predict which combinations of words will be good for executing the portion of the program on the identified hardware device based on performance efficiency using one or more machine learning algorithms, and convert the predicted combinations of words into corresponding numerical values ​​for executing the portion of the program on the identified hardware device.

Description

[Technical field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims the benefit of U.S. Patent Application No. 16 / 560,954, entitled “METHOD AND APPARATUS FOR PREDICTING KERNEL TUNING PARAMETERS,” filed September 4, 2019, the entire contents of which are incorporated herein by reference. [Background technology]

[0002] The performance efficiency of a program is determined, for example, by the speed or time that the program's instructions are executed on hardware (e.g., an integrated circuit (IC) or chip). The physical characteristics and specifications of the hardware vary with different generations or versions of the hardware. Thus, the performance efficiency of a program typically varies significantly between different generations of hardware devices. Programs typically include tuning parameters that are used to vary the performance efficiency of the program for different hardware.

[0003] A more detailed understanding may be had from the following description, given by way of example in conjunction with the accompanying drawings, in which: [Brief description of the drawings]

[0004] [Figure 1] FIG. 1 is a block diagram of an example device capable of implementing one or more features of the present disclosure. [Diagram 2] 2 is a block diagram of the device of FIG. 1 showing additional details. [Diagram 3] FIG. 1 is a block diagram illustrating an example of a method for predicting tuning parameters of a program. [Figure 4] FIG. 4 illustrates an exemplary method for implementing the language learning and prediction shown in FIG. 3. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0005] Prior to deploying the program for execution on the identified hardware device, the program is typically profiled on the identified hardware by running the program using different combinations of program tuning parameters to vary performance efficiency, and the program tuning parameters for the identified hardware are selected based on the resulting performance efficiency.

[0006] The performance efficiency of a program varies depending on the values ​​of the program's tuning parameters. A program typically includes multiple tuning parameters (e.g., 10 parameters), each with multiple different selectable values ​​(e.g., 10 values). Different combinations of these tuning parameter values ​​compute correct results, but yield different performance efficiencies for these results.

[0007] Conventional profiling systems determine tuning parameter values ​​for a program (e.g., a GPU computing kernel) by a search algorithm that traverses a solution space. For example, for a matrix multiplication instruction, conventional systems must continually search a database of stored tuning parameter values ​​for each combination of matrix sizes being multiplied.

[0008] These search algorithms are costly and time consuming. For example, these conventional search algorithms typically require costly computational resources and a lot of time to tune a program (e.g., kernel). Furthermore, the tuning is only applied to selected programs. Running programs that are not selected typically results in poor performance and long delays if users choose to tune their own kernels. Additionally, these conventional search algorithms do not provide tuning parameter values ​​that take into account different input sizes for each program and the various types of problems the programs are trying to solve.

[0009] The devices and methods described herein use machine learning algorithms to efficiently determine tuning parameter values ​​for programs to run on identified hardware without the use of inefficient search algorithms, predicting tuning parameter values ​​based on input values ​​(e.g., input tensor values ​​including image dimensions, matrix dimensions, number of color channels, number of operations to perform).

[0010] In contrast to traditional machine learning models that output a numeric value based on an input numeric value, the machine learning algorithm described herein converts the input numeric value into a word (i.e., a language of one or more characters) and uses a language model to predict parameters from the input word. The language learning algorithm learns to translate from a source language (e.g., an input word or word sequence converted from one or more numeric values) to a target language (e.g., an output word sequence). The output word is then converted into a numeric value to obtain an actionable tuning parameter value.

[0011] Tuning parameter values ​​are predicted based on tuning parameter values ​​that are input to the program in sequence (as opposed to parallel input), and the tuning parameter values ​​are encoded as individual words rather than scalar numbers. The individual words are then translated using neural machine translation techniques (e.g., techniques that translate sentences from one language to another using a combination of multi-layer perceptrons (MLPs) and other ML primitives (convolution, activation, batch normalization, dropout, and recurrent neural networks (RNNs))).

[0012] In contrast to conventional language models, the machine learning language algorithms described herein predict tuning parameter values ​​based on pre-determined (i.e., determined before execution) constraints (e.g., invalid parameter value combinations, maximum number of allocated registers per thread, and amount of memory accessible per thread). The constraints prevent values ​​that cannot coexist or that would produce invalid results from being predicted as tuning parameter values. Thus, the constraints facilitate a more efficient prediction process because tuning parameter values ​​are predicted from a small space (i.e., a small number of potential parameter values) and also provide more accurate predictions because the selected tuning parameter values ​​avoid invalid results.

[0013] A processing device for improving processing performance is provided, the processing device including a memory configured to store data and a processor in communication with the memory, the processor configured to receive tuning parameters, each having a numerical value, for executing a portion of a program on an identified hardware device, convert the numerical values ​​of the tuning parameters into words, and the processor configured to predict, using one or more machine learning algorithms, which combinations of words are good for executing the portion of the program on the identified hardware device based on performance efficiency, and convert the predicted combinations of words into corresponding numerical values ​​for executing the portion of the program on the identified hardware device.

[0014] A method for improving processing performance is provided that includes receiving tuning parameters, each having a numerical value, and converting the numerical values ​​of the tuning parameters into words for executing a portion of a program on an identified hardware device. The method also includes predicting, using one or more machine language learning algorithms, which combinations of words are good for executing the portion of the program on the identified hardware device based on performance efficiency, and converting the predicted combinations of words into corresponding numerical values ​​for executing the portion of the program on the identified hardware device.

[0015] A non-transitory computer-readable storage medium is provided that includes instructions for causing a computer to perform a method, the method including receiving tuning parameters, each having a numerical value, for executing a portion of a program on an identified hardware device, and converting the numerical values ​​of the tuning parameters into words for executing the portion of the program on an identified hardware device. The method also includes predicting, using one or more machine language learning algorithms, which combinations of words are good for executing the portion of the program on the identified hardware device based on performance efficiency, and converting the predicted combinations of words into corresponding numerical values ​​for executing the portion of the program on the identified hardware device.

[0016] As used herein, a program includes any sequence of instructions executed using one or more processors to perform a procedure or routine (e.g., an operation, calculation, function, process, job). As used herein, execution of programmed instructions (e.g., an application, driver, operating system, or other software) on a processor includes any of a number of stages, such as, but not limited to, fetching, decoding, scheduling for execution, initiating execution, and executing a particular portion of the programmed instructions (e.g., rendering a video in full screen). Programmed instructions include tuning parameters and tuning parameter settings, which have tunable (i.e., changeable) values ​​used to control the performance efficiency of a program executed on a hardware device.

[0017] 1 is a block diagram of an example device 100 capable of implementing one or more features of the present disclosure. Device 100 may include, for example, a computer, a gaming device, a handheld device, a set-top box, a television, a mobile phone, or a tablet computer. Device 100 includes a processor 102, a memory 104, a storage 106, one or more input devices 108, and one or more output devices 110. Device 100 may also include optional input drivers 112 and output drivers 114. It should be understood that device 100 may include additional components not shown in FIG. 1.

[0018] In various alternatives, the processor 102 may include a central processing unit (CPU), a graphics processing unit (GPU), a CPU and a GPU located on the same die, or one or more processor cores, each of which may be a CPU or a GPU. In various alternatives, the memory 104 may be located on the same die as the processor 102 or may be separate from the processor 102. The memory 104 may include volatile or non-volatile memory (e.g., random access memory (RAM), dynamic RAM, cache).

[0019] Storage 106 includes fixed or removable storage (e.g., a hard disk drive, a solid state drive, an optical disk, or a flash drive). Input devices 108 include, but are not limited to, a keyboard, a keypad, a touch screen, a touch pad, a detector, a microphone, an accelerometer, a gyroscope, a biometric scanner, or a network connection (e.g., a wireless local area network card for transmitting and / or receiving wireless IEEE 802 signals). Output devices 110 include, but are not limited to, a display, a speaker, a printer, a haptic feedback device, one or more lights, an antenna, or a network connection (e.g., a wireless local area network card for transmitting and / or receiving wireless IEEE 802 signals).

[0020] The input driver 112 communicates with the processor 102 and the input device 108, allowing the processor 102 to receive input from the input device 108. The output driver 114 communicates with the processor 102 and the output device 110, allowing the processor 102 to send output to the output device 110. It should be noted that the input driver 112 and the output driver 114 are optional components, and that the device 100 operates similarly when the input driver 112 and the output driver 114 are not present. The output driver 114 includes an accelerated processing device (APD) 116 coupled to a display device 118. The APD is configured to accept computational and graphics rendering commands from the processor 102, process the computational and graphics rendering commands, and provide pixel output to the display device 118 for display. As described in more detail below, the APD 116 includes one or more parallel processing units configured to perform computations according to a single instruction, multiple data (SIMD) paradigm. Thus, although various functions are described herein as being performed by or in conjunction with APD 116, in various alternatives, the functions described as being performed by APD 116 are not driven by a host processor (e.g., processor 102) but are additionally or alternatively performed by other computing devices having similar functionality configured to provide graphical output to display device 118. For example, it is contemplated that any processing system that performs processing tasks according to the SIMD paradigm may be configured to perform the functions described herein. Alternatively, computing systems that do not perform processing tasks according to the SIMD paradigm are contemplated to perform the functions described herein.

[0021] 2 is a block diagram of device 100 showing additional details related to the execution of processing tasks on APD 116. APD 116 includes multiple compute units 132, a processing pipeline (e.g., graphics processing pipeline) 134, and a scheduler 136. Processor 102 maintains in system memory 104 one or more control logic modules for execution by processor 102. The control logic modules include operating system 120, kernel mode driver 122, and applications 126. These control logic modules control various aspects of the operation of processor 102 and APD 116. For example, operating system 120 communicates directly with hardware and provides an interface to the hardware for other software executing on processor 102. Kernel mode driver 122 controls the operation of APD 116 and accesses various features of APD 116, for example, by providing an application programming interface (API) for software (e.g., applications 126) executing on processor 102 to access various features of APD 116. Kernel mode driver 122 also includes a just-in-time compiler that compiles programs for execution by processing components of APD 116 (such as SIMD unit 138, described in more detail below).

[0022] APD 116 executes commands and programs for selected functions, such as graphics and non-graphics operations that may be suitable for parallel processing. APD 116 may be used to perform graphics pipeline operations, such as pixel manipulation, geometric calculations, and to render images on display device 118 based on commands received from processor 102. APD 116 also performs computational operations not directly related to graphics operations, such as video-related operations, physics simulations, computational fluid dynamics, or other tasks based on commands received from processor 102.

[0023] The APD 116 includes a computation unit 132 that includes one or more SIMD units 138 configured to perform operations at the request of the processor 102 in parallel according to the SIMD paradigm. The SIMD paradigm is a paradigm in which multiple processing elements share a single program control flow unit and program counter, thus allowing them to execute the same program, but execute it on different data. In one example, each of the SIMD units 138 includes 16 lanes, each of which can execute the same instruction simultaneously with the other lanes of the SIMD units 138, but execute it on different data. Prediction can be used to turn off lanes when not all lanes need to execute a given instruction. Prediction can also be used to execute programs with branching control flows. More specifically, for programs with conditional branches or other instructions where the control flow is based on calculations made by the individual lanes, prediction of the lanes that correspond to the control flow paths that are not currently executed, and serial execution of the different control flow paths, allows for arbitrary control flows.

[0024] The basic unit of execution in the compute units 132 is the work item. Each work item represents a single instantiation of a program to be executed in parallel on a particular lane. Work items can be executed simultaneously on a single SIMD processing unit 138 as a "wavefront." One or more wavefronts are included in a "workgroup," which includes a collection of work items designated to execute the same program. A workgroup can be executed by executing each of the wavefronts that make up the workgroup. In alternative examples, wavefronts are executed sequentially on a single SIMD unit 138, or partially or fully in parallel on different SIMD units 138. A wavefront can be thought of as the largest collection of work items that can be executed simultaneously on a single SIMD unit 138. Thus, if commands received from processor 102 indicate that a particular program is to be parallelized to such an extent that the program cannot run simultaneously on a single SIMD unit 138, then the program is divided into wavefronts that are processed in parallel on two or more SIMD units 138, or that are processed serially (or both in parallel and serial, as appropriate) on the same SIMD unit 138. Scheduler 136 is configured to perform operations related to scheduling various wavefronts on different compute units 132 and SIMD units 138.

[0025] The parallelism permitted by the computation units 132 is appropriate for graphics-related operations such as pixel value calculations, vertex transformations, and other graphics operations. Thus, in some cases, graphics processing pipeline 134, which accepts graphics processing commands from processor 102, provides computation tasks to computation units 132 for execution in parallel.

[0026] Computation unit 132 is also used to perform computational tasks that are not related to graphics or that are not performed as part of the "normal" operation of graphics processing pipeline 134 (e.g., custom operations performed to supplement the processing performed to the operation of graphics processing pipeline 134). Applications 126 or other software executing on processor 102 send programs defining such computational tasks to APD 116 for execution.

[0027] 3 is a block diagram illustrating an example method 300 for predicting tuning parameters for a program to be executed on an identified hardware device. Each portion of the method 300, such as encoding, converting, language learning, comparing, and predicting, is performed by a processor, such as the APD 116.

[0028] Tuning parameters include parameters that are categorical in nature (e.g., parameters that represent options provided to a program to change the performance efficiency of the program) and parameters that have numerical values ​​for tuning a particular parameter, such as, for example, the amount of data accessed from memory (e.g., main memory), the number of parallel memory accesses (e.g., reads, writes) made across a link, the number of input image channels (e.g., color channels of an image), the number of output channels (e.g., output channels of a hyperspectral image), the pipeline depth (e.g., input depth and output depth). The target values ​​of the tuning parameters are determined according to input parameters, such as, for example, image height, image width, total number of input channels, total number of output channels, and number of images processed at one time. Furthermore, tuning parameters differ, in part, by parameters that have different interpretations between programs.

[0029] 3, the method 300 includes receiving numerical values ​​for a plurality of tuning parameters of a program to be executed on an identified hardware device (e.g., an identified version of the hardware device), each of the numerical tuning parameter values ​​being received sequentially (i.e., in sequence) by the APD 116, for example.

[0030] As shown at 304 in Figure 3, the method 300 includes encoding the numerical values ​​in the sequence of tuning parameters. The encoding is performed by converting the tuning parameter values ​​from numerical values ​​to words of a language. The conversion of the tuning parameter values ​​includes converting a single numerical value to a word, converting one or more numerical values ​​to a word, and converting a single numerical value to multiple words. Examples of encoding include one-hot encoding and dense vectors generated from one-hot encoding.

[0031] Each converted word is provided to a machine language model 312 and predicted based on constraints 314 as part of the language learning and prediction process 306, and a machine language learning and prediction algorithm is used to predict which words to use to execute the program on the identified hardware device based on performance efficiency, i.e., the machine language learning algorithm predicts which word combinations (which correspond to the numerical tuning parameter values) will result in the portion of the program executing efficiently on the identified hardware device (e.g., predicting whether the word combinations will cause the portion of the program to execute faster than other word combinations or in less time than other word combinations).

[0032] The machine model 312 processes the converted word values ​​of the tuning parameters according to one or more machine learning primitives. Examples of machine learning primitives include convolutional neural networks (CNNs), recurrent neural networks (RNNs) including convolutional and pooling layers, one-way and two-way long short-term memory (LSTM) cells or gated recurrent units (GRUs), and densely connected deep neural networks with dropout and differential activation functions.

[0033] The words are predicted based on constraints 314, which may include, for example, invalid combinations of parameter values, a maximum number of registers allocated per thread, and an amount of memory accessible per thread. The constraints 314 prevent prediction of tuning parameter values ​​that cannot coexist with one or more other tuning parameters or that would produce invalid results. The constraints improve efficiency since the predictions are made in a small space. Additionally, the constraints improve the accuracy of the predictions since the predicted tuning parameter values ​​do not produce invalid results.

[0034] As shown at 308 in Figure 3, the method 300 includes decoding the predicted tuning parameter value. The decoding is performed by converting the predicted tuning parameter word value back to a numeric value. The predicted tuning parameter numeric value is then provided as a predicted executable tuning parameter value, as shown at 310 in Figure 3. A portion of the program is executed on the identified hardware device using the predicted executable tuning parameter value.

[0035] An example of the language learning and prediction process 306 will now be described in more detail with respect to Figure 4. As noted above, in contrast to conventional systems for determining tuning parameters that receive multiple tuning parameter values ​​in parallel, in accordance with features of the present disclosure, tuning parameter values ​​are predicted based on tuning parameter values ​​that are input to the program in a sequence, i.e., each of the input tuning parameter values ​​is received consecutively (i.e., in order) and the tuning parameter values ​​are predicted as a sequence.

[0036] Figure 4 illustrates an example method 400 for performing language learning and prediction as shown at 306 in Figure 3, where each of the input tuning parameter values ​​are received in succession. As described in more detail below, Figure 4 illustrates stages of a prediction sequence including filtering intermediate tuning parameter value candidates using constraints 314 and predicting the next tuning parameter value candidate in the sequence using the predicted tuning parameter value candidates (e.g., candidates determined to be more likely to execute a portion of a program with better performance efficiency than other tuning parameter value candidates). Each portion of the method 400, such as encoding, converting, language learning, comparing, filtering, determining, and predicting, is performed by a processor, such as the APD 116.

[0037] 4, each word 402(1)-402(n) of an input word sequence 402 is received. A representation learning process 404 is performed on each word 402(1)-402(n) according to one or more machine learning primitives (e.g., one or more of the machine learning primitives described above) to determine an internal representation 406 (e.g., a condensed representation of the words 402(1)-402(n) internal to the machine language model 312). Each block of representation learning 404 represents, for example, a memory cell used to determine an internal representation for a corresponding word of the input word sequence 402.

[0038] For example, during representation learning 404, the internal representation of first word 402(1) is output (e.g., temporarily stored) as internal representation 406 of first word 402(1). The internal representation of first word 402(1) is also provided upstream (indicated by the left-to-right arrow between the memory cells of first word 402(1) and the memory cells of second word 402(2)) and used to determine the internal representation of second word 402(2).

[0039] An intermediate internal representation of second word 402(2) is determined based on the internal representations of first word 402(1) and second word 402(2). The intermediate internal representation of second word 402(2) is then output (e.g., temporarily stored) as internal representation 406 of second word 402(2). The internal representation of second word 402(2) is also provided upstream to the memory cells of third word 402(3) (indicated by the left-to-right arrow between the memory cells of second word 402(2) and the memory cells of third word 402(3)) and used to determine an internal representation of third word 402(3). This process continues upstream (i.e., in the direction of the left-to-right arrow of representation learning 404) for each remaining word in input word sequence 402.

[0040] In the example shown in FIG. 4, representation learning 404 includes bidirectional learning. That is, an internal representation of each word 402(1)-402(n) is also provided downstream (i.e., in the direction of the arrow pointing from right to left in representation learning 404). Thus, the internal representation of each word 402(1)-402(n-1) is determined based on an upstream word in the input word sequence 402 (i.e., directly based on the next upstream word in the sequence, and indirectly based on other upstream words in the input word sequence 402). Also, features of the present disclosure may be implemented, for example, by unidirectional learning (i.e., in the direction of the arrow pointing from left to right).

[0041] Using the internal representation 406 of the words, a sequence of words is predicted for executing the portion of the program on the identified hardware device. The prediction process includes generating an intermediate word sequence 408 and an output word sequence 410. As described below, a number of tuning parameter candidates are used to predict the sequence of words for execution, including a candidate determined to be more likely to result in better performance efficiency than other candidates. For example, if a first candidate does not satisfy one or more constraints 314, the next most likely candidate is used to predict the words in the sequence.

[0042] In one example, the candidate numerical tuning parameters to be used during the prediction process are determined in advance (i.e., determined before run-time), e.g., a given number of predictions k are propagated, resulting in k predictions.

[0043] The internal representations of words 402(1)-402(n) of word sequence 402 are then provided to a similar machine learning structure to generate intermediate word sequence 408. Each block of intermediate word sequence 408 in FIG. 4 represents, for example, a memory cell that is used to intermediately predict a corresponding word 408(1)-408(n) (i.e., a potential tuning parameter value) of intermediate word sequence 408.

[0044] A first word 408(1) (i.e., a first candidate) of the intermediate word sequence 408 is intermediately predicted for executing the portion of the program on the identified hardware device based on one or more machine learning primitives described above. The internal representation of the first word 408(1) is analyzed based on one or more constraints 314 for the portion of the program (e.g., a portion of a kernel). That is, if the first word 408(1) satisfies each of the one or more constraints 314, the first word 408(1) is intermediately predicted as a parameter value candidate for the output word sequence 410. If the first word 408(1) does not satisfy each of the one or more constraints 314, the first word 408(1) is not selected as a parameter value candidate for the output word sequence 410.

[0045] The internal representation of the first word 408(1) is also provided to the next memory cell (i.e., the next upstream memory cell) to determine the second word 408(2) of the intermediate word sequence 408. If the second word 408(2) satisfies each of the one or more constraints 314 instead of the first word 408(1), the second word 408(2) is intermediately predicted as a parameter value candidate for the output word sequence 410. If the second word 408(2) does not satisfy each of the one or more constraints 314, the second word 408(2) is not selected as a parameter value candidate for the output word sequence 410. The process continues for each remaining word of the intermediate word sequence 408.

[0046] The prediction process also includes an attention mechanism that compares the tuning parameter values ​​with other tuning parameter values ​​to predict which combination of tuning parameter values ​​will result in better performance efficiency than other combinations of candidate tuning parameter values ​​for executing the portion of the program on the identified hardware device.

[0047] For example, the tuning parameter value candidates 410(1)-410(n) of the output word sequence 410 are compared and ranked according to their likelihood of executing a portion of a program with better performance efficiency than other tuning parameter value candidates. One or more of the tuning parameter value candidates of the output word sequence 410 (e.g., tuning parameter value candidates determined to be more likely to result in better performance efficiency than other candidates) are provided back to memory cells of the intermediate word sequence 408 to intermediately predict one or more words 408(1)-408(n) of the intermediate word sequence 408. Thus, the machine learning algorithm learns to predict tuning parameter values ​​based on input tuning parameter values ​​(e.g., values ​​of the input word sequence 402) and the predicted tuning parameter value candidates that are fed back to the machine learning algorithm.

[0048] Next, as shown in block 308 of FIG. 3, the predicted tuning parameter value candidates 410(1)-410(n) in the output word sequence 410 are converted back to numeric values ​​and provided as predicted executable tuning parameter values ​​310 shown in FIG. 3 for executing the portion of the program on the identified hardware device.

[0049] It should be understood that many variations are possible based on the disclosure herein, and although features and elements have been described above in particular combinations, each feature or element can be used alone without the other features and elements, or in various combinations with or without the other features and elements.

[0050] The provided methods may be implemented in a general purpose computer, processor, or processor core. Suitable processors include, by way of example, general purpose processors, special purpose processors, conventional processors, digital signal processors (DSPs), multiple microprocessors, one or more microprocessors associated with a DSP core, controllers, microcontrollers, application specific integrated circuits (ASICs), field programmable gate array (FPGA) circuits, any other type of integrated circuit (IC), and / or state machines. Such processors may be manufactured by configuring a manufacturing process using results of processing hardware description language (HDL) instructions and other intermediate data (instructions storable in a computer readable medium) including a netlist. Such processing results may be maskwork used in a semiconductor manufacturing process to manufacture a processor that performs application profiling for power performance management.

[0051] The various functional units illustrated in the figures and / or described herein (including, but not limited to, the processor 102, the input driver 112, the input device 108, the output driver 114, the output device 110, the accelerated processing device 116, the scheduler 136, the graphics processing pipeline 134, the computational unit 132, and the SIMD unit 138) may be implemented as a general purpose computer, processor or processor core, or as a program, software or firmware stored in a non-transitory computer readable storage medium or another medium and executable by a general purpose computer, processor or processor core.

[0052] The methods or flow charts provided herein may be implemented in a computer program, software, firmware embodied in a non-transitory computer-readable storage medium for execution by a general purpose computer or processor. Examples of non-transitory computer-readable storage media include read-only memory (ROM), random access memory (RAM), registers, cache memory, semiconductor memory devices, magnetic media such as internal hard disks and removable disks, magneto-optical media, optical media such as CD-ROM disks and digital versatile disks (DVDs).

Claims

1. A processing device for improving processing performance, comprising: a memory configured to store data; a processor in communication with the memory, The processor, receiving tuning parameters, each having a value, for executing a portion of the program on the identified hardware device; converting the tuning parameter values ​​into words; using one or more machine learning algorithms to predict which word combinations would be good for executing the portion of the program on the identified hardware device based on performance efficiency; converting the predicted word combinations into corresponding numeric values ​​for executing the portion of the program on the identified hardware device; [0023] Processing device.

2. the processor is configured to successively determine a machine learning representation for each word input in a word sequence, the machine learning representation being an encoded representation of a tuning parameter; The processing device of claim 1 .

3. the processor is configured to determine a machine-learned representation of a word in the sequence of words based on the determined machine-learned representation of another word in the sequence of words. The processing device of claim 2.

4. The processor, predicting intermediate sequences of words based on the machine-learned representations of each word; determining any word of the intermediate sequence of words as a candidate word of the predicted word combination if the word satisfies each of one or more predetermined constraints; determining any word of the intermediate sequence of words as not being a candidate word of the predicted word combination if the word does not satisfy each of the one or more predetermined constraints; [0023] The processing device of claim 2.

5. each of the one or more predetermined constraints indicating whether a combination of words would cause an invalid result to be produced by executing the portion of the program; The processing device of claim 4.

6. The processor, determining the words of the intermediate sequence of words as candidate words of the predicted word combination; predicting a next word in the intermediate sequence of words based on a candidate word determined to be more likely to execute the portion of the program with better performance efficiency than other candidate words; [0023] The processing device of claim 4.

7. the performance efficiency being a measure of the speed or time to execute a portion of the program; the processor is configured to determine which combinations of words are better for executing the program on the identified hardware device based on the performance efficiency by predicting which combinations of words are better for executing the portion of the program faster or in less time than other combinations of words. The processing device of claim 1 .

8. the received values ​​of the tuning parameters are tensor input values. The processing device of claim 1 .

9. the one or more machine learning algorithms are implemented using at least one of a convolutional neural network, a recurrent neural network, and a coupled neural network; The processing device of claim 1 .

10. 1. A method for improving processing performance, comprising: receiving tuning parameters, each having a value, for executing a portion of the program on the identified hardware device; converting the tuning parameter values ​​into words; predicting, using one or more machine learning algorithms, which word combinations would be good for executing the portion of the program on the identified hardware device based on performance efficiency; and and converting the predicted word combinations into corresponding numeric values ​​for executing the portion of the program on the identified hardware device. method.

11. and determining a machine language learning representation for each word input in the word sequence, the machine language learning representation being an encoded representation of a tuning parameter. The method of claim 10.

12. determining a machine-learned representation for a word in the sequence of words based on the determined machine-learned representation for another word in the sequence of words.

12. The method of claim 11.

13. predicting intermediate sequences of words based on the machine-learned representations of each word; determining any word of the intermediate sequence of words as a candidate word of the predicted word combination if the word satisfies each of one or more predetermined constraints; determining any word of the intermediate sequence of words as not being a candidate word of the predicted word combination if the word does not satisfy each of the one or more predetermined constraints. The method of claim 10.

14. each of the one or more predetermined constraints indicating whether a combination of words would cause an invalid result to be produced by executing the portion of the program; 14. The method of claim 13.

15. determining the words of the intermediate sequence of words as candidate words of the predicted word combination; and predicting a next word in the intermediate sequence of words based on the candidate word determined to be more likely to execute the portion of the program with better performance efficiency than other candidate words.

14. The method of claim 13.

16. ranking each of the plurality of words of the intermediate sequence of words according to the likelihood of the candidate word to execute the portion of the program with greater performance efficiency than the other candidate words.

16. The method of claim 15.

17. the performance efficiency being a measure of the speed or time to execute a portion of the program; the method includes determining which combinations of words are better for executing the portion of the program on the identified hardware device based on the performance efficiency by predicting which combinations of words are better for executing the portion of the program faster or in less time than other combinations of words.

12. The method of claim 11.

18. the received values ​​of the tuning parameters are tensor input values.

12. The method of claim 11.

19. the one or more machine learning algorithms are implemented using at least one of a convolutional neural network, a recurrent neural network, and a coupled neural network; 12. The method of claim 11.

20. A computer-readable storage medium having instructions for causing a computer to perform a method, comprising: The method comprises: receiving tuning parameters, each having a value, for executing a portion of the program on the identified hardware device; converting the tuning parameter values ​​into words; predicting, using one or more machine learning algorithms, which word combinations would be good for executing the portion of the program on the identified hardware device based on performance efficiency; and and converting the predicted word combinations into corresponding numeric values ​​for executing the portion of the program on the identified hardware device. A computer-readable storage medium.

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