Photoelectric conversion device

Abstract

To provide a photoelectric conversion device advantageous for reducing loss of a signal.SOLUTION: A photoelectric conversion device includes a low-impurity concentration N-type semiconductor region 12 in which semiconductor regions having respective functions are disposed. The semiconductor regions include: an N-type semiconductor region 15 that stores signal charge generated by incident light; a P-type semiconductor region 13 that overlaps with the N-type semiconductor region 15 in a plan view, influences sensitivity of a PD part 2, and is electrically connected with a P-type semiconductor region 19 via P-type semiconductor regions 21, 22 disposed between the P-type semiconductor region 19 and the P-type semiconductor region 13; high-impurity concentration P-type semiconductor regions 14, 14' that are formed in semiconductor interface parts of the PD part and a memory part 3; the PD part including the P-type semiconductor region 14', the N-type semiconductor region 15, and an N-type semiconductor region that exists directly under the semiconductor region 15 and extends to a depth of the P-type semiconductor region 13; an N-type semiconductor region 16 that holds signal charge transferred from the N-type semiconductor region 15; and the memory part 3 including the P-type semiconductor region 14 and the N-type semiconductor region 16.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a photoelectric conversion device. [Background technology]

[0002] There is a sensor with a global shutter function. The sensor has an array of pixels, each of which has a photoelectric conversion device. The photoelectric conversion device included in the pixel may have a photodiode section (hereinafter referred to as a "PD section"), a memory section, and a gate for transferring the signal charge accumulated in the PD section to the memory section. In a sensor with a global shutter function, the timing of the start of signal accumulation in the PD section is aligned, and the timing of the end of accumulation is aligned by simultaneously transferring the signal charge from the PD section to the memory section. This realizes the global shutter function. Patent Document 1 discloses the configuration of a sensor with a global shutter function. Patent Document 1 describes that a first-conductivity-type high-impurity-concentration barrier region is provided below a second-conductivity-type charge accumulation region to block false signals from flowing into the charge accumulation region.

[0003] The inflow of false signals can be reduced by narrowing the area into which false signals can flow in the memory section. Therefore, the barrier region is often formed at a shallow position with a high concentration. If the barrier region is highly concentrated, the extension of the depletion layer from the charge storage region is small, and the area into which false signals can flow can be restricted to a narrow range. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2011-249406 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in such a structure, when the transfer gate electrode is turned on, the charge accumulation region is likely to lose its buried state, and the signal charge transferred from the PD section comes into contact with the semiconductor interface. Many trap levels exist at the semiconductor interface. If the signal carrier is an electron, the electron will be captured at the trap levels. When the gate electrode is turned off, holes are accumulated at the interface, and the captured electrons may recombine with the holes and disappear. This may result in signal loss. An object of the present invention is to provide a photoelectric conversion device that is advantageous in reducing signal loss. [Means for solving the problem]

[0006] The photoelectric conversion device of the present invention includes a first semiconductor region of a first conductivity type disposed between a first surface and a second surface, a second semiconductor region of a first conductivity type disposed between the first surface and the second surface and configured to accumulate signal charges generated by incident light, a third semiconductor region of a first conductivity type disposed between the first surface and the second surface, a fourth semiconductor region of a first conductivity type disposed between the first surface and the second surface and in contact with the third semiconductor region, a fifth semiconductor region of a second conductivity type disposed between the fourth semiconductor region and the first surface, and a fifth semiconductor region of a second conductivity type disposed on the first surface and configured to transfer the signal charges accumulated in the second semiconductor region to the third semiconductor region. first the third semiconductor region overlaps at least a part of the first transfer electrode and at least a part of the sixth semiconductor region in a plan view; the sixth semiconductor region and the seventh semiconductor region are electrically connected; an effective amount of dopant ions per unit area for forming the seventh semiconductor region is greater than an effective amount of dopant ions per unit area for forming the sixth semiconductor region; and a position at which the seventh semiconductor region is disposed is at a depth from the first surface that is the same as or deeper than that of the sixth semiconductor region. In a state in which the first channel is formed, the potential of the third semiconductor region is lower than the potential of the first transfer electrode. It is characterized by the fact that Effect of the Invention

[0007] It is possible to provide a photoelectric conversion device that is advantageous in reducing signal loss. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view of a photoelectric conversion device according to the present invention. [Diagram 2] 1 is a cross-sectional view of a photoelectric conversion device according to the present invention. [Diagram 3] FIG. [Figure 4] FIG. 13 is a graph showing a profile of an impurity concentration. [Diagram 5] FIG. 13 is a plan view of a modified example of the photoelectric conversion device. [Figure 6] FIG. 11 is a cross-sectional view of a modified example of a photoelectric conversion device. [Figure 7] FIG. 1 is a plan view showing an outline of a solid-state imaging device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the invention according to the claims, and not all combinations of features described in the embodiments are essential to the invention. Two or more features among the multiple features described in the embodiments may be arbitrarily combined. In addition, the same reference numbers are used for the same or similar configurations, and duplicated descriptions are omitted.

[0010] In the following embodiments, the signal carriers are electrons, so the conductivity type of the signal storage layer is N-type, and the transistors forming the circuit are also N-type MOS transistors unless otherwise specified. However, the signal carriers may be holes, and the N-type conductivity and P-type conductivity may be interchanged.

[0011] [Embodiment 1] A photoelectric conversion device according to this embodiment will be described. The photoelectric conversion device may include a PD section, a memory, and a PD signal transfer section for transferring the signal charge accumulated in the PD section to the memory. Furthermore, the photoelectric conversion device may include a memory signal transfer section for transferring the signal charge from the memory to a floating diffusion region (hereinafter referred to as an "FD section"), and an amplifying MOS transistor for amplifying and outputting the signal charge. When performing a global shutter operation, the signal charges accumulated in the PD section are transferred to the memory all at once.

[0012] FIG. 1 is a plan view of a semiconductor substrate on which a photoelectric conversion device 1 according to the present embodiment is formed, and shows a simplified layout of the photoelectric conversion device 1. The photoelectric conversion device 1 may have a photodiode (PD) section 2, a memory section 3 for holding signal charges, a transfer electrode 4 for transferring signal charges from the PD section 2 to the memory section 3, an FD section 5, and a transfer electrode 6 for transferring the signal charges held in the memory section 3 to the FD section 5. The photoelectric conversion device 1 may further have a signal charge discharge section (hereinafter referred to as "OFD") 7 for discharging signal charges to reset the PD section 2, and a transfer electrode 8 for transferring the signal charges accumulated in the PD section 2 to the OFD 7. The photoelectric conversion device 1 may also have a MOS transistor section 9 including a MOS transistor for amplifying and reading out the signal charges transferred to the FD section 5. An N-type semiconductor region 10 is arranged under the transfer electrode 4, in contact with the N-type semiconductor region of the memory section 3 and formed near the semiconductor interface. For element isolation, the semiconductor device may also have an element isolation section 11 formed of, for example, an oxide film such as Shallow Trench Isolation (STI) or a diffusion layer semiconductor.

[0013] The transfer electrodes 4, 6 and 8 can be disposed on the surface of a semiconductor substrate on which the PD 2 and the memory section 3 are formed. The N-type semiconductor region 10 is disposed so that at least a portion of it overlaps with the transfer electrode 4 in a plan view.

[0014] The MOS transistor section 9 may include a plurality of MOS transistors, such as a MOS transistor for signal amplification and a reset MOS transistor for resetting the FD section. A light shielding member may be disposed on the memory section 3 to reduce or prevent light from entering the memory section. For example, tungsten may be used as the light shielding member.

[0015] FIG. 2 is a cross-sectional view between A and B indicated by the dashed line in FIG. 1. This example shows an example in which semiconductor regions having various functions are arranged in an N-type semiconductor region 12 with a low impurity concentration. The N-type semiconductor region 15 can accumulate signal charges generated by incident light. The P-type semiconductor region 13 overlaps with the N-type semiconductor region 15 in a plan view, and can determine the sensitivity of the PD2. The P-type semiconductor region 13 can be electrically connected to the P-type semiconductor region 19 through the P-type semiconductor regions 21 and 22 arranged between the P-type semiconductor region 13 and the P-type semiconductor region 19. The P-type semiconductor regions 14 and 14' with a high impurity concentration are formed at the semiconductor interface of the PD section 2 and the memory section 3. The PD section 2 includes the P-type semiconductor region 14', the N-type semiconductor region 15, and an N-type semiconductor region that is directly under the semiconductor region 15 and extends to the depth of the P-type semiconductor region 13. The N-type semiconductor region 16 can hold signal charges transferred from the N-type semiconductor region 15. The memory section 3 includes a P-type semiconductor region 14 and an N-type semiconductor region 16. The PD 2 and the memory section 3 both have a buried structure.

[0016] The P-type semiconductor region 17 can electrically separate the N-type semiconductor region 15 from the N-type semiconductor region 10. The P-type semiconductor region 17 is located under the transfer electrode 4, and at least a part of it overlaps with the transfer electrode 4 in a planar view. The P-type semiconductor region 18 can electrically separate the N-type semiconductor region 16 from the FD section 5, which is an N-type semiconductor region. The P-type semiconductor region 19 is located under the N-type semiconductor region 10, and is arranged so as to overlap at least a part of it with the N-type semiconductor region 10 in a planar view and not overlap with the N-type semiconductor region 16. The P-type semiconductor region 20 is located under the N-type semiconductor region 16, and is arranged so as to overlap at least a part of it with the N-type semiconductor region 16 in a planar view. The P-type semiconductor regions 19 and 20 can prevent signal charges generated in the PD section by incident light on the PD section 2 from diffusing and flowing into the N-type semiconductor region 10 or the N-type semiconductor region 16. The P-type semiconductor regions 21 and 22 are both regions for separating the PDs of adjacent photoelectric conversion devices from each other. In other words, the separation boundary portion of the photoelectric conversion device can at least partially overlap with the memory section 3 and the FD section 5 when viewed in a plan view.

[0017] A thin dielectric film 23 is formed on the semiconductor interface. The transfer electrodes 4, 6, and 8 and the gate electrodes of the MOS transistors are formed on the dielectric film 23. A light shielding member 30 may be disposed on the memory section 3 (in the direction of the transfer electrodes 4 and 6 with respect to the dielectric film 23 in FIG. 2) in order to reduce or prevent light from being incident on the memory section 3. The light shielding member 30 may be disposed so as to cover the other regions except for the PD section 2.

[0018] Next, consider the potential change due to the change in the potential of the transfer electrode 4 when the signal charge is transferred from the N-type semiconductor region 15 to the N-type semiconductor region 10. FIG. 3 is a potential diagram between C and D indicated by the dashed line under the transfer electrode 4 in FIG. 2. That is, FIG. 3 shows the transfer electrode 4, the dielectric film 23, the N-type semiconductor region 10, the P-type semiconductor region 19, and the cross-sectional potential profile of the N-type semiconductor region between the N-type semiconductor region 10 and the P-type semiconductor region 19. A channel is formed according to the potential of the transfer electrode 4. When the potential of the transfer electrode 4 is VL, the channel is in the OFF state, and when the potential is VH, the channel is in the ON state. In the ON state, the signal charge is transferred from the N-type semiconductor region 15 to the N-type semiconductor region 10.

[0019] The line indicated by potential 1 is the potential profile when the potential of the transfer electrode 4 is VL. Here, the difference in potential between the lowest point of the potential indicated by potential 1 and the semiconductor interface or the neutral region of the P-type semiconductor region 19 is taken as the embedding voltage V1. The semiconductor interface is in a pinning state, that is, a state in which holes gather, so it has the same potential as the neutral region of the P-type semiconductor region 19. Let Qe be the electron charge, k be the Boltzmann constant, and T be the absolute temperature, and then Qe·V1 be sufficiently larger than k·T. In other words, even if the signal charge is at the bottom of potential 1 of the N-type semiconductor 10, the electrons are unlikely to be thermally excited to the semiconductor interface.

[0020] The line indicated by potential 2 represents a state in which the embeddability disappears when the potential of the transfer electrode 4 is VH. The line indicated by potential 3 represents a state in which the embeddability is sufficiently maintained when the potential of the transfer electrode 4 is VH. In the case of potential 2, the signal charges (electrons in this example) transferred from the N-type semiconductor region 15 accumulate at the semiconductor interface and are easily captured by the capture level at the interface. On the other hand, in the case of potential 3, the electrons transferred from the N-type semiconductor region 15 are hardly thermally excited at the semiconductor interface because the embeddability is maintained, and therefore the electrons are hardly captured by the capture level at the interface.

[0021] When the potential of the transfer electrode 4 becomes potential VL again, holes are induced at the semiconductor interface of the N-type semiconductor region 10, and most of the electrons captured at the semiconductor interface disappear due to recombination with the holes. In other words, when the transfer electrode 4 is on and in the situation represented by potential 2, at least a part of the signal charge transferred from the N-type semiconductor 15 disappears. However, in the situation represented by potential 3, the embedding property is maintained, so almost no signal charge disappears, and almost all of the signal charge can be transferred to the N-type semiconductor 16.

[0022] The reason for the difference between the situation of potential 2 and the situation of potential 3 as described above will be explained below. In the following, when we say capacitance, we mean capacitance per unit area. The amount of change in potential of the transfer electrode 4 when the potential of the transfer electrode 4 changes from potential VL to potential VH is set to V0. The amount of change in potential of the N-type semiconductor 10 when the potential changes to potential 2 is set to V2. The amount of change in potential of the N-type semiconductor 10 when the potential changes to potential 3 is set to V3.

[0023] The capacitance between the transfer electrode 4 and the semiconductor interface directly below it is the capacitance formed by the dielectric film 23, and this is C0. Assuming that the charge is stored at the lowest point of the potential of the N-type semiconductor 10, the capacitance between this and the semiconductor interface is C1. Therefore, since C0 and C1 are connected in series, the capacitance between the transfer electrode 4 and the N-type semiconductor region 10 is C0·C1 / (C0+C1), which is C01. The PN junction capacitance between the N-type semiconductor region 10 and the P-type semiconductor 19 is C2. In this case, when the transfer electrode 4 changes from potential VL to potential VH, the potential of the N-type semiconductor region 10 changes in response to the change in the potential of the transfer electrode 4. From the relationship between the voltages applied to C01 and C2, it drops by C01 / (C01+C2)×V0, which corresponds to the voltage applied to C2, where V0=VH-VL.

[0024] If the voltage drop in response to the change in the potential of the transfer electrode 4 is small, such as V2, the potential of the N-type semiconductor region 10 becomes higher than the potential of the transfer electrode 4, and the embeddability disappears. If the voltage drop in response to the change in the potential of the transfer electrode 4 is large, such as V3, the potential of the N-type semiconductor region 10 becomes lower than the potential of the transfer electrode 4, and the embeddability is maintained.

[0025] In other words, when the capacitance division ratio C01 / (C01+C2) is small, a situation like potential 2 will occur, and when the capacitance division ratio C01 / (C01+C2) is large and closer to 1, a situation like potential 3 will occur. If the capacitance division ratio is 1, V3=V0, and the embedded voltage V1 can be maintained as it is even when the transfer electrode 4 is on. Depending on the value of C2, the embeddability can be maintained even when the transfer electrode 4 is on, but the embedding voltage may not be sufficient, which may cause some loss of signal charge. Therefore, the smaller C2 is, the more the embeddability of the N-type semiconductor 10 can be maintained.

[0026] From the standpoint of preventing the disappearance of signal charge, C2 = 0 is ideal. However, if the distance between the N-type semiconductor region 10 and the P-type semiconductor region 19 is increased in order to reduce C2, that is, if the P-type semiconductor region is formed at a deeper position, the possibility of false signals flowing in increases, and the false signals mixed into the memory section may become larger.

[0027] Therefore, in order to prevent spurious signals while maintaining the embeddability of the N-type semiconductor region 10 and reducing the loss of signal charges, it is advisable to form the P-type semiconductor region 19 at a shallow position and set its impurity concentration appropriately. Then, when the transfer electrode 4 is off, most of the P-type semiconductor region 19 is a neutral region, while when the transfer electrode 4 is on, most of the P-type semiconductor region 19 is depleted. When most of the P-type semiconductor region 19 is depleted, C2 becomes a value close to zero, and the capacitance division ratio C01 / (C01+C2) becomes a value close to 1. At this time, the embeddability of the N-type semiconductor region 10 can be maintained sufficiently, as shown in potential 3. The impurity concentration of the P-type semiconductor region 19 that satisfies these conditions is obtained.

[0028] The relationship between the N-type semiconductor region 10 and the P-type semiconductor region 19 will be described with reference to FIG. 4. As a premise for obtaining the conditions, let the distance between the N-type semiconductor region 10 and the P-type semiconductor region 19 be D, and assume that the impurity distribution widths of the N-type semiconductor region 10 and the P-type semiconductor region 19 are sufficiently smaller than D. Also, assume that the impurity concentration in the semiconductor region between the N-type semiconductor region 10 and the P-type semiconductor region 19 is sufficiently lower than the impurity concentrations of the N-type semiconductor region 10 and the P-type semiconductor region 19.

[0029] Then, let the built-in potential formed between the N-type semiconductor region 10 and the P-type semiconductor region 19 be Vbi, and the dielectric constant of the semiconductor be ε. Also, let the amount of impurities (number of acceptor ions) per unit area of the P-type semiconductor region 19 be A.

[0030] From the above, if the P-type semiconductor region 19 is not depleted, the capacitance C2 formed by the N-type semiconductor region 10 and the P-type semiconductor region 19 is C2 = ε / D. When the voltage between the N-type semiconductor region 10 and the P-type semiconductor 19 changes by ΔV, the induced charge ΔQ is given by the following Equation 1. ΔQ = ε / D × ΔV (Equation 1) When the transfer electrode 4 is off, the charge amount of the P-type semiconductor 19 is ε / D × (Vbi + V1) from Equation 1. At this time, more than half of the impurities in the P-type semiconductor region are neutralized. That is, if there are holes of 1 / 2 × A or more in the P-type semiconductor region 19, 1 / 2 × Qe × A >= ε / D × (Vbi + V1) holds.

[0031] Also, assuming that the P-type semiconductor region 19 is completely depleted by the time the potential of the transfer electrode 4 changes from VL to VH, and making C01 / (C01 + C2) about 0.9, with respect to the charge amount of C2, Qe × A <= ε / D × (Vbi + V1 + 0.9 × V0) holds.

[0032] Summarizing the above, the following Equation 2 is obtained. 2 × ε / D / Qe × (Vbi + V1) <= A <= ε / D / Qe × (Vbi + V1 + 0.9 × V0) (Equation 2) The semiconductor is silicon, and D is preferably 0.3 to 0.5 microns. Vbi is approximately 0.7 V. V1 is preferably 1.4 to 2.4 V, and V0 is preferably 4 V to 6.5 V. In this range, the upper and lower limits of A, i.e., the amount of acceptor ions to be implanted to form the P-type semiconductor 19, are calculated from Equation 2, and A is 5.5×10 11 / cm 2 That's it, 1.2 x 10 12 / cm 2 I found that the following would be good:

[0033] If this condition is violated, it becomes difficult to suppress false signals and prevent signal extinction at the same time. However, the value of A means the effective amount, and when donor ions are present in the position of the P-type semiconductor region 19 in an amount B, the effective amount of acceptor ions is the amount obtained by subtracting B from the amount of acceptor ions introduced to form the P-type semiconductor 19. Therefore, the effective amount of doped impurities per unit area (effective amount of dopant ions) is 5.5×10 11 / cm 2 That's it, 1.2 x 10 12 / cm 2 The result is as follows.

[0034] The P-type semiconductor region 20, like the P-type semiconductor region 19, has the role of preventing false signals from being mixed into the memory section 3, but also has the role of forming a PN junction capacitance with the N-type semiconductor region 16 to increase the saturation signal amount of the memory section 3. Therefore, the P-type semiconductor region 20 is formed independently of the P-type semiconductor region 19 and can be electrically connected to the P-type semiconductor region 19, and the effective amount of dopant ions for forming the P-type semiconductor region 20 may be greater than the above amount A. Since the N-type semiconductor region 16 is formed to a position deeper than the N-type semiconductor region 10, the depth of the P-type semiconductor region 20 may be formed at a position equal to or deeper than the P-type semiconductor region 19.

[0035] In this example, when the potential of the transfer electrode 4 is VH, the P-type semiconductor region 19 is completely depleted, but at such a time, the P-type semiconductor region loses its potential barrier function, and some of the signal charge generated in PD2 may move directly to the N-type semiconductor region 10. However, since the time when the potential of the transfer electrode 4 becomes VH is during the signal transfer operation from PD2 to the memory unit 3, the direct movement of the signal charge during this operation is not the mixing of a false signal but is a normal operation and does not pose any problem.

[0036] On the other hand, when a signal is transferred from PD2 to memory 3, as shown by potential 3 in Fig. 3, when the potential of transfer electrode 4 rises, the potential of N-type semiconductor region 10 also rises significantly. Therefore, a large potential difference is generated between N-type semiconductor region 10 and N-type semiconductor region 15, which is the signal storage layer of PD2, and the charge signal (electrons) stored in N-type semiconductor region 15 is promptly transferred to N-type semiconductor region 10. When the potential of transfer electrode 4 returns to VL, the signal charge in N-type semiconductor region 10 moves to N-type semiconductor region 16, where the signal is held. Since it is easy to transfer signals from PD2 to memory section 3 in this way, the saturation signal amount of PD section 2 can be increased.

[0037] The photoelectric conversion device structure described above makes it possible to effectively suppress the intrusion of spurious signals into the memory section, reduce signal loss, and improve the saturation signal amount of PD2, compared to the conventional art.

[0038] [Modification of the first embodiment] The photoelectric conversion device 1 according to the modified example of the first embodiment will be described with reference to a plan view of the semiconductor substrate. FIG. 6 shows a cross-sectional structure between the transfer electrode 4 and the N-type semiconductor region 10 formed in the semiconductor substrate below the transfer electrode 4. The transfer electrode 4 and the transfer electrode 6 are close to each other, and the P-type semiconductor region 14 is formed at the semiconductor interface between them. The distance between the N-type semiconductor region 15 and the N-type semiconductor region 16 is larger than the distance between the N-type semiconductor region 16 and the N-type semiconductor region 5. In this example, the N-type semiconductor region 10 itself functions as a memory section, and the role of the N-type semiconductor region 16 is more important as a path for signal charges from the N-type semiconductor region 10 to the transfer electrode 6 than as a memory section serving as a charge storage section. Since the N-type semiconductor region 16 has a small area and plays a small role as a memory, the P-type semiconductor region 20 below the N-type semiconductor region 16 may have a low concentration and may be disposed at a deeper position than the P-type semiconductor region 19, and in some cases may be at the same depth as the P-type semiconductor region 19. In addition, the P-type semiconductor region 13 may be electrically connected to the P-type semiconductor region 19 via the P-type semiconductor regions 20, 21, and 22 disposed between the P-type semiconductor region 13 and the P-type semiconductor region 19.

[0039] As in the first embodiment, the P-type semiconductor region 20 is electrically connected to the P-type semiconductor region 19, and the P-type semiconductor region 20 is located at a position equal to or deeper than the P-type semiconductor region 19. However, in this example, the relationship of the impurity concentration between the P-type semiconductor region 19 and the P-type semiconductor region 20 is not particularly specified. Therefore, if the P-type semiconductor region 20 and the P-type semiconductor region 19 are the same depth and have the same impurity concentration, they can be combined into one P-type semiconductor region. For example, if the N-type semiconductor region 16 is arranged very shallow, the P-type semiconductor region 20 and the P-type semiconductor region 19 can be made into one semiconductor region. Even in the case of a structure in which the P-type semiconductor region 14 and the N-type semiconductor region 16 are not present and the N-type semiconductor region 10 extends to directly below the transfer electrode 6, the P-type semiconductor region 20 and the P-type semiconductor region 19 can be made into one semiconductor region.

[0040] 6, the P-type semiconductor region 20 extends long and serves as a part of the P-type semiconductor region for separating the PDs between the photoelectric conversion devices similar to 21 and 22, but it may not extend in this way and may only partially overlap the P-type semiconductor region 19 in a planar view. Alternatively, the P-type semiconductor region 20 may be formed so as to cover the entire surface of the photoelectric conversion device, or at least the N-type semiconductor region 15 in a planar view, and may serve to form a PN junction capacitance with the N-type semiconductor region 15 to improve the saturation of PD2.

[0041] This modification can increase the saturation signal amount of the memory per unit area compared to the first embodiment. This is because the MOS capacitance between the transfer electrode 4 and the N-type diffusion layer 10 is generally much larger than the PN junction capacitance formed by the P-type semiconductor region 14, the N-type semiconductor region 16, and the P-type semiconductor region 20. In addition, when the potential of the transfer electrode 4 is VH, the N-type semiconductor region 10 can maintain its embedding property. Therefore, according to this modification, it is possible to effectively prevent the intrusion of false signals into the memory section and also to prevent signal disappearance compared to the conventional method, and further to improve the saturation signal amount of the PD and the saturation signal amount of the memory.

[0042] [Solid-state imaging device] An example in which the above-described photoelectric conversion device is applied to a solid-state imaging device 100 will be described with reference to Fig. 7. The solid-state imaging device 100 includes, for example, a pixel section 101 in which a plurality of pixels are arranged in a matrix, a vertical scanning circuit 102 that controls the pixels in the rows of the pixel section 101, a signal processing circuit 103 that reads out and processes signals, and a horizontal scanning circuit 104 that controls the circuits provided for each column. Each pixel includes the photoelectric conversion device described in the first embodiment and the modified example. The solid-state imaging device may also include a control circuit that generates control signals and timing signals for controlling the solid-state imaging device.

[0043] Typically, the vertical scanning circuit 102 selects a specific row of pixels and performs control to read out signals from the pixels in that row. Under the control of the vertical scanning circuit 102, signals from the PD unit 2 of the photoelectric conversion device are output to vertical signal lines (not shown). The horizontal scanning circuit 104 controls the signal processing circuit 103 to output the signals read out row by row to the outside. The signal processing circuit 103 may include an amplifier circuit that amplifies signals from the pixels, a circuit that reduces noise, and an A / D converter.

[0044] The operation of the global shutter is performed, for example, as follows. At a predetermined timing under the control of the vertical scanning circuit 102, the PD section 2 included in the pixel of the pixel section 101 starts accumulating signal charges according to the incident light. Next, under the control of the vertical scanning circuit 102, the potentials of the transfer electrodes 4 of the photoelectric conversion device are all set to VH, and the signal charges accumulated in the PD section 2 are transferred to the semiconductor region that accumulates the signal charges at the same timing. In this way, the signal charges accumulated in the PD section 2 can be read out from the PD section 2 at the same timing. Next, the vertical scanning circuit 102 controls the transfer electrodes 6 for each row, and the signal charges are transferred to the floating diffusion region 5. The signal from the floating diffusion region 5 is amplified by the amplifier circuit of the MOS transistor section 9, read out to the vertical signal line, and input to the signal processing circuit 103. The signal processing circuit 103 amplifies the signal, for example, performs A / D conversion, and outputs the signal to the outside under the control of the horizontal scanning circuit 104.

[0045] The invention is not limited to the above-described embodiments, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, the following claims are appended to apprise the public of the scope of the invention. [Explanation of symbols]

[0046] 2: photodiode 3: memory section 4: transfer electrode 5: floating diffusion region 6: transfer electrode 11: element isolation section 12: first conductive type semiconductor region 13: second conductive type semiconductor region 14, 14': second conductive type semiconductor region 15, 16: first conductive type semiconductor region 17-22: second conductive type semiconductor region

Claims

1. a first semiconductor region of a first conductivity type disposed between the first surface and the second surface; a second semiconductor region of a first conductivity type disposed between the first surface and the second surface and configured to accumulate signal charges generated by incident light; a third semiconductor region of a first conductivity type disposed between the first surface and the second surface; a fourth semiconductor region of a first conductivity type disposed between the first surface and the second surface and in contact with the third semiconductor region; a fifth semiconductor region of a second conductivity type disposed between the fourth semiconductor region and the first surface; a first transfer electrode disposed on the first surface for forming a first channel in the first semiconductor region for transferring the signal charges stored in the second semiconductor region to the third semiconductor region; a sixth semiconductor region of a second conductivity type disposed between the third semiconductor region and the second surface; a seventh semiconductor region of a second conductivity type disposed between the fourth semiconductor region and the second surface; the third semiconductor region overlaps at least a portion of the first transfer electrode and at least a portion of the sixth semiconductor region in a plan view; the sixth semiconductor region and the seventh semiconductor region are electrically connected to each other; an effective amount of dopant ions per unit area for forming the seventh semiconductor region is greater than an effective amount of dopant ions per unit area for forming the sixth semiconductor region; The seventh semiconductor region is disposed at a position that is the same depth as or deeper than the sixth semiconductor region from the first surface; A photoelectric conversion device, wherein, in a state in which the first channel is formed, a potential of the third semiconductor region is lower than a potential of the first transfer electrode.

2. a first semiconductor region of a first conductivity type disposed between the first surface and the second surface; a second semiconductor region of a first conductivity type disposed between the first surface and the second surface and configured to accumulate signal charges generated by incident light; a third semiconductor region of a first conductivity type disposed between the first surface and the second surface; a fourth semiconductor region of a first conductivity type disposed between the first surface and the second surface and in contact with the third semiconductor region; a fifth semiconductor region of a second conductivity type disposed between the fourth semiconductor region and the first surface; a first transfer electrode disposed on the first surface for forming a first channel in the first semiconductor region for transferring the signal charges stored in the second semiconductor region to the third semiconductor region; a sixth semiconductor region of a second conductivity type disposed between the third semiconductor region and the second surface; a seventh semiconductor region of a second conductivity type disposed between the fourth semiconductor region and the second surface; the third semiconductor region overlaps at least a portion of the first transfer electrode and at least a portion of the sixth semiconductor region in a plan view; the sixth semiconductor region and the seventh semiconductor region are electrically connected to each other; an effective amount of dopant ions per unit area for forming the seventh semiconductor region is greater than an effective amount of dopant ions per unit area for forming the sixth semiconductor region; The seventh semiconductor region is disposed at a position that is the same depth as or deeper than the sixth semiconductor region from the first surface; a potential change amount of the first transfer electrode when the first channel is formed is V0, a ​​distance between the third semiconductor region and the sixth semiconductor region is D, a built-in potential between the third semiconductor region and the sixth semiconductor region is Vbi, a dielectric constant of a semiconductor is ε, an electronic charge is Qe, and a potential difference between a minimum value of the potential of the third semiconductor region when the first channel is not formed and a semiconductor interface portion or a neutral region of the sixth semiconductor region is V1, wherein an impurity amount A per unit area of ​​the sixth semiconductor region is 2×ε / D / Qe×(Vbi+V1)≦A≦ε / D / Qe×(Vbi+V1+0.9×V0).

3. The photoelectric conversion device according to claim 1 , wherein the seventh semiconductor region at least partially overlaps with the third semiconductor region in a plan view.

4. a first semiconductor region of a first conductivity type disposed between the first surface and the second surface; a second semiconductor region of a first conductivity type disposed between the first surface and the second surface and configured to accumulate signal charges generated by incident light; a third semiconductor region of a first conductivity type disposed between the first surface and the second surface; a fourth semiconductor region of a first conductivity type disposed between the first surface and the second surface and in contact with the third semiconductor region; a fifth semiconductor region of a second conductivity type disposed between the fourth semiconductor region and the first surface; a first transfer electrode disposed on the first surface for forming a first channel in the first semiconductor region for transferring the signal charges stored in the second semiconductor region to the third semiconductor region; a sixth semiconductor region of a second conductivity type disposed between the third semiconductor region and the second surface; an eighth semiconductor region of a second conductivity type disposed between the second semiconductor region, the sixth semiconductor region, and the second surface; the fourth semiconductor region and the sixth semiconductor region do not overlap in a plan view, the sixth semiconductor region and the eighth semiconductor region are electrically conductive, A photoelectric conversion device, wherein, in a state in which the first channel is formed, a potential of the third semiconductor region is lower than a potential of the first transfer electrode.

5. a first semiconductor region of a first conductivity type disposed between the first surface and the second surface; a second semiconductor region of a first conductivity type disposed between the first surface and the second surface and configured to accumulate signal charges generated by incident light; a third semiconductor region of a first conductivity type disposed between the first surface and the second surface; a fourth semiconductor region of a first conductivity type disposed between the first surface and the second surface and in contact with the third semiconductor region; a fifth semiconductor region of a second conductivity type disposed between the fourth semiconductor region and the first surface; a first transfer electrode disposed on the first surface for forming a first channel in the first semiconductor region for transferring the signal charges stored in the second semiconductor region to the third semiconductor region; a sixth semiconductor region of a second conductivity type disposed between the third semiconductor region and the second surface; an eighth semiconductor region of a second conductivity type disposed between the second semiconductor region, the sixth semiconductor region, and the second surface; the fourth semiconductor region and the sixth semiconductor region do not overlap in a plan view, the sixth semiconductor region and the eighth semiconductor region are electrically conductive, a potential change amount of the first transfer electrode when the first channel is formed is V0, a ​​distance between the third semiconductor region and the sixth semiconductor region is D, a built-in potential between the third semiconductor region and the sixth semiconductor region is Vbi, a dielectric constant of a semiconductor is ε, an electronic charge is Qe, and a potential difference between a minimum value of the potential of the third semiconductor region when the first channel is not formed and a semiconductor interface portion or a neutral region of the sixth semiconductor region is V1, wherein an impurity amount A per unit area of ​​the sixth semiconductor region is 2×ε / D / Qe×(Vbi+V1)≦A≦ε / D / Qe×(Vbi+V1+0.9×V0).

6. The photoelectric conversion device according to claim 4 , wherein the eighth semiconductor region overlaps with the second semiconductor region in a plan view.

7. The effective amount of dopant ions per unit area for forming the sixth semiconductor region is 5.5×10 １１ / cm ２ Greater than or equal to 1.2 x 10 １２ / cm ２ 7. The photoelectric conversion device according to claim 1, wherein:

8. The photoelectric conversion device according to claim 1 , further comprising a light shielding member disposed on the first surface and covering the fourth semiconductor region.

9. a floating diffusion region of a first conductivity type; The photoelectric conversion device according to any one of claims 1 to 8, further comprising a second transfer electrode arranged on the first surface for forming a second channel in the first semiconductor region for transferring the signal charge from the fourth semiconductor region to the floating diffusion region.

10. a first semiconductor region of a first conductivity type disposed between the first surface and the second surface; a second semiconductor region of a first conductivity type disposed between the first surface and the second surface and configured to accumulate signal charges generated by incident light; a third semiconductor region of a first conductivity type disposed between the first surface and the second surface; a first transfer electrode disposed on the first surface for forming a first channel in the first semiconductor region for transferring the signal charges stored in the second semiconductor region to the third semiconductor region; a sixth semiconductor region of a second conductivity type disposed between the third semiconductor region and the second surface and overlapping at least a portion of the third semiconductor region; the third semiconductor region and the first transfer electrode at least partially overlap each other in a plan view; The effective dopant ion amount per unit area of ​​the sixth semiconductor region is 5.5×10 １１ / cm ２ Greater than or equal to 1.2 x 10 １２ / cm ２ is as follows: When each semiconductor is silicon, the first conductivity type is an N-type semiconductor, and the second conductivity type is a P-type semiconductor, the distance between the third semiconductor region and the sixth semiconductor region is 0.3 microns or more and 0.5 microns or less, the sum of a built-in potential between the third semiconductor region and the sixth semiconductor region and a potential difference between a minimum potential value of the third semiconductor region when the first channel is not formed and a semiconductor interface portion or a neutral region of the sixth semiconductor region is 2.1 V or more and 3.1 V or less, and an amount of potential change of the first transfer electrode when the first channel is formed is 4.0 V or more and 6.5 V or less. A photoelectric conversion device comprising:

11. a ninth semiconductor region of the second conductivity type; the ninth semiconductor region overlaps with at least a portion of the first transfer electrode in a plan view, and does not overlap with the third semiconductor region; 11. The photoelectric conversion device according to claim 1,

12. A pixel portion in which pixels each having the photoelectric conversion device according to claim 1 are arranged in a matrix; a vertical scanning circuit for controlling the pixel unit to read out signals from the pixels; and a processing circuit that processes signals read out from the pixels.

Images