Image sensor structure for reducing crosstalk

Abstract

To provide an image sensor structure in which optical noise is better blocked in the structure and crosstalk between large photodiodes and small photodiodes is reduced.SOLUTION: An image sensor 200 includes: a first photodiode 208S disposed between a second photodiode 208L and a third photodiode 208L along a direction; a first deep trench isolation (DTI) feature 240D disposed around the first photodiode; and a second DTI feature 240 disposed along the second photodiode and a third photodiode side wall. A depth of the first DTI feature is greater than a depth of the second DTI feature. A quantum efficiency of the second photodiode is smaller than a quantum efficiency of the first photodiode.SELECTED DRAWING: Figure 17

Description

[Background technology]

[0001] The semiconductor integrated circuit (IC) industry is experiencing exponential growth. Technological advances in IC materials and designs have produced generations of ICs, with each generation having smaller and more complex circuits than the previous generation. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This miniaturization process generally provides the benefits of increased production efficiency and associated cost reduction. Such miniaturization has also increased the complexity of IC processing and manufacturing. [Prior art documents] [Patent documents]

[0002] Patent Document 1: U.S. Patent Publication No. 10,770,502 B2 Patent Document 2: U.S. Patent Publication No. 10,475,847 B2 Patent Document 3: U.S. Patent Publication No. 11,172,142 B2 Summary of the Invention [Problem to be solved by the invention]

[0003] Image sensors, such as complementary metal-oxide semiconductor (CMOS) image sensors (CIS), are frequently found in modern consumer electronics. For example, CIS are heavily used in the automotive industry to realize automation and sensing functions. To improve image detection sensitivity, photodiodes of different sizes are implemented in arrays. Different sized photodiodes have different quantum efficiency (QE) levels, so crosstalk from a large photodiode introduces significant noise into the adjacent smaller photodiodes. Thus, while existing image sensor structures are generally adequate for their intended purposes, they are not satisfactory in all respects. [Means for solving the problem]

[0004] The present invention provides an image sensor in some embodiments, the image sensor includes a first photodiode disposed between a second photodiode and a third photodiode along one direction, a first deep trench isolation (DTI) feature disposed between the first photodiode and the second photodiode, and a second DTI feature disposed between the first photodiode and the third photodiode, the depth of the first DTI feature being greater than the depth of the second DTI feature, and the quantum efficiency of the second photodiode being less than the quantum efficiency of the first photodiode.

[0005] The present invention also provides an image sensor in some embodiments, the image sensor including a first photodiode, a second photodiode adjacent to the first photodiode along one direction, a first passivation layer disposed above the first and second photodiodes, a metal grid disposed above the first passivation layer, and a metal film embedded in the first passivation layer and disposed directly above the first photodiode but not extending above the second photodiode, the quantum efficiency of the first photodiode being different from the quantum efficiency of the second photodiode.

[0006] The present invention further provides a method of forming an image sensor in some embodiments, the method of forming the image sensor includes receiving a substrate including a first photodiode region disposed between a second photodiode region and a third photodiode region along one direction, a first transistor disposed above the first photodiode region, a second transistor disposed above the second photodiode region, a third transistor disposed above the third photodiode region, and a first dielectric layer above the first transistor, the second transistor, and the third transistor. The method further includes forming an annular trench in the first dielectric layer such that the annular trench extends completely around the second transistor, and depositing a first metal fill layer in the annular trench to form a first metal structure. A first portion of the first metal structure is vertically aligned with an interface between the first photodiode region and the second photodiode region, and a second portion of the first metal structure is vertically aligned with an interface between the second photodiode region and the third photodiode region. Effect of the Invention

[0007] SUMMARY OF THE PRESENTLY PREFERRED EMBODIMENTS The present invention provides an image sensor structure that provides better isolation of optical noise and reduced crosstalk between large photodiodes and small photodiodes. [Brief description of the drawings]

[0008] Aspects of the present invention are best understood by reading the following detailed description in conjunction with the accompanying drawings. It is emphasized that, according to standard practice in the industry, various features have not been drawn to scale. In fact, dimensions of various features illustrated in the accompanying drawings may be arbitrarily increased or reduced for clarity of illustration. It is also emphasized that the accompanying drawings depict only typical embodiments of the present invention, and should not be considered as limiting in scope, as the present invention may be applicable to other embodiments as well.

[0009] [Figure 1]FIG. 1 is a flow diagram illustrating a method for manufacturing an image sensor device according to various aspects of the present invention. [Diagram 2] 2-20 depict fragmentary cross-sectional or top views of a workpiece undergoing various stages of manufacture according to the method of FIG. 1, according to various aspects of the present invention. [Diagram 3] 2-20 depict fragmentary cross-sectional or top views of a workpiece undergoing various stages of manufacture according to the method of FIG. 1, according to various aspects of the present invention. [Figure 4] 2-20 depict fragmentary cross-sectional or top views of a workpiece undergoing various stages of manufacture according to the method of FIG. 1, according to various aspects of the present invention. [Diagram 5] 2-20 depict fragmentary cross-sectional or top views of a workpiece undergoing various stages of manufacture according to the method of FIG. 1, according to various aspects of the present invention. [Figure 6] 2-20 depict fragmentary cross-sectional or top views of a workpiece undergoing various stages of manufacture according to the method of FIG. 1, according to various aspects of the present invention. [Figure 7] 2-20 depict fragmentary cross-sectional or top views of a workpiece undergoing various stages of manufacture according to the method of FIG. 1, according to various aspects of the present invention. [Figure 8] 2-20 depict fragmentary cross-sectional or top views of a workpiece undergoing various stages of manufacture according to the method of FIG. 1, according to various aspects of the present invention. [Figure 9] 2-20 depict fragmentary cross-sectional or top views of a workpiece undergoing various stages of manufacture according to the method of FIG. 1, according to various aspects of the present invention. [Figure 10] 2-20 depict fragmentary cross-sectional or top views of a workpiece undergoing various stages of manufacture according to the method of FIG. 1, according to various aspects of the present invention. [Figure 11] 2-20 depict fragmentary cross-sectional or top views of a workpiece undergoing various stages of manufacture according to the method of FIG. 1, according to various aspects of the present invention. [Figure 12] 2-20 depict fragmentary cross-sectional or top views of a workpiece undergoing various stages of manufacture according to the method of FIG. 1, according to various aspects of the present invention. [Figure 13] 2-20 depict fragmentary cross-sectional or top views of a workpiece undergoing various stages of manufacture according to the method of FIG. 1, according to various aspects of the present invention. [Figure 14] 2-20 depict fragmentary cross-sectional or top views of a workpiece undergoing various stages of manufacture according to the method of FIG. 1, according to various aspects of the present invention. [Figure 15] 2-20 depict fragmentary cross-sectional or top views of a workpiece undergoing various stages of manufacture according to the method of FIG. 1, according to various aspects of the present invention. [Figure 16] 2-20 depict fragmentary cross-sectional or top views of a workpiece undergoing various stages of manufacture according to the method of FIG. 1, according to various aspects of the present invention. [Figure 17] 2-20 depict fragmentary cross-sectional or top views of a workpiece undergoing various stages of manufacture according to the method of FIG. 1, according to various aspects of the present invention. [Figure 18] 2-20 depict fragmentary cross-sectional or top views of a workpiece undergoing various stages of manufacture according to the method of FIG. 1, according to various aspects of the present invention. [Figure 19] 2-20 depict fragmentary cross-sectional or top views of a workpiece undergoing various stages of manufacture according to the method of FIG. 1, according to various aspects of the present invention. [Figure 20] 2-20 depict fragmentary cross-sectional or top views of a workpiece undergoing various stages of manufacture according to the method of FIG. 1, according to various aspects of the present invention. [Figure 21] FIG. 21 illustrates generally how various features of an image sensor of the present invention, according to various aspects of the present invention, operate to reduce crosstalk. [Figure 22] 22 and 23 depict schematic top views of openings for metal absorbing features for small photodiode areas according to various aspects of the present invention. [Diagram 23] 22 and 23 depict schematic top views of openings for metal absorbing features for small photodiode areas according to various aspects of the present invention. [Figure 24]24-27 depict fragmentary top views of image sensors implemented with extended deep trench isolation (DTI) features around a small photodiode in accordance with various embodiments of the present invention. [Diagram 25] 24-27 depict fragmentary top views of image sensors implemented with extended deep trench isolation (DTI) features around a small photodiode in accordance with various embodiments of the present invention. [Figure 26] 24-27 depict fragmentary top views of image sensors implemented with extended deep trench isolation (DTI) features around a small photodiode in accordance with various embodiments of the present invention. [Figure 27] 24-27 depict fragmentary top views of image sensors implemented with extended deep trench isolation (DTI) features around a small photodiode in accordance with various embodiments of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] The following embodiments provide many different embodiments or examples for implementing different features of the provided subject matter. To simplify the present invention, specific examples of elements and arrangements are described below. Of course, these are illustrative and not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include an embodiment in which the first and second features are formed in direct contact, and may also be an embodiment in which an additional feature is formed between the first and second features such that the first and second features are not in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various embodiments. This repetition is for the purpose of simplicity and clarity, and does not itself dictate a relationship between the various embodiments and / or configurations referred to.

[0011] Additionally, spatially relative terms such as "below," "lower," "upper," "top," and the like may be used to facilitate the description to explain the relationship of one element or feature depicted in the figures to another element or feature. The spatially relative terms are intended to encompass different orientations of the device during use or operation in addition to the orientation depicted. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0012] Furthermore, when a number or a range of numbers is described using "about," "approximately," or the like, the term is intended to encompass the numerical values ​​within a reasonable range that takes into account variations that inherently occur during manufacturing, as understood by those of ordinary skill in the art. For example, the number or range of numbers encompasses a reasonable range that includes the stated value, such as plus or minus 10% of the stated number, based on known manufacturing tolerances associated with the manufacture of a feature having the characteristic associated with the number. For example, a material layer having a thickness of "about 5 nm" encompasses a dimensional range of 4.25 nm to 5.75 nm, when the manufacturing tolerances associated with the deposition of the material layer are known to those of ordinary skill in the art to be plus or minus 15%. Furthermore, the present invention may repeat reference numbers and / or letters in various embodiments. This repetition is for purposes of simplicity and clarity, and does not in itself dictate a relationship between the various embodiments and / or configurations being described.

[0013] Complementary metal oxide semiconductor (CMOS) image sensors (CIS) have become popular in recent years. For example, CIS are used in the automotive industry to achieve automation and sensing functions. In performing these functions, CIS provide machine vision that supplements or replaces human vision. One challenge facing the industry is the flickering of light emitting diodes (LEDs), which can be very annoying for machine vision. One solution is split pixel technology, which implements both large and small photodiodes. The large photodiodes have a higher quantum efficiency (QE) than the small photodiodes. The large photodiodes have a relatively large size or different implanted dopants to have a relatively high QE. That is, the large photodiodes are not necessarily larger than the small photodiodes. The large photodiodes are configured to capture the scene with a short exposure time, and the small photodiodes are configured to capture the LED signal with a long exposure time. When split pixel technology or similar technology is employed, the large photodiodes and the small photodiodes are placed next to each other. Light from an adjacent larger photodiode can cause noise in the smaller photodiode. Light from the larger photodiode can cross into the smaller photodiode through gaps in deep trench isolation (DTI) features, reflections from metal features in metallization processes, or through microlenses and color filters.

[0014] The present invention provides an image sensor structure that reduces crosstalk between large and small photodiodes. In one aspect, the image sensor structure of the present invention implements relatively deep or extended deep trench isolation (DTI) features around the small photodiode to better isolate optical noise from the adjacent large photodiode. In another aspect, the image sensor structure of the present invention includes a metal film embedded in a passivation structure above the small photodiode to isolate optical noise from the overlying microlenses and color filters. In yet another aspect, the image sensor structure of the present invention includes a contact structure in the back-end interconnect (BEOL) structure to isolate optical noise reflected from the metal features. Various features of the present invention function alone or in combination to reduce crosstalk to the small photodiode.

[0015] Various aspects of the present invention will now be described in more detail with reference to the drawings. In this regard, FIG. 1 is a flow diagram illustrating a method 100 for forming an image sensor on a workpiece 200 according to an embodiment of the present invention. The method 100 is merely exemplary and is not intended to limit the present invention to that explicitly depicted in the method 100. Additional steps may be provided before, during, and after the method 100, and some steps described may be replaced, eliminated, or moved for additional embodiments of the method. For the sake of brevity, not all steps will be described in detail herein. The method 100 will now be described in conjunction with FIGS. 2-19, which are fragmentary cross-sectional views of the workpiece 200 at various stages of fabrication according to an embodiment of the method 100. Because the workpiece 200 is fabricated into an image sensor or image sensor structure at the end of the fabrication process, the workpiece 200 may also be referred to as an image sensor 200 or an image sensor structure 200 depending on the context. Additionally, throughout this application, like reference numerals denote like features unless otherwise specified. The X, Y, and Z directions are used consistently in FIGS. 2-16 and are mutually orthogonal.

[0016] 1 and 2, the method 100 includes block 102, receiving a workpiece 200 including a small photodiode (SPD) region 202S and a large photodiode (LPD) region 202L. As shown in FIG. 2, the workpiece 200 includes a substrate 202 divided into a small photodiode (SPD) region 202S and a large photodiode (LPD) region 202L. The workpiece 200 further includes an LPD transistor 208L fabricated above the LPD region 202L and an SPD transistor 208S fabricated above the SPD region 202S. The LPD transistor 208L and the SPD transistor 208S are separated from each other by an isolation feature 204. The workpiece 200 further includes a first etch stop layer 206 above the isolation feature 204 and a first interlayer dielectric (ILD) layer 210. The substrate 202 may be a bulk silicon (Si) substrate. Alternatively, the substrate 202 may be an elemental semiconductor such as germanium (Ge), a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb), an alloy semiconductor such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP), or a combination thereof.

[0017] To form the SPD region 202S and the LPD region 202L in the substrate 202, the substrate 202 may include various doped regions (not shown), such as p-type doped regions, n-type doped regions, or combinations thereof. In one embodiment, the substrate 202 may include p-type dopants, such as boron (B), boron difluoride (BF2), or other p-type dopants, and n-type dopants, such as phosphorus (P), arsenic (As), or other n-type dopants. In this embodiment, the substrate 202 may be a commercially available silicon substrate with p-type and n-type dopants introduced into specific regions of the substrate 202 to form image sensors, also referred to as photodiodes.

[0018] Each of the SPD transistor 208S and the LPD transistor 208L includes a source, a drain, a channel region between the source and drain, and a gate structure above the channel region. It is noted that the SPD transistor 208S and the LPD transistor 208L shown in FIG. 2 may represent transistors of different configurations. For example, they may be planar transistors, fin field effect transistors (FinFETs), multi-bridge channel (MBC) transistors, gate-all-around (GAA) transistors, nanowire transistors, nanosheet transistors, transistors with nanostructures, or other multi-gate transistors in which the gate structure engages multiple surfaces of the channel region. The active areas of the SPD transistor 208S and the LPD transistor 208L are separated from each other by an isolation feature 204, which may be a shallow trench isolation (STI) feature. Depending on the configuration of the SPD transistor 208S and the LPD transistor 208L, the active areas may be embedded with the isolation feature 204. Alternatively, depending on the configuration of the SPD transistor 208S and the LPD transistor 208L, the active areas may have a sheet-like or fin-like shape. Alternatively, depending on the configuration of the SPD transistor 208S and the LPD transistor 208L, the active areas may include multiple channel members vertically spaced apart from one another. The isolation structure 204 may include silicon oxide, silicon nitride, silicon oxynitride, fluorine doped silicate glass (FSG), low-k dielectrics, combinations thereof, and / or other suitable materials. The first etch stop layer 206 may include silicon nitride or silicon oxynitride. The first ILD layer 210 may include materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and / or other suitable dielectric materials.

[0019] 1 and 3, the method 100 includes block 104, where at least one opening 212 is formed in a first ILD layer 210 above a workpiece 200. Photolithography and etching processes are used to form the at least one opening 212 at block 104. In one exemplary process, a photoresist layer is deposited above the workpiece 200. The photoresist layer undergoes a pre-exposure bake process, exposure to radiation reflected from or transmitted through a photomask, a post-exposure bake process, and a development process to form a patterned photoresist layer. The patterned photoresist layer is then applied as an etch mask to etch at least one opening 212 in the first ILD layer 210. Etching the first ILD layer 210 may be performed using a dry etch process that includes the use of an inert gas (e.g., Ar), a fluorine-containing gas (e.g., CF4, C2F6, SF6, or NF3), other suitable gases and / or plasmas, and / or combinations thereof. The at least one opening 212 extends or is positioned to extend around the vertical projection area of ​​the SPD region 202S. The at least one opening 212 may be of different shapes and configurations. In some embodiments depicted in FIG. 18, the at least one opening 212 may be a single continuous opening that extends completely around the vertical projection area of ​​the SPD region 202S. The single continuous opening 212 in FIG. 22 resembles a trench having a trench width between about 0.05 μm and about 0.2 μm. The single continuous opening 212 can be referred to as annular because it extends completely around the vertical projection area of ​​the SPD region 202S. In some other embodiments depicted in FIG. 23, the at least one opening 212 in FIG. 3 includes a plurality of separate openings 212S positioned along the edge of the vertical projection area of ​​the SPD region 202S. The plurality of separate openings 212S may be spaced apart from one another by a predetermined interval and are not in fluid communication with one another. Each of the plurality of separated openings 212S may be substantially circular and may have a diameter between about 0.05 μm and about 0.2 μm. The spacing between adjacent ones of the separated openings 212S may be between about 0.11 μm and about 0.5 μm.3, in the XY plane, the at least one opening 212 surrounds the SPD transistor 208S. Note that along the Z direction, the at least one opening 212 is substantially aligned with the boundary between the SPD region 202S and the adjacent LPD region 202L. In some embodiments, the at least one opening 212 extends through the first ILD layer 210 and the first etch stop layer 206. In some embodiments, the at least one opening 212 may extend partially into the isolation feature 204.

[0020] 1, 4, and 5, the method 100 includes a block 106 in which a metal absorber feature 215 is provided in the at least one opening 212. To form the metal absorber feature 215, a metal fill layer 214 is first deposited above the workpiece 200 and in the at least one opening 212 as shown in FIG. 4, and then the excess metal fill layer 214 above the dielectric layer 210 is removed by a planarization process, such as a chemical mechanical polishing (CMP) process, as shown in FIG. 5. The metal fill layer 214 may include copper (Cu), aluminum copper (AlCu), tungsten (W), or a suitable metal or alloy. The metal fill layer 214 may be deposited using physical vapor deposition (PVD) or electrolytic plating. When the metal fill layer 214 is formed using electrolytic plating, a seed layer is first deposited above the at least one opening 212 using CVD. After the deposition of the seed layer, the metal fill layer 214 is deposited using electrolytic plating. The seed layer may include copper (Cu) or titanium (Ti). In some embodiments illustrated in FIG. 4, a metal fill layer 214 is deposited on the top surface of the first ILD layer 210 as well as filling the at least one opening 212. The workpiece 200 is then planarized to remove excess metal fill layer 214 to form a metal absorber feature 215. Since the at least one opening 212 may be a single continuous opening 212 (illustrated in FIG. 22) or multiple separate openings 212S (illustrated in FIG. 23) in different embodiments, the metal absorber feature 215 may be a single continuous metal structure or an array of columnar separate metal absorber features.

[0021] 1 and 6, the method 100 includes block 108, in which a protective metal layer 216 is formed directly above the SPD region 202S. To form the protective metal layer 216, a second etch stop layer 218 and a second ILD layer 220 are sequentially deposited above the first ILD layer 210. The second etch stop layer 218 is similar to the first etch stop layer 206 in composition and formation process. The second ILD layer 220 is similar to the first ILD layer 210 in composition and formation process. An opening for the protective metal layer 216 is formed through the second etch stop layer 218 and the second ILD layer 220. A metal fill layer is then deposited in the opening. After the excess metal fill layer is removed by a planarization process, the protective metal layer 216 is formed on the second etch stop layer 218 and the second ILD layer 220. The metal fill layer for the protective metal layer 216 may include copper (Cu), aluminum copper (AlCu), tungsten (W), or a suitable metal or alloy. The protective metal layer 216 functions to reduce optical noise from entering the SPD region 202S and is provided directly above the SPD region 202S. To ensure the enclosure of the SPD region 202S, the protective metal layer 216 may be larger than the vertical projection area of ​​the SPD region 202S. In an embodiment in which both the protective metal layer 216 and the SPD region 202S are substantially square when viewed along the Z direction, the protective metal layer 216 may be made larger than the vertical projection area of ​​the SPD region 202S. However, to avoid occupying too much space in the interconnect structure, the margin of the enclosure may be less than about 1 μm along all edges. Because no electrical connection between the metal absorber feature 215 and the protective metal layer 216 is required, the protective metal layer 216 may or may not be in direct contact with the metal absorber feature 215. When the protective metal layer 216 is insulated from the metal absorber feature 215, the opening for the protective metal layer 216 terminates in the second etch stop layer 218, and the remaining second etch stop layer 218 is spaced from the protective metal layer 216 and the metal absorber feature 215.

[0022] 1 and 6, the method 100 includes block 110, where a further metal layer is formed above the protective metal layer 216. The formation of the metal absorber feature 215 and the protective metal layer 216 may be considered as part of the wiring process (BEOL) to form an interconnect structure 229 to functionally interconnect various devices in the image sensor 200. Block 110 continues to the BEOL to form a metal layer above the protective metal layer 216. Referring to FIG. 6, block 110 may deposit a third etch stop layer 222 above the second ILD layer 220 and the protective metal layer 216. A third ILD layer 224 is then deposited above the third etch stop layer 222. A plurality of contact vias 230 are then formed in the third etch stop layer 222 and the third ILD layer 224 using a process similar to that used to form the metal absorber feature 215 and the protective metal layer 216. Similarly, a fourth etch stop layer 226 and a fourth ILD layer 228 are sequentially deposited over the third ILD layer 224. A conductive line 231 is then formed in the fourth etch stop layer 226 and the fourth ILD layer 228. The contact via 230 and the conductive line 231 may comprise copper (Cu), aluminum copper (AlCu), tungsten (W), or a suitable metal or alloy. The third etch stop layer 222 and the fourth etch stop layer 226 may be similar to the first etch stop layer 206. The third ILD layer 224 and the fourth ILD layer 228 may be similar to the first ILD layer 210. As described below, without the protective metal layer 216, light from the LPD region 202L may be reflected by the contact via 230 and the conductive line 231 into the SPD region 202S. For ease of reference, the BEOL features, including the ILD layers, etch stop layers, contact vias, and conductive lines, may be collectively referred to as interconnect structures 229.

[0023] 1 and 7, the method 100 includes block 112, where an extended deep trench 232D is formed along the boundary of the small photodiode region. After the BEOL structures are formed, the workpiece 200 is flipped upside down so that the substrate 202 is on top and the BEOL structures are on the bottom. The Z-direction arrow in FIG. 7 points down to indicate the flip of the workpiece 200. To flip the workpiece 200 upside down, a carrier substrate (not explicitly shown) is bonded to the substrate 202. In some embodiments, the carrier substrate may be bonded to the workpiece 200 by fusion bonding, by use of an adhesive layer, or by a combination thereof. In some examples, the carrier substrate may be formed of a semiconductor material (e.g., silicon), sapphire, glass, a polymeric material, or other suitable material. In embodiments where fusion bonding is used, the carrier substrate includes a first oxide layer and the workpiece 200 includes a second oxide layer. After both the first oxide layer and the second oxide layer are processed, they are placed in intimate contact with each other for direct bonding at room temperature or at an elevated temperature. Once the carrier substrate is bonded to the workpiece 200, the workpiece 200 is flipped over as shown in FIG.

[0024] After the workpiece 200 is flipped upside down, a deep trench 232 and an extended deep trench 232D are formed in the substrate 202. As shown in FIG. 7, the deep trench 232 is formed between two adjacent LPD regions 202L, and the extended deep trench 232D is formed at the boundary between the SPD region 202S and the LPD region 202L. As the names suggest, the extended deep trench 232D extends deeper into the substrate 202. As shown in FIG. 7, the deep trench 232 has a first depth D1, and the extended deep trench 232D has a second depth D2. The second depth D2 is deeper than the first depth D1. In some examples, the first depth D1 is between about 1.0 μm and about 9 μm, and the second depth D2 is between about 1.5 μm and about 10 μm. The ratio of the first depth D1 to the second depth D2 may be between about 55% and about 90%. Etching the extended deep trenches 232 also results in a wider trench width. As shown in FIG. 7, each deep trench 232 may include a first trench width W1, and each extended deep trench 232D may include a second trench width W2. The second trench width W2 is wider than the first trench width W1. In some examples, the first trench width W1 may be between about 10 nm and about 300 nm, and the second trench width W2 may be between about 110% and about 200% of the first trench width W1.

[0025] In one exemplary process, a hard mask (not explicitly shown) is formed over the substrate 202. The hard mask may be a single layer or multiple layers. In one embodiment, the hard mask may include a silicon nitride layer and a silicon oxide layer over the silicon nitride layer. Photolithography and etching processes are then performed to pattern the hard mask. For example, a photoresist layer (not explicitly shown) is formed over the hard mask, exposed to a suitable photolithography radiation source, and developed to form a patterned photoresist layer. The patterned photoresist layer is then used as an etch mask to pattern the hard mask. The substrate 202 is then anisotropically etched using the patterned hard mask as an etch mask, thereby forming the deep trench 232. The anisotropic etch may be a dry etch process performed with sulfur hexafluoride (SF6), carbon tetrafluoride (CF4), nitrogen trifluoride (NF3), other fluorine-containing gases, oxygen (O2), or mixtures thereof. After the deep trench 232 is formed, another pattern film or another patterned photoresist layer is formed above the workpiece 200 to selectively expose the deep trench 232 along the border of the SPD region 202S. The deep trench 232 along the border of the SPD region 202S is then etched to extend further into the substrate 202 to form an extended deep trench 232D.

[0026] 1 and 8, the method 100 includes block 114, in which a liner 234 is conformally deposited over the workpiece 200, including the deep trench 232 and the extended deep trench 232D. The liner 234 may include a metal. In some embodiments, the liner 234 includes aluminum (Al), tungsten (W), ruthenium (Ru), cobalt (Co), or copper (Cu). The liner 234 may be deposited using CVD or atomic layer deposition (ALD).

[0027] 1 and 9, the method 100 includes block 116, in which a fill material 236 is deposited in the deep trench 232 and the extended deep trench 232D to form a deep trench isolation (DTI) feature 240 and an extended DTI feature 240D. The fill material 236 may include a dielectric material, such as a semiconductor oxide or a metal oxide. For example, the fill material 236 may include silicon oxide, aluminum oxide, hafnium oxide, titanium oxide, barium titanate, zirconium oxide, lanthanum oxide, barium oxide, strontium oxide, yttrium oxide, or combinations thereof. In one embodiment, the fill material 236 may include silicon oxide. The fill material 236 may be deposited using atomic layer deposition (ALD) or chemical vapor deposition (CVD). The deposition of the fill material 236 in the deep trench 232 and the extended deep trench 232D forms the DTI feature 240 and the extended DTI feature 240D, respectively. In general, the DTI feature 240 and the extended DTI feature 240D can function as reflectors that reflect light towards the SPD region 202S and the LPD region 202L to improve quantum efficiency (QE). In other words, the DTI feature 240 and the extended DTI feature 240D allow incident light to bounce around the SPD region 202S and the LPD region 202L before being dispersed, absorbed, or escaped.

[0028] 1, 10, and 11, the method 100 includes block 118, in which a metal film 244 is deposited above the fill material 236. The metal film 244 is formed directly above (or directly below when the workpiece 200 is flipped upside down) the SPD region 202S to diffract or deflect obliquely incident light away from the adjacent LPD region 202L. In one exemplary process depicted in FIGS. 10 and 11, a global metal layer 242 is blanket deposited above the fill material 236 to a thickness between about 100 Å and about 1000 Å, as shown in FIG. 10. The global metal layer 242 may include tin (Sn), aluminum copper (AlCu), or tungsten (W). The deposited global metal layer 242 is then patterned to form a metal film 244, as shown in FIG. 11. As shown in FIG. 11, the metal film 244 is directly over the SPD region 202S and the extended DTI features 240D around the SPD region 202S, and the metal film 244 overlaps the vertical projection area of ​​the SPD region 202S and the extended DTI features 240D. As further described in conjunction with FIGS. 21, 22, and 23, the extended DTI features 240D can extend completely around a single SPD region 202S or an array of multiple SPD regions 202S. In accordance with the present invention, the extended DTI features 240D are formed along the boundary between the SPD region 202S and the adjacent LPD region 202L. In at least some embodiments, the metal film 244 reduces the quantum efficiency (QE) of the SPD region 202S, which is at least one reason why the SPD region 202S has a lower QE than the LPD region 202L. Another reason may be related to the dimensions of the SPD region 202S and the LPD region 202L.

[0029] 1 and 12, the method 100 includes block 120, where a first passivation layer 246 is formed over the metal film 244. The first passivation layer 246 may include silicon oxide and may be deposited over the workpiece 200 using CVD. The first passivation layer 246 may share the same composition as the fill material 236.

[0030] 1, 13, and 14, the method 100 includes block 122, where a metal grid 250 is formed above the first passivation layer 246. As the name suggests, the metal grid 250 is a grid-like structure or framework that extends above some, if not all, of the SPD and LPD regions 202S and 202L. More specifically, the metal grid 250 corresponds to the boundaries of the SPD and LPD regions 202S and 202L to define optical path openings to the SPD and LPD regions 202S and 202L. In some embodiments, the metal grid 250 may include tin (Sn), aluminum copper (AlCu), aluminum (Al), tungsten (W), ruthenium (Ru), cobalt (Co), or copper (Cu). In one embodiment, the metal grid 250 may be formed of tin (Sn). The metal grid 250 physically blocks light reflection between adjacent photodiode regions (i.e., SPD region 202S and LPD region 202L) and prevents crosstalk between adjacent photodiodes. In one exemplary process for forming the metal grid 250, a metal layer is deposited above the first passivation layer 246. Photolithography and etching processes are then used to pattern the metal layer into the metal grid 250. In the illustrated embodiment, the metal grid 250 has chamfered or rounded top corners due to the etching manner in the formation process. As shown in the top view of the workpiece 200 in FIG. 15, the metal grid 250 may form rounded square openings rather than sharp square openings due to the etching manner in the formation process. As used herein, rounded square openings refer to substantially square grid openings with rounded corners.

[0031] 1 and 16, the method 100 includes block 124, in which a second passivation layer 252 is deposited above the metal grid 250. Like the first passivation layer 246, the second passivation layer 252 may include silicon oxide and may be deposited using CVD. The portions of the fill material 236 above the SPD region 202S and the LPD region 202L, the first passivation layer 246, and the second passivation layer 252 may be collectively considered a passivation structure. The metal grid 250 and the metal film 244 are embedded in such a passivation structure. In accordance with the present invention, the thickness of the passivation structure is minimized to reduce the path of optical noise from above the LPD region 202L to the SPD region 202S. 16, the passivation structure includes a top thickness T1 measured from the top surface of the metal grid 250 and a bottom thickness T2 measured from the bottom surface of the metal grid to the top surface of the substrate 202. The top thickness T1 represents the top gap that is not blocked by the metal grid 250, and the bottom thickness T2 represents the bottom gap that is not blocked by the metal grid 250. In some embodiments, the top thickness T1 and the bottom thickness T2 may each be between about 100 Å and about 1000 Å.

[0032] 1 and 17, the method 100 includes block 126 where further processes are performed. Such further processes may include forming a color filter array 260 above the second passivation layer 252 and forming a microlens feature 270 above the color filter array 260. The color filter array 260 may be formed of a polymeric material or a resin containing color pigments. At block 26, the color filter array 260 is formed above the second passivation layer 252. The color filter array 260 includes a number of filters that allow the transmission of radiation (e.g., light) having a particular range of wavelengths and block light having wavelengths outside the particular range. With reference to FIG. 17, the microlens feature 270 is formed above the color filter array 260. The microlens feature 270 may be formed of any material that can be patterned to form lenses, such as a highly transmittant acrylic polymer. In one embodiment, the microlens layer may be formed using liquid materials and spin-on techniques. This method has been found to produce a microlens layer having a substantially flat surface and a substantially uniform thickness, thereby providing greater uniformity of the microlens features 270. Other methods, such as CVD, PVD, etc., may also be used. The flat material for the microlens layer may be patterned using photolithography and etching techniques to pattern the flat material into microlens features 270 that correspond to the array of photodiode regions (i.e., SPD regions 202S and LPD regions 202L). The flat material may then be reflowed to form the appropriate curved surface for the microlens features 270. The microlens features 270 may be cured using an ultraviolet (UV) process.

[0033] Upon completion of the operations at block 126, the image sensor 200 shown in Figure 17 is substantially formed. As is customary in the industry, the side of the substrate 202 on which the LPD transistor 208L and the SPD transistor 208S are formed is referred to as the front side, and the opposite side on which the passivation structure 254 is formed is referred to as the back side. Because the image sensor 200 allows incident light to come from the back side, the image sensor 200 of Figure 17 includes a back side illuminated (BSI) structure and may be referred to as a BSI image sensor 200.

[0034] In some alternative embodiments, the color filter array 260 is partially embedded in the passivation structure 254 rather than being disposed completely above it. See FIG. 18. In these alternative embodiments, the second passivation layer 252 is formed thicker than that of FIG. 16. The thicker second passivation layer 252 in FIG. 18 is then patterned to form color filter openings. Color filter elements are then formed in the color filter openings to form the color filter array 260. Unlike the color filter array of FIG. 17, the color filter elements in the color filter array shown in FIG. 19 are separated from each other by the second passivation layer 252.

[0035] The BSI image sensor 200 shown in FIG. 17 may be provided in a pixel region surrounded by a peripheral region. As their names suggest, the pixel region includes the BSI image sensor 200 that is illuminated by incident light, and the peripheral region includes a reference structure that is not illuminated. FIG. 20 illustrates an exemplary reference structure 300. Unlike the BSI image sensor 200 of FIG. 17, the reference structure 300 includes a metal shield 2500. Rather than having a grid opening like the metal grid 250, the metal shield 2500 functions to block the incident light. In some implementations, the metal shield 2500 above the substrate structure 300 and the metal grid 250 above the BSI image sensor 200 are formed simultaneously using the same material. In one exemplary process, a metal layer is deposited above the pixel region and the peripheral region, and then only the metal layer in the pixel region undergoes a patterning process to form the metal grid 250. In an implementation, the metal shield 2500 and the metal grid 250 may have the same thickness along the Z direction. The thickness of the metal shield 2500 is greater than that of the metal film 244. In the illustrated embodiment, the reference structure 300 does not include the metal film 244 because the light incident on the peripheral area is completely blocked by the metal shield 2500. The reference structure 300 functions to provide a background level for the black state. The background level from the reference structure 300 enables black level compensation (BLC) to increase sensitivity.

[0036] FIG. 21 illustrates how the thinner passivation structure, metal film 244, extended DTI features 240D, metal absorber features 215, and protective metal layer 216 reduce stray light noise from the LPD region 202L to the SPD region 202S. Incident light A represents light transmitted through and / or reflected by the color filter array 260 and microlens features 270 from above the LPD region 202L. FIG. 21 illustrates diagrammatically that incident light A coming at a certain angle is blocked or reflected by the metal film 244. Note that the thinner passivation structure 254 also plays a role here. When the top separation (above the metal grid 250) and bottom separation (below the metal grid 250) are too large, incident light A at a shallow angle (i.e., having an incidence angle close to 90° relative to the normal direction of the image sensor 200) may avoid the metal film 244 and enter the SPD region 202S. Incident light B represents light reflected by the liner 234 of the DTI feature 240 around the LPD region 202L. Since the extended DTI feature 240D extends substantially through the substrate, the extended DTI feature 240D acts to block or reflect the incident light B and prevent it from entering the SPD region 202S. The incident light B reflected by the extended DTI feature 240D generates more photons-electrons in the LPD region 202L, increasing its quantum efficiency.

[0037] Please continue to refer to FIG. 21. Incident light C represents light penetrating the LPD region 202L and entering the interconnect structure 229. Without the metallic absorber feature 215 and the protective metal layer 216, the incident light C may be reflected by the metallic features in the interconnect structure 299 and become noise in the SPD region 202S. As representatively shown in FIG. 21, the metallic absorber feature 215 blocks and reflects the incident light C. Incident light D represents light reflected by the metallic features in the interconnect structure 299. The incident light D may originate from light similar to the incident light C, but does not originate from the adjacent LPD region 202L as the incident light C does. As shown in FIG. 21, the protective metal layer 216 functions to block and reflect the incident light D.

[0038] Although the SPD region 202S is shown sandwiched between two LPD regions 202L in Figures 2-20, it should be understood that the invention is not so limited and includes other designs in which at least one SPD region 202S is adjacent to an LPD region 202L. Exemplary designs of image sensors 200 according to the invention are shown in Figures 24, 25, 26, and 27. Figure 24 illustrates a schematic top view of a first image sensor 200-1 including one SPD region 202S and three LPD regions 202L arranged in a rectangle. The SPD region 202S is located in the upper left corner of the rectangle, and the three LPD regions 202L occupy the other three corners. In the embodiment illustrated in Figure 24, the SPD region 202S is separated from the LPD region 202L by the extended DTI feature 240D, and the LPD regions 202L are not spaced apart from one another by the DTI feature 240 or the extended DTI feature 240D. A first image sensor 200-1, which includes an SPD region 202S and three LPD regions 202L, is surrounded by a DTI feature 240.

[0039] 25 shows a schematic top view of a second image sensor 200-2 including one SPD region 202S and eight LPD regions 202L arranged in a rectangle surrounding the SPD region. The SPD region 202S is located at the geographic center of the rectangle, and the eight LPD regions 202L are located along the edges to surround the SPD region 202S. In the embodiment shown in FIG. 25, the SPD region 202S is separated from the eight LPD regions 202L by an extended DTI feature 240D, and the eight LPD regions 202L are not spaced apart from each other by the DTI feature 240 or the extended DTI feature 240D. The second image sensor 200-2 including the SPD region 202S and the eight LPD regions 202L is surrounded by the DTI feature 240.

[0040] 26 shows a schematic top view of a third image sensor 200-3 including four SPD regions 202S and twelve LPD regions 202L arranged in a rectangle. The four SPD regions 202S are located at the geographic center of the rectangle, and the twelve LPD regions 202L are located along the edges to surround the four central SPD regions 202S. In the embodiment shown in FIG. 26, the four SPD regions 202S are separated from the twelve LPD regions 202L by the extended DTI feature 240D, and the LPD regions 202L are not spaced apart from one another by the DTI feature 240 or the extended DTI feature 240D. In addition, the four SPD regions 202S are not spaced apart from one another by either the DTI feature 240 or the extended DTI feature 240D. A third image sensor 200-3, which includes four SPD regions 202S and twelve LPD regions 202L, is surrounded by a DTI feature 240.

[0041] 27 shows a schematic top view of a fourth image sensor 200-4 including octagonal LPD regions 202L and SPD regions 202S provided in the gaps between the octagonal LPD regions 202L. Each SPD region 202S may have a square or rectangular shape. Each SPD region 202S is surrounded by an extended DTI feature 240D. Except for the boundary edge with the SPD region 202S, each LPD region 202L is surrounded by a DTI feature 240D. That is, each LPD region 202L is surrounded by the DTI feature 240 and the extended DTI feature 240D.

[0042] Thus, in some embodiments, the present invention provides an image sensor including a first photodiode disposed between a second photodiode and a third photodiode along one direction, a first deep trench isolation (DTI) feature disposed between the first photodiode and the second photodiode, and a second DTI feature disposed between the first photodiode and the third photodiode, wherein a depth of the first DTI feature is greater than a depth of the second DTI feature, and a quantum efficiency of the second photodiode is less than the quantum efficiency of the first photodiode.

[0043] In some embodiments, the quantum efficiency of the third photodiode is substantially the same as the quantum efficiency of the first photodiode. In some implementations, the first photodiode has a first width along the one direction, and the second photodiode has a second width along the one direction, the first width being greater than the second width. In some examples, the image sensor further includes a passivation layer disposed above the first photodiode, the second photodiode, and the third photodiode, and a metal grid embedded in the passivation layer and spanning above the first photodiode, the second photodiode, and the third photodiode. In some embodiments, the image sensor further includes a metal film embedded in the passivation layer and disposed between the metal grid and the second photodiode. In some implementations, the image sensor further includes a first dielectric layer disposed below the first photodiode, the second photodiode, and the third photodiode, and a first metal structure embedded in the first dielectric layer. The first metal structure is substantially aligned with the first DTI feature along a vertical direction. In some embodiments, the first metal structure has a ring shape and extends completely around a portion of the first dielectric layer directly beneath the second photodiode. In some embodiments, the image sensor further includes a second dielectric layer disposed below the first dielectric layer and a second metal structure embedded in the second dielectric layer and disposed directly above the second photodiode. The first metal structure is in direct contact with the second metal structure. In some embodiments, the first metal structure includes an array of metal posts.

[0044] Another aspect of the invention relates to an image sensor including a first photodiode, a second photodiode adjacent to the first photodiode along one direction, a first passivation layer disposed above the first and second photodiodes, a metal grid disposed above the first passivation layer, and a metal film embedded in the first passivation layer and disposed directly above the first photodiode but not extending above the second photodiode, where the quantum efficiency of the first photodiode is different from the quantum efficiency of the second photodiode.

[0045] In some embodiments, the quantum efficiency of the first photodiode is lower than the quantum efficiency of the second photodiode. In some implementations, the first photodiode has a first width along the direction and the second photodiode has a second width along the direction, the first width being less than the second width. In some implementations, the image sensor further includes a first deep trench isolation (DTI) feature around the first photodiode and a second DTI feature along a sidewall of the second photodiode. The depth of the first DTI feature is greater than the depth of the second DTI feature. In some embodiments, the metal film includes tin, aluminum copper, or tungsten. In some embodiments, the image sensor further includes a second passivation layer disposed above the first passivation layer and the metal grid, a first color filter element embedded in the second passivation layer and disposed directly above the first photodiode, and a second color filter element embedded in the second passivation layer and disposed directly above the second photodiode. The first and second color filter elements are spaced apart by a portion of the second passivation layer, hi some embodiments, the first passivation layer comprises a thickness between about 100 Å and about 1000 Å.

[0046] Yet another aspect of the invention relates to a method, comprising receiving a substrate including a first photodiode region disposed between a second photodiode region and a third photodiode region along one direction, a first transistor disposed above the first photodiode region, a second transistor disposed above the second photodiode region, a third transistor disposed above the third photodiode region, and a first dielectric layer disposed above the first, second, and third transistors, the method further comprising forming an annular trench in the first dielectric layer to extend completely around the second transistor, and depositing a first metal fill layer in the annular trench to form a first metal structure, a first portion of the first metal structure being vertically aligned with an interface between the first and second photodiode regions, and a second portion of the first metal structure being vertically aligned with an interface between the second and third photodiode regions.

[0047] In some embodiments, the method further includes depositing a second dielectric layer over the first dielectric layer and the first metal structure, forming an opening in the second dielectric layer substantially aligned with a vertical projection area of ​​the second photodiode region, and depositing a second metal fill layer in the opening to form the second metal structure. In some implementations, the method further includes inverting the substrate and forming a deep trench that completely surrounds the second photodiode region, such that the first photodiode region and the third photodiode region are spaced apart from the second photodiode region by the deep trench along the one direction. The deep trench extends through substantially the entire height of the second photodiode region. In some examples, the method further includes conformally depositing a liner over the deep trench and depositing a dielectric material over the deep trench after conformally depositing the liner.

[0048] The foregoing outlines features of several embodiments to better enable those skilled in the art to understand aspects of the present invention. Those skilled in the art should appreciate that this disclosure may readily be used as a basis for designing or modifying other processes and structures to carry out the same purposes and / or achieve the same advantages as the embodiments presented herein. Those skilled in the art should also appreciate that such equivalent structures do not depart from the spirit and scope of the present invention, and that various modifications, substitutions, and alterations may be made without departing from the spirit and scope of the present invention. [Industrial Applicability]

[0049] The present invention provides an image sensor structure with reduced crosstalk between large and small photodiodes. [Explanation of symbols]

[0050] 100: Method 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126: Block 200: Image sensor 200-1: First image sensor 200-2: Second image sensor 200-3: The third image sensor 200-4: 4th image sensor 202: Substrate 202L: Large photodiode (LPD) area 202S: Small Photodiode (SPD) Area 204: Isolation Features 206: First etch stop layer 208L: Large Photodiode (LPD) Transistor 208S: Small Photodiode (SPD) Transistor 210: First interlayer dielectric (ILD) layer 212, 212S: Opening 214: Metal filled layer 215: Metal absorber characteristics 216: Protective metal layer 218: Second etch stop layer 220: second interlayer dielectric (ILD) layer 222: Third etch stop layer 224: Third interlayer dielectric (ILD) layer 226: Fourth etch stop layer 228: Fourth interlayer dielectric (ILD) layer 229: Interconnect Structures 230: Contact via 231: Conductive wire 232: Deep Trench 232D: Extended Deep Trench 234: Liner 236: Filling material 240: Deep Trench Isolation (DTI) Features 240D: Extended Deep Trench Isolation (DTI) Features 242: Global Metal Layer 244: Metal film 246: First passivation layer 250: Metal grid 252: Second passivation layer 254: Passivation structure 260: Color filter array 270: Microlens Features 300: Reference structure 2500: Metal shield A, B, C, D: Incident light D1: First depth D2: Second depth T1: Top thickness T2: Bottom thickness W1: First trench width W2: Second trench width X, Y, Z: direction

Claims

1. a first photodiode provided between the second photodiode and the third photodiode along one direction; a first deep trench isolation (DTI) feature disposed between the first photodiode and the second photodiode; a second DTI feature disposed between the first photodiode and the third photodiode; and a first dielectric layer disposed below the first photodiode, the second photodiode, and the third photodiode; at least one first metal structure embedded in the first dielectric layer; Including, a depth of the first DTI feature is greater than a depth of the second DTI feature; the quantum efficiency of the second photodiode is lower than the quantum efficiency of the first photodiode; the at least one first metal structure extends or is arranged to extend around a portion of the first dielectric layer directly beneath the second photodiode; Image sensor.

2. the quantum efficiency of the third photodiode is the same as the quantum efficiency of the first photodiode; 2. The image sensor of claim 1.

3. the first photodiode has a first width along the one direction; the second photodiode has a second width along the one direction; The first width is greater than the second width.

2. The image sensor of claim 1.

4. the first metal structure is aligned with the first DTI feature along a vertical direction; 2. The image sensor of claim 1.

5. A first photodiode; a second photodiode adjacent to the first photodiode along one direction; a first passivation layer provided above the first photodiode and the second photodiode; a metal grid disposed above the first passivation layer; a metal film embedded in the first passivation layer and disposed directly above the first photodiode but not extending above the second photodiode; a dielectric layer provided below the first photodiode and the second photodiode; at least one metal structure embedded in said dielectric layer; Including, the quantum efficiency of the first photodiode is lower than the quantum efficiency of the second photodiode; the at least one metal structure extends or is arranged to extend around a portion of the dielectric layer directly beneath the first photodiode. Image sensor.

6. the first photodiode has a first width along the one direction; the second photodiode has a second width along the one direction; The first width is smaller than the second width.

6. The image sensor according to claim 5.

7. a second photodiode region provided between the first photodiode region and the third photodiode region along one direction; a first transistor provided above the first photodiode region; a second transistor disposed above the second photodiode region; a third transistor provided above the third photodiode region; a first dielectric layer disposed above the first transistor, the second transistor, and the third transistor; receiving a substrate comprising: forming an annular trench in the first dielectric layer extending completely around the second transistor; depositing a first metal fill layer in the annular trench to form a first metal structure; Including, a first portion of the first metal structure vertically aligned with an interface between the first photodiode region and the second photodiode region, and a second portion of the first metal structure vertically aligned with an interface between the second photodiode region and the third photodiode region. A method for forming an image sensor.

8. depositing a second dielectric layer over the first dielectric layer and the first metal structure; forming an opening in the second dielectric layer aligned with a vertical projection area of ​​the second photodiode area; depositing a second metal fill layer in the opening to form a second metal structure; Further comprising: A method for forming the image sensor of claim 7.

9. inverting the substrate; forming a deep trench completely surrounding the second photodiode region, such that the first photodiode region and the third photodiode region are spaced apart from the second photodiode region by the deep trench along the one direction; Further comprising: the deep trench extends through the entire height of the second photodiode region; A method for forming the image sensor of claim 7.

Images