Display device

Abstract

To provide a display device that offers an improved lighting ratio of light-emitting elements.SOLUTION: A display device according to an embodiment of the present invention comprises: a substrate including a plurality of sub pixels; a first lower assembly electrode provided in the plurality of sub pixels; a first assembly line provided in the plurality of sub pixels and on a layer different from that of the first lower assembly electrode; a light-emitting element provided on the first lower assembly electrode and the first assembly line, including a first electrode, a semiconductor layer, and a second electrode; and a second lower assembly electrode provided between the first lower assembly electrode and the light emitting element and electrically connected to the first electrode or the second electrode.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present specification relates to a display device, and more particularly to a display device self-assembled with LEDs (Light Emitting Diodes). [Background technology]

[0002] Display devices used in computer monitors, TVs, mobile phones, etc. include organic light emitting displays (OLEDs), which emit light themselves, and liquid crystal displays (LCDs), which require a separate light source.

[0003] Display devices are now used in a wide variety of applications, including not only computer monitors and TVs but also personal portable devices. Research is currently underway into display devices that have a large display area while being reduced in volume and weight.

[0004] In recent years, displays that include LEDs (Light Emitting Diodes) have been attracting attention as the next generation of display devices. LEDs are made of inorganic materials, not organic materials, and therefore have excellent reliability and a longer lifespan than LCDs and OLEDs. LEDs not only light up quickly, but also have excellent luminous efficiency, strong impact resistance, excellent stability, and can display high brightness images. Summary of the Invention [Problem to be solved by the invention]

[0005] The problem to be solved by this specification is to provide a display device in which a lower assembly electrode that is in direct contact with the light-emitting element is disposed below the light-emitting element and connected to a power supply wiring, thereby improving the lighting rate of the light-emitting element.

[0006] The subject of the present specification is not limited to the subject mentioned above, and other subjects not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0007] In order to solve the above-mentioned problems, a display device according to an embodiment of the present specification includes a substrate including a plurality of sub-pixels, a first lower assembly electrode disposed in the plurality of sub-pixels, a first assembly wiring disposed in the plurality of sub-pixels and disposed in a layer different from the first lower assembly electrode, a light emitting element disposed on the first lower assembly electrode and the first assembly wiring and including a first electrode, a semiconductor layer, and a second electrode, and a second lower assembly electrode disposed between the first lower assembly electrode and the light emitting element and electrically connected to the first electrode or the second electrode. This can improve the assembly rate of the light emitting element and reduce the resistance of the power wiring to improve the lighting rate.

[0008] In order to solve the above-mentioned problems, a display device according to another embodiment of the present specification includes a substrate including a plurality of sub-pixels, first and second assembly wirings arranged in parallel with the plurality of sub-pixels, a light emitting element arranged to overlap the first or second assembly wiring, and a first lower auxiliary electrode and a second lower auxiliary electrode overlapping one of the first and second assembly wirings and the light emitting element below the light emitting element, thereby improving the assembly rate of the light emitting element and reducing the resistance of the power wiring to improve the lighting rate.

[0009] Further details of the embodiments are included in the detailed description and the drawings. Effect of the Invention

[0010] According to the embodiments of the present specification, the assembly electrodes disposed inside the assembly grooves are disposed on different layers, thereby improving the strength of the electric field for assembling the light emitting device.

[0011] According to the embodiment of the present specification, the first electrode of the light emitting device and the lower assembly electrode are in direct contact with each other, so that the light emitting device can be fixed to the substrate even after assembly of the light emitting device.

[0012] According to the embodiment of the present specification, by connecting the auxiliary electrode to the power supply wiring, the resistance of the power supply wiring can be reduced, and the lighting rate of the light emitting element can be improved.

[0013] According to the embodiments of the present specification, the thickness of the planarization layer disposed on the light emitting element can be reduced by disposing the light emitting element in the planarization layer.

[0014] The effects of the present invention are not limited to the above-mentioned examples, and various other effects are included within the scope of the present invention. [Brief description of the drawings]

[0015] [Figure 1] FIG. 1 is a schematic diagram illustrating a configuration of a display device according to an embodiment of the present specification. [Diagram 2] 1 is a schematic plan view of a display panel included in a display device according to an embodiment of the present disclosure; [Diagram 3] FIG. 1 is an enlarged plan view of a display device according to an embodiment of the present specification. [Figure 4] 3 is a cross-sectional view taken along lines AA' and BB' in FIG. 2. [Diagram 5] 3 is a cross-sectional view taken along lines AA' and CC' in FIG. 2. [Figure 6a] 1A to 1C are cross-sectional views for explaining a manufacturing process of a display device according to an embodiment of this specification. [Figure 6b] 1A to 1C are cross-sectional views for explaining a manufacturing process of a display device according to an embodiment of this specification. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] The advantages and features of the present specification, and the methods for achieving them, will become clear from the detailed description of the embodiments with accompanying drawings. However, the present specification is not limited to the embodiments disclosed below, but may be configured in various different forms, and the embodiments are provided merely to ensure that the disclosure of the present specification is complete and to fully inform those skilled in the art of the present specification of the scope of the invention, and the present specification is only defined by the scope of the claims.

[0017] The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of this specification are illustrative, and the specification is not limited to the matters illustrated. The same reference symbols refer to the same components throughout the specification. In addition, in explaining this specification, if it is determined that a specific description of related known technology may unnecessarily cloud the gist of this specification, the detailed description will be omitted. When "includes," "has," "is made," etc. are used in this specification, other parts may be added since "only" is not used. When a component is expressed in the singular, it includes the case where it includes a plural, unless otherwise expressly stated.

[0018] When interpreting elements, they are interpreted as including a margin of error even if there is no other explicit description.

[0019] When describing a positional relationship, for example when describing the positional relationship of two parts using "on top of," "at the top of," "at the bottom of," "next to," etc., one or more other parts may be located between the two parts, so long as "immediately" or "directly" is not used.

[0020] When an element or layer is referred to as "on" another element or layer, this includes the case where the element or layer is directly on top of the other element, or has other layers or elements interposed therebetween.

[0021] In addition, although the terms "first", "second" and the like are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, the first component referred to below may be the second component within the technical concept of this specification.

[0022] Like reference numbers refer to like elements throughout the specification.

[0023] The area and thickness of each component shown in the drawings are shown for convenience of explanation, and the present specification is not necessarily limited to the area and thickness of the components shown.

[0024] The features of the various embodiments of this specification may be combined or combined with each other, either partially or in whole, and may be technically interlocked and driven in various ways, and each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

[0025] Various embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0026] FIG. 1 is a schematic plan view of a display device according to an embodiment of the present specification.

[0027] For ease of explanation, FIG. 1 shows only a display panel PN, a gate driver GD, a data driver DD, and a timing controller TC among various components of the display device 100.

[0028] Referring to FIG. 1, a display device 100 includes a display panel PN including a plurality of sub-pixels SP, a gate driver GD and a data driver DD for supplying various signals to the display panel PN, and a timing controller TC for controlling the gate driver GD and the data driver DD.

[0029] The display panel PN is configured to display an image to a user and includes a plurality of sub-pixels SP. A plurality of scan lines SL and a plurality of data lines DL cross each other in the display panel PN, and each of the sub-pixels SP is connected to the scan lines SL and the data lines DL. In addition, each of the sub-pixels SP may be connected to a high potential power line VL1, a low potential power line VL2, a reference line VL3, etc.

[0030] The sub-pixels SP are the minimum units constituting a screen, and each of the sub-pixels SP includes a light-emitting element and a pixel circuit for driving the light-emitting element. The light-emitting elements may be defined differently depending on the type of the display panel PN. For example, when the display panel PN is an inorganic light-emitting display panel, the light-emitting element may be an LED (Light-emitting Diode) or a micro LED (Micro Light-emitting Diode).

[0031] The gate driver GD supplies a plurality of scan signals SCAN to a plurality of scan lines SL in response to a plurality of gate control signals GCS provided from a timing controller TC. Although one gate driver GD is shown to be disposed at a distance from one side of the display panel PN in FIG. 1, the number and arrangement of the gate driver GD are not limited thereto.

[0032] The data driver DD converts image data RGB input from the timing controller TC into data voltages Vdata using a reference gamma voltage in response to a plurality of data control signals DCS provided from the timing controller TC. The data driver DD can supply the converted data voltages Vdata to a plurality of data lines DL.

[0033] The timing controller TC aligns externally input image data RGB and supplies it to the data driver DD. The timing controller TC can generate gate control signals GCS and data control signals DCS using externally input synchronous signals, for example, a dot clock signal, a data enable signal, and a horizontal / vertical synchronous signal. The timing controller TC can then supply the generated gate control signals GCS and data control signals DCS to the gate driver GD and data driver DD, respectively, to control the gate driver GD and data driver DD.

[0034] In the following, the display panel PN of the display device 100 according to an embodiment of the present specification will be described in more detail.

[0035] 2 is a schematic plan view of a display panel included in a display device according to an embodiment of the present disclosure, in which for convenience of explanation, only a substrate 110, a plurality of pixels PX, pads, and wiring are shown among various components of the display device 100.

[0036] The substrate 110 is a component for supporting various components included in the display panel PN and may be made of an insulating material. For example, the substrate 110 may be made of glass, resin, etc. The substrate 110 may also be made of a flexible material including a polymer or plastic.

[0037] The substrate 110 can be divided into a display region and a non-display region, and the display region is a region where a plurality of pixels PX are arranged to display an image. The plurality of pixels PX may include at least two or more sub-pixels. In the drawings, the plurality of pixels PX are illustrated as including three sub-pixels SP1, SP2, and SP3, but are not limited thereto. The three sub-pixels include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. Hereinafter, any one of the three sub-pixels may be referred to as SP.

[0038] Each of the sub-pixels SP is an individual unit that emits light, and a light emitting element 120 and a pixel circuit are disposed in each of the sub-pixels SP. A unit pixel including three sub-pixels SP1, SP2, and SP3 may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, or may include sub-pixels that emit at least two colors among the red sub-pixel, the green sub-pixel, the blue sub-pixel, and the white sub-pixel, but is not limited thereto. The unit pixel may also include at least two or more sub-pixels that include the least efficient light emitting element among the red light emitting element, the green light emitting element, and the blue light emitting element.

[0039] A display device 100 according to one embodiment of the present specification includes a first subpixel SP1 that emits red light, a second subpixel SP2 that emits green light, and a third subpixel SP3 that emits blue light, and the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 may be arranged side by side in the row direction.

[0040] As mentioned above, the display area is an area in which a plurality of unit pixels are arranged, and the non-display area is an area in which no image is displayed and in which a plurality of unit pixels are not arranged, i.e., an area in which a gate driver GD for driving a plurality of sub-pixels SP arranged in the display area, wiring, pads for applying signals to the wiring, etc. are arranged.

[0041] The gate driver GD supplies gate signals to the sub-pixels SP through the gate lines GL. The gate signals include scan signals and light emission signals. The scan signals are provided through the scan lines SL, and the light emission signals are provided through the light emission lines EL. The scan lines SL and the light emission lines EL may be collectively referred to as the gate lines GL.

[0042] The gate driver GD includes a scan driver for providing a scan signal and an emission driver for providing an emission signal.

[0043] In the display device 100 according to an embodiment of the present disclosure, the gate driver GD may be divided into a plurality of regions on the substrate 110 and disposed between the plurality of pixels PX.

[0044] In the display device 100 according to an embodiment of the present specification, the light emitting element may be an LED (light emitting diode, inorganic light emitting element). Since the LED has excellent light emitting efficiency, the area occupied by the LED based on the sub-pixel SP region may be very small. Therefore, an LED and a pixel circuit driving the LED may be arranged for each sub-pixel SP, and a gate driver GD may be arranged in a non-display region for at least one sub-pixel SP or at least one unit pixel.

[0045] 2, the gate driver GD is arranged every two unit pixels and can provide gate signals to the sub-pixels SP arranged in the same row as the gate driver GD. For example, the gate driver GD can be arranged between the blue light-emitting sub-pixel and the red light-emitting sub-pixel. However, the arrangement density of the gate driver GD can be changed depending on the case.

[0046] The scan driver and the emission driver included in the gate driver GD may be arranged in the same row but in different regions.

[0047] The data driver DD converts image data into a data signal and supplies the converted data signal to the sub-pixel SP through the data line DL. The data driver DD may be formed on the rear surface of the substrate 110 or on a separate substrate. When the data driver DD is formed on one surface of the separate substrate, the other surface on which the data driver DD is not formed may be attached to the rear surface of the substrate 110 so as to face each other. To electrically connect the front and rear surfaces of the substrate 110 or to electrically connect the front surface of the substrate 110 to the other surface of the separate substrate, side wiring is disposed on the side of the substrate 110 or the substrate 110 and the other substrate. Thus, the data driver disposed on the rear surface of the substrate 110 or the other surface of the separate substrate may supply data signals to the sub-pixel SP through the side wiring.

[0048] As described above, in the display device 100 according to an embodiment of the present specification, the gate driver GD may be disposed between adjacent unit pixels on the substrate 110. However, the present invention is not limited thereto, and the gate driver GD may be disposed on one side or both sides of the substrate 110.

[0049] Meanwhile, the gate lines GL may be arranged in a row direction, and the data lines DL may be arranged in a column direction on the substrate 110. The gate lines GL and the data lines DL are arranged in all the sub-pixels SP, and provide signals to the pixel circuits arranged in the sub-pixels SP.

[0050] Pad areas PA1 and PA2 in which pads are arranged are formed on both sides of the substrate 110, i.e., on the upper and lower sides of the substrate 110 in the column direction. In this case, the pad area formed on the upper side of the substrate 110 is called the first pad area PA1, and the pad area formed on the lower side of the substrate 110 is called the second pad area PA2. The first pad area PA1 and the second pad area PA2 are areas facing each other on the substrate 110.

[0051] In the first pad area PA1, a data pad DP connected to the data line DL, a gate pad GP connected to the gate driver GD, a high potential voltage pad VP1 connected to the high potential voltage line VL1, and a reference voltage pad VP3 connected to the reference voltage line VL3 may be arranged. In this case, the number of data pads arranged is equal to the number of sub-pixels SP included in the unit pixel.

[0052] The gate driver GD is provided with lines for providing various clock signals, lines for providing gate low voltages, and lines for providing gate high voltages, and can transmit signals. The gate drivers GD are arranged in a row direction, and lines for transmitting signals to the gate driver GD are aligned with the gate driver GD. The lines for transmitting signals to the gate driver GD are called gate driving lines GDSL, and the gate driving lines GDSL are arranged in a row direction and connected to gate pads GP arranged in the first pad area PA1 to receive signals from the gate pads GP.

[0053] The high potential voltage wiring VL1 may be arranged in the column direction for each unit pixel or for each sub-pixel SP. In the drawings, the high potential voltage wiring VL1 is shown arranged on the left / right side of each unit pixel PX, but is not limited thereto. The high potential voltage wiring VL1 arranged in the column direction provides a high potential voltage to a plurality of sub-pixels SP through a high potential voltage pad VP1 in the first pad area PA1. The plurality of high potential voltage wirings VL1 arranged in the column direction are connected to auxiliary high potential voltage wirings AVL1 arranged in the row direction to form a mesh structure. The auxiliary high potential voltage wiring AVL1 may be arranged for every row in which the sub-pixels SP are arranged, or for every plurality of rows. The auxiliary high potential voltage wiring AVL1 can prevent a voltage drop in the high potential voltage wiring VL1 and provide a high potential voltage to a plurality of sub-pixels SP.

[0054] A low potential voltage pad VP2 connected to a low potential voltage wiring may be disposed in the second pad area PA2. In this case, the assembly wiring AL for self-assembling the light emitting element is used as the low potential voltage wiring after the light emitting element is assembled.

[0055] The assembly wiring AL may be arranged in the column direction, with two assembly wirings for each subpixel SP. The assembly wiring AL includes a first assembly wiring 122 and a second assembly wiring 123. The assembly wiring AL arranged in the column direction provides a low potential voltage to the subpixels SP through a low potential voltage pad VP2 in the second pad area PA2. A plurality of low potential voltage pads VP2 may be arranged, and may be arranged for at least two assembly wirings.

[0056] The assembly wirings AL arranged in the column direction are connected to the auxiliary low-potential voltage wirings AAL arranged in the row direction before being connected to the low-potential voltage pad VP2. In the drawing, the auxiliary low-potential voltage wirings AAL are shown only on one side of the substrate 110, but are not limited thereto and may be arranged on at least one side of the substrate 110. Furthermore, wiring for connecting the assembly wirings AL for every row or every few rows in which the sub-pixels SP are arranged may be arranged in the row direction. Thus, the auxiliary low-potential voltage wirings AAL can prevent a voltage drop in the assembly wirings AL and provide a low-potential voltage to the sub-pixels SP.

[0057] The reference voltage wiring VL3 may be arranged in the column direction for each unit pixel arranged in the row direction. The reference voltage wiring VL3 arranged in the column direction provides a reference voltage to the unit pixel through a separately arranged row direction wiring. The reference voltage wiring VL3 is connected to a reference voltage pad VP3 arranged in the first pad area PA1, and a reference voltage is provided to the plurality of reference voltage wirings VL3 through the reference voltage pad VP3.

[0058] The display panel PN included in the display device 100 according to an embodiment of the present specification may be removed by grinding the edge of the substrate 110 to reduce the bezel. The bezel is an edge area of ​​the substrate 110 where the sub-pixels SP are not arranged. During grinding, a portion of the pads and wiring arranged on the edge of the substrate 110 is removed, and the size of the substrate 110 is reduced, so that the display panel PN can be configured to the size of the final substrate 110F.

[0059] Specifically, most of the pads arranged in the first pad area PA1 and the second pad area PA2 may be removed from the final substrate 110F, leaving only parts or traces of the pads.

[0060] In the following, reference is also made to FIG. 2 for a more detailed description of the sub-pixels SP.

[0061] FIG 3 is an enlarged plan view of a display device according to an embodiment of the present specification. FIG 4 is a cross-sectional view taken along lines A-A' and B-B' in FIG 3. FIG 5 is a cross-sectional view taken along lines A-A' and C-C' in FIG 3. Referring to FIG 3, each of the sub-pixels SP includes a first transistor T1, a second transistor T2, a third transistor T3, a storage capacitor Cst, and one or more light-emitting elements LED. In FIG 3, for the sake of simplicity, hatching of the first cladding layer 122b, the second cladding layer 123b, the pixel electrode PE, and the light-emitting element LED is omitted, and the contact electrode CE is omitted.

[0062] 3 and 4, the sub-pixels SP include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. Each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 includes a light-emitting element LED and a pixel circuit, and can independently emit light. For example, the first sub-pixel SP1 may be a red sub-pixel, the second sub-pixel SP2 may be a green sub-pixel, and the third sub-pixel SP3 may be a blue sub-pixel, but is not limited thereto.

[0063] The display panel PN includes a substrate 110, a buffer layer 111, a gate insulating layer 112, an interlayer insulating layer 113, a first passivation layer 114, a first planarization layer 115, a second passivation layer 116, a third passivation layer 117, and a second planarization layer 118.

[0064] On the substrate 110, a high potential power supply line VL1, a plurality of data lines DL, a reference line VL3, an assembly line AL, a light shielding layer LS, and a first capacitor electrode SC1 are arranged.

[0065] The high potential power supply wiring VL1 is a wiring that transmits a high potential power supply voltage to each of the sub-pixels SP. The high potential power supply wirings VL1 can transmit the high potential power supply voltage to the second transistor T2 of each of the sub-pixels SP. The high potential power supply wiring VL1 can extend along the column direction between the sub-pixels SP. For example, the high potential power supply wiring VL1 can be disposed along the column direction between the first sub-pixel SP1 and the third sub-pixel SP3. The high potential power supply wiring VL1 can transmit the high potential power supply voltage to each of the sub-pixels SP disposed in the row direction through the auxiliary high potential power supply wiring AVL1 described later. In this case, the high potential voltage wiring VL1 can be referred to as a first power supply wiring. The column direction can be referred to as a first direction, and the row direction can be referred to as a second direction.

[0066] The data lines DL are lines that transmit a data voltage Vdata to each of the subpixels SP. The data lines DL may be connected to the first transistors T1 of each of the subpixels SP. The data lines DL may extend in the column direction between the subpixels SP. For example, the data line DL extending in the column direction between the first subpixel SP1 and the high potential power line VL1 may transmit the data voltage Vdata to the first subpixel SP1, the data line DL disposed between the first subpixel SP1 and the second subpixel SP2 may transmit the data voltage Vdata to the second subpixel SP2, and the data line DL disposed between the third subpixel SP3 and the high potential power line VL1 may transmit the data voltage Vdata to the third subpixel SP3.

[0067] The reference wiring VL3 is a wiring that transmits a reference voltage to each of the subpixels SP. The reference wiring VL3 may be connected to the third transistor T3 of each of the subpixels SP. The reference wiring VL3 may extend in the column direction between the subpixels SP. For example, the reference wiring VL3 may extend in the column direction between the second subpixel SP2 and the third subpixel SP3. The third drain electrodes DE3 of the third transistors T3 of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 adjacent to the reference wiring VL3 may extend in the row direction and be electrically connected to the reference wiring VL3. In this case, the reference voltage wiring VL3 may be referred to as a third power supply wiring.

[0068] In each of the sub-pixels SP, a light blocking layer LS is disposed on the substrate 110. The light blocking layer LS may block light incident on a transistor below the substrate 110 to minimize leakage current. For example, the light blocking layer LS may block light incident on a second active layer ACT2 of a second transistor T2, which is a driving transistor.

[0069] In each of the sub-pixels SP, a first capacitor electrode SC1 is disposed on the substrate 110. The first capacitor electrode SC1 may form a storage capacitor Cst together with other capacitor electrodes. The first capacitor electrode SC1 may be formed integrally with the light blocking layer LS.

[0070] A buffer layer 111 is disposed on the high potential power supply line VL1, the plurality of data lines DL, the reference line VL3, the light shielding layer LS, and the first capacitor electrode SC1. The buffer layer 111 can reduce the penetration of moisture or impurities through the substrate 110. The buffer layer 111 can be composed of, for example, a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. However, the buffer layer 111 may be omitted depending on the type of substrate 110 or the type of transistor, but is not limited thereto.

[0071] First, a first transistor T1 is disposed on the buffer layer 111 in each of the sub-pixels SP. The first transistor T1 is a transistor that transmits a data voltage Vdata to a second gate electrode GE2 of the second transistor T2. The first transistor T1 may be turned on by a scan signal from a scan line SL, and the data voltage Vdata may be transmitted from a data line DL to the second gate electrode GE2 of the second transistor T2 through the turned-on first transistor T1. Therefore, the first transistor T1 may be referred to as a switching transistor.

[0072] The first transistor T1 includes a first active layer ACT1, a first gate electrode GE1, a first source electrode SE1, and a first drain electrode DE1.

[0073] A first active layer ACT1 is disposed on the buffer layer 111. The first active layer ACT1 may be made of a semiconductor material such as, but not limited to, an oxide semiconductor, amorphous silicon, or polysilicon.

[0074] A gate insulating layer 112 is disposed on the first active layer ACT1. The gate insulating layer 112 is an insulating layer for insulating the first active layer ACT1 and the first gate electrode GE1, and may be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0075] A first gate electrode GE1 is disposed on the gate insulating layer 112. The first gate electrode GE1 may be electrically connected to the scan line SL. The first gate electrode GE1 may be made of a conductive material, for example, but is not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0076] An interlayer insulating layer 113 is disposed on the first gate electrode GE1. Contact holes are formed in the interlayer insulating layer 113 for connecting the first source electrode SE1 and the first drain electrode DE1 to the first active layer ACT1. The interlayer insulating layer 113 is an insulating layer for protecting the components below the interlayer insulating layer 113, and may be formed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0077] A first source electrode SE1 and a first drain electrode DE1 electrically connected to the first active layer ACT1 are disposed on the interlayer insulating layer 113. The first drain electrode DE1 may be connected to the data line DL and the first active layer ACT1, and the first source electrode SE1 may be connected to the first active layer ACT1 and the second gate electrode GE2 of the second transistor T2. The first source electrode SE1 and the first drain electrode DE1 may be made of a conductive material, for example, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0078] A second transistor T2 is disposed on the buffer layer 111 in each of the sub-pixels SP. The second transistor T2 is a transistor that supplies a driving current to the light-emitting element LED. The second transistor T2 can be turned on to control the driving current flowing through the light-emitting element LED. Therefore, the second transistor T2 that controls the driving current can be referred to as a driving transistor.

[0079] The second transistor T2 includes a second active layer ACT2, a second gate electrode GE2, a second source electrode SE2, and a second drain electrode DE2.

[0080] A second active layer ACT2 is disposed on the buffer layer 111. The second active layer ACT2 may be made of a semiconductor material such as, but not limited to, an oxide semiconductor, amorphous silicon, or polysilicon.

[0081] A gate insulating layer 112 is disposed on the second active layer ACT2, and a second gate electrode GE2 is disposed on the gate insulating layer 112. The second gate electrode GE2 may be electrically connected to the first source electrode SE1 of the first transistor T1. The second gate electrode GE2 may be made of a conductive material, for example, but is not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0082] The size of the second active layer ACT2 may vary depending on the type of the light emitting element LED connected to the second transistor T2. In this case, the type of the light emitting element LED means the type of light to be emitted, so the size of the second active layer ACT2 may vary depending on whether the light emitting element LED is a red light emitting element, a green light emitting element, or a blue light emitting element. Since the larger the size of the second active layer ACT2 is, the larger the magnitude of the driving current is, the larger the size of the second active layer ACT2 is, so the size of the second active layer ACT2 may be determined depending on the efficiency of the light emitting element LED.

[0083] 3, the size of the second active layer ACT2 arranged in the first subpixel SP1 is the largest, the size of the second active layer ACT2 arranged in the second subpixel SP2 is smaller than the size of the second active layer ACT2 arranged in the first subpixel SP1, and the size of the second active layer ACT2 arranged in the third subpixel SP3 is smaller than the size of the second active layer ACT2 arranged in the second subpixel SP2. In this case, the light-emitting element LED arranged in the first subpixel SP1 may be a red light-emitting element, the light-emitting element LED arranged in the second subpixel SP2 may be a green light-emitting element, and the light-emitting element LED arranged in the third subpixel SP3 may be a blue light-emitting element, but is not limited thereto.

[0084] An interlayer insulating layer 113 is disposed on the second gate electrode GE2, and a second source electrode SE2 and a second drain electrode DE2 electrically connected to the second active layer ACT2 are disposed on the interlayer insulating layer 113. The second drain electrode DE2 may be electrically connected to the second active layer ACT2 and the high potential power wiring VL1, and the second source electrode SE2 may be electrically connected to the second active layer ACT2 and the light emitting element LED. The second source electrode SE2 and the second drain electrode DE2 may be made of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but are not limited thereto.

[0085] A third transistor T3 is disposed on the buffer layer 111 in each of the sub-pixels SP. The third transistor T3 is a transistor for compensating for a threshold voltage of the second transistor T2. The third transistor T3 is connected between the second source electrode SE2 of the second transistor T2 and the reference wiring VL3. The third transistor T3 is turned on to transmit a reference voltage to the second source electrode SE2 of the second transistor T2 to sense the threshold voltage of the second transistor T2. Thus, the third transistor T3 sensing the characteristic of the second transistor T2 may be referred to as a sensing transistor.

[0086] The third transistor T3 includes a third active layer ACT3, a third gate electrode GE3, a third source electrode SE3 and a third drain electrode DE3.

[0087] A third active layer ACT3 is disposed on the buffer layer 111. The third active layer ACT3 may be made of a semiconductor material such as, but not limited to, an oxide semiconductor, amorphous silicon, or polysilicon.

[0088] A gate insulating layer 112 is disposed on the third active layer ACT3, and a third gate electrode GE3 is disposed on the gate insulating layer 112. The third gate electrode GE3 may be electrically connected to a scan line SL. The third gate electrode GE3 may be made of a conductive material, for example, but is not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0089] An interlayer insulating layer 113 is disposed on the third gate electrode GE3, and a third source electrode SE3 and a third drain electrode DE3 electrically connected to the third active layer ACT3 are disposed on the interlayer insulating layer 113. The third drain electrode DE3 may be electrically connected to the third active layer ACT3 and a reference wiring RL, and the third source electrode SE3 may be electrically connected to the third active layer ACT3 and a second source electrode SE2 of the second transistor T2. The third source electrode SE3 and the third drain electrode DE3 may be made of a conductive material, for example, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0090] The first transistor T1 and the third transistor T3 shown in FIG. 3 are both transistors connected to the scan line SL and controlled, but are not limited thereto, and the pixel circuit may include a transistor connected to the light emitting line EL.

[0091] Next, a second capacitor electrode SC2 is disposed on the gate insulating layer 112. The second capacitor electrode SC2 is one of the electrodes forming the storage capacitor Cst, and may be disposed to overlap the first capacitor electrode SC1. The second capacitor electrode SC2 may be integrally formed with the second gate electrode GE2 of the second transistor T2 and may be electrically connected to the second gate electrode GE2. The first capacitor electrode SC1 and the second capacitor electrode SC2 may be disposed spaced apart from each other with the buffer layer 111 and the gate insulating layer 112 interposed therebetween.

[0092] On the interlayer insulating layer 113, a plurality of scan lines SL, an auxiliary high potential power supply line AVL1, a first lower assembly electrode 121, and a third capacitor electrode SC3 are arranged.

[0093] First, the scan line SL is a line that transmits a scan signal SCAN to each of the sub-pixels SP. The scan line SL may extend in the row direction across the sub-pixels SP. The scan line SL may be electrically connected to the first gate electrode GE1 of the first transistor T1 and the third gate electrode GE3 of the third transistor T3 of each of the sub-pixels SP.

[0094] An auxiliary high potential power supply wiring AVL1 is disposed on the interlayer insulating layer 113. The auxiliary high potential power supply wiring AVL1 may be disposed extending in the row direction and crossing the sub-pixels SP. The auxiliary high potential power supply wiring AVL1 may be electrically connected to the high potential power supply wiring VL1 extending in the column direction and the second drain electrodes DE2 of the second transistors T2 of the sub-pixels SP disposed along the row direction.

[0095] A first lower assembly electrode 121 is disposed on the interlayer insulating layer 113. The first lower assembly electrode 121 may be partially formed in a region of the subpixel SP overlapping with the light-emitting element LED. The first lower assembly electrode 121 is disposed to overlap with the light-emitting element LED and second assembly wiring 123 described below, and is electrically connected to the second assembly wiring 123. The first lower assembly electrode 121 is a component disposed in each of the subpixels SP, and is not shared with other subpixels SP.

[0096] A third capacitor electrode SC3 is disposed on the interlayer insulating layer 113. The third capacitor electrode SC3 is an electrode forming a storage capacitor Cst, and may be disposed to overlap the first capacitor electrode SC1 and the second capacitor electrode SC2. The third capacitor electrode SC3 may be integrally formed with the second source electrode SE2 of the second transistor T2 and may be electrically connected to the second source electrode SE2. The second source electrode SE2 may also be electrically connected to the first capacitor electrode SC1 through a contact hole formed in the interlayer insulating layer 113 and the buffer layer 111. Thus, the first capacitor electrode SC1 and the third capacitor electrode SC3 may be electrically connected to the second source electrode SE2 of the second transistor T2.

[0097] The storage capacitor Cst stores a potential difference between the second gate electrode GE2 and the second source electrode SE2 of the second transistor T2 while the light emitting element LED emits light, thereby allowing a constant current to be supplied to the light emitting element LED. The storage capacitor Cst includes a first capacitor electrode SC1 formed on the substrate 110 and connected to the second source electrode SE2, a second capacitor electrode SC2 formed on the buffer layer 111 and the gate insulating layer 112 and connected to the second gate electrode GE2, and a third capacitor electrode SC3 formed on the interlayer insulating layer 113 and connected to the second source electrode SE2, and can store a voltage between the second gate electrode GE2 and the second source electrode SE2 of the second transistor T2.

[0098] A first passivation layer 114 is disposed on the first transistor T1, the second transistor T2, the third transistor T3, and the storage capacitor Cst. The first passivation layer 114 is an insulating layer for protecting the components below the first passivation layer 114, and may be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0099] A first planarization layer 115 is disposed on the first passivation layer 114. The first planarization layer 115 may planarize an upper portion of the substrate 110 on which the plurality of transistors T1, T2, T3 and the storage capacitor Cst are disposed. The first planarization layer 115 may be configured as a single layer or multiple layers and may be made of, for example, a photoresist or an acrylic organic material, but is not limited thereto.

[0100] The first planarization layer 115 and the first passivation layer 114 include an assembly groove LH1 for disposing the light-emitting element LED. The first planarization layer 115 and the first passivation layer 114 cover an edge of the first lower assembly electrode 121 to expose a part of the first lower assembly electrode 121. The assembly groove LH1 is an area where the first planarization layer 115 and the first passivation layer 114 are removed, and a part of the first lower assembly electrode 121 and a part of the interlayer insulating layer 113 are exposed. The assembly groove LH1 may be formed in the same pattern as the pattern of the light-emitting element LED disposed in the assembly groove LH1. However, the size of the assembly groove LH1 is approximately the same as or larger than the size of the light-emitting element LED so that the light-emitting element LED can be disposed in the assembly groove LH1.

[0101] A second passivation layer 116 is disposed on the first planarization layer 115. Specifically, the second passivation layer 116 is disposed not only on the first planarization layer 115 but also on the first lower assembly electrode 121 and the interlayer insulating layer 113 disposed in the assembly groove LH1. The second passivation layer 116 is an insulating layer for protecting the components below the second passivation layer 116, and may be formed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0102] A connection electrode 120 , a plurality of first assembly wirings 122 , and a plurality of second assembly wirings 123 are disposed on the second passivation layer 116 .

[0103] First, a connection electrode 120 is disposed in each of the sub-pixels SP. The connection electrode 120 is an electrode that electrically connects the second transistor T2 and the pixel electrode PE. The connection electrode 120 can be electrically connected to the third capacitor electrode SC3, which is the second source electrode SE2, through a contact hole formed in the second passivation layer 116, the first planarization layer 115, and the first passivation layer 114.

[0104] The connection electrode 120 may have a multi-layer structure including a first connection layer 120a and a second connection layer 120b. The first connection layer 120a is disposed on the second passivation layer 116, and the second connection layer 120b is disposed to cover the first connection layer 120a. The second connection layer 120b may be disposed to surround the entire upper and side surfaces of the first connection layer 120a. The second connection layer 120b is made of a material that is more resistant to corrosion than the first connection layer 120a, and thus may minimize short circuit defects caused by migration between the first connection layer 120a and adjacent wiring during the manufacture of the display device 100. For example, the first connection layer 120a may be made of a conductive material such as copper (Cu) and chromium (Cr), and the second connection layer 120b may be made of molybdenum (Mo), molybdenum titanium (MoTi), and the like, but is not limited thereto.

[0105] A plurality of assembly wirings AL are disposed on the second passivation layer 116. Specifically, the plurality of assembly wirings AL are disposed on the first planarization layer 115 disposed around the assembly groove LH1. The plurality of assembly wirings AL are wirings for transmitting a low potential power supply voltage to the light emitting element LED. The plurality of assembly wirings AL may extend in the column direction in each of the plurality of sub-pixels SP. For example, a pair of assembly wirings AL spaced apart from each other at a certain interval may be disposed in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The pair of assembly wirings AL includes a first assembly wiring 122 and a second assembly wiring 123. Either the first assembly wiring 122 or the second assembly wiring 123 is disposed to overlap with the first lower assembly electrode 121. In FIG. 4, the second assembly wiring 123 is illustrated to overlap with the first lower assembly electrode 121, but is not limited thereto.

[0106] Each of the assembly wirings AL includes a conductive layer and a clad layer. The conductive layer is disposed on the second passivation layer 116, and a clad layer covering the entire upper and side surfaces of the conductive layer is disposed on the conductive layer. Specifically, the first conductive layer 122a and the second conductive layer 123a are disposed on the second passivation layer 116, and the first clad layer 122b and the second clad layer 123b are disposed on the first conductive layer 122a and the second conductive layer 123a. For example, the first conductive layer 122a and the second conductive layer 123a may be made of a conductive material such as copper (Cu) and chromium (Cr). The first clad layer 122b and the second clad layer 123b may be made of a material that is more resistant to corrosion than the first conductive layer 122a and the second conductive layer 123a, such as, but not limited to, molybdenum (Mo), molybdenum titanium (MoTi), etc.

[0107] Specifically, the first cladding layer 122b covers the upper surface and side surfaces of the first conductive layer 122a, and is also disposed on the side surfaces of the first planarization layer 115 and inside the assembly groove LH1. The first cladding layer 122b disposed inside the assembly groove LH1 overlaps with the light emitting element LED. The first cladding layer 122b disposed on the side surfaces of the first planarization layer 115 and inside the assembly groove LH1 may be disposed only in an area corresponding to less than half of the side surfaces of the first planarization layer 115 and inside the assembly groove LH1, rather than entirely covering the side surfaces of the first planarization layer 115 and the inside of the assembly groove LH1. And the second cladding layer 123b covers the upper surface and side surfaces of the second conductive layer 123a, and is not disposed on the side surfaces of the first planarization layer 115 and inside the assembly groove LH1.

[0108] The first cladding layer 122b and the first lower assembly electrode 121 disposed inside the assembly groove LH1 are disposed on different layers, so that the distance between the first cladding layer 122b and the first lower assembly electrode 121 can be reduced. The narrower the distance between the assembly electrodes disposed inside the assembly groove LH1 for assembling the light emitting element LED, the greater the strength of the electric field, and the greater the assembly force. If the first cladding layer 122b and the first lower assembly electrode 121 are disposed on the same layer, there is a limit to reducing the distance between the first cladding layer 122b and the first lower assembly electrode 121. Therefore, in the display device 100 according to an embodiment of the present specification, the first cladding layer 122b and the first lower assembly electrode 121, which are disposed inside the assembly groove LH1 and form an electric field, are disposed on different layers, so that the assembly force for assembling the light emitting element LED can be improved.

[0109] The second conductive layer 123a disposed in each of the sub-pixels SP is electrically connected to the first lower assembly electrode 121 through the wiring contact electrode LCE. The wiring contact electrode LCE is disposed in a wiring contact hole LH2 formed in the second passivation layer 116, the first planarization layer 115, and the first passivation layer 114. The wiring contact hole LH2 may be formed through two contact hole forming processes. The first wiring contact hole LH2a may be formed through a first contact hole forming process, and the second wiring contact hole LH2b may be formed through a second contact hole forming process. The first wiring contact hole LH2a is a contact hole formed in the first planarization layer 115 and the first passivation layer 114, and the second wiring contact hole LH2b is a contact hole formed in the second passivation layer 116. That is, the wiring contact hole LH2 may include a first wiring contact hole LH2a and a second wiring contact hole LH2b. In this case, in order to align the first wiring contact hole LH2a and the second wiring contact hole LH2b, the size of the first wiring contact hole LH2a may be larger than the size of the second wiring contact hole LH2b.

[0110] Meanwhile, the second lower assembly electrode 125 is disposed on the second passivation layer 116. The second lower assembly electrode 125 may be formed of the same material and in the same process as the first cladding layer 122b, the second cladding layer 123b, and the second connection layer 120b. The second lower assembly electrode 125 is disposed inside the assembly groove LH1 and directly contacts the light emitting element LED. The second lower assembly electrode 125 is spaced apart from the first cladding layer 122b and partially overlaps the first lower assembly electrode 121. Before the light emitting element LED is disposed, the second lower assembly electrode 125 is coupled to a signal applied through the first lower assembly electrode 121 in a floating state and can function as an assembly wiring. Not only the assembly wiring AL, but also the first lower assembly electrode 121 electrically connected to the assembly wiring AL and the second lower assembly electrode 125 coupled to the first lower assembly electrode 121 can form an electric field for self-assembling the light emitting element LED.

[0111] A third passivation layer 117 is disposed on the connection electrode 120 and the assembly wiring AL. Specifically, the third passivation layer 117 exposes the entire second lower assembly electrode 125 and a part of the assembly wiring AL to the outside. The third passivation layer 117 is an insulating layer for protecting the components below the third passivation layer 117, and may be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0112] Next, a plurality of light-emitting elements LED are disposed on the third passivation layer 117 and the second lower assembly electrode 125. The light-emitting element LED is disposed inside the assembly groove LH1. One or more light-emitting elements LED are disposed in one sub-pixel SP. The light-emitting element LED is an element that emits light by electric current. The light-emitting element LED may include light-emitting elements LED that emit red light, green light, blue light, etc., and various hues including white light can be realized by combining these. In addition, various hues of light can be realized by using a light-emitting element LED that emits light of a specific hue and a light conversion member that converts light from the light-emitting element LED into light of another hue. The light-emitting element LED is electrically connected between the second transistor T2 and the assembly wiring AL, and can emit light by receiving a driving current from the second transistor T2.

[0113] In this case, the multiple light-emitting elements LED arranged in one subpixel SP may be connected in parallel, that is, one electrode of each of the multiple light-emitting elements LED may be connected to the source electrode of the same second transistor T2, and the other electrode may be connected to the same assembly wiring AL.

[0114] Meanwhile, the light emitting element LED arranged in each of the sub-pixels SP may have different structures. For example, the light emitting element LED may include a first light emitting element 130 and a second light emitting element 140. The first light emitting element 130 may be arranged in a first sub-pixel SP1 of the sub-pixels SP, and the second light emitting element 140 may be arranged in a second sub-pixel SP2 and a third sub-pixel SP3 of the sub-pixels SP. However, the types of the light emitting element LED are merely examples, and only one of the first light emitting element 130 or the second light emitting element 140 may be used as the light emitting element LED, or other types of light emitting element LED may be used, and are not limited thereto. Also, in FIG. 4 and FIG. 5, for convenience of explanation, two light emitting element LEDs are arranged in each of the sub-pixels SP, but the number of light emitting element LEDs arranged in each of the sub-pixels SP is not limited thereto.

[0115] 4, a first light emitting element 130 of the plurality of light emitting elements LED includes a first semiconductor layer 131, a light emitting layer 132, a second semiconductor layer 133, a first electrode 134, a second electrode 135 and a sealing layer 136.

[0116] A first semiconductor layer 131 is disposed on the third passivation layer 117, and a second semiconductor layer 133 is disposed on the first semiconductor layer 131. The first semiconductor layer 131 and the second semiconductor layer 133 may be layers formed by doping a specific material with n-type and p-type impurities. For example, the first semiconductor layer 131 and the second semiconductor layer 133 may be layers formed by doping a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), gallium arsenide (GaAs), etc. with p-type or n-type impurities. The p-type impurities may be magnesium (Mg), zinc (Zn), beryllium (Be), etc., and the n-type impurities may be silicon (Si), germanium (Ge), tin (Sn), etc., but are not limited thereto.

[0117] A portion of the first semiconductor layer 131 may be disposed to protrude outward from the second semiconductor layer 133. The top surface of the first semiconductor layer 131 may include a portion overlapping the bottom surface of the second semiconductor layer 133 and a portion disposed outside the bottom surface of the second semiconductor layer 133. However, the sizes and shapes of the first semiconductor layer 131 and the second semiconductor layer 133 may be modified in various ways and are not limited thereto.

[0118] The light emitting layer 132 is disposed between the first semiconductor layer 131 and the second semiconductor layer 133. The light emitting layer 132 can emit light by receiving holes and electrons from the first semiconductor layer 131 and the second semiconductor layer 133. The light emitting layer 132 can have a single layer or a multi-quantum well (MQW) structure and can be made of, for example, indium gallium nitride (InGaN) or gallium nitride (GaN), but is not limited thereto.

[0119] A first electrode 134 is disposed surrounding the bottom and side surfaces of the first semiconductor layer 131. The first electrode 134 is an electrode for electrically connecting the first light emitting element 130 to the assembly wiring AL. The first electrode 134 may be made of a conductive material, for example, a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, but is not limited thereto.

[0120] The second electrode 135 is disposed on an upper surface of the second semiconductor layer 133. The second electrode 135 is an electrode that electrically connects a pixel electrode PE, which will be described later, to the second semiconductor layer 133. The second electrode 135 may be made of a conductive material, for example, a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), but is not limited thereto.

[0121] An encapsulation layer 136 is disposed to surround at least a portion of the first semiconductor layer 131, the light emitting layer 132, the second semiconductor layer 133, the first electrode 134, and the second electrode 135. The encapsulation layer 136 is made of an insulating material and can protect the first semiconductor layer 131, the light emitting layer 132, and the second semiconductor layer 133. The encapsulation layer 136 can be disposed to cover the light emitting layer 132, a portion of a side surface of the first semiconductor layer 131 adjacent to the light emitting layer 132, and a portion of a side surface of the second semiconductor layer 133 adjacent to the light emitting layer 132. The first electrode 134 and the second electrode 135 can be exposed from the encapsulation layer 136, and the first electrode 134 and the second electrode 135 can be electrically connected to a chip contact electrode CCE and a pixel electrode PE to be formed later.

[0122] 5, the second light emitting element 140 includes a first semiconductor layer 141, a light emitting layer 142, a second semiconductor layer 143, a first electrode 144, a second electrode 145, and a sealing layer 146. The first semiconductor layer 141, the light emitting layer 142, the second semiconductor layer 143, the second electrode 145, and the sealing layer 146 of the second light emitting element 140 may be substantially the same as the first semiconductor layer 131, the light emitting layer 132, the second semiconductor layer 133, the second electrode 135, and the sealing layer 136 of the first light emitting element 130. However, the second light emitting element 140 differs from the first light emitting element 130 only in the structure of the first electrode 144, and the other configurations are substantially the same.

[0123] The first electrode 144 of the second light emitting element 140 is disposed so as to contact only the lower surface of the first semiconductor layer 141. Compared to the first light emitting element 130 in which the first electrode 134 covers both the lower surface and the side surface of the first semiconductor layer 131, in the second light emitting element 140, the first electrode 144 is disposed only on the lower surface of the first semiconductor layer 141, so that the side surface of the first semiconductor layer 141 of the second light emitting element 140 may be exposed from the first electrode 144. Thus, the chip contact electrode CCE may be electrically connected to the second light emitting element 140 by contacting the side surface of the first semiconductor layer 141 and the side surface of the first electrode 144.

[0124] Next, an adhesive layer may be disposed between the light emitting elements LED and the third passivation layer 117 and the second lower assembly electrode 125. The adhesive layer may be an organic film that temporarily fixes the light emitting elements LED during the self-assembly process of the light emitting elements LED. When the organic film covering the light emitting elements LED is formed during the manufacture of the display device 100, a portion of the organic film fills the space between the light emitting elements LED and the third passivation layer 117 and the second lower assembly electrode 125, so that the light emitting elements LED can be temporarily fixed on the third passivation layer 117 and the second lower assembly electrode 125. Even if the organic film is subsequently removed, a portion of the organic film that has seeped into the lower portion of the light emitting element LED may remain without being removed and may become an adhesive layer. The adhesive layer may be made of an organic material, for example, a photoresist or an acrylic organic material, but is not limited thereto.

[0125] A chip contact electrode CCE is disposed on the side of the light-emitting element LED. The chip contact electrode CCE is an electrode for electrically connecting the light-emitting element LED and the assembly wiring AL, and is also disposed on the upper part of the assembly wiring AL where the third passivation layer 117 is not disposed and on the second passivation layer 116 disposed on the side of the assembly groove LH1. The chip contact electrode CCE can also cover an edge part of the assembly wiring AL. The chip contact electrode CCE is disposed to surround at least a part of the first semiconductor layers 131, 141 and the first electrodes 134, 144 of the light-emitting element LED, and can electrically connect the first semiconductor layers 131, 141 and the first electrodes 134, 144 to the assembly wiring AL. In this case, the chip contact electrode CCE is also connected to the second lower assembly electrode 125. The second lower assembly electrode 125, which is in direct contact with the lower surfaces of the first electrodes 134, 144 to electrically connect the second assembly wiring 123 to the light-emitting element LED, is also connected, so that the contact resistance of the second assembly wiring 123 can be reduced. This can improve the lighting rate of the light emitting element LED, which may refer to the ratio of the number of light emitting element LEDs that normally emit light to the total number of light emitting element LEDs arranged on the display panel.

[0126] Then, a second planarization layer 118 is disposed on the light emitting element LED and the chip contact electrode CCE. The second planarization layer 118 may planarize the upper portion of the substrate 110 on which the light emitting element LED is disposed, and may fix the light emitting element LED onto the substrate 110 together with an adhesive layer. The light emitting element LED included in the display device 100 according to an embodiment of the present specification is disposed inside the assembly groove LH1 formed in the first planarization layer 115, thereby reducing the thickness of the second planarization layer 118 and forming a single layer. However, without being limited thereto, the second planarization layer 118 may be formed as a single layer or multiple layers and may be made of, for example, a photoresist or an acrylic organic material, but is not limited thereto.

[0127] A protective layer 119 is disposed on the second planarization layer 118 and the light-emitting element LED. The protective layer 119 is disposed in an area excluding a part of the second electrodes 135, 145 of the light-emitting element LED. The protective layer 119 is an insulating layer for protecting the components below the protective layer 119, and may be formed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0128] A pixel electrode PE is disposed on the protective layer 119. The pixel electrode PE is an electrode for electrically connecting a plurality of light emitting elements LED and the connection electrode 120. The pixel electrode PE may be electrically connected to the light emitting element LED, the connection electrode 120, and the second transistor T2 through a contact hole formed in the second planarization layer 118. Therefore, the second electrodes 135 and 145 of the light emitting element LED, the connection electrode 120, and the second source electrode SE2 of the second transistor T2 may be electrically connected to each other through the pixel electrode PE. The pixel electrode PE may be made of a conductive material, for example, a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), but is not limited thereto.

[0129] In the display device 100 according to an embodiment of the present specification, a pair of assembly wirings AL arranged in each of the sub-pixels SP, a first lower assembly electrode 121 connected to any one of the pair of assembly wirings AL, and a second lower assembly electrode 125 arranged to overlap the first lower assembly electrode 121 are electrodes for self-assembling the light emitting element LED. During the manufacture of the display device 100, the first lower assembly electrode 121 and the second lower assembly electrode 125 may form an electric field together with the pair of assembly wirings AL to self-assemble the light emitting element LED.

[0130] Hereinafter, a method for self-assembling the light-emitting element LED of the display device 100 according to an embodiment of the present disclosure will be described with reference to FIGS. 6a and 6b.

[0131] 6a and 6b are cross-sectional views illustrating a manufacturing process of a display device according to an embodiment of the present specification.

[0132] First, referring to FIG. 6A, a buffer layer 111 and an interlayer insulating layer 113 are formed on a substrate 110, and a first lower assembly electrode 121 is formed on the interlayer insulating layer 113.

[0133] Next, a first passivation layer 114, a first planarization layer 115, and a second passivation layer are sequentially formed on the first lower assembly electrode 121, and an assembly electrode AL and a second lower assembly electrode 125 are formed on the second passivation layer .

[0134] The second assembly wiring 123, the first lower assembly electrode 121, and the second lower assembly electrode 125 can function as a pair of low potential power supply wirings after the manufacture of the display device 100 is completed. Different voltages are applied to two adjacent assembly electrodes AL during the manufacturing process of the display device 100, and the same low potential power supply voltage can be applied to the two adjacent assembly electrodes AL after the manufacturing process of the display device 100 is completed.

[0135] The first assembly wiring 122 disposed on the second passivation layer 116 includes a first conductive layer 122a and a first cladding layer 122b covering the first conductive layer 122a.

[0136] The second assembly wiring 123 is disposed on the second passivation layer 116. The second assembly wiring 123 includes a second conductive layer 123a and a second cladding layer 123b covering the second conductive layer 123a. The second conductive layer 123a of the second assembly wiring 123 may be electrically connected to the first lower assembly electrode 125 through contact holes formed in the second passivation layer 116, the first planarization layer 115, and the first passivation layer 114. Thus, the formation of an assembly electrode including the assembly wiring AL and the lower assembly electrodes 121, 125 can be completed.

[0137] Next, a third passivation layer 117 is formed on the assembly electrode AL, and an organic layer DAL having an opening DALH is formed on the third passivation layer 117. The opening DALH of the organic layer DAL may correspond to an area where the light-emitting element LED is self-assembled. The opening DALH of the organic layer DAL may overlap the assembly wiring AL and the lower assembly electrodes 121, 125. The organic layer DAL is removed after the self-assembly of the light-emitting element LED is completed, and is not present in the display device 100 completed during the manufacturing process.

[0138] The substrate 110 on which the organic layer DAL is formed and the light emitting element LED are placed inside a chamber filled with a fluid, and an AC voltage is applied to the assembly electrodes including the assembly wiring AL and the lower assembly electrodes 121 and 125 to form an electric field. For example, the same voltage is applied to the second assembly wiring 123 and the first lower assembly electrode 121, and the second lower assembly electrode 125 is coupled to the first lower assembly electrode 121 so that a voltage is also formed on the second lower assembly electrode 125, and the second lower assembly electrode 125 can function as an assembly electrode. An electric field can be formed between the first assembly wiring 122 and the second assembly wiring 123, the first lower assembly electrode 121, and the second lower assembly electrode 125.

[0139] The light-emitting element LED may be dielectrically polarized by an electric field to have a polarity. The dielectrically polarized light-emitting element LED may be moved or fixed in a specific direction by dielectrophoresis (DEP), i.e., an electric field. Therefore, a plurality of light-emitting elements LED may be self-assembled inside the assembly wiring AL and the upper opening DALH of the lower assembly electrodes 121 and 125 by using dielectrophoresis.

[0140] After the light emitting element LED is self-assembled inside the opening DALH, the first electrodes 134, 144 of the light emitting element LED and the second lower assembly electrode 125 are in contact with each other and are conductive with each other, so that the second lower assembly electrode 125 is in a state of being integrated with the first electrodes 134, 144. As a result, the light emitting element LED can be stably fixed to the substrate 110 even after being self-assembled.

[0141] Finally, when the self-assembly of the light-emitting element LED is completed, the organic layer DAL is removed, and other components such as the second planarization layer 118 and the pixel electrode PE are formed, thereby completing the manufacturing process of the display device 100.

[0142] Meanwhile, the force of dielectrophoresis is proportional to the size of the light emitting device LED and the strength of the electric field. As the size of the light emitting device LED increases or the strength of the electric field increases, the dielectrophoresis becomes stronger, and the assembly rate can be improved.

[0143] Therefore, in the display device 100 according to an embodiment of the present specification, the strength of the electric field may be increased to increase dielectrophoresis. As described above, by disposing the first lower assembly electrode 121 and the first cladding layer 122b on different layers, the distance between the first lower assembly electrode 121 and the first cladding layer 122b is narrowed, thereby increasing the strength of the electric field and improving the self-assembly rate.

[0144] An embodiment of the present invention can also be described as follows.

[0145] According to an aspect of the present invention, a display device includes a substrate including a plurality of subpixels, a first lower assembly electrode arranged in the plurality of subpixels, a first assembly wiring arranged in the plurality of subpixels and arranged in a layer different from the first lower assembly electrode, a light-emitting element arranged on the first lower assembly electrode and the first assembly wiring and including a first electrode, a semiconductor layer, and a second electrode, and a second lower assembly electrode arranged between the first lower assembly electrode and the light-emitting element and electrically connected to the first electrode or the second electrode.

[0146] According to another feature herein, the first lower assembly electrode and the second lower assembly electrode can be electrically connected.

[0147] According to another feature of the present specification, the first assembly wiring and the first electrode may be electrically connected. The display device may further include a chip contact electrode connecting the first assembly wiring and the first electrode, and the chip contact electrode may contact a side surface of the light-emitting element. The first assembly wiring may be connected to a low potential power pad to which a low potential power supply is applied.

[0148] According to another feature of the present specification, the display device further includes a planarization layer covering a portion of the first lower assembly electrode and including an assembly groove, and a light-emitting element can be disposed in the assembly groove. The display device further includes a second assembly wiring disposed on the planarization layer, and the second assembly wiring can be connected to the first lower assembly electrode through a contact hole in the planarization layer. The second assembly wiring can be connected to a low-potential power supply pad to which a low-potential power supply is applied. In addition, the first assembly wiring includes a first conductive layer disposed on the planarization layer and a first clad layer covering the first conductive layer, and the second assembly wiring can include a second conductive layer disposed on the planarization layer and a second clad layer covering the second conductive layer.

[0149] According to another aspect of the present invention, a display device includes a substrate including a plurality of subpixels, first and second assembly wirings arranged in parallel with the plurality of subpixels, a light-emitting element arranged overlapping the first assembly wiring or the second assembly wiring, and a first lower auxiliary electrode and a second lower auxiliary electrode overlapping the light-emitting element and one of the first and second assembly wirings below the light-emitting element.

[0150] According to another feature of the present specification, the first assembly wiring and the second assembly wiring may be shared by a plurality of sub-pixels arranged in a first direction on a substrate.

[0151] According to another feature of the present specification, the display device may further include a low-potential voltage pad disposed on one side of the substrate to which a low-potential power supply is applied, and the first assembly wiring and the second assembly wiring may be connected to the low-potential voltage pad.

[0152] According to another feature of the present specification, the light emitting element may be a plurality of light emitting elements, and at least two light emitting elements may be arranged in each of the plurality of sub-pixels.

[0153] According to another feature of the present specification, the light emitting device may further include a driving transistor disposed on the substrate and electrically connected to the light emitting element, and the driving transistor may be disposed in each of the plurality of sub-pixels, and sizes of the driving transistors disposed in at least two of the sub-pixels may be different from each other.

[0154] According to another feature of the present specification, the light-emitting element includes a first electrode, a semiconductor layer, and a second electrode, and the second lower auxiliary electrode is disposed between the first lower auxiliary electrode and the light-emitting element and may be in contact with the first electrode or the second electrode.

[0155] Although the embodiments of the present invention have been described in detail above with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications can be made within the scope of the technical idea of ​​the present invention. Therefore, the embodiments disclosed in the present invention are for illustration purposes, not for limiting the technical idea of ​​the present invention, and the scope of the technical idea of ​​the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative and not restrictive in all respects. The scope of protection of the present invention should be interpreted according to the following claims, and all technical ideas within the scope equivalent thereto should be interpreted as being included in the scope of the present invention. [Explanation of symbols]

[0156] 100 display device 110 Substrate 120 Connection electrode

Claims

1. a substrate including a plurality of sub-pixels; a first lower assembly electrode disposed in the plurality of sub-pixels; a first assembly wiring disposed in the plurality of sub-pixels and disposed in a layer different from the first lower assembly electrode; a light emitting device disposed on the first lower assembly electrode and the first assembly wiring, the light emitting device including a first electrode, a semiconductor layer, and a second electrode; a second lower assembly electrode disposed between the first lower assembly electrode and the light emitting element and electrically connected to the first electrode or the second electrode; a planarization layer covering a portion of the first lower assembly electrode and including an assembly groove; and a second assembly wiring disposed on the planarization layer.

2. The display device according to claim 1 , wherein the first lower assembly electrode and the second lower assembly electrode are electrically connected to each other.

3. The display device according to claim 1 , wherein the first assembly wiring and the first electrode are electrically connected to each other.

4. further comprising a chip contact electrode connecting the first assembly wiring and the first electrode; The display device according to claim 3 , wherein the chip contact electrode is in contact with a side surface of the light emitting element.

5. The display device according to claim 3 , wherein the first assembly wiring is connected to a low potential power supply pad to which a low potential power supply is applied.

6. A display device as described in claim 1, wherein the light-emitting element is arranged in the assembly groove.

7. A display device as described in Claim 6, wherein the second assembly wiring is connected to the first lower assembly electrode through a contact hole in the planarization layer.

8. The display device according to claim 7 , wherein the second assembly wiring is connected to a low potential power supply pad to which a low potential power supply is applied.

9. the first assembly wiring includes a first conductive layer disposed on the planarization layer and a first clad layer covering the first conductive layer; The display device according to claim 7 , wherein the second assembly wiring includes a second conductive layer disposed on the planarization layer and a second cladding layer covering the second conductive layer.

10. a substrate including a plurality of sub-pixels; a first assembly wiring and a second assembly wiring arranged in parallel to the plurality of sub-pixels; A plurality of light emitting elements are disposed on the substrate, each of which overlaps with the first assembly wiring or the second assembly wiring; A display device comprising: a wiring of either the first assembly wiring or the second assembly wiring below the light emitting element; and a first lower assembly electrode and a second lower assembly electrode overlapping the light emitting element.

11. The display device according to claim 10 , wherein the first assembly wiring and the second assembly wiring are shared by the plurality of sub-pixels arranged in a first direction on the substrate.

12. The low-potential voltage pad is disposed on one surface of the substrate and receives a low-potential power supply. The display device according to claim 10 , wherein the first assembly wiring and the second assembly wiring are connected to the low potential voltage pad.

13. The display device according to claim 10 , wherein at least two light-emitting elements are arranged in each of the plurality of sub-pixels.

14. The display device according to claim 10 , further comprising a driving transistor disposed on the substrate and electrically connected to the light emitting element.

15. the driving transistor is disposed in each of the plurality of sub-pixels, The display device according to claim 14 , wherein the driving transistors arranged in at least two sub-pixels have different sizes from each other.

16. Each of the plurality of light emitting elements includes a first electrode, a semiconductor layer, and a second electrode; The display device of claim 10 , wherein the second lower assembly electrode is disposed between the first lower assembly electrode and the light emitting element and is in contact with the first electrode or the second electrode.

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