Display Panel

Abstract

To provide a display panel which avoids the problem of asymmetric light-emitting brightness curves of the light-emitting chips on the left and right sides, so as to eliminate the problem of color deviation when the display panel is viewed from sides.SOLUTION: A display panel includes a plurality light-emitting chips arranged in an array. Each light-emitting chip includes an N pole and a P pole. The light-emitting chips are arranged to share a common N pole or a common P pole. The plurality of light-emitting chips arrange in an array includes an adjacently positioned first column of light-emitting chips and second column of light-emitting chips. The first column of light-emitting chips and the second column of light-emitting chips are mirror-symmetrically positioned.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] This application relates to the field of display technology, and in particular to display panels. [Background technology]

[0002] With the increasing popularity of Mini-LED direct display technology on the market, people's requirements for its image quality are also increasing. When the Mini-LED display screen is turned on in white, the color is different when viewed from the left and right sides, one side appears bluish and the other side appears reddish, which seriously affects the viewing sensation. Summary of the Invention [Problem to be solved by the invention]

[0003] An object of the present application is to provide a display panel that is designed to solve the problem of color cast occurring when viewed from the side of a display panel in the prior art. [Means for solving the problem]

[0004] In a first aspect, the present application provides a display panel, the display panel including a plurality of light emitting chips arranged in an array, each of the light emitting chips including an N pole and a P pole, the plurality of light emitting chips in any one row among the plurality of rows of light emitting chips are arranged with a common N pole or a common P pole; The display panel includes adjacent first and second light-emitting areas, the first light-emitting area including at least one row of light-emitting chips, and the second light-emitting area including at least one row of light-emitting chips, and the at least one row of light-emitting chips in the first light-emitting area and the at least one row of light-emitting chips in the second light-emitting area are mirror symmetrical.

[0005] In some possible embodiments, the first light-emitting region includes a first row of light-emitting chips, the second light-emitting region includes a second row of light-emitting chips, the N poles of the light-emitting chips in the first row and the N poles of the light-emitting chips in the second row are mirror-symmetric, and the P poles of the light-emitting chips in the first row and the P poles of the light-emitting chips in the second row are mirror-symmetric.

[0006] In some possible embodiments, the shortest distance between the N pole of the light-emitting chip in the first row and the N pole of the light-emitting chip in the second row is shorter than the shortest distance between the N pole of the light-emitting chip in the first row and the P pole of the light-emitting chip in the second row.

[0007] In some possible embodiments, the shortest distance between the P pole of the light-emitting chip in the first row and the P pole of the light-emitting chip in the second row is shorter than the distance between the P pole of the light-emitting chip in the first row and the N pole of the light-emitting chip in the second row.

[0008] In some possible embodiments, the first light-emitting region includes adjacent third row of light-emitting chips and first row of light-emitting chips, the second light-emitting region includes adjacent second row of light-emitting chips and fourth row of light-emitting chips, the third row of light-emitting chips and the first row of light-emitting chips are mirror-symmetric, and the second row of light-emitting chips and the fourth row of light-emitting chips are mirror-symmetric.

[0009] In some possible embodiments, the shortest distance between the N pole of the light-emitting chip in the third row and the N pole of the light-emitting chip in the first row is shorter than the distance between the N pole of the light-emitting chip in the third row and the P pole of the light-emitting chip in the first row; The shortest distance between the N pole of the light emitting chip in the second row and the N pole of the light emitting chip in the fourth row is shorter than the distance between the N pole of the light emitting chip in the second row and the P pole of the light emitting chip in the fourth row.

[0010] In some possible embodiments, the shortest distance between the N pole of the light-emitting chip in the third row and the N pole of the light-emitting chip in the first row is longer than the distance between the N pole of the light-emitting chip in the third row and the P pole of the light-emitting chip in the first row; The shortest distance between the N pole of the light emitting chip in the second row and the N pole of the light emitting chip in the fourth row is longer than the distance between the N pole of the light emitting chip in the second row and the P pole of the light emitting chip in the fourth row.

[0011] In some possible embodiments, the first light-emitting region includes a fifth row of light-emitting chips and a first row of light-emitting chips adjacent to each other, and the second light-emitting region includes a second row of light-emitting chips and a sixth row of light-emitting chips adjacent to each other; The arrangement method of the PN poles in the light-emitting chips in the fifth row is the same as the arrangement method of the PN poles in the light-emitting chips in the first row, the arrangement method of the PN poles in the light-emitting chips in the second row is the same as the arrangement method of the PN poles in the light-emitting chips in the sixth row, the light-emitting chips in the fifth row and the light-emitting chips in the sixth row are mirror symmetrical, and the light-emitting chips in the first row and the light-emitting chips in the second row are mirror symmetrical.

[0012] In some possible embodiments, the shortest distance between the N pole of the light-emitting chip in the fifth row and the P pole of the light-emitting chip in the first row is shorter than the shortest distance between the N pole of the light-emitting chip in the fifth row and the N pole of the light-emitting chip in the first row; The shortest distance between the N pole of the light emitting chip in the second row and the P pole of the light emitting chip in the sixth row is longer than the shortest distance between the N pole of the light emitting chip in the second row and the N pole of the light emitting chip in the sixth row.

[0013] In some possible embodiments, the shortest distance between the N pole of the light-emitting chip in the fifth row and the P pole of the light-emitting chip in the first row is longer than the shortest distance between the N pole of the light-emitting chip in the fifth row and the N pole of the light-emitting chip in the first row; The shortest distance between the N pole of the light emitting chip in the second row and the P pole of the light emitting chip in the sixth row is shorter than the shortest distance between the N pole of the light emitting chip in the second row and the N pole of the light emitting chip in the sixth row. Effect of the Invention

[0014] The present application provides a display panel, which includes a plurality of light emitting chips arranged in an array, each of the light emitting chips includes an N pole and a P pole, the plurality of light emitting chips are arranged with a common N pole or a common P pole, the plurality of light emitting chips arranged in an array include a first row of light emitting chips and a second row of light emitting chips adjacent to each other, and the first row of light emitting chips and the second row of light emitting chips are arranged in mirror symmetry. The display panel provided in the present application arranges the light emitting chips in two adjacent rows in mirror symmetry, thereby avoiding the asymmetric problem of the light emitting brightness curves of the left and right sides of the light emitting chips, and thereby eliminating the problem of color cast when viewed from the side of the display panel. [Brief description of the drawings]

[0015] In order to more clearly describe the technical solutions in the embodiments of the present application, the following briefly introduces drawings that need to be used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can further derive other drawings based on these drawings without any creative efforts. [Figure 1] 1 is a schematic diagram of a light-emitting chip of a display panel in the prior art; [Diagram 2] 2 is a schematic diagram of one embodiment of a light-emitting chip in a display panel provided in an embodiment of the present application; [Diagram 3] FIG. 2 is a structural schematic diagram of another embodiment of a light emitting chip in a display panel provided in an embodiment of the present application. [Figure 4] FIG. 2 is a structural schematic diagram of another embodiment of a light emitting chip in a display panel provided in an embodiment of the present application. [Diagram 5] FIG. 2 is a structural schematic diagram of another embodiment of a light emitting chip in a display panel provided in an embodiment of the present application. [Figure 6] FIG. 2 is a structural schematic diagram of another embodiment of a light emitting chip in a display panel provided in an embodiment of the present application. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Hereinafter, the technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some of the embodiments of the present application, and not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without any creative efforts are all within the scope of protection of the present application.

[0017] In the description of this application, it should be understood that the orientations or positional relationships indicated by the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc. are based on the orientations or positional relationships shown in the drawings, and are merely for ease of explanation and simplification of the description of this application, and do not indicate or suggest that the devices or elements shown have a particular orientation and must be constructed and operated in a particular orientation, and should not be understood as limiting this application. In addition, the terms "first" and "second" are merely for explanatory purposes and are not to be understood as indicating or implying a relative importance or implying the number of the technical features indicated. Thus, a feature limited to "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, unless otherwise specified and specifically limited, the meaning of "plurality" is two or more than two.

[0018] In this application, the word "exemplary" is used to indicate "serving as an example, illustration, or description." Any embodiment described in this application as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. The following description is given to enable those skilled in the art to realize and use the present application. In the following description, details are enumerated for the sake of interpretation. Of course, it should be recognized that those skilled in the art can realize the present application without the use of these specific details. In other instances, well-known structures and processes are not described in detail to avoid obscuring the description of the present application with unnecessary detail. Thus, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

[0019] The embodiments of the present application provide a display panel, which will be described in detail below.

[0020] 1 is a schematic diagram of a light-emitting chip of a display panel in the prior art. The display panel shown in FIG. 1 includes a plurality of light-emitting chips, which are arranged in an array. Note that the light-emitting chip in the present application is generally a flip chip, and the light patterns on the left and right sides of such a chip are asymmetrical, which causes a color cast problem in the display panel when viewed from the side.

[0021] In order to solve the problem of color cast in the side view of the display panel, the present application provides a new design structure of the light-emitting chip. As shown in FIG. 2, it is a schematic diagram of one embodiment of the light-emitting chip in the display panel provided in the embodiment of the present application. In the embodiment of the display panel shown in FIG. 2, only the structure of some light-emitting chips in the display panel is shown, and does not include all the light-emitting chips in the complete display panel. It should be noted that in the embodiment of the display panel shown in FIG. 2, the display panel includes multiple rows of light-emitting chips arranged in an array, and each of the light-emitting chips includes an N pole and a P pole, and the N pole and the P pole are structures that the light-emitting chip itself has, and the multiple light-emitting chips in any one row of the multiple rows of light-emitting chips are arranged with a common N pole or a common P pole.

[0022] Referring to FIG. 2, in the embodiment shown in FIG. 2, the display panel includes a first light-emitting region 100 and a second light-emitting region 200 adjacent to each other, the first light-emitting region 100 includes at least one row of light-emitting chips 10, and the second light-emitting region 200 similarly includes at least one row of light-emitting chips 20. The light-emitting chips in the first row of light-emitting chips 10 are arranged with a common N pole or a common P pole, and the light-emitting chips in the second row of light-emitting chips are also arranged with a common N pole or a common P pole, that is, the N poles of the light-emitting chips are installed at the same end, or the P poles of the light-emitting chips are installed at the same end. In the embodiment shown in FIG. 2, the light-emitting chips form a structure arranged in an array of multiple rows and multiple columns, and the N poles of the light-emitting chips in the same column are connected to the same scan line, or the P poles of the light-emitting chips in the same column are connected to the same scan line.

[0023] Moreover, in the embodiment of the display panel shown in FIG. 2, the light emitting chips 10 in the first row and the light emitting chips 20 in the second row are installed in a mirror symmetrical manner, and the N pole and P pole of the light emitting chips 10 in the first row and the N pole and P pole of the light emitting chips 20 in the second row can be mirror symmetrical. Specifically, the N pole of the light emitting chips 10 in the first row and the N pole of the light emitting chips 20 in the second row are mirror symmetrical, and the P pole of the light emitting chips 10 in the first row and the P pole of the light emitting chips 20 in the second row are mirror symmetrical. With reference to FIG. 1, the multiple light emitting chips in the prior art shown in FIG. 1 are also arranged in an array, but the scanning lines corresponding to each of the multiple light emitting chips are all installed on the right or left side of the light emitting chips. In the multiple light emitting chips provided in the present application shown in FIG. 2, the scanning lines corresponding to some of the light emitting chips are installed on the left side of the chips, and the scanning lines corresponding to some of the light emitting chips are installed on the right side of the chips, and thus the multiple light emitting chips are mirror symmetrical.

[0024] When the first row of light-emitting chips 10 and the second row of light-emitting chips 20 are installed in this manner, the electrodes of the same polarity (N pole or P pole) of the light-emitting chips in different rows are simultaneously located on the outside or inside of the entire structure. Specifically, referring to FIG. 2, the first row of light-emitting chips 10, which are mirror-symmetrical, have their P poles located on the outside and their N poles located on the inside, and the second row of light-emitting chips 20 are mirror-symmetrical with the first row of light-emitting chips 10, so that the second row of light-emitting chips also have their P poles located on the outside and their N poles located on the inside, thus realizing mirror symmetry. In this case, the P poles of the adjacent first row of light-emitting chips and the P poles of the adjacent second row of light-emitting chips are both located on the outside, so that the N poles and P poles are simultaneously located on the outermost side, and therefore there is no problem of color cast in side view due to different electrodes.

[0025] The display panel provided in the present application includes a plurality of light emitting chips arranged in an array, each of the light emitting chips includes an N pole and a P pole, the plurality of light emitting chips are arranged with a common N pole or a common P pole, the plurality of light emitting chips arranged in an array include a first row of light emitting chips and a second row of light emitting chips adjacent to each other, and the first row of light emitting chips and the second row of light emitting chips are arranged in mirror symmetry. The display panel provided in the present application arranges the light emitting chips in two adjacent rows in mirror symmetry, thereby avoiding the asymmetric problem of the light emitting brightness curves on the left and right sides of the light emitting chips, and thereby eliminating the problem of color cast when viewed from the side of the display panel.

[0026] In the above embodiment, since the first row of light emitting chips 10 and the second row of light emitting chips 20 are mirror symmetrical, the shortest distance D1 between the N pole of the first row of light emitting chips 10 and the N pole of the second row of light emitting chips 20 is shorter than the shortest distance D2 between the N pole of the first row of light emitting chips 10 and the P pole of the second row of light emitting chips 20. With reference to Figures 1 and 2, take the adjacent first row of light emitting chips 10 and the second row of light emitting chips 20 as an example, the first row of light emitting chips 10 in Figure 1 have their N poles located on the outside and their P poles located on the inside, but the second row of light emitting chips 20 have their N poles located on the inside and their P poles located on the outside. Between the N pole of the first row of light emitting chips 10 and the N pole of the second row of light emitting chips 20 in Figure 1, the P pole of the first row of light emitting chips 10 is further inserted. In this case, the N poles of the light emitting chips 10 in the first row and the P poles of the light emitting chips 20 in the second row are located on the outside, respectively, causing a problem of color cast when viewed from the side.

[0027] 2, in this case, the N poles of the light-emitting chips 10 in the first row and the N poles of the light-emitting chips 20 in the second row are both located inside, the P poles of the light-emitting chips 10 in the first row and the P poles of the light-emitting chips 20 in the second row are both located outside, and the P poles of the light-emitting chips 10 in the first row or the P poles of the light-emitting chips 20 in the second row are not inserted between the N poles of the light-emitting chips 10 in the first row and the N poles of the light-emitting chips 20 in the second row. This also indicates that the shortest distance D1 between the N poles of the light-emitting chips in the first row and the N poles of the light-emitting chips in the second row is shorter than the shortest distance D2 between the N poles of the light-emitting chips in the first row and the P poles of the light-emitting chips in the second row. In the display panel shown in FIG. 1, the distance between the N poles of the light-emitting chips in the first row and the N poles of the light-emitting chips in the second row is longer than the distance between the N poles of the light-emitting chips in the first row and the P poles of the light-emitting chips in the second row.

[0028] The above embodiment describes the situation where the N pole is located inside, and in some other embodiments, the P pole of the light-emitting chip 10 in the first row and the P pole of the light-emitting chip 20 in the second row may be located inside. In this case, the distance between the P pole of the light-emitting chip 10 in the first row and the P pole of the light-emitting chip 20 in the second row is also shorter than the distance between the P pole of the light-emitting chip 10 in the first row and the N pole of the light-emitting chip 20 in the second row. Regardless of whether the P pole of the light-emitting chip 10 in the first row and the P pole of the light-emitting chip 20 in the second row are simultaneously located inside or simultaneously located outside, the light-emitting chip 10 in the first row and the light-emitting chip 20 in the second row have a mirror-symmetric structure, and the N pole P pole of the light-emitting chip 10 in the first row and the N pole P pole of the light-emitting chip 20 in the second row also have a mirror-symmetric structure. When installed in this manner, the electrodes located on the outside are of the same type, for example, all N poles or all P poles, and the outside of the entire display panel all have the same type of electrodes, for example, all N poles or all P poles, thereby avoiding the problem of color cast due to differences in electrodes.

[0029] In an actual display panel, two single light-emitting chips are not arranged in a mirror-symmetrical manner, but at least two adjacent rows of light-emitting chips are generally arranged in a mirror-symmetrical structure. Note that the embodiment shown in Fig. 2 shows only a part of the light-emitting chips arranged in a mirror-symmetrical manner, and the structure of the light-emitting chips other than the light-emitting chips shown in Fig. 2 is not limited. If a part of the light-emitting chips in the display panel is arranged in the structure shown in Fig. 2, the problem of color cast can be alleviated to a certain extent.

[0030] The above embodiment describes that the first light-emitting area 100 only has a first row of light-emitting chips 10, the second light-emitting area 200 only has a second row of light-emitting chips 20, and the two adjacent rows of light-emitting chips are installed in a mirror symmetrical manner. In some other embodiments, the first light-emitting area 100 may include more rows of light-emitting chips, and similarly, the second light-emitting area 200 may include more rows of light-emitting chips.

[0031] FIG. 3 is a structural schematic diagram of another embodiment of the light-emitting chip in the display panel provided in the embodiment of the present application. In the embodiment shown in FIG. 3, there are four or more even-numbered columns of light-emitting chips adjacent to each other, and the first light-emitting region 100 may include the light-emitting chips 30 of the third column adjacent to each other and the light-emitting chips 10 of the first column, and the second light-emitting region 200 may include the light-emitting chips 20 of the second column adjacent to each other and the light-emitting chips 40 of the fourth column. The light-emitting chips of the even columns include the light-emitting chips 10 of the first column and the light-emitting chips 20 of the second column that are mirror-symmetrical to each other as described above, and the light-emitting chips of the first column and the light-emitting chips of the second column are located at the center positions of the light-emitting chips of the even columns. The light-emitting chips 30 of the third column are located to the left of the light-emitting chips 10 of the first column, and the light-emitting chips 40 of the fourth column are located to the right of the light-emitting chips 20 of the second column.

[0032] In the embodiment shown in Fig. 3, not only are the first row of light emitting chips 10 and the second row of light emitting chips 20 mirror symmetrical, but also the third row of light emitting chips and the first row of light emitting chips 30 are mirror symmetrical, and the second row of light emitting chips 20 and the fourth row of light emitting chips 40 are also mirror symmetrical. The polarity of the two rows of light emitting chips in the first light-emitting region located on the left side is PNNP when arranged from left to right, and the polarity of the two rows of light emitting chips in the light-emitting region located on the right side is PNNP when arranged from left to right. In addition, the entire structure consisting of the first row of light emitting chips 10 and the third row of light emitting chips 30 in the first light-emitting region 100 and the entire structure consisting of the second row of light emitting chips 20 and the fourth row of light emitting chips 40 in the second light-emitting region 200 are mirror symmetrical. In the embodiment shown in Figure 3, the arrangement method of the light-emitting chips in different light-emitting regions is the same, and on the premise that the light-emitting chips in such a single light-emitting region maintain mirror symmetry, the entire structure formed by the multiple light-emitting regions is similarly mirror symmetric.

[0033] In this case, the shortest distance between the N pole of the light-emitting chip in the third row and the N pole of the light-emitting chip in the first row is shorter than the distance between the N pole of the light-emitting chip in the third row and the P pole of the light-emitting chip in the first row, and the shortest distance between the N pole of the light-emitting chip in the second row and the N pole of the light-emitting chip in the fourth row is shorter than the distance between the N pole of the light-emitting chip in the second row and the P pole of the light-emitting chip in the fourth row. In other words, the electrodes in the light-emitting chips 30 in the third row, the light-emitting chips 10 in the first row, the light-emitting chips 20 in the second row, and the light-emitting chips 40 in the fourth row are arranged in the order of PNNP-PNNP. The entire structure is similarly a mirror-symmetric structure. The electrodes located at the outermost positions of the entire structure are the same type of electrodes, and all are P poles. This arrangement can similarly avoid the problem of color cast caused by differences in electrodes.

[0034] As shown in FIG. 4, it is a structural schematic diagram of another embodiment of the light-emitting chip in the display panel provided in the embodiment of the present application. In FIG. 4, the display panel similarly includes four or more even-numbered columns of light-emitting chips adjacent to each other in order, and the first light-emitting area 100 may include the light-emitting chips 30 of the third column adjacent to the light-emitting chips 10 of the first column, and the second light-emitting area 200 may include the light-emitting chips 20 of the second column adjacent to the light-emitting chips 40 of the fourth column. The difference from the embodiment shown in FIG. 3 is that the shortest distance between the N pole of the light-emitting chips of the third column and the N pole of the light-emitting chips of the first column is longer than the distance between the N pole of the light-emitting chips of the third column and the P pole of the light-emitting chips of the first column, and the shortest distance between the N pole of the light-emitting chips of the second column and the N pole of the light-emitting chips of the fourth column is longer than the distance between the N pole of the light-emitting chips of the second column and the P pole of the light-emitting chips of the fourth column. That is, the electrodes of the third row of light-emitting chips 30, the first row of light-emitting chips 10, the second row of light-emitting chips 20, and the fourth row of light-emitting chips 40 are arranged in the order of NPPN-NPPN. The entire structure is similarly mirror-symmetric. The electrodes located on the outermost sides of the entire structure are the same type of electrodes, and all of them are N poles. This arrangement similarly avoids the problem of color cast due to differences in electrodes.

[0035] 5, which is a structural schematic diagram of another embodiment of the light emitting chip in the display panel provided in the embodiment of the present application. In FIG. 5, the display panel similarly includes four or more even-numbered columns of light emitting chips adjacent to each other, and the first light emitting region 100 may include the light emitting chips 50 in the fifth column adjacent to each other and the light emitting chips 10 in the first column, and the second light emitting region 200 may include the light emitting chips 20 in the second column adjacent to each other and the light emitting chips 60 in the sixth column. The arrangement of the PN poles in the light emitting chips 50 in the fifth column is the same as that in the light emitting chips 10 in the first column, and the arrangement of the PN poles in the light emitting chips 20 in the second column is the same as that in the light emitting chips 60 in the sixth column. The light emitting chips 50 in the fifth column and the light emitting chips 60 in the sixth column are mirror symmetrical, and the light emitting chips 10 in the first column and the light emitting chips 20 in the second column are mirror symmetrical.

[0036] 3 and 4, the embodiment is different from the embodiment shown in FIG. 3 and FIG. 4 in that the light emitting chips in two adjacent rows in the first light emitting region / second light emitting region are also arranged in mirror symmetry. However, in the display panel shown in FIG. 5, the light emitting chips 50 in the fifth row and the light emitting chips 10 in the first light emitting region 100 are not arranged in mirror symmetry, and the light emitting chips 20 in the second row and the light emitting chips 60 in the sixth row are not arranged in mirror symmetry. However, the entire structure of the light emitting chips in the first light emitting region and the entire structure of the light emitting chips in the second light emitting region 200 are still arranged in mirror symmetry, thereby ensuring that the electrodes located at the outermost positions of the entire structure are still the same, for example, both N poles or both P poles, thereby avoiding the color cast problem.

[0037] In the embodiment shown in FIG. 5, the shortest distance between the N pole of the light-emitting chip in the fifth row and the P pole of the light-emitting chip in the first row is shorter than the shortest distance between the N pole of the light-emitting chip in the fifth row and the N pole of the light-emitting chip in the first row, and the shortest distance between the N pole of the light-emitting chip in the second row and the P pole of the light-emitting chip in the sixth row is longer than the shortest distance between the N pole of the light-emitting chip in the second row and the N pole of the light-emitting chip in the sixth row. In this case, the electrodes of the light-emitting chip 50 in the fifth row, the light-emitting chip 10 in the first row, the light-emitting chip 20 in the second row, and the light-emitting chip 60 in the sixth row are arranged in the order of PNPN-NPNP. Although the light-emitting chips in multiple rows in a single display area are not installed in a mirror-symmetric manner, the entire structure is similarly a mirror-symmetric structure. The electrodes located at the outermost positions of the entire structure are the same type of electrodes, and are all P poles. This installation can similarly avoid the color cast problem caused by the difference in electrodes.

[0038] 6 is a structural schematic diagram of another embodiment of the light emitting chip in the display panel provided in the embodiment of the present application. In the embodiment shown in FIG. 6, the display panel similarly includes four or more even-numbered columns of light emitting chips adjacent to each other, and the first light emitting area 100 may include the light emitting chips 50 in the fifth column adjacent to each other and the light emitting chips 10 in the first column, and the second light emitting area 200 may include the light emitting chips 20 in the second column adjacent to each other and the light emitting chips 60 in the sixth column. The arrangement of the PN poles in the light emitting chips 50 in the fifth column is the same as that in the light emitting chips 10 in the first column, and the arrangement of the PN poles in the light emitting chips 20 in the second column is the same as that in the light emitting chips 60 in the sixth column. The light emitting chips 50 in the fifth column and the light emitting chips 60 in the sixth column are mirror symmetrical, and the light emitting chips 10 in the first column and the light emitting chips 20 in the second column are mirror symmetrical.

[0039] The difference from the embodiment shown in FIG. 5 is that in FIG. 6, the shortest distance between the N pole of the light-emitting chip in the fifth row and the P pole of the light-emitting chip in the first row is longer than the shortest distance between the N pole of the light-emitting chip in the fifth row and the N pole of the light-emitting chip in the first row, and the shortest distance between the N pole of the light-emitting chip in the second row and the P pole of the light-emitting chip in the sixth row is shorter than the shortest distance between the N pole of the light-emitting chip in the second row and the N pole of the light-emitting chip in the sixth row. In this case, the electrodes in the light-emitting chips 50 in the fifth row, the light-emitting chips 10 in the first row, the light-emitting chips 20 in the second row, and the light-emitting chips 60 in the sixth row are arranged in the order of NPNP-PNPN. Although the light-emitting chips in multiple rows in a single display area are not installed in mirror symmetry, the entire structure is similarly a mirror symmetric structure. The electrodes located at the outermost positions of the entire structure are the same type of electrodes, and all of them are N poles. By installing them in this way, the color cast problem caused by the difference in electrodes can be avoided in the same way.

[0040] In the embodiment of the present application, the direction of the N pole and the P pole is not limited, and it is only necessary to ensure that the light-emitting chips in the same row are a common N pole or a common P pole, and that the multiple rows of light-emitting chips are mirror symmetric (mainly the electrodes are mirror symmetric). And the number of rows of light-emitting chips in the first light-emitting region 100 and the second light-emitting region 200 is generally the same, and it is ensured that the entire structure is mirror symmetric. When both the first light-emitting region 100 and the second light-emitting region 200 include multiple rows of light-emitting chips, the rows of light-emitting chips in the first light-emitting region 100 may be mirror symmetric or not, and similarly, the rows of light-emitting chips in the second light-emitting region 200 may be mirror symmetric or not.

[0041] The present application further provides a display device, which includes any one of the display panels described above, and the description thereof is omitted here.

[0042] In the above embodiments, the description of each embodiment has its own emphasis, and for the parts of an embodiment that are not described in detail, reference may be made to the detailed descriptions of other embodiments above, and the description will be omitted here.

[0043] When specifically implemented, each of the above units or structures may be realized as an independent entity, or may be arbitrarily combined and realized as the same or several entities. For specific implementation of each of the above units or structures, reference may be made to the previous method embodiments, and description thereof will be omitted here.

[0044] For the specific implementation of each of the above operations, reference can be made to the previous embodiment, and the description will be omitted here.

[0045] The above provides a detailed introduction to the display panel provided in the examples of the present application, and the present specification describes the principles and embodiments of the present application by applying specific examples. The explanation of the above examples is only useful for understanding the method and core ideas of the present application, and those skilled in the art may make any changes to the specific embodiments and application scope based on the ideas of the present application. In short, the contents of this specification should not be construed as limiting the present application.

Claims

1. A display panel, comprising a plurality of rows of light emitting chips arranged in an array, each of the light emitting chips including an N pole and a P pole, and a plurality of light emitting chips in any one row of the plurality of rows of light emitting chips are arranged with a common N pole or a common P pole; the display panel includes a first light-emitting region and a second light-emitting region adjacent to each other, the first light-emitting region includes at least one row of light-emitting chips, the second light-emitting region includes at least one row of light-emitting chips, and the at least one row of light-emitting chips in the first light-emitting region and the at least one row of light-emitting chips in the second light-emitting region are mirror symmetrical; The first light-emitting region includes a fifth row of light-emitting chips and a first row of light-emitting chips adjacent to each other, and the second light-emitting region includes a second row of light-emitting chips and a sixth row of light-emitting chips adjacent to each other; a display panel characterized in that an arrangement method of the PN poles in the light-emitting chips in the fifth row is the same as an arrangement method of the PN poles in the light-emitting chips in the first row, an arrangement method of the PN poles in the light-emitting chips in the second row is the same as an arrangement method of the PN poles in the light-emitting chips in the sixth row, the light-emitting chips in the fifth row and the light-emitting chips in the sixth row are mirror symmetrical, and the light-emitting chips in the first row and the light-emitting chips in the second row are mirror symmetrical.

2. The display panel of claim 1, characterized in that the first light-emitting region includes a first row of light-emitting chips, the second light-emitting region includes a second row of light-emitting chips, the N poles of the light-emitting chips in the first row and the N poles of the light-emitting chips in the second row are mirror-symmetric, and the P poles of the light-emitting chips in the first row and the P poles of the light-emitting chips in the second row are mirror-symmetric.

3. The display panel of claim 2, characterized in that the shortest distance between the N pole of the light-emitting chip in the first row and the N pole of the light-emitting chip in the second row is shorter than the shortest distance between the N pole of the light-emitting chip in the first row and the P pole of the light-emitting chip in the second row.

4. The display panel according to claim 2, characterized in that the shortest distance between the P pole of the light-emitting chip in the first row and the P pole of the light-emitting chip in the second row is shorter than the distance between the P pole of the light-emitting chip in the first row and the N pole of the light-emitting chip in the second row.

5. the shortest distance between the N pole of the light-emitting chip in the fifth row and the P pole of the light-emitting chip in the first row is shorter than the shortest distance between the N pole of the light-emitting chip in the fifth row and the N pole of the light-emitting chip in the first row; The display panel of claim 1, characterized in that the shortest distance between the N pole of the light-emitting chip in the second row and the P pole of the light-emitting chip in the sixth row is longer than the shortest distance between the N pole of the light-emitting chip in the second row and the N pole of the light-emitting chip in the sixth row.

6. the shortest distance between the N pole of the light-emitting chip in the fifth row and the P pole of the light-emitting chip in the first row is longer than the shortest distance between the N pole of the light-emitting chip in the fifth row and the N pole of the light-emitting chip in the first row; The display panel of claim 1, characterized in that the shortest distance between the N pole of the light-emitting chip in the second row and the P pole of the light-emitting chip in the sixth row is shorter than the shortest distance between the N pole of the light-emitting chip in the second row and the N pole of the light-emitting chip in the sixth row.

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