Power supply circuits, chips and displays

Abstract

The present application provides a power supply circuit, a chip and a display, the circuit comprising: a reference circuit, a first current mirror unit, a first switch, a second current mirror unit, a second switch and an output stage, the reference circuit is configured to generate a primary mirror current, the first current mirror unit is connected to the reference circuit, the first switch is connected to the first current mirror unit and configured to control the on / off of the first current mirror unit, the second current mirror unit is connected to the first current mirror unit, the second switch is connected to the second current mirror unit and configured to control the on / off of the second current mirror unit, when the first switch and the second switch are turned on, the first current mirror unit and the second current mirror unit cooperate to form a current mirror, and are configured to perform a mirroring process on the primary mirror current to obtain an output current, and the output stage is connected to the second current mirror unit and configured to output the output current. The present application can effectively improve the current accuracy in the full current range of the output constant current source.

Description

[Technical field]

[0001] CROSS REFERENCE TO RELATED APPLICATIONS This application claims priority based on a Chinese application bearing application number 2020115016417 and entitled "Power Supply Circuit, Chip and Display" filed with the China Patent Office on December 17, 2020, the entire contents of which are incorporated herein by reference.

[0002] The present application is in the technical field of circuits, and in particular, relates to power supply circuits, chips and displays. [Background technology]

[0003] An LED (Light Emitting Diode) display is a flat panel display that is made up of multiple small LED module panels and is a device that displays various information such as text, images, and videos. LED displays are an integration of microelectronics technology, computer technology, and information processing technology, and have the advantages of vivid colors, wide dynamic range, high brightness, long life, stable operation, and high reliability. For this reason, LED displays are widely used in various situations such as commercial media, cultural performances, stadiums, information dissemination, press releases, and securities trading, and can meet the requirements of various usage environments.

[0004] LED display requires a driver chip, but the current accuracy of the conventional driver chip circuit is generally not high enough to meet the requirements. Summary of the Invention

[0005] The embodiments of the present application aim to provide a power supply circuit, a chip and a display.

[0006] An embodiment of the present application provides a power supply circuit, the power supply circuit comprising: a reference circuit, a first current mirror unit, a first switch, a second current mirror unit, a second switch, and an output stage, the reference circuit is configured to generate a primary mirror current, the first current mirror unit is connected to the reference circuit, the first switch is connected to the first current mirror unit and configured to control the on / off of the first current mirror unit, the second current mirror unit is connected to the first current mirror unit, the second switch is connected to the second current mirror unit and configured to control the on / off of the second current mirror unit, when the first switch and the second switch are turned on, the first current mirror unit and the second current mirror unit cooperate to form a current mirror, and are configured to perform a mirroring process on the primary mirror current to obtain an output current, and the output stage is connected to the second current mirror unit and configured to output the output current.

[0007] Optionally, the first current mirror unit includes a first amplifier and a plurality of first transistors, an inverting input terminal of the first amplifier is connected to a predetermined voltage signal, a drain of each of the first transistors is connected to a non-inverting input terminal of the first amplifier, a gate of the first transistor is connected to an output terminal of the first amplifier via the first switch, and a source of the first transistor is grounded.

[0008] Optionally, the first switch includes a plurality of first sub-switches, a gate of each of the first transistors being connected to one end of the first sub-switch, and the other end of each of the first sub-switches being connected to the output terminal of the first amplifier.

[0009] Optionally, the second current mirror unit includes a second amplifier and a plurality of second transistors, the second amplifier having a non-inverting input terminal connected to the drain of the first transistor and an output terminal connected to the output stage, the drain of each of the second transistors being connected to the inverting input terminal of the second amplifier, a gate connected to the output terminal of the first amplifier via the second switch, and a source grounded.

[0010] Optionally, the second transistor is an NMOS device.

[0011] Optionally, the second switch includes a plurality of second sub-switches, a gate of each of the second transistors is connected to one end of the second sub-switch, and the other end of each of the second sub-switches is connected to the output terminal of the first amplifier.

[0012] Optionally, the amplifier further comprises a buffer coupled between the first current mirror unit and the second current mirror unit.

[0013] Optionally, the reference circuit comprises a reference amplifier having an inverting input terminal connected to a reference signal, and an external resistor having a first terminal connected to the non-inverting input terminal of the reference amplifier and a second terminal connected to ground.

[0014] Optionally, the reference circuit further comprises a third transistor having a gate connected to the output terminal of the reference amplifier, a drain connected to the first end of the external resistor, and a source grounded, and a fourth transistor having a gate connected to the output terminal of the reference amplifier, a drain connected to each of the drains of the first transistors, and a source grounded.

[0015] Optionally, the output stage comprises a fifth transistor having a gate connected to the output terminal of the second amplifier, a source connected to a drain of each of the second transistors respectively, and a drain connected to a circuit to be driven.

[0016] Optionally, the system further comprises a controller connected to each of the first switch and the second switch and configured to send control signals to the first switch and the second switch.

[0017] An embodiment of the present application further provides a driver chip including the power supply circuit according to the embodiment of the present application.

[0018] Optionally, the driving chip is a driving chip for an LED display.

[0019] An embodiment of the present application further provides a display including the power supply circuit according to the embodiment of the present application, wherein the power supply circuit drives the display in a common anode manner, or the power supply circuit drives the display in a common cathode manner.

[0020] Optionally, the display is an LED display.

[0021] The power supply circuit, chip and display of the present application respectively control the on / off of the two current mirror units by setting a first switch corresponding to the first current mirror unit and setting a second switch corresponding to the second current mirror unit, and when the first switch and the second switch are turned on, the first current mirror unit and the second current mirror unit cooperate to form a current mirror, and perform mirroring processing on the primary mirror current generated by the reference circuit to obtain an output current, and the output stage outputs the output current as a constant current source current, thus reducing the impact of the on / off of the output constant current source on the output current accuracy, improving the stability of the inner loop, and effectively improving the current accuracy in the full current range of the output constant current source. [Brief description of the drawings]

[0022] In order to more clearly describe the technical solutions in the embodiments of the present application, the drawings used in the embodiments of the present application are briefly described below. Please note that the drawings described are only for illustrating some embodiments of the present application, and are not intended to limit the scope. Those skilled in the art can obtain other related drawings based on these drawings without using inventive abilities.

[0023] [Figure 1A] FIG. 1 is a schematic configuration diagram of a power supply circuit according to an embodiment of the present application. [Figure 1B] FIG. 1 is a schematic configuration diagram of a power supply circuit according to an embodiment of the present application. [Figure 1C] FIG. 2 is a schematic diagram illustrating the principle of current mirroring according to an embodiment of the present application. [Diagram 2] FIG. 1 is a schematic configuration diagram of a power supply circuit according to an embodiment of the present application. [Diagram 3] FIG. 1 is a schematic configuration diagram of a power supply circuit according to an embodiment of the present application. [Figure 4A] FIG. 2 is a schematic diagram showing a configuration of a circuit equivalent to a circuit of a constant current source output channel according to an embodiment of the present application. [Figure 4B] FIG. 2 is a schematic diagram showing a configuration of a circuit equivalent to a circuit of a constant current source output channel according to an embodiment of the present application. [Figure 4C] FIG. 2 is a schematic diagram showing a configuration of a circuit equivalent to a circuit of a constant current source output channel according to an embodiment of the present application. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] The technical solutions in the embodiments of the present application will be described below with reference to the drawings used in the embodiments of the present application. In the description of the present application, the terms "first", "second", etc. are merely used for distinguishing and describing purposes, and do not express or imply relative importance.

[0025] As shown in FIG. 1, this embodiment provides a power supply circuit 1, which mainly includes three parts: a reference circuit 10, a current mirroring 20, and an output circuit 30. The above power supply circuit 1 can be used in a driving chip of an LED display as a constant current source generating circuit. The reference circuit 10 generates a reference current I0 based on an internal predetermined reference voltage VREF and an external resistor Rext, and the reference current I0 is processed by the current mirroring 20 to obtain a current I1, and the output circuit 30 generates a constant current source current Iout to drive the output. The current mirroring 20 and the output circuit 30 need to adapt to the anode common structure of the LED and meet the requirements of multi-channel driving capability.

[0026] 1B, this embodiment provides a specific circuit of the power supply circuit 1. In this circuit, a reference voltage Vref is generated by a bandgap reference voltage source inside the chip, and a negative feedback structure formed by an error amplifier OP0, a transistor PM0, and an external resistor Rext is used to obtain the following reference current I0:

number

[0027] A precisely matched current I1 is obtained by a current mirror formed by transistor PM0 and transistor PM1.

[0028] The transistors can be MOS (Metal-Oxide-Semiconductor Field-Effect Transistor) devices. In practical applications, when the voltage bias is the same, the current of the MOS devices is directly proportional to the device dimensions. If MOS devices of the same dimensions are used, the current ratio is determined by the number of MOS devices, and the required current ratio can be obtained by adjusting the number of MOS devices. In this embodiment, the transistors NM0, NM1, and NM2 can function as a current mirror. The principle of the current mirroring 20 will be described in detail below.

[0029] The principle of the current mirroring 20 is as follows: as shown in FIG. 1C, when the gate voltages Vg1 of the transistors NM0 and NM1 are the same, the gate voltage of the transistor NM2 is set to Vg2, and the drain voltages of the transistors NM0, NM1, and NM2 are set to Vd0, Vd1, and Vd2, respectively, if Vg1 is equal to Vg2 and Vd1 is equal to Vd2, the two devices of the transistors NM1 and NM2 are under the same bias condition, and therefore the current I1 is equal to the current I2, that is, the current I2 is a mirror of the current I1.

[0030] According to the above principle, in the current branch circuit of the transistor PM1 and the transistor NM0 shown in FIG.

number

[0031] Here, K is the mirror ratio between the transistor PM1 and the transistor NM0, which is determined by the performance of the device selected. Then, using the negative feedback structure formed by the error amplifier OP1 and the transistor NM0, the drain voltage of the transistor NM0 is set as VCRES, and the gate voltage of the transistor NM0 is VGATE. In order to accurately mirror the output channel current Iout, it is necessary to make the gate voltage of the transistor NM1 equal to VGATE and the drain voltage equal to VCRES. Using the negative feedback loop formed by the amplifier DRIVER_OP and the transistor NM2, the drain voltage of the transistor NM1 is set to be equal to the drain voltage of NM0. The LED common anode structure driver chip satisfies the following relationship through two current mirrorings:

number

[0032] The mirror ratio of the transistors NM0 and NM1 is M:N. In this way, by adjusting the ratio of the external resistor Rext and the current mirror, a desired accurate output current Iout can be obtained.

[0033] In the above power supply circuit, the mirror ratio of the transistor NM0 and the transistor NM1 is M:N. By selecting an appropriate ratio, it is possible to meet the required current accuracy while suppressing the branch current of the transistor NM0 and suppressing the static power consumption of the chip.

[0034] As shown in FIG. 2 , this embodiment provides a power supply circuit 1, which includes a reference circuit 10, a first current mirror unit 21, a first switch 22, a second current mirror unit 23, a second switch 24, and an output stage 25.

[0035] The reference circuit 10 is configured to generate a primary mirror current I1. The first current mirror unit 21 is connected to the reference circuit 10. The first switch 22 is connected to the first current mirror unit 21 and configured to control the on / off of the first current mirror unit 21. The second current mirror unit 23 is connected to the first current mirror unit 21. The second switch 24 is connected to the second current mirror unit 23 and configured to control the on / off of the second current mirror unit 23. When the first switch 22 and the second switch 24 are turned on, the first current mirror unit 21 and the second current mirror unit 23 cooperate to form a current mirror, and are configured to perform a mirroring process on the primary mirror current I1 to obtain an output current Iout. The output stage 25 is connected to the second current mirror unit 23 and configured to output the output current Iout.

[0036] Optionally, the amplifier further includes a buffer 26 connected between the first current mirror unit 21 and the second current mirror unit 23. The buffer 26 can reduce feedback noise, ensure current accuracy, and improve the stability of the negative feedback loop.

[0037] Optionally, the system further comprises a controller 27 connected to each of the first switch 22 and the second switch 24 and configured to send control signals to the first switch 22 and the second switch 24 .

[0038] 3, in the power supply circuit 1 according to this embodiment, the first current mirror unit 21 includes a first amplifier OP1 and a plurality of first transistors NM0. The inverting input terminal of the first amplifier OP1 is connected to a predetermined voltage signal, the drains of the first transistors NM0 are connected to the non-inverting input terminals of the first amplifier OP1, the gates of the first transistors NM0 are connected to the output terminal of the first amplifier OP1 via the first switches 22, and the sources of the first transistors NM0 are grounded. In FIG. 3, four first transistors NM0 are illustrated as an example.

[0039] Optionally, the first switch 22 includes a plurality of first sub-switches K0, the gate of each of the first transistors NM0 is connected to one end of the first sub-switch K0, and the other end of the first sub-switch K0 is connected to the output terminal of the first amplifier OP1.

[0040] Optionally, the second current mirror unit 23 includes a second amplifier DRIVER_OP and a plurality of second transistors NM1. The second amplifier DRIVER_OP has a non-inverting input terminal connected to the drain of the first transistor NM0 and an output terminal connected to the output stage 25. The drain of each of the second transistors NM1 is connected to the inverting input terminal of the second amplifier DRIVER_OP, a gate is connected to the output terminal of the first amplifier OP1 via the second switch 24, and a source is grounded. In FIG. 3, four second transistors NM1 are illustrated.

[0041] Optionally, the second switch 24 includes a plurality of second sub-switches K1, the gate of each of the second transistors NM1 is connected to one end of the second sub-switch K1, and the other end of the second sub-switch K1 is connected to the output terminal of the first amplifier OP1.

[0042] Optionally, a buffer 26 is connected between the first current mirror unit 21 and the second current mirror unit 23 .

[0043] Optionally, the reference circuit 10 comprises a reference amplifier OP0 and an external resistor Rext, an inverting input terminal of the reference amplifier OP0 is connected to a reference signal, the reference signal being a reference voltage Vref, a first end of the external resistor Rext is connected to a non-inverting input terminal of the reference amplifier OP0, and a second end of the external resistor Rext is grounded.

[0044] Optionally, the reference circuit 10 further includes a third transistor PM0 and a fourth transistor PM1. The third transistor PM0 has a gate connected to the output terminal of the reference amplifier OP0, a drain connected to the first end of the external resistor Rext, and a source grounded. The fourth transistor PM1 has a gate connected to the output terminal of the reference amplifier OP0, a drain connected to each of the drains of the first transistors NM0, and a source grounded.

[0045] Optionally, the output stage 25 comprises a fifth transistor NM2 having a gate connected to the output terminal of the second amplifier DRIVER_OP, a source connected to the drain of each of the second transistors NM1, and a drain connected to a circuit to be driven.

[0046] 3, in order to more clearly explain the principle of the power supply circuit 1 according to this embodiment, it is assumed that there are four first transistors NM0, transistor NM0:1 to transistor NM0:4, four second transistors NM1, transistor NM1:1 to transistor NM1:4, four first switches 22, first sub-switches K0:1 to K0:4, and four second switches 2, second sub-switches K1:1 to K1:4. The principle will be explained in detail using this as an example.

[0047] First, the mirror ratio N / M between the first current mirror unit 21 and the second current mirror unit 23 is set to a range of 4 to 8, in order to satisfy the device performance and to suppress the power consumption of the chip.

[0048] In addition, the method of sending the voltage VGATE to the gate of the second transistor NM1 in the channel via the buffer 26 separates the constant current source generating circuit from the constant current source output channel by the buffer 26, as compared with the method of sending the voltage VGATE directly to the gate of the second transistor NM1 in the channel, thereby preventing the influence of noise generated in the constant current source output channel that is repeatedly turned on and off on the constant current source. In the multi-channel structure, the first amplifier OP1 drives multiple second transistors NM1, and the second transistors NM1 may be NMOS (N-Metal-Oxide-Semiconductor) and provide a very large parasitic capacitance at the output node of the first amplifier OP1, so that the buffer 26 can increase the driving capability of the voltage VGATE and reduce the difficulty of designing the first amplifier OP1.

[0049] In addition, the first transistor NM0 in the first current mirror unit 21 and the mirror current in its channel are divided into four groups, the control signal of the first sub-switch K0:1 is the same as that of the second sub-switch K1:1, the control signal of the first sub-switch K0:2 is the same as that of the second sub-switch K1:2, the control signal of the first sub-switch K0:3 is the same as that of the second sub-switch K1:3, and the control signal of the first sub-switch K0:4 is the same as that of the second sub-switch K1:4. The control signals of the above switches are provided by the control device 27. In different situations, the current requirements are different, and different sets of the first transistor NM0 and the second transistor NM1 are turned on and combined by each sub-switch, so that different current mirrors can be configured, and the accuracy of the constant current source can be improved under the premise that the range of the output current Iout is relatively large. For easy understanding, the principle is explained below.

[0050] 4A to 4C are schematic diagrams showing an equivalent circuit of an output constant current source channel circuit in the power supply circuit 1 according to this embodiment. FIG. 4A is a circuit diagram when a constant current source output channel and a light emitting diode LED are connected. If only the error caused by the device mismatch is considered as the main error source of the constant current source, there are mainly two error sources, Voff1 (equivalent offset voltage of the threshold voltage of the NMOS transistor constituting the current mirror) and Voff2 (equivalent input offset voltage of DRIVER_OP1), in the output constant current source channel. For the circuit shown in FIG. 4A, an equivalent circuit shown in FIG. 4B can be configured, and further, an equivalent circuit shown in FIG. 4C can be configured, in which case the current of the output constant current source shown in FIG. 4A is equivalent to the current of the biasing NMOS transistor shown in FIG. 4C.

[0051] In practical applications, the relationship between the current of an NMOS transistor, its gate voltage, and its drain voltage (ignoring some second-order effects) is given by the following equation:

number

[0052] μ is the channel carrier mobility, and C OX is the gate oxide capacitance per unit area, W / L is the aspect ratio of the MOS transistor, and V GS is the gate-source voltage of the MOS device, and V DS is the drain-source voltage of the MOS device, and V TH is the threshold voltage of the MOS device.

[0053] The current error due to the voltages Voff1 and Voff2 and the gate-source current I DS The ratio of ΔI 1 / I DS and ΔI 2 / I DS Then, we can obtain equations (2) and (3). The calculations are as follows:

number

[0054] Therefore

number

[0055] As can be seen from equations (2) and (3), the larger the gate-source voltage of the second transistor NM1 is, the smaller the effect of the error source due to the offset on the output current Iout becomes.

[0056] In practical applications, the channel current is several milliamperes to several tens of milliamperes, and as can be seen from the circuit connection state when the power supply circuit 1 shown in Figure 3 works normally, V DS is kept constant and is equal to the internally set voltage VCRES. According to equation (1), decreasing W / L (i.e., reducing the number of second transistors NM1) reduces V GS This corresponds to increasing the voltage, and therefore, when the output current Iout is relatively small, only the first sub-switch K0:1 and the second sub-switch K1:1 are turned on, and the accuracy of the power supply circuit 1 at this time is optimal. When the output current Iout increases to a level exceeding the capabilities of the first transistor NM0:1 and the second transistor NM1:1, the first sub-switch K0:2 and the second sub-switch K1:2 are further turned on, and thus, as the set output current Iout increases, the first sub-switches K0:1 to K0:4 and the second sub-switches K1:1 to K1:4 are turned on sequentially, i.e., when the output current Iout is relatively small, relatively few NMOS devices are turned on, and the current accuracy of the chip can be improved.

[0057] Generally, the current range of a constant current source is very large, from several milliamperes to tens of milliamperes, and when using MOS devices of the same size for such a large range, the change in current precision is very large. In view of this, the present embodiment proposes a grouping concept, and turns on different numbers of MOS transistors corresponding to different output current settings, so that different combinations correspond to different currents, and the current precision of the chip can be improved when the current change is relatively large.

[0058] The above power supply circuit 1 can reduce the static power consumption of the chip under the premise of ensuring the current accuracy by appropriately selecting the mirror ratio M:N between the first transistor NM0 and the second transistor NM1. The buffer 26 is added to the channel of the gate voltage VGATE of the current mirror NMOS transistor, which reduces the requirements for the driving ability of the first amplifier OP1, reduces the feedback noise, ensures the current accuracy, and improves the stability of the negative feedback loop formed by the first amplifier OP1 and the first transistor NM0. The constant current source adopts a grouping form, which can effectively ensure the current accuracy in the full current range of the output constant current source. The embodiment of the present application further provides a driving chip including the power supply circuit 1 according to the above embodiment. Since the driving chip has all the beneficial effects of the power supply circuit 1 according to the above embodiment, the details thereof can be referred to the description of the above embodiment, and the description will be omitted here. Optionally, the driving chip is a driving chip for an LED display.

[0059] The embodiment of the present application further provides a display including the power supply circuit 1 according to the above embodiment. The power supply circuit drives the display in a common anode manner, or the power supply circuit drives the display in a common cathode manner. The display has all the beneficial effects of the power supply circuit 1 according to the above embodiment, and the details thereof can be referred to the description in the above embodiment, and the description is omitted here. Optionally, the display is an LED display.

[0060] Although the embodiments of the present invention have been described with reference to the drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and these modifications and variations also fall within the scope of the claims. [Industrial Applicability]

[0061] According to the technical solution of the present application, the impact on the output current accuracy caused by turning on and off the output constant current source can be reduced, the stability of the inner loop can be improved, and the current accuracy over the entire current range of the output constant current source can be effectively improved. [Explanation of symbols]

[0062] 1 Power supply circuit 10 Reference circuit 20 Current Mirroring 30 Output circuit 21 First current mirror unit 22 First Switch 23 Second current mirror unit 24 Second Switch 25 Output Stage 26 Buffer 27 Control Device OP1 First amplifier NM0 1st transistor K0 1st sub switch NM1 2nd transistor K1 Second sub switch OP0 Reference Amplifier Rext External resistance PM0 3rd transistor PM1 4th transistor DRIVER_OP Second amplifier NM2 5th transistor I0 Reference current I1 Primary mirror current Iout Output current Vref Reference voltage LED Light Emitting Diode

Claims

1. a reference circuit, a first current mirror unit, a first switch, a second current mirror unit, a second switch, an output stage, and a buffer; the reference circuit is configured to generate a primary mirror current; the first current mirror unit is connected to the reference circuit; the first switch is connected to the first current mirror unit and configured to control on / off of the first current mirror unit; the second current mirror unit is connected to the first current mirror unit; the second switch is connected to the second current mirror unit and configured to control on / off of the second current mirror unit; When the first switch and the second switch are turned on, the first current mirror unit and the second current mirror unit cooperate to form a current mirror, and are configured to perform a mirroring process on the primary mirror current to obtain an output current; the output stage is connected to the second current mirror unit and configured to output the output current; the buffer is connected between the first current mirror unit and the second current mirror unit; the first current mirror unit includes a first amplifier and a plurality of first transistors; The inverting input terminal of the first amplifier is connected to a predetermined voltage signal; a drain of each of the first transistors is connected to a non-inverting input terminal of the first amplifier, a gate of the first transistor is connected to an output terminal of the first amplifier via the first switch, and a source of the first transistor is grounded; the first switch includes a plurality of first sub-switches, a gate of each of the first transistors is connected to one end of the first sub-switch, and the other end of the first sub-switch is connected to an output terminal of the first amplifier; the number of the first sub-switches is equal to the number of the first transistors; the second current mirror unit includes a second amplifier and a plurality of second transistors; the second amplifier has a non-inverting input terminal connected to the drain of the first transistor and an output terminal connected to the output stage; Each of the second transistors has a drain connected to an inverting input terminal of the second amplifier, a gate connected to an output terminal of the first amplifier via the second switch, and a source grounded; The second switch includes a plurality of second sub-switches, a gate of each of the second transistors is connected to one end of the second sub-switch, and the other end of the second sub-switch is connected to the output terminal of the first amplifier, and the number of the second sub-switches is the same as the number of the second transistors. A power supply circuit comprising:

2. The second transistor is an NMOS device.

2. The power supply circuit according to claim 1 .

3. The reference circuit comprises: a reference amplifier having an inverting input terminal connected to a reference signal; an external resistor having a first end connected to the non-inverting input terminal of the reference amplifier and a second end grounded; 3. The power supply circuit according to claim 1 or 2.

4. The reference circuit comprises: a third transistor having a gate connected to the output terminal of the reference amplifier, a drain connected to the first end of the external resistor, and a source grounded; a fourth transistor having a gate connected to the output terminal of the reference amplifier, a drain connected to the drain of each of the first transistors, and a source grounded.

4. The power supply circuit according to claim 3.

5. The output stage comprises: a fifth transistor having a gate connected to the output terminal of the second amplifier, a source connected to the drain of each of the second transistors, and a drain connected to a circuit to be driven; 5. The power supply circuit according to claim 1, wherein the first and second electrodes are electrically connected to each other.

6. a control device coupled to each of the first switch and the second switch and configured to transmit control signals to the first switch and the second switch. The power supply circuit according to any one of claims 1 to 5.

7. The power supply circuit according to any one of claims 1 to 6 is provided. A driving chip characterized by the above.

8. The driving chip is a driving chip for an LED display.

8. The driving chip according to claim 7.

9. A display, A power supply circuit according to claim 1, driving the display with a common anode by the power supply circuit; Alternatively, the display is driven by the power supply circuit in a cathode common manner. A display characterized by:

10. The display is an LED display.

10. A display as claimed in claim 9.

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