Antennas and Communication Modules

Abstract

This antenna comprises a substrate, a ground layer, a power feeding patch layer, a first non-power feeding patch layer, and a second non-feeding patch layer. The substrate is composed of a dielectric material. The ground layer is connected to a ground potential. The power feeding patch layer is inside the substrate and is located on a side closer to the surface of the substrate than the ground layer is. The first non-power feeding patch layer is located on a side closer to the surface of the substrate than the power feeding patch layer is. The second non-power feeding patch layer is inside the substrate and is located between the power feeding patch layer and the first non-power feeding patch layer. Further, the second non-power feeding patch layer is smaller than the power feeding patch layer and the first non-power feeding patch layer. This communication module has the antenna as configured above, and an RF element.

Description

[Technical field]

[0001] The disclosed embodiments relate to an antenna and a communication module. [Background technology]

[0002] 2. Description of the Related Art A patch antenna having a ground layer and a power feeding patch layer on a dielectric substrate has been disclosed (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2001-267833 A Summary of the Invention

[0004] The antenna of the present disclosure includes a substrate, a ground layer, a feed patch layer, a first parasitic patch layer, and a second parasitic patch layer. The substrate is made of a dielectric material. The ground layer is connected to a ground potential. The feed patch layer is located inside the substrate and closer to the surface of the substrate than the ground layer. The first parasitic patch layer is located closer to the surface of the substrate than the feed patch layer. The second parasitic patch layer is located inside the substrate between the feed patch layer and the first parasitic patch layer. In addition, the second parasitic patch layer is smaller than the feed patch layer and the first parasitic patch layer. [Brief description of the drawings]

[0005] [Figure 1] FIG. 1 is a front view showing an example of the configuration of an array antenna according to an embodiment. [Diagram 2] FIG. 2 is a cross-sectional view showing an example of the configuration of the antenna according to the embodiment. [Diagram 3] FIG. 3 is a front view showing an example of the configuration of the antenna according to the embodiment. [Figure 4] FIG. 4 is a diagram showing gain characteristics of the antennas of the embodiment and the first reference example. [Diagram 5] FIG. 5 is a diagram showing the reflection characteristics of the antennas of the embodiment and the reference example 1. In FIG. [Figure 6] FIG. 6 is a diagram showing gain characteristics when power is fed from one of the power feed vias in the array antennas of the embodiment and reference example 1. [Figure 7] FIG. 7 is a diagram showing gain characteristics when power is fed from the other power feed via in the array antennas of the embodiment and reference example 1. [Figure 8] FIG. 8 is a diagram showing the beam steering characteristics of the array antennas of the embodiment and the first reference example. [Figure 9] FIG. 9 is a diagram showing the beam steering characteristics of the array antennas of the embodiment and the reference example 1. In FIG. [Figure 10] FIG. 10 is a diagram showing the beam steering characteristics of the array antennas of the embodiment and the reference example 1. In FIG. [Figure 11] FIG. 11 is a diagram showing the beam steering characteristics of the array antennas of the embodiment and the first reference example. [Figure 12] FIG. 12 is a diagram showing the beam steering characteristics of the array antennas of the embodiment and the first reference example. [Figure 13] FIG. 13 is a diagram showing the beam steering characteristics of the array antennas of the embodiment and the first reference example. [Figure 14] FIG. 14 is a diagram showing gain characteristics when the size of the second parasitic patch layer is changed when power is fed from one of the power feed vias in the array antenna according to the embodiment. [Figure 15] FIG. 15 is a diagram showing gain characteristics when the size of the second parasitic patch layer is changed when power is fed from the other feed via in the array antenna according to the embodiment. [Figure 16] FIG. 16 is a diagram showing gain characteristics when the distance between the feed patch layer and the second parasitic patch layer and the distance between the first parasitic patch layer and the second parasitic patch layer are changed in the antennas of the embodiment and reference example 1. [Figure 17]FIG. 17 is a diagram showing changes in gain characteristics when the size of the second parasitic patch layer is changed in the embodiment. [Figure 18] FIG. 18 is a cross-sectional view illustrating an example of a configuration of an antenna according to another embodiment of the present invention. [Figure 19] FIG. 19 is a front view illustrating an example of a configuration of an antenna according to another embodiment. [Figure 20] FIG. 20 is a diagram showing gain characteristics of antennas according to another embodiment and reference example 2. In FIG. [Figure 21] FIG. 21 is a diagram showing the reflection characteristics of antennas according to another embodiment and reference example 2. In FIG. [Figure 22] FIG. 22 is a diagram showing gain characteristics when power is fed from one of the power feed vias in the array antennas of the other embodiment and the reference example 2. In FIG. [Diagram 23] FIG. 23 is a diagram showing gain characteristics when power is fed from the other power feed via in the array antenna of the other embodiment and the reference example 2. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0006] Hereinafter, embodiments of an antenna and a communication module disclosed in the present application will be described with reference to the accompanying drawings. Note that the present disclosure is not limited to the embodiments described below.

[0007] In addition, in the embodiments described below, expressions such as "constant", "orthogonal", "vertical", "parallel" or "same" may be used, but these expressions do not necessarily mean "constant", "orthogonal", "vertical" or "parallel" strictly. In other words, each of the above expressions allows for deviations due to, for example, manufacturing precision, installation precision, etc.

[0008] A patch antenna having a ground layer and a power supply patch layer on a dielectric substrate has been disclosed. It is expected that a technology that enables the gain characteristics of the patch antenna to be broadened.

[0009] <Array antenna> First, the configuration of an array antenna 1 according to an embodiment will be described with reference to Fig. 1. Fig. 1 is a front view showing an example of the configuration of the array antenna 1 according to an embodiment. As shown in Fig. 1, the array antenna 1 according to an embodiment includes a substrate 2 and a plurality of antennas 3.

[0010] In addition, in the accompanying drawings of this disclosure, in order to clarify the positional relationships, mutually perpendicular X-axis, Y-axis, and Z-axis are defined, with the Z-axis direction being the thickness direction of substrate 2, the X-axis direction being the E-plane direction of antenna 3, and the Y-axis direction being the H-plane direction of antenna 3.

[0011] The substrate 2 is made of a dielectric material and has, for example, a flat plate shape. The substrate 2 may be made of a ceramic material such as an aluminum oxide sintered body, a glass ceramic sintered body, a mullite sintered body, or an aluminum nitride sintered body, or may be made of an organic material.

[0012] A plurality of antennas 3 are arranged along the surface 2a of the substrate 2. For example, 8×8 antennas 3 are arranged in a matrix shape along the surface 2a of the substrate 2. Note that in the present disclosure, the number and arrangement of antennas 3 provided in the array antenna 1 are not limited to the example in FIG.

[0013] <Antenna details> Next, details of the antenna 3 according to the embodiment will be described with reference to Fig. 2 to Fig. 17. Fig. 2 is a cross-sectional view showing an example of the configuration of the antenna 3 according to the embodiment, and Fig. 3 is a front view showing an example of the configuration of the antenna 3 according to the embodiment.

[0014] As shown in FIG. 2 and other figures, the antenna 3 according to this embodiment is a patch antenna (microstrip antenna) configured by arranging a plurality of metal layers on the surface 2a of the substrate 2 and inside the substrate 2.

[0015] The antenna 3 includes metal layers arranged parallel to the surface 2a of the substrate 2, namely, a feed layer 11, a ground layer 12, a feed patch layer 13, a first parasitic patch layer 14, and a second parasitic patch layer 15.

[0016] The antenna 3 also includes a feed via 21, an inter-patch via 22, and a short-circuit via 23 as via conductors arranged perpendicular to the front surface 2a of the substrate 2. The inter-patch via 22 is an example of a first via conductor, and the short-circuit via 23 is an example of a second via conductor.

[0017] These metal layers and via conductors are made of metal materials such as copper, silver, palladium, gold, platinum tungsten, molybdenum, or manganese, or alloy materials or mixed materials containing these metal materials as main components.

[0018] Of the above-mentioned metal layers, the power supply layer 11 is disposed farthest from the surface 2a of the substrate 2. The power supply layer 11 is electrically connected to a control IC (not shown).

[0019] The control IC outputs, for example, a modulated electrical signal as an electrical signal corresponding to the radio waves to be transmitted to the power supply patch layer 13 via the power supply layer 11 and the power supply vias 21. The control IC also collects an electrical signal corresponding to the radio waves received by the antenna 3 from the power supply patch layer 13 via the power supply vias 21 and the power supply layer 11.

[0020] The ground layer 12 is disposed inside the substrate 2, closer to the front surface 2a than the power supply layer 11. The ground layer 12 is connected to a ground potential (not shown).

[0021] The power supply patch layer 13 is disposed inside the substrate 2, closer to the front surface 2a than the ground layer 12. The power supply patch layer 13 is electrically connected to the power supply layer 11 through a power supply via 21, and receives an electrical signal from the control IC described above.

[0022] The power supply patch layer 13 is, for example, a square shape with sides having lengths according to the frequency of radio waves to be transmitted and received, as shown in Fig. 3. Note that in the present disclosure, the power supply patch layer 13 is not limited to a square shape and may have various shapes.

[0023] The first parasitic patch layer 14 is disposed on the surface 2a of the substrate 2. The first parasitic patch layer 14 is, for example, as shown in Fig. 3, square and has approximately the same size and shape as the fed patch layer 13. Note that the sizes of the first parasitic patch layer 14 and the fed patch layer 13 referred to here can be the areas of each layer in a planar view. The first parasitic patch layer 14 is disposed so as to overlap with the fed patch layer 13 in a planar view.

[0024] The second parasitic patch layer 15 is disposed between the feed patch layer 13 and the first parasitic patch layer 14 inside the substrate 2. More specifically, the second parasitic patch layer 15 is disposed between the feed patch layer 13 and the first parasitic patch layer 14 in the thickness direction (Z direction) of the substrate 2. The second parasitic patch layer 15 has a square shape as shown in Fig. 3, for example, and has a smaller area in plan view than the feed patch layer 13 and the first parasitic patch layer 14. The second parasitic patch layer 15 is disposed inside the feed patch layer 13 in plan view.

[0025] The power feed via 21 electrically connects the power feed layer 11 and the power feed patch layer 13. Since a dielectric constituting the substrate 2 is disposed between the power feed via 21 and the ground layer 12, the power feed via 21 and the ground layer 12 are electrically insulated from each other.

[0026] In the antenna 3 according to the embodiment, two power feed vias 21 (hereinafter also referred to as power feed vias 21A and 21B) are connected to one power feed patch layer 13, as shown in FIG.

[0027] Furthermore, the power feed vias 21 are connected to positions away from the center of the power feed patch layer 13, for example, based on the input impedance (reflection characteristics) requirements of the antenna 3, and are located at positions differing by 90° so as to accommodate polarization characteristics in two orthogonal directions. For example, the power feed via 21A is connected to a position away from the center of the power feed patch layer 13 in the -Y direction, and the power feed via 21B is connected to a position away from the center of the power feed patch layer 13 in the -X direction.

[0028] The inter-patch vias 22 electrically connect the powered patch layer 13 , the second parasitic patch layer 15 , and the first parasitic patch layer 14 .

[0029] In the antenna 3 according to the embodiment, as shown in FIG. 3, two inter-patch vias 22 (hereinafter also referred to as inter-patch vias 22A and 22B) are connected to one power feeding patch layer 13.

[0030] Moreover, the inter-patch via 22 is connected, for example, to a position away from the center of the power supply patch layer 13 and closer to the center of the power supply patch layer 13 than the power supply via 21. For example, the inter-patch via 22A is connected to a position away from the center of the power supply patch layer 13 in the -Y direction, and the inter-patch via 22B is connected to a position away from the center of the power supply patch layer 13 in the -X direction.

[0031] The short-circuiting vias 23 electrically connect the power supply patch layer 13 and the ground layer 12. In the antenna 3 according to the embodiment, two short-circuiting vias 23 (hereinafter also referred to as short-circuiting vias 23A and 23B) are connected to one power supply patch layer 13, as shown in FIG.

[0032] Moreover, the short-circuiting via 23 is connected, for example, to a position away from the center of the power feed patch layer 13 and closer to the center of the power feed patch layer 13 than the power feed via 21. For example, the short-circuiting via 23A is connected to a position away from the center of the power feed patch layer 13 in the +Y direction, and the short-circuiting via 23B is connected to a position away from the center of the power feed patch layer 13 in the +X direction.

[0033] Here, in the embodiment, a second parasitic patch layer 15 is provided between the feeding patch layer 13 and the first parasitic patch layer 14. The second parasitic patch layer 15 is smaller than the feeding patch layer 13 and the first parasitic patch layer 14. That is, the area of ​​the second parasitic patch layer 15 in a plan view is smaller than the areas of the feeding patch layer 13 and the first parasitic patch layer 14 in a plan view.

[0034] As a result, in this embodiment, it is possible to improve the gain characteristics of the antenna 3 and the array antenna 1 in a wide band. The results are described in detail below.

[0035] Fig. 4 is a diagram showing gain characteristics of the antenna 3 according to the embodiment and reference example 1. In the present disclosure, the antenna 3 according to reference example 1 is an antenna having a configuration in which the second parasitic patch layer 15 is removed from the antenna 3 according to the embodiment shown in Figs. 2 and 3.

[0036] As shown in FIG. 4, the antenna 3 according to the embodiment can expand the range of high gain to a wider band (for example, around 31 (GHz)) compared to the reference example 1.

[0037] In this way, in the embodiment, by providing a second parasitic patch layer 15 having a smaller area than the powered patch layer 13 and the first parasitic patch layer 14, the gain characteristics of the antenna 3 and the array antenna 1 can be improved in a wide band.

[0038] 5 is a diagram showing the reflection characteristics of the antenna 3 according to the embodiment and reference example 1. The antenna 3 according to the embodiment can expand the resonant frequency to a wider band (for example, around 31.5 (GHz)) compared to reference example 1.

[0039] 6 is a diagram showing gain characteristics when power is fed from one of the power feed vias 21A in the array antenna 1 of the embodiment and reference example 1. In this disclosure, the array antenna 1 of reference example 1 is an array antenna having a configuration in which the second parasitic patch layer 15 is removed from all antennas 3 in the array antenna 1 shown in FIG.

[0040] As shown in FIG. 6, the array antenna 1 according to the embodiment can obtain high gain in all bands and can extend the range of high gain to a wider band (for example, around 31 (GHz)) compared to reference example 1.

[0041] 6, the fluctuation in the band from 26.5 (GHz) to 29.5 (GHz) is smaller than that in Reference Example 1. Specifically, the fluctuation range is 0.5 (dBi) in Reference Example 1, whereas the fluctuation range is 0.4 (dBi) in the embodiment.

[0042] That is, in the embodiment, by providing the second parasitic patch layer 15 having a smaller area than the fed patch layer 13 and the first parasitic patch layer 14, it is possible to reduce the fluctuation of the gain characteristics within a desired band.

[0043] FIG. 7 is a diagram showing gain characteristics when power is fed from the other power feed via 21B in the array antenna 1 of the embodiment and reference example 1.

[0044] As shown in FIG. 7, the array antenna 1 according to the embodiment can obtain high gain in all bands and can extend the range of high gain to a wider band (for example, around 31 (GHz)) compared to reference example 1.

[0045] 7, the fluctuation in the band from 26.5 (GHz) to 29.5 (GHz) is smaller than that in Reference Example 1. Specifically, the fluctuation range is 0.6 (dBi) in Reference Example 1, whereas the fluctuation range is 0.5 (dBi) in the embodiment.

[0046] That is, in the embodiment, by providing a second parasitic patch layer 15 having an area smaller than that of the powered patch layer 13 and the first parasitic patch layer 14, it is possible to reduce the fluctuation in gain characteristics within the desired band even when power is supplied from a different power supply point.

[0047] Fig. 8 to Fig. 13 are diagrams showing the beam steering characteristics of the array antenna 1 of the embodiment and reference example 1. Fig. 8 to Fig. 10 show the beam steering characteristics in the E plane of the array antenna 1, and Fig. 11 to Fig. 13 show the beam steering characteristics in the H plane of the array antenna 1. The results shown in Fig. 8 to Fig. 13 correspond to the E plane steering and H plane steering in the power feed via 21A (see Fig. 3).

[0048] In addition, Figures 8 and 11 show beam steering characteristics at a frequency of 26.5 (GHz), Figures 9 and 12 show beam steering characteristics at a frequency of 28 (GHz), and Figures 10 and 13 show beam steering characteristics at a frequency of 29.5 (GHz).

[0049] As shown in Figures 8 to 10, the array antenna 1 of the embodiment can improve the gain in the front direction of the E-plane (for example, within ±30°) in a wide band (here, 26.5 (GHz) to 29.5 (GHz)) compared to reference example 1.

[0050] Moreover, as shown in Figures 11 to 13, the array antenna 1 of the embodiment can improve the gain in the front direction of the H plane (for example, within ±30°) in a wide band (here, 26.5 (GHz) to 29.5 (GHz)) compared to reference example 1.

[0051] Fig. 14 is a diagram showing gain characteristics when the size (dimensions) of the second parasitic patch layer 15 is changed when power is fed from one power feed via 21A in the array antenna 1 according to the embodiment. Fig. 15 is a diagram showing gain characteristics when the size of the second parasitic patch layer 15 is changed when power is fed from the other power feed via 21B in the array antenna 1 according to the embodiment. Note that the size of the second parasitic patch layer 15 here can also be referred to as the area of ​​the second parasitic patch layer 15 in a planar view.

[0052] Specifically, Figures 14 and 15 show the results when the length of one side of the second parasitic patch layer 15 is changed from 1.5 mm to 1.8 mm for the powered patch layer 13 and the first parasitic patch layer 14, which are 2.67 mm square.

[0053] As shown in Figures 14 and 15, in the array antenna 1 of the embodiment, the gain characteristics are best when the second parasitic patch layer 15 is 1.7 (mm) square (i.e., the length of one side is approximately 64 (%) of the fed patch layer 13).

[0054] In this manner, in the embodiment, by setting the length of one side of the second parasitic patch layer 15 to 50(%) to 70(%) of the length of one side of the powered patch layer 13, good gain characteristics can be obtained.

[0055] 16 is a diagram showing gain characteristics when the distance d2 between the feed patch layer 13 and the second parasitic patch layer 15 and the distance d3 between the first parasitic patch layer 14 and the second parasitic patch layer 15 are changed in the antenna 3 of the embodiment and reference example 1. Note that the distance d2 (see FIG. 2) is the same value as the distance d3 (see FIG. 2).

[0056] Specifically, Figure 16 shows the results when the distance d1 (see Figure 2) between the ground layer 12 and the power supply patch layer 13 is 612 (μm), and the distance d2 between the power supply patch layer 13 and the second parasitic patch layer 15 and the distance d3 between the first parasitic patch layer 14 and the second parasitic patch layer 15 are changed to 80 (μm) to 150 (μm).

[0057] As shown in Figure 16, in the antenna 3 of the embodiment, the distance d2 between the powered patch layer 13 and the second parasitic patch layer 15 and the distance d3 between the first parasitic patch layer 14 and the second parasitic patch layer 15 are set to 120 (μm) or less, thereby making it possible to expand the range of high gain to a wider bandwidth (for example, around 31 (GHz)).

[0058] In this way, in the embodiment, the distance d2 between the powered patch layer 13 and the second parasitic patch layer 15 and the distance d3 between the first parasitic patch layer 14 and the second parasitic patch layer 15 are set to 10% to 20% of the distance d1 between the powered patch layer 13 and the ground layer 12, thereby making it possible to expand the range of high gain to a wider bandwidth.

[0059] In the embodiment, it is preferable that the distance d2 between the feeding patch layer 13 and the second parasitic patch layer 15 and the distance d3 between the first parasitic patch layer 14 and the second parasitic patch layer 15 are set to 15% to 20% of the distance d1 between the feeding patch layer 13 and the ground layer 12. This makes it possible to expand the range of high gain to a wider band and to suppress a decrease in gain in a desired band.

[0060] In the embodiment, the distance d2 between the feeding patch layer 13 and the second parasitic patch layer 15 and the distance d3 between the first parasitic patch layer 14 and the second parasitic patch layer 15 may be 0.8% to 3% of the wavelength of the radio wave radiated from the feeding patch layer 13. For example, when the dielectric constant of the substrate 2 is 3.28 and the frequency of the radio wave is 28 GHz, the wavelength of the radio wave radiated from the feeding patch layer 13 is 5.92 mm. This allows the range of high gain to be expanded to a wider band in the embodiment.

[0061] Fig. 17 is a diagram showing the change in gain characteristic when the size of the second parasitic patch layer 15 is changed in the embodiment. Note that the example of Fig. 17 shows the change in gain characteristic when the size of the powered patch layer 13 and the first parasitic patch layer 14 is 2.67 (mm) square.

[0062] As shown in Fig. 17, when the size of the second parasitic patch layer 15 is equal to or larger than the sizes of the powered patch layer 13 and the first parasitic patch layer 14, the gain characteristics in the band of 26.5 (GHz) to 29.5 (GHz) decrease. Note that the examples in Figs. 4 to 16 above show the results when the size of the second parasitic patch layer 15 is 1.7 (mm) square.

[0063] In the embodiment, the feed patch layer 13 and the first parasitic patch layer 14 may have the same size. This can further improve the gain characteristics of the antenna 3.

[0064] In addition, the present disclosure is not limited to the case where the powered patch layer 13 and the first parasitic patch layer 14 are the same size, and the powered patch layer 13 and the first parasitic patch layer 14 may be different sizes.

[0065] In the embodiment, the antenna 3 may be provided with inter-patch vias 22 connecting the powered patch layer 13, the second parasitic patch layer 15, and the first parasitic patch layer 14. This can further improve the gain characteristics of the antenna 3.

[0066] In the embodiment, the antenna 3 may be provided with a short-circuit via 23 that connects between the feeding patch layer 13 and the ground layer 12. This can further improve the gain characteristics of the antenna 3.

[0067] <Another embodiment> Next, details of the antenna 3 according to another embodiment of the present invention will be described with reference to Fig. 18 to Fig. 23. Fig. 18 is a cross-sectional view showing an example of the configuration of the antenna 3 according to another embodiment of the present invention, and Fig. 19 is a front view showing an example of the configuration of the antenna 3 according to the another embodiment of the present invention.

[0068] As shown in FIG. 18 and other figures, an antenna 3 according to another embodiment differs from the above-described embodiment in that an inter-patch via 22 is not provided.

[0069] Even with this configuration, by providing a second parasitic patch layer 15 between the powered patch layer 13 and the first parasitic patch layer 14, which is smaller than the powered patch layer 13 and the first parasitic patch layer 14, it is possible to improve the gain characteristics of the antenna 3 and the array antenna 1. The details of the results are described below.

[0070] Fig. 20 is a diagram showing gain characteristics of the antenna 3 according to another embodiment of the embodiment and Reference Example 2. In the present disclosure, the antenna 3 according to Reference Example 2 is an antenna having a configuration in which the second parasitic patch layer 15 is removed from the antenna 3 according to the other embodiment shown in Figs. 18 and 19.

[0071] As shown in FIG. 20, the antenna 3 according to the other embodiment can expand the range of high gain to a wider band (for example, around 30 (GHz)) compared to the reference example 2.

[0072] Thus, in another embodiment, by providing a second parasitic patch layer 15 having an area smaller than that of the powered patch layer 13 and the first parasitic patch layer 14, the gain characteristics of the antenna 3 and the array antenna 1 can be improved in a wide band.

[0073] 21 is a diagram showing the reflection characteristics of the antenna 3 according to another embodiment of the present invention and Reference Example 2. The antenna 3 according to the another embodiment can expand the resonant frequency to a wider band (for example, around 30 (GHz)) compared to Reference Example 2.

[0074] 22 is a diagram showing gain characteristics when power is fed from one of the power feed vias 21A in the array antenna 1 of another embodiment and Reference Example 2. In the present disclosure, the array antenna 1 of Reference Example 2 is an array antenna having a configuration in which the second parasitic patch layer 15 and the inter-patch vias 22 are removed from all the antennas 3 in the array antenna 1 shown in FIG.

[0075] As shown in FIG. 22, the array antenna 1 according to the other embodiment can obtain a higher gain in the desired band of 26.5 (GHz) to 29.5 (GHz) as compared with the reference example 2.

[0076] FIG. 23 is a diagram showing gain characteristics when power is fed from the other power feed via 21B in the array antenna 1 of the other embodiment and the reference example 2.

[0077] As shown in FIG. 23, the array antenna 1 according to the other embodiment can obtain a higher gain in the desired band of 26.5 (GHz) to 29.5 (GHz) as compared with the reference example 2.

[0078] The above-mentioned antenna 3 becomes a communication module when combined with an RF element, for example. Therefore, this communication module can also achieve a broadband gain characteristic and an improved gain characteristic.

[0079] The antenna 3 according to the embodiment includes a substrate 2, a ground layer 12, a feed patch layer 13, a first parasitic patch layer 14, and a second parasitic patch layer 15. The substrate 2 is made of a dielectric material. The ground layer 12 is connected to a ground potential. The feed patch layer 13 is located closer to the surface 2a of the substrate 2 than the ground layer 12 inside the substrate 2. The first parasitic patch layer 14 is located closer to the surface 2a of the substrate 2 than the feed patch layer 13. The second parasitic patch layer 15 is located between the feed patch layer 13 and the first parasitic patch layer 14 inside the substrate 2. The second parasitic patch layer 15 is smaller than the feed patch layer 13 and the first parasitic patch layer 14. This allows the gain characteristics to be improved in a wide band.

[0080] Moreover, in the antenna 3 according to the embodiment, the first parasitic patch layer 14 has the same size as the fed patch layer 13. This makes it possible to further improve the gain characteristics of the antenna 3.

[0081] Moreover, the antenna 3 according to the embodiment further includes a first via conductor (inter-patch via 22) that connects between the fed patch layer 13, the second parasitic patch layer 15, and the first parasitic patch layer 14. This can further improve the gain characteristics of the antenna 3. In this case, it is possible to widen the bandwidth as well as improve the gain.

[0082] Moreover, the antenna 3 according to the embodiment further includes a second via conductor (short-circuit via 23) that connects between the feeding patch layer 13 and the ground layer 12. This can further improve the gain characteristics of the antenna 3.

[0083] In the antenna 3 according to the embodiment, the feed patch layer 13 and the second parasitic patch layer 15 have a square shape in a plan view, and the length of one side of the second parasitic patch layer 15 is 50(%) to 70(%) of the length of one side of the feed patch layer 13. This makes it possible to obtain good gain characteristics.

[0084] In the antenna 3 according to the embodiment, the distance d2 between the feed patch layer 13 and the second parasitic patch layer 15 is 10% to 20% of the distance d1 between the feed patch layer 13 and the ground layer 12. This makes it possible to expand the range of high gain to a wider band.

[0085] In the antenna 3 according to the embodiment, the distance d2 between the powered patch layer 13 and the second parasitic patch layer 15 is 0.8% to 3% of the wavelength of the radio wave radiated from the powered patch layer 13. This makes it possible to expand the range of high gain to a wider band.

[0086] Although the embodiment of the present disclosure has been described above, the present disclosure is not limited to the above embodiment, and various modifications are possible without departing from the spirit of the present disclosure. For example, in the above embodiment, an example in which the first parasitic patch layer 14 is disposed on the surface 2a of the substrate 2 is shown, but the present disclosure is not limited to such an example, and the first parasitic patch layer 14 may be disposed inside the substrate 2.

[0087] In addition, in the above embodiment, an example is shown in which a short-circuit via 23 is provided in the antenna 3 to connect the ground layer 12 and the power supply patch layer 13, but the present disclosure is not limited to such an example, and such a short-circuit via 23 does not have to be provided in the antenna 3.

[0088] Further advantages and other aspects may readily occur to those skilled in the art. Thus, the disclosure in its broader aspects is not limited to the specific details and representative embodiments shown and described above. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and equivalents thereof. [Explanation of symbols]

[0089] 1 Array Antenna 2. Board 2a surface 3 Antennas 11 Feed layer 12 Ground Layer 13 Power supply patch layer 14 First parasitic patch layer 15 Second parasitic patch layer 21, 21A, 21B Power supply via 22, 22A, 22B: Inter-patch vias (an example of a first via conductor) 23, 23A, 23B: Shorting vias (an example of a second via conductor) d1, d2, d3 intervals

Claims

1. A substrate made of a dielectric material; A ground layer connected to a ground potential; a power supply patch layer located inside the substrate and closer to the front surface of the substrate than the ground layer; a first parasitic patch layer located on the front surface side of the substrate relative to the powered patch layer; a second parasitic patch layer located inside the substrate between the powered patch layer and the first parasitic patch layer; a first via conductor connecting the powered patch layer, the second parasitic patch layer, and the first parasitic patch layer; Equipped with The second parasitic patch layer has an area smaller than that of the powered patch layer and the first parasitic patch layer. antenna.

2. A substrate made of a dielectric material; A ground layer connected to a ground potential; a power supply patch layer located inside the substrate and closer to the front surface of the substrate than the ground layer; a first parasitic patch layer located on the front surface side of the substrate relative to the powered patch layer; a second parasitic patch layer located inside the substrate between the powered patch layer and the first parasitic patch layer; a second via conductor connecting the power supply patch layer and the ground layer; Equipped with The second parasitic patch layer has an area smaller than that of the powered patch layer and the first parasitic patch layer. antenna.

3. A substrate made of a dielectric material; A ground layer connected to a ground potential; a power supply patch layer located inside the substrate and closer to the front surface of the substrate than the ground layer; a first parasitic patch layer located on the front surface side of the substrate relative to the powered patch layer; a second parasitic patch layer located inside the substrate between the powered patch layer and the first parasitic patch layer; Equipped with the second parasitic patch layer has an area smaller than that of the powered patch layer and the first parasitic patch layer; the powered patch layer and the second parasitic patch layer have a square shape in a plan view, The length of one side of the second parasitic patch layer is 50% to 70% of the length of one side of the powered patch layer. antenna.

4. A substrate made of a dielectric material; A ground layer connected to a ground potential; a power supply patch layer located inside the substrate and closer to the front surface of the substrate than the ground layer; a first parasitic patch layer located on the front surface side of the substrate relative to the powered patch layer; a second parasitic patch layer located inside the substrate between the powered patch layer and the first parasitic patch layer; Equipped with the second parasitic patch layer has an area smaller than that of the powered patch layer and the first parasitic patch layer; The distance between the power supply patch layer and the second parasitic patch layer is 10% to 20% of the distance between the power supply patch layer and the ground layer. antenna.

5. A substrate made of a dielectric material; A ground layer connected to a ground potential; a power supply patch layer located inside the substrate and closer to the front surface of the substrate than the ground layer; a first parasitic patch layer located on the front surface side of the substrate relative to the powered patch layer; a second parasitic patch layer located inside the substrate between the powered patch layer and the first parasitic patch layer; Equipped with the second parasitic patch layer has an area smaller than that of the powered patch layer and the first parasitic patch layer; The distance between the powered patch layer and the second parasitic patch layer is 0.8% to 3% of the wavelength of the radio wave radiated from the powered patch layer. antenna.

6. The first parasitic patch layer is the same size as the powered patch layer. An antenna according to any one of claims 1 to 5.

7. An antenna according to any one of claims 1 to 5; An RF element; A communication module comprising:

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