Optical detector, optical detection system, lidar device, and moving object

Abstract

To provide a light detector, light detection system, lidar device and mobile body which can reduce noise.SOLUTION: According to one embodiment, a light detector includes a plurality of elements, a plurality of insulating parts, and an intermediate part. The plurality of elements are arranged along a first direction and a second direction that cross each other. Each of the plurality of elements includes: a first semiconductor region that is of a first conductivity type; and a second semiconductor region that is located around the first semiconductor region in a first plane that is along the first and second directions and is of a second conductivity type. The plurality of insulating parts are located respectively around the plurality of elements in the first plane. The intermediate part is located around the plurality of insulating parts in the first plane and includes a semiconductor.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] Embodiments of the present invention relate to a light detector, a light detection system, a LIDAR device, and a moving object. [Background technology]

[0002] There is a photodetector that detects light incident on a semiconductor region, and there is a demand for reducing noise in the photodetector. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. WO2019-098035 Summary of the Invention [Problem to be solved by the invention]

[0004] Embodiments of the present invention provide a photodetector, a photodetection system, a LIDAR device, and a moving object capable of reducing noise. [Means for solving the problem]

[0005] A photodetector according to an embodiment includes a plurality of elements, a plurality of insulating portions, and an intermediate portion. The plurality of elements are provided along a first direction and a second direction that intersect with each other. Each of the plurality of elements includes a first semiconductor region of a first conductivity type, and a second semiconductor region of a second conductivity type provided around the first semiconductor region on a first surface along the first direction and the second direction. The plurality of insulating portions are provided around the plurality of elements on the first surface, respectively. The intermediate portion is provided around each of the plurality of insulating portions on the first surface, and includes a semiconductor. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic plan view showing a photodetector according to the first embodiment. [Diagram 2] FIG. 2 is an enlarged view of a portion A of FIG. [Diagram 3] FIG. 3 is a cross-sectional view taken along line A1-A2 of FIG. [Figure 4] FIG. 4 is a schematic diagram showing a manufacturing process of the photodetector according to the first embodiment. [Diagram 5] FIG. 5 is a schematic diagram showing a manufacturing process of the photodetector according to the first embodiment. [Figure 6] FIG. 6 is a schematic diagram showing a manufacturing process of the photodetector according to the first embodiment. [Figure 7] FIG. 7 is a schematic diagram showing a manufacturing process of the photodetector according to the first embodiment. [Figure 8] FIG. 8 is a schematic diagram showing a manufacturing process of the photodetector according to the first embodiment. [Figure 9] FIG. 9 is a schematic diagram showing a manufacturing process of the photodetector according to the first embodiment. [Figure 10] FIG. 10 is a schematic diagram showing a manufacturing process of the photodetector according to the first embodiment. [Figure 11] FIG. 11 is a schematic diagram showing a manufacturing process of the photodetector according to the first embodiment. [Figure 12] FIG. 12 is a schematic diagram showing a manufacturing process of the photodetector according to the first embodiment. [Figure 13] FIG. 13 is a schematic diagram showing a manufacturing process of the photodetector according to the first embodiment. [Figure 14] FIG. 14 is a schematic view showing a manufacturing process of the photodetector according to the first embodiment. [Figure 15] FIG. 15 is a schematic diagram showing a manufacturing process of the photodetector according to the first embodiment. [Figure 16] FIG. 16 is a schematic view showing a manufacturing process of the photodetector according to the first embodiment. [Figure 17] FIG. 17 is a schematic view showing a manufacturing process of the photodetector according to the first embodiment. [Figure 18] FIG. 18 is a schematic view showing a manufacturing process of the photodetector according to the first embodiment. [Figure 19]FIG. 19 is a cross-sectional view showing a part of a photodetector according to a reference example. [Figure 20] FIG. 20 is an enlarged cross-sectional view of a part of the cross section of the photodetector according to the first embodiment. [Figure 21] FIG. 21 is a schematic plan view illustrating a portion of the photodetector according to the first embodiment. [Figure 22] FIG. 22 is a schematic plan view illustrating a portion of the photodetector according to the first embodiment. [Diagram 23] FIG. 23 is a schematic plan view illustrating a part of a photodetector according to a reference example. [Figure 24] FIG. 24 is a schematic plan view showing a part of a photodetector according to a modified example of the first embodiment. [Diagram 25] FIG. 25 is a cross-sectional view taken along the line A1-A2 of FIG. [Figure 26] FIG. 26 is a schematic plan view showing a photodetector according to the second embodiment. [Figure 27] FIG. 27 is an enlarged view of a portion A of FIG. [Figure 28] FIG. 28 is a cross-sectional view taken along the line A1-A2 of FIG. [Figure 29] FIG. 29 is a schematic cross-sectional view showing a part of the photodetector according to the second embodiment. [Diagram 30] FIG. 30 is a schematic plan view showing a part of the photodetector according to the third embodiment. [Diagram 31] FIG. 31 is a cross-sectional view taken along the line A1-A2 of FIG. [Diagram 32] FIG. 32 is an enlarged cross-sectional view of a part of a cross section of the photodetector according to the third embodiment. [Diagram 33] FIG. 33 is a schematic plan view showing a part of the photodetector according to the fourth embodiment. [Diagram 34] FIG. 34 is a cross-sectional view taken along the line A1-A2 of FIG. [Diagram 35] FIG. 35 is a schematic diagram showing a manufacturing process of the photodetector according to the fourth embodiment. [Diagram 36] FIG. 36 is a schematic diagram showing a manufacturing process of the photodetector according to the fourth embodiment. [Figure 37] FIG. 37 is a schematic diagram showing a manufacturing process of the photodetector according to the fourth embodiment. [Figure 38] FIG. 38 is a schematic diagram showing a manufacturing process of the photodetector according to the fourth embodiment. [Figure 39] FIG. 39 is a schematic diagram showing a manufacturing process of the photodetector according to the fourth embodiment. [Diagram 40] FIG. 40 is a schematic diagram showing a manufacturing process of the photodetector according to the fourth embodiment. [Diagram 41] FIG. 41 is a schematic diagram showing a manufacturing process of the photodetector according to the fourth embodiment. [Diagram 42] FIG. 42 is a schematic diagram showing a manufacturing process of the photodetector according to the fourth embodiment. [Diagram 43] FIG. 43 is a schematic diagram showing a manufacturing process of the photodetector according to the fourth embodiment. [Diagram 44] FIG. 44 is a schematic diagram showing a manufacturing process of the photodetector according to the fourth embodiment. [Diagram 45] FIG. 45 is a schematic diagram showing a manufacturing process of the photodetector according to the fourth embodiment. [Diagram 46] FIG. 46 is a schematic diagram showing a manufacturing process of the photodetector according to the fourth embodiment. [Figure 47] FIG. 47 is a schematic diagram showing a manufacturing process of the photodetector according to the fourth embodiment. [Figure 48] FIG. 48 is a schematic diagram showing a manufacturing process of the photodetector according to the fourth embodiment. [Figure 49] FIG. 49 is a schematic diagram showing a manufacturing process of the photodetector according to the fourth embodiment. [Figure 50] FIG. 50 is a schematic diagram showing a manufacturing process of the photodetector according to the fourth embodiment. [Figure 51] FIG. 51 is a schematic cross-sectional view showing a part of the photodetector according to the fourth embodiment. [Figure 52] FIG. 52 is a schematic cross-sectional view showing a part of the photodetector according to the fourth embodiment. [Diagram 53]FIG. 53 is a schematic plan view showing a part of the photodetector according to the fifth embodiment. [Figure 54] FIG. 54 is a cross-sectional view taken along line A1-A2 of FIG. [Figure 55] FIG. 55 is a schematic diagram showing a manufacturing process of the photodetector according to the fifth embodiment. [Figure 56] FIG. 56 is a schematic diagram showing a manufacturing process of the photodetector according to the fifth embodiment. [Figure 57] FIG. 57 is a schematic diagram showing a manufacturing process of the photodetector according to the fifth embodiment. [Figure 58] FIG. 58 is a schematic cross-sectional view showing a part of the photodetector according to the fifth embodiment. [Figure 59] FIG. 59 is a schematic diagram illustrating an active quench circuit. [Figure 60] FIG. 60 is a schematic diagram illustrating a LIDAR (Laser Imaging Detection and Ranging) device according to an embodiment. [Figure 61] FIG. 61 is a diagram for explaining detection of a detection target by a LIDAR device. [Figure 62] FIG. 62 is a schematic top view of a moving body equipped with a lidar device according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios of each part may be different depending on the drawing. In this specification and each drawing, elements similar to those already explained are given the same reference numerals and detailed explanations are omitted as appropriate. In each embodiment described below, the p-type and n-type of each semiconductor region may be reversed to implement each embodiment. In that case, the voltage applied to the pn junction is also reversed appropriately.

[0008] (First embodiment) Fig. 1 is a schematic plan view showing a photodetector according to a first embodiment, Fig. 2 is an enlarged view of a portion A in Fig. 1, Fig. 3 is a cross-sectional view taken along line A1-A2 in Fig. 2. 1 to 3, the photodetector 1 according to the first embodiment includes a p-type semiconductor layer 11 (first semiconductor layer), a p-type semiconductor layer 12 (second semiconductor layer), a plurality of elements 20, a plurality of insulating sections 30, an insulating layer 35, an intermediate section 40, a quench section 50, a first wiring 51, a second wiring 52, a pad 61 (first electrode), and a pad 62 (second electrode). Note that in FIG. 1, elements other than the elements 20, the wirings, the pad 61, and the pad 62 are omitted. In FIG. 2, the insulating layer 35 is omitted.

[0009] 1, the multiple elements 20 are arranged along two directions that intersect with each other. Here, one arrangement direction is the X direction (first direction). The other arrangement direction that intersects with the X direction is the Y direction (second direction). In the illustrated example, the X direction and the Y direction are mutually orthogonal.

[0010] The pads 61 and 62 are provided on the upper surface of the photodetector 1 and are spaced apart from each other. The pads 61 and 62 are electrically isolated from each other.

[0011] 3, a p-type (first conductivity type) semiconductor layer 11 is located in the lower part of the photodetector 1. A p-type semiconductor layer 12 is provided on the p-type semiconductor layer 11. A plurality of elements 20, a plurality of insulating portions 30, and an intermediate portion 40 are provided in the p-type semiconductor layer 12.

[0012] In addition, although "up" and "down" are used here to explain the relative positions of the components, these directions are unrelated to the direction of gravity. For example, "up" corresponds to the direction from the p-type semiconductor layer 11 toward the p-type semiconductor layer 12, and "down" corresponds to the opposite direction.

[0013] Each element 20 includes a p-type semiconductor region 21 (first semiconductor region), an n-type (second conductivity type) semiconductor region 22 (second semiconductor region), a p-type semiconductor region 23 (third semiconductor region), a p-type contact region 24, an n-type contact region 25, and an n-type guard ring region 26 (fourth semiconductor region).

[0014] The n-type semiconductor region 22 is provided around the p-type semiconductor region 21 on the XY plane (first plane). The n-type semiconductor region 22 contacts the p-type semiconductor region 21. A pn ​​junction is formed between the p-type semiconductor region 21 and the n-type semiconductor region 22. For example, the plane of the pn junction is parallel to the Z direction (third direction) that intersects with the XY plane. In the illustrated example, the Z direction is perpendicular to the XY plane.

[0015] The p-type semiconductor region 23 is surrounded by the p-type semiconductor region 21 in the XY plane. The p-type impurity concentration in the p-type semiconductor region 23 is lower than the p-type impurity concentration in the p-type semiconductor region 21. The p-type contact region 24 is provided on the p-type semiconductor region 23. The p-type impurity concentration in the p-type contact region 24 is higher than the p-type impurity concentration in the p-type semiconductor region 23.

[0016] The n-type contact region 25 is provided on the n-type semiconductor region 22. The n-type impurity concentration in the n-type contact region 25 is higher than the n-type impurity concentration in the n-type semiconductor region 22. The n-type guard ring region 26 is surrounded by the n-type semiconductor region 22 and the n-type contact region 25 in the XY plane. The n-type guard ring region 26 is separated from the p-type contact region 24. The n-type impurity concentration in the n-type guard ring region 26 is lower than the n-type impurity concentration in the n-type contact region 25 and lower than the n-type impurity concentration in the n-type semiconductor region 22.

[0017] 2, the insulating sections 30 are provided around the elements 20 on the XY plane. The insulating sections 30, like the elements 20, are arranged along the X and Y directions.

[0018] As shown in Figures 2 and 3, the intermediate portion 40 is provided between multiple insulating portions 30. As a result, the insulating portions 30 are separated from each other. The intermediate portion 40 surrounds each insulating portion 30 in the XY plane. The intermediate portion 40 includes a semiconductor. The intermediate portion 40 may include an impurity. For example, the intermediate portion 40 is a p-type semiconductor region. The intermediate portion 40 may be an n-type semiconductor region.

[0019] Each insulating portion 30 includes, for example, insulating layers 31 and 32. The insulating layer 32 is provided between the insulating layer 31 and the p-type semiconductor layer 12, between the insulating layer 31 and the element 20, and between the insulating layer 31 and the intermediate portion 40.

[0020] As shown in FIG. 3, guard ring region 27 (fifth semiconductor region) is provided around the bottom of insulating section 30. For example, a part of guard ring region 27 is aligned with n-type semiconductor region 22 in the Z direction. Another part of guard ring region 27 is aligned with insulating section 30 in the Z direction. For example, guard ring region 27 is n-type. The n-type impurity concentration in guard ring region 27 is lower than the n-type impurity concentration in n-type semiconductor region 22. Guard ring region 27 may be p-type.

[0021] The n-type semiconductor region 28 (sixth semiconductor region) is provided between the insulating portion 30 and the intermediate portion 40. The n-type semiconductor region 28 is aligned with a part of the guard ring region 27 in the Z direction. The n-type impurity concentration in the n-type semiconductor region 28 is higher than the n-type impurity concentration in the guard ring region 27.

[0022] The length in the Z direction of each of the p-type semiconductor region 21, the n-type semiconductor region 22, and the p-type semiconductor region 23 is shorter than the length in the Z direction of the insulating portion 30, and longer than the length in the Z direction of each of the p-type contact region 24, the n-type contact region 25, and the n-type guard ring region 26. When viewed from the Z direction, the p-type contact region 24 is located in the center of the element 20. The n-type semiconductor region 22, the n-type contact region 25, and the n-type guard ring region 26 are located on the outer periphery of the element 20.

[0023] As shown in FIG. 2 and FIG. 3, the p-type semiconductor region 21 is electrically connected to the quench portion 50 via the p-type semiconductor region 23, the p-type contact region 24, the plug 46a, and the wiring 46b. As shown in FIG. 2, the quench portion 50 is electrically connected to the first wiring 51 via the plug 47. The quench portion 50 is electrically connected between the p-type semiconductor region 21 and the first wiring 51. The n-type semiconductor region 22 is electrically connected to the second wiring 52 via the n-type contact region 25, the plug 45a, and the wiring 45b. In the illustrated example, the wiring 45b and the second wiring 52 are integrally provided. The wiring 45b and the second wiring 52 may be provided as separate bodies in different layers.

[0024] The second wiring 52 is electrically separated from the first wiring 51. In the illustrated example, the first wiring 51 and the second wiring 52 extend in the X direction. The first wiring 51 and the second wiring 52 are alternately provided in the Y direction. One first wiring 51 is electrically connected to the multiple p-type semiconductor regions 21 via the multiple quench portions 50. The multiple first wirings 51 are electrically connected to a pad 61. One second wiring 52 is electrically connected to the multiple n-type semiconductor regions 22. The multiple second wirings 52 are electrically connected to a pad 62.

[0025] The insulating layer 35 is optically transparent and is provided on the multiple elements 20, the multiple insulating portions 30, and the intermediate portion 40. The plug 45a, the wiring 45b, the plug 46a, the wiring 46b, the plug 46c, the plug 47, the quench portion 50, the first wiring 51, the second wiring 52, and the like are provided in the insulating layer 35. The insulating layer 35 may include multiple insulating films 35a to 35d. The insulating film 35b is provided on the insulating film 35a. The insulating film 35c is provided on the insulating film 35b. The insulating film 35d is provided on the insulating film 35c.

[0026] The operation of the photodetector 1 will now be described. A reverse voltage is applied between the p-type semiconductor region 21 and the n-type semiconductor region 22. That is, a positive operating voltage is applied to the pad 62 with respect to the pad 61. The element 20 includes a PIN diode or an avalanche photodiode. The operating voltage is, for example, +60V to +70V.

[0027] When light is incident on the element 20 from above, carriers are generated in the element 20, the p-type semiconductor layer 12, the upper part of the p-type semiconductor layer 11, and the like. The carriers move along the electric field of the depletion layer spreading from the pn junction between the p-type semiconductor region 21 and the n-type semiconductor region 22. A current based on the carriers flows through the p-type semiconductor region 21 and the first wiring 51 to the pad 61. The incidence of light on the element 20 can be detected based on the current flowing through the pad 61.

[0028] A reverse voltage exceeding the breakdown voltage may be applied between the p-type semiconductor region 21 and the n-type semiconductor region 22. That is, the element 20 may include an avalanche photodiode that operates in the Geiger mode. By operating in the Geiger mode, a pulse-shaped signal is output with a high multiplication factor (in other words, a high gain). This can improve the light receiving sensitivity of the photodetector 1.

[0029] The quench section 50 is provided to suppress the continuation of avalanche breakdown when light is incident on the element 20 and avalanche breakdown occurs. The electrical resistance of the quench section 50 is greater than the electrical resistance of each of the plug and each wiring. The electrical resistance of the quench section 50 is preferably 50 kΩ or more and 6 MΩ or less. When avalanche breakdown occurs and a current flows through the quench section 50, a voltage drop occurs according to the electrical resistance of the quench section 50. The voltage drop reduces the potential difference between the p-type semiconductor region 21 and the n-type semiconductor region 22, and the avalanche breakdown stops. This allows the element 20 to respond quickly with a short time constant, and the next light incident on the element 20 can be detected again.

[0030] An example of the material for each element will be described. The p-type semiconductor layer 11, the p-type semiconductor layer 12, the p-type semiconductor region 21, the n-type semiconductor region 22, the p-type semiconductor region 23, the p-type contact region 24, the n-type contact region 25, the n-type guard ring region 26, the guard ring region 27, the n-type semiconductor region 28, and the intermediate portion 40 contain at least one semiconductor material selected from the group consisting of silicon, silicon carbide, gallium arsenide, and gallium nitride. For example, when these semiconductor regions contain silicon, phosphorus, arsenic, or antimony is used as the n-type impurity. Boron or boron fluoride is used as the p-type impurity.

[0031] The insulating portion 30 and the insulating layer 35 include an insulating material. For example, the insulating material includes silicon and one or two selected from oxygen and nitrogen, and is silicon oxide, silicon nitride, or silicon oxynitride. As an example, the insulating layer 31, the insulating layer 32, the insulating film 35a, and the insulating film 35b include silicon oxide. The insulating films 35c and 35d include silicon nitride. The quench portion 50 includes polysilicon. The quench portion 50 may be doped with n-type impurities or p-type impurities. Each plug, each wiring, the pad 61, and the pad 62 include a metal material such as tungsten, titanium, copper, or aluminum.

[0032] Figures 4 to 18 are schematic diagrams showing the manufacturing process of the photodetector according to the first embodiment. Figures 4(b) to 17(b) are cross-sectional views taken along B1-B2 in Figures 4(a) to 17(a), respectively. Figures 4(a) to 17(a) are cross-sectional views taken along A1-A2 in Figures 4(b) to 17(b), respectively. An example of a preferable method for manufacturing the photodetector 1 according to the first embodiment will be described with reference to FIGS.

[0033] First, as shown in Fig. 4(a) and Fig. 4(b), a wafer W is prepared. The wafer W includes a single crystal p-type silicon substrate 100 and a p-type silicon epitaxial layer 101 provided thereon. The p-type silicon substrate 100 contains 4.0 × 10 18 / cm 3 The p-type silicon epitaxial layer 101 is doped with boron at a concentration of 1.0×10 15 / cm 3 The p-type silicon epitaxial layer 101 is doped with boron at 1000 nm. The thickness (length in the Z direction) of the p-type silicon epitaxial layer 101 is 7 μm.

[0034] As shown in FIG. 5(a) and FIG. 5(b), the surface of the p-type silicon epitaxial layer 101 is oxidized to form a silicon thermal oxide film 102 having a thickness of 100 nm. A silicon nitride film 103 is deposited on the silicon thermal oxide film 102 to a thickness of 300 nm by a low pressure thermal chemical vapor deposition (CVD) method. A silicon oxide film 104 is deposited on the silicon nitride film 103 to a thickness of 1000 nm by a low pressure thermal CVD method. A resist 105 is formed on the silicon oxide film 104. An opening OP is formed in the resist 105 by a lithography process. The position of the opening OP corresponds to the position of an element isolation region 106 to be formed later. Using the resist 105 as a mask, the silicon oxide film 104, the silicon nitride film 103, and the silicon thermal oxide film 102 are etched by a reactive ion etching (RIE) method. As an example, the width of the opening OP is designed to be 0.5 μm. An isolation region 107 is provided between adjacent element isolation regions 106. The width of the inter-isolation region 107 is designed to be 2 μm. The sum of the width of the inter-isolation region 107 and twice the width of the element isolation region 106 is preferably 3 μm or more. This allows secondary photons in the visible region traveling laterally between adjacent cells to be sufficiently absorbed by the silicon of the inter-isolation region 107.

[0035] 6(a) and 6(b), the resist 105 is peeled off. The p-type silicon epitaxial layer 101 exposed through the opening OP is etched using the silicon oxide film 104 as a mask. As a result, a trench structure 108 is formed in the element isolation region 106. The depth of the trench structure 108 is determined by the thickness of the p-type silicon epitaxial layer 101 and the amount of boron diffused from the p-type silicon substrate 100 to the p-type silicon epitaxial layer 101 by thermal steps in the entire process. As an example, the depth of the trench structure 108 is designed to be 5 um.

[0036] As shown in FIGS. 7(a) and 7(b), the surface of the trench structure 108 is oxidized to form a silicon oxide film 110 having a thickness of 50 nm. An n-type avalanche layer 111 is formed on the side and bottom surfaces of the trench structure 108 by ion implantation. Ions are implanted sequentially from four directions OR1 to OR4 tilted by 3 degrees with respect to the Z direction. The implantation angle in this ion implantation can be changed depending on the design of the width and depth of the trench structure 108 and the depth of the pn junction to be formed later. As an example, the n-type avalanche layer 111 is formed by implanting ions in one direction at an implantation acceleration voltage of 50 keV and an implantation dose of 5.0×10 14 / cm 2 The n-type guard ring layer 112 is formed by ion implantation of phosphorus under the conditions of: In order to improve the breakdown voltage at the corners of the bottom of the trench structure 108, boron is counter-ion-implanted into the bottom of the trench structure 108. As a result, an n-type guard ring layer 112 having a lower impurity concentration than the n-type avalanche layer 111 is formed at the bottom of the trench structure 108. As an example, the n-type guard ring layer 112 is formed by ion implantation at an implantation acceleration voltage of 25 keV and an implantation dose of 2.5×10 14 / cm 2 The layer is formed by implanting boron ions under the conditions:

[0037] As shown in Figures 8(a) and 8(b), an oxide film is deposited to a thickness of 1.2 µm inside the trench structure 108 by plasma CVD. The oxide film is densified by nitrogen annealing at 1000°C to form a buried oxide film 113. At the same time, solid-phase diffusion from the buried oxide film 113 to the n-type avalanche layer 111 and activation of the n-type guard ring layer 112 are performed. Using the silicon nitride film 103 as a stopper, the buried oxide film 113 is planarized by CMP processing.

[0038] 9(a) and 9(b), the oxide layer on the silicon nitride film 103 is removed by a hydrofluoric acid treatment. The silicon nitride film 103 is stripped by a thermal phosphoric acid treatment. The silicon thermal oxide film 102 is stripped by a hydrofluoric acid treatment. As a result, an element isolation structure 114 including a silicon oxide film 110 and a buried oxide film 113 is formed in the element isolation region 106.

[0039] As shown in Figures 10(a) and 10(b), the surface of the p-type silicon epitaxial layer 101 is oxidized to form a silicon oxide film 120 with a thickness of 50 nm. A polysilicon film with a thickness of 0.2 um is formed on the silicon oxide film 120 by low pressure thermal CVD. The polysilicon film is processed into a predetermined shape by lithography and RIE processes to form a quench resistor 121. For example, the implantation acceleration voltage is set to 20 keV and the implantation dose is set to 1.0 x 10 so that the quench resistor 121 has a predetermined resistance. 15 / cm 2 Boron ions are implanted under the conditions above, and activation annealing is performed.

[0040] 11(a) and 11(b), a p-type avalanche layer 123 is formed in an element region 122 surrounded by an element isolation structure 114 by a lithography process and ion implantation. The p-type avalanche layer 123 is formed along the n-type avalanche layer 111 and the element isolation structure 114. As an example, the p-type avalanche layer 123 is formed by implantation acceleration voltage of 1 MeV and implantation dose of 3.0×10 12 / cm 2 The layer is formed by implanting boron ions under the conditions:

[0041] 12(a) and 12(b), a p-type anode electrode 124 is formed on the surface of the element region 122 by a lithography process and multiple ion implantations. As an example, the p-type anode electrode 124 is formed by implantation acceleration voltage of 50 keV and implantation dose of 5.0×10 14 / cm 2 The layer is formed by implanting boron ions under the conditions:

[0042] 13(a) and 13(b), an n-type guard ring layer 130 and an n-type cathode electrode 131 are formed on the outer peripheral surface of the element region 122 by a lithography process and ion implantation. As an example, the n-type guard ring layer 130 is formed by implantation acceleration voltage of 200 keV and implantation dose of 3.0×10 12 / cm 2The n-type cathode electrode 131 is formed by ion-implanting phosphorus under the conditions of an implantation acceleration voltage of 50 keV and an implantation dose of 5.0×10 14 / cm 2 The layer is formed by ion-implanting phosphorus under the following conditions: In order to activate the impurity-implanted layer, nitrogen annealing is performed.

[0043] 14(a) and 14(b), a first interlayer insulating film 140 having a thickness of 0.5 um is formed on the silicon oxide film 120 by a CVD method. The first interlayer insulating film 140 is planarized by chemical mechanical polishing (CMP). Contact holes 141 located respectively on the quench resistor 121, the p-type anode electrode 124, and the n-type cathode electrode 131 are formed in the first interlayer insulating film 140 by a lithography process and an RIE process.

[0044] 15(a) and 15(b), titanium 142 and titanium nitride 143, each having a thickness of 10 nm, are formed by sputtering along the inner wall of contact hole 141. Tungsten 144 is formed by CVD to a thickness of 300 nm to fill contact hole 141. Using first interlayer insulating film 140 as a stopper, tungsten 144, titanium nitride 143, and titanium 142 are planarized by CMP.

[0045] As shown in FIG. 16(a) and FIG. 16(b), a metal film having a thickness of 0.5 um is formed on the first interlayer insulating film 140 by a sputtering method. The metal film is processed into a predetermined shape by lithography and RIE methods to form the wirings 145a, 145b, and 145c. A silicon oxide film having a thickness of 0.8 um is formed on the wirings 145a to 145c by a CVD method. The surface of the silicon oxide film is flattened to form the second interlayer insulating film 146. Note that the first interlayer insulating film 140 and the second interlayer insulating film 146 are omitted in FIG. 16(b) and FIG. 17(b).

[0046] As shown in FIG. 17(a), FIG. 17(b), and FIG. 18, a via hole 147 located on the wiring 145c is formed in the second interlayer insulating film 146. The via hole 147 is filled with titanium, titanium nitride, and tungsten. The formation and filling of the via hole 147 are performed by the same method as that shown in FIG. 14(a), FIG. 14(b), FIG. 15(a), FIG. 15(b), FIG. 16(a), and FIG. 16(b). A pad metal wiring 148, a read pad 150a, and a read pad 150b are formed. A silicon nitride film having a thickness of 0.3 um is formed as a passivation film 149 on the second interlayer insulating film 146 and the pad metal wiring 148 by the CVD method. A part of the passivation film 149 is removed by the RIE method to expose the read pads 150a and 150b. In this manner, the photodetector 1 according to the first embodiment is obtained.

[0047] For example, the p-type silicon substrate 100 in the above-described manufacturing method corresponds to the p-type semiconductor layer 11 of the photodetector 1 shown in FIGS. 1 to 3. A part of the p-type silicon epitaxial layer 101 corresponds to the p-type semiconductor layer 12. The p-type avalanche layer 123 corresponds to the p-type semiconductor region 21. A part of the n-type avalanche layer 111 corresponds to the n-type semiconductor region 22. Another part of the p-type silicon epitaxial layer 101 corresponds to the p-type semiconductor region 23. The p-type anode electrode 124 corresponds to the p-type contact region 24. The n-type cathode electrode 131 corresponds to the n-type contact region 25. The n-type guard ring layer 130 corresponds to the n-type guard ring region 26. The n-type guard ring layer 112 corresponds to the guard ring region 27. Another part of the n-type avalanche layer 111 located between the element isolation regions 106 corresponds to the n-type semiconductor region 28. The element isolation region 106 corresponds to the insulating portion 30. The buried oxide film 113 corresponds to the insulating layer 31. The silicon oxide film 110 corresponds to the insulating layer 32. The silicon oxide film 120 corresponds to the insulating film 35a. The first interlayer insulating film 140 corresponds to the insulating film 35b. The second interlayer insulating film 146 corresponds to the insulating film 35c. The passivation film 149 corresponds to the insulating film 35d. The p-type silicon epitaxial layer 101 between the element isolation regions 106 corresponds to the intermediate portion 40. The quench resistor 121 corresponds to the quench portion 50. The read pad 150a corresponds to the pad 61. The read pad 150b corresponds to the pad 62.

[0048] The advantages of the first embodiment will be described. FIG. 19 is a cross-sectional view showing a part of a photodetector according to a reference example. The photodetector 1r shown in FIG. 19 includes a p-type semiconductor layer 11, a p-type semiconductor layer 12, an element 20r, an insulating portion 30r, an insulating layer 35, and a quench portion 50. The element 20r and the insulating portion 30r are provided on the p-type semiconductor layer 12. The element 20r includes a p-type semiconductor region 21r, an n-type semiconductor region 22r, a p-type semiconductor region 23r, and an n-type guard ring region 26r. The p-type semiconductor region 21r is provided on the p-type semiconductor region 23r. The n-type semiconductor region 22r is provided on the p-type semiconductor region 21r. The n-type guard ring region 26r is provided around the n-type semiconductor region 22r in the XY plane, and suppresses electric field concentration at the curvature portions at the left and right ends of the n-type semiconductor region 22r. The insulating portion 30r surrounds each element 20r in the XY plane.

[0049] In the photodetector 1r, when a reverse voltage is applied between the p-type semiconductor region 21r and the n-type semiconductor region 22r, the depletion layer DL spreads toward the p-type semiconductor layer 12. The greater the thickness of the depletion layer DL, the more the sensitivity of the photodetector 1r can be improved. However, at the same time, an equivalent reverse voltage is also applied between the n-type guard ring region 26 and the p-type semiconductor layer 12, so the depletion layer DL0 spreads toward the p-type semiconductor layer 12. In the reference example, the impurity concentration of the p-type semiconductor layer 12 is lower than that of the p-type semiconductor region 21r, so the depletion layer DL0 is more likely to spread toward the lower side of the p-type semiconductor layer 12 than the depletion layer DL. In addition, since the electric field strength in the depletion layer DL0 is low, the depletion layer DL0 becomes a dead region where avalanche multiplication does not occur. This inhibits the extension of the depletion layer DL, which contributes to sensitivity, and deterioration of sensitivity becomes a problem, especially in the fine-pitch element 20. In addition, in order to increase the sensitivity to incident light of long wavelengths, it is necessary to thicken the p-type semiconductor layer 12. In this case, if a non-depleted region of the p-type semiconductor layer 12 exists under the depletion layer DL, the photoelectric conversion carriers generated there become delayed components. The delayed carriers cause an increase in jitter and afterpulse noise. For this reason, it is desirable to extend the depletion layer DL all the way to the p-type semiconductor layer 11 and completely deplete the p-type semiconductor layer 12. However, this requires a large reverse bias, which leads to an increase in the operating voltage and power consumption.

[0050] FIG. 20 is an enlarged cross-sectional view of a portion of FIG. In the photodetector 1, the pn junction involved in avalanche multiplication is formed between the p-type semiconductor region 21 and the n-type semiconductor region 22 that surround the p-type semiconductor region 23 in the XY plane. When a reverse voltage is applied between the p-type semiconductor region 21 and the n-type semiconductor region 22, a depletion layer DL1 spreads from the pn junction from both sides in the XY plane direction. As a result, in the miniaturized element 20 in particular, the p-type semiconductor layer 12 is more likely to be completely depleted than in the photodetector 1r, and an increase in jitter and after-pulse noise can be suppressed. In addition, when completely depleted, the extension of the depletion layer DL1 stops. The reverse voltage applied to the element 20 thereafter is consumed only to increase the electric field strength of the pn junction involved in avalanche multiplication. For this reason, it is possible to break down at a lower voltage, which contributes to reducing power consumption. Furthermore, the pn junction involved in avalanche multiplication extends in the Z direction. By deepening the depth of the insulating portion 30, the pn junction area can be increased without increasing the size of the element 20. Therefore, compared to the photodetector 1r, it is possible to compensate for the deterioration of sensitivity when the element 20 is miniaturized. Also, in the photodetector 1, the guard ring regions formed on both ends of the n-type semiconductor region 22 can be aligned vertically in the Z direction. This reduces the area occupied by the guard rings on the XY plane, and it is possible to avoid the deterioration of sensitivity when the element 20 is miniaturized.

[0051] When light is incident on the element 20, secondary photons may be generated near the pn junction. When the secondary photons are incident on the adjacent element 20, a carrier signal based on the secondary photons is detected. That is, crosstalk noise occurs. In the photodetector 1, a plurality of insulating parts 30 and intermediate parts 40 are provided between the adjacent elements 20. The refractive index of the insulating part 30 is lower than the refractive index of each semiconductor region included in the element 20. Therefore, a part of the secondary photons that are incident on the insulating part 30 are refracted downward or upward. A part of the secondary photons that are transmitted through the insulating part 30 and incident on the intermediate part 40 are absorbed during transmission through the intermediate part 40. A secondary photon that is transmitted through the intermediate part 40 and incident on another insulating part 30 is further refracted downward or upward. According to the photodetector 1, it is possible to suppress the incidence of secondary photons between the adjacent elements 20, and it is possible to reduce crosstalk noise.

[0052] In order to more effectively reduce crosstalk noise, the distance between adjacent elements 20 in the X direction or Y direction is preferably 3 μm or more. For example, the width of the intermediate portion 40 between adjacent elements 20 is 2 μm or more. This makes it easier for secondary photons to be absorbed in the intermediate portion 40.

[0053] More preferably, the photodetector 1 includes an n-type guard ring region 26 and a guard ring region 27. As shown in FIG. 20, when the n-type guard ring region 26 is provided, a depletion layer DL2 spreads from the pn junction between the n-type guard ring region 26 and the p-type semiconductor region 23. When the guard ring region 27 is provided, a depletion layer DL3 spreads from the pn junction between the guard ring region 27 and the p-type semiconductor layer 12. The electric field strength in each of the depletion layers DL2 and DL3 is lower than the electric field strength in the depletion layer DL1. For example, carriers flowing along the electric field of the depletion layers DL2 and DL3 do not cause avalanche multiplication and are negligible as a signal. On the upper surface of the element 20, dark carriers generated at the interface between the semiconductor layer and the insulating layer 35 flow to the n-type contact region 25 due to the electric field of the depletion layer DL2. Delayed carriers generated in the upper part of the p-type semiconductor layer 11 flow to the n-type contact region 25 due to the electric field of the depletion layer DL3. This makes it possible to suppress noise in the photodetector 1.

[0054] 21 and 22 are schematic plan views illustrating a portion of the photodetector according to the first embodiment. For example, the insulating part 30 is a polygon with an interior angle of 135 degrees or more when viewed from the Z direction. In the example shown in FIG. 21, the insulating part 30 is an octagon when viewed from the Z direction. One interior angle is about 135 degrees. Specifically, the insulating part 30 includes a pair of first extension parts 30a extending along the X direction, a pair of second extension parts 30b extending along the Y direction, and a plurality of connecting parts 30c. The element 20 is provided between the pair of first extension parts 30a in the Y direction. The element 20 is provided between the pair of second extension parts 30b in the X direction. Each connecting part 30c connects one end of the first extension part 30a to one end of the second extension part 30b.

[0055] The length of the first extension portion 30a in the X direction is longer than the length of the connecting portion 30c in the X direction. The length of the second extension portion 30b in the Y direction is longer than the length of the connecting portion 30c in the Y direction. For example, when viewed from the Z direction, the connecting portion 30c is linear. The angle θ1 between the first extension portion 30a and the connecting portion 30c is preferably 135 degrees or more. The angle θ2 between the second extension portion 30b and the connecting portion 30c is preferably 135 degrees or more.

[0056] It is preferable that the length L1 of the connecting portion 30c in the X direction and the length L2 of the connecting portion 30c in the Y direction are each 1 μm or more.

[0057] Alternatively, as shown in FIG. 22, the corners of the insulating part 30 may be curved when viewed from the Z direction. That is, the connecting part 30c may be curved when viewed from the Z direction. In the example shown in FIG. 22, the insulating part 30 has a rectangular shape with rounded corners when viewed from the Z direction. For example, one end of the connecting part 30c connected to the first extension part 30a is along the X direction. The other end of the connecting part 30c connected to the second extension part 30b is along the Y direction. This allows the connecting part 30c to be smoothly connected to the first extension part 30a and the second extension part 30b. Alternatively, the insulating part 30 may be annular when viewed from the Z direction.

[0058] FIG. 23 is a schematic plan view illustrating a part of a photodetector according to a reference example. In the photodetector 1r according to the reference example, as shown in Fig. 23, the insulating portion 30r is provided in a lattice pattern. Specifically, a part of the insulating portion 30r extends along the X direction. Another part of the insulating portion 30r extends along the Y direction. In the vicinity of the intersection portion CP between the part of the insulating portion 30r extending along the X direction and the part extending along the Y direction, the corner of the element 20 is approximately 90 degrees. Due to the protrusion of the corner of the element 20, a large stress is generated between the element 20 and the insulating portion 30r in the vicinity of the intersection portion CP compared to other portions.

[0059] For example, according to the structure shown in FIG. 21, the interior angle between the first extension portion 30a and the connecting portion 30c and the interior angle between the second extension portion 30b and the connecting portion 30c can be set to 135 degrees or more. Alternatively, when the insulating portion 30 is a polygon with rounded corners when viewed from the Z direction as shown in FIG. 22, the corners of the insulating portion 30 can be curved. According to these structures, the stress applied between the element 20 and the insulating portion 30 at the corners of the insulating portion 30 can be alleviated. For example, the occurrence of cracks in the element 20 and the insulating portion 30 can be suppressed by alleviating the stress. Operational malfunctions caused by the occurrence of cracks can be suppressed.

[0060] Furthermore, if cracks occur in the p-type silicon epitaxial layer 101, the silicon oxide film 110, or the buried oxide film 113 during the formation of the silicon oxide film 110 and the buried oxide film 113 corresponding to the insulating portion 30, the resist may get into the cracks in the subsequent photolithography process. If the resist gets into the cracks, resist residues will be generated in the cracks when the resist is peeled off. The resist residues will cause organic contamination of an oxidation furnace in the subsequent thermal process such as oxidation. By relieving the stress on the p-type silicon epitaxial layer 101, the silicon oxide film 110, and the buried oxide film 113, the occurrence of cracks can be suppressed, and the yield of the photodetector 1 can be improved.

[0061] In addition, in the structure of the insulating portion 30r shown in FIG. 23, the dimension Di2 of the intersection CP in the diagonal direction is about 1.4 times the dimension Di1 of the intersection CP in the X or Y direction. The diagonal direction is perpendicular to the Z direction and is inclined with respect to the X and Y directions. In other words, when manufacturing the structure shown in FIG. 23, in the process corresponding to FIG. 7, the dimension of the trench structure 108 in the diagonal direction is about 1.4 times the dimension Di1 in the X or Y direction in the portion where the intersection CP is formed. Due to this dimensional difference, when the buried oxide film 113 is formed in the trench structure 108, the trench structure 108 is not completely buried in the intersection CP, and a void occurs in the buried oxide film 113. The void causes the resist to enter the void and the resist to remain in the void, similar to a crack. According to the structure shown in FIG. 21 and FIG. 22, it is possible to avoid a local increase in the dimension of the trench structure 108, and to suppress the occurrence of a void.

[0062] 21 and 22, the length of each of the connecting portion 30c in the X direction and the Y direction is preferably 1 μm or more, which can effectively reduce stress generated in the vicinity of the connecting portion 30c.

[0063] Here, an example has been described in which the insulating part 30 includes a pair of first extending parts 30a, a pair of second extending parts 30b, and a plurality of connecting parts 30c. The insulating part 30 may include at least one first extending part 30a, one second extending part 30b, and one connecting part 30c that are connected to each other. This can reduce stress in the vicinity of the region where the one first extending part 30a, the one second extending part 30b, and the one connecting part 30c are provided.

[0064] (Modification) Fig. 24 is a schematic plan view showing a part of a photodetector according to a modified example of the first embodiment, and Fig. 25 is a cross-sectional view taken along line A1-A2 of Fig. 24. In the photodetector 1A according to the modification of the first embodiment, compared to the photodetector 1, the p-type contact region 24, the plug 45a, the wiring 45b, the first wiring 51, and the pad 61 are not provided. Instead, the photodetector 1A includes an electrode 60. The electrode 60 is provided under the p-type semiconductor layer 11 and is located on the lower surface of the photodetector 1A. The electrode 60 can be used as a p-type anode electrode. The p-type semiconductor region 21 and the p-type semiconductor region 23 are electrically connected to the electrode 60 via the p-type semiconductor layer 11 and the p-type semiconductor layer 12.

[0065] 24, in the photodetector 1A, the n-type semiconductor region 22 is electrically connected to the quench portion 50 via the n-type contact region 25, the plug 46a, the wiring 46b, and the plug 46c. The quench portion 50 is electrically connected to the second wiring 52.

[0066] Similar to the photodetector 1 shown in FIG. 1, the second wiring 52 is electrically connected to the pad 62. A potential is applied to the electrode 60 instead of the pad 61. In the photodetector 1A, a negative operating voltage is applied to the electrode 60 with respect to the pad 62. For example, the operating voltage is set to −60V to −70V. A signal when light is incident on the photodetector 1A is read out from the pad 62.

[0067] In the photodetector 1A, the p-type contact region 24, the plug 45a, and the wiring 45b are not present on the light incident surface side of the element 20. Therefore, compared to the photodetector 1, the aperture ratio is improved and the sensitivity is improved.

[0068] Second embodiment Fig. 26 is a schematic plan view showing a photodetector according to a second embodiment, Fig. 27 is an enlarged view of a portion A in Fig. 26, Fig. 28 is a cross-sectional view taken along line A1-A2 in Fig. 27. Compared with the photodetector 1, the photodetector 2 according to the second embodiment further includes a plug 48a (contact plug), an interconnect 48b, a plug 48c, a third interconnect 53, and a pad 63. The intermediate portion 40 includes a first intermediate region 41, a second intermediate region 42, and a third intermediate region 43.

[0069] 26, the pad 63 is provided on the upper surface of the photodetector 1. The pads 61 to 63 are spaced apart from each other and electrically isolated from each other.

[0070] 28, the second intermediate region 42 is provided on the first intermediate region 41. The third intermediate region 43 is provided on the second intermediate region 42. In the photodetector 2, the first intermediate region 41 is p-type. The second intermediate region 42 and the third intermediate region 43 are n-type. The n-type impurity concentration in the third intermediate region 43 is higher than the n-type impurity concentration in the second intermediate region 42.

[0071] 27, the second intermediate regions 42 are provided around each insulating portion 30 in the XY plane. The third intermediate regions 43 are provided on a part of the second intermediate regions 42. In the illustrated example, the third intermediate regions 43 are provided every other one between adjacent elements 20 in the tilt direction. The tilt direction is perpendicular to the Z direction and tilted with respect to the X direction and the Y direction.

[0072] As shown in FIG. 28, the plug 48a is provided on the third intermediate region 43. The wiring 48b is provided on the plug 48a. The plug 48c is provided on the wiring 48b. The plug 48c is electrically connected to the third wiring 53. The third wiring 53 is electrically connected to the pad 63. That is, the third intermediate region 43 is electrically connected to the pad 63 via the plug 48a, the wiring 48b, the plug 48c, and the third wiring 53. By applying a voltage to the pad 63, the potentials of the second intermediate region 42 and the third intermediate region 43 can be fixed.

[0073] 27, the third wiring 53 extends in the Y direction, and a plurality of third wirings 53 are provided in the X direction.

[0074] FIG. 29 is a schematic cross-sectional view showing a part of the photodetector according to the second embodiment. The advantages of the second embodiment will be described. When light incident on the element 20 is detected, the voltage of the element 20 varies. Here, between adjacent elements 20, there is a capacitive coupling C via the insulating portion 30 and the intermediate portion 40, as shown in Fig. 29. In the photodetector 1, when the voltage of one element 20 varies, the voltage of the adjacent element 20 varies via the capacitive coupling C.

[0075] For example, in an element 20 on which light is incident, carriers caused by avalanche breakdown flow to the quench portion 50, causing a potential drop. This causes the cathode potential to drop below the breakdown voltage. If this potential fluctuation propagates to an adjacent element 20 via the capacitive coupling C, the cathode potential of the adjacent element 20 drops. At this time, if light is incident on the adjacent element 20, this causes a malfunction in which the avalanche gain drops or the avalanche itself does not occur.

[0076] In the photodetector 2, the potentials of the second intermediate region 42 and the third intermediate region 43 are fixed. This makes it possible to suppress fluctuations in the voltage of an adjacent element 20 even if the voltage of one element 20 fluctuates. According to the second embodiment, the operation of the photodetector 2 can be further stabilized.

[0077] By setting the potential of the intermediate portion 40 to be approximately the same as the potential of the n-type contact region 25, even when the voltage of the element 20 fluctuates, an increase in the potential difference between the element 20 and the n-type semiconductor region 28 can be suppressed, and the occurrence of local avalanche breakdown can be suppressed.

[0078] Third embodiment Fig. 30 is a schematic plan view showing a part of a photodetector according to a third embodiment, and Fig. 31 is a cross-sectional view taken along line A1-A2 of Fig. 30. Compared to the photodetector 1, the photodetector 3 according to the third embodiment further includes an electrode 60. As shown in Fig. 31 , the electrode 60 is provided under the p-type semiconductor layer 11. The p-type semiconductor region 21 and the p-type semiconductor region 23 are electrically connected to the electrode 60 via the p-type semiconductor layer 11 and the p-type semiconductor layer 12.

[0079] 30 and 31, in the photodetector 3, the n-type semiconductor region 22 is electrically connected to the quench portion 50 via the n-type contact region 25, the plug 46a, the wiring 46b, and the plug 46c. The quench portion 50 is electrically connected to the second wiring 52. The p-type semiconductor region 21 is electrically connected to the first wiring 51 via the p-type semiconductor region 23, the p-type contact region 24, the plug 45a, and the wiring 45b.

[0080] Similar to the photodetector 1 shown in FIG. 1, the first wiring 51 is electrically connected to the pad 61. The second wiring 52 is electrically connected to the pad 62. In the photodetector 3, a negative operating voltage is applied to the electrode 60 and the pad 61 with respect to the pad 62. For example, the operating voltage is set to −60V to −70V. A signal when light is incident on the photodetector 3 is read out from the pad 62.

[0081] FIG. 32 is an enlarged cross-sectional view of a portion of FIG. 32, in the photodetector 3, the depletion layer DL1 spreads further toward the p-type semiconductor layer 11 compared to the photodetector 1. This is because an electric field is generated between the electrode 60 and the n-type semiconductor region 22, generating electric field lines EL toward the p-type semiconductor layer 11. According to the third embodiment, the area in which the depletion layer spreads is increased, and therefore the light receiving sensitivity of the photodetector 3 can be improved.

[0082] The operating voltage applied to the electrode 60 may be the same as the operating voltage applied to the pad 61, or may be different from the operating voltage applied to the pad 61. For example, the longer the wavelength of the incident light, the greater the proportion of the amount of light absorbed by the lower part of the p-type semiconductor region 23 or the p-type semiconductor layer 11. For this reason, it is preferable to lower the potential of the electrode 60 below the potential of the pad 61 and distribute the depletion layer closer to the p-type semiconductor layer 11 side.

[0083] (Fourth embodiment) Fig. 33 is a schematic plan view showing a part of a photodetector according to a fourth embodiment, and Fig. 34 is a cross-sectional view taken along line A1-A2 of Fig. 33. In the photodetector 4 shown in FIGS. 33 and 34, a part of the p-type semiconductor region 21, a part of the n-type semiconductor region 22, the lower end of the insulating portion 30, and the like are provided in the p-type semiconductor layer 11.

[0084] An n-type semiconductor region 22 is provided around the bottom of the insulating portion 30 in place of the guard ring region 27. That is, a part of the n-type semiconductor region 22 is located between the p-type semiconductor region 21 and the insulating portion 30 in the XY plane. Another part of the n-type semiconductor region 22 is located between the p-type semiconductor layer 11 and the insulating portion 30 in the Z direction.

[0085] The intermediate portion 40 is n The intermediate portion 40 is a semiconductor region having a p-type insulating portion 30. The intermediate portion 40 includes a second intermediate region 42 and a third intermediate region 43. The lower end of the second intermediate region 42 is located in the p-type semiconductor layer 11, and is located lower than the lower end of the insulating portion 30. The third intermediate region 43 is provided on the second intermediate region 42. The third intermediate region 43 is electrically connected to the second wiring 52 via a plug 45a.

[0086] Figures 35 to 50 are schematic diagrams showing a manufacturing process of a photodetector according to the fourth embodiment. Figures 35(b) to 49(b) are cross-sectional views taken along B1-B2 in Figures 35(a) to 49(a), respectively. Figures 35(a) to 49(a) are cross-sectional views taken along A1-A2 in Figures 35(b) to 49(b), respectively. An example of a preferable method for manufacturing the photodetector 1 according to the fourth embodiment will be described with reference to FIGS.

[0087] First, a wafer W was prepared as shown in Fig. 35(a) and Fig. 35(b). The wafer W includes a single crystal p-type silicon substrate 100 and a p-type silicon epitaxial layer 101 formed thereon. The p-type silicon substrate 100 has a concentration of 1.0 × 10 13 / cm 3 The p-type silicon epitaxial layer 101 is doped with boron at a concentration of 1.0×10 14 / cm 3The p-type silicon epitaxial layer 101 is formed by epitaxial growth and has a thickness of 8.5 μm. A layer doped with a high concentration of boron may be provided on the lower surface of the p-type silicon substrate 100 to suppress contamination.

[0088] As shown in FIG. 36(a) and FIG. 36(b), the surface of the p-type silicon epitaxial layer 101 is oxidized to form a silicon thermal oxide film 102 having a thickness of 100 nm. A silicon nitride film 103 is deposited to a thickness of 300 nm by low pressure thermal CVD. A silicon oxide film 104 is deposited to a thickness of 1000 nm by low pressure thermal CVD. Then, an opening OP (pattern) for defining an element isolation region 106 is formed in a resist 105 by a lithography process. The silicon oxide film 104, the silicon nitride film 103, and the silicon thermal oxide film 102 are etched through the opening OP of the resist 105 by RIE. For example, the width of the element isolation region 106 is set to 0.5 μm. The width of the inter-isolation region 107 is set to 2 μm. The width of the element isolation region 106 corresponds to the width of the opening OP. The sum of the width of the inter-isolation region 107 and twice the width of the element isolation region 106 is preferably 3 μm or more. This ensures that secondary photons in the visible region traveling laterally between adjacent cells are sufficiently absorbed by the silicon in the inter-isolation region 107 .

[0089] As shown in FIG. 37(a) and FIG. 37(b), the resist 105 is peeled off. The p-type silicon epitaxial layer 101 in the element isolation region 106 is etched using the thick silicon oxide film 104 as a mask. This forms a trench structure 108. The etching depth (depth of the trench structure 108) is determined by the thickness of the p-type silicon epitaxial layer 101 and the amount of boron diffused from the p-type silicon substrate 100 to the p-type silicon epitaxial layer 101 by the thermal process in the entire process. For example, the etching depth is set to 10 um. At this time, the trench structure 108 is formed so that the shape of the trench structure 108 is a quadrangle with rounded corners, a polygon with an inner angle of 135 degrees or more, or a ring shape when viewed from the Z direction, thereby suppressing the occurrence of cracks. As a result, it is possible to suppress malfunctions caused by the occurrence of cracks, and the yield of the photodetector 4 can be improved.

[0090] As shown in FIGS. 38(a) and 38(b), the surface of the trench structure 108 is oxidized to form a silicon oxide film 110 having a thickness of 50 nm. A p-type avalanche layer 123 is formed on the side and bottom surfaces of the trench structure 108 by ion implantation. Ions are implanted sequentially from four directions OR1 to OR4 tilted by 3 degrees with respect to the Z direction. The implantation angle in this ion implantation is appropriately set according to the width and depth of the trench structure 108 and the respective depths of the n-type avalanche layer 111 and the p-type avalanche layer 123 to be formed subsequently. For example, the p-type avalanche layer 123 is formed by implanting ions at an implantation acceleration voltage of 50 keV and an implantation dose of 1.25×10 per direction. 14 / cm 2 The trench structure 108 is formed by ion-implanting boron under the conditions described above. Then, in order to cause solid-phase diffusion and activation of the boron implanted in the silicon oxide film 110 into the silicon layer surrounding the trench structure 108, annealing is performed in a nitrogen atmosphere at 1100° C. for 100 minutes. The silicon oxide film 104 and the silicon oxide film 110 implanted with boron are removed by a hydrofluoric acid treatment.

[0091] As shown in FIG. 39(a) and FIG. 39(b), the surface of the trench structure 108 is oxidized to form a silicon oxide film 110a having a thickness of 50 nm. An n-type avalanche layer 111 is formed on the side and bottom surfaces of the trench structure 108 by ion implantation. Ions are implanted sequentially from four directions OR1 to OR4 tilted by 3 degrees with respect to the Z direction. The implantation angle in this ion implantation is appropriately set according to the width and depth of the trench structure 108 and the respective depths of the n-type avalanche layer 111 and the p-type avalanche layer 123 to be formed subsequently. For example, the n-type avalanche layer 111 is formed by implanting ions at an implantation acceleration voltage of 50 keV and an implantation dose of 5.0×10 per direction. 14 / cm 2The n-type avalanche layer 111 is formed by ion-implanting phosphorus under the conditions described above. In order to cause solid-phase diffusion and activation of the phosphorus implanted in the silicon oxide film 110a into the silicon layer surrounding the trench structure 108, annealing is performed in a nitrogen atmosphere at 1100° C. for 50 minutes. The dose of phosphorus for forming the n-type avalanche layer 111 is greater than the dose of boron for forming the p-type avalanche layer 123. As a result, a portion of the p-type impurity in the p-type avalanche layer 123 is offset by the n-type impurity.

[0092] As shown in Fig. 40(a) and Fig. 40(b), a buried oxide film 113 is deposited to a thickness of 1.2 µm by plasma CVD. The film is densified by nitrogen annealing at 1000°C. The buried oxide film 113 is planarized by CMP processing using the silicon nitride film 103 as a stopper.

[0093] 41(a) and 41(b), the silicon nitride film 103 is stripped by a hot phosphoric acid treatment, and the silicon thermal oxide film 102 is stripped by a hydrofluoric acid treatment, leaving an element isolation structure 114 including a silicon oxide film 110a and a buried oxide film 113.

[0094] As shown in FIG. 42(a) and FIG. 42(b), the surface of the p-type silicon epitaxial layer 101 is oxidized to form a silicon oxide film 120 having a thickness of 50 nm. The n-type cathode diffusion layer 115 is patterned and formed in the isolation region 107 by a lithography process and an ion implantation process. For example, the n-type cathode diffusion layer 115 is formed by two ion implantations. In the first ion implantation, the implantation acceleration voltage is 700 keV and the implantation dose is 3.0×10 12 / cm 2 In the second ion implantation, the implantation acceleration voltage is 3 MeV and the implantation dose is 4.0 × 10 12 / cm 2Phosphorus is implanted under the above conditions. Annealing is performed to activate the n-type cathode diffusion layer 115 and to diffuse the phosphorus in the substrate depth direction. For example, annealing is performed in a nitrogen atmosphere at 1100° C. for 50 minutes. The formation of the n-type cathode diffusion layer 115 offsets the p-type avalanche layer 123 formed in the isolation region 107.

[0095] As shown in Fig. 43(a) and Fig. 43(b), a polysilicon film is formed to a thickness of 0.2 um by low pressure thermal CVD. The polysilicon film is processed into a predetermined shape by lithography and RIE processes to form a quench resistor 121. For example, boron, 20 keV, 1.0 x 10 15 / cm 3 Impurities are implanted and activation annealing is performed.

[0096] As shown in FIG. 44(a) and FIG. 44(b), the p-type anode electrode 124 is patterned in the element region 122 by lithography and multiple ion implantation processes. For example, the p-type anode electrode 124 is formed by two ion implantations. In the first ion implantation, the implantation acceleration voltage is 50 keV and the implantation dose is 5.0×10 14 / cm 2 In the second ion implantation, the implantation acceleration voltage is 400 keV and the implantation dose is 3.0×10 12 / cm 2 Boron is implanted under the condition:

[0097] As shown in Figures 45(a) and 45(b), the n-type cathode electrode 131 is patterned in the n-type cathode diffusion layer 115 by lithography and ion implantation. For example, the n-type cathode electrode 131 is formed by implantation acceleration voltage of 20 keV and implantation dose of 1.0 x 10 15 / cm 2 After the ion implantation, activation annealing of the p-type anode electrode 124 and the n-type cathode electrode 131 is performed.

[0098] As shown in Fig. 46(a) and Fig. 46(b), a first interlayer insulating film 140 having a thickness of 0.5 um is formed by a CVD method. The first interlayer insulating film 140 is planarized by CMP. Contact holes 141 are formed on the quench resistor 121, the p-type anode electrode 124, and the n-type cathode electrode 131 by lithography and RIE processes. Note that the silicon oxide film 120 and the first interlayer insulating film 140 are omitted in the plan view shown in Fig. 46(b). The same applies to Fig. 47(b) shown next.

[0099] As shown in FIG. 47(a) and FIG. 47(b), a 10 nm thick titanium film 142 and a 10 nm thick titanium nitride film 143 are formed by sputtering. A 300 nm thick tungsten film 144 is formed by CVD. Using the first interlayer insulating film 140 as a stopper, the tungsten 144, titanium nitride 143, and titanium 142 are planarized by CMP. As a result, the contact hole 141 is filled.

[0100] As shown in FIG. 48(a) and FIG. 48(b), a metal film having a thickness of 0.5 um is formed by sputtering. This metal film is processed into a predetermined shape by lithography and RIE to form wirings 145a, 145b, and 145c, respectively. A silicon oxide film having a thickness of 0.8 um is formed as a second interlayer insulating film 146 by CVD. The second interlayer insulating film 146 is planarized by CMP. Note that the silicon oxide film 120, the first interlayer insulating film 140, and the second interlayer insulating film 146 are omitted in the plan view shown in FIG. 48(b). The same is true for FIG. 49(b) shown next.

[0101] As shown in FIG. 49(a), FIG. 49(b), and FIG. 50, a via hole 147 is formed on the wiring 145b. The via hole 147 is filled by depositing titanium, titanium nitride, and tungsten. A pad metal wiring 148 that serves as a read pad electrode is formed. A silicon nitride film having a thickness of 0.3 um is formed as a passivation film 149 by a CVD method. A part of the passivation film 149 is removed by an RIE method to open above the read pad 150a (shown in FIG. 50) and the read pad 150b. Through the above steps, the photodetector 4 according to the fourth embodiment is manufactured.

[0102] The operation of the photodetector 4 will be described. A positive operating voltage is applied to the pad 62 relative to the pad 61. The operating voltage is, for example, +60 V to +70 V. When light is incident on the photodetector 4, a pulse signal can be read out from the pad 61.

[0103] 51 and 52 are schematic cross-sectional views showing a part of the photodetector according to the fourth embodiment. 51, when light L is incident on the element 20, photoelectric conversion occurs in the element 20. When the photodetector 4 is in operation, a depletion layer DL1 extends from the pn junction between the p-type semiconductor region 21 and the n-type semiconductor region 22 toward the p-type semiconductor region 23. The depletion layer DL1 causes holes to drift toward the p-type contact region 24, and electrons to drift toward the pn junction.

[0104] Moreover, in the photodetector 4, the n-type semiconductor region 22 is provided around the insulating portion 30. Specifically, as shown in FIG. 51, the n-type semiconductor region 22 includes a first portion 22a, a second portion 22b, and a third portion 22c. The first portion 22a is located between the p-type semiconductor region 21 and the insulating portion 30 in the XY plane. The second portion 22b is located between the insulating portion 30 and the intermediate portion 40 in the XY plane. The third portion 22c is located below the insulating portion 30.

[0105] The first portion 22a faces the second portion 22b in the XY plane via the insulating portion 30. This allows the electric field direction at each point of the element 20 to be closer to parallel to the XY plane than in the photodetector 1. In other words, the depletion layer can be spread more parallel to the XY plane. As a result, the dead region that does not detect light can be made smaller, and the light receiving sensitivity of the photodetector 4 can be increased.

[0106] The first portion 22a preferably includes a first sub-region 22a1 and a second sub-region 22a2. The first sub-region 22a1 is provided on the second sub-region 22a2 and is located near the upper surface of the element 20. The n-type impurity concentration in the first sub-region 22a1 is lower than the n-type impurity concentration in the second sub-region 22a2. This relaxes the electric field near the upper surface of the element 20. In the vicinity of the upper surface of the element 20, carriers do not cause avalanche breakdown and flow through the n-type semiconductor region 22 as insensitive carriers. Many interface states exist on the upper surface of the element 20. Carriers emitted from these interface states become dark noise. By suppressing the avalanche breakdown near the upper surface of the element 20, dark noise can be reduced.

[0107] The concentration difference between the first sub-region 22a1 and the second sub-region 22a2 is formed by implanting ions obliquely into the wafer W in the process of forming the n-type avalanche layer 111 shown in Fig. 39. This is because the silicon nitride film 103 and the silicon thermal oxide film 102 act as masks during the ion implantation, suppressing phosphorus implantation into the upper surface portion of the n-type avalanche layer 111.

[0108] Furthermore, in the photodetector 4, the bottom end of the p-type semiconductor region 21 and the bottom end of the n-type semiconductor region 22 are located below the bottom end of the insulating portion 30. Therefore, the depletion layer can be expanded to a deeper region compared to the photodetector 1. This allows the photodetector 4 to have higher light sensitivity to light with a longer wavelength (for example, light in the near-infrared wavelength band with a wavelength of about 1 μm) compared to the photodetector 1.

[0109] In the photodetector 4, the pn junction between the p-type semiconductor region 21 and the n-type semiconductor region 22 is substantially parallel to the Z direction. The pn junction extends to below the insulating portion 30. The depletion layer can be expanded along the XY plane in a wider range in the Z direction. This can further increase the light receiving sensitivity of the photodetector 4.

[0110] Such a pn junction surface is realized in the above-mentioned manufacturing process by forming the n-type avalanche layer 111 and the p-type avalanche layer 123 by solid-phase diffusion from the insulating film on the sidewall of the trench structure 108. By using solid-phase diffusion, a semiconductor region having a more uniform impurity concentration distribution can be formed to a deeper position than by ion implantation.

[0111] 52, a thickness T2 in the Z direction of the third portion 22c is greater than a thickness T1 in the XY plane of the first portion 22a. The thickness T1 corresponds to the distance in the XY plane between the p-type semiconductor region 21 and the insulating portion 30. The thickness T2 corresponds to the distance in the Z direction between the p-type semiconductor layer 11 and the insulating portion 30.

[0112] When the thickness T2 is greater than the thickness T1, the electrical resistance in the third portion 22c can be reduced. This makes it possible to further stabilize the potential of the first portion 22a that is distant from the intermediate portion 40. Even when a current flows through the n-type semiconductor region 22, the fluctuation in the potential of the first portion 22a can be reduced. This makes it possible to further stabilize the operation of the photodetector 4.

[0113] The width W of at least a part of the third portion 22c is greater than the distance D in the XY plane between the p-type semiconductor region 21 and the intermediate portion 40. When the width W is greater than the distance D, the electrical resistance in the third portion 22c can be reduced. As a result, the operation of the photodetector 4 can be made more stable.

[0114] The p-type impurity concentration in the third portion 22c may be higher than the p-type impurity concentration in the first portion 22a and higher than the p-type impurity concentration in the second portion 22b, thereby reducing the electrical resistance in the third portion 22c and making the operation of the photodetector 4 more stable.

[0115] In the photodetector 4, the p-type impurity concentration in the p-type semiconductor layer 11 is lower than the p-type impurity concentration in the p-type semiconductor region 21, and is lower than the p-type impurity concentration in the p-type semiconductor region 23. Therefore, it is possible to suppress the occurrence of avalanche breakdown between the p-type semiconductor layer 11 and the n-type semiconductor region 22 below the insulating portion 30, on the outer periphery of the insulating portion 30, and the like.

[0116] In particular, when the n-type impurity concentration in the third portion 22c is higher than the n-type impurity concentrations in the first portion 22a and the second portion 22b, the electric field strength between the p-type semiconductor layer 11 and the third portion 22c increases. Even in this case, the occurrence of avalanche breakdown between the p-type semiconductor layer 11 and the n-type semiconductor region 22 can be suppressed by reducing the p-type impurity concentration in the p-type semiconductor layer 11.

[0117] When an avalanche breakdown occurs between the p-type semiconductor layer 11 and the n-type semiconductor region 22, secondary photons generated at that time travel toward the adjacent element 20 without passing through the insulating portion 30. This causes crosstalk noise. For this reason, it is preferable to suppress the occurrence of an avalanche breakdown between the p-type semiconductor layer 11 and the n-type semiconductor region 22.

[0118] Fifth embodiment Fig. 53 is a schematic plan view showing a part of a photodetector according to the fifth embodiment, and Fig. 54 is a cross-sectional view taken along line A1-A2 of Fig. 53. The photodetector 5 according to the fifth embodiment is different from the photodetector 1 in terms of the structure of the element 20. Instead of the p-type contact region 24, the element 20 includes an n-type semiconductor region 29a, a p-type semiconductor region 29b, an n-type semiconductor region 29c, and an n-type semiconductor region 29d.

[0119] The p-type semiconductor region 29b is provided around the n-type semiconductor region 29a in the XY plane. The n-type semiconductor region 29c is provided on the n-type semiconductor region 29a. The n-type impurity concentration in the n-type semiconductor region 29c is higher than the n-type impurity concentration in the n-type semiconductor region 29a. The n-type semiconductor region 29d is provided around the n-type semiconductor region 29c in the XY plane. The n-type impurity concentration in the n-type semiconductor region 29d is lower than the n-type impurity concentration in the n-type semiconductor region 29c. For example, the n-type semiconductor region 29c contacts the n-type semiconductor region 29a and the n-type semiconductor region 29d. The p-type semiconductor region 29b and the n-type semiconductor region 29d are away from the p-type semiconductor region 21 and the n-type guard ring region 26.

[0120] The n-type semiconductor region 29c is electrically connected to the wiring 46b via a plug 46a. The n-type contact region 25 is electrically connected to the wiring 46b via a plug 46d. The wiring 46b is electrically connected to the first wiring 51 via a quench portion 50. In other words, both the n-type semiconductor region 22 and the n-type semiconductor region 29a are electrically connected to the first wiring 51 and are set to substantially the same potential.

[0121] The photodetector 5 further includes an electrode 60 provided under the p-type semiconductor layer 11. The p-type semiconductor region 21 and the p-type semiconductor region 29b are electrically connected to the electrode 60 via the p-type semiconductor region 23, the p-type semiconductor layer 12, and the p-type semiconductor layer 11.

[0122] Figures 55 to 57 are schematic diagrams showing a manufacturing process of a photodetector according to the fifth embodiment. Figures 55(b) to 57(b) are cross-sectional views taken along B1-B2 in Figures 55(a) to 57(a), respectively. Figures 55(a) to 57(a) are cross-sectional views taken along A1-A2 in Figures 55(b) to 57(b), respectively. An example of a preferable method for manufacturing the photodetector 5 according to the fifth embodiment will be described with reference to FIGS.

[0123] First, the same steps as those shown in FIG. 4(a) to FIG. 10(b) are performed to form the trench structure 108, the n-type avalanche layer 111, the buried oxide film 113, and the like.

[0124] 55(a) and 55(b), the p-type avalanche layer 123 and the p-type avalanche layer 123a are patterned in the element region 122 by lithography and ion implantation. For example, the p-type avalanche layers 123 and 123a are formed by implantation accelerating voltage of 1 MeV and implantation dose of 3.0×10 12 / cm 2 The n-type avalanche layer 111a is formed by ion implantation under the condition of the following: The n-type avalanche layer 111a is patterned in the element region 122 by a lithography process and an ion implantation process. For example, the n-type avalanche layer 111a is formed by two ion implantations. In the first ion implantation, the implantation acceleration voltage is 700 keV and the implantation dose is 3.0×10 12 / cm 2 In the second ion implantation, the implantation acceleration voltage is 3 MeV and the implantation dose is 1.0 × 10 12 / cm 2 Phosphorus is injected under the condition:

[0125] As shown in Figures 56(a) and 56(b), an n-type guard ring layer 130, an n-type guard ring layer 130a, an n-type cathode electrode 131, and an n-type cathode electrode 131a are formed. The n-type guard ring layer 130a and the n-type cathode electrode 131a can be formed simultaneously by changing the opening pattern of a mask in the process for forming the n-type guard ring layer 130 and the n-type cathode electrode 131 shown in Figures 13(a) and 13(b).

[0126] 57(a) and 57(b), steps similar to those shown in FIGS. 14(a) to 18 are performed to form wiring 145a, 145b, a read pad (not shown), etc. A back electrode 151 is formed under the p-type silicon substrate 100. Through the steps described above, the photodetector 4 according to the fifth embodiment is manufactured.

[0127] FIG. 58 is a schematic cross-sectional view showing a part of the photodetector according to the fifth embodiment. The operation of the photodetector 5 will be described. A reverse voltage is applied between the p-type semiconductor region 21 and the n-type semiconductor region 22, and between the n-type semiconductor region 29a and the p-type semiconductor region 29b. That is, a negative operating voltage with respect to the pad 61 is applied to the electrode 60. The operating voltage is, for example, −60V to −70V. A signal generated when light is incident on the photodetector 5 is read out from the pad 61.

[0128] According to the fifth embodiment, the depletion layer spreads not only from the pn junction between the p-type semiconductor region 21 and the n-type semiconductor region 22, but also from the pn junction between the n-type semiconductor region 29a and the p-type semiconductor region 29b. For example, the region where avalanche breakdown occurs spreads compared to the photodetector 1. This makes it possible to improve the sensitivity of the photodetector 5 compared to the photodetector 1.

[0129] FIG. 59 is a schematic diagram illustrating an active quench circuit. In the photodetectors according to the embodiments described above, a resistor that generates a large voltage drop is provided as the quench unit 50. In the photodetectors according to the embodiments, a control circuit and a switching element may be provided instead of the resistor. That is, an active quench circuit for cutting off current is provided as the quench unit 50.

[0130] As shown in Fig. 59, the active quench circuit includes a control circuit CC and a switching array SWA. The control circuit CC includes a comparator, a control logic unit, etc. The switching array SWA includes a plurality of switching elements SW. For example, at least a part of the circuit elements included in the control circuit CC and the switching elements SW may be provided on the p-type semiconductor layer 11, or may be provided on a circuit board separate from the p-type semiconductor layer 11.

[0131] 59, one switching element SW may be provided for one element 20, or one switching element SW may be provided for multiple elements 20. For example, one switching element SW is provided between one p-type semiconductor region 21 and the first wiring 51. Alternatively, the switching element SW may be provided in the first wiring 51. When the quench section 50 is electrically connected to the n-type semiconductor region 22, one switching element SW may be provided between one n-type semiconductor region 22 and the second wiring 52. The switching element SW may be provided in the second wiring 52.

[0132] FIG. 60 is a schematic diagram illustrating a LIDAR (Laser Imaging Detection and Ranging) device according to an embodiment. This embodiment is configured with a line light source and a lens and can be applied to a long-distance object detection system (LIDAR), etc. The LIDAR device 5001 includes a light projection unit T that projects laser light onto an object 411, and a light receiving unit R (also called a light detection system) that receives the laser light from the object 411, measures the time it takes for the laser light to travel to and from the object 411, and converts it into distance.

[0133] In the light projection unit T, the light source 404 emits light. For example, the light source 404 includes a laser oscillator and emits a laser beam. The driving circuit 403 drives the laser oscillator. The optical system 405 extracts a part of the laser beam as a reference beam, and irradiates the remaining laser beam onto an object 411 via a mirror 406. The mirror controller 402 controls the mirror 406 to project the laser beam onto the object 411. Here, projecting the beam means shining light.

[0134] In the light receiving unit R, the reference light photodetector 409 detects the reference light extracted by the optical system 405. The photodetector 410 receives the reflected light from the object 411. The distance measurement circuit 408 measures the distance to the object 411 based on the reference light detected by the reference light photodetector 409 and the reflected light detected by the photodetector 410. The image recognition system 407 recognizes the object 411 based on the result measured by the distance measurement circuit 408.

[0135] The LIDAR device 5001 employs an optical time-of-flight distance measurement method that measures the time it takes for laser light to travel to and from the target 411 and converts the time into distance. The LIDAR device 5001 is applied to in-vehicle drive-assist systems, remote sensing, and the like. When the photodetector of the above-described embodiment is used as the photodetector 410, it exhibits good sensitivity, particularly in the near-infrared region. For this reason, the LIDAR device 5001 can be applied to a light source in a wavelength band invisible to humans. The LIDAR device 5001 can be used, for example, for obstacle detection for a moving object.

[0136] FIG. 61 is a diagram for explaining detection of a detection target by a LIDAR device. A light source 3000 emits light 412 to an object 600 to be detected. A photodetector 3001 detects light 413 that is transmitted through, reflected from, or diffused by the object 600.

[0137] For example, when the photodetector 3001 is the photodetector according to the present embodiment described above, high-sensitivity detection can be achieved. It is preferable to provide a plurality of sets of photodetectors 410 and light sources 404, and set their arrangement relationship in advance in software (also possible with a circuit). It is preferable that the sets of photodetectors 410 and light sources 404 are arranged at equal intervals, for example. This allows the output signals of the respective photodetectors 410 to complement each other, thereby generating an accurate three-dimensional image.

[0138] FIG. 62 is a schematic top view of a moving body equipped with a lidar device according to an embodiment. In the example of Fig. 62, the moving body is a car. Vehicle 700 according to this embodiment is equipped with LIDAR devices 5001 at the four corners of a vehicle body 710. By providing LIDAR devices at the four corners of the vehicle body, the vehicle according to this embodiment can detect the environment in all directions of the vehicle by the LIDAR devices.

[0139] The moving object may be a drone, a robot, etc., other than the car shown in FIG. 62. The robot may be, for example, an automated guided vehicle (AGV). By providing LIDAR devices at the four corners of these moving objects, the environment in all directions of the moving object can be detected by the LIDAR devices.

[0140] According to each of the embodiments described above, the noise of the photodetector can be improved.

[0141] The specific examples of each embodiment described above relate to a front-illuminated photodetector in which light is incident on the element 20 through the insulating layer 35. Each embodiment is also applicable to a back-illuminated photodetector in which light is incident on the element 20 through the p-type semiconductor layer 11. In this case, the p-type semiconductor layer 11 is formed thinner.

[0142] In this specification, "vertical" and "parallel" do not only mean strictly vertical and strictly parallel, but also include, for example, variations in the manufacturing process, and may mean substantially vertical and substantially parallel.

[0143] The above describes the embodiments of the present invention with reference to specific examples. However, the embodiments of the present invention are not limited to these specific examples. For example, the specific configurations of each element, such as each semiconductor layer, each semiconductor region, insulating part, insulating layer, plug, wiring, quench part, electrode, pad, etc., included in the photodetector are included in the scope of the present invention as long as a person skilled in the art can implement the present invention in the same way and obtain the same effect by appropriately selecting them from the known range.

[0144] Furthermore, any combination of two or more elements of each of the specific examples, within the scope of technical feasibility, is also included within the scope of the present invention as long as it includes the gist of the present invention.

[0145] In addition, all optical detectors, optical detection systems, LIDAR devices, and moving bodies that can be implemented by a person skilled in the art by making appropriate design modifications based on the optical detectors, optical detection systems, LIDAR devices, and moving bodies described above as embodiments of the present invention also fall within the scope of the present invention as long as they include the gist of the present invention.

[0146] In addition, within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications and alterations, and it will be understood that these modifications and alterations also fall within the scope of the present invention.

[0147] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0148] 1, 1r, 2, 3: photodetector, 11: p-type semiconductor layer, 12: p-type semiconductor layer, 20, 20r: element, 21, 21r: p-type semiconductor region, 22, 22r: n-type semiconductor region, 23, 23r: p-type semiconductor region, 24: p-type contact region, 25: n-type contact region, 26, 26r: n-type guard ring region, 27: guard ring region, 28: n-type semiconductor region, 30: insulating portion, 30a: first extension portion, 30b: second extension portion, 30c: connecting portion, 30r: insulating portion, 31, 32: insulating layer, 35: insulating layer, 35a to 35d: insulating film, 40: intermediate portion, 41: first intermediate region, 42: second intermediate region, 43: third intermediate region, 45a: plug, 45b: wiring, 46a: plug, 46b: wiring, 46c, 47, 48a: plug, 48b: wiring, 48c: plug, 50: quench portion, 51: first wiring, 52: second wiring, 53: third wiring, 60: electrode, 61-63: pad, 100: p-type silicon substrate, 101: p-type silicon epitaxial layer, 102: silicon thermal oxide film, 103: silicon nitride film, 104: silicon oxide film, 105: resist, 106: element isolation region, 107: isolation region, 108: trench structure, 110: silicon oxide film, 111: n-type avalanche layer, 112: n-type guard ring layer, 113: buried oxide film, 120: silicon oxide film, 121: quench resistor, 122: element region, 123: p-type avalanche layer, 124: p-type anode electrode, 130: n-type guard ring layer, 131: cathode electrode, 140: first interlayer insulating film, 141: contact hole, 142: titanium, 143: titanium nitride, 144: tungsten, 145a to 145c: wiring, 146: second interlayer insulating film, 147: via hole, 148: pad metal wiring, 149: passivation film, 150a, 150b: readout pad, 402: mirror controller, 403: drive circuit, 404: light source, 405: optical system, 406: mirror, 407: image recognition system, 408: distance measurement circuit, 409: reference light photodetector, 410: photodetector, 411: object, 412,413: light, 600: object, 700: vehicle, 710: vehicle body, 3000: light source, 3001: photodetector, 5001: lidar device, CC: capacitive coupling, CP: intersection, DL, DL0 to DL3: depletion layer, Di1, Di2: dimension, L: electric field line, OP: aperture, OR1 to OR4: direction, R: light receiving unit, T: light projecting unit, W: wafer, θ1, θ2: angle,

Claims

1. A plurality of elements arranged along a first direction and a second direction intersecting each other, each of the plurality of elements being: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type provided around the first semiconductor region in a first surface along the first direction and the second direction; the plurality of elements including a plurality of insulating portions provided around the plurality of elements on the first surface; an intermediate portion including a semiconductor and provided around each of the insulating portions on the first surface; Equipped with the plurality of elements are photodiodes, the first conductivity type is p-type, the second conductivity type is n-type, Each of the plurality of elements further includes a third semiconductor region of the first conductivity type surrounded by the first semiconductor region on the first surface, a concentration of the first conductive type impurity in the third semiconductor region is lower than a concentration of the first conductive type impurity in the first semiconductor region; Each of the plurality of elements further includes a p-type contact region provided on the third semiconductor region and having a function of an anode electrode; a concentration of the impurity of the first conductivity type in the p-type contact region is higher than a concentration of the impurity of the first conductivity type in the third semiconductor region; Each of the plurality of elements further includes an n-type contact region provided on the second semiconductor region and having a function of a cathode electrode; a concentration of the impurity of the second conductivity type in the n-type contact region is higher than a concentration of the impurity of the second conductivity type in the second semiconductor region; In operation, a reverse voltage is applied between the first semiconductor region and the second semiconductor region; The insulating portion surrounds the second semiconductor region on the first surface.

2. A plurality of elements arranged along a first direction and a second direction intersecting each other, each of the plurality of elements being: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type provided around the first semiconductor region in a first surface along the first direction and the second direction; the plurality of elements including a plurality of insulating portions provided around the plurality of elements on the first surface; an intermediate portion including a semiconductor and provided around each of the insulating portions on the first surface; a first semiconductor layer of the first conductivity type; An electrode provided under the first semiconductor layer; Equipped with the plurality of elements are provided on the first semiconductor layer, the first semiconductor region is electrically connected to the electrode via the first semiconductor layer; the plurality of elements are photodiodes, the first conductivity type is p-type, the second conductivity type is n-type, The electrode functions as an anode electrode, Each of the plurality of elements further includes a third semiconductor region of the first conductivity type surrounded by the first semiconductor region on the first surface, a concentration of the first conductive type impurity in the third semiconductor region is lower than a concentration of the first conductive type impurity in the first semiconductor region; Each of the plurality of elements further includes an n-type contact region provided on the second semiconductor region and having a function of a cathode electrode; a concentration of the impurity of the second conductivity type in the n-type contact region is higher than a concentration of the impurity of the second conductivity type in the second semiconductor region; In operation, a reverse voltage is applied between the first semiconductor region and the second semiconductor region; The insulating portion surrounds the second semiconductor region on the first surface.

3. A plurality of elements arranged along a first direction and a second direction intersecting each other, each of the plurality of elements being: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type provided around the first semiconductor region in a first surface along the first direction and the second direction; the plurality of elements including a plurality of insulating portions provided around the plurality of elements on the first surface; an intermediate portion including a semiconductor and provided around each of the insulating portions on the first surface; a first semiconductor layer of the first conductivity type; An electrode provided under the first semiconductor layer; Equipped with The electrode functions as an anode electrode, the plurality of elements are provided on the first semiconductor layer, the first semiconductor region is electrically connected to the electrode via the first semiconductor layer; the plurality of elements are photodiodes, the first conductivity type is p-type, the second conductivity type is n-type, Each of the plurality of elements further includes a third semiconductor region of the first conductivity type surrounded by the first semiconductor region on the first surface, a concentration of the first conductive type impurity in the third semiconductor region is lower than a concentration of the first conductive type impurity in the first semiconductor region; Each of the plurality of elements further includes a p-type contact region provided on the third semiconductor region and having a function of an anode electrode; a concentration of the impurity of the first conductivity type in the p-type contact region is higher than a concentration of the impurity of the first conductivity type in the third semiconductor region; Each of the plurality of elements further includes an n-type contact region provided on the second semiconductor region and having a function of a cathode electrode; a concentration of the impurity of the second conductivity type in the n-type contact region is higher than a concentration of the impurity of the second conductivity type in the second semiconductor region; In operation, a reverse voltage is applied between the first semiconductor region and the second semiconductor region; The insulating portion surrounds the second semiconductor region on the first surface.

4. A plurality of elements arranged along a first direction and a second direction intersecting each other, each of the plurality of elements being: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type provided around the first semiconductor region in a first surface along the first direction and the second direction; the plurality of elements including a plurality of insulating portions provided around the plurality of elements on the first surface; an intermediate portion including a semiconductor and provided around each of the insulating portions on the first surface; Equipped with the plurality of elements are photodiodes, the first conductivity type is p-type, the second conductivity type is n-type, Each of the plurality of elements further includes a third semiconductor region of the first conductivity type surrounded by the first semiconductor region on the first surface, a concentration of the first conductive type impurity in the third semiconductor region is lower than a concentration of the first conductive type impurity in the first semiconductor region; Each of the plurality of elements further includes a p-type contact region having a function of an anode electrode provided on the third semiconductor region; a concentration of the impurity of the first conductivity type in the p-type contact region is higher than a concentration of the impurity of the first conductivity type in the third semiconductor region; the intermediate portion includes a second intermediate region and a third intermediate region, a lower end of the second intermediate region is located lower than a lower end of the insulating portion and functions as an n-type source diffusion layer; the third intermediate region is provided on the second intermediate region and has a function of a cathode electrode; a concentration of the impurity of the second conductivity type in the third intermediate region is higher than a concentration of the impurity of the second conductivity type in the second semiconductor region; In operation, a reverse voltage is applied between the first semiconductor region and the second semiconductor region; The insulating portion is located around the first semiconductor region on the first surface, A photodetector having a portion of the second semiconductor region beneath the insulating portion.

5. A plurality of elements arranged along a first direction and a second direction intersecting each other, each of the plurality of elements being: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type provided around the first semiconductor region in a first surface along the first direction and the second direction; the plurality of elements including a plurality of insulating portions provided around the plurality of elements on the first surface; an intermediate portion including a semiconductor and provided around each of the insulating portions on the first surface; a first semiconductor layer of the first conductivity type; An electrode provided under the first semiconductor layer; Equipped with the plurality of elements are provided on the first semiconductor layer, the first semiconductor region is electrically connected to the electrode via the first semiconductor layer; the plurality of elements are photodiodes, the first conductivity type is p-type, the second conductivity type is n-type, The electrode functions as an anode electrode, Each of the plurality of elements further includes a third semiconductor region of the first conductivity type surrounded by the first semiconductor region on the first surface, a concentration of the first conductive type impurity in the third semiconductor region is lower than a concentration of the first conductive type impurity in the first semiconductor region; Each of the plurality of elements further includes a p-type semiconductor region, an n-type semiconductor region, a first n-type contact region having a function of a cathode electrode, and a second n-type contact region having a function of a cathode electrode; In the first surface, the first semiconductor region is between the second semiconductor region and the n-type semiconductor region, In the first surface, the third semiconductor region is between the first semiconductor region and the n-type semiconductor region, In the first surface, the p-type semiconductor region is between the third semiconductor region and the n-type semiconductor region, the first n-type contact region is provided on the n-type semiconductor region; the second n-type contact region is provided on the second semiconductor region; the impurity concentration of the first conductivity type in the third semiconductor region is lower than the impurity concentration of the first conductivity type in the p-type semiconductor region; an impurity concentration of the second conductivity type in the first n-type contact region is higher than an impurity concentration of the second conductivity type in the n-type semiconductor region; an impurity concentration of the second conductivity type in the second n-type contact region is higher than an impurity concentration of the second conductivity type in the second semiconductor region; During operation, a reverse voltage is applied between the first semiconductor region and the second semiconductor region and between the p-type semiconductor region and the n-type semiconductor region, The insulating portion surrounds the second semiconductor region on the first surface.

6. The photodetector of any one of claims 1 to 5, wherein one or more of the plurality of insulating parts has a rectangular shape with rounded corners, a polygonal shape with an interior angle of 135 degrees or more, or a ring shape when viewed from a third direction perpendicular to the first direction and the second direction.

7. 6. The photodetector according to claim 1, wherein the distance between adjacent elements in the first direction is 3 μm or more.

8. The photodetector of any one of claims 1 to 7, further comprising a resistor electrically connected to one of the plurality of first semiconductor regions or one of the plurality of second semiconductor regions, or a switching element electrically connected to one or more of the plurality of first semiconductor regions or one or more of the plurality of second semiconductor regions.

9. The photodetector of any one of claims 1 to 7, wherein one or more of the plurality of elements comprises an avalanche photodiode.

10. 10. The photodetector of claim 9, wherein the avalanche photodiode operates in Geiger mode.

11. The photodetector of claim 10 , further comprising a quench portion electrically connected to one or more of the first semiconductor regions or one or more of the second semiconductor regions.

12. a first electrode electrically connected to the first semiconductor regions; A second electrode electrically connected to the second semiconductor regions; The photodetector of claim 11 further comprising:

13. a first wiring electrically connected to two or more of the plurality of first semiconductor regions; a second wiring electrically connected to two or more of the plurality of second semiconductor regions; Further equipped with the first semiconductor regions are electrically connected to the first electrode via one or more of the first wirings; The photodetector according to claim 12 , wherein the plurality of second semiconductor regions are electrically connected to the second electrode via one or more of the second wirings.

14. A photodetector according to any one of claims 1 to 13, a distance measurement circuit for calculating a time of flight of light from an output signal of the photodetector; A light detection system comprising:

15. A light source that irradiates light onto an object; 15. The light detection system of claim 14, further comprising: A lidar device comprising:

16. The LIDAR device of claim 15 , further comprising an image recognition system that generates a three-dimensional image based on a positional relationship between the light source and the light detector.

17. A moving object comprising the LIDAR device according to claim 15 or 16.

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