Light-emitting display device

Abstract

To provide an upper light-emitting type display device or an upper light-emitting type transparent display device capable of embodying and realizing high density and high luminance.SOLUTION: A light-emitting display device includes: a board; low-potential wiring; a pad section; a first area; a second area; multiple auxiliary wiring; and a common electrode. The board includes a display area, and a non-display area surrounding the display area. The low-potential wiring includes: first low-potential wiring disposed in an upper side of the board; and second low-potential wiring disposed in a lower side of the board. The pad section is disposed outside the second low-potential wiring. The first area is defined in a right side of the board. The second area is defined in a left side of the board. The multiple auxiliary wiring connects the first low-potential wiring and the second low-potential wiring in the second area. The common electrode extends from the display area and is brought into face contact with the low-potential wiring.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present specification relates to a light emitting display device having a structure for preventing damage caused by current concentration. [Background technology]

[0002] Among display devices, an emissive display device, which is a self-emitting display device, can provide excellent display quality with a high aperture ratio and high brightness relative to power consumption. In particular, in the case of a top emission display device, the common electrode is formed of a transparent conductive material. In a large-area top emission display device, it is desirable to reduce the sheet resistance of the common electrode to prevent brightness differences across the entire area.

[0003] In order to reduce the resistance of the common electrode, a structure is required in which the auxiliary wiring is formed of a metal material with low electrical resistance and the auxiliary wiring and the common electrode are electrically connected. In this case, if a portion where current concentrates occurs at the connection portion between the auxiliary wiring and the common electrode, the display device may be damaged by overheating. Therefore, it is desirable to develop a display device having a structure that prevents the phenomenon of current concentrating at a specific point and distributes current density evenly under any circumstances. Summary of the Invention [Problem to be solved by the invention]

[0004] Some embodiments of the present specification are intended to overcome the problems of the prior art and to provide a top-emitting display device or a top-emitting transparent display device that can achieve high density and high brightness.

[0005] Some embodiments of the present specification aim to provide a top-emitting display device or a top-emitting transparent light-emitting display device having a structure including auxiliary wiring for reducing the surface resistance of a common electrode constituting a light-emitting diode, and a structure in which current density is uniformly distributed at multiple contact points where the common electrode and low-potential wiring come into contact.

[0006] Some embodiments of the present specification aim to provide a top-emitting light-emitting display device or a top-emitting transparent light-emitting display device having a structure that can evenly distribute current density at a contact portion connecting a common voltage supply wiring and a common electrode.

[0007] Some embodiments of the present specification aim to provide a top-emitting light-emitting display device or a top-emitting transparent light-emitting display device that can prevent power waste due to uneven current density by evenly distributing the current density of a common electrode applied across the entire area of ​​the display panel across the entire area of ​​the display panel. [Means for solving the problem]

[0008] In order to achieve the above object, a light emitting display device according to an embodiment of the present specification includes a substrate, a low potential wiring, a pad section, a first region, a second region, a plurality of auxiliary wirings, and a common electrode. The substrate has a display region and a non-display region surrounding the display region. The low potential wiring includes a first low potential wiring arranged on an upper side of the substrate and a second low potential wiring arranged on a lower side of the substrate. The pad section is arranged outside the second low potential wiring. The first region is defined on the right side of the substrate. The second region is defined on the left side of the substrate. The plurality of auxiliary wirings connect the first low potential wiring and the second low potential wiring in the second region. The common electrode extends from the display region and is in surface contact with the low potential wiring.

[0009] As an example, multiple auxiliary wirings are not arranged in one region.

[0010] As an example, the semiconductor device further includes a first low potential terminal, a second low potential terminal, and a third low potential terminal. The first low potential terminal is disposed in correspondence with a first region of the pad portion and is connected to the second low potential wiring. The second low potential terminal and the third low potential terminal are disposed in correspondence with a second region of the pad portion and are connected to the second low potential wiring.

[0011] As an example, the second low potential terminal is located on a first side of the second region. The third low potential terminal is located on a second side of the second region opposite the first side of the second region.

[0012] As an example, the first low potential terminal is disposed on a first side of the first region. The semiconductor device further includes a gate signal terminal for supplying a gate signal disposed on a second side of the first region opposite to the one side of the first region.

[0013] As an example, the second region further includes a plurality of dummy auxiliary wirings that are connected to the first low potential wiring and are not connected to the second low potential wiring.

[0014] As an example, the auxiliary wiring and the dummy auxiliary wiring are arranged at the same intervals.

[0015] For example, the auxiliary wirings are arranged to further connect the first low potential wiring and the second low potential wiring in the second region. The second region further includes an electronic functional layer interposed between the low potential wiring and the cathode electrode.

[0016] As an example, the display device further includes a light-emitting diode disposed in the display region. The light-emitting diode includes an anode electrode, a light-emitting layer stacked on the anode electrode, an electronic functional layer stacked on the light-emitting layer, and a cathode electrode stacked on the electronic functional layer. In the first region, the electronic functional layer is limited to the display region. In the second region, the electronic functional layer extends from the display region and is interposed between the low-potential wiring and the cathode electrode.

[0017] As an example, the semiconductor device further includes a third low potential wiring on the substrate outside the first low potential wiring, an auxiliary wiring is connected to the first low potential wiring in the first region, and an auxiliary wiring is connected to the third low potential wiring in the second region.

[0018] As an example, the non-display region further includes an insulating film covering the first low potential wiring and the third low potential wiring. The insulating film includes a first contact hole and a second contact hole. The first contact hole is disposed in the first region excluding the second region and exposes a part of the first low potential wiring. The second contact hole is disposed in the second region excluding the first region and exposes a part of the third low potential wiring.

[0019] As an example, the cathode electrode is connected to the first low potential wiring through the first contact hole, and the cathode electrode is connected to the third low potential wiring through the second contact hole.

[0020] As an example, the display device further includes a light emitting diode disposed in the display region. The light emitting diode includes an anode electrode, a light emitting layer stacked on the anode electrode, an electronic functional layer stacked on the light emitting layer, and a cathode electrode stacked on the electronic functional layer. The insulating film extends the electronic functional layer from the display region. Effect of the Invention

[0021] The light-emitting display device according to the present specification includes auxiliary wiring for reducing the surface resistance of the common electrode constituting the light-emitting diode, and the current density is evenly distributed to a plurality of contact points where the common electrode and the low-potential wiring come into contact. Also, the light-emitting display device according to the present specification has a structure that can evenly distribute the current density to the contact points that connect the common voltage supply wiring and the common electrode. Therefore, the current density can be evenly distributed to the low-potential wiring.

[0022] The light emitting display device according to the present specification has a structure that can prevent power waste due to non-uniform current density by uniformly distributing the current density of the common electrode applied over the entire area of ​​the display panel, thereby enabling low-power driving and reducing power consumption.

[0023] In addition, the current density does not concentrate in a specific area, and heat damage due to current concentration does not occur. This extends the life of the product and maintains high product reliability even after long periods of continuous use.

[0024] In addition to the effects of the present specification mentioned above, other features and advantages of the present specification will be described below or will be clearly understood by those having ordinary skill in the art to which the present specification pertains from such descriptions and explanations. [Brief description of the drawings]

[0025] [Figure 1] 1 is a plan view showing an overall configuration of a light emitting display device according to a first embodiment of the present specification. [Figure 2A] 2 is an enlarged plan view showing an arrangement of auxiliary wiring and a common electrode connected to a low potential wiring in an outer periphery of the light emitting display device according to the first embodiment, which is indicated by "X" in FIG. [Figure 2B] 2B is an enlarged plan view showing the structure of one pixel in FIG. 1 and FIG. 2A. [Diagram 3] 1 is an equivalent circuit diagram showing a structure of one pixel constituting a light emitting display device according to a first embodiment of the present specification. [Figure 4] 2C is a cross-sectional view taken along II' in FIG. 2B, illustrating a structure of a light emitting display device according to a first embodiment of the present disclosure. [Diagram 5] FIG. 11 is a plan view showing a structure of a light emitting display device according to a second embodiment of the present specification. [Figure 6] 1 is a plan view showing a characteristic structure of a light emitting display device according to an embodiment of the present specification; [Figure 7] FIG. 11 is a plan view showing a structure of a light emitting display device according to a third embodiment of the present specification. [Figure 8] 8 is an enlarged plan view showing an arrangement structure of auxiliary wiring and a common electrode connected to a low potential wiring at an outer periphery of a light emitting display device according to a third embodiment, which is indicated by "A" in FIG. 7; [Figure 9] 9 is a cross-sectional view taken along the line II-II' of FIG. 8, illustrating a structure of a light emitting display device according to a third embodiment of the present specification. [Figure 10] FIG. 11 is a plan view showing a structure of a light emitting display device according to a fourth embodiment of the present specification. [Figure 11] 11 is an enlarged plan view showing an arrangement of auxiliary wiring and a common electrode connected to a low potential wiring at an outer periphery of a light emitting display device according to a fourth embodiment, which is indicated by "B" in FIG. [Figure 12] 12 is a cross-sectional view taken along the line III-III' of FIG. 11, illustrating a structure of a light emitting display device according to a fourth embodiment of the present specification. [Figure 13] FIG. 13 is a plan view showing a structure of a light emitting display device according to a fifth embodiment of the present specification. [Figure 14] 14 is an enlarged plan view showing an arrangement of auxiliary wiring and a common electrode connected to a low potential wiring at an outer periphery of a light emitting display device according to a fifth embodiment, which is indicated by "C" in FIG. 13. FIG. [Figure 15] 14 is a cross-sectional view taken along line IV-IV' of FIG. 13, showing the structure of a light emitting display device according to a fifth embodiment of the present specification. [Figure 16] 14 is a cross-sectional view taken along the line VV' in FIG. 13, showing a structure of a light emitting display device according to a fifth embodiment of the present specification. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] The advantages and features of the present specification, and the methods for achieving them, will become apparent from the following detailed description of the embodiments with accompanying drawings. However, the present specification is not limited to the embodiments disclosed below, and may be embodied in various different forms. The embodiments are provided solely to make the disclosure of the present specification complete, and to fully inform those skilled in the art of the invention to which the present specification pertains, and the present specification is defined only by the claims.

[0027] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining an example of this specification are illustrative, and the present invention is not limited to the matters shown in the drawings. The same reference numbers refer to the same components throughout the specification. In addition, in the description of the present invention, if it is determined that a detailed description of related publicly known technology may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

[0028] Exemplary embodiments of the present specification will be described in detail with reference to the accompanying drawings. The same reference numbers are used throughout the drawings to refer to the same or similar components. Similar reference numbers that have already been used to indicate similar components in other drawings of the present specification will be used for one component as much as possible. In the following description, if functions and configurations known to those having ordinary skill in the art to which the present specification belongs are not related to the essential configuration of the present specification, their detailed description may be omitted. The terms used in the present specification should be understood as follows.

[0029] When the terms "including," "having," "consisting of," and the like are used in this specification, other parts may be added unless "only" is used. When an element is expressed in the singular, it includes the plural unless otherwise expressly stated.

[0030] When interpreting elements, they are to be interpreted as including an error range even if there is no explicit statement otherwise.

[0031] When describing a location relationship, for example when the location relationship of two parts is described using "on", "at the top", "at the bottom", "next to" etc., one or more other parts may be located between the two parts, unless "immediately" or "directly" is used.

[0032] When describing a temporal relationship, for example when the temporal precedence is described using "after", "following", "after", "before", etc., non-consecutive cases can also be included unless "immediately" or "directly" is used.

[0033] Although the terms "first", "second" and the like are used to describe various components, these components are not limited by these terms. These terms are merely used to distinguish one component from another. Therefore, the first component referred to below may also be the second component within the technical spirit of the present invention.

[0034] In describing components in this specification, terms such as first, second, A, B, (a), (b), etc. may be used. Such terms are used to distinguish the components from other components, and do not limit the nature, order, sequence, or number of the components. When a component is described as being "connected," "coupled," or "connected" to another component, it should be understood that the component may be directly connected or connected to the other component, but that other components may be "intervening" between each component that may be indirectly connected or connected without any specific explicit description.

[0035] The term "at least one" should be understood to include all combinations that can be presented from one or more of the associated items. For example, the meaning of "at least one of the first item, the second item, and the third item" can mean not only each of the first item, the second item, or the third item, but also all combinations of items that can be presented from two or more of the first item, the second item, and the third item.

[0036] The features of the various embodiments of the present invention may be partially or fully combined or combined with each other, and may be technically linked and driven in various ways, and each embodiment may be implemented independently of the others, or may be implemented together in a linked relationship.

[0037] Hereinafter, examples of display devices according to the present specification will be described in detail with reference to the accompanying drawings. In attaching reference numerals to components in each drawing, the same components may have the same reference numerals as far as possible even if they are shown in different drawings.

[0038] Hereinafter, a light emitting display device according to the present disclosure will be described in detail with reference to the accompanying drawings. The scales of components shown in the drawings may be different from the actual scales for convenience of explanation, and therefore, the scales are not limited to those shown in the drawings.

[0039] <First Example> A first embodiment of the present specification will be described below with reference to Figures 1 to 4. Figure 1 is a plan view showing an overall configuration of an electroluminescence display device according to a first embodiment of the present specification. In Figure 1, the X-axis indicates a direction parallel to the scan lines, the Y-axis indicates a direction parallel to the data lines, and the Z-axis indicates a height direction of the display device.

[0040] Referring to FIG. 1, the light emitting display device according to the present application includes a substrate 110 , a gate (or scan) driver 200 , a pad unit 300 , a source driver integrated circuit 410 , a flexible circuit film 430 , a circuit board 450 , and a timing controller 500 .

[0041] The substrate 110 may include an insulating material or a flexible material. The substrate 110 may be made of, but is not limited to, glass, metal, plastic, or the like. When the light emitting display device is a flexible display device, the substrate 110 may be made of a flexible material such as plastic. For example, the substrate 110 may include a transparent polyimide material.

[0042] The substrate 110 may be divided into a display area (AA) and a non-display area (NDA). The display area (AA) is an area for displaying an image, and may be defined as most of the area including the center of the substrate 110, but is not limited thereto. In the display area (AA), a plurality of pixels (P) are arranged in a matrix manner. Scan lines (or gate lines) and data lines are arranged. One of the pixels (P) is arranged in an area where the scan lines proceeding in the X-axis and the data lines proceeding in the Y-axis intersect. In addition, an auxiliary line 83 proceeding in the Y-axis may be arranged on one side of some of the pixels (P). Here, the pixel (P) may represent any one of red, green, and blue, or red, green, blue, and white. A red pixel, a green pixel, and a blue pixel may be collected together, or a red pixel, a green pixel, a blue pixel, and a white pixel may be collected together to form one unit pixel.

[0043] The non-display area (NDA) is an area where an image is not displayed, and may be defined at an edge of the substrate 110 so as to surround all or a part of the display area (AA). The low potential wiring 80, the gate driver 200, and the pad unit 300 may be formed in the non-display area (NDA).

[0044] The gate driver 200 supplies scan (or gate) signals to the scan lines according to gate control signals input from the timing controller 500. The gate driver 200 may be formed in a non-display area (NDA) on one side of the display area (AA) of the base substrate 110 in a gate driver in panel (GIP) manner. The GIP manner refers to a structure in which the gate driver 200 is directly formed on the substrate 110. For example, the gate driver 200 may be formed of a shift register, and the GIP manner refers to a structure in which transistors constituting the shift register of the gate driver 200 are directly formed on the substrate 110.

[0045] The pad unit 300 may be disposed in a non-display area (NDA) on one side edge of the display area (AA) of the substrate 110. The pad unit 300 may include data pads connected to the data lines, driving current pads connected to the driving current lines, high potential pads to which a high potential is applied, and low potential pads to which a low potential is applied.

[0046] The auxiliary wiring 83 proceeding along the Y-axis in the display area (AA) is connected in the non-display area (NDA) to low-potential wiring 80 arranged on the upper and lower sides of the display area (AA). As an example, one end of the auxiliary wiring 83 can be connected to the low-potential wiring 80 arranged in the non-display area (NDA) adjacent to the upper side of the display area (AA), and the other end can be connected to the low-potential wiring 80 arranged in the non-display area (NDA) adjacent to the lower side of the display area (AA).

[0047] The source driving integrated circuit 410 receives digital video data and a source control signal from the timing control unit 500. The source driving integrated circuit 410 converts the digital video data into an analog data voltage according to the source control signal and supplies it to the data wiring. If the source driving integrated circuit 410 is made of a chip, it can be mounted on the flexible circuit film 430 by a COF (chip on film) or COP (chip on plastic) method.

[0048] The flexible circuit film 430 may be formed with wiring for connecting the pad unit 300 and the source driving integrated circuit 410, and wiring for connecting the data pad unit 300 and the circuit board 450. The flexible circuit film 430 is attached onto the data pad unit 300 using an anisotropic conductive film, thereby allowing the wiring of the pad unit 300 and the flexible circuit film 430 to be connected.

[0049] The circuit board 450 may be attached to the flexible wiring film 430. The circuit board 450 may have a plurality of circuits implemented as driving chips. For example, the timing control unit 500 may be implemented on the circuit board 450. The circuit board 450 may be a printed circuit board or a flexible printed circuit board.

[0050] The timing control unit 500 receives digital video data and a timing signal from an external system board through a cable of the circuit board 450. The timing control unit 500 generates a gate control signal for controlling the operation timing of the gate driver 200 and a source control signal for controlling the source driving integrated circuit 410 based on the timing signal. The timing control unit 500 supplies the gate control signal to the gate driver 200 and the source control signal to the source driving integrated circuit 410. Depending on the product, the timing control unit 500 and the source driving integrated circuit 410 may be formed as one driving chip and mounted on the substrate 110.

[0051] Fig. 2A is an enlarged plan view showing an arrangement structure of auxiliary wiring and a common electrode connected to a low potential wiring at an outer periphery of the light emitting display device according to the first embodiment, indicated by "X" in Fig. 1. Fig. 2B is an enlarged plan view showing the structure of one pixel in Fig. 1 and Fig. 2A. Fig. 3 is an equivalent circuit diagram showing the structure of one pixel constituting the light emitting display device according to the first embodiment of the present specification.

[0052] The layout structure of the auxiliary wiring and the common electrode connected to the low potential wiring at the outer periphery of the light emitting display according to the first embodiment will be described with reference to FIGS. 2A and 2B. FIG.

[0053] A plurality of pixels (P) can be arranged on the substrate 110. As an example, a red pixel, a green pixel, and a blue pixel can be arranged in succession in the horizontal direction. The red pixel, the green pixel, and the blue pixel can form one unit pixel. In some cases, each of these red pixel, green pixel, and blue pixel can be called a sub-pixel, and a unit pixel formed by bundling them can be called a pixel. As another example, a red pixel, a green pixel, a white pixel, and a blue pixel can be arranged in succession in the horizontal direction. The red pixel, the green pixel, the white pixel, and the blue pixel can form one unit pixel.

[0054] One auxiliary wiring 83 can be arranged for each column of a plurality of pixels (P). As an example, an auxiliary wiring 83 running in the Y-axis direction can be arranged on one side of three pixels (P).

[0055] One end of the auxiliary wiring 83 overlaps with the low potential wiring 80 arranged on the upper side of the substrate 110. As an example, the auxiliary wiring 83 can be connected to the low potential wiring 80 via a contact hole formed in an insulating film covering the end of the auxiliary wiring 83.

[0056] 2B and 3, the structure of one pixel (P) constituting the light emitting display device according to the first embodiment of the present specification will be described. One pixel (P) of the light emitting display device according to the first embodiment of the present specification can be defined by a scan line 50, a data line 60 and a driving current line 70. One pixel (P) of the light emitting display device includes a switching thin film transistor 10, a driving thin film transistor 20, a light emitting diode 90 and a storage capacitance (Cst). A high potential voltage for driving the light emitting diode 90 is applied to the driving current line 70.

[0057] The switching thin film transistor 10 may be configured to connect to the scan line 50 and the data line 60. The switching thin film transistor 10 includes a gate electrode 11, a semiconductor layer 13, a source electrode 15, and a drain electrode 17. The gate electrode 11 may be configured as a part of the scan line 50. The semiconductor layer 13 overlaps with the gate electrode 11. As an example, the semiconductor layer 13 may be disposed across the scan line 50. The portion where the semiconductor layer 13 and the gate electrode 11 overlap is defined as a channel region. The source electrode 15 branches off or connects to the data line 60, and the drain electrode 17 connects to the driving thin film transistor 20. The switching thin film transistor 10 applies a data signal to the driving thin film transistor 20 to select a pixel to be driven.

[0058] The driving thin film transistor 20 functions to drive the light emitting diode 90 of the pixel selected by the switching thin film transistor 10. The driving thin film transistor 20 includes a gate electrode 21, a semiconductor layer 23, a source electrode 25, and a drain electrode 27. The gate electrode 21 of the driving thin film transistor 20 is connected to the drain electrode 17 of the switching thin film transistor 10. The semiconductor layer 23 is disposed across the gate electrode 21. The portion where the semiconductor layer 13 and the gate electrode 11 overlap is defined as a channel region. In the driving thin film transistor 20, the drain electrode 27 branches or connects to the driving current wiring 70, and the source electrode 25 connects to the anode electrode 91 of the light emitting diode (or light emitting element) 90. An auxiliary capacitance (Cst) can be formed between the gate electrode 21 of the driving thin film transistor 20 and the anode electrode 91 of the light emitting diode 90.

[0059] The driving thin film transistor 20 is disposed between the driving current wiring 70 and the light emitting diode 90. The driving thin film transistor 20 controls the amount of current flowing from the driving current wiring 70 to the light emitting diode 90 according to the voltage difference between the gate electrode 21 and the source electrode 25.

[0060] Further referring to FIG. 4, the cross-sectional structure of the light emitting display device according to the present specification will be described. FIG. 4 is a cross-sectional view taken along II' in FIG. 2, showing the structure of the light emitting display device according to the first embodiment of the present specification. The light emitting display device includes a substrate 110, a driving element layer 220, and a light emitting element layer 330. The driving element layer 220 includes a multi-layer thin film formed on the substrate 110. The driving element layer 220 includes a switching thin film transistor 10 and a driving thin film transistor 20.

[0061] Specifically, the data wiring 60, the driving current wiring 70, the auxiliary wiring 83, and the light-shielding layer 75 are formed on the substrate 110. The light-shielding layer 75 is spaced a certain distance from the data wiring 60 and the driving current wiring 70, and can be arranged in an island shape overlapping the semiconductor layers 13 and 23.

[0062] A buffer layer 31 is laminated on the driving current wiring 70, the auxiliary wiring 83, the data wiring 60, and the light-shielding layer 75 so as to cover the entire surface of the substrate 110. A semiconductor layer 13 of the switching thin-film transistor 10 and a semiconductor layer 23 of the driving thin-film transistor 20 are formed on the buffer layer 31. At least the channel regions of the semiconductor layers 13 and 23 are preferably disposed so as to overlap with the light-shielding layer 75.

[0063] A gate insulating film 33 is laminated on the substrate 110 on which the semiconductor layers 13 and 23 are formed. A gate electrode 11 overlapping the semiconductor layer 13 of the switching thin film transistor 10 and a gate electrode 21 overlapping the semiconductor layer 23 of the driving thin film transistor 20 are formed on the gate insulating film 33. A source electrode 15 in contact with one side of the semiconductor layer 13 while being spaced apart from the gate electrode 11 and a drain electrode 17 in contact with the other side of the semiconductor layer 13 are formed on both sides of the gate electrode 11 of the switching thin film transistor 10. Similarly, a source electrode 25 in contact with one side of the semiconductor layer 23 while being spaced apart from the gate electrode 21 and a drain electrode 27 in contact with the other side of the semiconductor layer 23 are formed on both sides of the gate electrode 21 of the driving thin film transistor 20.

[0064] The gate electrodes 11 and 21, the source electrodes 15 and 25, and the drain electrodes 17 and 27 are formed in the same layer, but are spatially or electrically separated from each other. The source electrode 15 of the switching thin film transistor 10 is connected to the data wiring 60 through a contact hole penetrating the gate insulating film 33 and the buffer layer 31. Although not shown in the figure, the drain electrode 27 of the driving thin film transistor 20 can be connected to the driving current wiring 70 through a contact hole penetrating the gate insulating film 33.

[0065] A protective film 35 is laminated on the substrate 110 on which the thin film transistors 10 and 20 are formed. The protective film 35 is preferably formed of an inorganic film such as silicon oxide (SiOx) or silicon nitride (SiNx).

[0066] A light emitting element layer 330 is formed on the driving element layer 220. The light emitting element layer 330 includes a light emitting diode 90. Before forming the light emitting diode 90, a planarization film 37 is laminated on the protective film 35. The planarization film 37 is a thin film for planarizing the uneven surface of the substrate 110 on which the thin film transistors 10 and 20 are formed. In order to make the height difference uniform, the planarization film 37 may be formed of an organic material. A pixel contact hole 30 exposing a part of the source electrode 25 of the driving thin film transistor 20 is formed in the protective film 35 and the planarization film 37.

[0067] The light emitting diode 90 includes an anode electrode 91, a light emitting layer 93, and a cathode electrode 95. The light emitting diode 90 emits light by a current adjusted by the driving thin film transistor 20. To explain again, the light emitting diode 90 can display an image by emitting light by a current adjusted by the driving thin film transistor 20. The anode electrode 91 of the light emitting diode 90 is connected to the source electrode 25 of the driving thin film transistor 20, and the cathode electrode 95 is connected to a low potential wiring 80 to which a low potential voltage is supplied. That is, the light emitting diode 90 is driven by a current flowing from the driving current wiring 70 to the low potential wiring 80 by the driving thin film transistor 20.

[0068] An anode electrode 91 is formed on an upper surface of the planarization film 37. The anode electrode 91 is connected to the source electrode 25 of the driving thin film transistor 20 through the pixel contact hole 30. The components of the anode electrode 91 may vary depending on the light emitting structure of the light emitting diode 90. For example, in the case of a bottom emission type that provides light toward the substrate 110, the anode electrode 91 may be formed of a transparent conductive material. For example, in the case of an upper emission direction facing the substrate 110, the anode electrode 91 may be formed of a metal material having excellent light reflectance. Since the present specification relates to a top emission type display device, it is preferable that the anode electrode 91 includes a metal material.

[0069] A bank 97 is formed on the surface of the substrate 110 on which the anode electrode 91 is formed. The bank 97 is preferably an insulating film made of an inorganic or organic material. Here, a case where the bank 97 is made of an organic material will be described. The bank 97 covers a part of the edge of the anode electrode 91 and exposes most of the central region. The central region not covered by the bank 97 is defined as the light-emitting region (EA), and the region where the bank 97 is formed is defined as the non-light-emitting region (NEA).

[0070] An emitting layer 93 is laminated on the anode electrode 91 and the bank 97. The emitting layer 93 may be formed over the entire display area (AA) of the substrate 110 to cover the anode electrode 91 and the bank 97. According to an example, the emitting layer 93 may include two or more emitting units to emit white light. For example, the emitting layer 93 may include a first emitting unit and a second emitting unit vertically stacked to emit white light by mixing a first light and a second light.

[0071] As another example, the light emitting layer 93 may include any one of a blue light emitting portion, a green light emitting portion, and a red light emitting portion for emitting light corresponding to a color set for the pixel. Also, the light emitting diode 90 may further include a functional layer for improving the light emitting efficiency and / or life of the light emitting layer 93.

[0072] A cathode electrode 95 is laminated on the entire surface of the substrate 110 on which the light emitting layer 93 is formed. The cathode electrode 95 is laminated so as to be in surface contact with the light emitting layer 93. The cathode electrode 95 is formed on the entire substrate 110 so as to be commonly connected to the light emitting layer 93 formed in all pixels. In the case of a top emission type, the cathode electrode 95 includes a transparent conductive material. For example, the cathode electrode 95 may be made of an oxide containing indium, and may be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0073] In the top emission type, the metal oxide, which is a transparent conductive material constituting the cathode electrode 95, has a much higher sheet resistance than metal materials. Therefore, when the area of ​​the cathode electrode 95 is large, such as in a large-area TV, there may be areas where the sheet resistance is high, and it may not be possible to ensure a uniform low voltage across the entire area. This causes uneven brightness and is a major cause of image quality degradation.

[0074] In order to solve such problems, it is necessary to have a structure that reduces the resistance of the cathode electrode 95. The auxiliary wiring 83 is a component arranged to reduce the resistance of the cathode electrode 95. Hereinafter, the structure of the upper side of the substrate 110 to which the low potential wiring 80, the auxiliary wiring 83, and the cathode electrode 95 are connected will be described with reference to Figures 2A-2B and 4.

[0075] The auxiliary wiring 83 may be formed first on the substrate 110. Alternatively, the auxiliary wiring 83 may be formed in the same layer and made of the same material as the source electrodes 15, 25 and drain electrodes 17, 27 of the thin film transistors 10, 20. Here, a case will be described in which the auxiliary wiring 83 is formed in the same layer as the data wiring 60 and the driving current wiring 70.

[0076] The auxiliary wiring 83 is disposed on one side of the pixel (P) in parallel with the data wiring 60 and the driving current wiring 70. It is not necessary to dispose an auxiliary wiring 83 for each pixel (P). For example, one auxiliary wiring 83 can be disposed for every three, six, or twelve pixels (P) in the horizontal direction. As shown in FIGS. 2A-2B, the auxiliary wiring 83 can be disposed slightly away from one side of the pixel (P). As another example, it can be disposed so as to overlap the pixel (P) and can be disposed between the data wiring 60 and the driving current wiring 70.

[0077] A buffer layer 31 and a gate insulating film 33 are sequentially laminated on the auxiliary wiring 83. A first contact hole (CH1) exposing a part of the auxiliary wiring 83 is formed in the gate insulating film 33 and the buffer layer 31. An auxiliary electrode 85 is formed on the gate insulating film 33. The auxiliary electrode 85 contacts the auxiliary wiring 83 through the first contact hole (CH1). As another example, the auxiliary electrode 85 can be omitted.

[0078] A protective film 35 is laminated on the auxiliary electrode 85. A planarizing film 37 is laminated on the protective film 35. A second contact hole (CH2) may be formed in the planarizing film 37 and the protective film 35 so as to expose a portion of the auxiliary electrode 85. As another example, the planarizing film 37 and the protective film 35 may be removed so as to expose the entire auxiliary electrode 85.

[0079] A low potential wiring 80 is formed on the planarizing film 37. The low potential wiring 80 can be made of the same metal material as the anode electrode 91.

[0080] A bank 97 is formed on the anode electrode 91. However, the bank 97 can be patterned so as to expose the entire low-potential wiring 80 formed of the same material in the same layer as the anode electrode 91. As a result, the low-potential wiring 80 can have a structure in which the entire low-potential wiring 80 is exposed on the planarization film 37. The low-potential wiring 80 is connected to the auxiliary electrode 85 via a second contact hole (CH2) formed in the planarization film 37 and the protective film 35. As a result, the low-potential wiring 80 is electrically connected to the auxiliary wiring 83 via the auxiliary electrode 85.

[0081] A light-emitting layer 93 is laminated on the anode electrode 91 and the bank 97. The light-emitting layer 93 is laminated commonly to all the pixels (P) formed on the substrate 110. However, the light-emitting layer 93 can only extend to the upper surface of the bank 97 in the non-display area (NDA). Therefore, the low-potential wiring 80 does not contact the light-emitting layer 93.

[0082] A cathode electrode 95 is laminated on the light-emitting layer 93. The cathode electrode 95 is laminated commonly to all the pixels (P) formed on the substrate 110. In particular, the cathode electrode 95 can be disposed so as to extend outside the non-display area (NDA) and come into direct surface contact with the low-potential wiring 80.

[0083] 2A-2B and 4 show a structure in which the cathode electrode 95 and the low potential wiring 80 are connected to the upper side of the substrate 110. In a similar configuration, the cathode electrode 95 can also be connected to the low potential wiring 80 arranged on the lower side of the substrate 110.

[0084] In the light emitting display device according to the first embodiment of the present specification, a cathode electrode 95 made of a transparent conductive material is connected to low potential wirings 80 disposed on the upper and lower sides of a substrate 110. The low potential wirings 80 on the upper side and the low potential wirings 80 on the lower side are connected to each other via an auxiliary wiring 83.

[0085] 1, the low potential wiring 80 can receive a low potential voltage via a low potential supply wiring 89 provided on the circuit board 450. In this case, the low potential supply wiring 89 provided on the circuit board 450 and the low potential wiring 80 provided on the substrate 110 can be connected via a wiring provided on the flexible circuit film 430.

[0086] As an example, a plurality of flexible circuit films 430 may be provided to connect the circuit board 450 and the substrate 110. As shown in Fig. 1, five flexible circuit films 430 may be provided. The flexible circuit films 430 are components for connecting the signal wiring of the substrate 110 and the signal wiring of the circuit board 450. The more signal wirings there are, the more flexible circuit films 430 are required.

[0087] As the number of flexible circuit films 430 increases, the number of source driving integrated circuits 410 also increases. Therefore, in a display device with high resolution, the number of source driving integrated circuits 410 and flexible circuit films 430 increases, so the cost gradually increases and the structure becomes more complicated.

[0088] In order to reduce costs and simplify the structure, it is necessary to reduce the number of source driving integrated circuits 410 and flexible circuit films 430 as much as possible. In addition, the flexible circuit film 430 must also include signal wiring connected to the gate supply wiring 51 that supplies gate signals to the gate driver 200.

[0089] 1, it is preferable that the source driving integrated circuit 410 and the flexible circuit film 430 arranged on the outermost left and right sides have a connection structure for supplying a gate signal to the gate supply wiring 51. As a result, an asymmetric structure can be formed in which a signal wiring connected to the gate supply wiring 51 is arranged on one side of the source driving integrated circuit 410 and the flexible circuit film 430 arranged on the outermost side, and a signal wiring connected to the low potential terminal 81 is arranged on the other side.

[0090] 1, the source driving integrated circuit 410 and the flexible circuit film 430 arranged in the center of the substrate 110 may have two low potential terminals 81, one at each end, connected to the low potential wiring 80. Meanwhile, the source driving integrated circuit 410 and the flexible circuit film 430 arranged on the outermost side may have only one low potential terminal 81 connected to the low potential wiring 80.

[0091] 1, when a higher current is supplied to increase the brightness of the display device, a problem may occur in that the current density becomes high at one low potential terminal 81 provided on the outermost flexible circuit film 430. In the central flexible circuit film 430 with one low potential terminal 81 on each side, the current density is divided in two, and the current density can be dispersed even when a high current is supplied. However, in the outermost flexible circuit film 430, the current density may be concentrated at one low potential terminal 81.

[0092] Hereinafter, the current density concentration phenomenon will be described using the first flexible circuit film 431 arranged at the rightmost side of the substrate 110 in FIG. 1 and the second flexible circuit film 432 arranged at the center of the substrate 110. The first flexible circuit film 431 and the second flexible circuit film 432 have the same size and are arranged to equally distribute the signal wiring of the substrate 110. In the display area (AA), the area corresponding to the first flexible circuit film 431 and the area corresponding to the second flexible circuit film 432 can be divided by a boundary line (BL). Therefore, the same current "I" can be passed through the first flexible circuit film 431 and the second flexible circuit film 432, respectively.

[0093] The boundary lines (BL) shown in Figures 1, 5, 6, 7, 10 and 13, which show the overall planar structures of display devices according to various embodiments of the present application, and in Figures 2A, 8, 11 and 14, which show enlarged planar structures, are lines that separate the area corresponding to the flexible circuit film arranged at the rightmost position from the area corresponding to the flexible circuit film arranged at the center, or the area corresponding to the flexible circuit film arranged at the leftmost position from the area corresponding to the flexible circuit film arranged at the center.

[0094] 1, the second flexible circuit film 432 has two low potential terminals 81, so a current of "i / 2" can flow through each of the low potential terminals 81. Meanwhile, the first flexible circuit film 431 has one low potential terminal 81, so a current of "i" can flow through the low potential terminal 81. Therefore, the low potential terminal 81 of the first flexible circuit film 431 can have twice the current density.

[0095] As a result, excessive heat may be generated at the receiving portion of the low potential terminal 81 of the first flexible circuit film 431 located at the outermost portion, and if such heat is concentrated for a long period of time, it may cause damage to the display device.

[0096] In the following embodiment, a structure for preventing current density concentration that may occur due to the provision of a first flexible circuit film 431 having an asymmetric structure and dispersing the current density will be described.

[0097] <Second Example> Hereinafter, the structure of a light emitting display device according to a second embodiment of the present specification will be described with reference to Fig. 5. Fig. 5 is a plan view showing the structure of a light emitting display device according to a second embodiment of the present specification. The light emitting display device according to the second embodiment shown in Fig. 5 has almost the same structure as that of the first embodiment. However, in the second embodiment, there is a difference in that auxiliary wiring is not arranged in the portion corresponding to the outermost flexible circuit films 431 and 435 in the display area (AA), and auxiliary wiring 83 is arranged only in the portion corresponding to the central flexible circuit films 432, 433, and 434.

[0098] In the following description, differences from the first embodiment will be mainly described. In the display area (AA), an auxiliary wiring 83 is not arranged in an area corresponding to the first flexible circuit film 431 arranged on the first right side. However, the cathode electrode 95 in this area has a structure in which it is connected to the low potential wiring 80 arranged on the upper and lower sides of the substrate 110.

[0099] For example, the region of the cathode electrode 95 corresponding to the first flexible circuit film 431 with respect to the boundary line (BL) may be divided into a lower region 951 and an upper region 952. This division is not a physical division but may be made based on current density. As an example, the area ratio of the lower region 951 to the upper region 952 may be 3:2.

[0100] The low potential voltage applied to the cathode electrode 95 is supplied via a low potential wiring arranged nearby. Therefore, in the lower region 951 of the cathode electrode 95, the low potential voltage can be supplied via the low potential wiring 80 on the lower side of the substrate 110, and in the upper region 952 of the cathode electrode 95, the low potential voltage can be supplied via the low potential wiring 80 on the upper side of the substrate 110.

[0101] As a result, a current of 3i / 5 may flow through the low potential terminal 81 connected to the low potential wiring 80 on the lower side of the lower region 951. A current of 2i / 5 may flow through the low potential wiring 80 on the upper side of the upper region 952. The current flowing through the low potential wiring 80 on the upper side of the upper region 952 flows to the low potential wiring 80 on the lower side of the lower region 952 via the auxiliary wiring 83 arranged in the region corresponding to the second flexible circuit film 432. That is, the current flowing through the current path (1) in FIG. 5 is 3i / 5=6i / 10.

[0102] The low potential wiring 80 disposed in the region corresponding to the second flexible circuit film 432 has two low potential terminals 81, and thus a current of i / 2 flows through each low potential terminal 81. Here, the current of 2i / 5 transferred from the upper region 952 in the region corresponding to the first flexible circuit film 431 may also be divided in half and flow.

[0103] That is, a current of i / 2+i / 5=7i / 10 flows through each of the two low potential terminals 81 provided on the second flexible circuit film 432. That is, in FIG. 5, the current flowing through current path (2) is 7i / 10, and the current flowing through current path (3) is also 7i / 10.

[0104] As a result, the currents flowing through the current paths (1), (2), and (3) are distributed in a substantially uniform manner, so that the current density does not concentrate on the low potential terminal 81 of the first flexible circuit film 431 arranged on the outermost side, and excessive heat is not generated.

[0105] Hereinafter, structural features of a light emitting display device according to an embodiment of the present specification will be described with reference to Fig. 6. Fig. 6 is a plan view showing a characteristic structure of a light emitting display device according to an embodiment of the present specification.

[0106] The light emitting display device according to an embodiment of the present specification includes a substrate 110, a pad unit 300, a low potential wiring 80, a low potential terminal 81, an auxiliary wiring 83, and a common electrode 95 (or a cathode electrode). The substrate 110 includes a display area (AA) and a non-display area (NDA). The display area (AA) may be defined in a central area of ​​the substrate 110. The non-display area (NDA) may be defined to surround the periphery of the display area (AA). The substrate 110 may be divided into a first area 1101 and a second area 1102 by a boundary line (BL) disposed on the substrate 110. The first area 1101 may be allocated to the right side of the boundary line (BL), and the second area 1102 may be allocated to the left side of the boundary line (BL).

[0107] The low potential wiring 80 includes a first low potential wiring 801 and a second low potential wiring 802 arranged in parallel facing each other. The first low potential wiring 801 is arranged laterally across the first region 1101 and the second region 1102 on the upper side of the substrate 110. The second low potential wiring 802 is arranged laterally across the first region 1101 and the second region 1102 on the lower side of the substrate 110.

[0108] The pad section 300 may be defined on the lower side of the substrate 110. As an example, the pad section 300 may be disposed outside the second low potential wiring 802 disposed on the lower side. The low potential terminal 81 may be disposed in the pad section 300.

[0109] The low potential terminal 81 arranged in the pad section 300 is connected to the second low potential wiring 802. One low potential terminal 81 can be arranged in the first region 1101. Two low potential terminals 81 can be arranged in the second region 1102. As an example, a first low potential terminal 811 can be arranged in the first region 1101, and a second low potential terminal 812 and a third low potential terminal 813 can be arranged in the second region 1102.

[0110] The auxiliary wiring 83 may be realized in the form of a plurality of line segments connecting the first low potential wiring 801 and the second low potential wiring 802. In particular, the auxiliary wiring 83 is characterized in that it is not formed in the first region 1101 but is disposed only in the second region 1102.

[0111] The common electrode 95 can be formed as one layer over the entire area of ​​the substrate 110. The common electrode 95 can be formed so as to cover both the first region 1101 and the second region 1102. The common electrode 95 can be in surface contact with the first low potential wiring 801 and the second low potential wiring 801 while overlapping therewith.

[0112] In this structure, a lower region 951 of the first region 1101 of the common electrode 95 receives a low potential via a first low potential terminal 811 connected to the second low potential wiring 802. On the other hand, an upper region 952 of the common electrode 95 receives a low potential via the first low potential wiring 801. In particular, the upper region 952 is connected to the first low potential wiring 801, is connected to the second low potential wiring 802 arranged in the second region 1102 along the auxiliary wiring 83, and is again connected to the second low potential terminal 812 and the third low potential terminal 813 arranged in the second region 1102.

[0113] Therefore, in the first region 1101 having only one first low potential terminal 811, only the current in the lower region 951 is transmitted to the first low potential terminal 811. At the same time, the current in the upper region 952 is dispersed and transmitted to the second low potential terminal 812 and the third low potential terminal 813 via the second region 1102. Therefore, an excessively high current density does not concentrate in the first low potential terminal 811, but is dispersed to the adjacent second low potential terminal 812 and third low potential terminal 813.

[0114] In the following embodiment, the basic structure and current dispersion mechanism are the same as those in the second embodiment, but the specific configurations of the components and the connection structure can be varied in a variety of ways.

[0115] <Third Example> Hereinafter, a third embodiment of the present specification will be described with reference to Fig. 7 to Fig. 9. Fig. 7 is a plan view showing a structure of a light emitting display device according to a third embodiment of the present specification. Fig. 8 is an enlarged plan view showing an arrangement structure of auxiliary wiring and a common electrode connected to a low potential wiring at an outer periphery of the light emitting display device according to the third embodiment, as indicated by "A" in Fig. 7.

[0116] 7 and 8, the light emitting display device according to the third embodiment of the present application has substantially the same structure as the light emitting display device according to the second embodiment, except that the third embodiment further includes dummy auxiliary wiring 831 in a portion corresponding to the outermost flexible circuit films 431 and 435.

[0117] In the light emitting display device according to the third embodiment, auxiliary wiring 83 is arranged in the display area (AA) corresponding to central flexible circuit films 432, 433, and 434. Also, dummy auxiliary wiring 831 is arranged in the display area (AA) corresponding to outermost flexible circuit films 431 and 435.

[0118] The dummy auxiliary wiring 831 is connected to the low potential wiring 80 arranged on the lower side of the substrate 110. However, the dummy auxiliary wiring 831 is not physically or electrically connected to the low potential wiring 80 arranged on the upper side of the substrate 110.

[0119] FIG. 9 is a cross-sectional view taken along II-II' of FIG. 8 and showing a structure of a light emitting display device according to a third embodiment of the present specification. Referring to FIG. 9, as an example, the dummy auxiliary wiring 831 may be arranged at a certain distance from the low potential wiring 80 arranged on the upper side of the substrate 110. As another example, not shown in the figure, the dummy auxiliary wiring 831 may overlap with the low potential wiring 80 arranged on the upper side. In this case, the first contact hole (CH1), the second contact hole (CH2), and the auxiliary electrode 85 shown in FIG. 4 may not be provided. As a result, the dummy auxiliary wiring 831 is not physically and electrically connected to the low potential wiring 80 arranged on the upper side.

[0120] In the second embodiment, the parts corresponding to the outermost flexible circuit films 431, 435 where the auxiliary wiring is not arranged have different components of the display device from the parts where the auxiliary wiring is arranged. As a result, the external light reflection and the image quality depending on the presence or absence of wiring may be perceived differently in the central region and the outermost region. Therefore, in the third embodiment, the components of the central part and the outermost part are made the same, and dummy auxiliary wiring 831 is provided to ensure the same level of image quality over the entire substrate. In particular, in order to maintain the image quality uniform over the entire area of ​​the display device, it is preferable that the auxiliary wiring 83 and the dummy auxiliary wiring 831 are arranged at the same intervals.

[0121] <Fourth Example> A fourth embodiment of the present specification will be described below with reference to Fig. 10 and Fig. 11. Fig. 10 is a plan view showing a structure of a light emitting display device according to a fourth embodiment of the present specification. Fig. 10 is an enlarged plan view showing an arrangement structure of auxiliary wiring and a common electrode connected to a low potential wiring at an outer periphery of the light emitting display device according to the fourth embodiment, as indicated by "B" in Fig. 10.

[0122] The light emitting display device according to the fourth embodiment shown in Fig. 10 has almost the same structure as that of the first embodiment, except that the laminated structure of the layers constituting the light emitting diode 90 has a different feature from that of the first embodiment.

[0123] For example, the light emitting diode 90 has a structure in which an anode electrode 91, a light emitting layer 93, and a cathode electrode 95 are sequentially stacked. More specifically, the light emitting diode 90 may further include an electronic functional layer 95′ for improving electrical contact between the light emitting layer 93 and the cathode electrode 95.

[0124] The light emitting display device according to the fourth embodiment has a structural feature in that an electronic functional layer 95' is interposed between the cathode electrode 95 and the low potential wiring 80 in an area of ​​the display area AA corresponding to the first flexible circuit film 431 disposed on the first right side. The electronic functional layer 95' is in contact with the light emitting layer 93 and functions to increase the mobility of electrons so as to smoothly transfer electrons supplied from the cathode electrode 95 to the light emitting layer 93. However, the electronic functional layer 95' has low charge mobility and has very high contact resistance unless it is combined with a charge functional layer that supplies charges or a light emitting layer that receives charges.

[0125] Therefore, in the area to the right of the boundary line (BL), which corresponds to the outermost flexible circuit films 431, 435, an electronic functional layer 95' extending from the display area (AA) is disposed below the cathode electrode 95. On the other hand, in the area to the left of the boundary line (BL), which corresponds to the central flexible circuit films 432, 433, 434, an electronic functional layer 95' is not disposed between the cathode electrode 95 and the low potential wiring 80.

[0126] Hereinafter, a cross-sectional structure of a portion corresponding to the outermost flexible circuit films 431 and 435, which is a right region of the boundary line (BL), will be described with further reference to Fig. 12. Fig. 12 is a cross-sectional view showing a structure of a light emitting display device according to a fourth embodiment of the present disclosure, taken along III-III' in Fig. 11.

[0127] In Fig. 12, the same parts as in Fig. 4 will not be described. In the light-emitting diode 90, a light-emitting layer 93 is laminated on an anode electrode 91. Although not shown in the figure, a charge functional layer may be further provided between the anode electrode 91 and the light-emitting layer 93. The light-emitting layer 93 may be laminated in common over the entire display area (AA). In this case, the charge functional layer may also be laminated in common over the entire display area (AA) like the light-emitting layer 93.

[0128] An electronic functional layer 95' is laminated on the light-emitting layer 93. The electronic functional layer 95' can be disposed over the entire display area (AA) and partially extending into the non-display area (NDA) so as to cover the low-potential wiring 80. The cathode electrode 95 is disposed on the electronic functional layer 95' so as to extend over the entire display area (AA) and the non-display area (NDA) and overlap with the low-potential wiring 80.

[0129] On the upper side of the substrate 110, the auxiliary wiring 83 is connected to the low-potential wiring 80 via the auxiliary electrode 85. In the portions corresponding to the outermost flexible circuit films 431, 435, an electronic functional layer 95' is laminated so as to extend from the display area (AA) and completely cover the low-potential wiring 80. On the other hand, in the portions corresponding to the central flexible circuit films 432, 433, 434, the electronic functional layer 95' is disposed only inside the display area (AA).

[0130] A cathode electrode 95 is laminated on the electronic functional layer 95'. In the areas corresponding to the outermost flexible circuit films 431, 435, the electronic functional layer 95' and the cathode electrode 95 are in surface contact. On the other hand, in the areas corresponding to the central flexible circuit films 432, 433, 434, the cathode electrode 95 is in direct surface contact with the low-potential wiring 80.

[0131] Therefore, the auxiliary wiring 83 has a structure in which it is physically and electrically connected to the upper side low potential wiring 80 over the entire display area (AA). However, the cathode electrode 95 has a structure in which it is physically and electrically connected to the low potential wiring 80 only in the portion corresponding to the central flexible circuit films 432, 433, and 434 in the display area (AA).

[0132] As a result, in the third embodiment, the same current path as described in the second embodiment can be formed, and the current density can be prevented from concentrating on the low potential terminals 81 arranged on the outermost flexible circuit films 431 and 435.

[0133] <Fifth Example> Hereinafter, a fifth embodiment of the present specification will be described with reference to Fig. 13 and Fig. 14. Fig. 13 is a plan view showing a structure of a light emitting display device according to a fifth embodiment of the present specification. Fig. 14 is an enlarged plan view showing an arrangement structure of auxiliary wiring and a common electrode connected to a low potential wiring at an outer periphery of the light emitting display device according to the fifth embodiment, indicated by "C" in Fig. 13.

[0134] 13 and 14, the light emitting display device according to the fifth embodiment of the present specification includes a substrate 110, a pad unit 300, a low potential wiring 80, a low potential terminal 81, an auxiliary wiring 83, and a cathode electrode 95.

[0135] The substrate 110 includes a display area (AA) and a non-display area (NDA). The display area (AA) can be defined in a central area of ​​the substrate 110. The non-display area (NDA) can be defined to surround the periphery of the display area (AA). The substrate 110 can also be divided into a first area 1101 and a second area 1102 by a boundary line (BL) disposed on the substrate 110. The first area 1101 can be allocated to the right side of the boundary line (BL) on the substrate 110, and the second area 1102 can be allocated to the left side of the boundary line (BL).

[0136] The low potential wiring 80 is composed of a first low potential wiring 801, a second low potential wiring 802, and a third low potential wiring 803. The first low potential wiring 801 and the third low potential wiring 803 are disposed on the upper side of the substrate 110. The second low potential wiring 802 is disposed on the lower side of the substrate 110. The first low potential wiring 801 and the third low potential wiring 803 are spaced apart at a constant interval and have a line segment shape extending in parallel to each other in the lateral direction of the substrate 110. The third low potential wiring 803 can be disposed on the substrate 110 on the outer side than the first low potential wiring 801. The second low potential wiring 802 faces the third low potential wiring 803 and has a line segment shape extending in parallel to the lateral direction of the substrate 110.

[0137] The pad section 300 may be defined on the lower side of the substrate 110. As an example, the pad section 300 may be disposed outside the second low potential wiring 802 disposed on the lower side. The low potential terminal 81 may be disposed in the pad section 300.

[0138] The low potential terminal 81 arranged in the pad unit 300 is connected to the second low potential wiring 802. A plurality of low potential terminals 81 may be arranged. As an example, a plurality of flexible circuit films 430 may be arranged in the pad unit 300. For convenience, five flexible circuit films 431, 432, 433, 434, and 435 are shown in FIG. 13. Specifically, the flexible circuit film 430 includes one rightmost flexible circuit film 431, one leftmost flexible circuit film 435, and three central flexible circuit films 432, 433, and 434.

[0139] The rightmost flexible circuit film 431 and the leftmost flexible circuit film 435 each have one low potential terminal 81 and a gate terminal 51' connected to the gate supply wiring 51. Meanwhile, the middle flexible circuit films 432, 433, and 434 each have two low potential terminals 81 but no gate terminal 51'.

[0140] The auxiliary wiring 83 includes a plurality of first auxiliary wirings 832 and a plurality of second auxiliary wirings 834. The plurality of first auxiliary wirings 832 are arranged in the first region 1101 and connect the first low potential wiring 801 and the second low potential wiring 802. The plurality of second auxiliary wirings 834 are arranged in the second region 1102 and connect the third low potential wiring 803 and the second low potential wiring 802.

[0141] The common electrode 95 can be formed in one layer over the entire area of ​​the substrate 110. The common electrode 95 can be formed so as to cover both the first region 1101 and the second region 1102. The common electrode 95 can be in surface contact with the second low potential wiring 801 while overlapping therewith. Meanwhile, the common electrode 95 is not connected to the first low potential wiring 801 in the first region 1101 but is connected to the third low potential wiring 803. Also, the common electrode 95 is not connected to the third low potential wiring 803 in the second region 1102 but is connected to the first low potential wiring 801.

[0142] Hereinafter, a cross-sectional structure of a light emitting display device according to a fifth embodiment of the present specification will be described with reference to Figures 15 and 16. Figure 15 is a cross-sectional view showing the structure of a light emitting display device according to a fifth embodiment of the present specification taken along line IV-IV' in Figure 14. Figure 16 is a cross-sectional view showing the structure of a light emitting display device according to a fifth embodiment of the present specification taken along line V-V' in Figure 14.

[0143] Since the cross-sectional structure of the light emitting display device according to the fifth embodiment is basically similar to the structure shown in Fig. 4, only the main features that are different will be described. For the same parts, refer to the description of Fig. 4.

[0144] First, the structure of the first region 1101 will be described with reference to Fig. 13, Fig. 14, and Fig. 15. A first auxiliary wiring 832 is formed on a substrate 110. The first auxiliary wiring 832 has a length that starts to overlap with a second low potential wiring 802 formed later and ends to overlap with the first low potential wiring 801.

[0145] A buffer layer 31 and a gate insulating film 33 are laminated in this order on the first auxiliary wiring 832. A first contact hole (CH1) exposing a part of an end of the first auxiliary wiring 832 is formed in the gate insulating film 33 and the buffer layer 31. A first auxiliary electrode 851 is formed on the gate insulating film 33. The first auxiliary electrode 851 is in contact with the first auxiliary wiring 832.

[0146] A protective film 35 is laminated on the first auxiliary electrode 851. A planarizing film 37 is laminated on the protective film 35. A second contact hole (CH2) can be formed in the planarizing film 37 and the protective film 35 so as to expose a portion of the first auxiliary electrode 851.

[0147] A first low potential wiring 801 and a third low potential wiring 803 are formed on the planarization film 37. The first low potential wiring 801 and the third low potential wiring 803 are spaced apart by a certain distance. The first low potential wiring 801 contacts the first auxiliary electrode 851 through a second contact hole (CH2).

[0148] In the display area (AA), an anode electrode 91 is formed, which is made of the same material in the same layer as the first low potential wiring 801 and the third low potential wiring 803. The edge of the anode electrode 91 is covered with a bank 97, which defines the light emitting area (EA). On the other hand, the bank 97 does not cover the first low potential wiring 801 and the third low potential wiring 803, and can be formed only up to the vicinity of the boundary between the display area (AA) and the non-display area (NDA).

[0149] A light-emitting layer 93 is laminated on the anode electrode 91 and the bank 97. The light-emitting layer 93 is commonly laminated over the entire display area (AA) on the substrate 110. The light-emitting layer 93 can be extended only up to the upper surface of the bank 97 in the non-display area (NDA). Therefore, the first low potential wiring 801 and the third low potential wiring 803 do not contact the light-emitting layer 93.

[0150] An electronic functional layer 95′ is laminated on the light emitting layer 93. The electronic functional layer 95′ can be disposed over the entire display area (AA) and extending into the non-display area (NDA) so as to cover both the first low potential wiring 801 and the third low potential wiring 803.

[0151] In the first region 1101, the electronic functional layer 95' covering the third low-potential wiring 803 is patterned to form a first low-potential contact hole (CT1) exposing a part of the third low-potential wiring 803. However, in the first region 1101, the first low-potential wiring 801 has a structure covered with the electronic functional layer 95'. A cathode electrode 95 is laminated on the electronic functional layer 95'. The cathode electrode 95 does not contact the first low-potential wiring 801 in the first region 1101, but contacts the third low-potential wiring 803.

[0152] Next, the structure of the second region 1102 will be described with reference to Fig. 13, Fig. 14, and Fig. 16. A second auxiliary wiring 834 is formed on the substrate 110. The second auxiliary wiring 834 has a length that starts to overlap with the second low potential wiring 802 to be formed later, extends to overlap with the first low potential wiring 801, and ends to overlap with the third low potential wiring 803.

[0153] A buffer layer 31 and a gate insulating film 33 are laminated in this order on the second auxiliary wiring 834. A first contact hole (CH1) exposing a part of an end of the second auxiliary wiring 834 is formed in the gate insulating film 33 and the buffer layer 31. A second auxiliary electrode 852 is formed on the gate insulating film 33. The second auxiliary electrode 852 is in contact with the second auxiliary wiring 834.

[0154] A protective film 35 is laminated on the second auxiliary electrode 852. A planarizing film 37 is laminated on the protective film 35. A second contact hole (CH2) can be formed in the planarizing film 37 and the protective film 35 so as to expose a portion of the second auxiliary electrode 852.

[0155] A first low potential wiring 801 and a third low potential wiring 803 are formed on the planarization film 37. The first low potential wiring 801 and the third low potential wiring 803 are spaced apart by a certain distance. The third low potential wiring 803 contacts the second auxiliary electrode 852 through a second contact hole (CH2).

[0156] In the display area (AA), an anode electrode 91 is formed, which is made of the same material in the same layer as the first low potential wiring 801 and the third low potential wiring 803. The edge of the anode electrode 91 is covered with a bank 97, which defines the light emitting area (EA). On the other hand, the bank 97 does not cover the first low potential wiring 801 and the third low potential wiring 803, and can be formed only up to the vicinity of the boundary between the display area (AA) and the non-display area (NDA).

[0157] A light-emitting layer 93 is laminated on the anode electrode 91 and the bank 97. The light-emitting layer 93 is commonly laminated over the entire display area (AA) on the substrate 110. The light-emitting layer 93 can be extended only up to the upper surface of the bank 97 in the non-display area (NDA). Therefore, the first low potential wiring 801 and the third low potential wiring 803 do not contact the light-emitting layer 93.

[0158] An electronic functional layer 95' is laminated on the light-emitting layer 93. The electronic functional layer 95' can be disposed over the entire display area (AA) and extending into the non-display area (NDA) so as to cover both the first low-potential wiring 801 and the third low-potential wiring 803. Meanwhile, the electronic functional layer 95' covering the first low-potential wiring 801 in the second area 1102 is patterned to form a second low-potential contact hole (CT2) exposing a part of the first low-potential wiring 801. However, in the second area 1102, the third low-potential wiring 803 has a structure covered with the electronic functional layer 95'. A cathode electrode 95 is laminated on the electronic functional layer 95'. The cathode electrode 95 contacts the first low-potential wiring 801 in the second area 1102 but does not contact the third low-potential wiring 803.

[0159] In the fifth embodiment, the electronic functional layer 95' is used to prevent the first low potential wiring 801 and the cathode electrode 95 from contacting each other in the second region 1102 and the third low potential wiring 803 and the cathode electrode 95 from contacting each other in the first region 1101. However, the present invention is not limited to this. A separate insulating film instead of the electronic functional layer may be further disposed in the non-display area (NDA) to cover the first low potential wiring 801 and the third low potential wiring 803, and then the first low potential contact hole (CT1) and the second low potential contact hole (CT2) may be formed.

[0160] As a result, at the bottom side of the first region 1101, a current path is formed from the cathode electrode 95 through the second low potential wiring 802 to the low potential terminal 81. On the other hand, at the top side of the first region 1101, a current path is formed from the cathode electrode 95 through the third low potential wiring 803 and the second auxiliary wiring 834 to the low potential terminal 81 of the second region 1102.

[0161] In a similar manner, in the lower side portion of the second region 1102, a current path is formed from the cathode electrode 95 through the second low potential wiring 802 to the low potential terminal 81. On the other hand, in the upper side portion of the second region 1102, a current path is formed from the cathode electrode 95 through the first low potential wiring 801, and through the first auxiliary wiring 832 to the low potential terminal 81 of the first region 1101.

[0162] That is, the low potential voltage via the cathode electrode 95 is advantageously evenly distributed to the low potential terminal 81 arranged in the first region 1101 and the low potential terminal 81 arranged in the second region 1102. Therefore, the phenomenon in which current is concentrated in a specific low potential terminal 81 can be prevented.

[0163] As described above, in some embodiments of the present application, the high potential wiring connecting the driving current wiring 70 is not shown in the drawings and is not specifically described. As an example, a high potential wiring can be further arranged between the low potential wiring 80 arranged on the upper and lower sides in FIG. 4 and the display area (AA). The high potential wiring can be arranged in parallel with the low potential wiring 80. On the other hand, in terms of the cross-sectional structure, it is preferable that the high potential wiring is arranged in a layer different from the low potential wiring 80. As an example, when the low potential wiring 80 is arranged in the same layer as the light shielding layer 75, the high potential wiring can be arranged in the same layer as the source electrodes 15, 25, and the drain electrodes 17, 27. As another example, an additional layer different from the light shielding layer 75, the source electrodes 15, 25, and the drain electrodes 17, 27 can be further formed.

[0164] The features, structures, effects, etc. described in the above-mentioned examples of the present application are included in at least one example of the present application and are not necessarily limited to only one example. Furthermore, the features, structures, effects, etc. exemplified in at least one example of the present application can be combined or modified in other examples by a person having ordinary knowledge in the field to which the present application belongs. Therefore, the contents related to such combinations and modifications should be interpreted as being included in the scope of the present application.

[0165] Although the embodiments of the present application have been described in detail above with reference to the accompanying drawings, the present specification is not necessarily limited to these embodiments, and various modifications can be made within the scope of the technical idea of ​​the present application. Therefore, the embodiments disclosed in the present application are for illustration purposes, not for limiting the technical idea of ​​the present application, and the scope of the technical idea of ​​the present invention is not limited by such embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not limiting. The scope of protection of this application should be interpreted according to the claims, and all technical ideas within the scope equivalent thereto should be interpreted as being included in the scope of the present invention. [Explanation of symbols]

[0166] 110 Substrate 200 Drive unit 300 Pad section

Claims

1. a substrate including a display area and a non-display area surrounding the display area; a low potential wiring including a first low potential wiring arranged on an upper side of the substrate and a second low potential wiring arranged on a lower side of the substrate; a pad portion disposed outside the second low potential wiring; a first region defined on a right side of the substrate and a second region defined on a left side of the substrate; a plurality of auxiliary wirings connecting the first low potential wiring and the second low potential wiring in the second region; a common electrode extending from the display area and in contact with an upper surface of the low potential wiring; a first low potential terminal disposed in correspondence with the first region of the pad portion and connected to the second low potential wiring; a second low potential terminal and a third low potential terminal that are disposed in correspondence with the second region of the pad portion and are connected to the second low potential wiring; Including, the first low potential terminal is disposed on a first side of the first region; a gate signal terminal for supplying a gate signal, the gate signal terminal being disposed on a second side of the first region opposite to the first side of the first region; Light emitting display device.

2. The light emitting display device according to claim 1 , wherein the auxiliary wirings are not arranged in the first region.

3. the second low potential terminal is disposed on a first side of the second region; The light emitting display device according to claim 1 , wherein the third low potential terminal is disposed on a second side of the second region opposite to a first side of the second region.

4. A substrate including a display area and a non-display area surrounding the display area; a low potential wiring including a first low potential wiring arranged on an upper side of the substrate and a second low potential wiring arranged on a lower side of the substrate; a pad portion disposed outside the second low potential wiring; a first region defined on a right side of the substrate and a second region defined on a left side of the substrate; a plurality of auxiliary wirings connecting the first low potential wiring and the second low potential wiring in the second region; a common electrode extending from the display area and in contact with an upper surface of the low potential wiring; a plurality of dummy auxiliary wirings connected to the first low potential wiring and not connected to the second low potential wiring in the first region; A light emitting display device comprising:

5. The light emitting display device according to claim 4 , wherein the auxiliary wirings and the dummy auxiliary wirings are arranged at equal intervals.

6. A substrate including a display area and a non-display area surrounding the display area; a low potential wiring including a first low potential wiring arranged on an upper side of the substrate and a second low potential wiring arranged on a lower side of the substrate; a pad portion disposed outside the second low potential wiring; a first region defined on a right side of the substrate and a second region defined on a left side of the substrate; a plurality of auxiliary wirings connecting the first low potential wiring and the second low potential wiring in the second region; a common electrode extending from the display area and in contact with an upper surface of the low potential wiring; an electronic functional layer interposed between the low potential wiring and the common electrode in the first region; A light emitting display device comprising:

7. Further comprising a light emitting diode disposed in the display area; The light emitting diode is An anode electrode; a light-emitting layer laminated on the anode electrode; an electronic functional layer laminated on the light-emitting layer; a common electrode laminated on the electronic functional layer; Including, The electronic functional layer comprises: In the second region, the display area is disposed across the display area; In the first region, a wiring extending from a display region is interposed between the low potential wiring and the common electrode. The light emitting display device according to claim 6 .

8. A substrate including a display area and a non-display area surrounding the display area; a low potential wiring including a first low potential wiring arranged on an upper side of the substrate and a second low potential wiring arranged on a lower side of the substrate; a pad portion disposed outside the second low potential wiring; a first region defined on a right side of the substrate and a second region defined on a left side of the substrate; a plurality of auxiliary wirings connecting the first low potential wiring and the second low potential wiring in the second region; a common electrode extending from the display area and in contact with an upper surface of the low potential wiring; a third low potential wiring disposed on the substrate outside the first low potential wiring; Including, In the first region, the auxiliary wiring is connected to the first low potential wiring; In the second region, the auxiliary wiring is connected to the third low potential wiring. Light emitting display device.

9. In the non-display area, an insulating film is further included which covers the first low potential wiring and the third low potential wiring, The insulating film is a first contact hole disposed in the first region excluding the second region and exposing a portion of the third low potential wiring; a second contact hole disposed in the second region excluding the first region and exposing a part of the first low potential wiring; The light emitting display device according to claim 8 .

10. The common electrode is connecting to the third low potential wiring through the first contact hole; 10. The light emitting display device according to claim 9, wherein the first low potential wiring is connected to the second contact hole.

11. Located in the display area, An anode electrode; a light-emitting layer laminated on the anode electrode; an electronic functional layer laminated on the light-emitting layer; a light-emitting diode including the common electrode laminated on the electronic functional layer; Further comprising: The light-emitting display device according to claim 9 , wherein the insulating film is such that the electronic functional layer extends from the display region.

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