Display device

Abstract

To provide a display device based on a micro LED, the device increasing a product yield.SOLUTION: The present invention includes: a first pixel having a first-color light emitting element connected to a first data line and independently driven; and a second pixel having a first-color light emitting element connected to a second data line adjacent to the first data line and independently driven, the first and second pixels being included in a first unit pixel.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present invention relates to displays, and in particular to scalable tiling displays. [Background technology]

[0002] Large displays can be used in various fields such as indoor and outdoor digital advertising. To meet the demand for large displays, an expandable tiling display device has been proposed. The tiling display device is configured by connecting a plurality of display modules to form a single screen, and has an advantage that a screen of a desired size can be realized by adjusting the number of connected display modules.

[0003] In a tiling display device, the display panel included in each display module can be made of micro light emitting diodes (micro LEDs) to realize low power consumption. Micro LEDs are ultra-small LEDs with a size of 100 micrometers (μm) or less, or LED chips may or may not require a wafer when manufactured. Micro LEDs have the advantage of being thinner and brighter than existing OLEDs, but because of their small size, it is difficult to mount red (R), green (G), and blue (B) LED chips on a substrate using a transfer process.

[0004] There are various transfer technologies for LED chips, but there are many transfer failures and the product yield is low. A driving method that can increase the product yield from a different perspective than transfer is required. Summary of the Invention [Problem to be solved by the invention]

[0005] Therefore, embodiments of the present invention aim to increase production yield in micro LED based display devices. [Means for solving the problem]

[0006] A display device according to an embodiment of the present invention includes a first pixel having a first color light-emitting element connected to a first data line and independently driven, and a second pixel having a first color light-emitting element connected to a second data line adjacent to the first data line and independently driven, the first pixel and the second pixel being included in a first unit pixel. Effect of the Invention

[0007] This embodiment has the following effects. In this embodiment, two LED chips are connected to each of the R, G, and B pixels to reduce yield reduction due to poor transfer of the micro LED chips. Since the G chip and the B chip have good light efficiency at low current density, two of them are driven in parallel in the G pixel and two in the B pixel, respectively. Meanwhile, since the R chip has poor light efficiency at low current density, one is independently driven (or separately driven) in the main R pixel and one in the redundancy R pixel for high current density.

[0008] The main R pixel and the redundancy R pixel are alternately driven due to the high current density, and when at least one of the main R pixel and the redundancy R pixel included in one unit pixel at a specific position is a defective pixel, at least one of the main R pixel and the redundancy R pixel included in another adjacent unit pixel is alternatively driven on, thereby compensating for the brightness loss at the specific position due to the defective pixel being turned off.

[0009] The effects of the present invention are not limited to the above examples, and more diverse effects are included within the scope of the present invention. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a schematic diagram illustrating a tiling display device according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a diagram showing a connection configuration of one display module. [Diagram 3] FIG. 1 illustrates a microLED-based display panel. [Figure 4] FIG. 1 illustrates a microLED-based display panel. [Diagram 5] 2 is a schematic equivalent circuit diagram of one pixel provided in a display panel. [Figure 6] FIG. 2 is a diagram illustrating an example of the configuration of one unit pixel. [Figure 7a] 13 is a diagram showing an example of alternate driving of a main pixel and a redundancy pixel of the same color included in one unit pixel UP. FIG. [Figure 7b] 13 is a diagram showing an example of alternate driving of a main pixel and a redundancy pixel of the same color included in one unit pixel UP. FIG. [Figure 8] 13 is a diagram showing an example of alternate driving of a main pixel and a redundancy pixel of the same color included in one unit pixel UP. FIG. [Figure 9a] FIG. 13 is a diagram illustrating alternating driving and alternative-on driving when a main pixel is a defective pixel and a redundancy pixel is a normal pixel in one unit pixel at a specific position. [Figure 9b] FIG. 13 is a diagram illustrating alternating driving and alternative-on driving when a main pixel is a defective pixel and a redundancy pixel is a normal pixel in one unit pixel at a specific position. [Figure 10a] FIG. 13 is a diagram illustrating alternating driving and alternative-ON driving when both a main pixel and a redundancy pixel are defective in one unit pixel at a specific position. [Figure 10b] FIG. 13 is a diagram illustrating alternating driving and alternative-ON driving when both a main pixel and a redundancy pixel are defective in one unit pixel at a specific position. [Figure 11] 2 is a diagram showing a configuration of a timing controller and a data driver according to an embodiment of the present invention; [Figure 12] 2 is a diagram showing a configuration of a timing controller and a data driver according to an embodiment of the present invention; [Figure 13] 2 is a diagram showing a configuration of a timing controller and a data driver according to an embodiment of the present invention; [Figure 14]2 is a diagram showing a configuration of a timing controller and a data driver according to an embodiment of the present invention; [Figure 15a] 2 is a diagram showing a configuration of a timing controller and a data driver according to an embodiment of the present invention; [Figure 15b] 2 is a diagram showing a configuration of a timing controller and a data driver according to an embodiment of the present invention; [Figure 16] 13 is a diagram illustrating a configuration of a timing controller and a data driver according to another embodiment of the present invention. [Figure 17] 13 is a diagram illustrating a configuration of a timing controller and a data driver according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] The advantages and features of the present invention, as well as the methods for achieving the same, will become apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be embodied in various different forms. However, the embodiments are provided to fully disclose the present invention and to inform those skilled in the art of the scope of the invention. The present invention is defined only by the scope of the claims.

[0012] The shapes, sizes, scales, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are merely examples, and the present invention is not limited to the matters shown in the drawings. The same components are designated by the same reference symbols throughout the specification. When "including", "having", "comprises", etc. are used in the present invention, other parts may be included unless the expression "only" is used. When an element is expressed in the singular, it includes the plural unless otherwise expressly specified.

[0013] In interpreting elements, they are to be interpreted as including a margin of error even if there is no explicit statement to the contrary.

[0014] When describing the positional relationship of two parts, for example, using words such as 'on top of', 'on the top of', 'on the bottom of', 'beside', etc., one or more other parts may be located between the two parts, unless the words 'immediately' or 'directly' are used.

[0015] Although the terms "first", "second", etc. are used to describe various components, these components are not limited to these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical concept of the present invention.

[0016] Hereinafter, the embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, if it is determined that the detailed description of the known functions and configurations related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

[0017] 1 is a schematic diagram of a tiling display device according to an embodiment of the present invention, and FIG 2 is a diagram showing a connection structure of one display module.

[0018] 1 and 2, a tiling display device 100 according to this embodiment includes a set board SET and a plurality of display modules CB. Each display module CB can also be called a cabinet, and includes a plurality of display panels PNL.

[0019] The display modules CB can be connected to each other via an interface circuit to form a large screen. The overall resolution of the large screen can be determined as the sum of the unit resolutions of the respective display modules CB. For example, if one screen is formed from eight display modules CB each having a unit resolution of 960*1080, the overall resolution of the screen can be 3840*2160.

[0020] The display modules CB may be connected to each other via a first interface circuit IF1 of a bidirectional serial communication type in order to execute a target operation corresponding to a control command signal input from the set board SET. The bidirectional first interface circuit IF1 may be realized as a bidirectional multichain interface of a feedback loop type between adjacent display modules CB. The bidirectional first interface circuit IF1 enables individual bidirectional serial communication between the display modules CB, so that a short communication line can be secured, and the short communication line can improve the speed and reliability of large-capacity data communication. The bidirectional first interface circuit IF1 may be realized as, but is not limited to, a dual SPI (Serial Peripheral Interface).

[0021] The first display module CB of the display module CB may be connected to the set board SET via a unidirectional or bidirectional first interface circuit IF1. If the unidirectional first interface circuit IF1 is applied, there is an advantage that the connection compatibility between the first display module CB and the set board SET is good. On the other hand, if the bidirectional first interface circuit IF1 is applied, there is an advantage that the communication speed between the first display module CB and the set board SET is increased. The unidirectional first interface circuit IF1 may be implemented as, but is not limited to, a single SPI (Serial Peripheral Interface).

[0022] The set board SET can sequentially transmit image data for implementing an input image to the display module CB via a unidirectional or bidirectional second interface circuit IF2. The second interface circuit IF2 can be implemented in a V-by-One (V×1) manner capable of high-speed and large-capacity data interfacing, but is not limited thereto.

[0023] Each display module CB can include a plurality of display panels PNL, a panel drive circuit for driving the display panels PNL, and a timing control unit TCON for controlling the operation timing of the panel drive circuit.

[0024] The display panel PNL may be implemented as a micro LED based electroluminescence display type, but is not limited thereto, and may be a light emitting element including a mini LED.

[0025] The timing control units TCON can be connected to each other via first and second interface circuits IF1 and IF2. The timing control units TCON of each display module CB are mounted on a control printed circuit board CPCB and can be connected in parallel to the panel driving circuits of the corresponding display modules CB via branch cables CBL.

[0026] The panel driving circuit may be provided independently for each of a plurality of display panels PNL constituting the same display module CB. The panel driving circuit may include a source printed circuit board SPCB connected to the timing controller TCON via a cable CBL, a memory circuit MEM mounted on the source printed circuit board SPCB, a conductive film COF electrically connecting the source printed circuit board SPCB and the display panel PNL, a data driver SIC bonded on the conductive film COF, a gate driver and a power circuit electrically connected to the source printed circuit board SPCB, etc.

[0027] The memory circuit MEM is a non-volatile memory having panel characteristics, and may be a flash memory and / or an EEPROM including a correction value for gamma setting, a first compensation value for compensating for a driving characteristic deviation / color deviation between pixels, a second compensation value for compensating for a boundary deviation between adjacent display panels PNL, and various image quality and driving control data. Here, large capacity data may be stored in the flash memory, and low capacity data may be stored in the EEPROM.

[0028] The timing controller TCON can operate the panel driving circuit according to the control command signal transmitted through the first interface circuit IF1, execute a target operation corresponding to the control command signal, and generate a control response signal including the execution result of the target operation. The target operation can include reset, mute (blackout), APL (Average Picture Level) range change, gamma change, image quality compensation value update, firmware update, etc. The target operation can further include an operation of writing and storing the control command data in a specific memory, and an operation of reading out the control execution data from the specific memory.

[0029] The timing control unit TCON can control the operation of the panel driving circuit to write the image data transferred through the first interface circuit IF1 to the display panel PNL.

[0030] 3 and 4 are diagrams illustrating a micro LED-based display panel, and Fig. 5 is a schematic equivalent circuit diagram of one pixel provided on the display panel.

[0031] 3 and 4, a pixel array for reproducing an input image is formed on each display panel PNL. A number of pixels may be arranged in the pixel array, and signal wiring for driving the pixels may be arranged. Such signal wiring may include a data line DL for supplying a data voltage Vdata to the pixels, a gate line GL for supplying a gate signal GSIG to the pixels, and a power line for supplying a power supply voltage to the pixels.

[0032] Each of the pixels may include a micro LED chip μLED chip as a light emitting element EL. The micro LED chip μLED chip may include a red chip μLED chip_R, a green chip μLED chip_G, and a blue chip μLED chip_B located on a TFT (Thin Film Transistor) backplane. The R pixel includes a red chip μLED chip_R as a light emitting element EL, the G pixel includes a green chip μLED chip_G as a light emitting element EL, and the B pixel includes a blue chip μLED chip_B as a light emitting element EL.

[0033] The micro LED chip μLED chip can be mounted on the TFT backplane by being transferred from an R / G / B donor. The red chip μLED chip_R can be transferred from the R donor, the green chip μLED chip_G can be transferred from the G donor, and the blue chip μLED chip_B can be transferred from the B donor. The transfer technique can be electrostatic force, laser, speed-dependent adhesion, load-dependent adhesion, etc. The transfer technique is not limited thereto, and magnetic assembly using electromagnetic force can also be used.

[0034] The TFT backplane can be an active matrix structure for efficient driving. On the TFT backplane, pixels can be defined by the intersection of data lines DL, gate lines GL and power lines.

[0035] A plurality of pixels may constitute a single unit pixel. For example, R (red), G (green), and B (blue) pixels adjacently arranged along the extension direction of the gate line GL or the extension direction of the data line DL may constitute a single unit pixel.

[0036] As shown in FIG. 5, one pixel PXL may include a light emitting element EL, a driving TFT DT, and a node circuit NCON.

[0037] The node circuit NCON may be connected to the gate line GL and the data line DL. The node circuit NCON receives a data voltage Vdata from the data line DL and a gate signal GSIG from the gate line GL. The node circuit NCON may set a gate-source voltage of the driving TFT DT to match a driving current generation condition by applying the data voltage Vdata to the gate electrode of the driving TFT DT in synchronization with the gate signal GSIG. The node circuit NCON may include an internal compensation circuit that senses a threshold voltage and / or an electron mobility of the driving TFT DT to compensate the gate voltage of the driving TFT DT.

[0038] The driving TFT DT is a driving element that generates a driving current corresponding to a gate-source voltage. The gate electrode of the driving TFT DT is connected to the node circuit NCON, the first electrode (drain electrode) is connected to a high-potential pixel power supply VDD, and the second electrode (source electrode) is connected to the light-emitting element EL.

[0039] The light emitting element EL is a light emitting element that emits light with an intensity corresponding to a driving current input from the driving TFT DT. The light emitting element EL may be realized as a micro light emitting diode including an inorganic light emitting layer. A first electrode of the light emitting element EL is connected to the driving TFT DT, and a second electrode of the light emitting element EL is connected to the low potential pixel power supply VSS.

[0040] The connection configuration and operation of one pixel PXL are merely examples, and the technical idea of ​​the present invention is not limited thereto. For example, the driving TFT DT and the node circuit NCON can be realized based on PMOS or NMOS. Also, there can be a plurality of gate lines GL connected to the node circuit NCON.

[0041] FIG. 6 is a diagram showing an example of the configuration of one unit pixel.

[0042] Referring to FIG. 6, in order to reduce a reduction in yield due to a transfer failure of the light emitting element EL, four pixels PRa, PRb, PG, and PB constituting one unit pixel UP in the display panel PNL may include six light emitting elements EL.

[0043] Four pixels PRa, PRb, PG, and PB constituting one unit pixel UP may be connected to different data lines DL and the same gate line GL. Six light emitting elements EL included in the four pixels PRa, PRb, PG, and PB include two R chips, two G chips, and two B chips.

[0044] The G chip and B chip have good light efficiency at low current density, so they can be driven in parallel in pairs to improve yield. On the other hand, the R chip has poor light efficiency at low current density, so it can be driven independently (or separately) in pairs to achieve high current density.

[0045] The two R chips include a main R chip and a redundant R chip. The main R chip serves as the light emitting element EL of the R1 pixel PRa, and the redundant R chip serves as the light emitting element EL of the R2 pixel PRb. The R1 pixel PRa serves as the main pixel for expressing R, and the R2 pixel PRb serves as the redundant pixel for expressing R. Even if only one of the R1 pixel PRa and the R2 pixel PRb is driven, R can be expressed in one unit pixel UP, thereby improving the yield.

[0046] The two G chips include a main G chip and a redundancy G chip, and serve as the light emitting element EL of the G pixel PG. In the G pixel PG, the two G chips are connected in parallel between the driving TFT DT and the low potential pixel power supply VSS. Even if only one of the two G chips connected in parallel is driven, the G pixel PG can still operate normally, thereby improving the yield.

[0047] The two B chips include a main B chip and a redundancy B chip, and serve as the light emitting element EL of the B pixel PB. In the B pixel PB, the two B chips are connected in parallel between the driving TFT DT and the low potential pixel power supply VSS. Even if only one of the two B chips connected in parallel is driven, the B pixel PB can operate normally, thereby improving the yield.

[0048] 7a, 7b and 8 are diagrams illustrating an example of alternate driving of a main pixel and a redundancy pixel of the same color included in one unit pixel UP, in which R pixels PRa and PRb are taken as examples.

[0049] In one unit pixel UP, the G pixel PG and the B pixel PB are continuously driven to be on, whereas the two R pixels PRa and PRb can be selectively driven to be on due to the high current density.

[0050] The R pixels PRa and PRb include a main pixel PRa and a redundancy pixel PRb. The selective on-driving method includes a first method of driving one of the main pixel PRa and the redundancy pixel PRb, which has a relatively high light efficiency, and a second method of driving the main pixel PRa and the redundancy pixel PRb alternately.

[0051] The first method is difficult to consider because it requires a precise brightness measurement process to select pixels with better light efficiency, which increases the tack time, and it must target all unit pixels, resulting in a large volume of selection map data and increasing various resources related to transmitting and processing the selection map data.

[0052] In order to solve the problems of the first method, the present embodiment proposes an alternating driving method as a second method, in which the main pixel PRa and the redundancy pixel PRb are alternately turned on at a fixed time interval.

[0053] The main pixel PRa and the redundancy pixel PRb are alternately turned on at regular intervals and alternately driven in reverse order on a pixel row basis, thereby forming a checkered pattern (or lattice pattern) on the display screen.

[0054] For example, in an odd frame, as shown in FIG. 7a, the main pixel PRa located on the odd-numbered row line and the redundancy pixel PRb located on the even-numbered row line can be driven on, and the redundancy pixel PRb located on the odd-numbered row line and the main pixel PRa located on the even-numbered row line can be driven off.

[0055] Meanwhile, in an even frame, as shown in FIG. 7b, the main pixel PRa located on the odd-numbered row line and the redundancy pixel PRb located on the even-numbered row line can be driven off, and the redundancy pixel PRb located on the odd-numbered row line and the main pixel PRa located on the even-numbered row line can be driven on.

[0056] In alternating drive, the perceived luminance is the sum of the luminance of the main pixel PRa and the redundancy pixel PRb, which are turned on / off complementarily to each other. Above a certain refresh rate (or frame frequency), screen flicker caused by alternating drive is not noticeable.

[0057] 9a and 9b are diagrams illustrating alternating driving and alternative-on driving when a main pixel PRa is a defective pixel and a redundancy pixel PRb is a normal pixel in one unit pixel at a specific position.

[0058] A defective pixel refers to a pixel that is unable to realize normal brightness and is therefore treated as a dark point (always driven off). The location of the defective pixel can be detected in advance by a brightness measurement process and stored in a defect map. Defective pixels are dark points when compared with normal pixels and are easily distinguished. Therefore, the brightness measurement process for finding the location of a defective pixel is more advantageous in terms of tack time than the brightness measurement process for pixel selection described above. Since there are not many defective pixels within one screen, the capacity of the defect map related to the location of the defective pixels is small. Therefore, when compared with the selection map data described above, the various resources related to transmitting and processing the defect map data are not large.

[0059] Since the defective pixel is always driven off, a specific color (eg, R) can be darkened in one unit pixel at a fixed time interval by alternate driving.

[0060] Figure 9a shows a case where the main pixel PRa located on the odd-numbered row line and the redundancy pixel PRb located on the even-numbered row line are driven on, and the redundancy pixel PRb located on the odd-numbered row line and the main pixel PRa located on the even-numbered row line are driven off, as in Figure 7a. And Figure 9b shows a case where the main pixel PRa located on the odd-numbered row line and the redundancy pixel PRb located on the even-numbered row line are driven off, and the redundancy pixel PRb located on the odd-numbered row line and the main pixel PRa located on the even-numbered row line are driven on, as in Figure 7b.

[0061] For example, in the first unit pixel UP1 at a specific position (Column#2, Row#2), if the main pixel PRa is a defective pixel and the redundancy pixel PRb is a normal pixel, the redundancy pixel PRb is driven to be on in the odd frames of Fig. 9a, so that the first unit pixel UP1 can express red color without darkening the R pixel in the odd frames. Also, since the main pixel PRa in the first unit pixel UP1 is driven to be off, there is no problem.

[0062] However, Figure 9b shows a case in which the main pixel PRa of the first unit pixel UP1 is driven on and the redundancy pixel PRb is driven off in an even frame. Since the main pixel PRa of the first unit pixel UP1 is a defective pixel and the redundancy pixel PRb is also driven off, the R pixels PRa and PRb of the first unit pixel UP1 become dark during an even frame.

[0063] To prevent such dark spots, in this embodiment, the R pixel adjacent to the main pixel PRa (i.e., defective pixel) of the first unit pixel UP1 is driven to be alternatively on in the even frame to compensate for the luminance loss caused by the main pixel PRa being turned off. Since the adjacent R pixel driven to be alternatively on is a pixel that should have been driven to be turned off in the even frame, no luminance distortion occurs even if this R pixel is driven to be alternatively on.

[0064] For convenience of explanation, the main pixel PRa having a defect in the first unit pixel UP1 in FIG. 9b is indicated as the first pixel P1, and the redundancy pixel PRb driven in the alternative-on mode is indicated as the second pixel P2. Additionally, adjacent R pixels driven in the alternative-on mode are indicated as the third to fifth pixels P3, P4, and P5. The third pixel P3 is the main pixel PRa of the second unit pixel UP2 adjacent to the first unit pixel UP1 on the upper side in the column direction. The fourth pixel P4 is the main pixel PRa of the third unit pixel UP3 adjacent to the first unit pixel UP1 on the lower side in the column direction. The fifth pixel P5 is the redundancy pixel PRb of the fourth unit pixel UP4 adjacent to the first unit pixel UP1 on the left side in the row direction. Meanwhile, in FIG. 9b, only the R pixels PRa and PRb are shown among the unit pixels, and the G and B pixels are omitted. The omitted G and B pixels are located in each column and can form one unit pixel together with the R pixels PRa and PRb. The G, B pixels can be the sixth and seventh pixels in the claims.

[0065] 9b, in an even frame, the first pixel P1, which is a defective pixel, is driven off, and the second pixel P2, the third pixel P3, the fourth pixel P4, and the fifth pixel P5 are driven on instead. If the first pixel P1 is a normal pixel without any defect, the second pixel P2, the third pixel P3, the fourth pixel P4, and the fifth pixel P5 are pixels that should be driven off in the even frame.

[0066] The first pixel P1 and the second pixel P2 are pixels connected to the same gate line and connected to adjacent data lines to be driven independently. The first pixel P1 can be connected to the first data line, and the second pixel P2 can be connected to the second data line. The third pixel P3 and the fourth pixel P4 can be connected to the first data line and can be located adjacent to the first pixel P1 in the column direction. The fifth pixel P5 can share a gate line with the first pixel P1 and can be located adjacent to the first pixel P1 with the G and B pixels (i.e., the sixth and seventh pixels) in between. The positions of the R, G, and B pixels are not limited thereto.

[0067] In addition, the luminance distribution ratios distributed to the pixels P2, P3, P4, and P5 driven in the alternate-on mode in the even-numbered frames may be set to be different depending on the distance from the first pixel P1. The second pixel P2 is closest to the first pixel P1, the third pixel P3 and the fourth pixel P4 are next closest, and the fifth pixel P5 is the furthest. Therefore, the luminance distribution ratio is the largest in the second pixel P2, the third pixel P3 and the fourth pixel P4 are next largest, and the fifth pixel P5 is the smallest. For example, if the luminance to be realized in the first pixel P1 is 100 nit, the second pixel P2 may be responsible for a luminance of 50 nit, the third pixel P3 and the fourth pixel P4 may be responsible for a luminance of 20 nit, and the fifth pixel P5 may be responsible for a luminance of 10 nit, by the alternate-on drive.

[0068] The temporal / spatial positions and luminance distribution ratio of pixels P2, P3, P4, and P5 that are alternate-on driven under the alternate driving condition may vary depending on the position of the defective pixel on the display panel. For this, a pixel map for alternate driving must be set in advance, and a defect map for alternate-on driving must be set in advance. Then, there must be a process of modulating image data based on the pixel map and the defect map. The operation of modulating image data for the luminance distribution ratio can be performed by a timing controller or a data driver.

[0069] The pixels P2, P3, P4, and P5 that are driven as alternate ON are pixels that should originally be driven as OFF in even frames, so they only express compensation gray levels for luminance distribution in even frames, and therefore do not cause a problem of distorting the original image due to alternate ON driving in even frames.

[0070] Figures 10a and 10b are diagrams illustrating alternate driving and alternative on driving when both the main pixel and the redundancy pixel in one unit pixel at a specific position are defective pixels. Figure 10a shows a case where the main pixel PRa located on the odd-numbered row line and the redundancy pixel PRb located on the even-numbered row line are driven on, and the redundancy pixel PRb located on the odd-numbered row line and the main pixel PRa located on the even-numbered row line are driven off, as in Figure 7a. And Figure 10b shows a case where the main pixel PRa located on the odd-numbered row line and the redundancy pixel PRb located on the even-numbered row line are driven off, and the redundancy pixel PRb located on the odd-numbered row line and the main pixel PRa located on the even-numbered row line are driven on, as in Figure 7b.

[0071] Since the defective pixel is always driven off, when both the main pixel and the redundancy pixel are defective, a specific color (eg, R) can be darkened in one unit pixel.

[0072] For example, if the main pixel PRa and the redundancy pixel PRb are both defective pixels in the first unit pixel UP1 at a specific position (Column #2, Row #2), the R pixels PRa and PRb will be successively darkened in the odd frame of FIG. 10a and the even frame of FIG. 10b.

[0073] To prevent such dark spots, in this embodiment, some R pixels of the second to fourth unit pixels UP adjacent to the redundancy pixel PRb (i.e., defective pixel) that should be driven on in odd frames are driven on instead to compensate for the luminance loss caused by turning off the redundancy pixel PRb. Since the R pixels driven on instead are pixels that should originally be driven off in odd frames, no luminance distortion due to the alternative on drive occurs in these R pixels.

[0074] For convenience of explanation, the defective main pixel PRa and the redundancy pixel PRb in the first unit pixel UP1 in FIG. 10a are indicated as the first pixel P1 and the second pixel P2, respectively. Adjacent R pixels driven in the alternative-on mode are indicated as the third to fifth pixels P3, P4, and P5. The third pixel P3 is the redundancy pixel PRb of the second unit pixel UP2 adjacent to the first unit pixel UP1 on the upper side in the column direction. The fourth pixel P4 is the redundancy pixel PRb of the third unit pixel UP3 adjacent to the first unit pixel UP1 on the lower side in the column direction. The fifth pixel P5 is the main pixel PRa of the fourth unit pixel UP4 adjacent to the first unit pixel UP1 on the right side in the row direction. Meanwhile, in FIG. 10a, only the R pixels PRa and PRb are shown among the unit pixels, and the G and B pixels are omitted. The omitted G and B pixels are located in each column and can form one unit pixel together with the R pixels PRa and PRb. The G and B pixels can be the sixth and seventh pixels in the claims.

[0075] 10a, the first and second pixels P1 and P2, which are defective pixels, are driven to be off during an odd frame, and the third pixel P3, the fourth pixel P4, and the fifth pixel P5 are driven to be alternatively on. If the second pixel P2 is a normal pixel without any defect, the third pixel P3, the fourth pixel P4, and the fifth pixel P5 are pixels that should be driven to be off during the odd frame.

[0076] The first pixel P1 and the second pixel P2 are pixels connected to the same gate line and connected to adjacent data lines to be driven independently. The first pixel P1 can be connected to the first data line, and the second pixel P2 can be connected to the second data line. The third pixel P3 and the fourth pixel P4 can be connected to the second data line and can be adjacent to the second pixel P2 in the column direction. The fifth pixel P5 can share a gate line with the second pixel P2 and be adjacent to the second pixel P2 with the G and B pixels (i.e., the sixth and seventh pixels) in between. The positions of the R, G, and B pixels are not limited thereto.

[0077] In odd-numbered frames, the luminance distribution ratios distributed to the pixels P3, P4, and P5 driven in the alternate-on mode may be set to be different depending on the distance from the second pixel P2. The distance from the second pixel P2 is relatively closer for the third pixel P3 and the fourth pixel P4, and relatively farther for the fifth pixel P5. Therefore, the luminance distribution ratios are relatively larger for the third pixel P3 and the fourth pixel P4, and relatively smaller for the fifth pixel P5. For example, if the luminance to be realized in the second pixel P2 is 100 nit, the third pixel P3 and the fourth pixel P4 may each be responsible for a luminance of 40 nit, and the fifth pixel P5 may be responsible for a luminance of 20 nit, by the alternate-on drive.

[0078] 10b, in this embodiment, the R pixel adjacent to the main pixel PRa (i.e., the defective pixel) is alternately driven on in an even frame to compensate for the luminance loss caused by the main pixel PRa being turned off. Since the adjacent R pixel that is alternately driven on is a pixel that should have been originally driven off in an even frame, no luminance distortion due to alternate on driving occurs in this R pixel.

[0079] For convenience of explanation, the defective main pixel PRa and the redundancy pixel PRb in the first unit pixel UP1 in FIG. 10b are indicated as the first pixel P1 and the second pixel P2, respectively. Adjacent R pixels driven in the alternative-on mode are indicated as the third to fifth pixels P3, P4, and P5. The third pixel P3 is the main pixel PRa of the second unit pixel UP2 adjacent to the first unit pixel UP1 on the upper side in the column direction. The fourth pixel P4 is the main pixel PRa of the third unit pixel UP3 adjacent to the first unit pixel UP1 on the lower side in the column direction. The fifth pixel P5 is the redundancy pixel PRb of the fourth unit pixel UP4 adjacent to the first unit pixel UP1 on the left side in the row direction. Meanwhile, in FIG. 10b, only the R pixels PRa and PRb are shown among the unit pixels, and the G and B pixels are omitted. The omitted G and B pixels are located in each column and can form one unit pixel together with the R pixels PRa and PRb. The G, B pixels can be the sixth and seventh pixels in the claims.

[0080] 10b, the first and second pixels P1 and P2, which are defective pixels, are driven to be off during an even frame, and the third pixel P3, the fourth pixel P4, and the fifth pixel P5 are driven to be alternatively on. If the first pixel P1 is a normal pixel without any defect, the third pixel P3, the fourth pixel P4, and the fifth pixel P5 are pixels that should be driven to be off during an even frame.

[0081] The first pixel P1 and the second pixel P2 are pixels connected to the same gate line and connected to adjacent data lines to be driven independently. The first pixel P1 can be connected to the first data line, and the second pixel P2 can be connected to the second data line. The third pixel P3 and the fourth pixel P4 can be connected to the first data line and can be located adjacent to the first pixel P1 in the column direction. The fifth pixel P5 can share a gate line with the first pixel P1 and can be located adjacent to the first pixel P1 with the G and B pixels (i.e., the sixth and seventh pixels) in between. The positions of the R, G, and B pixels are not limited thereto.

[0082] In even-numbered frames, the luminance distribution ratios distributed to the pixels P3, P4, and P5 driven in the alternate-on mode may be set to be different depending on the distance from the first pixel P1. The distance from the first pixel P1 is relatively closer for the third pixel P3 and the fourth pixel P4, and relatively farther for the fifth pixel P5. Therefore, the luminance distribution ratios are relatively larger for the third pixel P3 and the fourth pixel P4, and relatively smaller for the fifth pixel P5. For example, if the luminance to be realized in the second pixel P2 is 100 nit, the third pixel P3 and the fourth pixel P4 may each be responsible for a luminance of 40 nit, and the fifth pixel P5 may be responsible for a luminance of 20 nit, by the alternate-on drive.

[0083] Under such an alternating driving condition, the temporal / spatial positions and luminance distribution ratio of pixels P3, P4, and P5 driven as alternate-on may vary depending on the position of the defective pixel on the display panel. For this, a pixel map for the alternate driving must be preset, and a defect map for the alternate-on driving must be preset. Then, there must be a process of modulating image data based on the pixel map and the defect map. The operation of modulating image data for the luminance distribution ratio may be performed by a timing controller or a data driver.

[0084] Meanwhile, the pixels P3, P4, and P5 driven as alternate ON in Fig. 10a are pixels that should originally be driven as OFF in odd frames, so they only express compensation gray levels for luminance distribution in odd frames, and therefore do not cause a problem of distortion of the original image due to alternate ON driving in odd frames.

[0085] In addition, the pixels P3, P4, and P5 in Fig. 10b that are alternately driven on are pixels that should originally be driven off in even frames, so they only express compensation gray levels for luminance distribution in even frames, and therefore do not cause a problem of distortion of the original image due to alternate on driving in even frames.

[0086] 11 to 15b are diagrams illustrating configurations of a timing controller and a data driver according to an embodiment of the present invention.

[0087] 11 to 15b, a modulation operation of image data based on a luminance allocation ratio can be performed by the timing controller TCON.

[0088] The timing control unit TCON may include an image processing unit, a memory, a map generating circuit, a pixel selector, a defect selector, and an output circuit.

[0089] The image processor converts the image data that has undergone various image quality compensation processes into an R, G, B serial system (e.g., R 10 bits, G 10 bits, B 10 bits), and generates line count information (CNT) and frame count information (CNT) corresponding to the R, G, B image data.

[0090] The memory stores position coordinate information of defective pixels obtained by a brightness measurement process based on a camera or the like, where the defective pixels are pixels of a particular color (e.g., R).

[0091] The map generation circuit generates a pixel map as shown in Figure 12 based on line / frame count information (CNT) input from the image processor. The pixel map is used to match R image data with R pixels for alternate driving. The map generation circuit generates a defect map as shown in Figure 13 by referring to position coordinate information of defective pixels stored in memory. The defect map indicates the positions of defective pixels.

[0092] The pixel selector converts the R, G, B image data into Ra, Rb, G, B image data (Ra 10 bits, Rb 10 bits, G 10 bits, B 10 bits) for alternate driving based on the pixel map.

[0093] The defect selector modulates the Ra, Rb, G, B image data based on the defect map into Ra', Rb', G, B image data (Ra' 10 bits, Rb' 10 bits, G 10 bits, B 10 bits) capable of alternative on-drive.

[0094] For this purpose, the defect selector may include a multiplexer MUX, a defect analyzer, a lookup table LUT, and a data modulation circuit, as shown in FIG. 14. The multiplexer MUX selectively outputs Ra and Rb based on the pixel map. The defect analyzer sets a defect priority for determining a luminance distribution ratio of a pixel adjacent to a defective pixel based on the defect map. The closer the distance between the defective pixel and the pixel, the higher the defect priority, and the lower the defect priority. The lookup table LUT stores luminance distribution ratio information according to the defect priority in advance. The data modulation circuit modulates the Ra and Rb image data to Ra' and Rb', which reflect the luminance distribution ratio of the lookup table. Meanwhile, FIG. 15a and FIG. 15b show pixel maps and defect maps according to the alternating and alternate driving of FIG. 9a and FIG. 9b.

[0095] The output circuit outputs 40-bit Ra', Rb', G, B image data to the data driver SIC via the internal interface circuit.

[0096] The digital / analog converter DAC of the data driver SIC converts the Ra', Rb', G, B image data into gamma compensation voltages to generate Ra', Rb', G, B data voltages. The digital / analog converter DAC supplies the Ra', Rb', G, B data voltages to the main pixel PRa, the redundancy pixel PRb, the G pixel PG, and the B pixel PB via the data lines DL.

[0097] 16 and 17 are diagrams showing the configuration of a timing controller and a data driver according to another embodiment of the present invention. Compared with FIG. 11, FIG. 16 has an advantage in that the amount of data transmission between the timing controller TCON and the data driver SIC is reduced.

[0098] 16 and 17, a modulation operation of image data based on a luminance distribution ratio can be performed in the data driver SIC.

[0099] The timing control unit TCON may include a video processing unit, a memory, a map generating circuit, and an output circuit.

[0100] The image processor converts the image data that has undergone various image quality compensation processes into an R, G, B serial system (e.g., R 10 bits, G 10 bits, B 10 bits), and generates line count information (CNT) and frame count information (CNT) corresponding to the R, G, B image data.

[0101] The memory stores position coordinate information of defective pixels obtained by a luminance measurement process using a camera or the like, where the defective pixels are pixels of a particular color (e.g., R).

[0102] The map generation circuit generates a pixel map (2 bits) as shown in Figure 12 based on line / frame count information (CNT) input from the image processor. The pixel map is used to match R image data with R pixels for alternate driving. The map generation circuit generates a defect map (2 bits) as shown in Figure 13 by referring to position coordinate information of defective pixels stored in memory. The defect map indicates the positions of defective pixels.

[0103] The output circuit outputs 30-bit R, G, B image data and 2-bit defect map to the data driver SIC via the internal interface circuit. The data area of ​​the transmission data packet output to the data driver SIC via the internal interface circuit can include 32-bit information including the R, G, B image data and the defect map as shown in Fig. 17. In this case, since the 2-bit pixel map is common to Ra and Rb, it can be included in the control area of ​​the transmission data packet and transmitted.

[0104] The data driver SIC may include a pixel selector, a defect selector, a digital-to-analog converter DAC, and the like.

[0105] The operations of the pixel selector, the defect selector and the digital-to-analog converter DAC are substantially similar to those described with reference to FIG.

[0106] From the above description, a person skilled in the art may make various changes and modifications within the scope of the technical concept of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims. [Explanation of symbols]

[0107] PRa Main Pixel PRb Redundancy Pixel P3, P4, P5 Alternate On Drive Pixels

Claims

1. a first pixel having a red micro light emitting diode connected to a first data line; a second pixel having the red micro light emitting diode connected to a second data line adjacent to the first data line; a sixth pixel including a first green micro light emitting diode and a second green micro light emitting diode connected to a third data line adjacent to the second data line and driven in parallel; a seventh pixel including a blue first micro light emitting diode and a blue second micro light emitting diode connected to a fourth data line adjacent to the third data line and driven in parallel; the first pixel, the second pixel, the sixth pixel, and the seventh pixel are included in a first unit pixel; If the first pixel and the second pixel are both normal pixels, In an odd frame, the first pixel is driven off and the second pixel is driven on; In an even frame following the odd frame, the first pixel is driven on and the second pixel is driven off.

2. If the first pixel is a defective pixel and the second pixel is a normal pixel, 2. The micro light-emitting diode display device of claim 1, wherein in the even frames, the first pixel is driven off and the second pixel is driven alternately on.

3. In the even frame, a third pixel and a fourth pixel adjacent to the first pixel and connected to the first data line are alternately driven to be on; Each of the third pixel and the fourth pixel has an independently driven red micro light emitting diode; The third pixel is included in a second unit pixel adjacent to the first unit pixel on an upper side in a column direction, The micro light-emitting diode display device according to claim 2 , wherein the fourth pixel is included in a third unit pixel adjacent to the first unit pixel on a lower side in the column direction.

4. In the even frame, a fifth pixel that shares a gate line with the first pixel and is adjacent to the first pixel is alternately driven to be on; The fifth pixel has the red micro light emitting diode that is independently driven; The micro light-emitting diode display device according to claim 3 , wherein the fifth pixel is included in a fourth unit pixel adjacent to the first unit pixel on the left side in a row direction.

5. The micro light-emitting diode display device of claim 4, wherein in the even frame, a luminance to be realized by the first pixel is respectively allocated to the second pixel, the third pixel, the fourth pixel, and the fifth pixel which are alternately driven on in the even frame.

6. 6. The micro light-emitting diode display device according to claim 5, wherein the luminance distribution ratios allocated to the second pixel, the third pixel, the fourth pixel, and the fifth pixel that are alternately turned on in the even frames are set to be larger as their distance from the first pixel decreases.

7. The micro light-emitting diode display device according to claim 6 , wherein the luminance distribution ratio is the largest in the second pixel, the next largest in the third pixel and the fourth pixel, and the smallest in the fifth pixel.

8. If the first pixel and the second pixel are both defective pixels, In the odd-numbered frame, the first pixel and the second pixel are both driven to be off, and a third pixel and a fourth pixel adjacent to the second pixel and connected to the second data line are driven to be alternatively on; Each of the third pixel and the fourth pixel has an independently driven red micro light emitting diode; The third pixel is included in a second unit pixel adjacent to the first unit pixel on an upper side in a column direction, The micro light-emitting diode display device according to claim 1 , wherein the fourth pixel is included in a third unit pixel adjacent to the first unit pixel on a lower side in the column direction.

9. In the odd-numbered frame, a fifth pixel that shares a gate line with the first pixel and the second pixel and is adjacent to the second pixel is alternately driven to be on; The fifth pixel has the red micro light emitting diode that is independently driven; The micro light-emitting diode display device according to claim 8 , wherein the fifth pixel is included in a fourth unit pixel adjacent to the first unit pixel on the left side in a row direction.

10. The micro light-emitting diode display device of claim 9, wherein in the odd frames, the luminance to be realized by the second pixel is respectively allocated to the third pixel, the fourth pixel, and the fifth pixel which are alternately driven on in the odd frames.

11. The micro light-emitting diode display device of claim 10, wherein in the odd frame, the luminance distribution ratios allocated to the third pixel, the fourth pixel, and the fifth pixel that are alternatively driven on are set to be larger as their distance from the second pixel decreases.

12. The micro light-emitting diode display device of claim 11 , wherein the luminance distribution ratio is relatively large in the third pixel and the fourth pixel, and relatively small in the fifth pixel.

13. If the first pixel and the second pixel are both defective pixels, In the even-numbered frame, the first pixel and the second pixel are both driven to be off, and a third pixel and a fourth pixel adjacent to the first pixel and connected to the first data line are driven to be alternatively on; Each of the third pixel and the fourth pixel has an independently driven red micro light emitting diode; The third pixel is included in a second unit pixel adjacent to the first unit pixel on an upper side in a column direction, The micro light-emitting diode display device according to claim 1 , wherein the fourth pixel is included in a third unit pixel adjacent to the first unit pixel on a lower side in the column direction.

14. In the even frame, a fifth pixel that shares a gate line with the first pixel and the second pixel and is adjacent to the first pixel is alternately driven to be on; The fifth pixel has the red micro light emitting diode that is independently driven; The micro light-emitting diode display device according to claim 13 , wherein the fifth pixel is included in a fourth unit pixel adjacent to the first unit pixel on the left side in the row direction.

15. The micro light-emitting diode display device of claim 14, wherein in the even frames, the luminance to be realized by the first pixel is respectively allocated to the third pixel, the fourth pixel, and the fifth pixel which are alternately driven on in the even frames.

16. The micro light-emitting diode display device of claim 15, wherein in the even frame, the luminance distribution ratios allocated to the third pixel, the fourth pixel, and the fifth pixel that are alternately driven on are set to be larger as their distance from the first pixel decreases.

17. 17. The micro light-emitting diode display device of claim 16, wherein the luminance distribution ratio is relatively large in the third pixel and the fourth pixel, and relatively small in the fifth pixel.

Images