Display device

Abstract

To provide a display device which suppresses the deterioration of the light emitting brightness of a pixel circuit.SOLUTION: A display device 1 includes: a plurality of pixel circuits 10 arranged along a first direction d1 and a second direction d2 intersecting with the first direction d1; and a plurality of voltage supply lines Vs1, Vs2 which are connected to the plurality of pixel circuits 10, respectively, to supply voltages to the plurality of pixel circuits 10. Each of the plurality of pixel circuits 10 includes a plurality of sub-pixel circuits 11R, 11G, 11B which include light-emitting devices ELR, ELG, ELB and transistors (for example, drive transistors TDR, TDG, TDB) driven to make the light-emitting devices ELR, ELG, ELB emit light. The plurality of sub-pixel circuits, 11R, 11G, 11B are arranged in each pixel circuit 10 along the first direction d1. The plurality of voltage supply lines Vs1, Vs2 extend along the first direction d1 and are arranged with intervals in the second direction d2.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] The present disclosure relates to a display device including a plurality of pixel circuits. [Background technology]

[0002] Active matrix display devices using organic EL (Electro-Luminescence) elements have been put to practical use (see, for example, Patent Document 1). The display device is configured by arranging a plurality of pixel circuits in a matrix, each of which is made up of three sub-pixel circuits equipped with light-emitting elements that emit light of red (R), green (G), and blue (B). The display device displays color images by controlling the emission brightness of each sub-pixel circuit. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2007-73499 A Summary of the Invention [Problem to be solved by the invention]

[0004] In display devices, a voltage supply line for supplying an auxiliary voltage is sometimes provided to suppress a voltage drop in the voltage supplied to the pixel circuits. However, the thickness of the auxiliary voltage supply line creates a step in the EL layer constituting the light-emitting element, which causes a problem of a decrease in the light emission brightness of the pixel circuit.

[0005] In view of the above, an object of the present disclosure is to provide a display device that suppresses a decrease in the emission luminance of a pixel circuit. [Means for solving the problem]

[0006] In order to achieve the above object, a display device according to one embodiment disclosed herein includes a plurality of pixel circuits arranged along a first direction and a second direction intersecting the first direction, and a plurality of voltage supply lines connected to each of the plurality of pixel circuits and supplying a voltage to the plurality of pixel circuits, each of the plurality of pixel circuits including a plurality of sub-pixel circuits each having a light-emitting element and a transistor for driving the light-emitting element to emit light, the plurality of sub-pixel circuits being arranged along the first direction within the pixel circuit, the plurality of voltage supply lines including a first voltage supply line and a second voltage supply line different from the first voltage supply line, the first voltage supply line being connected to an anode of the light-emitting element via the transistor, and the second voltage supply line being connected to a cathode of the light-emitting element, the first voltage supply line and the second voltage supply line extending along the first direction, Without the light emitting element in between They are arranged side by side and spaced apart in the second direction. Effect of the Invention

[0007] According to the display device according to the present disclosure, it is possible to suppress a decrease in the emission luminance of the pixel circuit. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram showing a functional configuration of a display device of Comparative Example 1. [Diagram 2] 1 is a plan view illustrating a pixel circuit included in a display device of Comparative Example 1. FIG. [Diagram 3] 4 is a diagram showing a cross section and luminance distribution of a portion of a pixel circuit of Comparative Example 1. FIG. [Figure 4] 11 is a plan view illustrating a pixel circuit included in a display device of Comparative Example 2. FIG. [Diagram 5] 13 is a diagram showing the lifetime of a subpixel circuit of a display device of Comparative Example 2. FIG. [Figure 6] 1 is a block diagram showing a functional configuration of a display device according to a first embodiment. [Figure 7] 2 is a circuit diagram of a pixel circuit included in the display device according to the first embodiment. FIG. [Figure 8] FIG. 2 is a plan view illustrating a pixel circuit according to the first embodiment. [Figure 9] 2 is a diagram illustrating a cross section of a portion of the pixel circuit according to the first embodiment. FIG. [Figure 10] 4 is a diagram showing wiring at an end portion of the display panel according to the first embodiment. FIG. [Figure 11] FIG. 11 is a diagram showing pixel circuits and gate driver wiring of a display device according to a modified example of the first embodiment. [Figure 12] 4 is a timing chart showing a method of driving the pixel circuit according to the first embodiment. [Figure 13] 4 is a timing chart showing a method of driving the display device according to the first embodiment. [Figure 14] FIG. 11 is a block diagram showing a functional configuration of a display device according to a second embodiment. [Figure 15] FIG. 11 is a circuit diagram of a pixel circuit included in a display device according to a second embodiment. [Figure 16] FIG. 11 is a plan view illustrating a pixel circuit according to a second embodiment. [Figure 17] FIG. 11 is a plan view illustrating a display panel of a display device according to a third embodiment. [Figure 18] FIG. 13 is a plan view illustrating a display panel of a display device according to a modified example of the third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] (Background to this disclosure) The process leading to the present disclosure will be described with reference to comparative examples shown in FIGS.

[0010] 1 is a block diagram showing the functional configuration of a display device 9 of Comparative Example 1. In the following description, for simplicity, a signal and a wiring that transmits the signal may be referred to by the same reference numeral, a voltage and a wiring that supplies the voltage may be referred to by the same reference numeral, and a circuit and an area in which the circuit is formed may be referred to by the same reference numeral.

[0011] As shown in FIG. 1, the display device 9 of Comparative Example 1 includes a display panel 92, a gate driver 93, a data driver 95, a controller 96, and a power supply 97.

[0012] The display panel 92 has a plurality of pixel circuits 90 arranged in a matrix. The plurality of pixel circuits 90 are arranged along a first direction d1 and a second direction d2 perpendicular to the first direction d1. Each pixel circuit 90 is composed of three sub-pixel circuits 91R, 91G, and 91B corresponding to the emitted colors of R, G, and B, respectively. In Comparative Example 1, the first direction d1 is the horizontal direction of the screen, and the second direction d2 is the vertical direction of the screen.

[0013] The display panel 92 is provided with an initialization signal line INI, a reference signal line REF, and a write signal line WS connected to the pixel circuits 90. The display panel 92 also has three data signal lines Vdat R , Vdat G , Vdat B will be established.

[0014] The controller 96 receives a video signal from the outside, and supplies control signals to the gate driver 93 and the data driver 95 for displaying an image of each frame of the video signal on the display panel 92 .

[0015] The power supply 97 supplies voltages to the display panel 92, the gate driver 93, the data driver 95, and the controller 96. The display panel 92 is supplied with an initialization voltage VINI, a reference voltage VREF, a positive power supply voltage VCC, and a negative power supply voltage VCATH from the power supply 97.

[0016] FIG. 2 is a plan view illustrating a pixel circuit 90 included in a display device 9 of the first comparative example.

[0017] 2, the sub-pixel circuits 91R, 91G, and 91B are arranged along a first direction d1 in the pixel circuit 90. The sub-pixel circuits 91R, 91G, and 91B are arranged in a first direction d1 in the pixel circuit 90. R , E.L.G , E.L. B , drive transistor TD R , T.D. G , T.D. B , and the storage capacity CS R , C.S. G , C.S. B etc.

[0018] A positive power supply voltage line VCC is connected to each of the sub-pixel circuits 91R, 91G, and 91B of the pixel circuit 90. Each of the positive power supply voltage lines VCC connected to each of the sub-pixel circuits 91R, 91G, and 91B extends along the second direction d2. In addition, the pixel circuit 90 includes a light-emitting element EL R , E.L. G , E.L. B A positive power supply voltage VCC and a negative power supply voltage VCATH are supplied to the positive power supply voltage line VCC. Note that Fig. 2 also shows a voltage relay line VCCr along the second direction d2. The voltage relay line VCCr is connected to the positive power supply voltage line VCC.

[0019] In the pixel circuit 90, the sub-pixel circuits 91R, 91G, and 91B are laid out at a high density, and the positive power supply voltage line VCC cannot have a wide wiring width, so the wiring resistance is likely to be high. In addition, the negative power supply voltage line VCATH is made of a planar transparent electrode, so the resistance is likely to be high due to restrictions on materials and film thickness. In other words, in the pixel circuit 90, the wiring resistance of the power supply wiring is high, so a voltage drop is likely to occur in the power supply wiring.

[0020] Therefore, in the display device 9, in order to suppress a voltage drop due to the wiring resistance of the pixel circuit 90, a plurality of voltage supply lines Vs91, Vs92 are provided to supply voltages for supplementing the positive power supply voltage VCC and the negative power supply voltage VCATH. The voltage supply lines Vs91, Vs92 connected to the sub-pixel circuit 91R are provided along the second direction d2 so as to overlap the region of the sub-pixel circuit 91R. The voltage supply lines Vs91, Vs92 connected to the sub-pixel circuit 91G are provided along the second direction d2 so as to overlap the region of the sub-pixel circuit 91G. The voltage supply lines Vs91, Vs92 connected to the sub-pixel circuit 91B are provided along the second direction d2 so as to overlap the region of the sub-pixel circuit 91B. However, in this display device 9, by providing the voltage supply lines Vs91, Vs92, a step is formed at the location where the voltage supply lines Vs91, Vs92 are provided.

[0021] Fig. 3 is a diagram showing a cross section and luminance distribution of a portion of a pixel circuit 90 of Comparative Example 1. Fig. 3(a) shows the luminance distribution of the pixel circuit 90, and Fig. 3(b) shows a cross section of the pixel circuit 90 taken along line III-III shown in Fig. 2.

[0022] As shown in (b) of FIG. 3, in the pixel circuit 90, an insulating layer 65 is formed on a TFT (Thin Film Transistor) layer 51 on a substrate 50, and voltage supply lines Vs91 and Vs92 having a predetermined thickness are formed on the insulating layer 65. Then, an insulating layer 66 is formed on the insulating layer 65 so as to cover the voltage supply lines Vs91 and Vs92, and an EL layer 53 consisting of an anode layer 54, a light-emitting layer 55 and a cathode layer 56 is formed on the insulating layer 66. In the display device 9 having such a laminated structure, a flat region and a step region are formed in the EL layer 53. Therefore, as shown in (a) of FIG. 3, the emission luminance in the step region is lower than the emission luminance in the flat region, and there is a problem that the average emission luminance of the pixel circuit 90 is reduced.

[0023] In order to solve this problem, it is conceivable that the number of auxiliary voltage supply lines Vs91 and Vs92 may be reduced to suppress the decrease in light emission luminance.

[0024] Fig. 4 is a plan view illustrating a pixel circuit 90a included in a display device 9a of Comparative Example 2. Fig. 5 is a diagram illustrating the lifetimes of sub-pixel circuits 91R, 91G, and 91B of the display device 9a of Comparative Example 2.

[0025] 4, in this pixel circuit 90a, the auxiliary voltage supply lines Vs91 and Vs92 are provided so as to overlap only the sub-pixel circuit 91R. Therefore, in Comparative Example 2, the number of voltage supply lines Vs91 and Vs92 is two, which is fewer than that in Comparative Example 1. This makes it possible to suppress a decrease in the average emission luminance of the pixel circuit 90.

[0026] However, when the voltage supply lines Vs91 and Vs92 are provided only in the region of the sub-pixel circuit 91R as in Comparative Example 2, the emission luminance of the sub-pixel circuit 91R is lower than that of the other sub-pixel circuits 91G and 91B. If the pixel current flowing through the sub-pixel circuit 91R is increased to compensate for the decrease in the emission luminance of the sub-pixel circuit 91R, the life of the sub-pixel circuit 91R becomes shorter than that of the other sub-pixel circuits 91G and 91B, as shown in Fig. 5. This results in a problem of a shorter life of the display device 9a.

[0027] In response to this, the display device of the present disclosure has the following configuration in order to suppress a decrease in the light emission luminance of the pixel circuit.

[0028] Hereinafter, the embodiments of the present disclosure will be described with reference to the drawings. Note that each of the embodiments described below shows a specific example of the present disclosure. Therefore, the numerical values, shapes, materials, components, the arrangement and connection of the components, steps, and the order of steps shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Therefore, among the components in the following embodiments, components that are not described in the independent claims showing the highest concept in the present disclosure will be described as optional components.

[0029] In addition, each figure is a schematic diagram and is not necessarily precisely illustrated. Therefore, the scales and the like are not necessarily the same in each figure. In addition, in each figure, the same reference numerals are given to substantially the same configurations, and duplicated explanations are omitted or simplified.

[0030] In this specification, the terms "upper" and "lower" do not refer to the upper direction (vertically upward) and lower direction (vertically downward) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in a stacked configuration. The terms "upper" and "lower" are applied not only to the case where two components are arranged in contact with each other, but also to the case where two components are arranged with a gap between them and another component is present between the two components.

[0031] (Embodiment 1) [1-1. Display device configuration] A display device 1 according to the first embodiment will be described.

[0032] 6 is a block diagram showing a functional configuration of the display device 1 according to the first embodiment. In the following description, for simplicity, a signal and a wiring that transmits the signal may be referred to by the same reference numeral, a voltage and a wiring that supplies the voltage may be referred to by the same reference numeral. Also, a circuit and an area in which the circuit is formed may be referred to by the same reference numeral.

[0033] As shown in FIG. 6, the display device 1 according to the first embodiment includes a display panel 12, a gate driver 13, a data driver 15, a controller 16, and a power supply 17.

[0034] The display panel 12 has a plurality of pixel circuits 10 arranged in a matrix. The plurality of pixel circuits 10 are arranged along a first direction d1 and a second direction d2 intersecting the first direction d1. The first direction d1 and the second direction d2 are perpendicular to each other. In this embodiment, the first direction d1 is the vertical direction of the screen, and the second direction d2 is the horizontal direction of the screen.

[0035] Each pixel circuit 10 has three sub-pixel circuits 11R, 11G, and 11B that respectively correspond to the emitted light colors of R, G, and B. Each of the sub-pixel circuits 11R, 11G, and 11B includes an organic EL light-emitting element EL R , E.L. G , E.L. B and a light-emitting element EL R , E.L. G , E.L. B The light emitting device has a plurality of transistors which are driven to emit light.

[0036] The sub-pixel circuits 11R, 11G, and 11B are arranged along a first direction d1 in the pixel circuit 10. That is, the sub-pixel circuits 11R, 11G, and 11B are arranged along the vertical direction of the screen of the display panel 12 formed by the multiple pixel circuits 10.

[0037] The display panel 12 is provided with an initialization signal line INI, a reference signal line REF, and a write signal line WS, which are connected to the pixel circuit 10. The initialization signal line INI, the reference signal line REF, and the write signal line WS transmit the initialization signal INI, the reference signal REF, and the write signal WS, which are supplied from the gate driver 13, to the pixel circuit 10, respectively.

[0038] The display panel 12 is provided with data signal lines Vdat connected to each pixel circuit 10. The data signal lines Vdat transmit data signals Vdat related to the emission luminance of R, G, and B supplied from a data driver 15 to the pixel circuits 10, respectively.

[0039] The controller 16 receives a video signal from an external source, and supplies control signals to the gate driver 13 and the data driver 15 for displaying an image of each frame of the video signal on the display panel 12 .

[0040] The power supply 17 supplies voltages to the display panel 12, the gate driver 13, the data driver 15, and the controller 16. The display panel 12 is supplied with an initialization voltage VINI, a reference voltage VREF, a positive power supply voltage VCC, and a negative power supply voltage VCATH from the power supply 17.

[0041] Fig. 7 is a circuit diagram of a pixel circuit 10 included in the display device 1. Note that a first voltage supply line Vs1 and a second voltage supply line Vs2, which will be described later, are omitted from Fig. 7.

[0042] 7, the sub-pixel circuits 11R, 11G, and 11B constituting the pixel circuit 10 have the same configuration. Hereinafter, the configuration of the pixel circuit 10 will be described with focus on the sub-pixel circuit 11R.

[0043] The sub-pixel circuit 11R includes an initialization transistor T1 R , voltage compensation transistor T2 R , write transistor T3 R , drive transistor TD R , retention capacity CS R , light-emitting element EL R It has.

[0044] Initialization transistor T1 R is turned on in response to the initialization signal INI, and the driving transistor TD R The source node of the voltage compensation transistor T2 is set to the initialization voltage VINI. R is turned on according to the reference signal REF, and the driving transistor TD R The gate node of the write transistor T3 is set to the reference voltage VREF. R is turned on in response to the write signal WS, and the voltage of the data signal Vdat is applied to the storage capacitance CS R The driving transistor TD R is the storage capacity CS R In response to the voltage held on the R This causes the light-emitting element EL R emits light with a luminance according to the voltage of the data signal Vdat.

[0045] The sub-pixel circuits 11G and 11B are configured in the same manner as the sub-pixel circuit 11R. Therefore, in the sub-pixel circuits 11G and 11B as well, the data signal Vdat is held in accordance with the initialization signal INI, the reference signal REF, and the write signal WS, and the light-emitting element EL has a luminance according to the voltage of the held data signal. G , E.L. B will emit light.

[0046] FIG. 8 is a plan view illustrating a schematic configuration of the pixel circuit 10. As shown in FIG.

[0047] 8, the initialization signal line INI, the reference signal line REF, and the write signal line WS connected to the pixel circuit 10 extend along the second direction d2. The initialization signal line INI, the reference signal line REF, and the write signal line WS are provided for each of the sub-pixel circuits 11R, 11G, and 11B.

[0048] The data signal line Vdat, the reference voltage line VREF, and the initialization voltage line VINI connected to the pixel circuit 10 extend along a first direction d1. The data signal line Vdat, the reference voltage line VREF, and the initialization voltage line VINI are provided for each pixel circuit 10, not for each sub-pixel circuit 11R, 11G, and 11B.

[0049] The display device 1 has a plurality of first voltage supply lines Vs1 and a plurality of second voltage supply lines Vs2 that supply voltages to a plurality of pixel circuits 10. Each of the first voltage supply line Vs1 and the second voltage supply line Vs2 is connected to each of the plurality of pixel circuits 10. Note that in FIG. 8, the first voltage supply line Vs1 and the second voltage supply line Vs2 are shown without hatching. Hereinafter, the first voltage supply line Vs1 may be referred to as the voltage supply line Vs1, and the second voltage supply line Vs2 may be referred to as the voltage supply line Vs2.

[0050] The pixel circuit 10 includes a light-emitting element EL R , E.L. G , E.L. BIn the present embodiment, the positive power supply voltage VCC is supplied using a single voltage supply line Vs1. R , E.L. G , E.L. B A negative power supply voltage VCATH, which is a voltage for emitting light, is supplied by the cathode layer 56 described later, but in this embodiment, a voltage for supplementing this negative power supply voltage VCATH is supplied using a single voltage supply line Vs2.

[0051] The voltage supply line Vs1 is connected to the drive transistor TD R Light emitting element EL R is connected to the anode of the drive transistor TD R Light emitting element EL R The voltage supply line Vs1 supplies a voltage to the driving transistor TD G Light emitting element EL G is connected to the anode of the drive transistor TD G Light emitting element EL G The voltage supply line Vs1 supplies a voltage to the driving transistor TD B Light emitting element EL B is connected to the anode of the drive transistor TD B Light emitting element EL B 8 supplies a voltage to the driving transistors TD R , T.D. G , T.D. B and each drive transistor TD R , T.D. G , T.D. B The power supply supplies voltage to the

[0052] The voltage supply line Vs2 is connected to the light-emitting element EL R The cathode of the light-emitting element EL R The voltage supply line Vs2 supplies a voltage to the light-emitting element EL G The cathode of the light-emitting element EL GThe voltage supply line Vs2 supplies a voltage to the light-emitting element EL B The cathode of the light-emitting element EL B Supply voltage to.

[0053] Each of the voltage supply lines Vs1, Vs2 extends along the first direction d1, which is the screen vertical direction. That is, the voltage supply lines Vs1, Vs2 are provided along the arrangement direction of the sub-pixel circuits 11R, 11G, and 11B in the pixel circuit 10. The multiple voltage supply lines Vs1, Vs2 are arranged side by side at intervals in the second direction d2. The total number of voltage supply lines Vs1, Vs2 in the pixel circuit 10 is two, which is fewer than the number (six) of voltage supply lines Vs91, Vs92 in Comparative Example 1.

[0054] Furthermore, when viewed from a direction perpendicular to both the first direction d1 and the second direction d2 (when the screen is viewed in plan), the voltage supply lines Vs1 and Vs2 evenly overlap the regions of the sub-pixel circuits 11R, 11G, and 11B. This allows the step regions formed by the voltage supply lines Vs1 and Vs2 to be evenly provided in the regions of the sub-pixel circuits 11R, 11G, and 11B.

[0055] Here, we will explain the step region formed in the pixel circuit 10. Note that the step region is a region between a high flat region and a low flat region.

[0056] 9 is a schematic cross-sectional view of a portion of the pixel circuit 10. In FIG. 9, a cross-sectional view taken along line IX-IX of the pixel circuit 10 shown in FIG.

[0057] The display panel 12 is an organic EL display panel having a top emission structure. In the pixel circuit 10 of the display panel 12, a TFT layer 51 constituting a transistor is formed on a substrate 50, an insulating layer 65 serving as an interlayer insulating layer is formed above the TFT layer 51, and a light-emitting element EL is formed above the insulating layer 65. R , E.L. G , E.L. BIn addition, a protective film, a sealing resin, and a sealing substrate (not shown) may be laminated in this order on the EL layer 53.

[0058] The substrate 50 is a flat base, for example, a glass substrate or a glass film.

[0059] The TFT layer 51 includes a semiconductor layer L0, a first wiring layer L1 constituting a gate electrode 71, a second wiring layer L2 constituting a drain electrode 72 and a source electrode 73, insulating layers 61, 62, 63 and 64, and the like.

[0060] For example, the insulating layer 61 is provided so as to cover the surface of the substrate 50. On the insulating layer 61, a semiconductor layer L0 having a channel region 76, a drain semiconductor 77, and a source semiconductor 78 is formed. Then, an insulating layer 62 is formed on the insulating layer 61 so as to cover this semiconductor layer L0, and further, an insulating layer 63 is formed on the insulating layer 62. A first wiring layer L1 constituting the gate electrode 71 is formed inside the insulating layer 63 so as to be located above the channel region 76. On the insulating layer 63, a second wiring layer L2 constituting the drain electrode 72 and the source electrode 73 is formed. The drain electrode 72 is connected to the drain semiconductor 77 through one via conductor, and the source electrode 73 is connected to the source semiconductor 78 through the other via conductor. Then, an insulating layer 64 is formed so as to cover the second wiring layer L2 and the insulating layer 63.

[0061] An insulating layer 65, which is an interlayer insulating layer, is provided so as to cover the entire surface of the insulating layer 64. The voltage supply lines Vs1 and Vs2 are provided on the insulating layer 65 and are covered with an insulating layer 66.

[0062] The EL layer 53 is provided on the insulating layer 66. The EL layer 53 is a light-emitting element EL R , E.L. G , E.L. B anode layer 54 that constitutes the anode of the light-emitting element EL; a light-emitting layer 55 that emits light when a predetermined voltage is applied thereto; R , E.L. G , E.L.B The anode layer 54 is formed by laminating the cathode layer 56 constituting the cathode of each light-emitting element EL in this order. R , E.L. G , E.L. B The cathode layer 56 constitutes a negative power supply voltage line VCATH that is a single transparent planar electrode that is connected throughout the entire display panel 92.

[0063] 9, the voltage supply lines Vs1 and Vs2 are provided between the TFT layer 51 and the EL layer 53. Specifically, the voltage supply lines Vs1 and Vs2 are provided with respect to the EL layer 53 via the insulating layer 66 on the side opposite to the light emission side of the light emitting layer 55. In this manner, in the pixel circuit 10, the insulating layer 66 and the EL layer 53 are provided on the voltage supply lines Vs1 and Vs2 having a predetermined thickness, thereby forming a flat region and a step region in the EL layer 53.

[0064] This step region leads to a decrease in the emission luminance of the pixel circuit 10, but in the present embodiment, the number of voltage supply lines Vs1 and Vs2 is smaller than in Comparative Example 1, and therefore the area of ​​the step region is smaller. Therefore, in the present embodiment, it is possible to suppress the decrease in emission luminance more than in Comparative Example 1.

[0065] In addition, in the display device 1, the voltage supply lines Vs1 and Vs2 extend in the first direction d1 and are arranged so as to evenly overlap the regions of the sub-pixel circuits 11R, 11G, and 11B arranged in the first direction d1. Therefore, step regions are evenly formed in the regions of the sub-pixel circuits 11R, 11G, and 11B. This makes it possible to suppress variations in the emission luminance of the sub-pixel circuits 11R, 11G, and 11B.

[0066] In the display device 1 of the present embodiment, each voltage supply line Vs1 is connected to a driving transistor TD R , T.D. G , T.D. B Therefore, the light-emitting element EL R , E.L. G , E.L. BThe wiring path for the voltage supplied to the display device 9a in Comparative Example 2 can be made shorter than the wiring path in the display device 9a in Comparative Example 2. This makes it possible to suppress the voltage drop due to wiring resistance, and thus to suppress the decrease in luminance.

[0067] Moreover, in the display device 1 of the present embodiment, the distance between the display panel 12 and the data driver 15 can be shortened, allowing the display device 1 to be made smaller.

[0068] Fig. 10 is a diagram showing wiring at an end portion of the display panel 12 of the embodiment 1. Fig. 10(a) shows the wiring at the end portion of the display panel 12 of the embodiment 1, and Fig. 10(b) shows the wiring at the end portion of the display panel 92 of the comparative example 2.

[0069] 10(a), a plurality of relay wirings 85 are provided on one side of a frame region that is an end of the display panel 12. The relay wirings 85 are wirings that connect the data signal lines Vdat, the initialization voltage lines VINI, and the reference voltage lines VREF of the display panel 12 to the data driver 15 and the power supply 17. In the second direction d2, the data signal lines Vdat, the initialization voltage lines VINI, and the reference voltage lines VREF are arranged in an area wider than the width of the data driver 15 or the power supply 17, and therefore each relay wiring 85 is drawn obliquely from the data driver 15 or the power supply 17 toward the data signal lines Vdat, the initialization voltage lines VINI, and the reference voltage lines VREF.

[0070] For example, in the case of a display panel 92 of Comparative Example 2 shown in FIG. 10(b), a data driver 95, a power supply 97, and three data signal lines Vdat R , Vdat G , Vdat B and three positive power supply voltage lines VCC, six relay wirings 85 are required. Since the six relay wirings 85 are drawn out at an angle, the distance (length in the first direction d1) between the ends of the display panel 92 becomes long in Comparative Example 2.

[0071] 10(a), only three relay wirings 85 are required to connect the data driver 15 to the data signal line Vdat, the initialization voltage line VINI, and the reference voltage line VREF. Therefore, in the embodiment, the distance between the ends of the display panel 12 (the length in the first direction d1) can be made shorter than in Comparative Example 2. This allows the display device 1 to be made smaller.

[0072] [1-2. Modifications of the first embodiment] A description will be given of a display device 1 according to a modification of the embodiment 1. In this modification, an example will be described in which some of the wiring connecting the pixel circuits 10 and the gate driver 13 of the display device 1 is shared.

[0073] FIG. 11 is a diagram showing wiring of the pixel circuits 10 and the gate driver 13 of the display device 1 according to a modified example.

[0074] 11, the pixel circuit 10 of the modified example is connected to the gate driver 13 via three initialization signal lines INI connected to the pixel circuit 10 and one common initialization signal line INIc connected to the three initialization signal lines INI. The common initialization signal line INIc is a common wiring formed by bundling the three initialization signal lines INI. The gate driver 13 uses the common initialization signal line INIc and the initialization signal line INI to simultaneously transmit the initialization signal INI to each of the sub-pixel circuits 11R, 11G, and 11B.

[0075] Furthermore, the pixel circuit 10 of the modified example is connected to the gate driver 13 via three reference signal lines REF connected to the pixel circuit 10 and one common reference signal line REFc connected to the three reference signal lines REF. The common reference signal line REFc is a common wiring that bundles the three reference signal lines REF. The gate driver 13 uses the common reference signal line REFc and the reference signal line REF to simultaneously transmit the reference signal REF to each of the sub-pixel circuits 11R, 11G, and 11B.

[0076] In the display device 1 of the embodiment, the number of initialization signal lines INI and reference signal lines REF is greater than in the display device 9 of the comparative example 1, and the number of outputs of the gate driver 13 is increased. However, in the display device 1 according to the modification, some of the wiring is shared, so that the number of outputs of the gate driver 13 can be reduced compared to the embodiment. This allows the gate driver 13 to be made more compact.

[0077] [1-3. Pixel circuit and display device driving method] Next, a method of driving the pixel circuit 10 and the display device 1 will be described.

[0078] 12 is a timing chart showing a method of driving the pixel circuit 10 of the embodiment 1. In the pixel circuit 10, the following operations corresponding to the emitted light colors R, G, and B, respectively, are performed.

[0079] First, during the off period, the driving transistor TD R , T.D. G , T.D. B Then, the reference voltage VREF is supplied to the gate node of the driving transistor TD R , T.D. G , T.D. B The initialization voltage VINI is supplied to the source node of the driving transistor TD R , T.D. G , T.D. B A reference voltage VREF is supplied to the gate node of the storage capacitor CS R , C.S. G , C.S. B Drive transistor TD R , T.D. G , T.D. B Next, a data signal Vdat related to the light emission luminance is written to the storage capacitor CS in response to the write signal WS. R , C.S. G , C.S. B A current corresponding to each data signal Vdat flows through the driving transistor TD R , T.D. G, T.D. B The output is from the driving transistor TD R , T.D. G , T.D. B The current output from the light-emitting element EL R , E.L. G , E.L. B As a result, each light-emitting element EL R , E.L. G , E.L. B emits light.

[0080] The off period is a period during which the subpixel circuits 11R, 11G, and 11B are not lit, and is defined as n×H, for example, where n is the number of pixel rows and H is the horizontal period.

[0081] Fig. 13 is a timing chart showing a method of driving the display device 1 according to embodiment 1. In Fig. 13, the numbers in parentheses next to the signal names indicate the rows to which the signals are supplied. As shown in Fig. 13, the pixel circuits 10 operate in row sequential order in the pixel circuits of all rows 0 to n of the display device 1.

[0082] [1-4. Effects, etc.] The display device 1 according to the present embodiment includes a plurality of pixel circuits 10 arranged along a first direction d1 and a second direction d2 intersecting the first direction d1, and a plurality of voltage supply lines connected to the pixel circuits 10 and supplying voltages to the pixel circuits 10. Each of the pixel circuits 10 includes a light-emitting element EL R , E.L. G , E.L. B and light-emitting element EL R , E.L. G , E.L. B A transistor (such as a driving transistor TD R , T.D. G , T.D. B The pixel circuit 10 has a plurality of sub-pixel circuits 11R, 11G, 11B each having a first voltage supply line and a second voltage supply line, the plurality of sub-pixel circuits 11R, 11G, 11B being arranged along a first direction d1 within the pixel circuit 10, and the plurality of voltage supply lines extending along the first direction d1 and spaced apart in the second direction d2.

[0083] In this way, by arranging the sub-pixel circuits 11R, 11G, and 11B along the first direction d1 and extending the voltage supply lines along the same first direction d1, it is possible to reduce the number of voltage supply lines compared to Comparative Example 1. This makes it possible to reduce the number of step regions caused by the voltage supply lines, and to suppress a decrease in the light emission luminance of the pixel circuit 10. In addition, by extending the voltage supply lines in the same direction as the arrangement direction of the sub-pixel circuits 11R, 11G, and 11B, it is possible to arrange the voltage supply lines in each of the sub-pixel circuits 11R, 11G, and 11B without being biased toward only one sub-pixel circuit. This makes it possible to form step regions in each of the sub-pixel circuits 11R, 11G, and 11B, and to suppress variations in the light emission luminance of the sub-pixel circuits 11R, 11G, and 11B.

[0084] The multiple voltage supply lines are at least one of multiple voltage supply lines Vs1 and multiple voltage supply lines Vs2. That is, the multiple voltage supply lines may be multiple voltage supply lines Vs1, multiple voltage supply lines Vs2, or multiple voltage supply lines Vs1 and Vs2.

[0085] Furthermore, the voltage supply line Vs1 (or Vs2) may overlap each of the multiple subpixel circuits 11R, 11G, and 11B arranged along the first direction d1 when viewed from a direction perpendicular to both the first direction d1 and the second direction d2.

[0086] In this way, the voltage supply line Vs1 (or Vs2) overlaps with each of the subpixel circuits 11R, 11G, and 11B, so that the voltage supply line Vs1 (or Vs2) can be evenly arranged in each of the regions of the subpixel circuits 11R, 11G, and 11B. This makes it possible to form evenly stepped regions in each of the regions of the subpixel circuits 11R, 11G, and 11B, and thus makes it possible to suppress variations in the emission luminance of the subpixel circuits 11R, 11G, and 11B.

[0087] The voltage supply line Vs1 is connected to a transistor (for example, a drive transistor TDR , T.D. G , T.D. B ) through the light-emitting element EL R , E.L. G , E.L. B The light-emitting element EL R , E.L. G , E.L. B A voltage may be supplied to

[0088] According to this, the light-emitting element EL R , E.L. G , E.L. B This can prevent a drop in the voltage supplied to the pixel circuit 10. As a result, a decrease in the emission luminance of the pixel circuit 10 can be prevented.

[0089] In addition, the voltage supply line Vs2 is R , E.L. G , E.L. B The cathode of the light-emitting element EL R , E.L. G , E.L. B A voltage may be supplied to

[0090] According to this, the light-emitting element EL R , E.L. G , E.L. B This can prevent a drop in the voltage supplied to the pixel circuit 10. As a result, a decrease in the emission luminance of the pixel circuit 10 can be prevented.

[0091] The plurality of voltage supply lines also includes a first voltage supply line Vs1 and a second voltage supply line Vs2 different from the first voltage supply line Vs1. The first voltage supply line Vs1 is connected to a transistor (e.g., a drive transistor TD R , T.D. G , T.D. B ) through the light-emitting element EL R , E.L. G , E.L. B The second voltage supply line Vs2 is connected to the anode of the light-emitting element EL R , E.L. G , E.L. B The cathode of the first electrode may be connected to the cathode of the second electrode.

[0092] According to this, the light-emitting element EL R , E.L. G , E.L. B This can prevent a drop in the voltage supplied to the pixel circuit 10. As a result, a decrease in the emission luminance of the pixel circuit 10 can be prevented.

[0093] In addition, the light-emitting element EL R , E.L. G , E.L. B is formed by an EL layer 53 having an anode layer 54, a light-emitting layer 55 and a cathode layer 56, and a voltage supply line Vs1 (or Vs2) may be provided on the opposite side to the light-emitting side of the light-emitting layer 55 with an insulating layer 66 interposed between the EL layer 53 and the light-emitting layer 55.

[0094] According to the display device 1 of the present embodiment, even if a step region is formed in the EL layer 53 by the above configuration, the number of voltage supply lines Vs1 (or Vs2) can be reduced compared to Comparative Example 1, and therefore the number of step regions can be reduced. This makes it possible to suppress a decrease in the emission luminance of the pixel circuit 10. Furthermore, according to this display device 1, the step region is not concentrated in one subpixel circuit, but is provided in each of the subpixel circuits 11R, 11G, and 11B, so that the variation in the emission luminance of the subpixel circuits 11R, 11G, and 11B can be suppressed compared to Comparative Example 2.

[0095] In addition, the transistor is formed by a TFT layer 51 having a semiconductor layer L0 having a channel region 76, a first wiring layer L1 constituting a gate electrode 71, and a second wiring layer L2 constituting a drain electrode 72 and a source electrode 73, and a voltage supply line Vs1 (or Vs2) may be provided between the TFT layer 51 and the EL layer 53.

[0096] According to the display device 1 of the present embodiment, even if a step region is formed in the EL layer 53 by the above configuration, the number of voltage supply lines Vs1 (or Vs2) can be reduced compared to Comparative Example 1, and therefore the number of step regions can be reduced. This makes it possible to suppress a decrease in the emission luminance of the pixel circuit 10. Furthermore, according to this display device 1, the step region is not concentrated in one subpixel circuit, but is provided in each of the subpixel circuits 11R, 11G, and 11B, so that the variation in the emission luminance of the subpixel circuits 11R, 11G, and 11B can be suppressed compared to Comparative Example 2.

[0097] The first direction d1 is the screen vertical direction of the display panel 12 formed by the plurality of pixel circuits 10, and each of the plurality of voltage supply lines extends along the screen vertical direction.

[0098] In this way, by arranging the sub-pixel circuits 11R, 11G, and 11B along the vertical direction of the screen and extending the voltage supply lines along the same vertical direction of the screen, it is possible to reduce the number of voltage supply lines arranged in the horizontal direction of the screen. This makes it possible to suppress a decrease in the emission luminance of the pixel circuit 10. Also, it is possible to suppress the variation in the emission luminance of the pixel circuit 10 in the vertical direction of the screen.

[0099] The display device 1 may further include drivers (for example, a gate driver 13 and a data driver 15) that drive and control the plurality of pixel circuits 10, and a power supply 17 that supplies voltages using a plurality of voltage supply lines.

[0100] In this way, by providing the power source 17 that supplies voltage using the voltage supply line, the light-emitting element EL R , E.L. G , E.L. B This suppresses the voltage drop supplied to the light-emitting element EL R , E.L. G , E.L. B can be appropriately illuminated.

[0101] (Embodiment 2) A display device 1a according to embodiment 2 will be described. In embodiment 2, an example will be described in which the arrangement direction of the subpixel circuits 11R, 11G, and 11B and the extension direction of the voltage supply lines Vs1 and Vs2 are different by 90° from embodiment 1. Unlike embodiment 1, in embodiment 2, the horizontal direction of the screen of the display panel 12a is called the first direction d1, and the vertical direction of the screen is called the second direction d2.

[0102] FIG. 14 is a block diagram showing a functional configuration of a display device 1a according to the second embodiment.

[0103] As shown in FIG. 14, the display device 1a according to the second embodiment includes a display panel 12a, a gate driver 13, a data driver 15, a controller 16, and a power supply 17.

[0104] The display panel 12a has a plurality of pixel circuits 10a arranged in a matrix. The pixel circuits 10a are arranged along a first direction d1 and a second direction d2 that intersects with the first direction d1. The first direction d1 and the second direction d2 are perpendicular to each other.

[0105] Each pixel circuit 10a has three sub-pixel circuits 11R, 11G, and 11B that respectively correspond to the emitted light colors of R, G, and B. Each of the sub-pixel circuits 11R, 11G, and 11B includes an organic EL light-emitting element EL R , E.L. G , E.L. B and a light-emitting element EL R , E.L. G , E.L. B The light emitting device has a plurality of transistors which are driven to emit light.

[0106] The sub-pixel circuits 11R, 11G, and 11B are arranged along a first direction d1 in the pixel circuit 10a. The sub-pixel circuits 11R, 11G, and 11B in the second embodiment are arranged along the horizontal direction of a screen of a display panel 12a formed by the multiple pixel circuits 10a.

[0107] The display panel 12a is provided with an initialization signal line INI, a reference signal line REF, and a write signal line WS, which are connected to the pixel circuit 10a. The initialization signal line INI, the reference signal line REF, and the write signal line WS transmit the initialization signal INI, the reference signal REF, and the write signal WS, which are supplied from the gate driver 13, to the pixel circuit 10a, respectively.

[0108] The display panel 12a includes a data signal line Vdat R , Vdat G , Vdat B The data signal line Vdat R , Vdat G , Vdat B is a data signal Vdat related to the light emission luminance of R, G, and B supplied from the data driver 15. R , Vdat G , Vdat B to the pixel circuit 10a, respectively.

[0109] The controller 16 receives a video signal from the outside, and supplies the gate driver 13 and the data driver 15 with control signals for displaying an image of each frame of the video signal on the display panel 12a.

[0110] The power supply 17 supplies voltages to the display panel 12a, the gate driver 13, the data driver 15, and the controller 16. The power supply 17 supplies an initialization voltage VINI, a reference voltage VREF, a positive power supply voltage VCC, and a negative power supply voltage VCATH to the display panel 12a.

[0111] 15 is a circuit diagram of a pixel circuit 10a included in the display device 1a. The power source 17 may be disposed to the side of the display panel 12a (in the first direction d1).

[0112] 15, the sub-pixel circuits 11R, 11G, and 11B constituting the pixel circuit 10a have the same configuration as each other. Hereinafter, the configuration of the pixel circuit 10a will be described with focus on the sub-pixel circuit 11R.

[0113] The sub-pixel circuit 11R includes an initialization transistor T1 R , voltage compensation transistor T2 R , write transistor T3 R , drive transistor TD R , retention capacity CS R , light-emitting element EL R It has.

[0114] Initialization transistor T1 R is turned on in response to the initialization signal INI, and the driving transistor TD R The source node of the voltage compensation transistor T2 is set to the initialization voltage VINI. R is turned on according to the reference signal REF, and the driving transistor TD R The gate node of the write transistor T3 is set to the reference voltage VREF. R is turned on according to the write signal WS, and the data signal Vdat R The voltage of the storage capacitance CS R The driving transistor TD R is the storage capacity CS R In response to the voltage held on the R This causes the light-emitting element EL R is the data signal Vdat R It emits light with a brightness that corresponds to the voltage.

[0115] The sub-pixel circuits 11G and 11B are configured in the same manner as the sub-pixel circuit 11R. Therefore, the sub-pixel circuits 11G and 11B also output the data signal Vdat at the same timing in accordance with the initialization signal INI, the reference signal REF, and the write signal WS. G , Vdat B The light-emitting element EL has a brightness according to the voltage of the held data signal. G , E.L. B will emit light.

[0116] FIG. 16 is a plan view illustrating a schematic configuration of the pixel circuit 10a.

[0117] As shown in FIG. 16, the data signal line Vdat R , Vdat G , Vdat B Each of these extends along the second direction d2.

[0118] The initialization signal line INI, the reference signal line REF, and the write signal line WS connected to the pixel circuit 10a each extend along the first direction d1. The reference voltage line VREF and the initialization voltage line VINI connected to the pixel circuit 10a extend along the first direction d1. The voltage relay line VCCr (not shown in FIG. 16) may extend along the first direction d1.

[0119] The display device 1a has a plurality of first voltage supply lines Vs1 and a plurality of second voltage supply lines Vs2 that supply voltages to the plurality of pixel circuits 10a. Each of the first voltage supply lines Vs1 and the second voltage supply lines Vs2 is connected to each of the plurality of pixel circuits 10a. In FIG. 16, the first voltage supply lines Vs1 and the second voltage supply lines Vs2 are shown without hatching.

[0120] The pixel circuit 10a is supplied with voltages for causing the light emitting elements ELR, ELG, and ELB to emit light. Supply Positive supply voltage line VCC extends along the first direction d1. In the second embodiment, a voltage for supplementing the positive power supply voltage VCC is further supplied using one voltage supply line Vs1. The voltage supply line Vs1 is connected to the positive power supply voltage VCC through a via. In addition, a negative power supply voltage VCATH, which is a voltage for causing the light-emitting elements ELR, ELG, and ELB to emit light, is supplied to the pixel circuit 10a by the cathode layer 56, but in the second embodiment, a voltage for supplementing this negative power supply voltage VCATH is supplied using one voltage supply line Vs2.

[0121] The voltage supply line Vs1 and the positive power supply voltage line VCC of the sub-pixel circuit 11R are connected to the driving transistor TD R Light emitting element EL R is connected to the anode of the drive transistor TDR Light emitting element EL R The voltage supply line Vs1 and the positive power supply voltage line VCC of the sub-pixel circuit 11G are connected to the driving transistor TD G Light emitting element EL G is connected to the anode of the drive transistor TD G Light emitting element EL G The voltage supply line Vs1 and the positive power supply voltage line VCC of the sub-pixel circuit 11B are connected to the driving transistor TD B Light emitting element EL B is connected to the anode of the drive transistor TD B Light emitting element EL B Supply voltage to.

[0122] The voltage supply line Vs2 is connected to the light-emitting element EL R The cathode of the light-emitting element EL R The voltage supply line Vs2 supplies a voltage to the light-emitting element EL G The cathode of the light-emitting element EL G The voltage supply line Vs2 supplies a voltage to the light-emitting element EL B The cathode of the light-emitting element EL B Supply voltage to.

[0123] Each of the voltage supply lines Vs1, Vs2 extends along the first direction d1, which is the horizontal direction of the screen. That is, the voltage supply lines Vs1, Vs2 are provided along the arrangement direction of the sub-pixel circuits 11R, 11G, and 11B in the pixel circuit 10a. The multiple voltage supply lines Vs1, Vs2 are arranged side by side at intervals in the second direction d2. The total number of voltage supply lines Vs1, Vs2 in the pixel circuit 10a is two, which is fewer than the number (six) of voltage supply lines Vs91, Vs92 in Comparative Example 1.

[0124] Furthermore, when viewed from a direction perpendicular to both the first direction d1 and the second direction d2, the voltage supply lines Vs1 and Vs2 evenly overlap the regions of the subpixel circuits 11R, 11G, and 11B. As a result, the step regions formed due to the voltage supply lines Vs1 and Vs2 are evenly provided in the regions of the subpixel circuits 11R, 11G, and 11B.

[0125] The display device 1a according to the second embodiment also includes a plurality of pixel circuits 10a arranged along a first direction d1 and a second direction d2 intersecting the first direction d1, and a plurality of voltage supply lines connected to the pixel circuits 10a and supplying voltages to the pixel circuits 10a. R , E.L. G , E.L. B and light-emitting element EL R , E.L. G , E.L. B The pixel circuit 10a has a plurality of sub-pixel circuits 11R, 11G, 11B each having a transistor for driving the sub-pixel circuit 11R, 11G, 11B to emit light, and the plurality of sub-pixel circuits 11R, 11G, 11B are arranged along a first direction d1 within the pixel circuit 10a, and the plurality of voltage supply lines extend along the first direction d1 and are spaced apart in the second direction d2.

[0126] In this way, by arranging the subpixel circuits 11R, 11G, and 11B along the first direction d1 and extending the voltage supply lines along the same first direction d1, it is possible to reduce the number of voltage supply lines compared to Comparative Example 1. This makes it possible to reduce the number of step regions caused by the voltage supply lines, and to suppress a decrease in the light emission luminance of the pixel circuit 10a. In addition, by extending the voltage supply lines in the same direction as the arrangement direction of the subpixel circuits 11R, 11G, and 11B, it is possible to arrange the voltage supply lines in each of the subpixel circuits 11R, 11G, and 11B without being biased toward only one subpixel circuit. This makes it possible to form step regions in each of the subpixel circuits 11R, 11G, and 11B, and to suppress variation in the light emission luminance of the subpixel circuits 11R, 11G, and 11B.

[0127] Furthermore, the first direction d1 may be the horizontal direction of a screen of a display panel 12a formed by a plurality of pixel circuits 10a, and each of the plurality of voltage supply lines may extend along the horizontal direction of the screen.

[0128] In this way, by arranging the sub-pixel circuits 11R, 11G, and 11B along the horizontal direction of the screen and extending the voltage supply lines along the same horizontal direction of the screen, it is possible to reduce the number of voltage supply lines arranged in the vertical direction of the screen. This makes it possible to suppress a decrease in the emission luminance of the pixel circuit 10a. Also, it is possible to suppress the variation in the emission luminance of the pixel circuit 10a in the horizontal direction of the screen.

[0129] (Embodiment 3) A display device 1b according to a third embodiment will be described. In the third embodiment, an example in which the subpixel circuits 11R, 11G, and 11B are arranged in a pen tile format will be described. In the third embodiment, similarly to the first embodiment, the vertical direction of the screen of the display panel 12b will be called the first direction d1, and the horizontal direction of the screen will be called the second direction d2.

[0130] Fig. 17 is a plan view that illustrates a schematic diagram of a display panel 12b of a display device 1b according to embodiment 3. In Fig. 17, a pixel line layout region is indicated by a dashed line.

[0131] 17, the display panel 12b has a plurality of pixel circuits 10b. The plurality of pixel circuits 10b are arranged along a first direction d1 and a second direction d2 intersecting the first direction d1.

[0132] Each pixel circuit 10b has sub-pixel circuits 11R, 11B, 11G, and 11G corresponding to the emission colors of R, B, G, and G, respectively. R , E.L. B , E.L. G , E.L. G and a light-emitting element EL R , E.L. B , E.L. G , E.L. GThe LED has a plurality of transistors (not shown) that are driven to emit light.

[0133] The sub-pixel circuits 11R and 11B are arranged along the first direction d1 in the pixel circuit 10b, and the sub-pixel circuits 11G and 11G are arranged along the first direction d1 in the pixel circuit 10b.

[0134] A voltage for supplementing the positive power supply voltage VCC is supplied to the pixel circuit 10b via a voltage supply line Vs1. Also, a voltage for supplementing the negative power supply voltage VCATH is supplied to the pixel circuit 10b via a voltage supply line Vs2.

[0135] Each of the voltage supply lines Vs1, Vs2 extends along the first direction d1, which is the vertical direction of the screen. Of the voltage supply lines Vs1, Vs2, the voltage supply line Vs2 is provided along the arrangement direction of the sub-pixel circuits 11R, 11B in the pixel circuit 10b. The voltage supply line Vs1 is provided along the arrangement direction of the sub-pixel circuits 11G, 11G in the pixel circuit 10b. The multiple voltage supply lines Vs2, Vs1 are arranged side by side at intervals in the second direction d2. The number of the voltage supply lines Vs2, Vs1 in the pixel circuit 10b is two, which is less than the number (six) of the voltage supply lines Vs91, Vs92 in the comparative example 1. Therefore, in the display device 1b of the third embodiment, it is possible to suppress a decrease in the emission luminance of the pixel circuit 10b compared to the display device 9 of the comparative example 1.

[0136] In addition, when viewed from a direction perpendicular to both the first direction d1 and the second direction d2, the voltage supply line Vs2 evenly overlaps the light-emitting regions of the subpixel circuits 11R and 11B, and the voltage supply line Vs1 evenly overlaps the light-emitting regions of the subpixel circuits 11G and 11G. As a result, the step regions formed due to the voltage supply lines Vs2 and Vs1 are evenly provided in the light-emitting regions of the subpixel circuits 11R and 11B or the subpixel circuits 11G and 11G. Therefore, in the display device 1b of the third embodiment, the variation in the light-emitting luminance of the subpixel circuits 11R, 11B, 11G, and 11G can be suppressed compared to the display device 9a of the second comparative example.

[0137] Next, a display device 1b according to a modification of the third embodiment will be described. In this modification, an example in which the voltage supply lines Vs2 and Vs1 are provided in a zigzag pattern will be described. FIG. 18 is a plan view that illustrates a display panel 12b of a display device 1b according to a modification of the third embodiment.

[0138] The voltage supply lines Vs2 and Vs1 of the display device 1b in this modification extend in a triangular wave shape, i.e., in a zigzag pattern, along the first direction d1, which is the screen vertical direction. The voltage supply line Vs2 is disposed in the pixel circuit 10b so as to pass between the light-emitting regions of the sub-pixel circuits 11R and 11B and the light-emitting regions of the sub-pixel circuits 11G and 11G. The voltage supply line Vs1 is disposed in the pixel circuit 10b so as to pass between the light-emitting regions of the sub-pixel circuits 11G and 11G and the light-emitting regions of the sub-pixel circuits 11R and 11B. The number of the voltage supply lines Vs2 and Vs1 in the pixel circuit 10b of the modification is two, which is less than the number (six) of the voltage supply lines Vs91 and Vs92 in the first comparative example. Therefore, in the display device 1b of the modification, it is possible to suppress a decrease in the light emission luminance of the pixel circuit 10b compared to the display device 9 of the first comparative example.

[0139] Furthermore, when viewed from a direction perpendicular to both the first direction d1 and the second direction d2 (when the screen is viewed in plan), the voltage supply lines Vs2 and Vs1 are arranged to avoid the light emitting regions of the subpixel circuits 11R, 11B, 11G, and 11G. As a result, the step regions formed due to the voltage supply lines Vs2 and Vs1 are provided at positions avoiding the light emitting regions of the subpixel circuits 11R, 11B, 11G, and 11G. Therefore, in the modified example, it is possible to further suppress a decrease in the light emission luminance of the subpixel circuits 11R, 11B, 11G, and 11G compared to the third embodiment.

[0140] (Other embodiments) Although the display devices according to the embodiments of the present disclosure have been described above, the present disclosure is not limited to the individual embodiments. As long as they do not deviate from the spirit of the present disclosure, various modifications conceived by a person skilled in the art to the present embodiments and forms constructed by combining components in different embodiments may also be included within the scope of one or more aspects of the present disclosure.

[0141] For example, in the above description, the pixel circuit 10 has been described as a so-called 4Tr1C configuration having a drive transistor, an initialization transistor, a voltage compensation transistor, a write transistor, and a storage capacitor as a display device that causes a light emitting element to emit light. However, the configuration of the pixel circuit 10 is not limited to this, and may be, for example, a so-called 2Tr1C configuration having a drive transistor circuit, a write transistor, and a storage capacitor.

[0142] Although each transistor is, for example, an N-type channel TFT element, the present invention is not limited thereto and may be a P-type channel TFT element. Also, some of the multiple transistors may be N-type channel TFT elements and the other transistors may be P-type channel TFT elements.

[0143] For example, although the gate driver 13 is arranged on one side of the display panel 12 in Fig. 6, it may be arranged on both sides. The gate driver 13 may be composed of a shift register in which flip-flop circuits are connected in multiple stages. Furthermore, the gate driver 13 may be composed of any of CMOS transistors, N-type channel transistors, and P-type channel transistors.

[0144] Furthermore, the data driver 15 may be mounted on the display panel 12 by COG (Chip on Glass) or COF (Chip on Film). [Industrial Applicability]

[0145] The present disclosure can be widely used as a display device in various image display devices such as portable information terminals, personal computers, and television receivers. [Explanation of symbols]

[0146] 1, 1a, 1b display device 10, 10a, 10b Pixel circuit 11R, 11G, 11B Sub-pixel circuit 12, 12a, 12b Display panel 13 Gate Driver 15 Data Driver 16 Controller 17 Power supply 50 Substrates 51 TFT layers 53 EL layer 54 Anode layer 55 Light-emitting layer 56 Cathode Layer 61, 62, 63, 64, 65, 66 Insulating layer 71 Gate electrode 72 Drain electrode 73 Source Electrode 76 Channel Area 77 Drain Semiconductor 78 Source Semiconductor 85 Relay wiring CS R , C.S. G , C.S. B holding capacity d1 1st direction d2 2nd direction EL R , E.L. G , E.L. B Light emitting element L0 Semiconductor layer L1 1st wiring layer L2 2nd wiring layer INI initialization signal line (initialization signal) INIc Common initialization signal line REF Reference signal line (reference signal) REFc Common reference signal line T1 R , T1 G, T1 B Initialization Transistor T2 R , T2 G , T2 B Voltage Compensation Transistor T3 R , T3 G , T3 B Write Transistor T.D. R , T.D. G , T.D. B Drive Transistor VCATH Negative power supply voltage line (negative power supply voltage) VCC Positive power supply voltage line (positive power supply voltage) VCCr Voltage relay line Vdat, Vdat R , Vdat G , Vdat B Data signal line (data signal) VINI Initialization voltage line (initialization voltage) VREF Reference voltage line (reference voltage) Vs1, Vs2 voltage supply lines WS Write signal line (write signal)

Claims

1. A plurality of pixel circuits arranged along a first direction and a second direction intersecting the first direction; a plurality of voltage supply lines connected to the plurality of pixel circuits, respectively, for supplying voltages to the plurality of pixel circuits; Equipped with Each of the plurality of pixel circuits includes a plurality of sub-pixel circuits each including a light-emitting element and a transistor for driving the light-emitting element to emit light; The plurality of sub-pixel circuits are arranged along the first direction within the pixel circuit, the plurality of voltage supply lines include a first voltage supply line and a second voltage supply line different from the first voltage supply line; the first voltage supply line is connected to an anode of the light-emitting element via the transistor; the second voltage supply line is connected to a cathode of the light-emitting element; The first voltage supply line and the second voltage supply line extend along the first direction and are arranged side by side in the second direction at an interval without the light emitting element therebetween. Display device.

2. The first voltage supply line and the second voltage supply line overlap each of the sub-pixel circuits arranged along the first direction when viewed in a direction perpendicular to both the first direction and the second direction. The display device according to claim 1 .

3. The first voltage supply line is connected to the anode of the light-emitting element via the transistor, and supplies a voltage to the light-emitting element via the transistor. The display device according to claim 1 .

4. The second voltage supply line is connected to a cathode of the light emitting element and supplies a voltage to the light emitting element. The display device according to claim 1 .

5. The light-emitting element is formed by an EL (Electro-Luminescence) layer having an anode layer, a light-emitting layer, and a cathode layer, The first voltage supply line and the second voltage supply line are provided on the opposite side of the light emitting layer from the light emitting side, with respect to the EL layer via an insulating layer. The display device according to any one of claims 1 to 4.

6. the transistor is formed by a TFT (Thin Film Transistor) layer having a semiconductor layer having a channel region, a first wiring layer constituting a gate electrode, and a second wiring layer constituting a drain electrode and a source electrode; The first voltage supply line and the second voltage supply line are provided between the TFT layer and the EL layer. The display device according to claim 5 .

7. the first direction is a screen vertical direction of a display panel formed by the plurality of pixel circuits, Each of the first voltage supply line and the second voltage supply line extends along the screen vertical direction. The display device according to any one of claims 1 to 6.

8. the first direction is a horizontal direction of a screen of a display panel formed by the plurality of pixel circuits, Each of the first voltage supply line and the second voltage supply line extends along the horizontal direction of the screen. The display device according to any one of claims 1 to 6.

9. moreover, A driver that drives and controls the plurality of pixel circuits; a power supply that supplies a voltage using the first voltage supply line and the second voltage supply line; The display device according to any one of claims 1 to 8, comprising:

Images