Display with reduced temperature and brightness sensitivity - Patents.com

Abstract

The display may include an array of pixels. Each pixel in the array may include a drive transistor, an emission transistor, a data loading transistor, a gate voltage setting transistor, an initialization transistor, an anode reset transistor, a storage capacitor, and an optional current boost capacitor. The data refresh includes an initialization phase, a threshold voltage sampling phase, and a data programming phase. The threshold voltage sampling phase may be substantially longer than the data programming phase to reduce the current sampling level during the threshold voltage sampling phase, which is useful for reducing the display luminance sensitivity to temperature variations.

Description

[Technical field]

[0001] This relates generally to electronic devices having displays, and more particularly to displays such as organic light emitting diode (OLED) displays.

[0002] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims priority to U.S. Patent Application No. 17 / 317,128, filed May 11, 2021, and U.S. Provisional Patent Application No. 63 / 156,612, filed March 4, 2021, each of which is incorporated by reference in its entirety. [Background technology]

[0003] Electronic devices often include a display. For example, mobile phones and portable computers usually include a display for presenting image content to a user. An OLED display has an array of display pixels based on light-emitting diodes. In this type of display, each display pixel includes a light-emitting diode and an associated thin-film transistor for controlling the application of a data signal that causes the light-emitting diode to emit light. Designing a satisfactory OLED display for an electronic device can be difficult. Summary of the Invention

[0004] The electronic device may include a display having an array of display pixels. The display pixels may be organic light emitting diode display pixels. Each display pixel may include at least an organic light emitting diode (OLED) for emitting light and an associated thin film transistor for controlling operation of the pixel and for assisting in reducing the temperature luminance sensitivity of the display.

[0005] According to some embodiments, a display is provided that includes a gate driver circuit and an array of pixels coupled to the gate driver circuit. At least one pixel in the array comprises a light emitting diode having an anode terminal, a drive transistor coupled in series with the light emitting diode, the drive transistor including a gate terminal, a first source-drain terminal, and a second source-drain terminal, a data loading transistor having a first source-drain terminal coupled to the gate terminal of the drive transistor, a second source-drain terminal coupled to a data line, and a gate terminal configured to receive a first scan signal from the gate driver circuit, and a gate voltage setting transistor having a first source-drain terminal coupled to the gate terminal of the drive transistor, a second source-drain terminal configured to receive a reference voltage, and a gate terminal configured to receive the second scan signal from the gate driver circuit. The gate driver circuit can be configured to assert the second scan signal during a threshold voltage sampling phase and assert the first scan signal during a data programming phase. The data programming phase can have a first duration and the threshold voltage sampling phase can have a second duration that is longer than the first duration. The second duration can be at least 5-20 times longer than the first duration.

[0006] At least one pixel may further include an anode reset transistor having a first source-drain terminal coupled to the anode terminal of the light emitting diode, a second source-drain terminal configured to receive an anode reset voltage, and a gate terminal configured to receive a third scan signal from a gate driver circuit. At least one pixel may further include an initialization transistor having a first source-drain terminal coupled to the second source-drain terminal of the drive transistor, a second source-drain terminal configured to receive an initialization voltage, and a gate terminal configured to receive the third scan signal. The gate driver circuit may be configured to assert the second scan signal and the third scan signal during the initialization phase. At least one pixel may further include a first emission transistor coupled between a positive power supply line and the first source-drain terminal of the drive transistor, and a second emission transistor coupled between the second source-drain terminal of the drive transistor and the anode terminal. The first and second emission transistors can have gate terminals configured to receive an emission signal from a gate driver circuit, the gate driver circuit being configured to assert the emission signal during the threshold voltage sampling phase. All of the transistors in the at least one pixel can be semiconductor oxide transistors.

[0007] According to some embodiments, a method of operating a display is provided. The display may include a gate driver circuit and an array of pixels, each of the pixels including at least a light emitting diode, a drive transistor, a data loading transistor, a gate voltage setting transistor, and a storage capacitor. The method may include, during a threshold voltage sampling phase, sampling a threshold voltage of the drive transistor onto the storage capacitor by asserting a second scan signal and activating the gate voltage setting transistor using the gate driver circuit, and during a data programming phase, loading data onto the storage capacitor by asserting a first scan signal and activating the data loading transistor using the gate driver circuit. The data programming phase may occur after the threshold voltage sampling phase during a data refresh operation. The threshold voltage sampling phase may have a duration at least 10-20 times longer than the duration of the data programming phase.

[0008] The method may further include resetting the anode of the light emitting diode by asserting a third scan signal with a gate driver circuit to activate the anode reset transistor during the initialization phase. The method may further include applying a bias voltage to the drive transistor by asserting a third scan signal with a gate driver circuit to activate the initialization transistor during the initialization phase. Each pixel may include one or two emission transistors. At least one of the emission transistors may be deactivated during the initialization phase and activated during the threshold voltage sampling phase.

[0009] According to some embodiments, there is provided a display pixel comprising: a light emitting diode having an anode terminal; a drive transistor coupled in series with the light emitting diode, the drive transistor having a first source-drain terminal, a second source-drain terminal, and a gate terminal; a data loading transistor having a first source-drain terminal coupled to the gate terminal of the drive transistor, a second source-drain terminal coupled to a data line, and a gate terminal configured to receive a first scan signal; a gate voltage setting transistor having a first source-drain terminal coupled to the gate terminal of the drive transistor, a second source-drain terminal configured to receive a reference voltage, and a gate terminal configured to receive a second scan signal; an emission transistor coupled in series with the light emitting diode and the drive transistor, the emission transistor having a gate terminal configured to receive the emission signal; and an anode reset transistor having a first source-drain terminal coupled to the anode terminal, a second source-drain terminal configured to receive a reset voltage, and a gate terminal configured to receive a third scan signal.

[0010] The display pixel may be operable in (1) an initialization phase in which the gate voltage setting transistor and the anode reset transistor are activated, (2) a threshold voltage sampling phase in which the gate voltage setting transistor and the emission transistor are activated, and (3) a data programming phase in which the data loading transistor is activated. The threshold voltage sampling phase may have a duration selected to mitigate the amount that luminance changes as a function of temperature (i.e., to mitigate the temperature luminance sensitivity of the display). [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 illustrates an exemplary electronic device having a display, according to some embodiments. [Diagram 2]1 is a diagram of an exemplary display having an array of organic light emitting diode (OLED) display pixels according to some embodiments. [Diagram 3] FIG. 2 illustrates a diagram showing sampling current during a threshold voltage sampling phase in accordance with some embodiments. [Figure 4] 1 is a plot showing how temperature luminance sensitivity in a display varies as a function of threshold voltage sampling duration, according to some embodiments. [Figure 5A] FIG. 2 is a circuit diagram of an exemplary display pixel operable to perform an extended threshold voltage sampling phase separate from a data programming phase in accordance with some embodiments. [Figure 5B] FIG. 5B is a timing diagram illustrating the behavior of associated control waveforms during a refresh operation of the pixel shown in FIG. 5A according to some embodiments. [Figure 5C] FIG. 5B is a timing diagram illustrating the behavior of relevant control waveforms during a vertical blanking operation of the pixel shown in FIG. 5A according to some embodiments. [Figure 6] FIG. 2 is a diagram of a low refresh rate display driving scheme according to some embodiments. [Figure 7] 4 is a circuit diagram of an exemplary display pixel having an additional current boost capacitor in accordance with some embodiments. [Figure 8A] FIG. 2 is a circuit diagram of an illustrative display pixel having a drive transistor source node that is isolated from the OLED anode during a threshold voltage sampling phase in accordance with some embodiments. [Figure 8B] FIG. 8B is a timing diagram illustrating the behavior of associated control waveforms during a refresh operation of the pixel shown in FIG. 8A according to some embodiments. [Figure 8C] FIG. 8B is a timing diagram illustrating the behavior of relevant control waveforms during a vertical blanking operation of the pixel shown in FIG. 8A according to some embodiments. [Figure 9] FIG. 2 is a circuit diagram of an illustrative display pixel having a drive transistor drain node shorted to a positive supply in accordance with some embodiments. [Figure 10] FIG. 2 is a circuit diagram of an exemplary display pixel having a drive transistor drain node shorted to a positive power supply and having a drive transistor source node driven to an initialization voltage level during an initialization phase in accordance with some embodiments. [Figure 11A] 1 is a circuit diagram of an illustrative display pixel having an anode reset transistor but lacking a separate initialization transistor in accordance with some embodiments. [Figure 11B] FIG. 11B is a timing diagram illustrating the behavior of associated control waveforms during a refresh operation of the pixel shown in FIG. 11A according to some embodiments. [Figure 11C] FIG. 11B is a timing diagram illustrating the behavior of relevant control waveforms during a vertical blanking operation of the pixel shown in FIG. 11A according to some embodiments. [Figure 12A] 1 is a circuit diagram of an exemplary display pixel having a reduced number of emission transistors in accordance with some embodiments. [Figure 12B] FIG. 12B is a timing diagram illustrating the behavior of associated control waveforms during a refresh operation of the pixel shown in FIG. 12A according to some embodiments. [Figure 12C] FIG. 12B is a timing diagram illustrating the behavior of relevant control waveforms during a vertical blanking operation of the pixel shown in FIG. 12A according to some embodiments. [Figure 13A] 1 is a circuit diagram of an exemplary display pixel having only five transistors and two capacitors in accordance with some embodiments. [Figure 13B] FIG. 13B is a timing diagram illustrating the behavior of associated control waveforms during a refresh operation of the pixel shown in FIG. 13A according to some embodiments. [Figure 14A] 1 is a circuit diagram of an exemplary display pixel having only five transistors and two capacitors in accordance with some embodiments. [Figure 14B] FIG. 13B is a timing diagram illustrating the behavior of associated control waveforms during a refresh operation of the pixel shown in FIG. 13A according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] An exemplary type of electronic device that may include a display is shown in FIG. 1. As shown in FIG. 1, electronic device 10 may have control circuitry 16. Control circuitry 16 may include storage and processing circuitry to support operation of device 10. The storage and processing circuitry may include storage devices such as hard disk drive storage, non-volatile memory (e.g., flash memory or other electrically programmable read-only memory configured to form a solid-state drive), volatile memory (e.g., static or dynamic random access memory), etc. Processing circuitry within control circuitry 16 may be used to control operation of device 10. The processing circuitry may be based on one or more microprocessors, application processors, microcontrollers, digital signal processors, baseband processors, power management units, audio chips, application specific integrated circuits, etc.

[0013] Input / output circuitry within device 10, such as input / output device 12, may be used to enable data to be provided to device 10 and to enable data to be provided from device 10 to external devices. Input / output device 12 may include buttons, joysticks, scroll wheels, touch pads, keypads, keyboards, microphones, speakers, sound sources, vibrators, cameras, sensors, light emitting diodes and other status indicators, data ports, etc. A user may control the operation of device 10 by providing commands through input / output device 12, and may receive status information and other output from device 10 using the output resources of input / output device 12.

[0014] Input / output device 12 may include one or more displays, such as display 14. Display 14 may be a touchscreen display that includes touch sensors for collecting touch input from a user, or display 14 may not be touch-sensitive. The touch sensors for display 14 may be based on an array of capacitive touch sensor electrodes, acoustic touch sensor structures, resistive touch components, force-based touch sensor structures, optically-based touch sensors, or other suitable touch sensor devices.

[0015] Control circuitry 16 may be used to execute software, such as operating system code and applications, on device 10. During operation of device 10, software executing on control circuitry 16 may display images on display 14 using an array of pixels in display 14. Device 10 may be a tablet computer, a laptop computer, a desktop computer, a display, a mobile phone, a media player, a watch device or other wearable electronic device, or other suitable electronic device.

[0016] Display 14 may be an organic light emitting diode display or a display based on other types of display technologies. An arrangement in which display 14 is an organic light emitting diode (OLED) display may be described herein as an example. However, this is merely exemplary. Any suitable type of display may be used in device 10 as desired.

[0017] Display 14 may have a rectangular shape (i.e., display 14 may have a rectangular footprint and a rectangular perimeter extending around the perimeter of the rectangular footprint) or may have any other suitable shape. Display 14 may be flat or may have a curved profile.

[0018] A top view of a portion of the display 14 is shown in Figure 2. As shown in Figure 2, the display 14 may have an array of pixels 22 formed on a substrate 36. The substrate 36 may be formed of glass, metal, plastic, ceramic, porcelain, or other substrate material. The pixels 22 may receive data signals via signal paths, such as data lines D (which may also be referred to as data signal lines, column lines, etc.), and one or more control signals via control signal paths, such as horizontal control lines G (which may also be referred to as gate lines, scan lines, emission control lines, row lines, etc.). There may be any suitable number of rows and columns of pixels 22 in the display 14 (e.g., tens or more, hundreds or more, or thousands or more).

[0019] Each pixel 22 may have a light emitting diode 26 that emits light 24 under the control of a pixel control circuit formed from thin film transistor circuitry, such as a thin film transistor 28 and a thin film capacitor. The thin film transistor 28 may be a polysilicon thin film transistor, a semiconductor oxide thin film transistor, such as an indium zinc gallium oxide transistor, or a thin film transistor formed from other semiconductors. The pixels 22 may include light emitting diodes of different colors (e.g., red, green, and blue) to provide the display 14 with the ability to display color images.

[0020] Display driver circuitry 30 may be used to control the operation of pixels 22. Display driver circuitry 30 may be formed from integrated circuits, thin film transistor circuitry, or other suitable electronic circuitry. Display driver circuitry 30 of FIG. 2 may include communication circuitry for communicating with system control circuitry, such as control circuitry 16 of FIG. 1, via paths 32. Paths 32 may be formed from traces on a flexible printed circuit or other cable. In operation, control circuitry (e.g., control circuitry 16 of FIG. 1) may provide information to circuitry 30 about an image to be displayed on display 14.

[0021] To display an image on the display pixels 22, the display driver circuit 30 may provide image data to data lines D (e.g., data lines that run down columns of pixels 22) while issuing clock signals and other control signals to auxiliary display driver circuitry, such as gate driver circuitry 34 over path 38. If desired, the display driver circuit 30 may also provide clock signals and other control signals to gate driver circuitry 34 on an opposing edge of the display 14 (e.g., gate driver circuits may be formed on more than one side of the display pixel array).

[0022] The gate driver circuit 34 (sometimes referred to as a horizontal line control circuit or row driver circuit) may be implemented as part of an integrated circuit and / or may be implemented using thin film transistor circuitry. The horizontal / row control lines G in the display 14 may carry gate line signals (scan line control signals), emission enable control signals, and / or other horizontal control signals for controlling each row of pixels. There may be any suitable number of horizontal control signals for each row of pixels 22 (e.g., one or more row control lines, two or more row control lines, three or more row control lines, four or more row control lines, five or more row control lines, etc.).

[0023] FIG. 3 is a diagram illustrating a portion of a display pixel 22. As shown in FIG. 3, the pixel 22 may include at least a drive transistor, such as a transistor Tdrive, a storage capacitor, such as a capacitor Cst, and a light-emitting diode 26. The pixel 22 may also include other transistors, such as a data loading transistor, an emission control transistor, an anode reset transistor, and an initialization transistor. The drive transistor Tdrive is configured to provide a drive current to the diode 26 and has a gate (G) terminal, a drain (D) terminal, and a source (S) terminal. The terms "source" and "drain" terminals used to describe the current conducting terminals of a transistor are sometimes interchangeable and may be referred to herein as "source-drain" terminals. A storage capacitor Cst may be coupled to the gate terminal of the transistor Tdrive and may be configured to store a data signal value for the pixel 22.

[0024] In practice, the display pixels 22 may be subject to process, voltage, and temperature (PVT) variations. Such variations may cause transistor threshold voltages to vary between different display pixels 22. Variations in the threshold voltage of the drive transistor may cause different display pixels 22 to generate amounts of light that do not match the desired image. In an effort to mitigate threshold voltage variations, a display pixel 22 of the type shown in FIG. 3 may be operable to support in-pixel threshold voltage (Vt) compensation. In-pixel threshold voltage compensation operations, also referred to as in-pixel Vt cancelling operations, may typically include at least an initialization phase, a Vt sampling phase, a data programming phase, and an emission phase (in that order). During the Vt sampling phase, the threshold voltage of the transistor Tdrive may be sampled using a storage capacitor Cst. Then, during the emission phase, the emission current flowing from the transistor Tdrive into the light emitting diode 26 has a period of time in which it is offset with the sampled Vt level. As a result, the emission current is independent of the threshold voltage Vt of the drive transistor and is therefore not affected by any Vt variations in the drive transistor. During the Vt sampling phase, a sampling current can flow through transistor Tdrive as indicated by current Isample.

[0025] The sampling current level Isample may affect the sensitivity of the display to temperature. For example, the luminance of the display may vary as a function of temperature. Such variation is defined herein as temperature-luminance sensitivity. Experiments have shown that higher sampling current levels result in higher temperature-luminance sensitivity, especially at low gray levels, and lower sampling current levels result in lower temperature-luminance sensitivity at low gray levels. Temperature-luminance sensitivity may be defined as the percentage change in display luminance for a given change in temperature. In general, it is desirable to keep the temperature-luminance sensitivity as close to zero as possible to minimize the sensitivity of the display to temperature.

[0026] According to an embodiment, the sampling current Isample can be reduced by increasing the duration of the Vt sampling phase. FIG. 4 plots a characteristic curve 50 showing how the temperature luminance sensitivity in a display varies as a function of the threshold voltage sampling duration Tsample. As shown in FIG. 4, the curve 50 approaches 0% / °C as the threshold voltage sampling time Tsample increases. In other words, increasing the Tsample duration can help reduce the sensitivity of the display to temperature. However, in conventional display pixel architectures, the Vt sampling duration is limited by the duration of the data programming period (i.e., the data programming period is usually limited to one row time set by the performance requirements of the display).

[0027] According to an embodiment, Fig. 5A is a circuit diagram of an exemplary display pixel 22 operable to reduce temperature-luminance sensitivity by separating a threshold voltage sampling phase from a data programming phase and extending the duration of the threshold voltage sampling phase to reduce temperature-luminance sensitivity. As shown in Fig. 5A, the display pixel 22 can include a light-emitting element such as an organic light-emitting diode 26, a capacitor such as a storage capacitor Cst, and thin-film transistors such as a drive transistor Tdrive, a gate voltage setting transistor Tgate, a data loading transistor Tdata, an initialization transistor Tini, an anode reset transistor Tar, and emission control transistors Tem1 and Tem2. The emission transistors Tem1 and Tem2 may be referred to as emission transistors. At least some or all of the transistors in the pixel 22 are semiconductor oxide transistors. A semiconductor oxide transistor is defined as a thin film transistor having a channel region formed from a semiconductor oxide material (e.g., indium gallium zinc oxide or IGZO, indium tin zinc oxide or ITZO, indium gallium tin zinc oxide or IGTZO, indium tin oxide or ITO, or other semiconductor oxide material) and is generally considered to be an n-type (n-channel) transistor.

[0028] Semiconductor oxide transistors are significantly different from silicon transistors (i.e., transistors having a polysilicon channel region deposited using a low temperature process, sometimes referred to as LTPS or low temperature polysilicon). Because semiconductor oxide transistors have lower leakage than silicon transistors, implementing at least a portion of the transistor within pixel 22 can help reduce flicker (e.g., by preventing current from leaking out of the gate terminal or drive transistor Tdrive).

[0029] If desired, at least some of the transistors in pixel 22 may be implemented as silicon transistors such that pixel 22 has a hybrid configuration including a combination of semiconductor oxide transistors and silicon transistors (e.g., n-type LTPS transistors or p-type LTPS transistors). In yet other suitable embodiments, pixel 22 may include additional initialization transistors for applying initialization or reference voltages to one or more internal nodes in pixel 22. As another example, display pixel 22 may further include additional switching transistors (e.g., one or more additional semiconductor oxide or silicon transistors) for applying one or more bias voltages that improve the performance or operation of pixel 22. An exemplary configuration in which pixel 22 includes only semiconductor oxide transistors and no silicon transistors may be described herein by way of example.

[0030] The drive transistor Tdrive has a gate terminal G, a drain terminal D (sometimes referred to as a first source-drain terminal), and a source terminal S (sometimes referred to as a second source-drain terminal). The transistor Tdrive, the emission control transistors Tem1 and Tem2, and the light emitting diode 26 are connected in series between a positive power supply rail 500 and a ground power supply rail 502. The light emitting diode 26 may have an associated diode capacitance Coled. The emission transistors Tem1 and Tem2 each have a gate terminal configured to receive a shared emission control signal EM. This example in which the transistors Tem1 and Tem2 receive a common emission signal is merely illustrative. In other embodiments, the transistors Tem1 and Tem2 may receive different emission control signals.

[0031] A positive power supply voltage VDDEL may be provided to the positive power supply terminal 500, and a ground power supply voltage VSSEL may be provided to the ground power supply terminal 502. The positive power supply voltage VDD may be 3V, 4V, 5V, 6V, 7V, 2-8V, greater than 6V, greater than 8V, greater than 10V, greater than 12V, 6-12V, 12-20V, or any suitable positive power supply voltage level. The ground power supply voltage VSSEL may be 0V, -1V, -2V, -3V, -4V, -5V, -6V, -7V, less than 2V, less than 1V, less than 0V, or any suitable ground or negative power supply voltage level. During the emission phase, signals EM1 and EM2 are asserted to turn on transistors Tem1 and Tem2, thereby allowing current to flow from drive transistor Tdrive to diode 26. The degree to which drive transistor Tdrive is turned on controls the amount of current that flows from terminal 500 through diode 26 to terminal 502 , thereby controlling the amount of light emitted by display pixel 22 .

[0032] In the example of FIG. 5A, the storage capacitor Cst may be coupled between the gate terminal of the drive transistor Tdrive and the anode (A) terminal of the diode 26. The data loading transistor Tdata may have a first source-drain terminal coupled to the gate terminal of the transistor Tdrive, a second source-drain terminal coupled to a data line (e.g., a column line carrying a data signal Vdata), and a gate terminal configured to receive the first scan control signal SCAN1. The transistor Tgate may have a first source-drain terminal coupled to the gate terminal of the transistor Tdrive, a second source-drain terminal coupled to a reference voltage Vref via a reference voltage line (e.g., a column line carrying a reference voltage Vref), and a gate terminal configured to receive the first scan control signal SCAN1. Thus, the transistor Tgate operable to pass the reference voltage Vref to its gate terminal to Tdrive may be referred to as a gate voltage setting transistor. The voltage Vref may be a fixed voltage level that is equal to or less than VDDEL, or some other voltage level between VSSEL and VDDEL.

[0033] The transistor Tini may have a first source-drain terminal coupled to a source terminal of Tdrive, a second source-drain terminal configured to receive an initialization voltage Vini via an initialization voltage line (e.g., a column line carrying the initialization voltage Vini), and a gate terminal configured to receive a third scan control signal SC3. The transistor Tar may have a first source-drain terminal coupled to an anode terminal (sometimes referred to as an anode electrode) of the diode 26, a second source-drain terminal configured to receive an anode reset voltage via an anode reset voltage line (e.g., a column line carrying the anode reset voltage Var), and a gate terminal configured to receive a third scan control signal SC3. The diode 26 has a cathode terminal (sometimes referred to as a cathode electrode) coupled to a VSSEL ground power line 502 (sometimes referred to as a common power line).

[0034] The voltages Var and Vini may be collectively referred to as reset voltages. Thus, the transistors Tar and Vini may be collectively referred to as reset transistors or initialization transistors. The voltages Var and Vini may be fixed voltage levels that are less than VDDEL, equal to VSSEL, or some other intermediate voltage level between VSSEL and VDDEL. If desired, the voltages Var and Vini may be adjustable voltages that change dynamically during operation of the pixel 22. In certain embodiments, the voltage Var may be equal to the voltage Vini. In other embodiments, the voltage Var may be different from the voltage Vini. Scan control signals SCAN1, SCAN2, and SCAN3 (sometimes referred to as scan signals) may be provided via row control lines (see line G in FIG. 2).

[0035] FIG. 5B is a timing diagram illustrating the operation of a display pixel 22 of the type shown in FIG. 5A. Prior to time t1, a scan signal SCAN2 may be asserted (e.g., driven high) to activate (turn on) transistor Tgate, and an emission signal EM may be deasserted (e.g., driven low) to turn off transistors Tem1 and Tem2. Activating transistor Tgate drives the gate terminal of transistor Tdrive to a reference voltage level Vref. At time t1, a scan signal SCAN3 is briefly pulsed high to turn on transistors Tini and Tar. Activating transistor Tini drives the source node of transistor Tdrive to voltage Vini, and activating transistor Tar drives the OLED anode terminal to voltage Var. Thus, while signal SCAN3 is asserted, the gate-source voltage Vgs of transistor Tdrive is biased to (Vref-Vini). This period during which the Vgs of transistor Tdrive is initialized to a known voltage difference and the anode terminal is reset to voltage Var is sometimes referred to as the initialization phase. Signal SCAN3 is deasserted at the end of the initialization phase to turn off transistors Tini and Tar.

[0036] In certain circumstances, the drive transistor threshold voltage Vt may change, such as when the display 14 is transitioning from a black image to a white image, or from one gray level to another. This Vt shift (sometimes referred to herein as thin film transistor "hysteresis") may reduce brightness and is therefore known as "first frame dimming." For example, the waveform of the saturation current Ids as a function of the Vgs of the drive transistor for a black frame may be slightly offset from the waveform of the target Ids as a function of the Vgs of the drive transistor for a white frame. To help mitigate this offset, a suitable bias voltage may be applied directly to the terminals of the drive transistor during the non-emission phase. In the example of FIG. 5A, application of a voltage Vini to the source terminal of transistor Tdrive during the initialization phase may help mitigate the hysteresis and improve the first frame response, and may be referred to as an "on-bias stress" operation.

[0037] At time t2, the emission signal EM is asserted (e.g., driven high) to turn on the transistors Tem1 and Tem2. Turning on the transistor Tem1 drives the drain terminal of the transistor Tdrive to VDDEL, which results in the source terminal of the transistor Tdrive being charged to a level that is 1 Vt lower than the Vref level at the gate of the transistor Tdrive. In other words, the source terminal of the transistor Tdrive is charged to (Vref-Vt). Because the transistor Tem2 is also turned on during this time, the OLED anode terminal is similarly charged to (Vref-Vt). Thus, during this time, the sampled voltage across the storage capacitor is equal to (Vref[Vref-Vt]), which is equal to Vt. At time t3, the emission signal EM is deasserted (e.g., driven low). This period from t2 to t3 during which Vt is sampled across the storage capacitor Cst is called the Vt sampling phase.

[0038] At time t4, the scan signal SCAN1 is pulsed high to turn on the transistor Tdata. Activating the transistor Tdata drives the gate terminal of the transistor Tdrive to a data voltage Vdata corresponding to the new data signal value of the pixel 22. Because the transistors Tem2 and Tar are both turned off at this point, the anode terminal is a high impedance node, and therefore the capacitor Cst cannot discharge (e.g., the voltage across the capacitor Cst remains equal to Vt even when the drive transistor gate terminal is driven to the new Vdata level). This period during which the transistor Tdata is activated to load the data voltage Vdata is called the data programming phase. If desired, the emission signal EM can be optionally asserted throughout the data programming phase to pass a current proportional to Vdata through the emission transistors Tem1 and Tem2 during the period from t3 to t5 (see alternative waveform 590).

[0039] At time t5, the emission signal EM is asserted to initiate the emission phase during which the diode 26 can emit an amount of light proportional to the voltage Vdata. During the emission phase, the resulting Vgs of the transistor Tdrive is equal to [Vdata-(Vref-Vt)]. Since the final emission current is proportional to Vgs-Vt, (Vgs-Vt) is equal to (Vdata-Vref+Vt-Vt), and Vt is cancelled out, so the emission current is independent of Vt. This type of operation scheme in which the drive transistor threshold voltage is internally sampled and cancelled out is sometimes called in-pixel threshold voltage compensation. The period from t1 to t5, which includes the initialization phase, the Vt sampling phase, and the data programming phase, is sometimes called the data refresh period.

[0040] To minimize the sensitivity of the display to temperature variations, the duration of the Vt sampling phase can be extended, thereby reducing the sampling current level. Decoupling the Vt sampling phase from the data programming phase allows the Vt sampling phase duration to be extended independently of the data programming phase duration, which is typically limited to one row time set by the performance requirements of the display. In some embodiments, the Vt sampling phase duration (i.e., the time period from t2 to t3) can be 10-20 times longer than the data programming phase duration (i.e., the pulse width of SCAN1). In general, the Vt sampling phase duration can be at least 2 times, 5 times, 2-5 times, 10 times, 5-10 times, 10-20 times, or more than 20 times longer than the data programming phase duration. The duration of the Vt sampling phase can also be dynamically adjusted depending on the desired degree of suppression of the display temperature luminance sensitivity. In general, a longer Vt sampling phase duration will reduce the temperature luminance sensitivity.

[0041] In some embodiments, display 14, including pixels 22, may be optionally configured to support low refresh rate operation. Operating display 14 at a relatively low refresh rate (e.g., 1 Hz, 2 Hz, 1-10 Hz, less than 30 Hz, less than 60 Hz, or other low refresh rates) may be suitable for applications that output content that is static or near static and / or require minimal power consumption.

[0042] FIG. 6 is a diagram of a low refresh rate display drive scheme. As shown in FIG. 6, the display 14 may alternate between short data refresh periods and extended vertical blanking periods. As an example, each data refresh period may be approximately 16.67 milliseconds (ms) in accordance with a 60 Hz data refresh operation, while each vertical blanking period may be approximately 1 second, lowering the overall refresh rate of the display 14 to 1 Hz. When so configured, the blanking duration j may be adjusted to adjust the overall refresh rate of the display 14. For example, if the blanking duration is adjusted to 0.5 seconds, the overall refresh rate will increase to approximately 2 Hz. In the low refresh rate drive scheme, the vertical blanking time may be (for example) at least 2 times, at least 10 times, at least 30 times, or at least 60 times longer than the data refresh time.

[0043] As shown in FIG. 5A, the light emitting diode 26 may have an associated capacitance Coled. When using the pixel 22 to output low grey levels, the emission current is relatively small, so charging the capacitance Coled may take a significant amount of time. Such low grey level blinking is typically not perceptible at high refresh rates. However, at low refresh rates, low grey level blinking may be observed due to low frequency luminance changes during each refresh period. To improve low refresh rate blinking and help reduce luminance fluctuations, it may be desirable to perform one or more anode resets during the vertical blanking period.

[0044] FIG. 5C is a timing diagram illustrating the behavior of relevant signal waveforms for controlling pixel 22 of FIG. 5A during a vertical blanking period. Before time ta, emission signal EM may be deasserted (e.g., driven low) to temporarily stop emission. After time ta, signal SCAN3 may be pulsed to temporarily activate transistors Tar and Tini. Activating transistor Tar drives the OLED anode terminal to the anode reset voltage level Var. At time tb, emission signal EM may be asserted to resume emission. The duration from time ta to tb should be equal to the active refresh period from time t1 to t5. Such an anode reset may be performed every 8 ms, 4 ms, 2 ms, or other suitable intervals during the vertical blanking period, depending on when the system is able to update data values. Performing multiple anode resets during the vertical blanking period may help mitigate flickering and brightness fluctuations at low grey levels when display 14 is operating at a low refresh rate.

[0045] The example of Figure 5A in which pixel 22 includes one capacitor Cst is merely illustrative. The drive current of pixel 22 of Figure 5A (e.g., the current through the drive transistor Tdrive during emission) is proportional to [Coled / (Cst+Coled)]. If the OLED capacitance Coled is small relative to Cst, the drive current will decay.

[0046] FIG. 7 shows another suitable embodiment of pixel 22 including an additional capacitor Cboost. As shown in FIG. 7, capacitor Cboost has a first terminal coupled to the OLED anode terminal and a second terminal coupled to a DC voltage level Vdc. Voltage Vdc can be shorted to VDDEL, VSSEL, Vref, Var, Vini, or other available / existing voltage in pixel 22. The structure and function of the remaining portion of pixel 22 in FIG. 7 is identical to that of FIG. 5A and need not be repeated for clarity. The data refresh operation of FIG. 5B and the vertical blanking anode reset operation of FIG. 5C can also be applied to pixel 22 in FIG. 7. Configured in this manner, the drive current of pixel 22 in FIG. 7 will be proportional to [(Coled+Cboost) / (Cst+Coled+Cboost)]. By appropriately sizing capacitor Cboost, the drive current decay caused by Coled can be reduced in a particular data voltage range. Capacitor Cboost therefore functions to boost the drive current level and is therefore sometimes referred to as a current boost capacitor.

[0047] The embodiment of FIG. 7 in which the emission transistors Tem1 and Tem2 are controlled by a common emission signal EM is merely exemplary. FIG. 8A shows another embodiment of the pixel 22 having emission transistors controlled by separate emission control signals. As shown in FIG. 8A, the emission transistor Tem1 has a gate configured to receive a first emission control signal EM1, while the emission transistor Tem2 has a gate configured to receive a second emission control signal EM2. By having a separate emission control signal EM2, the transistor Tem2 can be turned off during the Vt sampling phase, which electrically isolates the drive transistor source terminal from the anode terminal. Isolating or decoupling the drive transistor source terminal from the anode terminal improves the immunity of the pixel 22 to potential noise sources that may be coupled onto the VSSEL common electrode. For example, a touch sensor array that is sometimes overlaid on the display 14 can inject noise onto the VSSEL line. By turning off the transistor Tem2 during the Vt sampling and data programming phases, such type of noise injection can be rejected.

[0048] Capacitor Cst has a first terminal coupled to the gate terminal of transistor Tdrive and a second terminal coupled to the source terminal of transistor Tdrive. Capacitor Cboost has a first terminal coupled to the source terminal of transistor Tdrive and a second terminal coupled to voltage Vdc. Voltage Vdc can be shorted to VDDEL, VSSEL, Vref, Var, Vini, or other available / existing voltage in pixel 22. The structure and function of the remainder of pixel 22 of FIG. 8A is identical to that of FIG. 5A and need not be repeated for clarity. So configured, the drive current of pixel 22 of FIG. 8A is proportional to [(Cboost) / (Cst+Cboost)]. By appropriately sizing capacitor Cboost, the drive current can be made to keep its relative sign for a particular data voltage range during the data programming phase. Capacitor Cboost thus functions to boost the drive current level and is therefore sometimes referred to as a current boost capacitor.

[0049] FIG. 8B is a timing diagram illustrating the operation of a display pixel 22 of the type shown in FIG. 8A. Prior to time t1, scan signal SCAN2 may be asserted (e.g., driven high) to activate (turn on) transistor Tgate, and emission signals EM1 and EM2 may be deasserted (e.g., driven low) to turn off transistors Tem1 and Tem2. Activating transistor Tgate drives the gate terminal of transistor Tdrive to a reference voltage level Vref. At time t1, scan signal SCAN3 is briefly pulsed high to turn on transistors Tini and Tar. Activating transistor Tini drives the source node of transistor Tdrive to voltage Vini, and activating transistor Tar drives the OLED anode terminal to voltage Var. During the initialization phase, the gate-source voltage Vgs of transistor Tdrive is biased to (Vref-Vini).

[0050] At time t2, only the emission signal EM1 is asserted (e.g., driven high) to turn on transistor Tem1, while transistor Tem2 remains off. Turning on transistor Tem1 drives the drain terminal of transistor Tdrive to VDDEL, which results in the source terminal of transistor Tdrive being charged to a level that is 1 Vt lower than the Vref level at the gate of transistor Tdrive. In other words, the source terminal of transistor Tdrive is charged to (Vref-Vt) during the Vt sampling phase from time t2 to t3. Because transistor Tem2 is turned off during this time, any potential noise injected into the VSSEL and OLED anode terminals is blocked from the drive transistor source terminals.

[0051] At time t4, the scan signal SCAN1 is pulsed high to turn on the transistor Tdata. Activating the transistor Tdata drives the gate terminal of the transistor Tdrive to a data voltage Vdata corresponding to the new data signal value of the pixel 22. Because the transistors Tem2 and Tar are both turned off at this point, the anode terminal is a high impedance node, and therefore the capacitor Cst cannot discharge (e.g., the voltage across the capacitor Cst remains equal to Vt even when the drive transistor gate terminal is driven to the new Vdata level). This period during which the transistor Tdata is activated to load the data voltage Vdata is called the data programming phase. If desired, the emission signal EM1 can be optionally asserted throughout the data programming phase to allow a current proportional to Vdata to flow through at least the emission transistor Tem1 during the period from t3 to t5 (see alternative waveform 890).

[0052] At time t5, the emission signal EM is asserted to initiate the emission phase during which the diode 26 can emit an amount of light proportional to the voltage Vdata. During the emission phase, the resulting Vgs of the transistor Tdrive is equal to [Vdata-(Vref-Vt)]. Since the final emission current is proportional to Vgs-Vt, (Vgs-Vt) is equal to (Vdata-Vref Since the Vt sampling phase is equal to Vt + Vt - Vt), the emission current is independent of Vt and Vt is cancelled out to complete the intra-pixel threshold voltage cancellation operation. As discussed above in connection with FIG. 5B, the duration of the Vt sampling phase can be increased independently relative to the duration of the data programming phase (e.g., the duration of the Vt sampling phase can be at least 2 times, 5 times, 2-5 times, 10 times, 5-10 times, 10-20 times, or more than 20 times longer than the duration of the data programming phase) to minimize the temperature-luminance sensitivity of the display 14.

[0053] The pixel 22 of FIG. 8A can be used for low refresh rate displays. FIG. 8C is a timing diagram illustrating the behavior of relevant signal waveforms controlling the pixel 22 of FIG. 8A during an extended vertical blanking period of low refresh rate operation. Before time ta, the emission signals EM1 and EM2 may be deasserted (e.g., driven low) to temporarily stop emission. After time ta, the signal SCAN3 may be pulsed to temporarily activate the transistors Tar and Tini. Activating the transistor Tar drives the OLED anode terminal to the anode reset voltage level Var. At time tb, the emission signals EM1 and EM2 may be asserted to resume emission. The duration from time ta to tb should be equal to the active refresh period from time t1 to t5 (see FIG. 8B). Such anode resets may be performed every 8 ms, 4 ms, 2 ms, or other suitable intervals during the vertical blanking period, depending on when the system is able to update the data values. Performing multiple anode resets during the vertical blanking interval can help mitigate flickering and brightness fluctuations at low grey levels when display 14 is operating at low refresh rates.

[0054] The embodiment of pixel 22 in FIG. 8A, in which emission transistor Tem1 is inserted between the positive power rail and transistor Tdrive, is merely illustrative. In such a configuration, parasitic gate-drain capacitance between transistors Tdrive may unintentionally couple the data signal associated with the previous row to the drain terminal of transistor Tdrive, which is typically floating during the data programming phase. In order for this potential data to couple to the drive transistor drain terminal, the SCAN1 data loading pulse must be limited to less than one row time. Such a tight constraint on the SCAN1 pulse time may increase the design complexity of gate driver circuit 34 (FIG. 2).

[0055] To help alleviate such design constraints, the order of transistors Tem1 and Tdrive can be swapped (see, for example, FIG. 9). As shown in FIG. 9, an emission transistor Tem1 may be interposed between transistors Tdrive and Tem2. In particular, transistor Tdrive can have a drain terminal shorted to VDDEL and a source terminal coupled to emission transistor Tem1. By connecting the drain terminal of transistor Tdrive to VDDEL, the drain terminal of the drive transistor is no longer floating, and therefore there can be no potential memory of previous row data stored at that node. As a result, the pulse width of SCAN1 during the data programming phase can be longer than one row time. Allowing a wider SCAN1 pulse can help simplify the gate driver design.

[0056] Capacitor Cst has a first terminal coupled to the gate terminal of transistor Tdrive and a second terminal coupled to the source terminal of transistor Tem1. Capacitor Cboost has a first terminal coupled to the source terminal of transistor Tem1 and a second terminal coupled to voltage Vdc. Voltage Vdc can be shorted to VDDEL, VSSEL, Vref, Var, Vini, or other available / existing voltage in pixel 22. Because the positions of transistors Tdrive and Tem1 have been swapped, transistors Tem2 and Tini are directly coupled to the source terminal of transistor Tem1.

[0057] The structure and function of the remainder of pixel 22 of FIG. 9 is similar to that of FIG. 8A and need not be repeated for clarity. The data refresh operation of FIG. 8B and the vertical blanking anode reset operation of FIG. 8C can also be applied to pixel 22 of FIG. 9. Thus configured and operated, the drive current of pixel 22 of FIG. 9 will be proportional to [(Cboost) / (Cst+Cboost)]. By appropriately sizing capacitor Cboost, the drive current can be made to maintain the relative sign for a particular data voltage range during the data programming phase. Capacitor Cboost thus functions to boost the drive current level and is therefore sometimes referred to as a current boost capacitor.

[0058] In the embodiment of FIG. 9, since the transistor Tem1 is turned off during the initialization phase, the transistor Tini cannot apply the voltage Vini to the transistor Tdrive during the initialization phase. In other words, the on-bias stress operation cannot be applied to the pixel 22 of FIG. 9. FIG. 10 shows another embodiment of the pixel 22 in which the initialization transistor Tini is coupled to the source terminal of the transistor Tdrive. By directly connecting the transistor Tini to the source terminal of the transistor Tdrive, the transistor Tini can perform the on-bias stress operation during the initialization phase to mitigate hysteresis and first frame dimming. The structure and function of the remaining parts of the pixel 22 of FIG. 10 are identical to those of FIG. 9 and need not be repeated for clarity. The data refresh operation of FIG. 8B can also be applied to the pixel 22 of FIG. 10. However, during the initialization phase, the signal EM1 can remain asserted (e.g., held high) to turn on the transistor Tem1. Similarly, the vertical blanking anode reset control scheme of FIG. 8C can also be applied to the pixel 22 of FIG. 10.

[0059] The embodiment of FIG. 8A in which the pixel 22 includes both an anode reset transistor Tar coupled to the anode terminal and a separate initialization transistor Tini coupled to the transistor Tdrive is merely exemplary. FIG. 11A shows another suitable embodiment of the pixel 22 that does not include a separate initialization transistor Tini. In other words, the structure and function of the pixel 22 of FIG. 11A is the same as that of FIG. 8A, except that the pixel 22 of FIG. 11A includes one less transistor (i.e., the pixel 22 of FIG. 11A does not include the transistor Tini).

[0060] FIG. 11B is a timing diagram illustrating the operation of a display pixel 22 of the type shown in FIG. 11A. Prior to time t1, scan signal SCAN2 may be asserted (e.g., driven high) to activate (turn on) transistor Tgate, and emission signal EM1 may be deasserted (e.g., driven low) to turn off transistor Tem1. Activating transistor Tgate drives the gate terminal of transistor Tdrive to a reference voltage level Vref. At time t1, scan signal SCAN3 is pulsed high, turning on transistor Tar. Activating transistor Tar drives the OLED anode terminal to voltage Var. Because signal EM2 remains high during the initialization phase, the source terminal of transistor Tdrive is also reset to Var via transistor Tem2. Thus, during the initialization phase, the gate-source voltage Vgs of transistor Tdrive is biased to (VrefVar). Because voltage Var is also applied directly to the source terminal of transistor Tdrive during the initialization phase, voltage Var can also function to apply on-bias stress to mitigate Vt hysteresis and improve first frame response.

[0061] At time t2, only the emission signal EM1 is asserted (e.g., driven high) to turn on transistor Tem1, and transistor Tem2 is off. Turning on transistor Tem1 drives the drain terminal of transistor Tdrive to VDDEL, which results in the source terminal of transistor Tdrive being charged to a level that is 1 Vt lower than the Vref level at the gate of transistor Tdrive. In other words, the source terminal of transistor Tdrive is charged to (Vref-Vt) during the Vt sampling phase from time t2 to t3. Because transistor Tem2 is turned off during this time, any potential noise injected into the VSSEL and OLED anode terminals is blocked from the drive transistor source terminals.

[0062] At time t4, the scan signal SCAN1 is pulsed high to turn on the transistor Tdata during the data programming phase. Activating the transistor Tdata drives the gate terminal of the transistor Tdrive to a data voltage Vdata corresponding to the new data signal value of the pixel 22. Because the transistors Tem2 and Tar are both turned off at this point, the anode terminal is a high impedance node, and therefore the capacitor Cst cannot discharge (e.g., the voltage across the capacitor Cst remains equal to Vt, even when the drive transistor gate terminal is driven to the new Vdata level). If desired, the emission signal EM1 is optionally asserted throughout the data programming phase to allow a current proportional to Vdata to flow through at least the emission transistor Tem1 during the period from t3 to t5 (see alternative waveform 1190).

[0063] At time t5, the emission signal EM is asserted to initiate an emission phase during which the diode 26 can emit an amount of light proportional to the voltage Vdata. During the emission phase, the resulting Vgs of the transistor Tdrive is equal to [Vdata-(Vref-Vt)]. Since the final emission current is proportional to Vgs-Vt, (Vgs-Vt) is equal to (Vdata-Vref+Vt-Vt), so the emission current is independent of Vt and Vt is cancelled out to complete the intra-pixel threshold voltage cancellation operation. As discussed above in connection with FIG. 5B, the duration of the Vt sampling phase can be increased independently relative to the duration of the data programming phase (e.g., the duration of the Vt sampling phase can be at least 2 times, 5 times, 2-5 times, 10 times, 5-10 times, 10-20 times, or more than 20 times longer than the duration of the data programming phase) to minimize the temperature luminance sensitivity of the display 14.

[0064] The pixel 22 of FIG. 11A can be used for low refresh rate displays. FIG. 11C is a timing diagram illustrating the behavior of relevant signal waveforms controlling the pixel 22 of FIG. 11A during an extended vertical blanking period of low refresh rate operation. Before time ta, the emission signals EM1 and EM2 may be deasserted (e.g., driven low) to temporarily stop emission. After time ta, the signal SCAN3 may be pulsed to temporarily activate the transistor Tar. Activating the transistor Tar drives the OLED anode terminal to the anode reset voltage level Var. At time tb, the emission signals EM1 and EM2 may be asserted to resume emission. The duration from time ta to tb should be equal to the active refresh period from time t1 to t5 (see FIG. 11B). Such anode resets may be performed every 8 ms, 4 ms, 2 ms, or other suitable intervals during the vertical blanking period, depending on when the system is able to update the data values. Performing multiple anode resets during the vertical blanking interval can help mitigate flickering and brightness fluctuations at low grey levels when display 14 is operating at low refresh rates.

[0065] The embodiment of FIG. 8A in which the pixel 22 includes two emission transistors is merely exemplary. FIG. 12A shows another suitable embodiment of the pixel 22 including one emission transistor. In other words, the structure and function of the pixel 22 of FIG. 12A is the same as that of FIG. 8A, except that the pixel 22 of FIG. 12A includes one less emission transistor (i.e., the pixel 22 of FIG. 12A includes a single emission transistor Tern coupled between the transistor Tdrive and the diode 26, but does not include any other emission control transistor). The single emission transistor Tem has a gate configured to receive an emission signal EM.

[0066] FIG. 12B is a timing diagram illustrating the operation of a display pixel 22 of the type shown in FIG. 12A. Prior to time t1, scan signal SCAN2 may be asserted (e.g., driven high) to activate (turn on) transistor Tgate, and emission signal EM may be deasserted (e.g., driven low) to turn off transistor Tem. Activating transistor Tgate drives the gate terminal of transistor Tdrive to a reference voltage level Vref. At time t1, scan signal SCAN3 is briefly pulsed high to turn on transistors Tar and Tini. Activating transistor Tini drives the source terminal of transistor Tdrive to Vini, and activating transistor Tar drives the OLED anode terminal to voltage Var. Thus, during the initialization phase, the gate-source voltage Vgs of transistor Tdrive is biased to (Vref-Vini).

[0067] During this time, there may be a short circuit current path from VDDEL to Vini through transistors Tdrive and Tini. If Vini were carried on a row-wise routing line, such a current from every single accessed pixel along a given row would generate a significant IR drop. To help keep the IR drop to a manageable level, the initialization voltage Vini may be routed to the pixels 22 through a column-wise routing line, so that each initialization column line sees only one short circuit current path when any given row is being accessed.

[0068] From time t2 to t3, only SCAN2 remains asserted. Since the drain terminal of transistor Tdrive is now directly connected to VDDEL, turning off SCAN3 at time t2 allows the source terminal of transistor Tdrive to charge to a level 1 Vt lower than the Vref level at the gate of transistor Tdrive. In other words, the source terminal of transistor Tdrive is charged to (Vref-Vt) during the Vt sampling phase from time t2 to t3.

[0069] At time t4, the scan signal SCAN1 is pulsed high to turn on the transistor Tdata during the data programming phase. Activating the transistor Tdata drives the gate terminal of the transistor Tdrive to a data voltage Vdata corresponding to the new data signal value of the pixel 22. Because the transistors Tem and Tini are both turned off at this point, the capacitor Cst cannot discharge (e.g., the voltage across the capacitor Cst remains equal to Vt even though the drive transistor gate terminal is driven to the new Vdata level). If desired, the emission signal EM can be optionally asserted throughout the data programming phase to allow a current proportional to Vdata to flow through the emission transistor Tem during the period from t3 to t5 (see alternative waveform 1490).

[0070] At time t5, the emission signal EM is asserted to initiate an emission phase during which the diode 26 can emit an amount of light proportional to the voltage Vdata. During the emission phase, the resulting Vgs of the transistor Tdrive is equal to [Vdata-(Vref-Vt)]. Since the final emission current is proportional to Vgs-Vt, (Vgs-Vt) is equal to (Vdata-Vref+Vt-Vt), so the emission current is independent of Vt and Vt is cancelled out to complete the intra-pixel threshold voltage cancellation operation. As discussed above in connection with FIG. 5B, the duration of the Vt sampling phase can be increased independently relative to the duration of the data programming phase (e.g., the duration of the Vt sampling phase can be at least 2 times, 5 times, 2-5 times, 10 times, 5-10 times, 10-20 times, or more than 20 times longer than the duration of the data programming phase) to minimize the temperature luminance sensitivity of the display 14.

[0071] The pixel 22 of FIG. 12A can be used for low refresh rate displays. FIG. 12C is a timing diagram illustrating the behavior of relevant signal waveforms controlling the pixel 22 of FIG. 12A during an extended vertical blanking period of low refresh rate operation. Before time ta, the emission signal EM may be deasserted (e.g., driven low) to temporarily stop emission. After time ta, the signal SCAN3 may be pulsed to temporarily activate the transistors Tar and Tini. Activating the transistor Tar drives the OLED anode terminal to the anode reset voltage level Var. At time tb, the emission signal EM may be asserted to resume emission. The duration from time ta to tb should be equal to the active refresh period from time t1 to t5 (see FIG. 12B). Such an anode reset may be performed every 8 ms, 4 ms, 2 ms, or other suitable intervals during the vertical blanking period, depending on when the system is able to update the data values. Performing multiple anode resets during the vertical blanking interval can help mitigate flickering and brightness fluctuations at low grey levels when display 14 is operating at low refresh rates.

[0072] The embodiment of FIG. 12A in which the pixel 22 includes both the anode reset transistor Tar coupled to the anode terminal and a separate initialization transistor Tini coupled to the transistor Tdrive is merely exemplary. FIG. 13A shows another suitable embodiment of the pixel 22 that does not include a separate initialization transistor Tini. In other words, the structure and function of the pixel 22 of FIG. 13A are the same as those of FIG. 12A, except that the pixel 22 of FIG. 13A includes one less transistor (i.e., the pixel 22 of FIG. 13A does not include the transistor Tini). Thus, the pixel 22 of FIG. 13A includes only five semiconductor oxide transistors and two capacitors Cst and Cboost.

[0073] FIG. 13B is a timing diagram illustrating the operation of a display pixel 22 of the type shown in FIG. 13A. Prior to time t1, scan signal SCAN2 may be asserted (e.g., driven high) to activate (turn on) transistor Tgate. Activating transistor Tgate drives the gate terminal of transistor Tdrive to a reference voltage level Vref. At time t1, scan signal SCAN3 is pulsed high to turn on transistor Tar. Activating transistor Tar drives the source terminal of transistor Tdrive to Var. During the initialization phase, signal EM is held high so that voltage Var may be applied to the source terminal of transistor Tdrive via transistor Tern. Thus, during the initialization phase, the gate-source voltage Vgs of transistor Tdrive is biased to (Vref-Var). Because voltage Var is also applied directly to the source terminal of transistor Tdrive during the initialization phase, voltage Var may also function to apply an on-bias stress to mitigate Vt hysteresis and improve first frame response.

[0074] During this time, there may be a short circuit current path from VDDEL to Var through transistors Tdrive, Tern, and Tar. If Var were carried on a row-wise routing line, such a current from every single accessed pixel along a given row would generate a significant IR drop. To help keep the IR drop to a manageable level, the anode reset voltage Var may be routed to the pixels 22 via a column-wise routing line, so that each anode reset column line sees only one short circuit current path when any given row is being accessed.

[0075] From time t2 to t3, only SCAN2 remains asserted. Since the drain terminal of transistor Tdrive is now directly connected to VDDEL, turning off SCAN3 at time t2 allows the source terminal of transistor Tdrive to charge to a level 1 Vt lower than the Vref level at the gate of transistor Tdrive. In other words, the source terminal of transistor Tdrive is charged to (Vref-Vt) during the Vt sampling phase from time t2 to t3.

[0076] At time t4, scan signal SCAN1 is pulsed high to turn on transistor Tdata during the data programming phase. Activating transistor Tdata drives the gate terminal of transistor Tdrive to a data voltage Vdata corresponding to the new data signal value for pixel 22. Because transistor Tern is turned off at this point, capacitor Cst is not able to discharge (e.g., the voltage across capacitor Cst remains equal to Vt even though the drive transistor gate terminal is driven to the new Vdata level).

[0077] At time t5, the emission signal EM is asserted to initiate an emission phase during which the diode 26 can emit an amount of light proportional to the voltage Vdata. During the emission phase, the resulting Vgs of the transistor Tdrive is equal to [Vdata-(Vref-Vt)]. Since the final emission current is proportional to Vgs-Vt, (Vgs-Vt) is equal to (Vdata-Vref+Vt-Vt), so the emission current is independent of Vt and Vt is cancelled out to complete the intra-pixel threshold voltage cancellation operation. As discussed above in connection with FIG. 5B, the duration of the Vt sampling phase can be increased independently relative to the duration of the data programming phase (e.g., the duration of the Vt sampling phase can be at least 2 times, 5 times, 2-5 times, 10 times, 5-10 times, 10-20 times, or more than 20 times longer than the duration of the data programming phase) to minimize the temperature luminance sensitivity of the display 14.

[0078] The pixel 22 of Figure 13A can also be used in low refresh rate displays. The vertical blanking anode reset control scheme of Figure 12C can also be applied to the pixel 22 of Figure 13A.

[0079] The embodiment of FIG. 13A in which pixel 22 includes a transistor Tdrive having a drain terminal shorted to the VDDEL power line is merely exemplary. FIG. 14A shows another suitable embodiment of pixel 22 having a transistor Tdrive with a drain terminal coupled to the VDDEL line via an emission transistor Tern and a source terminal coupled to the anode terminal. In other words, the structure and function of pixel 22 in FIG. 14A are the same as those in FIG. 13A, except that the positions of transistors Tdrive and Tern are swapped. Pixel 22 in FIG. 14A includes only five semiconductor oxide transistors and two capacitors Cst and Cboost. In particular, capacitor Cst can have a first terminal coupled to the gate terminal of transistor Tdrive and a second terminal coupled to the anode terminal. Capacitor Cboost has a first terminal coupled to the anode terminal and a second terminal configured to receive voltage Vdc. Pixel 22 does not need to include capacitor Cboost (i.e., capacitor Cboost is optional).

[0080] FIG. 14B is a timing diagram illustrating the operation of a display pixel 22 of the type shown in FIG. 13A. Prior to time t1, scan signal SCAN2 may be asserted (e.g., driven high) to activate (turn on) transistor Tgate. Activating transistor Tgate drives the gate terminal of transistor Tdrive to a reference voltage level Vref. At time t1, scan signal SCAN3 is pulsed high to turn on transistor Tar. Activating transistor Tar drives the source terminal of transistor Tdrive to Var. Signal EM may be temporarily turned off during the initialization phase. By activating transistor Tar, voltage Var may be applied to the source terminal of transistor Tdrive. Thus, during the initialization phase, the gate-source voltage Vgs of transistor Tdrive is biased to (VrefVar). Because voltage Var is also applied directly to the source terminal of transistor Tdrive during the initialization phase, voltage Var may also function to apply an on-bias stress to mitigate Vt hysteresis and improve the first frame response. By turning off transistor Tern during the initialization phase, a short circuit current path between VDDEL and Var is prevented.

[0081] From time t2 to t3, signals SCAN2 and EM are asserted. Asserting signal EM connects the drain terminal of transistor Tdrive to VDDEL. Since the drain terminal of transistor Tdrive is now directly connected to VDDEL, turning off SCAN3 at time t2 allows the source terminal of transistor Tdrive to be charged to a level that is 1 Vt lower than the Vref level at the gate of transistor Tdrive. In other words, the source terminal of transistor Tdrive is charged to (Vref-Vt) during the Vt sampling phase from time t2 to t3.

[0082] At time t4, scan signal SCAN1 is pulsed high to turn on transistor Tdata during the data programming phase. Activating transistor Tdata drives the gate terminal of transistor Tdrive to a data voltage Vdata corresponding to the new data signal value for pixel 22. Because transistors Tar and Tern are turned off at this point, capacitor Cst cannot discharge (e.g., the voltage across capacitor Cst remains equal to Vt even when the drive transistor gate terminal is driven to the new Vdata level).

[0083] At time t5, the emission signal EM is asserted to initiate an emission phase during which the diode 26 can emit an amount of light proportional to the voltage Vdata. During the emission phase, the resulting Vgs of the transistor Tdrive is equal to [Vdata-(Vref-Vt)]. Since the final emission current is proportional to Vgs-Vt, (Vgs-Vt) is equal to (Vdata-Vref+Vt-Vt), so the emission current is independent of Vt and Vt is cancelled out to complete the intra-pixel threshold voltage cancellation operation. As discussed above in connection with FIG. 5B, the duration of the Vt sampling phase can be increased independently relative to the duration of the data programming phase (e.g., the duration of the Vt sampling phase can be at least 2 times, 5 times, 2-5 times, 10 times, 5-10 times, 10-20 times, or more than 20 times longer than the duration of the data programming phase) to minimize the temperature luminance sensitivity of the display 14.

[0084] The pixel 22 of Figure 14A can also be used in low refresh rate displays. The vertical blanking anode reset control scheme of Figure 12C can also be applied to the pixel 22 of Figure 14A.

[0085] According to an embodiment, there is provided a display comprising a gate driver circuit and a plurality of pixels coupled to the gate driver circuit, at least one pixel of the plurality of pixels comprising: a light emitting diode having an anode terminal; a drive transistor coupled in series with the light emitting diode, the drive transistor including a gate terminal, a first source-drain terminal, and a second source-drain terminal; a data loading transistor having a first source-drain terminal coupled to the gate terminal of the drive transistor, a second source-drain terminal coupled to a data line, and a gate terminal configured to receive a first scan signal from the gate driver circuit; and a gate voltage setting transistor having a first source-drain terminal coupled to the gate terminal of the drive transistor, a second source-drain terminal configured to receive a reference voltage, and a gate terminal configured to receive the second scan signal from the gate driver circuit, wherein the gate driver circuit is configured to assert the second scan signal during a threshold voltage sampling phase and assert the first scan signal during a data programming phase, wherein the data programming phase has a first duration and the threshold voltage sampling phase has a second duration longer than the first duration.

[0086] According to another embodiment, the gate driver circuit is configured to perform a threshold voltage sampling phase before a data programming phase during a refresh operation.

[0087] According to another embodiment, the second duration is at least 10 times greater than the first duration.

[0088] According to another embodiment, at least one pixel in the plurality of pixels further comprises an anode reset transistor having a first source-drain terminal coupled to the anode terminal of the light emitting diode, a second source-drain terminal configured to receive an anode reset voltage, and a gate terminal configured to receive a third scan signal from the gate driver circuit.

[0089] According to another embodiment, at least one pixel in the plurality of pixels comprises: The gate driver circuit is configured to assert the second scan signal and the third scan signal during the initialization phase. The gate driver circuit is configured to assert the second scan signal and the third scan signal during the initialization phase. The gate driver circuit is configured to assert the second scan signal and the third scan signal during the initialization phase. The gate driver circuit is configured to assert the second scan signal and the third scan signal during the initialization phase.

[0090] According to another embodiment, at least one pixel in the plurality of pixels comprises: and a first emission transistor coupled between the positive power supply rail and a first source-drain terminal of the drive transistor, and a second emission transistor coupled between a second source-drain terminal and an anode terminal of the drive transistor, the first and second emission transistors having gate terminals configured to receive an emission signal from a gate driver circuit, the gate driver circuit configured to assert the emission signal during the threshold voltage sampling phase.

[0091] According to another embodiment, the drive transistor, the data loading transistor, the gate voltage setting transistor, the anode reset transistor, the initialization transistor, the first emission transistor, and all of the second emission transistor comprise semiconductor oxide transistors.

[0092] According to another embodiment, at least one pixel in the plurality of pixels further comprises a storage capacitor having a first terminal coupled to the gate terminal of the drive transistor and having a second terminal coupled to the anode terminal.

[0093] According to another embodiment, at least one pixel in the plurality of pixels further comprises an additional capacitor having a first terminal coupled to the anode terminal and having a second terminal configured to receive a static voltage.

[0094] According to another embodiment, at least one pixel in the plurality of pixels comprises a first emission transistor coupled between a positive power rail and a first source-drain terminal of the drive transistor, the first emission transistor having a gate terminal configured to receive a first emission signal from a gate driver circuit, and a second emission transistor coupled between a second source-drain terminal and an anode terminal of the drive transistor, the second emission transistor having a gate terminal configured to receive a second emission signal from the gate driver circuit, wherein the gate driver circuit asserts the first emission signal and deasserts the second emission signal during the threshold voltage sampling phase.

[0095] According to another embodiment, at least one pixel in the plurality of pixels further includes a storage capacitor having a first terminal coupled to the gate terminal of the drive transistor and a second terminal coupled to the second source-drain terminal of the drive transistor, and an additional capacitor having a first terminal coupled to the second source-drain terminal of the drive transistor and a second terminal configured to receive a static voltage.

[0096] According to another embodiment, a first source-drain terminal of the drive transistor is shorted to a positive power supply line, and at least one pixel of the plurality of pixels includes a first emission transistor having a first source-drain terminal coupled to the second source-drain terminal of the drive transistor, a second source-drain terminal coupled to the anode terminal, and a gate terminal configured to receive a first emission signal from a gate driver circuit, and a first source-drain terminal coupled to the second source-drain terminal of the first emission transistor, a second source-drain terminal coupled to the anode terminal, and a gate terminal configured to receive a second emission signal from the gate driver circuit. an initialization transistor having a first source-drain terminal coupled to the second source-drain terminal of the first emission transistor, a second source-drain terminal configured to receive an initialization voltage, and a gate terminal configured to receive a third scan signal; a storage capacitor having a first terminal coupled to the gate terminal of the drive transistor and a second terminal coupled to the second source-drain terminal of the first emission transistor; and an additional capacitor having a first terminal coupled to the second source-drain terminal of the first emission transistor and a second terminal configured to receive a static voltage. Further includes.

[0097] According to another embodiment, at least one pixel in the plurality of pixels comprises: and a storage capacitor having a first terminal coupled to the gate terminal of the drive transistor and a second terminal coupled to the second source-drain terminal of the drive transistor, and an additional capacitor having a first terminal coupled to the second source-drain terminal of the drive transistor and a second terminal configured to receive a static voltage.

[0098] According to an embodiment, there is provided a method of operating a display having a gate driver circuit and a plurality of pixels, each pixel including at least a light emitting diode, a drive transistor, a data loading transistor, a gate voltage setting transistor, and a storage capacitor, comprising the steps of: Sampling a threshold voltage of the drive transistor onto the storage capacitor by asserting a second scan signal to activate a gate voltage setting transistor using the gate driver circuit during a threshold voltage sampling phase; and loading data onto the storage capacitor by asserting a first scan signal to activate a data loading transistor using the gate driver circuit during a data programming phase. wherein a data programming phase occurs after a threshold voltage sampling phase during a data refresh operation, the data programming phase having a first duration and the threshold voltage sampling phase having a second duration that is longer than the first duration.

[0099] According to another embodiment, the second duration is at least 10 times greater than the first duration.

[0100] According to another embodiment, each pixel in the plurality of pixels further includes an anode reset transistor, and the method further includes, during the initialization phase, resetting, using the gate driver circuit, an anode of the light emitting diode by asserting a third scan signal to activate the anode reset transistor.

[0101] According to another embodiment, each pixel in the plurality of pixels further includes an initialization transistor, and the method further includes applying, during the initialization phase, a bias voltage to the drive transistor by asserting, using the gate driver circuit, a third scan signal to activate the initialization transistor.

[0102] According to another embodiment, each pixel in the plurality of pixels further includes at least one emission transistor, and the method further includes deasserting, using the gate driver circuit, an emission control signal to deactivate the at least one emission transistor during the initialization phase, and asserting, using the gate driver circuit, an emission control signal to activate the at least one emission transistor during the threshold voltage sampling phase.

[0103] According to another embodiment, the method further includes, during the data programming phase, keeping the emission control signal deasserted using the gate driver circuitry.

[0104] According to another embodiment, the method further includes keeping the emission control signal asserted using the gate driver circuit during the data programming phase.

[0105] According to another embodiment, each pixel in the plurality of pixels further includes a first and a second emission transistor, and the method further includes: deasserting, using a gate driver circuit, a first emission control signal to deactivate the first emission transistor during an initialization phase; deasserting, using a gate driver circuit, a second emission control signal to deactivate the second emission transistor during the initialization phase; and asserting, using the gate driver circuit, the first emission control signal to activate the first emission transistor while the second emission control signal is deasserted during the threshold voltage sampling phase.

[0106] According to an embodiment, a display pixel having a luminance includes a light emitting diode having an anode terminal; a drive transistor coupled in series with the light emitting diode, the drive transistor having a first source-drain terminal, a second source-drain terminal, and a gate terminal; a data loading transistor having a first source-drain terminal coupled to the gate terminal of the drive transistor, a second source-drain terminal coupled to a data line, and a gate terminal configured to receive a first scan signal; a gate voltage setting transistor having a first source-drain terminal coupled to the gate terminal of the drive transistor, a second source-drain terminal configured to receive a reference voltage, and a gate terminal configured to receive a second scan signal; and an emission transistor coupled in series with the light emitting diode and the drive transistor. and an anode reset transistor having a gate terminal configured to receive an emission signal, a first source-drain terminal coupled to the anode terminal, a second source-drain terminal configured to receive a reset voltage, and a gate terminal configured to receive a third scan signal, the display pixel being operable in an initialization phase in which the gate voltage setting transistor and the anode reset transistor are activated, a threshold voltage sampling phase in which the gate voltage setting transistor and the emission transistor are activated, and a data programming phase in which the data loading transistor is activated, the threshold voltage sampling phase having a duration selected to mitigate the amount that luminance changes as a function of temperature.

[0107] The above is merely illustrative and various modifications may be made to the described embodiments. The above embodiments may be implemented individually or in any combination.

Claims

1. A gate driver circuit; a plurality of pixels coupled to the gate driver circuit, wherein at least one pixel of the plurality of pixels comprises: a light emitting diode having an anode terminal; a drive transistor coupled in series with the light emitting diode, the drive transistor including a gate terminal, a first source-drain terminal, and a second source-drain terminal; a data loading transistor having a first source-drain terminal coupled to the gate terminal of the drive transistor, a second source-drain terminal coupled to a data line, and a gate terminal configured to receive a first scan signal from the gate driver circuit; a gate voltage setting transistor having a first source-drain terminal coupled to the gate terminal of the drive transistor, a second source-drain terminal configured to receive a reference voltage, and a gate terminal configured to receive a second scan signal from the gate driver circuit; an anode reset transistor having a first source-drain terminal coupled to the anode terminal of the light emitting diode, a second source-drain terminal configured to receive an anode reset voltage, and a gate terminal configured to receive a third scan signal from the gate driver circuit, the gate driver circuit comprising: asserting the second scan signal during a threshold voltage sampling phase; configured to assert the first scan signal during a data programming phase, the data programming phase having a first duration and the threshold voltage sampling phase having a second duration that is longer than the first duration; performing a plurality of anode reset operations by pulsing said third scan signal during a vertical blanking interval.

2. 2. The display of claim 1, wherein the gate driver circuit is configured to perform the threshold voltage sampling phase before the data programming phase during a refresh operation, and during the data programming phase, the data loading transistor is activated and the anode reset transistor is deactivated.

3. 2. A display as claimed in claim 1, wherein the second duration is at least ten times longer than the first duration.

4. The at least one pixel in the plurality of pixels is 2. The display of claim 1, further comprising an initialization transistor having a first source-drain terminal coupled to the second source-drain terminal of the drive transistor, a second source-drain terminal configured to receive an initialization voltage, and a gate terminal configured to receive the third scan signal, wherein the gate driver circuit is configured to assert the second scan signal and the third scan signal during an initialization phase.

5. The at least one pixel in the plurality of pixels is a first emission transistor coupled between a positive power supply rail and the first source-drain terminal of the drive transistor; 5. The display of claim 4, further comprising: a second emission transistor coupled between the second source-drain terminal and the anode terminal of the drive transistor, the first and second emission transistors having gate terminals configured to receive an emission signal from the gate driver circuit, the gate driver circuit being configured to assert the emission signal during the threshold voltage sampling phase.

6. 6. The display of claim 5, wherein the drive transistor, the data loading transistor, the gate voltage setting transistor, the anode reset transistor, the initialization transistor, the first emission transistor, and the second emission transistor all comprise semiconductor oxide transistors.

7. The at least one pixel in the plurality of pixels is 6. The display of claim 5, further comprising a storage capacitor having a first terminal coupled to the gate terminal of the drive transistor and having a second terminal coupled to the anode terminal.

8. The at least one pixel in the plurality of pixels is 8. The display of claim 7, further comprising an additional capacitor having a first terminal coupled to the anode terminal and having a second terminal configured to receive a constant voltage.

9. The at least one pixel in the plurality of pixels is a first emission transistor coupled between a positive power rail and the first source-drain terminal of the drive transistor, the first emission transistor having a gate terminal configured to receive a first emission signal from the gate driver circuit; a second emission transistor coupled between the second source-drain terminal and the anode terminal of the drive transistor, the second emission transistor having a gate terminal configured to receive a second emission signal from the gate driver circuit; 5. The display of claim 4, further comprising: said gate driver circuitry configured to assert said first emission signal and de-assert said second emission signal during said threshold voltage sampling phase.

10. the at least one pixel in the plurality of pixels includes a storage capacitor having a first terminal coupled to the gate terminal of the drive transistor and a second terminal coupled to the second source-drain terminal of the drive transistor; an additional capacitor having a first terminal coupled to the second source-drain terminal of the drive transistor and having a second terminal configured to receive a constant voltage; The display of claim 9 further comprising:

11. The first source-drain terminal of the drive transistor is shorted to a positive power supply line, and the at least one pixel of the plurality of pixels is a first emission transistor having a first source-drain terminal coupled to the second source-drain terminal of the drive transistor, a second source-drain terminal, and a gate terminal configured to receive a first emission signal from the gate driver circuit; a second emission transistor having a first source-drain terminal coupled to the second source-drain terminal of the first emission transistor, a second source-drain terminal coupled to the anode terminal, and a gate terminal configured to receive a second emission signal from the gate driver circuit; an initialization transistor having a first source-drain terminal coupled to the second source-drain terminal of the first emission transistor, a second source-drain terminal configured to receive an initialization voltage, and a gate terminal configured to receive the third scan signal; a storage capacitor having a first terminal coupled to the gate terminal of the drive transistor and having a second terminal coupled to the second source-drain terminal of the first emission transistor; an additional capacitor having a first terminal coupled to the second source-drain terminal of the first emission transistor and having a second terminal configured to receive a constant voltage rail different from the positive power rail; The display of claim 1 further comprising:

12. The at least one pixel in the plurality of pixels is a storage capacitor having a first terminal coupled to the gate terminal of the drive transistor and a second terminal coupled to the second source-drain terminal of the drive transistor; an additional capacitor having a first terminal coupled to the second source-drain terminal of the drive transistor and having a second terminal configured to receive a constant voltage; The display of claim 1 further comprising:

13. 1. A method of operating a display having a gate driver circuit and a plurality of pixels, each pixel including at least a light emitting diode, a drive transistor, a data loading transistor, a gate voltage setting transistor, an anode reset transistor, and a storage capacitor, comprising: sampling, during a threshold voltage sampling phase, a threshold voltage of the drive transistor onto the storage capacitor by asserting, with the gate driver circuit, a second scan signal to activate the gate voltage setting transistor; loading data onto the storage capacitor by asserting a first scan signal to activate the data loading transistor with the gate driver circuit during a data programming phase; performing a plurality of anode reset operations in the gate driver circuit during a vertical blanking interval by pulsing a third scan signal a plurality of times to activate the anode reset transistor; The method, wherein the data programming phase occurs after the threshold voltage sampling phase during a data refresh operation.

14. 14. The method of claim 13, wherein the data programming phase has a first duration and the threshold voltage sampling phase has a second duration that is at least ten times greater than the first duration.

15. The method comprises:

14. The method of claim 13, further comprising, during an initialization phase, resetting, with the gate driver circuit, the anode of the light emitting diode by asserting the third scan signal to activate the anode reset transistor.

16. Each pixel in the plurality of pixels further includes an initialization transistor, the method comprising:

16. The method of claim 15, further comprising applying, during the initialization phase, a bias voltage to the drive transistor by asserting, with the gate driver circuit, the third scan signal to activate the initialization transistor.

17. Each pixel in the plurality of pixels further includes at least one emission transistor, and the method further comprises: deasserting, during the initialization phase, an emission control signal to deactivate the at least one emission transistor using the gate driver circuit; 17. The method of claim 16, further comprising: during the threshold voltage sampling phase, asserting, with the gate driver circuit, the emission control signal to activate the at least one emission transistor.

18. Each pixel in the plurality of pixels further includes first and second emission transistors, and the method further comprises: deasserting, during the initialization phase, a first emission control signal to deactivate the first emission transistor using the gate driver circuit; deasserting, during the initialization phase, a second emission control signal to deactivate the second emission transistor using the gate driver circuit; 17. The method of claim 16, further comprising: during the threshold voltage sampling phase, asserting, with the gate driver circuit, the first emission control signal to activate a first emission transistor while the second emission control signal is deasserted.

19. A display pixel, a light emitting diode having an anode terminal; a drive transistor coupled in series with the light emitting diode between a positive power supply rail and a ground rail; a first capacitor having a first terminal coupled to the gate terminal of the drive transistor and a second terminal coupled to the source-drain terminals of the drive transistor; a second capacitor having a first terminal coupled to the source-drain terminal of the drive transistor and a second terminal coupled to a voltage rail different from the positive power rail; a data loading transistor having a first source-drain terminal coupled to the gate terminal of the drive transistor, a second source-drain terminal coupled to a data line, and a gate terminal configured to receive a first scan signal asserted during a data loading phase having a first duration; a gate voltage setting transistor having a first source-drain terminal coupled to the gate terminal of the drive transistor, a second source-drain terminal configured to receive a reference voltage, and a gate terminal configured to receive a second scan signal that is asserted during a threshold voltage sampling phase having a second duration that is longer than the first duration; an emission transistor coupled in series with the light emitting diode and the drive transistor, the emission transistor having a gate terminal configured to receive an emission signal; an anode reset transistor having a first source-drain terminal coupled to the anode terminal, a second source-drain terminal configured to receive a reset voltage, and a gate terminal configured to receive a third scan signal that is asserted a number of times during a vertical blanking interval.

20. The display pixel of claim 19, wherein during the data loading phase, the data loading transistor is activated and the anode reset transistor is deactivated.

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