In-pixel memory display

Abstract

An electronic display having one or more pixels including memory and drivers is provided that can help reduce bandwidth associated with transmitting and processing image data for presentation on the electronic display. An electronic display may include an active area having first pixels (70) formed within the active area, the first pixels (70) emitting light in response to image data (86). The electronic display may also include a controller (60, 62, 54) that sends the image data (86) to the first pixels (70). The first pixels (70) may include a memory (78) for digitally storing the image data (86) received from the controller (60, 62, 54) and a driver circuit (80) for receiving the image data (86) from the memory (78). The driver circuit (80) may cause the first pixels (70) to emit light in response to the image data (86).

Description

Summary of the Invention

[0001] A summary of certain embodiments disclosed herein is provided below. It should be understood that these aspects are presented merely to provide the reader with an overview of these specific embodiments, and that these aspects are not intended to limit the scope of this disclosure. Indeed, the disclosure may encompass a variety of aspects that are not set forth below.

[0002] Methods and systems for reducing the bandwidth or amount of image data transmitted and processed to prepare an image for presentation on an electronic display by implementing in-pixel memory in the electronic display may provide immeasurable value. Such implementation of in-pixel memory may allow for the elimination of a frame buffer associated with the electronic display. Having memory in the pixel may not only reduce the complexity of the electronic display design, but may also allow the electronic display to be designed more simply, since less image data is simultaneously transmitted to the pixel array of the electronic display. For example, pixels may be programmed in smaller groups, since the in-pixel memory stores values ​​until the time of presentation of the image.

[0003] This disclosure describes an electronic display having one or more pixels including memory and drivers that may help reduce bandwidth associated with transmitting and processing image data for presentation on the electronic display. The inclusion of memory within the pixel may allow for storage of image data prior to output to the light emitting portion of the pixel. Thus, the memory within the pixel may reduce or possibly eliminate reliance on a frame buffer within the electronic display by acting as an individual frame buffer for the pixel. The memory within the pixel may be used in conjunction with a driver to cause the light emitting portion of the pixel to emit light. [Brief description of the drawings]

[0004] The various aspects of the present disclosure can be better understood by reading the following Detailed Description and by referring to the following drawings.

[0005] [Figure 1] 1 is a schematic block diagram of an electronic device according to one embodiment.

[0006] [Diagram 2] FIG. 2 is a perspective view of a watch that represents one embodiment of the electronic device of FIG. 1, according to one embodiment.

[0007] [Diagram 3] FIG. 2 is a front view of a handheld tablet device representing an embodiment of the electronic device of FIG. 1, according to one embodiment.

[0008] [Figure 4] 2 is a front view of a computer that represents one embodiment of the electronic device of FIG. 1, according to one embodiment.

[0009] [Diagram 5] 2 is a block diagram of a display system of the electronic device of FIG. 1 according to one embodiment.

[0010] [Figure 6] 6 is a block diagram of a pixel array of the display system of FIG. 5 according to one embodiment.

[0011] [Figure 7] FIG. 7 is a block diagram of an embodiment of the pixel array of FIG. 6, according to one embodiment.

[0012] [Figure 8] 7 is a block diagram of a pixel of the pixel array of FIG. 6 that emits light according to a binary pulse-width modulated emission scheme, according to one embodiment.

[0013] [Figure 9]7 is a block diagram of an embodiment of a pixel of the pixel array of FIG. 6 that emits light according to a single pulse-width modulated emission scheme in accordance with one embodiment.

[0014] [Figure 10] 7 is a block diagram of another embodiment of a pixel of the pixel array of FIG. 6 that emits light according to a pulse density modulated light emission scheme in accordance with one embodiment.

[0015] [Figure 11] 6 is a timing diagram of a program sequence performed by a column driver of the display system of FIG. 5 according to one embodiment.

[0016] [Figure 12] 7 is a circuit diagram of a first embodiment of a sub-pixel of the pixel array of FIG. 6 having current drive according to one embodiment.

[0017] [Figure 13] FIG. 7 is a circuit diagram of a second embodiment of a sub-pixel of the pixel array of FIG. 6 having a hybrid drive and having memory, according to an embodiment.

[0018] [Figure 14] FIG. 14 is a timing diagram of control signals used to operate the sub-pixels of FIG. 13 to display an image according to one embodiment.

[0019] [Figure 15] 13 is a graph illustrating current and voltage produced by simulating the transmission of image data corresponding to a binary pulse width modulated emission scheme to the sub-pixels of FIG. 12, according to one embodiment.

[0020] [Figure 16] 14 is a graph illustrating current and voltage produced by simulating the transmission of image data corresponding to a binary pulse width modulated emission scheme to the sub-pixels of FIG. 13, according to one embodiment.

[0021] [Figure 17] FIG. 13 is a circuit diagram of a memory circuit associated with the subpixel of FIG. 12 according to one embodiment.

[0022] [Figure 18] FIG. 18 is a circuit diagram of an embodiment of the memory circuit of FIG. 17 coupled to an embodiment of the subpixel of FIG. 12 implementing a global anode, according to an embodiment.

[0023] [Figure 19] 19 is a process for operating the subpixel of FIG. 18 according to one embodiment.

[0024] [Figure 20] FIG. 19 is a circuit diagram of an embodiment of the subpixel of FIG. 18 implementing a global cathode according to one embodiment.

[0025] [Figure 21] FIG. 14 is a circuit diagram of the memory circuit of FIG. 13 according to one embodiment.

[0026] [Figure 22] 22 is a process for operating the memory circuit of FIG. 21 according to one embodiment.

[0027] [Diagram 23] FIG. 14 is a circuit diagram of one embodiment of the memory circuit of FIG. 13, according to one embodiment.

[0028] [Figure 24A] 24 is a bit plane graph corresponding to no reordering implemented in the memory circuit of FIG. 23 according to one embodiment.

[0029] [Figure 24B] 24 is an error graph corresponding to no reordering implemented in the memory circuit of FIG. 23 according to one embodiment.

[0030] [Figure 24C]24 is a bit-plane graph corresponding to two permutations implemented in the memory circuit of FIG. 23 according to one embodiment.

[0031] [Figure 24D] 24 is an error graph corresponding to two permutations implemented in the memory circuit of FIG. 23 according to one embodiment.

[0032] [Figure 24E] 24 is a bit-plane graph corresponding to three permutations implemented in the memory circuit of FIG. 23 according to one embodiment.

[0033] [Figure 24F] 24 is an error graph corresponding to three permutations implemented in the memory circuit of FIG. 23 according to one embodiment.

[0034] [Figure 24G] 24 is a bit-plane graph corresponding to an ideal case of permutation implemented in the memory circuit of FIG. 23 according to one embodiment.

[0035] [Fig. 24H] 24 is an error graph corresponding to an ideal case of permutation implemented in the memory circuit of FIG. 23 according to one embodiment.

[0036] [Diagram 25] 24D is a bit plane graph showing the bit plane graph of FIG. 24C over time, including an additional color channel, according to one embodiment.

[0037] [Figure 26] FIG. 26 is a timing diagram illustrating the load and discharge process associated with the third quadrant of the bit plane graph of FIG. 25 according to one embodiment.

[0038] [Figure 27] FIG. 24 is a circuit diagram of one embodiment of the memory circuit of FIG. 23 implemented for use in a digital mirror display, according to one embodiment.

[0039] [Figure 28] FIG. 26 is a circuit diagram of an embodiment of the pixel of FIG. 25 for use in a liquid crystal display according to one embodiment.

[0040] [Figure 29] FIG. 6 is a block diagram comparing the display system of FIG. 5 with a display system having a smart buffer outside the active area of ​​the electronic display, according to one embodiment.

[0041] [Diagram 30] FIG. 31 is a circuit diagram of one embodiment of the memory circuit of FIG. 13 for use in the smart buffer of FIG. 29 according to one embodiment.

[0042] [Diagram 31] FIG. 30 is a circuit diagram of a third embodiment of a sub-pixel of the pixel array of FIG. 6 for use in a display system having the smart buffer of FIG. 29 in accordance with an embodiment.

[0043] In the following, one or more specific embodiments are described. In order to provide a concise description of these embodiments, not all features of an actual implementation are shown in the specification. As with any engineering or design project, it should be understood that the development of any such practical implementation requires numerous implementation-specific decisions to be made in order to achieve the developer's specific objectives, such as compliance with system-related and business-related constraints that may vary from implementation to implementation. Moreover, it should be understood that such a development effort may be complex and time-consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill in the art having the benefit of this disclosure.

[0044] When introducing elements of various embodiments of the present disclosure, the articles "a," "an," and "the" mean that there is one or more elements. The terms "comprising," "including," and "having" are intended to be inclusive and mean that there may be additional elements other than the listed elements. Further, it should be understood that references to "one embodiment" or "embodiments" of the present disclosure are not intended to be interpreted as excluding the existence of additional embodiments that incorporate the recited features.

[0045] Electronic displays are found in many electronic devices, from cell phones to computers, televisions, car dashboards, and more. Electronic displays have achieved higher resolution by reducing the size of individual pixels. However, increasing resolution can increase the difficulty associated with managing the increased amount of image data that is processed by processing circuitry before displaying the image, for example, by causing increased power consumption due to processing the increased amount of image data. Furthermore, increasing resolution can increase the bandwidth used to communicate image data from processing circuitry to the pixel array for presenting the image, since more image data is used to communicate the same image at a higher electronic display resolution.

[0046] Embodiments of the present disclosure relate to systems and methods for implementing in-pixel memory circuits that can be used as individual frame buffers for each pixel, which can reduce the reliance of an electronic display's pixel array and drive circuitry on external frame buffers. The memory can be implemented within pixel circuits that include light emitting diodes (LEDs). Organic light emitting diodes (OLEDs) represent one type of LED that may be found in pixels, although other types of LEDs may also be used, and other types of LEDs may be used in pixel circuits such as components supporting liquid crystal displays (LCDs), plasma display panels, and / or dot matrix displays.

[0047] The disclosed systems and methods for implementing in-pixel memory circuits can reduce the bandwidth of image data transmission to a pixel array for display because the pixel can store image data in memory. In this way, the dependency on a frame buffer to temporarily store image data external to the pixel is reduced because the pixel has its own memory to store its image data before displaying it.

[0048] A general description of suitable electronic devices that can include self-emissive displays, such as LED (e.g., OLED) displays, and corresponding circuitry of the present disclosure is provided. OLEDs represent one type of LED that may be found in self-emissive pixels, although other types of LEDs may also be used.

[0049] For illustrative purposes, an electronic device 10 including an electronic display 18 is shown in FIG. 1. As described in more detail below, electronic device 10 can be any suitable electronic device, such as a computer, a mobile phone, a portable media device, a tablet, a television, a virtual reality headset, a vehicle dashboard, etc. It should therefore be noted that FIG. 1 is merely one example of a particular implementation and is intended to illustrate the types of components that may be present in electronic device 10. Electronic device 10 may include, among other things, a processing core complex 12, such as a system on a chip (SoC) and / or a processing circuit(s), storage device(s) 14, communication interface(s) 16, an electronic display 18, an input structure 20, and a power source 22. The various components depicted in FIG. 1 may include hardware elements (e.g., circuitry), software elements (e.g., a tangible non-transitory computer-readable medium that stores instructions), or a combination of both hardware and software elements. It should be noted that the various illustrated components may be combined into fewer components or separated into additional components.

[0050] As shown, the processing core complex 12 is operatively coupled to a storage device(s) 14. Thus, the processing core complex 12 executes instructions stored in the storage device(s) 14 to perform operations such as generating and / or transmitting image data. As such, the processing core complex 12 may include one or more general-purpose microprocessors, one or more application specific processors (ASICs), one or more field programmable logic arrays (FPGAs), or any combination thereof. Using pixels including light-emitting components (e.g., LEDs, OLEDs), an electronic display 18 may display images generated by the processing core complex 12.

[0051] In addition to instructions, the storage device(s) 14 may store data to be processed by the processing core complex 12. Thus, in some embodiments, the storage device(s) 14 may include one or more tangible non-transitory computer-readable media. The storage device(s) 14 may be volatile and / or non-volatile. For example, the storage device(s) 14 may include random access memory (RAM) and / or read-only memory (ROM), re-writable non-volatile memory such as flash memory, hard drives, optical disks, or any combination thereof.

[0052] As shown, processing core complex 12 is also operatively coupled to communication interface(s) 16. In some embodiments, communication interface(s) 16 may facilitate communicating data with another electronic device and / or network. For example, communication interface(s) 16 (e.g., a radio frequency system) may enable electronic device 10 to be communicatively coupled to a personal area network (PAN), such as a Bluetooth® network, a local area network (LAN), such as a 1622.11x Wi-Fi® network, and / or a wide area network (WAN), such as a 4G or Long Term Evolution (LTE) cellular network.

[0053] Additionally, as shown, processing core complex 12 is also operably coupled to a power source 22. In some embodiments, power source 22 can provide power to processing core complex 12 and / or one or more components within electronic device 10, such as electronic display 18. Thus, power source 22 may include any suitable energy source, such as a rechargeable lithium polymer (Li-poly) battery and / or an alternating current (AC) power converter.

[0054] As shown, electronic device 10 is also operatively coupled to one or more input structures 20. In some embodiments, input structure 20 can facilitate user interaction with electronic device 10, for example, by receiving user input. Thus, input structure 20 may include buttons, a keyboard, a mouse, a trackpad, etc. Additionally, in some embodiments, input structure 20 can include touch-sensing components within electronic display 18. In such embodiments, the touch-sensing components can receive user input by detecting the presence and / or location of an object touching a surface of electronic display 18.

[0055] In addition to enabling user input, electronic display 18 may include a display panel having one or more display pixels. As described above, electronic display 18 may present a visual representation of information, such as an operating system graphical user interface (GUI), an application interface, still images, or video content, by controlling emission of light from the display pixels to display frames based at least in part on corresponding image data. As shown, electronic display 18 is operatively coupled to processing core complex 12. In this manner, electronic display 18 may display frames based at least in part on image data generated by processing core complex 12. Additionally or alternatively, electronic display 18 may display frames based at least in part on image data received via communication interface(s) 16 and / or input structure 20.

[0056] As can be appreciated, the electronic device 10 can take a number of different forms. As shown in FIG. 2, the electronic device 10 can take the form of a watch 30. For purposes of illustration, the watch 30 can be any Apple Watch® model available from Apple Inc. As shown, the watch 30 includes an enclosure 32 (e.g., a housing). In some embodiments, the enclosure 32 can protect the internal components from physical damage and / or shield from electromagnetic interference (e.g., components within a home). A strap 34 can allow the watch 30 to be worn on the arm or wrist. The electronic display 18 can display information regarding the operation of the watch 30. The input structure 20 can enable a user to activate or deactivate the watch 30, navigate the user interface to a home screen, navigate the user interface to user-configurable application screens, activate a voice recognition function, provide volume control, and / or toggle between vibrate and ring modes. As shown, the input structure 20 can be accessed through an opening in the enclosure 32. In some embodiments, input structure 20 may include, for example, an audio jack for connecting to an external device.

[0057] The electronic device 10 may also take the form of a tablet device 40, as shown in FIG. 3. For purposes of illustration, the tablet device 40 may be any iPad® model available from Apple Inc. Depending on the size of the tablet device 40, the tablet device 40 may function as a handheld device, such as a mobile phone. The tablet device 40 includes an enclosure 42 through which the input structure 20 may protrude. In certain embodiments, the input structure 20 may include a hardware keypad (not shown). The enclosure 42 may also enclose the electronic display 18. The input structure 20 may enable a user to interact with a GUI of the tablet device 40. For example, the input structure 20 may enable a user to type Rich Communication Services (RCS) text messages, Short Message Service (SMS) text messages, or make phone calls. The speaker 44 may output received audio signals, and the microphone 46 may capture the user's voice. The tablet device 40 may also include a communication interface 16 that enables the tablet device 40 to connect via a wired connection to another electronic device.

[0058] FIG. 4 illustrates a computer 48 that represents another form that the electronic device 10 may take. For purposes of illustration, the computer 48 may be any Macbook® or iMac® model available from Apple, Inc. It should be understood that the electronic device 10 may also take the form of any other computer, including a desktop computer. The computer 48 illustrated in FIG. 4 includes an electronic display 18 and an input structure 20 that includes a keyboard and a trackpad. The communication interface 16 of the computer 48 may include, for example, a Universal Service Bus (USB) connection.

[0059] In either case, as discussed above, operating electronic device 10 to communicate information by displaying images on its electronic display 18 generally consumes power. Furthermore, as discussed above, electronic device 10 often stores a finite amount of electrical energy. Thus, to facilitate improved power consumption efficiency, in some embodiments, electronic device 10 may include an electronic display 18 that implements in-pixel memory as a way to reduce or eliminate the use of an external frame buffer in displaying images, thus reducing power consumed by using a frame buffer in displaying images, and / or reducing the bandwidth of image data received by electronic display 18. In some cases, an internal frame buffer (e.g., located within electronic display 18, such as in the display driver integrated circuit of electronic display 18) may be used instead of or in addition to in-pixel memory technology. By implementing in-pixel memory or related technology, electronic display 18 may be programmed with smaller bandwidth image data, further enabling power consumption savings. Additionally, an electronic display 18 that uses memory in the pixel or in an on-board frame buffer can have a less complex design than an electronic display 18 without memory in the pixel or without an on-board frame buffer. These advantages can be realized because the pixels retain data sent to them in memory until new image data is written to the memory.

[0060] Similarly, a portion of the image data may program a subset of the pixels associated with the electronic display 18 at a time. The image to be displayed is typically converted into numerical or image data such that the image can be interpreted by the components of the electronic display 18. In this manner, the image data itself may be divided into small "pixel" portions, each of which may correspond to a pixel portion of the electronic display 18, or a pixel portion of a display panel corresponding to the electronic display 18. In some embodiments, the image data is represented by a combination of red, green, and blue light, such that a pixel that appears to have a single color is actually three sub-pixels that emit portions of red, green, and blue light, respectively, to create a single color. In this manner, the numerical value or image data that quantifies the red-green-blue light combination may correspond to a digital luminance level or gray level that relates the luminance intensity (e.g., brightness) of the image data color for those particular sub-pixels. As will be appreciated, the number of gray levels in an image typically depends on the number of bits used to represent the gray levels in a particular electronic display 18, and may be greater than or equal to 2. N where N corresponds to the number of bits used to represent the gray levels. By way of example, in an embodiment in which electronic display 18 uses 8 bits to represent gray levels, the gray levels range from 0 for black or no light to 255 for maximum light and / or full light, for a total of 256 potential gray levels. Similarly, an electronic display 18 using 6 bits can use 64 gray levels to represent the luminance intensity of each subpixel.

[0061] Having memory within the pixels of the electronic display 18 allows image data to be sent to sub-pixels associated with one color without the need to simultaneously send image data to additional sub-pixels associated with a second color. For purposes of this disclosure, the sub-pixels are discussed in terms of red-green-blue color channels, where a color channel is a layer of image data containing gray levels of a single color that, when combined with additional color channels, creates an image of a true or desired color, and the image data for a color channel corresponds to the image data sent to the sub-pixels of the color channel. However, it should be understood that any combination of color channels and / or sub-pixels may be used, such as blue-green-red, cyan-magenta-yellow, and / or cyan-magenta-yellow-black.

[0062] For illustrative purposes, a display system 50 associated with an electronic display 18 that does not implement in-pixel memory and a display system 52 associated with an electronic display 18 that implements in-pixel memory, each of which may be implemented as electronic device 10, are shown in Figure 5. Display system 50 includes a timing controller 54 for receiving image data 56, a frame buffer 58, a row driver 60, a column driver 62 communicatively coupled to timing controller 54 via communication link 64, and a pixel array 66 that receives control signals from column driver 62 and row driver 60 to create images on electronic display 18. Display system 52 further includes a timing controller 54 for receiving image data 56, a row driver 60, a column driver 62 communicatively coupled to timing controller 54 via communication link 68, and a pixel array 69 that implements in-pixel memory technology that receives control signals from column driver 62 and row driver 60 to create images on electronic display 18.

[0063] In preparation for displaying an image, the display system 50 may receive image data 56 at a timing controller 54. The timing controller 54 may receive and use the image data 56 to determine clock and / or control signals to control the provision of the image data 56 to a pixel array 66 via column drivers 62 and row drivers 60. Additionally or alternatively, in some embodiments, the image data 56 is received by a frame buffer 58.

[0064] In either case, the frame buffer 58 may serve as an external storage device for the timing controller 54 to store the image data 56 before being output to the column drivers 62 and / or row drivers 60. The timing controller 54 may transmit the image data 56 from the frame buffer 58 to the column drivers 62 and / or row drivers 60 via a communication link 64.

[0065] The communication link 64 is large enough (e.g., as determined by the image data transmission bandwidth) to simultaneously transmit image data 56 associated with all channels, e.g., image data 56 associated with the red, green, and blue channels, to the row driver 60 and / or column driver 62. In this manner, the communication link 64 simultaneously communicates image data 56 associated with each pixel of the pixel array 66 for the red, green, and blue channels. The column driver 62 and row driver 60 can transmit control signals based on the image data 56 to the pixel array 66. In response to the control signals, the pixel array 66 emits light at various luminous intensities or brightnesses, e.g., indicated by gray levels ranging from 0 to 255, to communicate an image.

[0066] However, the display system 52 receives image data 56 at a timing controller 54. The timing controller 54 may use the image data 56 to determine clock signals used to provide the image data 56 to an in-pixel memory pixel array 69. The timing controller 54 transmits the image data 56 to row drivers 60 and / or column drivers 62 to program the memory of the pixel array 69 with digital data signals associated with the image data 56, which indicate the luminance / gray level of the pixels in the pixel array 69.

[0067] By implementing the in-pixel memory systems and methods, the display system 52 may reduce the bandwidth of signals communicated over the communication link 68, for example, when compared to the bandwidth of signals communicated over the communication link 64. In some examples, a single channel of image data 56 may be transmitted over the communication link 64 (e.g., the red channel) as opposed to all channels being transmitted simultaneously to the pixel array 66 (e.g., the red-green-blue channels). In this manner, the communication link 68 communicates image data 56 associated with each pixel of the pixel array 66 for the red, green, and blue channels at different times, causing a reduction in the overall bandwidth of the signals used to communicate the image data 56. Reducing the overall bandwidth of the communication link 68 may lead to a reduction in power consumption of the electronic device 10, as processing less data (e.g., a single channel of image data) at a given time may consume fewer processing resources than processing more data (e.g., three channels of image data).

[0068] To further illustrate the operation of a pixel array 69 with in-pixel memory to display an image, an example of a display system 52A implementing in-pixel memory is shown in FIG. 6, having a timing controller 54 linked to row drivers 60 and / or column drivers 62 via communication links 68. The display system 52A includes a pixel array 69 with L rows by M columns, where one or more pixels 70 each include a sub-pixel 72 corresponding to a color channel of the electronic display 18, e.g., a red sub-pixel 72R, a green sub-pixel 72G, and a blue sub-pixel 72B, each of the sub-pixels 72 including a memory 78 for storing up to N bits, and a driver (DRV) 80 for operating the sub-pixel 72 to emit light, as shown in FIG. 6. It should be understood that the illustrated display system 52A is intended to be illustrative only and not limiting. For example, in some embodiments, pixel array 69 may include sub-pixels 72 that emit varying amounts of cyan, yellow, and magenta light corresponding to cyan-yellow-magenta color channels instead of, or in addition to, red-green-blue color channels.

[0069] In operation of the display system 52A, the timing controller 54 receives image data 56 corresponding to a next image to be displayed on an electronic display having a pixel array 69. The timing controller 54 generates control and / or clock signals responsive to the image data 56 and sends signals associated with active rows of pixels 70 to a row driver 60 and signals associated with active columns of pixels 70 to a column driver 62. The row driver 60 generates emission control signals 82 and write control signals 84 for each red-green-blue (RGB) channel in response to signals associated with the image data 56 sent from the timing controller 54. The column driver 62 also generates image data 86 that is sent to the memory 78 for each of the pixels 70 in response to signals associated with the image data 56 sent from the timing controller 54. While the column driver 62 can generate the image data 86 in response to the image data 56 and / or signals associated with the image data 56 in some embodiments, in some embodiments the image data 56 is sent to each of the pixels 70 as the image data 86. The column driver 62 generates data of size N bits for each sub-pixel 72, matching the size of the memory 78 which is also N bits in size.

[0070] In general, through the transmission of emission control signals 82, write control signals 84, and image data 86, the pixels 70 are operated to emit light to create an image on the electronic display 18. Each of the pixels 70 receives a respective emission control signal 88 of the emission control signals 82, three respective write control signals 90 of the write control signals 84, and respective image data 92 for the channels of the pixel 70, e.g., N bits of image data for a red channel (image data-R) 92R, N bits of image data for a green channel (image data-G) 92G, and N bits of image data for a blue channel (image data-B) 92B, transmitted from the row driver 60. The write control signals 84 can enable the memory 78 of the pixel 70 to be programmed by the image data 86 transmitted by the column driver 62. Furthermore, the respective emission control signals 88 of the emission control signals 82 can control whether the pixel 70 can emit light. The emission control signals 88 are transmitted to each pixel 70 in the column. The enabled emission control signal 88 can activate the driver 80 to transmit digital image data 92 from the memory 78 to light emitting diodes (LEDs) associated with light emitting portions of the pixel 70, e.g., the sub-pixels 72 that use analog data signals to cause the pixel 70 to emit light. In the illustrated embodiment, a column of pixels 70, e.g., pixels 70R1C1, R2C1, R3C1 through RLC1 in a first column, receive the same emission control signal 88. The image data 92 transmitted to the pixel 70 causes the pixel 70 to emit light of an overall color and / or brightness.

[0071] The perceived color emitted from pixel 70 varies based on the light emitted from each of the three channels, i.e., each sub-pixel, of pixel 70. For example, operating each sub-pixel to output a luminance of 0 may cause pixel 70 to appear off, while operating red sub-pixel 72R to output a luminance of 100%, green sub-pixel 72G to output a luminance of 50%, and blue sub-pixel 72B to output a luminance of 0% may cause pixel 70 to emit an overall color that is perceived as orange. Data is thus rendered and transmitted to each sub-pixel 72 to correspond to the individual color channels of pixel 70.

[0072] Implementing memory 78 within pixel 70 allows image data 92 to be programmed into pixel 70 prior to the desired presentation time of the image. In some embodiments, an enabled write control signal 90 can cause memory 78 to clear (or overwrite) the stored image data 92, while not enabling write control signal 90 can cause memory 78 to retain the programmed image data 92. For example, to write new image data, write control signal -R 90R can clear memory 78 of red sub-pixel 72R and enable the writing of new image data, image data-R 92R, and loading into memory 78. In this example, write control signal -B 90B is not enabled, so memory 78 of blue sub-pixel 72B is not cleared and continues to retain its programmed image data, image data-B 92B. Having the memory 78 within the pixel 70 is an improvement in display and processing technology since the memory 78 allows a portion of the image data 86 to be written at a time rather than an entire frame of data, improving the use of the bandwidth available for communicating image data for display on the electronic display 18, as well as an improvement in the power consumption used to process the image data, as described above with reference to FIG. 5.

[0073] In the pixel array 69, image data 86 is communicated from the column driver 62 to the sub-pixels 72 via a direct communication coupling, such as a communication coupling 94. In some embodiments, a multiplexing circuit may be used to control the transmission of image data 86 to the sub-pixels 72, such that a multiplexing control signal may be used by the column driver 62 to arbitrate the transmission of image data 98 ​​to the sub-pixels 72, such that, for example, a red sub-pixel 72R may not receive image data 98 ​​at the same time as a blue sub-pixel 72B or a green sub-pixel 72G.

[0074] To elaborate, an exemplary embodiment of a display system 52B associated with an electronic display 18 implementing in-pixel memory is shown in FIG. 7, including a timing controller 54 linked to row drivers 60 and column drivers 62 via communication links 68. Similar to the display system 52A shown in FIG. 6, the display system 52B includes an L row by M column pixel array 69, where one or more pixels 70 each include sub-pixels 72, e.g., a red sub-pixel 72R, a green sub-pixel 72G, and a blue sub-pixel 72B, each of which includes a memory 78 for storing up to N bits, and a driver (DRV) 80 for operating the sub-pixels 72 to emit light, as shown in FIG. 6. It should be understood that the illustrated display system 52B is intended to be illustrative only and not limiting. The functions and / or descriptions of the display system 52 common to both FIG. 6 and FIG. 7 are relied upon herein.

[0075] In the exemplary embodiment of the display system 52B of FIG. 7, the pixel array 69 includes a multiplexing circuit 96 that receives image data 98 ​​of size N bits from the column driver 62. The multiplexing circuit 96 is responsive to a respective multiplexing control signal (MUX control signal) 100 of the multiplexing control signal 101. The MUX control signal 100 can cause the multiplexing circuit 96 to output data to the sub-pixels 72 of the pixel 70. In this manner, the column driver 62, through emission of the MUX control signal 100, can be operated to program the sub-pixels 72 (e.g., one color channel) of the pixel 70, for example, via the communicative coupling 94. Various embodiments of the sub-pixel 72 circuit can be used for the pixel array 69.

[0076] An example of an embodiment of a sub-pixel 72 implementing in-pixel memory technology includes a memory 78, a driver 80, a current source 102, an LED 103, a switch 104, and a counter 105, with the sub-pixel 72 receiving various signals including image data 98, a bit plane clock 106, a reset signal 108, a common voltage 110, a first reference voltage 112, a second reference voltage 114, and a data clock 116, as shown in FIG. 8. It should be understood that the illustrated sub-pixel 72 is intended to be illustrative only and not limiting. For example, the memory 78 is illustrated as a 12-bit register, but may be any suitable memory circuit storing any suitable number of bits.

[0077] The illustrated sub-pixels 72 may emit light according to a binary pulse width modulation emission scheme. To illustrate the operation of the sub-pixels 72, image data 98 ​​may be transmitted, for example, from the column driver 62 to the memory 78. Additionally or alternatively, the image data 92, the image data 56, or any suitable image data may be transmitted to the memory 78 for storage. Upon receiving the image data 98, the memory 78 stores the image data 98 ​​clocked in by the data clock 116. The image data 98 ​​may be represented by binary data such that any given bit may be equal to a zero "0" or a one "1", where a zero corresponds to a system logic low voltage value and a one corresponds to a system logic high voltage value. The memory 78 may output the image data 98 ​​to the switch 104 bit by bit, for example, from the least significant bit to the most significant bit, according to a clock signal generated by a combination of the counter 105 and the bit plane clock 106.

[0078] As shown, the bitplane clock 106 has a time period that increases over time to correspond to the level of influence of a particular bit in the image data 98. In this manner, the least significant bits of the image data 98 ​​may be associated with a shorter clock time period than the most significant bits of the image data 98.

[0079] When memory 78 outputs image data 98, for example, on the rising edge of bit plane clock 106, image data 98 ​​operates switch 104 to open or close. A 0 bit opens switch 104 and causes LED 103 to emit no light, while a 1 bit closes switch 104 and causes LED 103 to emit light. The operation of switch 104 occurs at various light emission periods as a way to modulate the light emission from LED 103, changing the perceived brightness of subpixel 72 as the modulation changes. Thus, depending on the relationship of image data 98 ​​output from memory 78 to switch 104, image data 98 ​​equal to "000000000000" may cause LED 103 to emit no light, while image data 98 ​​equal to "101011000111" may cause LED 103 to be perceived as brighter. Image data 98 ​​equal to "101011000111" may be perceived as brighter because subpixel 72 operates to emit light in response to each logic high value "1", which is the value that enables switch 104 to emit light. The more times switch 104 is actuated during the light emission period, the brighter the pixel is perceived as because more light is emitted over time (e.g., light is emitted in response to a "1" and not in response to a "0"). In this manner, image data 98 ​​may be derived from the desired gray level of subpixel 72 without being an exact binary representation of the gray level. However, it should be noted that there may be scenarios in which the desired gray level of subpixel 72 actually equals the binary representation transmitted via image data 98.

[0080] When the switch 104 is closed, an electrical connection is created between the common voltage 110 and the first reference voltage 112. This allows current from the current source 102 to be sent through the LED 103 to emit light from the sub-pixel 72. Thus, the light emission period of the sub-pixel 72 can be altered to control the perceived light emitted from the sub-pixel 72, the light emission period corresponding to the bit arrangement (e.g., most significant bit, least significant bit) of the image data 98 ​​stored in the memory 78, the closer a bit of the image data 98 ​​is to the most significant bit position, the longer the light emission period corresponding to that bit of the image data 98. When the counter 105 counts up to 11, the counter 105 restarts, for example, causing the bit plane clock 106 to restart its clock interval to correspond to the next least significant bit after the last most significant bit emission period. Additionally or alternatively, in some embodiments, a second reference voltage 114 is included to alter the overall current value used to control the light emitted from the LED 103. For example, the second reference voltage 114 may increase the sensitivity of the LED 103 to changes in current such that a lower current value may be used to cause the LED 103 to emit light or enable the LED 103.

[0081] This lighting scheme is referred to as a binary pulse width modulation lighting scheme for the subpixel 72 because the image data 98 ​​is binary data selected to modulate the lighting from the subpixel 72 to vary the perceived brightness of the subpixel 72. Graph 118 illustrates the lighting period of the subpixel 72 caused by the binary pulse width modulation lighting scheme. In the binary pulse width modulation lighting scheme, the subpixel 72 is operated to vary the perceived brightness of the light emitted by varying the lighting period of the light. As shown in graph 118, the image data 98 ​​received by the subpixel 72 is represented by five bits of binary data. Thus, when the image data 98 ​​is equal to 01111, the subpixel 72 emits light corresponding to a first range 120 having a lighting period 124A of the least significant bit and lighting periods 124B, 124C, and 124D of the subsequent bits. In this embodiment, the least significant bit of the image data 98 ​​from the memory 78 operates the switch 104 first, so that the least significant bit corresponds in time to the first lighting period 124A. Thus, light emission temporarily ceases during the transmission of a bit to operate switch 104, as can be seen by the absence of an emission period between first emission period 124A and emission period 124B. Furthermore, when image data 98 ​​is equal to 11111, the emission period of subpixel 72 corresponds to a second range 122 that is equal to first range 120 plus the last emission period 124E that corresponds to the most significant bit (e.g., because the most significant bit is now effective as a 1).

[0082] When following a binary pulse width modulated lighting scheme, image data 98 ​​having data of 01111 will be perceived as less bright than image data 98 ​​having data of 11111 due to how light is perceived by a viewer of electronic display 18. This is because the more lighting periods that occur during a full lighting cycle (e.g., as represented by all 1's in image data 98 ​​being 11111), the brighter the light emitted from subpixel 72 will be perceived to be. Thus, if subpixel 72 is emitted for the first range 120 plus the final lighting period 124E (e.g., if the most significant bit of image data 98 ​​is 1), subpixel 72 may be perceived as brighter on electronic display 18 than subpixel 72 that only emits in first range 120.

[0083] Another example of an embodiment of a subpixel 72 is shown in Figure 9, including a memory 78, a driver 80, a current source 102, an LED 103, a switch 104, a counter 130, and a comparator 132, where the subpixel 72 receives various signals including image data 98, a gray level clock 134, a common voltage 110, a first reference voltage 112, a second reference voltage 114, and a data clock 116. It should be understood that the illustrated subpixel 72 is intended to be illustrative only and not limiting. For example, the memory 78 is illustrated as an 8-bit register, but may be any suitable memory circuit that stores any suitable number of bits.

[0084] The illustrated subpixels 72 having in-pixel memory can emit light according to a single pulse width emission scheme. To illustrate the operation of the subpixels 72, image data 98 ​​is transmitted, for example, from the column driver 62 to the memory 78 for storage. Additionally or alternatively, the image data 92, the image data 56, or any suitable image data may be transmitted to the memory 78 for storage. In some embodiments, the image data 98 ​​may be clocked into the memory 78 by the data clock 116, for example, on a rising edge of the data clock 116. The image data 98 ​​communicated to the subpixels 72 may correspond to a desired gray level at which the subpixels 72 emit light. Using the image data 98 ​​stored in the memory 78, the comparator 132 determines whether the current number represented by the counter 130 is less than or equal to the image data 98 ​​in the memory 78. In other words, the counter 130 counts up to the number indicated by the image data 98, and in response to satisfying a condition that the number represented by the counter 130 is, for example, less than or equal to the number indicated by the image data 98, the comparator 132 outputs a control signal to close the switch 104 if the condition is satisfied. If the condition is not satisfied, the comparator 132 does not output a control signal and opens the switch 104. Additionally or alternatively, the comparator 132 activates a deactivation control signal to open the switch 104. For example, if the memory 78 stores a binary sequence of 10110101, which corresponds to the number 181, the comparator 132 checks whether the counter 130 has counted up to the number 181, and if the counter 130 exceeds the number 181, the comparator 132 sends a signal to open the switch 104 to stop emitting light.

[0085] When the switch 104 is closed, an electrical connection is created between the common voltage 110 and the first reference voltage 112. This causes current from the current source 102 to be sent through the LED 103, causing light to be emitted from the sub-pixel 72. Thus, the light emitting period of the sub-pixel 72 can be altered to control the perceived light emitted from the sub-pixel 72 by altering the number indicated by the image data 98. Additionally or alternatively, in some embodiments, the second reference voltage 114 is included to alter the overall current value used to control the light emitted from the LED 103. For example, the second reference voltage 114 can increase the sensitivity of the LED 103 to current changes such that a lower current value can be used to cause the LED 103 to emit light or enable the LED 103.

[0086] Counter 130 counts from 0 to 255 and increments based on a gray level clock 134, e.g., a rising edge of gray level clock 134. The period of gray level clock 134 represents the time difference between the increments of gray levels of electronic display 18, e.g., the difference in emission between the emission of gray level 100 and the emission of gray level 101. In this manner, counter 130 counts up to the number represented by image data 98 ​​stored in memory 78 and then emits light for a time period corresponding to the desired gray level. Counter 130 may continue counting beyond the number represented by image data 98 ​​stored in memory 78 to a maximum value, e.g., 255, or may restart counting at a minimum value, e.g., 0. Thus, in some embodiments, the counting range of counter 130 may be defined through the design of counter 130, e.g., through several registers and / or logic components included in counter 130. By the time counter 130 restarts counting at zero, additional image data 98 ​​may be stored in memory 78 and comparison of the next emission period of the gray levels associated with the additional image data 98 ​​may begin.

[0087] By following this lighting scheme, the sub-pixel 72 can follow a single pulse-width modulated lighting scheme. A representation of the emission of light from the sub-pixel 72 according to the single pulse-width modulated lighting scheme is shown in graph 136. Graph 136 includes an actual lighting period 138 and a total lighting period 140. The total lighting period 140 corresponds to the total length of the lighting represented by a maximum number transmitted as image data 98, for example 255, and may correspond to a maximum perceived brightness of the light emitted from the sub-pixel 72. The actual lighting period 138 corresponds to a period during which the sub-pixel 72 emitted light, for example according to a number less than the maximum value transmitted as image data 98 ​​from the counter 130. The counter 130 increments from 0 to 255 in response to the time represented by the total lighting period 140, while the comparator 132 allows the light to be emitted for the time represented by the actual lighting period 138. In this way, the sub-pixel 72 can emit light of various perceived brightnesses.

[0088] Another example of an embodiment of a subpixel 72 is shown in FIG. 10, including a memory 78, a driver 80, a current source 102, an LED 103, a switch 104, an accumulator 150, and a summer 152, where the subpixel 72 receives various signals including an emission clock 154, image data 98, a common voltage 110, a first reference voltage 112, a second reference voltage 114, and a data clock 116. It should be understood that the illustrated subpixel 72 is intended to be illustrative only and not limiting. For example, the memory 78 is illustrated as being capable of storing 8 bits of image data 98, but may be any suitable memory circuitry storing any suitable number of bits.

[0089] The illustrated subpixel 72 with in-pixel memory can be illuminated according to a pulse density modulated illumination scheme. In a pulse density modulated illumination scheme, each pulse has a fixed illumination and a fixed illumination duration, but with a variable separation interval between the pulses, with brighter light emitted from the subpixel 72 corresponding to a greater number of pulses during the same period. To illustrate the operation of the subpixel 72 in a pulse density modulated illumination scheme, image data 98 ​​is transmitted, for example, from the column driver 62 to the memory 78 for storage. Additionally or alternatively, the image data 92, the image data 56, or any suitable image data may be transmitted to the memory 78 for storage. The image data 98 ​​transmitted to the subpixel 72 is generated based at least on the desired gray level at which the subpixel 72 emits light.

[0090] Upon receiving the image data 98, the memory 78 stores the image data 98 ​​according to the data clock 116, e.g., loads a bit of the image data 98 ​​bit by bit on each rising edge of the data clock 116. The memory 78 outputs the image data 98 ​​which is added to the binary data stored in the accumulator 150. Although the accumulator 150 is shown as an 8-bit accumulator, it should be understood that any suitable accumulator or register may be used to temporarily store data. The adder 152 may perform a binary addition of the image data 98 ​​and the binary data of the accumulator 150 in response to an emission clock 154, e.g., a rising edge of the emission clock 154. The sum from the adder 152 is sent for storage in the accumulator 150 for use with the next image data 98, and the carry bit is used to open or close the switch 104.

[0091] When the switch 104 is closed, an electrical connection is created between the common voltage 110 and the first reference voltage 112. This allows current from the current source 102 to be sent through the LED 103, generally allowing light to be emitted from the subpixel 72. In this manner, a variable separation interval between the pulses generated by the emission clock 154 and the adder 152 sending the carry bit from the summation can contribute to varying the light emission from the subpixel 72. Thus, the interval separating the emission pulses of the subpixel 72 can be varied to control the light emitted from the subpixel 72, with brighter light being emitted in response to smaller intervals separating the pulses (e.g., a higher density of pulses corresponds to a brighter perceived light emitted from the LED 103). Additionally or alternatively, in some embodiments, the second reference voltage 114 is included to modify the overall current value used to control the light emitted from the LED 103. For example, the second reference voltage 114 may increase the sensitivity of the LED 103 to changes in current such that a lower current value may be used to cause the LED 103 to emit light or enable the LED 103.

[0092] Graph 156 illustrates the luminance pulses and variable separation intervals between the pulses caused by a pulse density modulated luminance scheme. In a pulse density modulated luminance scheme, the subpixel 72 emits pulses separated by non-emitting intervals of different lengths to vary the total light emitted from the subpixel 72. As shown in graph 156, image data 98 ​​can cause the subpixel to emit luminance pulses 158 and not emit light for a time period of non-emitting interval 160. For example, luminance pulses 162 have shorter non-emitting intervals separating each luminance pulse than luminance interval 160, and thus, the LED 103 of the subpixel 72 can emit light of luminance pulses 162 that is perceived as brighter than the light emitted from the LED 103 by the luminance pulses 158.

[0093] In summary, therefore, the use of in-pixel memory techniques allows the timing controller 54 to program image data 98 ​​into the display system 52 in smaller portions of the image data 98, rather than simultaneously programming the image data into all of the sub-pixels 72. For purposes of illustration, a timing diagram of signals transmitted within the display system 52 in preparation for transmitting the image data for storage in the one or more memories 78 illustrates a red image data transmission period 174R, a green image data transmission period 174G, a blue image data transmission period 174B, one or more copy periods 176, and one or more valid periods 178, which is shown in FIG.

[0094] As shown, the column driver 62 may receive a signal to initiate copying of red data to one or more memories 78 for one or more red subpixels 72R. Upon receiving the signal, the column driver 62 may enter a copy period 176 in preparation for transmitting the red data to the red subpixels 72R. During the copy period 176, the column driver 62 may prepare to enable a multiplexing circuit 96 associated with a pixel 70 of the display system 52, for example via an internal circuit such as a row decoder. The column driver 62 or other suitable circuit may operate the multiplexing circuit 96 to allow programming of the memory 78 for the red subpixels 72R, and may operate the multiplexing circuit 96 to disallow programming of the memories 78 for the blue and green subpixels 72B and 72G, for example by enabling and / or disabling a multiplexing control signal 101. In this manner, red image data may be transmitted and stored in the memory 78 corresponding to the red subpixels 72R. At the end of the copy period 176, the column driver 62 may transmit red image data to the red sub-pixels 72R during a red image data transmission period 174R. The transmitted red image data is sent to the respective memories 78 of the red sub-pixels 72R to be programmed with the new red image data. Once the red image data has been transmitted to the red sub-pixels 72R, the column driver 62 and row decoder can repeat the process described for the green and blue image data, allowing selective programming of the various color channels associated with each pixel 70.

[0095] In general, the subpixels 72 are operated to emit light by receiving one or more control signals, such as from a column driver 62 and / or a row driver 60. The row driver 60 and column driver 62 can control the operation of the subpixels 72 by using the control signals to control components of the subpixels 72, such as the current drive of the subpixels 72. As mentioned above, the column driver 62 can be responsible for sending at least image data to the subpixels 72, and the row driver 60 can be responsible for sending one or more control signals to the subpixels 72 to control the emission of light. The subpixels 72 can include any suitable controllable element responsive to these control signals and image data, such as a transistor, one example of which is a metal oxide semiconductor field effect transistor (MOSFET). However, any other suitable type of controllable element can also be used, including thin film transistors (TFTs), p-type and / or n-type MOSFETs, as well as other transistor types.

[0096] In some embodiments, row drivers 60 and / or column drivers 62 may perform processes to initialize, charge, program, and illuminate subpixels 72 to prepare them for displaying images on the electronic display 18. By performing these processes, row drivers 60 and / or column drivers 62 of the electronic display 18 may initialize the subpixels 72 to be programmed, charge capacitors for programming, program the subpixels 72 with signals corresponding to drive currents designed to cause the subpixels 72 to emit light, and allow image data to control the emission of light from the subpixels 72. In some embodiments, a current drive may be responsible for generating the drive currents within the subpixels 72.

[0097] To help illustrate the subpixel circuitry with current drive, one embodiment of a subpixel 72 is shown in FIG. 12 including an initialization transistor (MINI) 220, a drive transistor (MDR) 222, a select transistor (MSEL) 224, a switching transistor (MS) 226, a reset transistor (MRST) 228, a light emitting portion such as an LED 230, a capacitor 232, and an auto-zero transistor (MAZ) 234. It should be understood that the subpixel 72 shown is intended to be illustrative and not limiting. For example, although the row driver 60 and column driver 62 are described herein as outputting image data and control signals related to displaying a next image on the electronic display 18, it should be understood that any suitable components may be used to emit the control signals to display the next image. Furthermore, the circuitry shown in FIG. 12 is merely one example of circuitry that may be implemented within the subpixel 72 and / or pixel 70 and should not be construed as limiting. For example, a voltage drive circuit (e.g., a voltage drive) may be used with the subpixel 72 instead of a current drive circuit (e.g., a current drive).

[0098] During the initialization process, the row driver 60 can enable a reset control (CSreset) signal 235 and disable an auto-zero control (CSauto.zero) signal 237. The CSreset signal 235 can be sent to the MRST 228. In response to receiving the CSreset signal 235, the MRST 228 can activate and allow residual signals from the display of the first image to be discharged from the subpixels 72. These residual signals can be discharged to a node coupled to a voltage reset (Vreset) signal 239 designed to facilitate the discharge of residual signals (e.g., 0 volts), such as a system ground or a system reference voltage. Additionally, the row driver 60 can enable a select control (CSselect) signal 241. The CSselect signal 241 can be sent to the MSEL 224. In response to receiving the CSselect signal 241, the MSEL 224 can activate and allow a voltage data (Vdata) signal 242 to be sent to the node of the capacitor 232. To complete the initialization process, the row driver 60 can also enable an initialization control (CSinitialization) signal 243. The CSinitialization signal 243 can be sent to the MINI 220. In response to receiving the CSinitialization signal 243, the MINI 220 can activate and allow the initialization of the capacitor 232 to occur. In this state, the capacitor 232 can be charged with a voltage corresponding to the voltage difference between the Vdata signal 242 and the initialization voltage (Vinitialization) signal 244. Thus, the voltage difference may be programmed by selecting different values ​​for the Vdata signal 242 and the Vinitialization signal 244 based on the desired voltage level for initializing the capacitor 232 while protecting the subpixel 72 from receiving additional signals that may interfere with the initialization or cause unintended light emission from the LED 230. The row driver 60 can continue the initialization process until the row driver 60 disables the CSinitialization signal 243 to deactivate the MINI 220.

[0099] After the initialization process, the row driver 60 may perform a charging process while the MINI 220 and the MRST 228 are inactive. During the charging process, the MAZ 234 and the MINI 220 remain inactive and the MSEL 224 remains activated. While the MSEL 224 is activated, the capacitor 232 is charged based on the Vdata signal 242 and the Vreference signal 246. Charging the capacitor 232 may enable a drive current to be sent through the MDR 222 even while the MSEL 224 is inactive. In some embodiments, the capacitor 232 stores the voltage value of the Vdata signal 242 so that the MDR 222 remains active throughout the light emission process, enabling the subpixel 72 to generate a constant drive current through the LED 230 for light emission. In this way, the subpixel 72 has a current drive since the drive current enables the emission of light from the LED 230 while the MS 226 is active.

[0100] During the programming process, the row driver 60 may enable the CSauto.zero signal 237 to cause activation of the MAZ 234. When the MAZ 234 is activated, an electrical coupling is formed between the node of the capacitor 232 and the source node of the MS 226 such that the voltage value of the source node of the MS 226 is equal to the voltage value of the gate voltage (Vg) 245 of the MDR 222. After a period of time sufficient to increase the voltage of the source node of the MS 226 to equal the voltage value of Vg 245, the row driver 60 may disable the CSauto.zero signal 237 to deactivate the MAZ 234. In this state, the subpixel 72 is programmed with an electrical signal ready to be sent to the LED 230 upon activation of the MS 226. That is, in this state, the subpixel 72 is ready to send a drive current generated via a programmed signal in response to the CSimage.data signal 247 enabling the MS 226.

[0101] Once the programming process is complete, the row driver 60 can operate the sub-pixels 72 to perform a light-emitting process. During the light-emitting process, the sub-pixels 72 emit light according to, for example, an image data control (CSimage.data) signal 247 sent from the column driver 62 to the MS226. The sub-pixels 72 can receive the CSimage.data signal 247 from any suitable component of the electronic device 10 that can generate and / or generate image data for display via the sub-pixels 72. In response to, for example, an enabled CSimage.data signal 247, the MS226 activates a logic high bit of a voltage having a sufficient value to switch the MS226 (e.g., large enough to overcome a programmed voltage at the source node of the MS226 and a threshold voltage of the MS226). Upon activation of the MS226, the voltage stored at the source node of the MS226 transmits as a drive current through the LED 230. When the drive current exceeds the threshold voltage of the LED 230, the threshold voltage of the LED represents a voltage value above which light is emitted from the LED, and thus the LED 230 can emit light based at least in part on the value of the drive current.

[0102] As will be appreciated, the CSimage.data signal 247 may be binary and / or digital data representing image data used to manipulate the sub-pixels 72 to emit light at particular gray levels to convey an image (e.g., a second image). As previously discussed, the sub-pixels 72 may operate according to a variety of lighting schemes and thus the CSimage.data signal 247 sent to the MS 226 may vary between embodiments. However, across embodiments, the CSimage.data signal 247 is derived from an image displayed on the display. Additionally, enabling and / or disabling the CSimage.data signal 247 at least partially causes the LEDs 230 to emit or not emit light, thus allowing the CSimage.data signal 247 to modulate the emission of light from the sub-pixels 72.

[0103] Once the emission process is complete, row driver 60 can disable CSselect signal 241 and enable CSreset signal 235, causing deactivation of MSEL 224 and activation of MRST 228. With MSEL 224 deactivated, subpixel 72 is no longer operable to emit light because capacitor 232 no longer receives charge and any residual signal from the emission process is drained by the activation of MRST 228.

[0104] The described subpixel 72 is considered a current drive pixel because the subpixel 72 has a primary current that drives the LED 230 to emit light or not emit light. The primary or drive current is transmitted via the MS 226 in response to various control signals that control the timing of light emission from the subpixel 72. The described subpixel 72 circuit may have certain advantages including a manner in which a digital output may control light emission from the LED 230 without further conversion to an analog output. Additionally, the inclusion of the capacitor 232 may compensate for changes in threshold voltages associated with the subpixel 72 from substrate bias effects, a side effect associated with applying voltages to the gates of some transistors.

[0105] Further improvements to the subpixel 72 may occur if a voltage drive is included in addition to the current drive structure of the subpixel 72 of FIG. 12. At the beginning of the light emission process, the voltage drive may be enabled for a period of time to provide amplification to the anode of the LED 230 to facilitate the initial emission of light, and allow light emission using a weaker drive current without amplification of the anode of the LED 230. A smaller drive current value may be used to drive the LED 230 to emit light because the LED 230 may be operated in a forward bias region, or the operating region of the LED 230 is more sensitive to small changes in current due to the amplification provided by the voltage drive.

[0106] For purposes of illustration, a second embodiment of a subpixel 72 having a hybrid drive including a current drive 270 and a voltage drive 272 and having a memory 78 is shown in Figure 13. It should be understood that the subpixel 72 shown is intended to be exemplary and not limiting. For example, although the current drive 270 and the voltage drive 272 are shown as separate elements within the subpixel 72, one or both of the drives may be included in the driver 80 discussed above.

[0107] The row driver 60 and / or column driver 62 can operate the sub-pixels 72 to emit light by enabling and / or disabling the control signals. The row driver 60 and / or column driver 62 can use the control signals to perform various processes to cause the sub-pixels 72 to emit light, including initialization processes, charging processes, programming processes, and emitting processes for the sub-pixels 72, to enable the display of image data corresponding to an image to be displayed.

[0108] To help illustrate the interaction of the control signals emitted by the row driver 60 and / or column driver 62 with the subpixels 72 of Figure 13, a timing diagram 279 is shown in Figure 14 corresponding to signals used for display including the Vdata signal 242, the CSinitialization signal 243, the CSselect signal 241, the CSauto.zero signal 237, the CSimage.data signal 247, the CSselect signal 280, and the CSreset signal 235. It should be understood that the timing diagram is intended to be illustrative and not limiting, and for example, the control signals shown in Figure 14 may represent more or less control signals than are implemented in the subpixels 72.

[0109] The initialization process described above corresponds to a time period 282. During the time period 282, the row driver 60 may provide a high voltage on the Vdata signal 242, may enable the CSinitialization signal 243 for the duration of the initialization process, may enable the CSselect signal 241, may disable the CSauto.zero signal 237, may disable the CSreset signal 235, and may disable the CSselect signal 280 for a time period 284.

[0110] 13, the control signals output by the row driver 60 to perform the initialization process cause the activation and / or deactivation of various switching elements, as previously described. By implementing the control signals of FIG. 14 in the subpixel 72, the MINI 220 is activated in response to an enabled CSinitialization signal 243, the MSEL 224 is activated in response to an enabled CSselect signal 241, the MAZ 234 is deactivated in response to a disabled CSauto.zero signal 237, the MRST 228 is deactivated in response to a disabled CSreset signal 235, and the voltage drive switching element (MVD) 285 is deactivated in response to a disabled CSselect signal 280. This configuration allows the difference in voltage value between the Vdata signal 242 and the Vinitialization signal 244 to charge the capacitor 232. The row driver 60 may continue the initialization process until the row driver 60 disables the CSinitialization signal 243, deactivating the MINI 220 and thus terminating the initialization.

[0111] 14, the timing diagram 279 shows that after the initialization process, the row driver 60 disables the CSinitialization signal 243 and performs a charging process to the subpixels 72. During the charging process, the Vdata signal 242, the CSauto.zero signal 237, the CSimage.data signal 247, the CSselect signal 280, and the CSreset signal 235 remain in their previous states. The timing diagram 279 shows the Vdata signal 242 at a high voltage level on the subpixel 72 circuit (DVDD), corresponding to a logic high value in the binary data of the subpixels 72 and / or the electronic device 10, for example. In some embodiments, DVDD is equal to the voltage value of the Vreference signal 246.

[0112] 13, the control signals output by the row driver 60 activate and / or deactivate various switching elements to perform the charging process. Upon disabling the CSinitialization signal 243 and deactivating the MINI 220, the capacitor 232 charges based on the Vdata signal 242 and the Vreference signal 246. Charging the capacitor 232 may allow the current drive 270 to continue to be used during the light-emitting process even while the MSEL 224 is deactivated. In some embodiments, the capacitor 232 holds the voltage value of the Vdata signal 242 after the charging process so that the MDR 222 can remain active throughout the light-emitting process, allowing the current drive 270 to generate a constant drive current through the LED 230 for light-emitting.

[0113] After a suitable settling period to charge capacitor 232, row driver 60 can perform the programming process. Referring briefly to FIG. 14, to perform the programming process row driver 60 enables CSauto.zero signal 237 for a time period 286 and holds Vinitialization signal 243, Vdata signal 242, CSimage.data signal 247, CSselect signal 280, and CSreset signal 235 in their previous states. As shown, row driver 60 also transmits a ground voltage (GND) as Vdata signal 242 for a time period 288 during the programming process. GND may be equal to zero volts or any suitable ground reference voltage associated with electronic display 18, electronic device 0, and / or subpixel 72.

[0114] Returning to FIG. 13, in response to the enabled CSauto.zero signal 237, MAZ 234 activates. When MAZ 234 activates, an electrical coupling is formed between the node of capacitor 232 and the source node of MS 226 such that the voltage value of the source node of MS 226 is equal to the voltage value of Vg 245. After a time period 286, row driver 60 disables CSauto.zero signal 237 and MAZ 234 deactivates. In this state, subpixel 72 is programmed with an electrical signal ready to be sent to LED 230 upon activation of MS 226. That is, in this state, subpixel 72 is ready to send a drive current generated via a programmed signal in response to CSimage.data signal 247 enabling MS 226. Once the source node of MSEL 226 is programmed with the Vg 245 voltage, the row driver 60 sends a Vdata signal 242 equal to GND and, at the end of the time period 284, disables the CSselect signal 241 to deactivate MSEL 224. Upon completion of the programming process, the row driver 60 can enable and / or disable the control signals to perform the light emission process.

[0115] 14, during the light emission process, the row driver 60 may return the Vdata signal 242 to DVDD, may continue to disable the CSinitialization signal 243, may continue to disable the CSselect signal 241, may enable the CSimage.data signal 247 for a time period 290, may enable the CSselect signal 280 for a time period 292, and may continue to disable the CSreset signal 235. As shown, the CSselect signal 280 is enabled at the same time as the CSimage.data signal 247, but is disabled earlier than the CSimage.data signal 247 because the CSselect signal 280 acts to activate a switching element to provide amplification to the anode of the LED 230 of the subpixel 72.

[0116] Returning to FIG. 13 for illustration, the voltage drive switching element (MVD) 285 of the subpixel 72 activates in response to the assertion of the CSselect signal 280 to activate the voltage drive 272. In response to the MVD 285 becoming active, a reference voltage (Vreference) signal 300 transmits to the anode of the LED 230 as the CSimage.data signal 247 enables the switching transistor (MS) 302 and MS 226 for the first transmitted CSimage.data signal 247. This causes the Vreference signal 300 to transmit at the anode of the LED 230 to enable or "amplify" the smaller programmed value from the source of MS 226 to cause the emission of light from the LED 230. The amplification may continue for a time period 292, at the end of which the row driver 60 disables the CSselect signal 280 to cause the deactivation of the MVD 285 and MS 302.

[0117] In general, the light emission process can continue for a time period 290, while the amplification lasts for a shorter period, e.g., time period 292. During the light emission process, the subpixel 72 is programmed to transmit a drive current through the LED 230 in response to activation of the MS 226. As previously described, the memory 78 of the subpixel 72 stores digital data and outputs digital data. Through the described hybrid drive, the stored digital data is transmitted from the memory 78 as digital data that translates into a control signal that controls the emission of light from the subpixel 72, with little overhead and no increased power consumption. At the end of the amplification, in some embodiments, the subpixel 72 can be reset by enabling the CSreset signal 235 for a duration, such as time period 294. Thus, the light emitted from the LED 230 can follow various light emission schemes, as previously described in Figures 8-10, to communicate gray levels associated with an image, since the binary data output from the memory 78 acts to modulate the light emitted through the LED 230.

[0118] To illustrate the effect of "amplification" on the anode voltage of subpixel 72, a graph 348 is shown in Figure 15 illustrating an exemplary CSimage.data signal 350, a voltage signal 352 corresponding to the voltage at the anode of LED 230, and a current signal 354 corresponding to the current through LED 230 for a subpixel 72 that does not implement a hybrid drive. It should be understood that the timing diagrams shown are intended to be illustrative and not limiting.

[0119] In this simulation, a binary pulse width modulation lighting scheme was tested by providing a wider binary pulse as the CSimage.data signal 350. The simulation results shown in graph 348 generally have two parts. The first part 356 can correspond to a slower lighting response time, and the second part 358 can correspond to a normal lighting response time, where the lighting response time generally refers to the relative responsiveness of the LED 230 to an applied voltage. It is also worth noting that LEDs such as the LED 230 operate to conduct based on the difference in voltage between the anode and cathode of the LED. When the voltage difference between the anode and cathode is greater than a threshold voltage, the LED operates to emit light according to the value of the current transmitted through the LED. In graph 348, the current signal 354 may generally correspond to the lighting of the LED 230, and the closer the value of the current signal 354 is to the state of the CSimage.data signal 350, the better the lighting response time of the LED 230. In graph 348, the impact of the slow charge effect on the anode voltage of the LED 230 is evident. As shown by the general matching of the amplitude of the current signal 354 with the CSimage.data signal 350 during the first portion 356 and the second portion 358, and its general lack of coupling during the first portion 356, the current signal 354 appears to be less responsive to changes in state of the CSimage.data signal 350 than the second portion 358. Amplifying the anode at the beginning of the emission period can reduce or eliminate the slow charging effect of the anode voltage.

[0120] Turning to Figure 16 for comparison, a graph 370 is shown in Figure 16 illustrating an exemplary CSimage.data signal 350, a voltage signal 374 corresponding to the voltage at the anode of the LED 230, and a current signal 376 corresponding to the current through the LED 230 for a subpixel 72 having a hybrid drive. It should be understood that the timing diagram shown is intended to be illustrative and not limiting. For example, although the CSimage.data signal 350 is shown following a binary pulse width modulated lighting scheme, any suitable lighting scheme may result in the same improvements to responsivity as described below.

[0121] In this simulation, a binary pulse width modulated lighting scheme was tested by providing a wider binary pulse as the CSimage.data signal 350, similar to graph 348. However, unlike graph 348, graph 370 shows that the current signal 376 responds to changes in the CSimage.data signal 350. This improved responsiveness is due, at least in part, to the addition of a voltage drive 272 to the subpixel 72. Because the hybrid drive voltage drive 272 "amplifies" the anode of the LED 230, a smaller change in voltage at the anode of the LED 230 can elicit the same and / or similar responsiveness of the second portion 358 of graph 348. Thus, graph 370 illustrates the benefits and improvements to display technology provided by at least implementing a hybrid drive to the subpixel 72.

[0122] As mentioned above, displays implementing in-pixel memory technology can implement various pixel circuit embodiments and various memory circuit embodiments to achieve the advantages previously described in this disclosure. An exemplary embodiment is a memory circuit supporting a binary pulse width emission scheme, where digital data stored in the memory circuit is output to a drive circuit to control the emission of light from the pixel. As a guide, the binary pulse width emission scheme works in conjunction with a clock signal, e.g., a bit plane clock, to assign contribution weights to various portions of the digital data transmitted from the memory circuit. In some embodiments, the clock signal is used to clock a register to output the stored digital data from the memory circuit. However, in some embodiments, the system clock and / or row driver 60 can control the emission duration through the length of time that the emission enable signal is enabled.

[0123] To help illustrate a memory circuit that facilitates control of light emission via a light emission enable signal, a subpixel 72 is shown in FIG. 17 including a memory circuit 400A, an analog drive circuit 402, and a light emission circuit 404. It should be understood that the subpixel 72 is intended to be illustrative and not limiting. For example, the memory circuit 400A is shown as storing 12 bits of digital data, however, any suitable memory circuit may be used, such as a circuit that stores more or less than 12 bits of digital data.

[0124] The memory circuit 400A may include a write enable transistor (MWR) 406, one or more inverter pairs 408, and a transmit select transistor (MSEL) 410. The memory circuit 400A receives and stores digital data (DATA) 412, for example, from the column driver 62. Before the memory circuit 400A stores DATA 412, the row driver 60 enables a write enable control signal (write_en) 414 to activate the MWR 406 and allow the image data to be written to the memory (e.g., the inverter pair 408) so that the memory can store the image data. Upon receiving DATA 412, the inverter pair 408 stores the DATA 412 value. It should be emphasized that the use of the memory circuit 400A allows for parallel transmission of DATA 412, whereby all bits of DATA 412 are stored in the respective inverter pairs 408 at the same time or in the same write cycle (e.g., when the write_en signal 414 is valid), in addition to bit-wise transmission, where each bit of DATA 412 is stored one bit at a time. The MSEL 410 activates in response to a valid select control signal (Sel) 415 transmitted, for example, by the row driver 60, which operates to activate the MSEL 410 of the memory bit intended for transmission to the analog drive circuit 402. In this manner, the MSEL 410A may be activated at the same time that the MSEL 410B is deactivated. Thus, the memory circuit 400A is loaded with one or more DATA 412 bits before the light emission process begins, and the DATA 412 is easily read bit by bit by activation of the respective MSEL 410.

[0125] At the beginning of the light emission process, for example, an emission process as described in FIG. 14, the row driver 60 can enable a precharge control signal (Precharge) 416 to initially enable light emission based at least in part on the activation of a light emission transistor (MEM) 419. The MEM 419 can be activated in response to the row driver 60, which enables the light emission control signal (Emit_en) 420. In some embodiments, the row driver 60 can enable the precharge signal 416 simultaneously with the Emit_en signal 420 to allow the Vreference signal 246 to be sent to the MS 226 to precharge or amplify the anode of the LED 230 before the activation of the MSEL 410. After the precharge is completed, the Emit_en signal 420 can continue to be enabled by the row driver 60 during the light emission process. Meanwhile, the row driver 60 disables the precharge signal 416 after precharge to let the stored DATA 412 at least in part control the activation of the MEM 419. In this manner, the stored DATA 412 transmitted from the inverter pair 408 can activate the MEM 419 in response to the logic value of the stored value (e.g., "1" or "0"). Note that in some embodiments, a logic high value is equal to the Vreference signal 246 and a logic low value is equal to the Vreference signal 248.

[0126] When the stored DATA 412 is transmitted from the memory circuit 400A, the light emission circuit 404 receives the stored DATA 412 at the gate of MS226. MS226 becomes active in response to the stored DATA 412 value, allowing a current generated by the analog drive circuit 402 to be transmitted to the LED 230 to cause light emission. Light emission may continue as long as the stored DATA 412 is applied as the CSimage.data signal 247. Thus, following the initialization, charging, programming, and light emission processes, the light emitted from the subpixel 72 is generally described using Figures 12 through 14.

[0127] A further embodiment of a subpixel 72 having a memory circuit 400B and an analog drive circuit 442 including a light emission circuit 404 is shown in FIG. 18. It should be understood that the subpixel 72 is intended to be illustrative and not limiting. For example, the memory circuit 400B is shown as storing 16 bits of digital data, however any suitable memory may be used, such as a circuit that stores more or less than 16 bits of digital data. Additionally, the subpixel 72 is shown as having an LED 230 included in the light emission circuit 404, however any suitable light emission circuit 404 may be combined with the described in-pixel memory technology.

[0128] The memory circuit 400B is shown as including one or more write enable transistors (MWR) 406, one or more inverter pairs 408, and one or more select transistors (MSEL) 410. DATA 412 is received into the memory circuit 400B, for example, from a column driver 62. To transmit DATA 412 into the memory circuit 400B, the row driver 60 can enable the write_en signal 406 and the inverse write_en signal 444 to enable bit-wise memory storage of DATA 412. For example, the row driver 60 can enable storage of the last bit of DATA 412 in the inverter pair 408B by activating MWR 406D and / or MWR 406C. Thus, the row driver 60 and column driver 62 can operate to enable bit-wise transmission and storage of DATA 412 into the memory circuit 400B.

[0129] Upon storing DATA 412 in inverter pair 408, memory circuit 400B stores the DATA 412 value until row driver 60 selects the respective bit for transmission. Prior to selecting the respective bit for transmission, row driver 60 precharges sense amplifier 440 by enabling Precharge signal 416. By precharging sense amplifier 440 and then analog drive circuit 442, the responsiveness of subpixel 72 to transmitted electrical signals may be improved compared to subpixel 72 that is not precharged. As previously mentioned, precharging subpixel 72 may make switching states easier and less demanding on circuitry (e.g., by increasing the responsiveness of the circuitry).

[0130] Once precharging is complete, the row driver 60 selects a bit for transmission to the analog drive circuit 442 to emit light according to the stored DATA 412. To transmit a bit to the analog drive circuit 442, the row driver can enable a Sel signal 415 to activate MSEL 410 corresponding to the inverter pair 408. For example, the row driver 60 can enable a Sel signal 415A to activate MSEL 410A and MSEL 410B to transmit the DATA 412 stored in the inverter pair 408A to the analog drive circuit 442.

[0131] In some embodiments, DATA 412 is sent through a sense amplifier 440 before being sent to an analog drive circuit 442. The sense amplifier 440 acts to sense the logic state of DATA 412 and can amplify the sensed logic state to an interpretable logic state (e.g., by increasing the signal amplitude). The interpretable logic state may be based at least in part on a threshold voltage of MS 226 of the analog drive circuit 442. For example, the bit sent to node 446 outputs as having a greater voltage value at node 448 based at least in part on a voltage difference between Vreference signal 248 and Vreference signal 246 caused by the sending through the sense amplifier 440 and representing any suitable voltage value common to a display system (e.g., display system 52).

[0132] After the DATA 412 is amplified, the amplified DATA 412 is sent as a CSimage.data signal 247 to an analog drive circuit 442 to activate or deactivate the MS 226. For example, in some embodiments, the MS 226 deactivates (e.g., sent as a CSimage.data signal 247) in response to a logic high DATA 412 sent, and activates (e.g., sent as a CSimage.data signal 247) in response to a logic low DATA 412 sent. In this manner, the voltage value of the digital data sent as the CSimage.data signal 247 corresponds to the bias voltage of the MS 226, or the voltage value that operates the MS 226 to change state. When the MS 226 is activated, a drive current generated by the analog drive circuit 442 based at least in part on the voltage difference between the Vreference signal 450 and the Vreference signal 451 is sent through the LED 230, enabling the sub-pixel 72 to emit light. Thus, in the described method, the DATA 412 stored in the memory circuit 400B can drive light emission from a pixel circuit (e.g., a sub-pixel, a pixel).

[0133] To summarize the operation of the embodiments of the subpixel 72 of Figures 18 and 17, an example of a process 461 for controlling the operation of the subpixel 72 coupled to a memory circuit 400 is described in Figure 19. In general, the process 461 includes the steps of loading a current bit into memory (block 462), determining whether the current bit is the last bit to load into memory (block 464), loading the next current bit into memory in response to the current bit not being the last bit (block 462), enabling a select signal to read the bit from memory in response to the current bit being the last bit (block 466), waiting for the bit to cause light emission in the pixel circuit (block 468), and determining whether the bit is the last bit to be read from memory (block 471). In response to the bit being the last bit, the display cycle is completed (block 472), and in response to the bit not being the last bit, the next select signal is enabled to read the next bit from memory (block 466). In some embodiments, process 461 may be performed at least in part by processing circuitry, such as processing core complex 12, executing instructions stored in a tangible, non-transitory computer-readable medium, such as one or more storage devices 14. Additionally or alternatively, process 461 may be performed at least in part based on circuit connections formed in display control circuitry, such as row driver 60, column driver 62, and / or timing controller 54.

[0134] Thus, in some embodiments, row driver 60 may load the current bit into memory circuit 400 (block 462). As described above, row driver 60 selectively enables a respective switching element, such as MWR 406B or MWR 406D, to allow a bit-by-bit load of the current bit of DATA 412 into memory circuit 400. Upon enabling MWR 406, a bit corresponding to the current bit of DATA 412 is transmitted for storage, such as through inverter pair 408, where the value of the current bit is continually inverted until the bit is selected for transmission.

[0135] After loading the current bit into memory, the row driver 60 may determine whether the current bit is the last bit (block 464). The last bit represents the last bit of DATA 412 (e.g., the last bit stored in the memory circuit 400). Thus, checking whether the current bit is the last bit checks whether all of DATA 412 has been sent from the column driver 62 for storage. Various techniques may be implemented to determine whether the current bit is the last bit, including, for example, maintaining a separate count to track the current bit position relative to the last bit position.

[0136] In response to the current bit not being the last bit, row driver 60 may load the next current bit into memory circuit 400 (block 462). As described above, row driver 60 enables the next respective switching element to enable bit-wise transmission of the next bit of DATA 412 to memory circuit 400 as the next current bit. Thus, process 461 repeats until the last bit of DATA 412 is stored in memory circuit 400.

[0137] However, in response to the current bit being the last bit, the row driver 60 may enable the select signal to transmit the bit from memory (block 466). If the current bit is the last bit, the row driver 60 determines that the target data to store in the memory circuit 400 has completed loading into memory, and therefore, at this point, the row driver 60 transmits the stored DATA 412, bit by bit or bit by bit, to the analog drive circuit 442 to cause the subpixels 72 to emit light at a level, or intensity, gray, corresponding to the DATA 412. In some embodiments, the row driver 60 transmits the stored bits in order from least significant bit to most significant bit, although any suitable order of the memory circuit 400 and display system 52 may be used. To cause transmission, the row driver 60 enables a Sel signal 415 corresponding to the target bit from the memory circuit 400 for reading. Upon enabling the Sel signal 415, the target bit is transmitted to the sense amplifiers 440 and / or the analog drive circuit 442 to cause emission of light.

[0138] The row driver 60 then waits the programmed time period of the bit transmitted from the memory to allow light to be emitted from the sub-pixel 72 (block 468). While the row driver 60 waits, the bit stored in the inverter pair 408 transmits to the MS 226. Activating the MS 226 causes the analog drive circuit 442 to enable a drive current to be transmitted through the LED 230 to cause light emission from the sub-pixel 72. As previously described in FIG. 8, the bit plane clock 106 can act to modulate the width of the light emission to correspond to the importance of the bit from the memory to an overall perceived gray level. The row driver 60 can use the bit plane clock 106 to modulate the light emission from the sub-pixel 72, for example, by modulating the overall light emission of the sub-pixel 72 (e.g., by enabling the Emit_en signal 420) and / or by modulating the time period during which the bit is selected to transmit from the memory circuit 400 (e.g., by allowing the Sel signal 415 to activate the MSEL 410 for a time period corresponding to the importance of the bit). Note that in some embodiments, row driver 60 does not wait and continues to determine whether the bit read from memory circuit 400 was the last bit of DATA 412 stored.

[0139] After reading a bit, the row driver 60 may determine (block 471) whether the bit is the last bit of stored DATA 412. The row driver 60 determines whether the last bit has been read and / or sent to the analog drive circuit 442. The row driver 60 can manage this determination in a variety of ways, for example, by maintaining a counter that increments in parallel with the assertion of the Sel signal 415 to indicate when the row driver 60 has read the expected number of bits from the memory circuit 400.

[0140] If the bit is the last bit, the row driver 60 may complete the display cycle (block 427). The display cycle may include the entire process 461, such that upon reaching block 427, the row driver 60 emits light of the gray level corresponding to DATA 412. Once the display cycle is complete, the row driver 60 may be ready to accept new DATA 412 corresponding to the same or a different gray level for emission.

[0141] However, in response to the bit not being the last bit, the row driver 60 may enable the next select signal to permit the next current bit to be read from the memory (block 466). The row driver 60 may manage the enabling of the next select signal in a variety of ways, such as, for example, maintaining a separate count to track the current transmit bit position relative to the last transmit bit position. In any case, the row driver 60 determines which Sel signal 415 to enable (e.g., the Sel signal 415 corresponding to the bit to be next transmitted from the memory circuit 400). Once the row driver 60 has determined which Sel signal 415 to enable, the row driver 60 enables the Sel signal 415 to cause activation of the MSEL 410 corresponding to the target bit for transmission. The row driver 60 may repeat transmitting bits of the stored DATA 412 until the last bit is reached. Once the last bit is reached, the row driver 60 may complete the illumination cycle and prepare for the next illumination cycle (block 427).

[0142] 18 and 19, the embodiment of the subpixel 72 described has an analog drive circuit 442 with a global anode. Further embodiments of the subpixel 72 may have an analog drive circuit 442 with a global cathode.

[0143] A subpixel having a global cathode including a memory circuit 400C, an analog drive circuit 442 having a light emitting circuit 404 is shown in Figure 20. It should be understood that subpixel 72 is intended to be illustrative and not limiting. For example, although memory circuit 400C is shown as storing 16 bits of digital data through bit-wise transmission of the data, any suitable memory circuit may be used, such as a circuit that stores more or less than 16 bits of digital data and / or a circuit that allows for parallel transmission of data.

[0144] In the illustrated embodiment, the cathode of LED 230 is coupled to a reference voltage (Vreference) signal 470, and the anode of LED 230 is coupled to a reference voltage (Vreference) signal 473 via MS226A, MS226B, MS276, and MS278. As previously described, after DATA 412 is stored in memory circuit 400C, and in some embodiments after precharging the circuit via Precharge signal 416, row driver 60 enables Emit_en signal 420 to cause emission of light. Activating MEM 480 and MEM 482 causes the stored DATA 412 bit to be sent through sense amplifier 440, and the amplified bit to be sent to MEM 480, while an inverted version of the stored DATA 412 bit is sent to MEM 482 without amplification. From the previous discussion, the inverted bit and the amplified bit are used as control signals to activate MS226A and 226B, which effectively act like CSimage.data signal 247. When MS226A and MS226B are activated, the analog drive circuit 442 generates a drive current based at least in part on the voltage difference between Vreference signal 473 and Vreference signal 470 to send through LED 230, causing it to emit light.

[0145] Similar to the global anode embodiment, the global cathode sub-pixels 72 can generate different gray levels by following a binary pulse width modulation scheme. The binary pulse width modulation scheme can use, in part, a bit plane clock to control the control signals output from the row driver 60. In this way, the Emit_en signal 420 can be enabled for shorter time periods for bits with less importance in the perceived gray level (e.g., the least significant bit of DATA 412) and for longer time periods for bits with more importance in the perceived gray level (e.g., the most significant bit of DATA 412). In some embodiments, the Sel signal 415 can be modulated to cause the sub-pixels 72 to emit light according to different gray levels.

[0146] The use of in-pixel memory techniques and comparators as described in Figure 9 allows the row driver to generate a single pulse width modulated lighting scheme. Thus, an embodiment of a subpixel 72 including a comparator 490, a memory circuit 491, and a memory circuit 492 is shown in Figure 21. It should be understood that the subpixel 72 is intended to be illustrative and not limiting. For example, although the memory circuit 492 is shown as being coupled to an LED drive circuit and coupled to the lighting circuit of the subpixel 72, the memory circuit 492 can be coupled to any suitable lighting circuit and / or drive circuit.

[0147] In the illustrated subpixel 72, DATA 412 of size n bits is received into the memory circuit 491 according to a similar process as described above. That is, the row driver 60 operates to enable the write_en signal 494, causing transmission of DATA 412 to the inverter pair 496. In some embodiments, the row driver 60 operates in conjunction with the column driver 62 to cause all bits associated with DATA 412 to be transmitted in parallel to the inverter pair 496 by simultaneously enabling the write_en signals 494. Additionally or alternatively, the row driver 60 may cause bit-wise transmission of bits associated with DATA 412, for example, by selectively enabling the write_en signal 494, e.g., by selectively enabling the write_en signal 494A, causing transmission of the first bit of DATA 412 to load the bit into the inverter pair 496A.

[0148] Once DATA 412 is stored in inverter pair 496, comparator 490 performs a comparison between two sets of bits using the stored DATA 412 bits and bits sent from a counting circuit (e.g., counter 130). As a reminder, in a single pulse width modulation lighting scheme, a counting circuit such as counter 130 increments to a maximum gray level on the rising edge of a clock signal such as gray level clock 134, and lighting occurs from subpixels 72 until the counting circuit counts to a number equal to and / or greater than the number represented by stored DATA 412. In this way, comparator 490 compresses all bits of DATA 412 into a single bit that indicates whether DATA 412 is the same as the count sent from the counting circuit. Thus, comparator 490 performs a bit-wise XNOR compression on the single bit with embodiments of memory circuit 491 and memory circuit 492, where the output from comparator 490 is a logic low (e.g., "0") value unless all bits match. If all bits match, comparator 490 outputs a logic high value. The output from comparator 490 is stored in memory circuit 492 and the value is held in inverter pair 498 until row driver 60 enables emet_en signal 420 and the stored output of comparator 490 is released to the LED driver and lighting circuitry to drive lighting as described above. Note that CNT_b[n:0] corresponds to the inverse of CNT[n:0] and is used to compare the inverted output from inverter pair 496 with the inverted bit of CNT[n:0].

[0149] It should be understood that in some embodiments, the count circuit may decrement, the comparator 490 may output a logic low value if all bits match, or any combination thereof. In other words, various advantageous embodiments may apply the in-pixel memory techniques described. Additionally, an optional transistor 500 may be included in the sub-pixel 72 to provide a power saving effect by precharging the common output (e.g., MTCH) node of the comparator 490, thereby making the circuit more responsive to changes in the output from the comparator 490.

[0150] To elaborate on the operation of the subpixel 72 shown in FIG. 21, a process 520 for operating the subpixel 72 having a comparator 490 and a memory circuit 491 is described in FIG. 22. In general, the process 520 includes initializing the memory circuit (block 522), precharging a common output from the comparator (block 524), incrementing a count of the counting circuit (block 526), ​​causing light emission based on an automatic comparator decision stored in the memory circuit (block 528), and determining whether the counting circuit has reached a maximum count (block 530). In response to the counting circuit reaching the maximum count, the next image is prepared (block 532), and in response to the counting circuit not reaching the maximum count, the common output from the comparator is precharged (block 524). In some embodiments, the process 520 can be implemented at least in part by executing instructions stored in a tangible non-transitory computer-readable medium, such as one or more storage devices 14, using a processing circuit, such as the processing core complex 12. Additionally or alternatively, process 461 may be performed based at least in part on circuit connections made within display control circuitry, such as row driver 60, column driver 62, and / or timing controller 54.

[0151] Thus, in some embodiments, the row driver 60 may initialize the memory circuit 492 (block 522). To initialize the memory circuit 492, the row driver 60 enables a control signal to force a node of the memory circuit 492 to a low voltage value. Taking FIG. 21 as an example, to initialize the memory circuit 492, the row driver may enable an S reset (S_rst) signal to reset a voltage value of a node (e.g., an S node) of the memory circuit 492. Initializing the node of the memory circuit 492 may cause the light emission circuit to emit light until the comparator outputs a logic high and stop emitting light from the subpixel 72 (e.g., in response to the gray level stored in the memory being reached by the counting circuit). In other words, for one or more subpixels 72 implementing the comparator 490, the subpixels 72 may start emitting light at the same time but stop emitting light at different times, with each light emission duration corresponding to the target gray level of the respective subpixel 72.

[0152] After initializing the memory circuit 492, the row driver 60 may precharge the comparator 490 (block 524). To precharge the comparator 490, the row driver 60 may enable a precharge signal to cause a voltage amplifying circuit, thus allowing the subpixel 72 to become more responsive to changes in the output from the comparator 490. To precharge the comparator 490, the row driver 60 may enable a "Precharge" signal operating in conjunction with the inverse emit_en signal 420 to send a voltage (e.g., DVDD) to the comparator 490 (e.g., the MTCH node of the comparator 490) to amplify the circuit. Although a particular circuit operative to precharge the comparator 490 in response to the Precharge signal is shown, it should be understood that a variety of effective circuit configurations may be used to facilitate the precharging of the comparator 490.

[0153] After precharging the comparator 490, the row driver 60 may increment the count of the count circuit (block 526). The row driver 60 may increment the count circuit, for example, in response to a clock signal that times the increment. After incrementing the count circuit, the subpixel 72 automatically determines whether the count of the count circuit equals or exceeds the value represented by the stored DATA 412. This is because each individual bit of the count and each individual bit of the DATA 412 are sent to the comparator 490, which outputs a logic high value if all bits match and a logic low value if any bit does not match. The comparator 490 sends for storage in an inverter pair 498 of the memory circuit 492, where the value is stored until the row driver 60 enables emission via the activation of the emit_en signal 420.

[0154] After incrementing the count of the counting circuit, the row driver 60 causes light emission based on the output from the decision of the comparator 490 stored in the memory circuit 492 (block 528). The row driver 60 causes light emission by enabling the emit_en signal 420. As previously described, enabling emit_en 420 sends a value from the inverter pair 498 to the LED driver and light emission circuit of the subpixel to cause light emission from, for example, the LED 230 or any suitable light emission circuit. The value sent from the memory circuit 492 can activate or deactivate the switching circuit of the LED driver and the light emission circuit responsible for causing light emission.

[0155] Once the row driver 60 has caused lighting based on the output from the comparator 490, the row driver may determine whether the count of the counting circuit is at a maximum count (block 530). The counting circuit may count from a minimum value to a maximum value, for example from 0 to 255. Thus, once the maximum value or maximum count is reached by the counting circuit, the row driver 60 may perform certain processing steps to restart the counting.

[0156] In response to not reaching the maximum count, row driver 60 restarts process 520 by precharging the common output from comparator 490 (block 524). From there, process 520 thus continues as described, causing row driver 60 to transmit another output from comparator 490 indicating whether stored DATA 412 is greater than or equal to the count represented by the counting circuit.

[0157] However, in response to reaching the maximum count, the row driver 60 prepares for the next image (block 532). To do this, the row driver 60 prepares to receive new DATA 412 corresponding to the target gray level of the subpixel 72 that will be used to communicate the next image. Different embodiments of the subpixel 72 may be prepared in various ways. For example, the subpixel 72 of FIG. 21 may have one or more write_en signals 494 enabled to facilitate loading of new DATA 412 into the memory circuit 491. In some embodiments, preparing for the next image includes restarting the counting circuit, which may cause the counting circuit to be incremented to zero and restarted at block 526. It should be appreciated that in embodiments where the counting circuit is a series of flip-flops coupled together to form a counter, such as counter 130, it is not necessary to restart the counting circuit at zero, as the counting circuit will automatically restart at zero based on the digital logic characteristics of the circuit.

[0158] Several lighting schemes, such as binary pulse width modulation and single pulse width modulation, have been described with respect to a general theory of operation, specific exemplary memory circuits, and specific exemplary pixel circuits that enable the use of the lighting schemes to generate perceived gray levels of light emitted from the sub-pixels. An additional lighting scheme can be implemented by using in-pixel memory technology, which is a binary pulse width modulation permuted lighting scheme.

[0159] To aid in illustration, a memory circuit 560 having one or more MWRs 406, one or more MSELs 410, an inverter pair 408, an inverter pair 498, and a switch / reset (SR) latch 562 is shown in Figure 23. The row driver 60 can operate in cooperation with the column driver 62 to provide DATA 412 to the memory circuit 560 for storage prior to transmission as a CSimage.data signal 247 to the light emitting portion of the pixel, for example, by enabling a control signal that enables the column driver 62 to store DATA 412 in the memory circuit 560.

[0160] In general, row driver 60 can operate memory circuit 560 to emit multiple bits of data simultaneously from memory to the same node, for example node BP_pre. In this manner, row driver 60 can modulate the emission times to rearrange the bit order represented by DATA 412. For example, if DATA 412 is equal to 0010, row driver 60 can operate memory circuit 560 to follow the emission to 1-0-0-0, such that the emission times of "1" occur first and are not emitted after the time period corresponding to "00". This rearrangement can improve the appearance of visual artifacts on electronic display 18, while still allowing the same gray levels as "0010" to be emitted from the subpixels.

[0161] 24A shows bit plane graph 580, FIG. 24B shows error graph 588, FIG. 24C shows bit plane graph 582, FIG. 24D shows error graph 590, FIG. 24E shows bit plane graph 584, FIG. 24F shows error graph 592, FIG. 24G shows bit plane graph 586, and FIG. 24H shows error graph 594, with FIG. 24 showing the effect of permutation on the overall error as a whole. FIGs. 24A-24H represent simulated performance of an electronic display 18 implementing a binary pulse width modulation lighting scheme with and without permutation of 6-bit binary numbers representing target gray levels for sub-pixels and / or pixels.

[0162] The bit plane graph 580 shows the original sequence of the binary pulse width modulation emission scheme without reordering of the gray levels represented by 6 bits, and all bit plane graphs 580, 582, 584, and 586 have a light portion 595 corresponding to emission and a dark portion 596 corresponding to no emission. The bit plane graph 580 is caused by the row driver 60 operating the sub-pixels 72 to emit light via binary pulse width modulation (e.g., the LED 230 is driven to emit light in response to at least the binary representation of the most significant bit, such that 0101 emits after 1-0-1-0 without reordering). Each rectangle in the bit plane graph shows the relative importance of a particular bit in a particular position shown with respect to the bit plane used to cause a particular gray level ranging from a minimum gray level 598 (corresponding to all dark portions 596 for all bit plane values) to a maximum gray level 599 (corresponding to all light portions 595 for all bit plane values). For example, block 597 representing the most significant bit of bit plane graph 580 is logically high for gray levels from 32 to 64 and logically low for gray levels from 0 to 32. This coincides with the 6-bit binary representation of their decimal values. Furthermore, all bit planes are logically low with gray level 0 and all are logically high with gray level 64. These binary states correspond to the numerical representation of the gray levels, so that to have a gray level of 0, all bit planes are expected to be logically low or 000000. Thus, the bit plane graph can visually represent the relative importance of the bits representing the gray levels (e.g., in bit plane graph 580, the state of the 6th bit changes the gray level value more dramatically than the first or least significant bit).

[0163] When subpixels 72 are operated to emit light according to a binary pulse width modulated emission scheme without reordering, the total error count is high (e.g., 322), as shown in bit plane graph 580 and error graph 588. Because errors manifest themselves on the electronic screen of electronic display 18 as, for example, false dynamic contours, color collapse, and / or flickering of light emitted from one or more pixels, it may be desirable to reduce the total error count by reordering.

[0164] As seen in bit plane graph 582 and bit plane graph 584, as reordering occurs and the gray levels of the bit plane graph are reordered so that the most significant bit is emitted first, the bit plane patterns tend to look more like the ideal bit planes shown in bit plane graph 586. Furthermore, as reordering occurs, the errors decrease, as shown in error graph 588, error graph 590, error graph 592, and error graph 594. The perceived image quality may be improved from reducing the error count by reordering the bit planes. The ideal case (e.g., bit plane graph 586) shows how by increasing the number of reorderings, bit plane graph 586 tends to change gradually as the gray levels increase, and how the total error tends to be several total states represented by the bit planes (e.g., 6 bits correspond to a total of 64 states according to the following relationship: Number of states=2 n where n is the number of bits.

[0165] Returning to FIG. 23 to further illustrate how the row driver 60 operates the memory circuit 560 to implement the binary pulse width modulation reordering illumination scheme, the row driver 60 enables and / or disables control signals to regulate the transmission of the reordered DATA 412 from the memory circuit 560. For example, the row driver 60 may selectively enable and / or disable the Sel signals 415 to transmit respective bits from the inverter pairs 408. In some embodiments, the row driver 60 may selectively enable and / or disable the Sel signals 415 in response to the bit plane clock 106 that defines the illumination periods for bit positions of the DATA 412.

[0166] In a high level and ideal reordering case, row driver 60 may operate memory circuit 560 to send DATA 412 as CSimage.data signal 247 in most significant bit to least significant bit order to cause emission from subpixels 72, except when a bit of DATA 412 is logically low. When a DATA 412 bit is logically low, row driver 60 effectively operates memory circuit 560 to skip the logically low emission period and emit light according to the next logically high emission period. Once all logically high bits represented in DATA 412 have been sent, row driver 60 may be paused for a duration equal to the entire logically low emission period, or in some embodiments, proceed to process new DATA 412 for emission. For example, referring to illumination reordering example 600, if DATA 412 is equal to 1111, then CSimage.data signal 247 transmits from memory circuit 560 as "1111" with the same overall illumination period as "1111", whereas if DATA 412 is equal to "0011", then CSimage.data signal 247 transmitted from memory circuit 560 is equal to "1100" with each bit having the same illumination period as "0011", and if DATA 412 is equal to "0100", then the data is recoded to "1000" for transmission as CSimage.data signal 247. Finally, a single pulse width of illumination is generated from the data corresponding to a binary pulse width modulated illumination scheme.

[0167] During the permutation, the row driver 60 can operate the memory circuit 560 to either emit a bit or ignore a bit if the stored bit in the memory is zero. The row driver 60 can operate in several different modes of operation based on the number of permutations the row driver 60 performs. For example, for one permutation, the row driver 60 may have two modes of operation, and for three permutations, the row driver 60 may have eight modes of operation.

[0168] The row driver 60 can determine which mode of operation to operate based at least in part on a comparison of the current emission time to the quadrant time. The row driver 60 can compare the current time to a predefined time frame that defines the mode of operation (e.g., a first mode of operation corresponds to a length of a first emission). These different modes of operation can define how the row driver 60 prioritizes image data to cause emission. For example, for one reordering example, the row driver 60 in the first mode of operation can allow emission according to a bit plane if the first most significant bit is equal to a binary state "0" (e.g., a bit plane refers to how a pixel operates to emit light in response to a binary state of image data used to operate the switch 104), but if the first most significant bit is equal to a binary state "1", the row driver 60 can allow emission regardless of the emission defined by the bit plane, resulting in a reordering of the bit planes.

[0169] For each mode of operation, regardless of the number of permutations, row driver 60 may perform similar control operations. Row driver 60 for each mode of operation operates to iterate through each bit of DATA 412 starting with the least significant bit (e.g., DATA[0] 412A) and proceeding to the bit before the most significant bit that corresponds to the number of permutations (e.g., DATA[n-1] 412 for one permutation, DATA[n-2] 412 for two permutations). For each iteration, starting with DATA[0], row driver 60 resets the S node, precharges memory circuit 560, enables Sel signal 415B to allow transmission of the DATA[n] 412B bit to SR latch 562, and enables Sel signal 415 corresponding to the current repetition of the least significant bit so that either the current repetition of the most significant bit or the current repetition of the least significant bit is transmitted as CSimage.data signal 247.

[0170] The row driver 60 can operate the memory circuit 560 in different ways based on the mode of operation. For example, when the row driver 60 operates in a first mode of operation, the row driver 60 further precharges the memory circuit 560 between asserting the Sel signal 415B to allow transmission of the DATA[n] 412B bit to the SR latch 562 and asserting the Sel signal 415 corresponding to the current iteration of the least significant bit. Additionally or alternatively, in modes of operation other than the first mode of operation, the row driver terminates by enabling Sel signal 415B, enabling other Sel signals 415 corresponding to a number of most significant bits equal to the number of permutations (e.g., Sel signals 415 for DATA[n] 412B and DATA[n-1] 412 for two permutations, Sel signals 415 corresponding to DATA[n] 412B, DATA[n-1] 412, and DATA[n-2] 412 for three permutations), and enabling the Sel signal 415 corresponding to the current iteration of at least the least significant bits (e.g., DATA[0] 412A for the first iteration, DATA[1] 412 for the second iteration, and DATA[2] 412 for the third iteration).

[0171] Thus, in the two-reorder example, the row driver 60 can operate in four different operating modes for the stored DATA 412 having six bits. In a first operating mode (e.g., corresponding to a first quarter of the gray level value between zero and the gray level threshold 16), the row driver 60 can reset and precharge the S node (e.g., enable Precharge signal 416), enable Sel[6] 415, enable SET signal 602, precharge, enable Sel[5] 415, enable SET signal 602, precharge, enable Sel[n] 415 (e.g., for the first iteration, n=0 and Sel[0] 415A is enabled), in addition to the SET signal for each bit of DATA 412, and increase the value of n from zero for each iteration until DATA[4] 412 is reached. In a second operating mode (e.g., corresponding to a second quarter of the gray level values ​​between the gray level threshold 16 and twice the gray level threshold 32), the row driver 60 resets, precharges, and enables Sel[6] 415B, enables the SET signal 602, precharges, and enables Sel[5] 415, and in addition to the SET signal for each bit of DATA 412, enables Sel[n] 415, increasing the value of n from zero with each iteration until DATA[4] 412 is reached. In a third operating mode (e.g., corresponding to a third quarter of the gray level values ​​between 32, twice the gray level threshold, and 48, three times the gray level threshold), the row driver 60 resets the S node, precharges, enables Sel[6] 415B, enables Sel[5] 415, enables the SET signal 602, precharges, enables Sel[6] 415B, and enables Sel[n] 415 in addition to the SET signal for each bit of DATA 412, increasing the value of n from zero with each iteration until DATA[4] 412 is reached.In a fourth operating mode (e.g., corresponding to a fourth quarter of a gray level value between 48, three times the gray level threshold, and 64, four times the gray level threshold), the row driver 60 resets and precharges the S node, enables Sel[6] 415B, enables Sel[5] 415, and in addition to the SET signal for each bit of DATA 412, enables Sel[n] 415, increasing the value of n from zero with each iteration until DATA[4] 412 is reached.

[0172] 25 includes a bit plane graph 604 representing a binary pulse width modulated lighting scheme with two permutations implemented in three color channels. As shown, the bit plane graphs 582 corresponding to the two permutations are represented over time in the bit plane graph 604 for the three color channels of one pixel 70. The row driver 60 can time the lighting with respect to quadrants, and for two permutations, one quadrant 606 can correspond approximately to one quarter of the lighting time (e.g., 1 / 2). n, where n is equal to the number of permutations. These quadrants 606 may be in parallel with the modes of operation described above. As time increases, the electronic display 18 may vary the lighting priority. In other words, the two most significant bits of the image data for a particular pixel 70 may be given a higher lighting priority than the other bits during lighting. The electronic display 18 may, in some embodiments, manage lighting based on a comparison of the most significant bits with a value represented by a counter, increasing from a binary state "00" to a binary state "11" on an edge (e.g., a rising edge or a falling edge) of a clock signal (e.g., one period of the clock signal corresponds to the duration of one quadrant). Thus, in these embodiments, for a subpixel 72 of pixel 70, for the first quadrant 606A, if the two most significant bits (MSBs) are equal to the binary state "00", the subpixel 72 may emit light according to bit plane 608 (e.g., according to the binary data stored in memory 78, represented by), however, if the two most significant bits are equal to the binary states "11", "01" and / or "10", the subpixel emits light for the duration of the emission period of the channel of the first quadrant 606 (e.g., the first color channel corresponds to time duration 609), as generally summarized in output logic outline 610.

[0173] To summarize the other three quadrants, while operating in the second quadrant 606B, the subpixel 72 emits light according to the bit plane 608 if the two most significant bits are equal to the binary state "01", emits light if the two most significant bits are equal to the binary state "10" and / or "11", and does not emit light if the two most significant bits are equal to the binary state "00". While operating in the third quadrant 606C, the subpixel 72 emits light according to the bit plane 608 if the most significant bit is equal to the binary state "10", emits light if the two most significant bits are equal to the binary state "11", and does not emit light if the two most significant bits are equal to the binary state "00" and / or "01". While operating in the fourth quadrant 606D, the subpixels 72 emit light according to the bit plane 608 if the two most significant bits are equal to the binary state "11" and do not emit light if the two most significant bits are equal to "00", "01", and / or "10". In this manner, the subpixels 72 are therefore operated to reorder the emission corresponding to the two most significant bits, such that emission of the two most significant bits occurs before emission according to the bit plane 608.

[0174] To help provide content, FIG. 26 shows a timing diagram of a binary pulse width modulation lighting scheme with two permutations implemented in three color channels. The timing diagram shows the relationship between the loading of digital data into memory 78, which occurs substantially simultaneously with other operations performed by row driver 60. For example, the loading of data for the most significant bit of the green channel occurs at time 612 of the lighting of the least significant bit of the red channel. Comparing FIG. 26 with FIG. 25, as described for the fourth quadrant 606D, row driver 60 enables subpixels 72 to emit light according to bit planes represented by data stored in and transmitted from memory 78. As shown in the timing diagram, the total lighting period for all three color channels is approximately equal to three times the channel-specific lighting period.

[0175] An exemplary embodiment of a pixel operated by a row driver 60 according to a binary pulse width modulation reordering emission scheme, including a memory circuit 560, MWR 406, MSEL 410, inverter pair 408, inverter pair 498, and an SR latch 562 coupled to an analog drive circuit 561, is shown in Figure 27. This diagram is meant to be illustrative and not limiting, for example, various pixel circuits and analog drive circuits can be used in combination with the memory circuit 560 and in-pixel memory technology. Figure 27 shows an example of a memory circuit 560 applied to a digital mirror display (DMD).

[0176] In general, the illustrated memory circuit 560 operates to receive DATA 412 corresponding to the target gray level of the color channel of the pixel 70 corresponding to the memory circuit 560. As illustrated, the memory circuit 560 includes a different color group memory for each color channel. In this embodiment, the pixel 70 has a memory circuit for each color channel instead of a subpixel 72 specific to each color channel (e.g., RGB). The row driver 60 can operate the color channel by enabling a color group (CG) signal 564. Upon activating the CG transistor (MCG) 565, the stored DATA 412 transmits toward the analog drive circuit 561. The row driver 60 can allow one color channel to transmit at a time. Thus, the illustrated memory circuit 560 facilitates color sequential output from the individual memory circuits to a shared output circuit coupled to the DMD electrodes.

[0177] The row driver 60 can operate the illustrated memory circuit 560 similarly to the memory circuit 560 of FIG. 23. Thus, in the two permutation examples, the row driver 60 can operate in four different operation modes, and the operation mode is selected based on the gray level value of DATA 412. After writing DATA 412 to the inverter pair 408, the row driver 60 operates the memory circuit 560 to transmit the stored DATA 412 one bit at a time to the SR latch 562 to drive the DMD electrodes via the analog drive circuit 561. By driving the memory circuit 560 in different operation modes, the row driver 60 can permute the DATA 412 to generate a single pulse width modulated signal from the binary pulse width modulated light emission data by selectively enabling and / or disabling the CG signal 564 (e.g., enabling 564B to transmit red data corresponding to bit plane 7).

[0178] For example, as described above, for a first mode of operation (e.g., corresponding to a gray level between zero and a gray level threshold), the row driver 60 may reset, precharge, and enable S node Sel[n] 415B, enable SET signal 602, precharge, and enable Sel[n-1] 415, enable SET signal 602, precharge, and enable Sel[0] 415A. The row driver may repeat the first mode of operation for each bit of DATA 412, incrementing from the first bit DATA[0] 412A until DATA[n-2] is reached (e.g., 2 corresponds to the number of permutations). The row driver 60 may operate as described with respect to FIG. 23 while in the second, third, and fourth modes of operation.

[0179] Similar to Fig. 27, an exemplary embodiment of a pixel 650 operated by a row driver 60 and following a single pulse width modulated lighting scheme, including a memory circuit 654, a color channel selection transistor 656, an inverter pair 498, an analog drive circuit 561, and a comparator 490 electrically coupled to a lighting circuit (not shown), is shown in Fig. 28. This figure is meant to be exemplary and not limiting, for example, any suitable pixel circuit may be used in conjunction with any combination of additional and / or alternative embodiments of memory circuits and in-pixel memory technologies, such as suitable switching elements (e.g., MOSFETs as shown). Fig. 28 is included to show an example of a pixel 650 applied to a liquid crystal display (LCD), where the operation of the memory circuit 654 and comparator 490 may generally follow the process shown and described in Fig. 22.

[0180] In general, pixel 650 receives DATA 412 during a data write process managed by row driver 60, and write_en signal 414 is enabled to allow DATA 412 bits to be written to memory, e.g., inverter pair 408. During the data write process, pixel 650 receives gray level digital data in red channel (DATA) 412R, gray level digital data in green channel (DATA) 412G, and gray level digital data in blue channel (DATA) 412B, and pixel 650 receives DATA 412 in serial data transmission and / or parallel data transmission to each of memory circuits 654. Once DATA 412 is written to the memory of pixel 650, comparator 490 performs an automatic comparison of DATA 412 from memory with a count transmitted from a counting circuit, such as counter 130 and / or any suitable counting method. Using the same method as described for the comparator 490 of FIG. 21, the comparator 490 transmits a "1" if the DATA 412 and the count 658 from the count circuit are the same (e.g., all bits match) and transmits a "0" if they are not the same (e.g., one or more bits do not match). The row driver 60 transmits a CG signal 564 to a respective transistor of the color channel selection transistors 656 to enable a color channel for color sequential emission, e.g., either the red, green, or blue color channel for emission via a shared output stage. When the row driver 60 enables transmission from a color channel, the MTCH bit is transmitted to the memory circuit 492 for storage. The row driver 60 can enable an EMIT signal to enable emission according to the stored MTCH bit, as described above. Additionally or alternatively, the row driver 60 can enable a GHOST signal to at least partially suppress emission, regardless of the MTCH bit stored in the memory circuit 492. To emit light, the row driver 60 asserts the EMIT signal, causing the stored MTCH bit to be transmitted to an analog driver circuit 561 that is coupled to a high and low reference voltage.The stored MTCH bits are sent to the analog drive circuit 561 in response to reference voltages (e.g., MS566A, MS566B) to either activate and / or deactivate the MS566 coupled to the LC electrodes. The reference voltages are shown as 5V and VSS, but may be any suitable voltages used to drive the LC electrodes upon activation of the MS566.

[0181] According to the above structure, pixel 650 can be operated to emit according to a single pulse width modulated emission scheme. Different embodiments can be operated by row driver 60 to emit according to different emission schemes. For example, the color channels of pixel 650 may be operated according to a binary pulse width modulated emission scheme if the digital data normally sent to pixel 650 is changed and comparator 490 is removed.

[0182] It should be understood that in-pixel memory techniques are useful in various embodiments and display technologies as discussed throughout this disclosure. It should also be understood that additional or alternative reference voltages may be used for each reference voltage described or disclosed in the figures. Additionally or alternatively, although described as reducing or eliminating reliance on using a frame buffer, it should be noted that in some embodiments in-pixel memory techniques may be used in parallel with a frame buffer. Furthermore, while the memory circuits are described as storing 6 bits, 12 bits, 8 bits, and / or 16 bits, it should be understood that any suitable number of bits may be stored using any suitable memory structure.

[0183] As briefly described in FIG. 21, slight adjustments can generally be applied to in-pixel memory technology to allow memory 78 to be moved to a smart buffer, as opposed to or in addition to including memory 78 in the sub-pixel 72 itself. FIG. 29 illustrates this generally in an in-pixel memory architecture electronic display 700 and a smart buffer architecture electronic display 702. In-pixel memory architecture electronic display 700 includes memory 78 in each sub-pixel 72 located within an active area 704 of electronic display 18, as shown, which includes all of the light-emitting components of the electronic display and communicative couplings to support data transmission to the light-emitting components. In in-pixel memory architecture electronic display 700, digital data is transmitted from memory 708 to each respective sub-pixel 72 for localized buffering in memory 78. In some embodiments, the digital data is transmitted from memory 708 to a source area 710 before being transmitted to memory 78 for localized buffering (e.g., buffering in sub-pixel 72). However, a memory substantially similar to memory 78 may be included in a smart buffer 712 of smart buffer architecture electronic display 702, still eliminating or at least reducing the dependency on a frame buffer, but further removing memory 78 from active area 704. By moving memory 78 to smart buffer 712, row driver 60 can operate input latches 714 and output latches 716 to arbitrate the emission from each subpixel 72 through an analog output circuit, such as driver 80. Here, smart buffer 712 may represent any suitable buffer memory located within the integrated circuitry of electronic display 18, but outside the active area of ​​electronic display 18.

[0184] FIG. 30 illustrates an example of a smart buffer embodiment of a memory 78 circuit including a memory circuit 750, a comparator 752, a memory circuit 754, and an output inverter 756. This circuit functions similarly to the memory circuit shown in FIG. 21, with the smart buffer of FIG. 30 receiving digital data in response to a write_en control signal 757 that enables the writing of digital data into the memory circuit 750 (e.g., an inverter pair). Thus, the general operation of the memory circuit 754 and the comparator 752 may generally follow the process shown and described in FIG. 22. The smart buffer of FIG. 30 may have a memory 78 circuit for each subpixel 72 of the active area 704. The digital data value may be stored in the memory circuit 750 until a new value of digital data is written to the smart buffer for the particular subpixel 72.

[0185] When the digital data is sent to the memory circuit 750, the comparator 752 determines whether all the bits of the digital data match the output (CNT / CNT_b) from the counting circuit. Similar to the previous embodiment, the counting circuit counts to enable light emission according to the gray level represented by the digital data. The comparator may output a logic zero, "0", as the MTCH bit until the digital data matches the count, at which point the comparator outputs a logic one, "1", as the MTCH bit. The MTCH bit is typically sent to the memory circuit 754 for storage, while the inverted MTCH bit value is sent to the output inverter 756 and ultimately to the corresponding sub-pixel to cause and / or stop light emission.

[0186] Continuing with the transmission path of the MTCH bits, Figure 31 illustrates a pixel circuit 780 that may be used in conjunction with the smart buffer circuit of Figure 30. The pixel circuit 780 includes an input latch 782 (e.g., an inverter pair) and an output latch 784 (e.g., an inverter pair), both of which are operated to latch digital data transmitted from a smart buffer, e.g., smart buffer 712, in response to a write enable (write_en) control signal 786. Once latched, the digital data may be automatically transmitted to the gate of a drive transistor 788. As previously discussed, the drive transistor 788 is activated in response to the digital data and in response to the value of the digital data to cause a drive current to be transmitted through a light emitting circuit, e.g., a light emitting diode 790 of the pixel circuit 780.

[0187] Thus, the technical effect of the present disclosure includes techniques for implementing memory in one or more pixels of an electronic display to improve processing of image data for presentation. The techniques include systems and methods for receiving image data, storing the image data in a memory in the pixel, and transmitting the image to a drive circuit to operate the light emitting elements of the pixel to emit light. Additionally, any suitable pixel circuit implementing the in-pixel memory technology can be used to perform different lighting schemes, including binary pulse width modulated lighting schemes, binary pulse width modulated reordering schemes, single pulse width modulated lighting schemes, and pulse density modulated lighting schemes, benefiting from reduced bandwidth used to communicate the same image without the use of in-pixel memory technology. These pixel circuits enabling lighting schemes can be coupled to pixel circuits with hybrid drives to increase the responsiveness of the LEDs to electrical signals.

[0188] The techniques described herein may be applied and integrated with a variety of display technologies and should not be limited to the specific embodiments shown and / or described herein. For example, although the pixel with memory is shown as having a light emitting diode as the light modulating device, the in-pixel memory technique may generally be applied to different pixel circuits to support a variety of display technologies using a variety of light modulating devices. Thus, suitable pixel circuits supporting emission via light emitting diodes, digital mirror displays, organic light emitting diodes, or liquid crystal displays, plasma displays, or dot matrix displays may each have memory within the pixel to achieve at least improved data transmission bandwidth and ease of programming the pixel.

[0189] It should be understood that the specific embodiments described above are shown by way of example, and that these embodiments may be susceptible to various modifications and alternative forms. It is further to be understood that the claims are not limited to the particular forms disclosed, but rather are intended to cover all modifications, equivalents, and alternatives falling within the spirit and intent of this disclosure.

[0190] The technology presented and claimed herein is applied with reference to tangible objects and specific examples of practical nature that clearly advance the art, and as such is not abstract, insubstantial, or merely theoretical. Moreover, where any of the claims appended at the end of this specification contain one or more elements recited as "means for [performing] ___ [function]" or "step for [performing] ___ [function]," it is intended that such elements are to be construed in accordance with 35 U.S.C. 112(f). However, with respect to any of the claims that contain elements recited in any other manner, it is not intended that such elements are to be construed in accordance with 35 U.S.C. 112(f).

[0191] Exemplary embodiments may include the following.

[0192] Example embodiment 1: An electronic display, an active area including a first pixel formed within the active area, the first pixel configured to emit light in response to image data; a controller configured to transmit image data to the first pixel; The first pixel is an organic light emitting diode configured to emit light in response to image data; a memory configured to digitally store image data received from the controller; and a drive circuit configured to receive image data from the memory, the drive circuit configured to cause the organic light emitting diodes to emit light in response to the image data.

[0193] Example Embodiment 2: The electronic display of Example Embodiment 1, wherein the controller is configured to transmit image data to the memory of the first pixel via the data lines of the active area.

[0194] Example embodiment 3: An electronic display as described in example embodiment 1, wherein the controller is configured to transmit image data to a multiplexing circuit via data lines in the active area, and the controller is configured to control the multiplexing circuit to arbitrate the transmission of the image data for a first pixel to the memory.

[0195] Example Embodiment 4: An electronic display as described in Example embodiment 3, wherein the image data includes two or more color channels corresponding to the image to be displayed, and the controller is configured to program a memory associated with a first color channel of the image data at a first time by enabling a first multiplexing control signal, causing the memory of the first pixel to be programmed, and the controller is configured to program a memory associated with a second color channel of the image data at a second time by enabling a second multiplexing control signal, causing the memory of the second pixel to be programmed.

[0196] Example Embodiment 5: An electronic display as described in Example Embodiment 1, wherein the controller is configured to program the memory of a first pixel with image data, the image data being associated with a first color channel and programmed at a first time, and the controller is configured to program the memory of the first pixel with second image data, the second image data being associated with a second color channel and programmed at a second time.

[0197] Example Embodiment 6: The electronic display of example embodiment 1, wherein the memory of the first pixel is configured to act as an intra-display frame buffer for the first pixel in the electronic display.

[0198] Example embodiment 7: An electronic display as described in example embodiment 1, wherein the memory of the first pixel is configured to receive a counter signal and image data, and the memory is configured to operate the switch by transmitting image data based at least in part on the counter signal to cause the organic light-emitting diode to emit light according to a binary pulse width modulated light emission scheme.

[0199] Example embodiment 8: An electronic display as described in example embodiment 1, wherein the drive circuit of the first pixel includes a comparator configured to receive a signal indicative of a number and image data, and the comparator is configured to operate a switch based at least in part on the signal representing the image data and the number to cause the organic light-emitting diode to emit light according to a single pulse-width modulated light-emitting scheme.

[0200] Example embodiment 9: The electronic display of example embodiment 1, wherein the drive circuit includes an adder configured to add image data to a predetermined value of an accumulator during an addition process, and a carry bit from the addition process is configured to operate a switch to cause an organic light-emitting diode to emit light according to a pulse density modulated light emission scheme.

[0201] Example embodiment 10: A subpixel of a particular color in an electronic display, comprising: a memory configured to receive a signal indicative of a value within a data range; a first terminal configured to receive a first voltage signal; a second terminal configured to receive a second voltage signal; a light emitting diode configured to emit light based at least in part on a signal indicative of a value within the data range, and the memory configured to enable a current to be transmitted through the light emitting diode to cause the light to be emitted, the current being based at least in part on the first voltage signal and the second voltage signal.

[0202] Example embodiment 11: A subpixel as described in example embodiment 10, wherein the memory includes a register configured to receive a counter signal and a signal indicative of a value within the data range, and the memory is configured to operate the switch by sending a signal indicative of a value within the data range based at least in part on the counter signal to cause the light emitting diode to emit light according to a binary pulse width modulated light emitting scheme.

[0203] Example embodiment 12: A subpixel as described in example embodiment 10, including a comparator configured to receive a signal indicating a number and a signal indicating a value within a data range, the comparator configured to operate an light emitting diode based on the signal indicating a value within the data range and the signal indicating the number to emit light according to a single pulse width modulated light emitting scheme.

[0204] Example embodiment 13: A subpixel as described in example embodiment 10, including an adder configured to add a signal indicating a value within a data range to a predetermined value of an accumulator configured to be coupled to the adder during the addition process, and a carry bit from the addition process is configured to operate a light emitting diode to emit light according to a pulse density modulated light emission scheme.

[0205] Example embodiment 14: A subpixel as described in example embodiment 10, wherein the memory is configured to function as a frame buffer to store a signal indicative of a value within the data range for a period of time before allowing the signal indicative of a value within the data range to be used to cause the light emitting diode to emit light.

[0206] Example embodiment 15: A pixel, a first subpixel of the pixel, the first subpixel corresponding to a first color channel; a first memory configured to store a first signal indicative of a first value within a first data range used to communicate image data for a first color channel of a pixel; a first sub-pixel including: a first drive circuit configured to receive a first signal indicative of a first value from a first memory, the first drive circuit configured to cause a first light emitting diode to emit light based at least in part on the first signal indicative of the first value; a second subpixel of the pixel, the second subpixel corresponding to a second color channel; a second memory configured to store a second signal indicative of a second value within a second data range used to communicate image data for a second color channel of the pixel; and and a second sub-pixel including a second drive circuit configured to receive a second signal indicative of a second value from a second memory, the second drive circuit configured to cause a second light emitting diode to emit light based at least in part on the second signal indicative of the second value.

[0207] Example embodiment 16: A pixel as described in example embodiment 15, wherein the first subpixel is configured to be programmed with a first signal indicating a first value at a first time, and the second subpixel is configured to be programmed with a second signal indicating a second value at a second time, the first time occurring earlier than the second time.

[0208] Example embodiment 17: A pixel as described in example embodiment 16, wherein the first signal is configured to be transmitted to the first sub-pixel via a multiplexing circuit configured to operate in response to a first control signal transmitted at a first time, and the first signal is configured to stop being transmitted to the first sub-pixel in response to the multiplexing circuit receiving a second control signal transmitted at a second time.

[0209] Example embodiment 18: The pixel of example embodiment 15, wherein the first memory is configured to act as a frame buffer for the first sub-pixel.

[0210] Example embodiment 19: The pixel of example embodiment 15, wherein the first subpixel includes a first counter, the first memory is configured to receive an output from the first counter, the output from the first memory is configured to activate a switch in response to the output from the counter, and the output from the first memory is configured to operate the first light emitting diode to emit light according to a binary pulse width modulated light emitting scheme.

[0211] Example embodiment 20: A pixel as described in example embodiment 15, wherein the first drive circuit includes a comparator configured to receive an output from the first memory and an output from a counter configured to correspond to a time difference between increments of gray levels associated with the first color channel, and the first drive circuit is configured to operate the first light-emitting diode based at least in part on the output from the comparator.

[0212] Example 21: An electronic display comprising: a memory formed within an active area of ​​the electronic display or within an integrated circuit of the electronic display outside the active area, the memory configured to store digital data signals indicative of values ​​within a data range; a driver disposed within the active area, the driver configured to generate one or more analog electrical signals in response to a digital data signal; a light modulating device disposed over an active area, the light modulating device configured to emit light based at least in part on one or more analog electrical signals.

[0213] Example 22: The electronic display of Example 21, wherein the light modulating device comprises a light emitting diode, a digital mirror display, an organic light emitting diode, or a device supporting a liquid crystal display, a plasma display, or a dot matrix display, or any combination thereof.

[0214] Example 23: An electronic display as described in Example 21, wherein the light modulation device includes a light emitting diode, and the light emitting diode and driver are configured to support a global cathode or global anode configuration configured to emit light using one or more analog electrical signals.

[0215] Example 24: An electronic display as described in Example 21, wherein the light modulation device includes a light emitting diode, and the light emitting diode and driver are configured to support a global cathode or global anode configuration configured to emit light using one or more analog electrical signals.

[0216] Example embodiment 25: An electronic display as described in example embodiment 24, wherein the memory includes a transistor configured to be activated in response to a selection control signal, and a first subset of the digital data signals is configured to be transmitted to the driver in response to activation of the transistor.

[0217] Example Embodiment 26: The electronic display of Example embodiment 24, wherein the first pair of inverters is configured to output a first subset of the digital data signals to a sense amplifier before outputting them to the driver.

[0218] Example embodiment 27: An electronic display as described in example embodiment 24 including a switch / reset (SR) latch configured to couple to an output of a first inverter pair and a second inverter pair configured to couple to the output of the switch / reset latch, wherein the switch / reset latch and the second inverter pair are configured to enable a binary pulse width modulation lighting scheme with reordering.

[0219] Example Embodiment 28: The electronic display of Example Embodiment 24, wherein the memory includes a second inverter pair configured to store a second subset of the digital data signals sent to the pixels.

[0220] Example Embodiment 29: The electronic display of Example embodiment 28, wherein the first subset of digital data signals and the second subset of digital data signals are sent to the first inverter pair in response to the controller enabling a write enable control signal.

[0221] Example Embodiment 30: A pixel of an electronic display, comprising: a memory configured to store a first digital data signal sent from the column driver to the pixel, the first digital data signal configured to correspond to an image to be displayed by having values ​​within a data range to communicate a portion of the image; a memory including one or more inverter pairs configured to receive a first digital data signal transmitted from a column driver to the memory in the pixel; a comparator configured to receive the first digital data signal and the second digital data signal from the one or more inverter pairs, the comparator configured to output a control signal in response to determining when the first digital data signal matches the second digital data signal; A pixel comprising: a driver configured to receive a control signal from the memory, the driver configured to cause light to be emitted from the pixel based at least in part on the control signal.

[0222] Example embodiment 31: The pixel of example embodiment 30 including a counter configured to output an indication of the current number being counted as the second digital data signal to the comparator.

[0223] Example Embodiment 32: The pixel of Example embodiment 30 including a transistor configured to enable precharging of the memory.

[0224] Example Embodiment 33: The pixel of example embodiment 30 including an additional inverter pair separate from the one or more inverter pairs configured to store the output from the comparator before sending it as a control signal to the driver.

[0225] Example Embodiment 34: The pixel of Example embodiment 33, wherein the additional inverter pair is reset between a first memorization of the first output and a second memorization of the second output.

[0226] Example embodiment 35: A pixel as described in example embodiment 30 including a transistor configured to enable a control signal to be output from the comparator and sent to the driver, the transistor configured to activate in response to a release enable signal.

[0227] Example Embodiment 36: The pixel of Example embodiment 30, further comprising an additional memory corresponding to a color channel associated with displaying an image, the additional memory being configured to couple to the driver.

[0228] Example 37: An electronic display comprising: a controller configured to generate one or more digital data signals to cause an image to be displayed; a buffer including a first memory configured to store a first digital data signal of the one or more data signals, the first digital data signal configured to cause a portion of an image to be displayed on an electronic display; A plurality of pixels configured to emit light in response to one or more digital data signals, each pixel of the plurality of pixels comprising: a plurality of pixels including a driver configured to receive a first digital data signal from a first memory, the driver configured to generate an analog data signal in response to the first digital data signal transmitted from the first memory; 1. An electronic display comprising: a lighting circuit configured to couple to a driver, the lighting circuit configured to emit light based at least in part on an analog data signal.

[0229] Example embodiment 38: An electronic display as described in example embodiment 37, including a selection circuit configured to couple to an output of the first memory and an output of the second memory, the buffer also including a second memory for storing a second digital data signal, and the selection circuit configured to select the first memory and output the first digital data signal to the driver independently of selecting the second memory.

[0230] Example embodiment 39: An electronic display as described in example embodiment 38, wherein the selection circuit is configured to couple to the output of the inverter pair, the inverter pair being configured to store the output from the first memory when the selection circuit operates in a first state, and the inverter pair being configured to store the output from the second memory when the selection circuit operates in a second state.

[0231] Example embodiment 40: An electronic display as described in example 37, wherein each pixel includes a counting circuit configured to couple to a first subpixel, the first subpixel includes a comparator, and the comparator is configured to compare an output from the counting circuit with an output from the first memory.

[0232] Example Embodiment 41: A pixel circuit for an electronic display, comprising: a memory configured to store digital data signals indicative of values ​​within a data range; a light emitting diode configured to emit light based at least in part on a digital data signal; an initialization transistor configured to initialize the pixel circuit before the light emitting diode emits light; a drive transistor configured to be activated based at least in part on a digital data signal.

[0233] Example 42: A pixel circuit as described in Example 41, including a voltage drive circuit configured to couple to an anode of the light emitting diode, the voltage drive circuit configured to amplify the anode of the light emitting diode at the start of a light emitting period of the light emitting diode.

[0234] Example 43: A pixel circuit as described in Example 41, wherein the drive transistor is configured as a metal oxide semiconductor field effect transistor (MOSFET), and the pixel circuit includes a plurality of p-type or n-type MOSFETs configured to cause the light emitting diode to emit light in response to a control signal.

[0235] Example Embodiment 44: The pixel circuit of Example embodiment 41, comprising a reset circuit configured to be coupled in parallel to the light emitting diode, the reset circuit configured to reset an anode voltage of the light emitting diode after a light emitting period.

[0236] Example embodiment 45: The pixel circuit of example embodiment 41, including a hybrid drive, the hybrid drive including a voltage drive and a current drive circuit, the hybrid drive configured to operate the light emitting diode to emit light in response to an image data control signal based at least in part on a voltage data signal, a plurality of reference voltages, and a digital data signal.

[0237] Example embodiment 46: A pixel circuit as described in example embodiment 41, including an auto-zero transistor configured to be activated in response to an auto-zero control signal, and wherein a voltage value of a source node of the auto-zero transistor is configured to increase until the voltage value of the source node of the auto-zero transistor is equal to the voltage value of the gate voltage of the drive transistor.

[0238] Example embodiment 47: A pixel circuit as described in example embodiment 41, wherein the memory includes a register configured to store a digital data signal and a comparator configured to compare the digital data signal with a number configured to be generated by the counter, and the memory is configured to transmit an output from the comparator to activate the drive transistor.

[0239] Example embodiment 48: The pixel circuit of example embodiment 41 including additional circuitry configured to operate in conjunction with the memory to activate the drive transistor to cause emission according to a binary pulse width modulated emission scheme, a single pulse width modulated emission scheme, a pulse density modulated emission scheme, or any combination thereof.

[0240] Example Embodiment 49: An electronic display comprising: a controller configured to generate one or more digital data signals to cause an image to be displayed; a plurality of pixels configured to emit light in response to one or more digital data signals, a first pixel of the plurality of pixels comprising: a memory configured to receive a first digital data signal generated by the controller based at least in part on the image; a light emitting circuit configured to emit light based at least in part on the first digital data signal; an initialization transistor configured to initialize the first pixel before the light emission circuit emits light; and a drive transistor configured to activate based at least in part on a first digital data signal.

[0241] Example embodiment 50: An electronic display as described in example embodiment 49 including a second pixel of the plurality of pixels, the memory of the second pixel being configured to receive a second digital data signal at a time different from the time the memory of the first pixel is configured to receive the first digital data signal.

[0242] Example embodiment 51: The electronic display of example embodiment 50, wherein the controller is configured to arbitrate the transmission of one or more digital data signals to one or more pixels by controlling the multiplexing circuitry.

[0243] Example embodiment 52: The electronic display of example embodiment 49, wherein the light emitting circuit includes a light emitting diode, and the first pixel includes a voltage drive circuit configured to amplify the anode of the light emitting diode during a light emitting period of the light emitting diode.

[0244] Example embodiment 53: An electronic display as described in example embodiment 49, wherein the first pixel includes a hybrid drive circuit configured to operate the light emitting circuit to emit light in response to a voltage data signal, a plurality of reference voltages, and an image data control signal based at least in part on the first digital data signal.

[0245] Example 54: The electronic display of Example 49, wherein the light emitting circuitry includes light emitting diodes, organic light emitting diodes, or circuitry supporting a liquid crystal display, a plasma display panel, a dot matrix display, a digital mirror drive display, or any combination thereof.

[0246] Example Embodiment 55: A method comprising: transmitting, via the controller, a first value to a first memory of a first pixel at a first time; performing, via the controller, an initialization process to prepare a first pixel to emit light according to a first value; executing, via the controller, a programming process to program a node of the first pixel with one or more voltage values; and executing, via the controller, an emission process, the execution of the emission process configured to cause light to be emitted from a light emitting circuit of the first pixel.

[0247] Example Embodiment 56: The step of transmitting the first value to the first memory comprises: enabling, by the controller, a first multiplexing control signal via the controller to permit transmission of a first value to a first memory at a first time; The method of example embodiment 55, comprising: arbitrating the programming of the first memory and the second memory of the second pixel by disabling, via the controller, a second multiplexing control signal that stops transmission of the first value to the second memory at the first time.

[0248] Example Embodiment 57: The programming process comprises: Enabling an auto-zero control signal via a controller; and disabling the auto-zero control signal after a predetermined time via the controller.

[0249] Example embodiment 58: The light emitting process is enabling, via the controller, a voltage drive control signal configured to cause amplification of the light emitting circuit; and emitting, via the controller, image data control signals configured to activate the drive transistor in response to a binary pulse width modulated light emission scheme, a single pulse width modulated light emission scheme, a pulse density modulated light emission scheme, or any combination thereof.

[0250] Example embodiment 59: The method described in example embodiment 45, including performing a reset process to reset the lighting circuitry in preparation for future lighting.

[0251] Example embodiment 60: The method described in example embodiment 45, wherein the initialization process includes a step of enabling a selection control signal via the controller, which causes charging of a capacitor, through which the capacitor is configured to transmit a drive current to the first pixel.

Claims

1. 1. An electronic display comprising: a memory located within an active area of ​​the electronic display or within an integrated circuit of the electronic display outside the active area, at least a portion of the memory configured to store a plurality of bits indicating values ​​within a data range, the plurality of bits including a first bit, a second bit, and a third bit in a first order, the first bit being located in a most significant bit position of the first order, the first bit including a first bit state, the third bit including the first bit state, the second bit including a second bit state involving light emission, the first bit state being different from the second bit state; a switch disposed within the active area for selectively providing an electrical signal in response to the plurality of bits stored in the memory being read from the memory; a light modulation device disposed on the active area, the light modulation device configured to emit light based at least in part on the electrical signal; and A display driver circuit; Equipped with The display driver circuit includes: generating a first control signal for writing the first bit, the second bit, and the third bit to the memory in the first order, the first bit being associated with a first light emission time period based on the first order, the second bit being associated with a second light emission time period based on the first order, and the third bit being associated with a third light emission time period based on the first order, the first light emission time period being longer than the second light emission time period, and the second light emission time period being longer than the third light emission time period; determining a second order for permuting the plurality of bits when reading from the memory based on the first order and the second bit including the second bit state; generating a second control signal for reading the second bit from the memory before the first and third bits based on the second order during the second emission time period, the light modulation device being configured to emit light during the second emission time period based on the second bit state of the second bit of the plurality of bits that is read from the memory first. Electronic display.

2. the display driver circuitry is disposed outside the active area; 10. The electronic display of claim 1.

3. the display driver circuitry is disposed outside the active area; the display driver circuitry is configured to perform the step of causing output of each bit of the plurality of bits that includes the second bit state before each bit of the plurality of bits that includes the first bit state.

10. The electronic display of claim 1.

4. the display driver circuit performs the steps of generating the first control signal and the second control signal based on a bit-plane clock characterized by a monotonically increasing time period; the longest time period of the bit plane clock corresponds to the first light emission time period; 4. The electronic display of claim 3.

5. the memory is associated with a pixel, and the portion of the memory is less than the entire memory; 10. The electronic display of claim 1.

6. the value corresponds to a first color channel, and the memory includes unused memory configured to store bits or data for a second color channel, the bits including the first bit state.

10. The electronic display of claim 1.

7. a pixel comprising a current source, the memory, the switch, and the light modulation device; the current source generates the electrical signal for transmission to the optical modulation device; 10. The electronic display of claim 1.

8. the light modulating device comprises an organic light emitting diode; 10. The electronic display of claim 1.

9. the display driver circuitry is configured to simultaneously load different portions of the memory corresponding to different light modulation devices; 10. The electronic display of claim 1.

10. A particular color subpixel of an electronic display, comprising: a first terminal configured to receive a first voltage signal; a second terminal configured to receive a second voltage signal; a memory configured to store a plurality of bits indicative of a value within a data range, the plurality of bits including a first bit, a second bit, and a third bit in a first order, the first bit being disposed in a most significant bit position of the first order, the first bit being associated with a first light emission time period based on the first order, the second bit being associated with a second light emission time period based on the first order, and the third bit being associated with a third light emission time period based on the first order, the first light emission time period being longer than the second light emission time period, and the second light emission time period being longer than the third light emission time period; a light emitting diode configured to emit light in response to a current transmitted through a switch, wherein a control signal is generated based on the second bit read from the memory before the first bit and the third bit, the second bit being read from the memory before the first bit and the third bit based on the first bit and the third bit comprising a first bit state and the second bit comprising a second bit state, the second bit state being associated with light emission differently than the first bit state, and the current being based at least in part on the first voltage signal and the second voltage signal; Equipped with The light emitting diode is configured to emit light for the second light emission time period based on the second bit of the plurality of bits that is read out from the memory first.

11. the first voltage signal comprises a data voltage and the second voltage signal comprises a system voltage; The subpixel of claim 10.

12. a current source configured to generate the current based on the first voltage signal and the second voltage signal. The subpixel of claim 10.

13. 1. An electronic display comprising: a first sub-pixel corresponding to a first color channel; a second sub-pixel corresponding to a second color channel; The first sub-pixel comprises: a first memory configured to store a first plurality of bits indicating a first value within a first data range used to communicate image data for the first color channel, the first plurality of bits including a first bit, a second bit, and a third bit in a first order, the first bit being disposed in a most significant bit position of the first order, the first bit including a first bit state, the third bit including the first bit state, the second bit including a second bit state involving light emission, the first bit state being different from the second bit state; generating a first control signal for writing the first bit, the second bit, and the third bit to the first memory in the first order, the first bit being associated with a first light emission time period based on the first order, the second bit being associated with a second light emission time period based on the first order, and the third bit being associated with a third light emission time period based on the first order, the first light emission time period being longer than the second light emission time period, and the second light emission time period being longer than the third light emission time period; determining a second order for permuting the first plurality of bits when read from the first memory based on the first order and the second bits including the second bit states; generating a second control signal for reading the second bit from the first memory prior to the first bit and the third bit according to the second order during the second light emission time period; a first driver circuit configured to perform the steps of: generating a third control signal based on the second bit to cause transmission of an electrical signal through the first light emitting diode during the second light emitting time period, thereby causing the first light emitting diode to at least partially emit light; Including, the first driving circuit causes the first light emitting diode to emit light for the second light emission time period based on the second bit of the first plurality of bits that is read out first from the first memory; The second sub-pixel has a second memory configured to store a second plurality of bits indicative of a second value within a second data range used to communicate image data for the second color channel; and a second drive circuit configured to receive the second plurality of bits from the second memory, the second drive circuit configured to cause a second light emitting diode to at least partially emit light by generating a fourth control signal based on the second plurality of bits; Including, Electronic display.

14. the first drive circuit comprises a row driver; 14. The electronic display of claim 13.

15. For the second subpixel, the second drive circuit is configured to receive the second plurality of bits from the second memory in a different order than the input to the second memory.

14. The electronic display of claim 13.

16. the first sub-pixel is configured to be programmed with the first plurality of bits before the second sub-pixel is programmed with the second plurality of bits.

14. The electronic display of claim 13.

17. The first drive circuit includes: generating a fifth control signal for causing the third bit to be output from the first memory after the first bit and the second bit based on the third bit including the first bit state.

14. The electronic display of claim 13.

18. the first driver circuit is configured to generate one or more control signals causing each bit of the first plurality of bits to be output from the first memory in the second order.

14. The electronic display of claim 13.

19. the first driver circuit is configured to generate the one or more control signals according to a time period of a bit-plane clock.

20. The electronic display of claim 18.

Images