Synthesis circuit

Abstract

This multiplexing circuit comprises a transfer circuit and a control circuit. The transfer circuit comprises: an inductance value switching circuit that includes a plurality of inductors; a plurality of first switch elements; a capacitance value switching circuit that includes a plurality of capacitors; and a plurality of second switch elements. The control circuit comprises a plurality of first comparators, a plurality of second comparators, and a voltage-dividing circuit that is configured to divide a reference voltage to output a divided voltage. The first comparators are configured to compare the divided voltage with a sawtooth wave input voltage, and to control the first switch elements to closed state if the sawtooth wave input voltage is lower than the divided voltage. The second comparators are configured to compare the divided voltage with the sawtooth wave input voltage, and to control the second switch elements to closed state if the sawtooth wave input voltage is greater than the divided voltage.

Description

[Technical field]

[0001] The present disclosure relates to a synthesis circuit. [Background technology]

[0002] A backscattering method is known as a data communication method for wireless communication devices. For example, Patent Document 1 discloses a technique for realizing a single sideband by suppressing either an upper sideband (USB) signal or a lower sideband (LSB) signal using a splitter / combiner. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2005-323223 A Summary of the Invention

[0004] A combining circuit according to an aspect of the present disclosure includes a transmission circuit configured to be connected to an antenna, and a control circuit configured to control an impedance of the transmission circuit, the transmission circuit including an inductance value switching circuit including a plurality of inductors, a plurality of first switch elements connected to each of the plurality of inductors, a capacitance value switching circuit including a plurality of capacitors, and a plurality of second switch elements connected to each of the plurality of capacitors, the control circuit including a plurality of first comparators connected to each of the first switch elements, and a plurality of second comparators connected to each of the second switch elements. and a voltage divider circuit constituted of a plurality of resistance elements configured to divide a reference voltage and output a divided voltage to each of the plurality of first comparators and the plurality of second comparators, wherein the first comparator is configured to compare the divided voltage with an input voltage having a sawtooth waveform, and control the first switch element to a closed state when the input voltage having the sawtooth waveform is lower than the divided voltage, and the second comparator is configured to compare the divided voltage with the input voltage having the sawtooth waveform, and control the second switch element to a closed state when the input voltage having the sawtooth waveform is higher than the divided voltage.

[0005] A combining circuit according to one embodiment of the present disclosure includes a transmission circuit configured to be connected to an antenna and a control circuit configured to control the impedance of the transmission circuit, wherein the transmission circuit includes a capacitance value switching circuit including a plurality of capacitors and a plurality of switch elements connected to each of the plurality of capacitors, and the control circuit includes a plurality of comparators connected to each of the switch elements and a voltage divider circuit composed of a plurality of resistive elements configured to divide a reference voltage and output the divided voltage to each of the plurality of comparators, and an inductor is configured to be connected between an output terminal of the transmission circuit and the antenna.

[0006] A combining circuit according to one embodiment of the present disclosure is a combining circuit including a transmission circuit configured to be connected to an antenna and a control circuit configured to control the impedance of the transmission circuit, wherein the transmission circuit includes an inductance value switching circuit including a plurality of inductors and a plurality of switch elements connected to each of the plurality of inductors, and the control circuit includes a plurality of comparators connected to each of the switch elements and a voltage divider circuit including a plurality of resistive elements configured to divide a reference voltage and output a divided voltage to each of the plurality of comparators, and a capacitor is configured to be connected between an output terminal of the transmission circuit and the antenna. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a block diagram showing an example of a configuration of a wireless communication device according to an embodiment. [Diagram 2] FIG. 2 is a diagram for explaining a method for controlling the rotation of impedance on a complex plane according to the embodiment. [Figure 3A] FIG. 3A is a diagram for explaining a change in a backscatter signal. [Figure 3B] FIG. 3B is a diagram for explaining a change in the backscatter signal. [Figure 3C] FIG. 3C is a diagram for explaining a change in the backscatter signal. [Figure 4] FIG. 4 is a diagram for explaining a method for controlling the impedance of the transmission circuit according to the first embodiment. [Diagram 5] FIG. 5 is a diagram illustrating an example of an input signal according to the first embodiment. [Figure 6] FIG. 6 is a diagram illustrating an example of an input signal according to the first embodiment. [Figure 7] FIG. 7 is a diagram for explaining the operation of the transmission circuit according to the first embodiment. [Figure 8] FIG. 8 is a diagram showing an example of a spectral waveform of a backscattering signal according to the first embodiment. [Figure 9]FIG. 9 is a diagram showing an example of a spectral waveform of a backscattering signal according to the first embodiment. [Figure 10] FIG. 10 is a diagram for explaining a method for controlling the impedance of the transmission circuit according to the second embodiment. [Figure 11] FIG. 11 is a diagram for explaining the operation of the transmission circuit according to the second embodiment. [Figure 12] FIG. 12 is a diagram showing an example of a spectral waveform of a backscattering signal according to the second embodiment. [Figure 13] FIG. 13 is a diagram showing an example of a spectral waveform of a backscattering signal according to the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Note that the present disclosure is not limited to these embodiments, and when there are multiple embodiments, the present disclosure also includes a configuration in which each embodiment is combined. In the following embodiments, the same parts are denoted by the same reference numerals, and duplicated descriptions are omitted.

[0009] [Embodiment] The configuration of a wireless communication device according to an embodiment will be described with reference to Fig. 1. Fig. 1 is a block diagram showing an example of the configuration of a wireless communication device according to an embodiment.

[0010] 1, the wireless communication device 1 includes an antenna 10, a BPF (Band Pass Filter) 11, an RFBS (Radio Frequency Backscatter) device 20, a control device 30, and a sensor 40. The wireless communication device 1 is a communication device configured to perform wireless communication using a backscatter method such as RFID.

[0011] The antenna 10 is configured to receive a signal transmitted to the wireless communication device 1. The antenna 10 is configured to transmit radio waves toward the outside of the wireless communication device 1. The BPF 11 is a filter configured to pass a signal in a desired frequency band.

[0012] The RFBS device 20 includes a high frequency switch 21, an amplifier 22, a demodulator 23, an oscillator 24, an LPF (Low Pass Filter) 25, an LPF 26, a control circuit 27, and a transmission circuit 28. The RFBS device 20 is a wireless communication device that supports backscattering data communication. In backscattering data communication, communication is performed by utilizing the reflection of transmitted radio waves.

[0013] The high frequency switch 21 is configured to switch the connection between the antenna 10 and a transmission circuit system or a reception circuit system. The high frequency switch 21 is configured to be able to connect the transmission circuit system to the antenna 10. The wireless communication device 1 is configured to transmit when the antenna 10 is connected to the transmission circuit system. The high frequency switch 21 is configured to be able to connect the reception circuit system to the antenna 10. The transmission circuit system includes an oscillator 24, an LPF 25, an LPF 26, a control circuit 27, and a transmission circuit 28. The reception circuit system includes an amplifier 22 and a demodulator 23.

[0014] The amplifier 22 is configured to amplify and output a signal received from the antenna 10. The amplifier 22 is configured to output the amplified signal to the demodulation unit 23. The demodulation unit 23 is configured to perform demodulation processing on the input signal. The demodulation unit 23 is configured to demodulate the signal received from the amplifier 22. For example, the demodulation unit 23 is configured to perform demodulation processing on the signal received from the amplifier 22 (a modulated signal such as ASK (Amplitude Shift Keying)).

[0015] The control device 30 is realized, for example, by a processor or the like executing a program stored therein using a RAM (Random Access Memory) or the like as a working area. The control device 30 may be a controller. The control device 30 may be realized, for example, by an integrated circuit such as an ASIC (Application Specific Integrated Circuit) or an FPGA (Field Programmable Gate Array). The control device 30 may be realized by a combination of software and hardware.

[0016] The control device 30 is configured to output serial data S1 based on output data from the sensor 40 to the control circuit 27 via the LPF 25. The control device 30 is configured to output serial data S2 based on output data from the sensor 40 to the control circuit 27 via the LPF 26. The serial data S1 and the serial data S2 are out of phase with each other by approximately 90°.

[0017] The control device 30 is configured to output a control signal S3 for suppressing either the USB signal or the LSB signal relative to the carrier signal to the control circuit 27. The control device 30 is configured to output a control signal S4 for controlling a channel used for communication to the oscillator 24.

[0018] The sensor 40 is configured to detect various physical quantities. There is no particular limit to the physical quantities detected by the sensor 40. The sensor 40 may include, for example, one or both of a temperature sensor configured to detect the temperature around the wireless communication device 1 and an acceleration sensor configured to detect acceleration occurring in the wireless communication device 1. The sensor 40 may include other sensors.

[0019] The oscillator 24 is configured to generate an oscillation signal of a predetermined frequency. The oscillator 24 is configured to generate an oscillation signal S5 in accordance with a control signal S4. The oscillator 24 is configured to generate an oscillation signal S6 that is 90° out of phase with the oscillation signal S5.

[0020] The control circuit 27 is configured to control the transmission circuit 28. The control circuit 27 is configured to control the impedance value of the transmission circuit 28 based on the serial data S1, the serial data S2, and the control signal S3. The control circuit 27 is configured to change the impedance of the transmission circuit 28. Due to the change in impedance, the reflection coefficient of the output terminal on the antenna 10 side rotates in the complex plane. The control circuit 27 changes the impedance of the transmission circuit 28 to control the reflection coefficient of the output terminal to rotate in the complex plane. For example, the control circuit 27 is configured to control the impedance of the transmission circuit 28 so as to reduce the USB signal or LSB signal relative to the carrier signal in the reflected signal (hereinafter also referred to as the backscatter signal) and realize a single sideband.

[0021] A method in which the control circuit 27 controls the reflection coefficient of the output terminal of the transmission circuit 28 on the antenna 10 side to rotate on the complex plane of the polar chart will be described using the polar chart (polar coordinates) in Fig. 2. Fig. 2 is a diagram for explaining a method in which the control circuit 27 changes the impedance of the transmission circuit 28 and controls the reflection coefficient of the output terminal to rotate.

[0022] Figure 2 shows the change in reflection coefficient Γ due to the change in impedance on a polar chart. Impedance is calculated by the following formula (1). In formula (1), Z is impedance, R is resistance, j is an imaginary number, ω is angular frequency, L is inductance, and C is capacitance. Z = R + j(ωL-1 / ωC) (1)

[0023] The reflection coefficient Γ can be expressed by the following equation: Γ=(Z-Z0) / (Z+Z0) (2) Here, Z0 is the impedance of the antenna 10 or the BPF 11.

[0024] The control circuit 27 selects and controls the impedance Z to control the reflection coefficient Γ to rotate around a reference point. The reference point includes the origin, but is not limited to the origin, and includes any point. The closer the reference point is to the origin, the more likely it is that the transmission circuit will obtain a signal that is closer to the ideal. The more the transmission circuit is controlled to rotate in a circle around the reference point, the more likely it is that the signal will be closer to the ideal. In terms of a Smith chart, the lower semicircular area indicates capacitive properties, and the upper half indicates inductive properties. Changes on the real axis represent changes in resistance value.

[0025] The control circuit 27 can selectively control a plurality of impedances included in the transmission circuit 28. For example, the control circuit 27 is configured to control the impedance of the transmission circuit 28 in increments of 45°, i.e., 0°, 45°, 90°, 135°, 180°, −135°, −90°, and −45°. The control circuit 27 is configured to control the reflection coefficient Γ by controlling the impedance. The control circuit 27 is configured to be able to control the impedance to rotate discretely by sequentially changing the impedance of the transmission circuit 28. The control circuit 27 rotates the reflection coefficient Γ discretely in response to the discrete rotation of the impedance.

[0026] The control circuit 27 is configured to be able to change the impedance in a counterclockwise direction by changing the impedance of the transmission circuit 28. The control circuit 27 is configured to be able to change the reflection coefficient Γ in a counterclockwise direction by rotating the impedance in a counterclockwise direction. When the control of the reflection coefficient is in a counterclockwise direction, the reflected signal for the RF (Radio Frequency) is only a USB (Upper Side Band) signal. When the control is performed so that the reflection coefficient is in a clockwise direction, only a LSB (Lower Side Band) signal is obtained. At that time, the frequency of the reflected signal is a frequency detuned by the rotation speed frequency from the RF signal frequency. Using FIG. 3A, FIG. 3B, and FIG. 3C, some examples of changes in the backscatter signal caused by changing the impedance and controlling the reflection coefficient will be described.

[0027] FIG. 3A is a diagram showing a frequency spectrum for explaining the state of a backscatter signal when the control circuit 27 controls only the resistance component of the impedance and changes the reflection coefficient Γ on the real axis of the polar chart (FIG. 2). The horizontal axis shows frequency, and the vertical axis shows the intensity of the RF signal and the reflected signal. FIG. 3A shows a carrier signal 51, a USB signal 52, and an LSB signal 53. When the resistance component is controlled, the reflection coefficient Γ is controlled to either 0° or 180° on the real axis. When the reflection coefficient Γ is controlled by changing the impedance only with the resistance component, as shown in FIG. 3A, for example, when switching from 0° to 180°, a right-handed signal component and a left-handed signal component are inherent. Due to the existence of signal components of two rotation directions, the USB signal 52 and the LSB signal 53 appear simultaneously, and it is not possible to selectively suppress only one of the signals. As a result, an SSB signal cannot be obtained by controlling only the resistance component.

[0028] FIG. 3B is a diagram showing a frequency spectrum for explaining the change in the backscatter signal when the control circuit 27 changes the inductance / capacitance of the impedance to control the locus of the reflection coefficient Γ to draw a circle. The horizontal axis indicates the frequency, and the vertical axis indicates the intensity of the RF signal and the reflected signal. Based on the formulas (1) and (2), the control circuit 27 can control the impedance to rotate counterclockwise by controlling the value of the inductance. At this time, the impedance rotates counterclockwise, for example, from 0° to 45°, 90°, and 135°. The control circuit 27 can further control the impedance to rotate counterclockwise by controlling the value of the capacitance. At this time, the impedance rotates counterclockwise, for example, from 180° to -135°, -90°, and -45°. As shown in FIG. 3B, the control circuit 27 can reflect the transmitted RF signal so as to suppress the LSB signal 53 by controlling the impedance to rotate counterclockwise. In other words, the control circuit 27 can obtain a backscattered signal converted into SSB in the USB signal 52 by controlling the impedance to rotate counterclockwise.

[0029] FIG. 3C is a diagram for explaining the change of the backscatter signal when the control circuit 27 changes the capacitance / inductance of the impedance and controls the locus of the reflection coefficient Γ to draw a circle. Based on the formulas (1) and (2), the control circuit 27 can control the impedance to rotate clockwise by controlling the capacitance value. At this time, the impedance rotates clockwise, for example, from 0° to −45°, −90°, and −135°. The control circuit 27 can further control the impedance to rotate clockwise by controlling the inductance value. At this time, the impedance rotates clockwise, for example, from 180° to 135°, 90°, and 45°. As shown in FIG. 3C, the control circuit 27 can reflect the transmitted RF signal so as to suppress the USB signal 52 by controlling the impedance to rotate clockwise. In other words, the control circuit 27 can obtain the backscatter signal that has been SSB-converted into the LSB signal 53 by controlling the clockwise rotation of the impedance.

[0030] The transmission circuit 28 is disposed at the front end of the wireless communication device 1. The transmission circuit 28 is a circuit configured to perform backscatter communication in which a transmitted radio wave is reflected as a backscatter signal. The transmission circuit 28 is configured to be connected to the antenna 10. The transmission circuit 28 includes a plurality of impedance circuits each having a different impedance. Each of the plurality of impedance circuits includes a switch element. The switch element is configured to switch the connection of the impedance circuit. The control circuit 27 is configured to switch the connection of the plurality of impedance circuits by controlling the plurality of switch elements. The control circuit 27 is configured to control the impedance of the transmission circuit 28 by controlling the plurality of switch elements.

[0031] [First embodiment] [Impedance control method] A method for controlling the impedance of the transmission circuit according to the first embodiment will be described with reference to Fig. 4. Fig. 4 is a diagram for explaining a method for controlling the impedance of the transmission circuit according to the first embodiment. The control circuit 27 receives an input signal corresponding to transmission data to be transmitted to an external device. The control circuit 27 outputs a control signal for controlling the impedance of the transmission circuit 28 in response to the control signal.

[0032] In this embodiment, the input signal input to the control signal is an input signal having a sawtooth waveform (hereinafter, simply referred to as a sawtooth wave). The sawtooth wave may be a rising sawtooth wave indicating a rising edge, or a falling sawtooth wave indicating a falling edge. In this embodiment, the method of controlling impedance is changed depending on whether the sawtooth wave is a rising sawtooth wave or a falling sawtooth wave.

[0033] Fig. 4 shows the configuration of a drive control circuit 29 corresponding to the output section of the control circuit 27 in Fig. 1, and a transmission circuit 28. The drive control circuit 29 is a drive control circuit for the transmission circuit 28 that switches impedance and controls the reflection coefficient Γ to rotate on a complex plane. The drive control circuit 29 and the transmission circuit 28 may also be referred to as a synthesis circuit.

[0034] As shown in FIG. 4, the drive control circuit 29 includes a reference power supply V, a resistive element R1, a resistive element R2, a resistive element R3, a resistive element R4, a resistive element R5, a resistive element R6, a resistive element R7, a resistive element R8, a resistive element R9, a resistive element R10, a resistive element R11, a resistive element R12, a resistive element R13, a resistive element R14, a resistive element R15, a resistive element R16, and a resistive element R17. The drive control circuit 29 also includes a comparator CML1, a comparator CML2, a comparator CML3, a comparator CML4, a comparator CML5, a comparator CML6, a comparator CML7, a comparator CML8, a comparator CMC1, a comparator CMC2, a comparator CMC3, a comparator CMC4, a comparator CMC5, a comparator CMC6, a comparator CMC7, and a comparator CMC8.

[0035] An input signal S11 is input to the drive control circuit 29. Fig. 5 and Fig. 6 are diagrams showing an example of an input signal according to the first embodiment. In Fig. 5 and Fig. 6, the horizontal axis is time (S) and the vertical axis is signal level (V). Fig. 5 shows a waveform W1. The waveform W1 is an example of a rising sawtooth wave. Fig. 6 shows a waveform W2. The waveform W2 is an example of a falling sawtooth wave. In the first embodiment, the input signal S11 can be a rising sawtooth wave or a falling sawtooth wave, as shown in the waveform W1 or waveform W2.

[0036] The transmission circuit 28 includes an inductance value switching circuit 110 and a capacitance value switching circuit 120. The inductance value switching circuit 110 and the capacitance value switching circuit 120 are a type of impedance circuit.

[0037] The resistor elements R1 to R9 are connected in series. The resistor element R1 is connected to a reference power supply V. The resistor element R9 is connected to a reference potential. The resistor elements R1 to R9 and the comparators CML1 to CML8 form a voltage divider circuit that outputs a control signal to the inductance value switching circuit 110.

[0038] The node N1 is a node to which the input signal S11 is input. The node N2 is a node between the resistor element R1 and the resistor element R2. The node N3 is a node between the resistor element R2 and the resistor element R3. The node N4 is a node between the resistor element R3 and the resistor element R4. The node N5 is a node between the resistor element R4 and the resistor element R5. The node N6 is a node between the resistor element R5 and the resistor element R6. The node N7 is a node between the resistor element R6 and the resistor element R7. The node N8 is a node between the resistor element R7 and the resistor element R8. The node N9 is a node between the resistor element R8 and the resistor element R17. A reference signal according to the voltage value of the input signal S11 can be output from the node N1. A divided voltage according to the voltage value of the reference power supply V and the resistance values ​​of the resistor elements R1 to R8 can be output as an output signal from the nodes N2 to 9.

[0039] A node N1 is electrically connected to one input terminal of the comparator CML1. A node N2 is electrically connected to the other input terminal of the comparator CML1. An output terminal of the comparator CML1 is electrically connected to the switch element SWL1 of the inductance value switching circuit 110. The comparator CML1 is configured to compare an input signal S11 input from the node N1 with a first divided voltage as a control signal input from the node N2, and output a switch control signal according to the comparison result. For example, the comparator CML1 is configured to output a switch control signal that closes the switch element SWL1 if the first divided voltage is greater than the input signal S11. The comparator CML1 is configured to output a switch control signal that opens the switch element SWL1 if the first divided voltage is smaller than the input signal S11.

[0040] A node N1 is electrically connected to one input terminal of the comparator CML2. A node N3 is electrically connected to the other input terminal of the comparator CML2. An output terminal of the comparator CML2 is electrically connected to the switch element SWL2 of the inductance value switching circuit 110. The comparator CML2 is configured to compare the input signal S11 input from the node N1 with the second divided voltage as a control signal input from the node N3, and output a switch control signal according to the comparison result. For example, the comparator CML2 is configured to output a switch control signal that closes the switch element SWL2 if the second divided voltage is greater than the input signal S11. The comparator CML2 is configured to output a switch control signal that opens the switch element SWL2 if the second divided voltage is smaller than the input signal S11.

[0041] A node N1 is electrically connected to one input terminal of the comparator CML3. A node N4 is electrically connected to the other input terminal of the comparator CML3. An output terminal of the comparator CML3 is electrically connected to the switch element SWL3 of the inductance value switching circuit 110. The comparator CML3 is configured to compare the input signal S11 input from the node N1 with the third divided voltage as a control signal input from the node N4, and output a switch control signal according to the comparison result. For example, the comparator CML3 is configured to output a switch control signal that closes the switch element SWL3 if the third divided voltage is greater than the input signal S11. The comparator CML3 is configured to output a switch control signal that opens the switch element SWL3 if the third divided voltage is smaller than the input signal S11.

[0042] A node N1 is electrically connected to one input terminal of the comparator CML4. A node N5 is electrically connected to the other input terminal of the comparator CML4. An output terminal of the comparator CML4 is electrically connected to the switch element SWL4 of the inductance value switching circuit 110. The comparator CML4 is configured to compare the input signal S11 input from the node N1 with the fourth divided voltage as a control signal input from the node N5, and output a switch control signal according to the comparison result. For example, the comparator CML4 is configured to output a switch control signal that closes the switch element SWL4 if the fourth divided voltage is greater than the input signal S11. The comparator CML4 is configured to output a switch control signal that opens the switch element SWL4 if the fourth divided voltage is smaller than the input signal S11.

[0043] A node N1 is electrically connected to one input terminal of the comparator CML5. A node N6 is electrically connected to the other input terminal of the comparator CML5. An output terminal of the comparator CML5 is electrically connected to the switch element SWL5 of the inductance value switching circuit 110. The comparator CML5 is configured to compare the input signal S11 input from the node N1 with the fifth divided voltage as a control signal input from the node N6, and output a switch control signal according to the comparison result. For example, the comparator CML5 is configured to output a switch control signal that closes the switch element SWL5 if the fifth divided voltage is greater than the input signal S11. The comparator CML5 is configured to output a switch control signal that opens the switch element SWL5 if the fifth divided voltage is smaller than the input signal S11.

[0044] A node N1 is electrically connected to one input terminal of the comparator CML6. A node N7 is electrically connected to the other input terminal of the comparator CML6. An output terminal of the comparator CML6 is electrically connected to the switch element SWL6 of the inductance value switching circuit 110. The comparator CML6 is configured to compare the input signal S11 input from the node N1 with the sixth divided voltage as a control signal input from the node N7, and output a switch control signal according to the comparison result. For example, the comparator CML6 is configured to output a switch control signal that closes the switch element SWL6 if the sixth divided voltage is greater than the input signal S11. The comparator CML6 is configured to output a switch control signal that opens the switch element SWL6 if the sixth divided voltage is smaller than the input signal S11.

[0045] A node N1 is electrically connected to one input terminal of the comparator CML7. A node N8 is electrically connected to the other input terminal of the comparator CML7. An output terminal of the comparator CML7 is electrically connected to the switch element SWL7 of the inductance value switching circuit 110. The comparator CML7 is configured to compare the input signal S11 input from the node N1 with the seventh divided voltage as a control signal input from the node N8, and output a switch control signal according to the comparison result. For example, the comparator CML7 is configured to output a switch control signal that closes the switch element SWL7 if the seventh divided voltage is greater than the input signal S11. The comparator CML7 is configured to output a switch control signal that opens the switch element SWL7 if the seventh divided voltage is smaller than the input signal S11.

[0046] A node N1 is electrically connected to one input terminal of the comparator CML8. A node N9 is electrically connected to the other input terminal of the comparator CML8. An output terminal of the comparator CM8 is electrically connected to the switch element SWL8 of the inductance value switching circuit 110. The comparator CML8 is configured to compare the input signal S11 input from the node N1 with the eighth divided voltage as a control signal input from the node N9, and output a switch control signal according to the comparison result. For example, the comparator CML8 is configured to output a switch control signal that closes the switch element SWL8 if the eighth divided voltage is greater than the input signal S11. The comparator CML8 is configured to output a switch control signal that opens the switch element SWL8 if the eighth divided voltage is smaller than the input signal S11.

[0047] That is, the comparators CML1 to CML8 are configured to control the switch elements to the closed state when the input signal S11 is lower than the divided voltage.

[0048] The resistor elements R9 to R17 are connected in series. The resistor elements R1 to R8 and the resistor elements R9 to R17 are connected in series. The resistor element R9 is connected to a reference potential. The resistor elements R9 to R17 and the comparators CMC1 to CMC8 form a voltage divider circuit that outputs a control signal to the capacitance value switching circuit 120.

[0049] The node N17 is a node between the resistor element R9 and the resistor element R10. The node N18 is a node between the resistor element R10 and the resistor element R11. The node N19 is a node between the resistor element R11 and the resistor element R12. The node N20 is a node between the resistor element R12 and the resistor element R13. The node N21 is a node between the resistor element R13 and the resistor element R14. The node N22 is a node between the resistor element R14 and the resistor element R15. The node N23 is a node between the resistor element R15 and the resistor element R16. The node N24 is a node between the resistor element R16 and the resistor element R17.

[0050] A node N1 is electrically connected to one input terminal of the comparator CMC1. A node N17 is electrically connected to the other input terminal of the comparator CMC1. An output terminal of the comparator CMC1 is electrically connected to the switch element SWC1 of the capacitance value switching circuit 120. The comparator CMC1 is configured to compare the input signal S11 input from the node N1 with the ninth divided voltage as a control signal input from the node N17, and output a switch control signal according to the comparison result. For example, the comparator CMC1 is configured to output a switch control signal that opens the switch element SWC1 if the ninth divided voltage is greater than the input signal S11. The comparator CMC1 is configured to output a switch control signal that closes the switch element SWC1 if the ninth divided voltage is smaller than the input signal S11.

[0051] The node N1 is electrically connected to one input terminal of the comparator CMC2. The node N18 is electrically connected to the other input terminal of the comparator CMC2. The output terminal of the comparator CMC2 is electrically connected to the switch element SWC2 of the capacitance value switching circuit 120. The comparator CMC2 is configured to compare the input signal S11 input from the node N1 with the tenth divided voltage as a control signal input from the node N18, and output a switch control signal according to the comparison result. For example, the comparator CMC2 is configured to output a switch control signal that opens the switch element SWC2 if the tenth divided voltage is greater than the input signal S11. The comparator CMC2 is configured to output a switch control signal that closes the switch element SWC2 if the tenth divided voltage is smaller than the input signal S11.

[0052] A node N1 is electrically connected to one input terminal of the comparator CMC3. A node N19 is electrically connected to the other input terminal of the comparator CMC3. An output terminal of the comparator CMC3 is electrically connected to the switch element SWC3 of the capacitance value switching circuit 120. The comparator CMC3 is configured to compare the input signal S11 input from the node N1 with the eleventh divided voltage as a control signal input from the node N19, and output a switch control signal according to the comparison result. For example, the comparator CMC3 is configured to output a switch control signal that opens the switch element SWC3 if the eleventh divided voltage is greater than the input signal S11. The comparator CMC3 is configured to output a switch control signal that closes the switch element SWC3 if the eleventh divided voltage is smaller than the input signal S11.

[0053] A node N1 is electrically connected to one input terminal of the comparator CMC4. A node N20 is electrically connected to the other input terminal of the comparator CMC4. An output terminal of the comparator CMC4 is electrically connected to the switch element SWC4 of the capacitance value switching circuit 120. The comparator CMC4 is configured to compare the input signal S11 input from the node N1 with the twelfth divided voltage as a control signal input from the node N20, and output a switch control signal according to the comparison result. For example, the comparator CMC4 is configured to output a switch control signal that opens the switch element SWC4 if the twelfth divided voltage is greater than the input signal S11. The comparator CMC4 is configured to output a switch control signal that closes the switch element SWC4 if the twelfth divided voltage is smaller than the input signal S11.

[0054] A node N1 is electrically connected to one input terminal of the comparator CMC5. A node N21 is electrically connected to the other input terminal of the comparator CMC5. An output terminal of the comparator CMC5 is electrically connected to the switch element SWC5 of the capacitance value switching circuit 120. The comparator CMC5 is configured to compare the input signal S11 input from the node N1 with the thirteenth divided voltage as a control signal input from the node N21, and output a switch control signal according to the comparison result. For example, the comparator CMC5 is configured to output a switch control signal that opens the switch element SWC5 if the thirteenth divided voltage is greater than the input signal S11. The comparator CMC5 is configured to output a switch control signal that closes the switch element SWC5 if the thirteenth divided voltage is smaller than the input signal S11.

[0055] A node N1 is electrically connected to one input terminal of the comparator CMC6. A node N22 is electrically connected to the other input terminal of the comparator CMC6. An output terminal of the comparator CMC6 is electrically connected to the switch element SWC6 of the capacitance value switching circuit 120. The comparator CMC6 is configured to compare the input signal S11 input from the node N1 with the 14th divided voltage as a control signal input from the node N22, and output a switch control signal according to the comparison result. For example, the comparator CMC6 is configured to output a switch control signal that opens the switch element SWC6 if the 14th divided voltage is greater than the input signal S11. The comparator CMC6 is configured to output a switch control signal that closes the switch element SWC6 if the 14th divided voltage is smaller than the input signal S11.

[0056] A node N1 is electrically connected to one input terminal of the comparator CMC7. A node N23 is electrically connected to the other input terminal of the comparator CMC7. An output terminal of the comparator CMC7 is electrically connected to the switch element SWC7 of the capacitance value switching circuit 120. The comparator CMC7 is configured to compare the input signal S11 input from the node N1 with the 15th divided voltage as a control signal input from the node N23, and output a switch control signal according to the comparison result. For example, the comparator CMC7 is configured to output a switch control signal that opens the switch element SWC7 if the 15th divided voltage is greater than the input signal S11. The comparator CMC7 is configured to output a switch control signal that closes the switch element SWC7 if the 15th divided voltage is smaller than the input signal S11.

[0057] A node N1 is electrically connected to one input terminal of the comparator CMC8. A node N24 is electrically connected to the other input terminal of the comparator CMC8. An output terminal of the comparator CMC8 is electrically connected to the switch element SWC8 of the capacitance value switching circuit 120. The comparator CMC8 is configured to compare the input signal S11 input from the node N1 with the 16th divided voltage as a control signal input from the node N24, and output a switch control signal according to the comparison result. For example, the comparator CMC8 is configured to output a switch control signal that opens the switch element SWC8 if the 16th divided voltage is greater than the input signal S11. The comparator CMC8 is configured to output a switch control signal that closes the switch element SWC8 if the 16th divided voltage is smaller than the input signal S11.

[0058] That is, the comparators CMC1 to CMC8 are configured to control the switch elements to the closed state when the input signal S11 is higher than the divided voltage. Therefore, in the present disclosure, the comparators CML1 to CML8 and the comparators CMC1 to CMC8 are configured to perform the opposite comparison operations.

[0059] [Inductance value switching circuit] The following describes the configuration of the inductance value switching circuit 110. The inductance value switching circuit 110 includes a switch element SWL1, a switch element SWL2, a switch element SWL3, a switch element SWL4, a switch element SWL5, a switch element SWL6, a switch element SWL7, a switch element SWL8, an inductor L1, an inductor L2, an inductor L3, an inductor L4, an inductor L5, an inductor L6, an inductor L7, and a high-resistance element RL.

[0060] An input terminal of the switch element SWL1 is electrically connected to an output terminal of the comparator CML1. One end of the output terminal of the switch element SWL1 is electrically connected to a reference potential via one end of the inductor L1 and a high resistance element RL. The other end of the output terminal of the switch element SWL1 is connected to the reference potential. The other end of the inductor L1 is electrically connected to the selection circuit 130 via inductors L2 to L7. The switch element SWL1 is configured to electrically connect the inductor L1 and the selection circuit 130 when in a closed state. When the switch element SWL1 is in a closed state and the switch elements SWL2 to SWL8 are in an open state, the impedance of the inductance value switching circuit 110 becomes the sum of the inductances of the inductors L1 to L7.

[0061] An input terminal of the switch element SWL2 is electrically connected to an output terminal of the comparator CML2. One end of the output terminal of the switch element SWL2 is electrically connected to the other end of the inductor L1 and one end of the inductor L2. The other end of the output terminal of the switch element SWL2 is connected to a reference potential. The other end of the inductor L2 is electrically connected to the selection circuit 130 via inductors L3 to L7. The switch element SWL2 is configured to electrically connect the inductor L2 and the selection circuit 130 when in a closed state. When the switch element SWL2 is in a closed state and the switch elements SWL3 to SWL8 are in an open state, the impedance of the inductance value switching circuit 110 becomes the sum of the inductances of the inductors L2 to L7.

[0062] An input terminal of the switch element SWL3 is electrically connected to an output terminal of the comparator CML3. One end of the output terminal of the switch element SWL3 is electrically connected to the other end of the inductor L2 and one end of the inductor L3. The other end of the output terminal of the switch element SWL3 is connected to a reference potential. The other end of the inductor L3 is electrically connected to the selection circuit 130 via inductors L4 to L7. The switch element SWL3 is configured to electrically connect the inductor L3 and the selection circuit 130 when in a closed state. When the switch element SWL3 is in a closed state and the switch elements SWL4 to SWL8 are in an open state, the impedance of the inductance value switching circuit 110 becomes the sum of the inductances of the inductors L3 to L7.

[0063] An input terminal of the switch element SWL4 is electrically connected to an output terminal of the comparator CML4. One end of the output terminal of the switch element SWL4 is connected to the other end of the inductor L3 and one end of the inductor L4. The other end of the output terminal of the switch element SWL4 is connected to a reference potential. The other end of the inductor L4 is electrically connected to the selection circuit 130 via inductors L5 to L7. The switch element SWL4 is configured to electrically connect the inductor L4 and the selection circuit 130 when in a closed state. When the switch element SWL4 is in a closed state and the switch elements SWL5 to SWL8 are in an open state, the impedance of the inductance value switching circuit 110 becomes the sum of the inductances of the inductors L4 to L7.

[0064] An input terminal of the switch element SWL5 is electrically connected to an output terminal of the comparator CML5. One end of the output terminal of the switch element SWL5 is electrically connected to the other end of the inductor L4 and one end of the inductor L5. The other end of the output terminal of the switch element SWL5 is connected to a reference potential. The other end of the inductor L5 is electrically connected to the selection circuit 130 via the inductors L6 and L7. The switch element SWL5 is configured to electrically connect the inductor L5 and the selection circuit 130 when in a closed state. When the switch element SWL5 is in a closed state and the switch elements SWL6 to SWL8 are in an open state, the impedance of the inductance value switching circuit 110 becomes the sum of the inductances of the inductors L5 to L7.

[0065] An input terminal of the switch element SWL6 is electrically connected to an output terminal of the comparator CML6. One end of the output terminal of the switch element SWL6 is electrically connected to the other end of the inductor L5 and one end of the inductor L6. The other end of the output terminal of the switch element SWL6 is connected to a reference potential. The other end of the inductor L6 is electrically connected to the selection circuit 130 via the inductor L7. The switch element SWL6 is configured to electrically connect the inductor L6 and the selection circuit 130 when in a closed state. When the switch element SW6 is in a closed state and the switch elements SWL7 to SWL8 are in an open state, the impedance of the inductance value switching circuit 110 becomes the sum of the inductances of the inductors L6 and L7.

[0066] An input terminal of the switch element SWL7 is electrically connected to an output terminal of the comparator CML7. One end of the output terminal of the switch element SWL7 is connected to the other end of the inductor L6 and one end of the inductor L7. The other end of the output terminal of the switch element SWL7 is connected to a reference potential. The other end of the inductor L7 is electrically connected to the selection circuit 130. The switch element SWL7 is configured to electrically connect the inductor L7 and the selection circuit 130 when in a closed state. When the switch element SWL7 is in a closed state and the switch element SWL8 is in an open state, the impedance of the inductance value switching circuit 110 becomes the inductance of the inductor L7.

[0067] An input terminal of the switch element SWL8 is electrically connected to an output terminal of the comparator CML8. One end of the output terminal of the switch element SWL8 is electrically connected to the other end of the inductor L7 and the selection circuit 130. The other end of the output terminal of the switch element SWL8 is connected to a reference potential. The switch element SWL8 is configured to electrically connect the reference potential to the selection circuit 130 when in a closed state.

[0068] In the inductance value switching circuit 110, the inductors L1 to L7 are configured to be connected in series. That is, when each switch element is in a closed state, the sum of the inductors connected in series changes. As the input signal S11 changes from 0V to a high voltage, the switch elements SWL1 to SWL8 are opened in the order of the switch element SWL8 to the switch element SWL1. Since the inductance value switching circuit 110 includes a high resistance element RL that is a ground resistor with a relatively large resistance value (for example, 10 kilohms), the inductors subsequent to the switch element that is in a closed state can be ignored. That is, when the switch element SWL8 is in a closed state, the inductances of the inductors L1 to L7 can be ignored. The inductance value switching circuit 110 outputs an impedance state according to the open / close state of each switch element to the selection circuit 130 via the node NL.

[0069] [Capacitance value switching circuit] The configuration of the capacitance value switching circuit 120 will be described. The capacitance value switching circuit 120 includes a switch element SWC1, a switch element SWC2, a switch element SWC3, a switch element SWC4, a switch element SWC5, a switch element SWC6, a switch element SWC7, a switch element SWC8, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a capacitor C7, and a high resistance element RC. In the capacitance value switching circuit 120, nodes N25 to N32 and the selection circuit 130 are electrically connected.

[0070] An input terminal of the switch element SWC1 is electrically connected to an output terminal of the comparator CMC1. One end of the output terminal of the switch element SWC1 is electrically connected to a node N25. The node N25 is electrically connected to a reference potential via a high resistance element RC and to the selection circuit 130 via a node N26 and a node N32. The other end of the output terminal of the switch element SWC1 is connected to a reference potential via a capacitor C1. When the switch element SWC1 is in a closed state, the switch element SWC1 is configured to electrically connect the capacitor C1 and the selection circuit 130. When the switch element SWC1 is in an open state, the switch element SWC1 is configured to electrically separate the capacitor C1 and the selection circuit 130. That is, when the switch element SWC1 is in a closed state, the capacitance of the capacitor C1 is added to the impedance of the capacitance value switching circuit 120.

[0071] An input terminal of the switch element SWC2 is electrically connected to an output terminal of the comparator CMC2. One end of the output terminal of the switch element SWC2 is electrically connected to a node N26. The node N26 is electrically connected to the selection circuit 130 via a node N27 to a node N32. The other end of the output terminal of the switch element SWC2 is connected to a reference potential via a capacitor C2. When the switch element SWC2 is in a closed state, the switch element SWC2 is configured to electrically connect the capacitor C2 to the selection circuit 130. When the switch element SWC2 is in an open state, the switch element SWC2 is configured to electrically separate the capacitor C2 from the selection circuit 130. That is, when the switch element SWC2 is in a closed state, the capacitance of the capacitor C2 is added to the impedance of the capacitance value switching circuit 120.

[0072] An input terminal of the switch element SWC3 is electrically connected to an output terminal of the comparator CMC3. One end of the output terminal of the switch element SWC3 is electrically connected to a node N27. The node N27 is electrically connected to the selection circuit 130 via a node N28 and a node N32. The other end of the output terminal of the switch element SWC3 is connected to a reference potential via a capacitor C3. When the switch element SWC3 is in a closed state, the switch element SWC3 is configured to electrically connect the capacitor C3 and the selection circuit 130. When the switch element SWC3 is in an open state, the switch element SWC3 is configured to electrically separate the capacitor C3 and the selection circuit 130. That is, when the switch element SWC3 is in a closed state, the capacitance of the capacitor C3 is added to the impedance of the capacitance value switching circuit 120.

[0073] An input terminal of the switch element SWC4 is electrically connected to an output terminal of the comparator CMC4. One end of the output terminal of the switch element SWC4 is electrically connected to a node N28. The node N28 is electrically connected to the selection circuit 130 via a node N29 to a node N32. The other end of the output terminal of the switch element SWC4 is connected to a reference potential via a capacitor C4. When the switch element SWC4 is in a closed state, the switch element SWC4 is configured to electrically connect the capacitor C4 to the selection circuit 130. When the switch element SWC4 is in an open state, the switch element SWC4 is configured to electrically separate the capacitor C4 from the selection circuit 130. That is, when the switch element SWC4 is in a closed state, the capacitance of the capacitor C4 is added to the impedance of the capacitance value switching circuit 120.

[0074] An input terminal of the switch element SWC5 is electrically connected to an output terminal of the comparator CMC5. One end of the output terminal of the switch element SWC5 is electrically connected to a node N29. The node N29 is electrically connected to the selection circuit 130 via a node N30 and a node N32. The other end of the output terminal of the switch element SWC5 is connected to a reference potential via a capacitor C5. When the switch element SWC5 is in a closed state, the switch element SWC5 is configured to electrically connect the capacitor C5 and the selection circuit 130. When the switch element SWC5 is in an open state, the switch element SWC5 is configured to electrically separate the capacitor C5 and the selection circuit 130. That is, when the switch element SWC5 is in a closed state, the capacitance of the capacitor C5 is added to the impedance of the capacitance value switching circuit 120.

[0075] An input terminal of the switch element SWC6 is electrically connected to an output terminal of the comparator CMC6. One end of the output terminal of the switch element SWC6 is electrically connected to a node N30. The node N30 is electrically connected to the selection circuit 130 via nodes N31 and N32. The other end of the output terminal of the switch element SWC6 is connected to a reference potential via a capacitor C6. When the switch element SWC6 is in a closed state, the switch element SWC6 is configured to electrically connect the capacitor C6 to the selection circuit 130. When the switch element SWC6 is in an open state, the switch element SWC6 is configured to electrically separate the capacitor C6 from the selection circuit 130. That is, when the switch element SWC6 is in a closed state, the capacitance of the capacitor C6 is added to the impedance of the capacitance value switching circuit 120.

[0076] An input terminal of the switch element SWC7 is electrically connected to an output terminal of the comparator CMC7. One end of the output terminal of the switch element SWC7 is electrically connected to a node N31. The node N31 is electrically connected to the selection circuit 130 via a node N32. The other end of the output terminal of the switch element SWC7 is connected to a reference potential via a capacitor C7. When the switch element SWC7 is in a closed state, the switch element SWC7 is configured to electrically connect the capacitor C7 and the selection circuit 130. When the switch element SWC7 is in an open state, the switch element SWC7 is configured to electrically separate the capacitor C7 and the selection circuit 130. That is, when the switch element SWC7 is in a closed state, the capacitance of the capacitor C7 is added to the impedance of the capacitance value switching circuit 120.

[0077] An input terminal of the switch element SWC8 is electrically connected to an output terminal of the comparator CMC8. One end of the output terminal of the switch element SWC8 is electrically connected to a node N32. The node N32 is electrically connected to the selection circuit 130. The other end of the output terminal of the switch element SWC8 is connected to a reference potential. The switch element SWC8 is configured to electrically connect the reference potential to the selection circuit 130 when in a closed state. The switch element SWC8 is configured to electrically isolate the switch element SWC8 from the selection circuit 130 when in an open state.

[0078] In the capacitance value switching circuit 120, the capacitors C1 to C7 are electrically connected to the switch elements SWC1 to SWC7, respectively, so that the sum of the capacitances changes when each switch element is in a closed state. As the input signal S11 changes from 0V to a high voltage, the switch elements SWC1 to SWC8 are closed in this order, starting from the switch element SWC1 to the switch element SWC8. Since the capacitance value switching circuit 120 includes a high resistance element RC that is a ground resistor with a relatively large resistance value (for example, 10 kilohms), when all the switch elements are in an open state, the circuit is open. When the switch element SWC8 is in a closed state, the capacitances of the capacitors C1 to C7 can be ignored. The capacitance value switching circuit 120 outputs an impedance state according to the open / closed state of each switch element to the selection circuit 130 via the connection of the node NC.

[0079] In the transmission circuit 28, the switching elements SWL1 to SWL8 of the inductance value switching circuit 110 or the switching elements SWC1 to SWC8 of the capacitance value switching circuit 120 can be controlled to open or close according to the output results of the comparators connected to each of them.

[0080] [Transmission circuit operation] The operation of the transmission circuit according to the first embodiment will be described with reference to Fig. 7. Fig. 7 is a diagram for explaining the operation of the transmission circuit according to the first embodiment.

[0081] Fig. 7 shows the position of the reflection coefficient Γ due to the impedance of the transmission circuit 28 according to the embodiment in polar coordinates (polar chart). Points P1 to P16 in the polar coordinates are shown in Fig. 7. The control circuit 27 is configured to position the impedance of the transmission circuit 28 at any phase between points P1 to P16 by controlling the switch elements SWL1 to SWL8 and the switch elements SWC1 to SWC8.

[0082] In FIG. 7, the phase of point P1 is 0°. The phase of point P2 is 22.5°. The phase of point P3 is 45°. The phase of point P4 is 67.5°. The phase of point P5 is 90°. The phase of point P6 is 112.5°. The phase of point P7 is 135°. The phase of point P8 is 157.5°. The phase of point P9 is 180°. The phase of point P10 is 202.5°. The phase of point P11 is 225°. The phase of point P12 is 247.5°. The phase of point P13 is 270°. The phase of point P14 is 292.5°. The phase of point P15 is 315°. The phase of point P16 is 337.5°.

[0083] Point P1 indicates the impedance when switch elements SWL1 to SWL8 are open and switch elements SWC1 to SWC8 are open. In this case, the impedance of the transmission circuit 28 is, in principle, infinite. Point P9 indicates the impedance when all switch elements SWL1 to SWL8 and SWC1 to SWC8 are closed. In this case, the impedance of the transmission circuit 28 is, in principle, zero.

[0084] In FIG. 7, solid arrows V1 and V2 indicate the direction of rotation of the impedance when the input signal S11 is a rising sawtooth wave. As indicated by the arrows V1 and V2, the direction of rotation of the impedance when the input signal S11 is a rising sawtooth wave is clockwise. Dotted arrows V3 and V4 indicate the direction of rotation of the impedance when the input signal S11 is a falling sawtooth wave. As indicated by the arrows V3 and V4, the direction of rotation of the impedance when the input signal S11 is a falling sawtooth wave is counterclockwise. In other words, the direction of rotation of the impedance is opposite when the input signal S11 is a rising sawtooth wave and when it is a falling sawtooth wave.

[0085] 7, the upper semicircular region indicates the operating region of the inductance value switching circuit 110, and the lower semicircular region indicates the operating region of the capacitance value switching circuit 120. In this embodiment, the operations of the inductance value switching circuit 110 and the capacitance value switching circuit 120 are switched in response to a change in the voltage value of the input signal S11.

[0086] (Rising sawtooth wave) The operation of the transmission circuit 28 will be described when the input signal S11 is a rising sawtooth wave. The rising sawtooth wave is a signal in which the input voltage rises from 0 [V] to a high voltage of X [V].

[0087] First, when the voltage value of the input signal S11 rises from 0V to X / 2[V], the capacitance value switching circuit 120 is operated to rotate the impedance. Specifically, the drive control circuit 29 sequentially switches the switch elements SWC1 to SWC8 from an open state to a closed state, thereby sequentially adding the capacitance values ​​of the capacitors C1 to C8 to the transmission circuit 28. At this time, the impedance of the node NC shifts clockwise along the arrow V1 on the outer periphery of the lower semicircle in FIG. 7 in the order of points P16, P15, P14, P13, P12, P11, P10, and P9.

[0088] Next, when the voltage value of the input signal S11 rises from X / 2 [V] to X [V], the inductance value switching circuit 110 is operated to rotate the impedance. Specifically, the drive control circuit 29 sequentially switches the switch elements SWL8 to SWL1 from the closed state to the open state, thereby sequentially adding the inductance values ​​of the inductors L7 to L1 to the transmission circuit. At this time, the impedance of the node NL shifts clockwise along the arrow V2 on the upper semicircle of FIG. 7 in the order of points P8, P7, P6, P5, P4, P3, P2, and P1.

[0089] (Downward sawtooth wave) The operation of the transmission circuit 28 will be described when the input signal S11 is a falling sawtooth wave. The falling sawtooth wave is a signal in which the high input voltage falls from X [V] to 0 [V].

[0090] First, when the voltage value of the input signal S11 falls from X [V] to X / 2 [V], the inductance value switching circuit 110 is operated to rotate the impedance. Specifically, the drive control circuit 29 sequentially switches the switch elements SWL1 to SWL7 from the open state to the closed state, thereby sequentially removing the inductance values ​​of the inductors L1 to L7 from the transmission circuit 28. At this time, the impedance of the node NL shifts counterclockwise along the outer periphery of the upper semicircle in FIG. 7, in the order of points P2, P3, P4, P5, P6, P7, P8, and P9, along the arrow V3.

[0091] Next, when the voltage value of the input signal S11 falls from X / 2 [V] to 0 [V], the capacitance value switching circuit 120 is operated to rotate the impedance. Specifically, the drive control circuit 29 sequentially switches the switch elements SWC8 to SWC1 from the closed state to the open state, thereby sequentially removing the capacitance values ​​of the capacitors C8 to C1 from the transmission circuit. At this time, the impedance of the node NC shifts counterclockwise along the arrow V4 on the lower semicircle of FIG. 7 in the order of points P10, P11, P12, P13, P14, P15, P16, and P1.

[0092] [Operation of the selection circuit] Referring again to FIG. 4, the operation of the selection circuit 130 will be described.

[0093] The selection circuit 130 executes an operation of switching the outputs of the inductance value switching circuit 110 and the capacitance value switching circuit 120 according to the voltage of the input signal S11. The selection circuit 130 can obtain an SSB signal by switching the outputs of the capacitance value switching circuit 120 and the inductance value switching circuit 110 according to the voltage of the input signal S11 between when the voltage value of the input signal S11 is 0 [V] to X / 2 [V] and when it is X / 2 [V] to X [V]. Specifically, the selection circuit 130 obtains an LSB signal when the input signal S11 is a rising sawtooth wave, and obtains a USB signal when the input signal S11 is a falling sawtooth wave. That is, in this embodiment, it is possible to switch between the LSB signal and the USB signal by inverting the sawtooth wave. The selection circuit 130 outputs the obtained signal as the output signal S12 to the high-frequency switch 21 shown in FIG. 1.

[0094] [Backscatter signal] An example of a backscattering signal according to the first embodiment will be described with reference to Fig. 8 and Fig. 9. Fig. 8 and Fig. 9 are diagrams showing an example of a spectrum waveform of a backscattering signal according to the first embodiment. In Fig. 8 and Fig. 9, the horizontal axis indicates frequency (GHz (gigahertz)) and the vertical axis indicates signal level (V).

[0095] FIG. 8 shows a spectrum waveform W11. The spectrum waveform W11 is a spectrum waveform when the input signal S11 is a rising sawtooth wave as shown in FIG. 5. The spectrum waveform W11 includes a carrier signal RF1, a USB signal US1, and an LSB signal LS1. The frequency of the carrier signal RF1 is 1.00 [GHz]. The frequency of the LSB signal LS1 is 0.99 [GHz]. The frequency of the USB signal US1 is 1.01 [GHz]. As shown in FIG. 8, the USB signal US1 is suppressed compared to the LSB signal LS1. That is, in the spectrum waveform W11 shown in FIG. 8, the SSB of the LSB signal LS1 is realized.

[0096] FIG. 9 shows a spectrum waveform W12. The spectrum waveform W12 is a spectrum waveform when the input signal S11 is a falling sawtooth wave as shown in FIG. 6. The spectrum waveform W12 includes a carrier signal RF2, a USB signal US2, and an LSB signal LS2. The frequency of the carrier signal RF2 is 1.00 [GHz]. The frequency of the LSB signal LS2 is 0.99 [GHz]. The frequency of the USB signal US2 is 1.01 [GHz]. As shown in FIG. 9, the LSB signal LS2 is suppressed compared to the USB signal US2. That is, in the spectrum waveform W12 shown in FIG. 9, the SSB of the USB signal US2 is realized.

[0097] [Second embodiment] Next, a second embodiment of the present disclosure will be described.

[0098] [Impedance control method] A method for controlling the impedance of the transmission circuit according to the second embodiment will be described with reference to Fig. 10. Fig. 10 is a diagram for explaining a method for controlling the impedance of the transmission circuit according to the second embodiment. The control circuit 27 receives an input signal corresponding to transmission data to be transmitted to an external device. The control circuit 27 outputs a control signal for controlling the impedance of the transmission circuit 28 in response to the control signal.

[0099] Fig. 10 shows the configuration of a drive control circuit 29A corresponding to the output section of the control circuit 27 in Fig. 1, and a transmission circuit 28A. The drive control circuit 29A is a drive control circuit for the transmission circuit 28A that switches impedance and controls the reflection coefficient Γ to rotate on the complex plane. The drive control circuit 29A and the transmission circuit 28A may also be referred to as a synthesis circuit.

[0100] As shown in Fig. 10, the drive control circuit 29A includes a reference power supply V, resistor elements R1 to Rn+1 (n is a natural number), and comparators CMC1 to CMCn. The drive control circuit 29A differs from the drive control circuit 29 shown in Fig. 4 in that it does not include a comparator CML. The configuration of the drive control circuit 29A is the same as that of the drive control circuit 29 shown in Fig. 4 except that it does not include the comparator CML, so a description thereof will be omitted.

[0101] The transmission circuit 28A includes a capacitance value switching circuit 120A. The transmission circuit 28A differs from the transmission circuit 28 shown in FIG.

[0102] [Resonant circuit] The configuration of the capacitance value switching circuit 120A will be described. The capacitance value switching circuit 120A includes switching elements SWC1 to SWCn and a high resistance element RC. In the capacitance value switching circuit 120A, nodes N1A to NnA and one end of an inductor Lr are electrically connected. That is, the capacitance value switching circuit 120A and the inductor Lr form a resonant circuit. An output signal S13 is output from the other end of the inductor Lr to the high frequency switch 21 shown in FIG. 1.

[0103] The inductor Lr is an inductor provided between the transmission circuit 28A and the high-frequency switch 21 shown in Fig. 1. That is, the inductor Lr may be provided outside the transmission circuit 28A. Since the number of inductors used is reduced, the transmission circuit 28A has a configuration that is advantageous for integration into an integrated circuit, for example, compared to the transmission circuit 28 shown in Fig. 4.

[0104] The drive control circuit 29A can selectively control the impedance of the transmission circuit 28A. The drive control circuit 29A can switch the resonance frequency between the transmission circuit 28A and the inductor Lr by selectively connecting a plurality of capacitors included in the transmission circuit 28A to the inductor Lr. The drive control circuit 29A is configured to be able to control the impedance to rotate discretely by switching the resonance frequency between the transmission circuit 28A and the inductor Lr.

[0105] 10, the transmission circuit 28A is described as including a plurality of capacitors, but the present disclosure is not limited thereto. The transmission circuit 28A may include a plurality of inductors, for example. In this case, the transmission circuit 28A may be configured to be connected with a capacitor instead of the inductor Lr.

[0106] [Transmission circuit operation] The operation of the transmission circuit according to the second embodiment will be described with reference to Fig. 11. Fig. 11 is a diagram for explaining the operation of the transmission circuit according to the second embodiment.

[0107] Fig. 11 shows the positions on a polar coordinate system (polar chart) of the reflection coefficient Γ due to the impedance of the transmission circuit 28A according to the second embodiment. Fig. 11 shows points P1 to P16 on the polar coordinate system.

[0108] (Rising sawtooth wave) The operation of the transmission circuit 28A when the input signal S11 is a rising sawtooth wave will be described.

[0109] First, when the voltage value of the input signal S11 rises from 0 [V] to X / 2 [V], the drive control circuit 29A controls the switch elements SWC1 to SWC8 (n=16 since there are 16 points) so as to sequentially add the capacitance values ​​of the multiple capacitors included in the transmission circuit 28A to the transmission circuit 28A. At this time, the impedance shifts clockwise along the arrow V11 on the outer periphery of the upper semicircle in FIG. 11 in the order of points P1, P16, P15, P14, P13, P12, P11, and P9.

[0110] Next, when the voltage value of the input signal S11 rises from X / 2 [V] to X [V], the drive control circuit 29A controls the switch elements SWC9 to SWC16 to further add the capacitance values ​​of the multiple capacitors added to the transmission circuit 28A. At this time, the impedance shifts clockwise along the arrow V12 on the upper semicircle in FIG. 11 in the order of points P8, P7, P6, P5, P4, P3, P2, and P1.

[0111] (Downward sawtooth wave) The operation of the transmission circuit 28A will be described when the input signal S11 is a falling sawtooth wave. The rising sawtooth wave is a signal in which the high input voltage falls from X [V] to 0 [V].

[0112] First, when the voltage value of the input signal S11 falls from X [V] to X / 2 [V], the drive control circuit 29A controls the switch elements SWC16 to SWC9 to sequentially remove the capacitance values ​​of the multiple capacitors added to the transmission circuit 28A. At this time, the impedance shifts counterclockwise along the arrow V13 on the upper semicircle in FIG. 11 in the order of points P2, P3, P4, P5, P6, P7, P8, and P9.

[0113] Next, when the voltage value of the input signal S11 falls from X / 2 [V] to 0 [V], the drive control circuit 29A controls the switch elements SWC8 to SWC1 so as to sequentially remove the capacitance values ​​of the multiple capacitors included in the transmission circuit 28A from the transmission circuit 28A. At this time, the impedance shifts counterclockwise along the arrow V14 on the outer periphery of the lower semicircle in FIG. 11 in the order of points P10, P11, P12, P13, P14, P15, P16, and P1.

[0114] [Backscatter signal] An example of a backscattering signal according to the second embodiment will be described with reference to Fig. 12 and Fig. 13. Fig. 12 and Fig. 13 are diagrams showing an example of a spectrum waveform of a backscattering signal according to the second embodiment. In Fig. 12 and Fig. 13, the horizontal axis indicates frequency (GHz) and the vertical axis indicates signal level (V).

[0115] FIG. 12 shows a spectrum waveform W13. The spectrum waveform W13 is a spectrum waveform when the input signal S11 is a rising sawtooth wave as shown in FIG. 5. The spectrum waveform W13 includes a carrier signal RF3, a USB signal US3, and an LSB signal LS3. The frequency of the carrier signal RF3 is 1.00 [GHz]. The frequency of the LSB signal LS3 is 0.99 [GHz]. The frequency of the USB signal US3 is 1.01 [GHz]. As shown in FIG. 12, the USB signal US3 is suppressed compared to the LSB signal LS3. That is, in the spectrum waveform W13 shown in FIG. 12, the SSB of the LSB signal LS3 is realized.

[0116] FIG. 13 shows a spectrum waveform W14. The spectrum waveform W14 is a spectrum waveform when the input signal S11 is a falling sawtooth wave as shown in FIG. 6. The spectrum waveform W14 includes a carrier signal RF4, a USB signal US4, and an LSB signal LS4. The frequency of the carrier signal RF4 is 1.00 [GHz]. The frequency of the LSB signal LS4 is 0.99 [GHz]. The frequency of the USB signal US4 is 1.01 [GHz]. As shown in FIG. 13, the LSB signal LS4 is suppressed compared to the USB signal US4. That is, in the spectrum waveform W14 shown in FIG. 13, the SSB of the USB signal US4 is realized.

[0117] Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the contents of these embodiments. The above-mentioned components include those that a person skilled in the art can easily imagine, those that are substantially the same, and those that are within the so-called equivalent range. Furthermore, the above-mentioned components can be appropriately combined. Furthermore, various omissions, substitutions, or modifications of the components can be made without departing from the gist of the above-mentioned embodiments. [Explanation of symbols]

[0118] 1. Wireless communication devices 10 Antennas 11 BPF 20 RFBS Devices 21 High Frequency Switch 22 Amplifier 23 Demodulation section 24 Oscillator 25,26 LPF 27 Control circuit 28 Transmission Circuit 29 Drive control circuit 30 Control device 40 Sensors 110 Inductance value switching circuit 120 Capacitance value switching circuit SWL1 to SWL8, SWC1 to SWC8 switch elements CML1 to CML8, CMC1 to CMC8 Comparators

Claims

1. A synthesis circuit including a transmission circuit configured to be connected to an antenna and a control circuit configured to control an impedance of the transmission circuit, The transmission circuit includes: an inductance value switching circuit including a plurality of inductors; a plurality of first switch elements connected to the plurality of inductors, respectively; A capacitance value switching circuit including a plurality of capacitors; a plurality of second switch elements connected to each of the plurality of capacitors; The control circuit includes: a plurality of first comparators connected to each of the first switch elements; a plurality of second comparators connected to each of the second switch elements; a voltage dividing circuit including a plurality of resistor elements configured to divide a reference voltage and output a divided voltage to each of the plurality of first comparators and the plurality of second comparators; the first comparator is configured to compare the divided voltage with an input voltage having a sawtooth waveform, and control the first switch element to a closed state when the input voltage having the sawtooth waveform is lower than the divided voltage; the second comparator is configured to compare the divided voltage with the input voltage of the sawtooth waveform, and control the second switch element to a closed state when the input voltage of the sawtooth waveform is higher than the divided voltage. Synthetic circuit.

2. 2. The synthesis circuit according to claim 1, a combining circuit, the voltage dividing circuit being configured to be controllable by changing the impedance of the transmission circuit so that a reflection coefficient with the antenna rotates around a reference point on a complex plane.

3. 3. The synthesis circuit according to claim 2, A synthesis circuit configured to, when the sawtooth waveform input voltage is a rising signal, control the capacitance value switching circuit to rotate the lower semicircle of the reference point in a clockwise direction, and to control the inductance value switching circuit to rotate the upper semicircle of the reference point in a clockwise direction.

4. 3. The synthesis circuit according to claim 2, A synthesis circuit configured to, when the sawtooth waveform input voltage is a falling signal, control the inductance value switching circuit to rotate the upper semicircle of the reference point counterclockwise, and control the capacitance value switching circuit to rotate the lower semicircle of the reference point counterclockwise.

5. 5. The synthesis circuit according to claim 1, a combining circuit including a selection circuit configured to switch outputs of the inductance value switching circuit and the capacitance value switching circuit according to a voltage value of the sawtooth waveform input voltage and output the selected output to the antenna.

6. 5. The synthesis circuit according to claim 1, The voltage divider circuit is configured to output divided voltages having different voltage values ​​to each of the plurality of first comparators and the plurality of second comparators.

7. A synthesis circuit including a transmission circuit configured to be connected to an antenna and a control circuit configured to control an impedance of the transmission circuit, The transmission circuit includes: A capacitance value switching circuit including a plurality of capacitors; a plurality of switch elements connected to each of the plurality of capacitors; The control circuit includes: a plurality of comparators connected to each of the switch elements; a voltage dividing circuit including a plurality of resistor elements configured to divide a reference voltage and output a divided voltage to each of the plurality of comparators; An inductor is connected between the output terminal of the transmission circuit and the antenna. Synthetic circuit.

8. A synthesis circuit including a transmission circuit configured to be connected to an antenna and a control circuit configured to control an impedance of the transmission circuit, The transmission circuit includes: an inductance value switching circuit including a plurality of inductors; a plurality of switch elements connected to the plurality of inductors, The control circuit includes: a plurality of comparators connected to each of the switch elements; a voltage dividing circuit including a plurality of resistor elements configured to divide a reference voltage and output a divided voltage to each of the plurality of comparators; A capacitor is connected between the output terminal of the transmission circuit and the antenna. Synthetic circuit.

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