Interconnection between a quantum computing module and a non-quantum processing module in a quantum computing system

Abstract

The technology disclosed in this patent document can be implemented to combine quantum computing, classical qubit control / readout, and classical digital computing in a scalable computing system based on superconducting qubits and a specialized interconnect design for connecting hardware components in a multi-stage cryogenic system to provide high-speed communication between quantum computing modules and their controllers while allowing efficient management of wiring with other modules.

Description

Technical Field

[0001] Priority Claim and Related Applications This patent document claims the priority and benefit of U.S. Provisional Patent Application No. 63 / 091,455 (Attorney Docket No. 133858-8002.US00), filed on October 14, 2020, by applicant SeeQC, Inc., entitled "INTERCONNECTION BETWEEN QUANTUM COMPUTING MODULE AND NONQUANTUM PROCESSING MODULES IN QUANTUM COMPUTING SYSTEMS", the entire disclosure of which is incorporated herein by reference as part of this patent document.

[0002] This patent document relates to a computing or information processing system that includes a quantum computing module that performs information processing or computing using the quantum states of quantum mechanical devices or circuits.

Background Art

[0003] Classical digital computers, including general-purpose digital computers and high-performance digital supercomputers, perform operations based on Boolean logic. Computing technologies based on Boolean logic have revolutionized a wide range of industries and technologies over the past few decades, but they also have limitations when dealing with very complex problems, such as molecular modeling of the structures and properties of chemical compounds or biological structures, cryptography, or modeling of complex systems for weather forecasting, climate change, etc., which involve a large number of operations. Various new computing techniques have been investigated to complement or replace Boolean logic-based digital computing.

[0004] Quantum mechanical systems can be used to build new computing systems for complex information processing. A quantum system suitable for quantum computing has an ensemble of subsystems that exhibit different quantum states that are correlated or "entangled" with each other due to quantum coherence, including long-range quantum coherence. In various implementations for quantum computers, each subsystem within the ensemble of subsystems can be a quantum system that exhibits two or more different quantum states in order to operate as a basic quantum device, and information can be represented, stored, processed, and transmitted by the superposition and correlation of the quantum states of different basic quantum devices. One example of such a basic quantum device is a two-state device known as a quantum bit ("qubit"). Some examples of qubit implementations include superconducting qubits based on superconducting Josephson junctions developed at IBM, Google, Intel, and others, ion trap devices based on electromagnetic trapping fields by laser beams developed at Honeywell and IonQ, semiconductor-based quantum dots, and other devices capable of quantum computing operations. SUMMARY OF THE INVENTION MEANS FOR SOLVING THE PROBLEM

[0005] The technology disclosed in this patent document is based on superconducting qubits using Josephson junctions, which exhibit low dissipation and long coherence times and can be processed using well-developed integrated circuit processing techniques. It can be implemented to combine quantum computing and classical digital computing within a scalable computing system. Quantum computers based on superconducting qubits are complex due to various requirements for providing and maintaining superconducting qubit devices or systems, require complex and bulky cryogenic systems, and it is well-known that special superconducting materials are used. In view of their technical complexity and challenges for scalable commercial applications, the disclosed technology strategically partitions and combines the hardware for quantum computing and the hardware for classical digital computing, and provides a hybrid quantum-classical computing architecture and configuration in which such hardware components are installed in a certain way within a multi-stage cryogenic system, producing a scalable hybrid quantum-classical computing system for commercial use. The disclosed technology can be implemented by using a special interconnect design for connecting hardware components within a multi-stage cryogenic system.

[0006] On one side, the disclosed technology can be implemented to provide a system that can perform information processing, at least in part, based on quantum computing using the quantum states of qubits. The system includes a cryostat system structured to include different cryogenic stages operable to provide a lower cryogenic temperature and a higher cryogenic temperature, and a quantum computing module surrounded by the cryostat system at the lower cryogenic temperature and comprising a first integrated chip structured to support a plurality of qubit circuits. Each qubit circuit is structured as a superconducting circuit at the lower cryogenic temperature to exhibit different quantum states as a quantum mechanical system and interact quantum mechanically with other qubit circuits via quantum entanglement to cause a superposition or correlation of different quantum states of the qubit circuits. The system further includes a qubit management circuit module surrounded by the cryostat system, positioned adjacent to the quantum computing module, and coupled to be maintained at the cryogenic temperature. The qubit control circuits, each supported by a second integrated chip, are structured to direct control signals for controlling the qubit circuits to the qubit circuits, respectively. The qubit readout circuits, each supported by the second integrated chip, are structured to output readout signals from the qubit circuits, respectively. The readout signals represent the quantum states of the qubit circuits, respectively. The qubit control circuits and the qubit readout circuits include superconducting circuits at the lower cryogenic temperature and are structured to operate using the control signals and the readout signals in a non-quantum classical manner based on digital processing. The second integrated chip is engaged with the first integrated chip to form a multi-chip module and includes the qubit management circuit module that transfers the control signals and the readout signals therebetween.The system further includes a circuit module that is surrounded by a cryostat system at a higher cryogenic temperature and structured to communicate with a qubit management circuit module in relation to control signals and readout signals, conductive bumps formed to engage the first and second integrated chips with each other, and conductive wires coupled between the qubit management circuit module and at least one of the circuit modules placed at a higher temperature stage of the cryostat system to provide communication therebetween and transfer signals.

[0007] In another aspect, the disclosed technology can be implemented to provide a method for processing information processing based at least in part on quantum computing that uses the quantum states of qubits. The method includes operating a quantum computing module comprising a plurality of qubit circuits that are operable as a quantum mechanical system to exhibit different quantum states, cause quantum mechanical interactions between qubit circuits, and cause superposition or correlation of different quantum states of the qubit circuits; directing control signals for controlling the qubit circuits to the qubit circuits, respectively, by a qubit control circuit; operating a qubit readout circuit to output a readout signal from each qubit circuit, the readout signal representing the quantum state of each qubit circuit; thermally coupling the qubit circuits, the qubit control circuit, and the qubit readout circuit to a common cryogenic stage; coupling the qubit circuits, the qubit control circuit, and the qubit readout circuit to each other via capacitive coupling or inductive coupling to apply the control signal from the qubit control circuit to the qubit circuit, respectively; and transmitting information using conductive wires coupled between the qubit management circuit module and one or more circuit modules at a temperature one degree or more above the temperature of the common cryogenic stage associated with operating the qubit circuits, the qubit control circuit, and the qubit readout circuit.

[0008] In yet another aspect, the disclosed technology can be implemented to provide a system capable of information processing, at least in part, based on quantum computing using the quantum states of qubits. The system includes a cryostat system structured to include different cryogenic stages operable to provide a lower cryogenic temperature and a higher cryogenic temperature, and a quantum computing module surrounded by the cryostat system at the lower cryogenic temperature. The quantum computing module comprises a first integrated chip structured to support a plurality of qubit circuits, each qubit circuit being structured as a superconducting circuit at the lower cryogenic temperature to exhibit different quantum states as qubits, interact quantum mechanically with other qubit circuits, and cause correlations (superposition or entanglement) of different quantum states and parts of the qubit circuits. The system further includes a qubit management circuit module surrounded by the cryostat system, positioned adjacent to the quantum computing module, and coupled thereto to be maintained at the same lower cryogenic temperature as the quantum computing module. The qubit management circuit module includes a qubit control circuit structured to include a second integrated chip and support, respectively, directing control signals for controlling the qubit circuits to the qubit circuits, and a qubit readout circuit structured to include a second integrated chip and support, respectively, outputting readout signals from the qubit circuits. The readout signals represent the quantum states of the qubit circuits, respectively, and the qubit control circuit and the qubit readout circuit include superconducting circuits at the lower cryogenic temperature and are structured to operate using the control signals and the readout signals in a non-quantum classical manner based on digital processing. The second integrated chip is engaged with the first integrated chip to form a multi-chip module therebetween for transferring the control signals and the readout signals.The system further includes a circuit module structured to communicate with a qubit management circuit module in relation to control signals and readout signals, surrounded by a cryostat system at a higher cryogenic temperature, and a conductive bump formed to connect with a first and a second integrated chip, at least a part of which forms a conductive path between the qubit management circuit module and a quantum computing module to transfer a part of the control signals and readout signals without using other wirings between the qubit management circuit module and the quantum computing module, and a conductive wire coupled between the qubit management circuit module and at least one of the circuit modules to provide communication and transfer signals therebetween.

[0009] This aspect and other aspects, and their implementations, are described in more detail in the drawings, the description, and the claims. The present invention provides, for example, the following. (Item 1) A system capable of information processing based at least in part on quantum computing using the quantum states of qubits, A cryostat system structured to include different cryogenic stages operable to provide a low cryogenic temperature and a higher cryogenic temperature, At the low cryogenic temperature, a quantum computing module surrounded by the cryostat system, the quantum computing module comprising a first integrated chip structured to support a plurality of qubit circuits, each qubit circuit being a quantum mechanical system that exhibits different quantum states and interacts quantum mechanically with other qubit circuits via quantum entanglement to cause a superposition or correlation of different quantum states of the qubit circuits, and being structured as a superconducting circuit at the low cryogenic temperature, a quantum computing module, A qubit management circuit module, the qubit management circuit module being surrounded by the cryostat system, located adjacent to the quantum computing module, coupled to be maintained at a cryogenic temperature, the qubit control circuit being supported by a second integrated chip and each being structured to direct a control signal for controlling the qubit circuit to the qubit circuit, the qubit readout circuit being supported by the second integrated chip and each being structured to output a readout signal from the qubit circuit, the readout signal representing the quantum state of the qubit circuit respectively, the qubit control circuit and the qubit readout circuit including superconducting circuits at the low cryogenic temperature and being structured to be operable to operate using the control signal and the readout signal in a non-quantum classical manner based on digital processing, the second integrated chip being engaged with the first integrated chip to form a multi-chip module and transferring control signals and readout signals therebetween, a qubit management circuit module, A circuit module, wherein the circuit module is surrounded by the cryostat system at the higher cryogenic temperature and is structured to communicate with the qubit management circuit module in relation to the control signal and the readout signal. Conductive bumps formed to engage the first and second integrated chips with each other. A conductive wire, wherein the conductive wire is coupled between the qubit management circuit module and at least one of the circuit modules placed at a higher temperature stage of the cryostat system, provides communication therebetween, and transfers signals. A system comprising the above. (Item 2) The conductive bump is for providing mechanical engagement between the first integrated chip and the second integrated chip, and is not electrically connected to a circuit in either the first integrated chip or the second integrated chip. The quantum computing module and the qubit management circuit module are coupled to each other and exchange information via a conductive coupling or an inductive coupling. The system according to Item 1. (Item 3) The system according to Item 1, wherein the conductive bump is connected so as to at least partially form a conductive path between the qubit management circuit module and the quantum computing module for transfer of a part of the control signal and the readout signal without using other wiring between the qubit management circuit module and the quantum computing module. (Item 4) The system according to Item 1, wherein the conductive bump includes a conductive insulating bump that forms an insulating fence separating the conductive wires and is positioned to reduce crosstalk between the conductive wires. (Item 5) The system according to Item 1, wherein the quantum computing module includes a conductive insulating bump that forms an insulating fence separating the qubit circuits, is positioned to reduce crosstalk therebetween, and reduces decoherence of the qubit circuits. (Item 6) The system according to Item 1, further comprising a conductive insulating wall that forms an insulating wall separating the conductive wires and is positioned to reduce crosstalk between the conductive wires. (Item 7) The quantum computing module of claim 1, comprising a conductive insulating wall that separates the quantum bit circuits, reduces crosstalk therebetween, and reduces decoherence of the quantum bit circuits. (Item 8) The quantum bit management circuit module and the quantum computing module of claim 1, comprising a capacitive coupling circuit network, structured to enable capacitive coupling between the quantum bit management circuit module and the quantum computing module and provide a separate signal transmission from the conductive path formed by the conductive bumps. (Item 9) The quantum bit management circuit module and the quantum computing module of claim 1, comprising a magnetic coupling circuit network, structured to enable magnetic inductive coupling between the quantum bit management circuit module and the quantum computing module and provide a separate signal transmission from the conductive path formed by the conductive bumps. (Item 10) The system of claim 1, further comprising a flexible non-conductive material on which the conductive wires are formed and separated from each other, thereby forming a flexible ribbon that connects at least one of the circuit module and the quantum bit management circuit module. (Item 11) The system of claim 1, wherein each quantum bit circuit includes a superconducting Josephson junction circuit at the low cryogenic temperature. (Item 12) The system of claim 1, wherein the quantum bit management circuit module includes a superconducting switching circuit different from the Josephson junction circuit. (Item 13) The system of claim 1, wherein the quantum bit management circuit module includes a Josephson junction circuit. (Item 14) The system of claim 1, wherein the quantum bit management circuit module includes a single flux quantum (SFQ) logic circuit. (Item 15) The system of claim 1, wherein the quantum bit management circuit module includes a quantum flux parametron circuit. (Item 16) The system of claim 1, wherein the quantum bit management circuit module includes a nanowire switch. (Item 17) The system of claim 1, wherein the quantum bit management circuit module includes a superconducting ferromagnetic transistor. (Item 18) The system of claim 1, wherein the quantum bit management circuit module includes a superconducting spintronics device. (Item 19) The quantum bit management circuit module includes a field effect superconducting device, and the system according to Item 1. (Item 20) The system according to Item 1, further comprising an optical transmitter and a receiver device to enable transmission and reception of optical signals between the cryogenic stage placed at the highest temperature of the cryostat system and room temperature electronic devices and to provide communication therebetween. (Item 21) The system according to Item 1, wherein the quantum bit management circuit module and the quantum computing module are maintained at the same low cryogenic temperature. (Item 22) The quantum computing module further includes a plurality of readout resonators, the plurality of readout resonators are supported by the first integrated chip, and are respectively structured to interact with the plurality of quantum bit circuits and produce quantum bit circuit readout signals. The quantum bit readout circuit is supported by the second integrated chip, and is respectively structured to interact with the plurality of readout resonators supported by the first integrated chip, receive the quantum bit circuit readout signals respectively, and output the readout signals respectively. The system according to Item 1. (Item 23) The quantum bit readout circuit supported by the second integrated chip is structured to include a plurality of readout resonators supported by the second integrated chip, and is respectively structured to interact with the plurality of quantum bit circuits supported by the first integrated chip and produce quantum bit circuit readout signals. The quantum bit readout circuit supported by the second integrated chip is respectively structured to interact with the plurality of readout resonators, receive the quantum bit circuit readout signals respectively, and output the readout signals respectively. The system according to Item 1. (Item 24) A method for processing information based at least in part on quantum computing using the quantum state of a quantum bit, comprising: operating a quantum computing module comprising a plurality of quantum bit circuits that can operate as a quantum mechanical system to exhibit different quantum states, cause quantum mechanical interactions between the quantum bit circuits, and cause superposition or correlation of different quantum states of the quantum bit circuits. Directing control signals for controlling the quantum bit circuit to the quantum bit control circuit, respectively, Operating a quantum bit readout circuit to output readout signals from the quantum bit circuit, respectively, where the readout signals represent the quantum states of the quantum bit circuit, respectively, Thermally coupling the quantum bit circuit, the quantum bit control circuit, and the quantum bit readout circuit to a common cryogenic stage, Coupling the quantum bit circuit, the quantum bit control circuit, and the quantum bit readout circuit via capacitive coupling or inductive coupling, and applying the control signals from the quantum bit control circuit to the quantum bit circuit, respectively, Using a conductive wire coupled between a quantum bit management circuit module and one or more circuit modules at a temperature one degree or more higher than the temperature of the common cryogenic stage coupled to the quantum bit circuit, the quantum bit control circuit, and the quantum bit readout circuit, in relation to operating the quantum bit circuit, the quantum bit control circuit, and the quantum bit readout circuit, to transmit information A method comprising the above. (Item 25) The method according to item 24, including one or more operating steps when operating a system as listed in one of items 1 - 23.

Brief Description of the Drawings

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DETAILED DESCRIPTION OF THE INVENTION

[0020] The technology disclosed herein for a computing or information processing system with a superconducting-based quantum computing module (e.g., a superconducting Josephson junction) enables the system to be scalable for complex computing applications by combining a quantum computing module or device and a classical digital computing module or device, and at various cryogenic stages at different cryogenic temperatures, strategically partitioning such a system into different quantum and classical digital computing modules, devices, or components, and achieving superconducting conditions at those cryogenic stages. Such an implementation of the disclosed technology simplifies and reduces the complex and bulky cryogenic systems commonly used within various quantum computer systems that use superconducting quantum computing devices, and can be used to reduce the use or the level of use of complex superconducting cable systems for connecting different computing or processing modules. The implementation of the disclosed technology can be devised to enable commercially scalable processing using integrated circuit (IC) processing processes and equipment when manufacturing important modules or devices for quantum computer systems based on superconducting Josephson junctions. The technology disclosed in this patent document can be implemented to provide a special interconnection design for connecting hardware components within a multi-stage cryogenic system while enabling efficient management of wiring with other modules, and to provide high-speed communication between a quantum computing module and its controller.

[0021] Figures 1A, 1B, 1C, 1D, and 1E show examples for implementing a quantum computing system based on the disclosed technology and an interconnection design for connecting different hardware modules within a multi-stage cryogenic system.

[0022] FIG. 1A shows an example of a quantum computing system 110 for producing a scalable hybrid quantum-classical computing system for commercial use. As the name implies, the quantum computing system 110 includes a plurality of qubit circuits, performs computing operations based on the quantum states of the qubit circuits, and communicates with an external computer or computing system 130 via a communication link or network 120. The communication link and network 120 may include circuits through which signals are transferred in the form of electromagnetic signals, including electrical signals, carried, for example, by conductive wires and / or optical signals. In operation, the quantum computing system 110 receives computing requests or tasks from one or more external computers or computing systems 130, performs the requested computing operations, and returns the computing results to one or more requesting external computers or computing systems 130. The communication and / or interaction between the quantum computing system 110 and the external computer or computing system 130 is via the communication link or network 120 and may constitute the longest communication cycle in time in the operation of the quantum computing system 110 and is labeled as a long communication link or loop. As further explained below, the quantum computing system 110 is structured to partition different internal computing modules such that those internal computing modules communicate via internal shorter communication links or loops, such as medium communication links or loops with medium delays in time and high-speed communication links or loops with the shortest delays in time.

[0023] The quantum computing system 110 includes a multi-stage cryogenic system to maintain at different cryogenic temperatures at different locations to provide different cryogenic stages and keep different modules or devices at their individual desired temperatures (e.g., T1, T2, T3, and T4 as shown). In some implementations, the different cryogenic stages may be designed to produce temperatures in the millikelvin to tens of kelvin range. This exemplary system 110 includes a quantum computing module 102 that includes a plurality of qubit circuits or devices as a quantum qubit ensemble to perform desired quantum computing operations via their individual qubit states. In many implementations, the quantum computing module 102 is engaged or coupled to a cryogenic stage at a low cryogenic temperature T1 to ensure that the qubit circuits or devices are under the desired superconducting state and the noise level and interference level are at acceptable quantum computing operating conditions that are sufficiently low. The qubit management circuit module 104 communicates with the quantum computing module 102, provides control signals to the individual qubit circuits or devices of the quantum computing module 102, and is provided to read from the individual qubit circuits or devices, and may be implemented by using a non-quantum mechanical processing circuit such as a digital circuit network or an analog circuit network or a combination of a digital circuit network and an analog circuit network. The qubit management circuit module 104 may be implemented using a superconducting circuit network and, in some implementations, is coupled to a cryogenic stage at a cryogenic temperature T2 that may be different from the low cryogenic temperature T1 or, in other implementations, may be the same as the temperature T1. As further explained below, in some designs, the quantum computing module 102 and the qubit management circuit module 104 may be engaged to share a common cryogenic stage such that both modules are maintained at the same cryogenic temperature.The qubit management circuit module 104 can be structured to include, respectively, (1) a qubit control circuit for directing a control signal to the qubit circuit to control the qubit circuit, and (2) a qubit readout circuit for outputting a readout signal from the qubit circuit. In this embodiment, partly, the quantum computing operation is implemented within the quantum computing module 102 based on the control signal from the qubit management circuit module 104 to the qubit circuit, and the readout of the qubit circuit is implemented by the qubit management circuit module 104. Therefore, the quantum computing module 102 and the qubit management circuit module 104 together form the "heart" or "core" of the quantum computing system 110. The communication between the quantum computing module 102 and the qubit management circuit module 104 is essential for the quantum computing operation in terms of the quality and speed of such communication. Thus, in implementation, the quantum computing module 102 and the qubit management circuit module 104 are physically close to or adjacent to or positioned relative to each other to shorten the signal path between the two modules 102 and 104 and reduce any interference or noise to such communication. Additionally, the function or operation of the qubit management circuit module 104 can be limited to certain core functions or operations related to the quantum operations implemented by the quantum computing module 102 by intentional design, whereby the qubit management circuit module 104 can achieve short or fast response or processing times and ensure fast input / output signal transmission in the quantum computing module 102.The deliberately reduced functional design considerations for the qubit management circuit module 104 are also based on the proximity to its quantum computing module 102, the power consumption and energy dissipation around it by the qubit management circuit module 104, the desire to reduce noise or interference from the qubit management circuit module 104 to the quantum computing module 102, and the need to maintain appropriate cryogenic conditions in both the qubit management circuit module 104 and the adjacent quantum computing module 102. Based on the above and other considerations, the interconnections and signal paths between the two modules 102 and 104 are designed to form a high-speed communication link or loop with the shortest delay over time for the quantum computing system 110. For example, in some implementations, the quantum computing module 102 may include at least one integrated chip that supports one or more qubit circuits, and the qubit management circuit module 104 may be formed on another integrated chip that is directly coupled mechanically and electrically, as a multi-chip module, to the integrated chip with the qubit circuit via superconducting bumps, capacitive coupling, or magnetic coupling through a vacuum, and transfer control signals and readout signals therebetween. The multi-chip module formed by the two modules 102 and 104 can be coupled to the same cryogenic stage at a low cryogenic temperature T1. This design is a scalable platform for chip processing for the multi-chip module formed by the two modules 102 and 104, enabling a wide range of qubit circuits to be processed and included within the quantum computing module 102. Similarly, the qubit management circuit module 104 can also be scaled based on the number of qubit circuits present, which can be commercially important.

[0024] The quantum computing system 110 of FIG. 1A further includes a digital processing module 108 that provides certain signal and data processing functions or operations for the quantum computing system 110 in connection with quantum operations performed by the quantum computing module 102 via the qubit management circuit module 104. In this regard, the digital processing module 108 forms a core processing module for non-quantum operations and / or processing functions within the quantum computing system 110 and is thus designed with a much more complex circuitry and higher processing capabilities than the qubit management circuit module 104. Specifically, certain functions and / or processing operations that cannot be built into the qubit management circuit module 104 may be included within the circuitry of the digital processing module 108. Additionally, the digital processing module 108 also functions as an interface between the quantum computing system 110 and one or more external computers or computing systems 130 via a communication link or network 120. Thus, the digital processing module 108 is designed to further include processing functions associated with communication and interaction between the quantum computing system 110 and the external computer or computing system 130. Thus, unlike the setup and design of the qubit management circuit module 104, the digital processing module 108 is designed to be complex and capable of being a classical counterpart and coprocessor of the quantum computing module 102 of the quantum computing system 110. The increase in functions and / or processing operations and processing capabilities packed into the digital processing module 108 adds to the complexity and size of the circuitry of the digital processing module 108 and further increases the power consumption and energy dissipation of the digital processing module 108. Therefore, it is desirable to physically separate the digital processing module 108 from the quantum computing module 102 and its adjacent qubit management circuit module 104 in order to reduce the noise and interference that the digital processing module 108 may impose on the quantum computing module 102.The digital processing module 108 may be designed with various functions and capabilities, including, for example, an error correction function for the quantum computing system 110, and functions related to the control and readout of the quantum computing module 102, which are, for example, implemented by the qubit management circuit module 104, including non-quantum operations and / or processing functions within the quantum computing system 110, and may involve the management of data for quantum operations implemented by the quantum computing module 102. In some implementations, the digital processing module 108 may be coupled to the cryogenic stage at a higher temperature T4 than that for the quantum computing module 102 (at T1) and the qubit management circuit module 104 (at T1 or T2). The digital processing module 108 may be designed to include a superconducting circuit network and be enclosed within the multi-stage cryogenic system of the quantum computing system 110.

[0025] An intentional design to place the digital processing module 108 remotely from the qubit management circuit module 104 leads to a longer signal path or link between the digital processing module 108 and the qubit management circuit module 104. Such a signal path or link may be formed within the enclosure of the multi-stage cryogenic system by using superconducting wires or cables. In particular, the long length of such a signal path or link can cause a certain degree of signal degradation, and one option to address this is to add one or more interconnect repeaters or signal conditioning circuits 106 between the digital processing module 108 and the qubit management circuit module 104 to condition the signal. Similar to other modules within the multi-stage cryogenic system, each interconnect repeater or signal conditioning circuit 106 may be engaged or coupled to the cryogenic stage at a temperature T3 that is higher than the temperature of the qubit management circuit module 104 (at T1 or T2) and lower than the temperature of the digital processing module 108 (at T4). For example, the digital signal conditioning circuit module 106 may include a superconducting circuit that conditions a control signal or a readout signal.

[0026] In some implementations, the quantum computing system 110 may further include a digital processing subsystem 109 outside the multi-stage cryogenic system or cryostat system, communicate with the digital processing module 108, and perform operations associated with supporting the execution of quantum or quantum-classical algorithms and / or communication with one or more other computers or networks 130. This is shown in the embodiments of FIGS. 1C and 1D. The digital processing subsystem 109, which is outside the cryostat system, may include one or more CMOS digital processors, one or more field programmable gate arrays (FPGAs), or one or more application specific integrated circuits (ASICs), or one or more central processing units (CPUs).

[0027] The quantum processing performed by the quantum computing module 102 is the core of the quantum computing system 110, and the signal transmission and communication between the quantum computing module 102 and the rest of the system 110 play an important role in the overall computing speed and performance of the system 110. The latency in signal transmission and communication between the quantum computing module 102 and the rest of the system 110 is an important parameter to be optimized in order to achieve a scalable hybrid quantum-classical computing system for commercial use. During operation, information is passed between the quantum computing module 102, other processing modules, and computing entities involved in the operations performed in the quantum computing system 110. As shown, different communication links and / or feedback loops are formed between the quantum computing module 102, non-quantum modules, and other modules within the system 110. The fastest link / loop, labeled as the short loop in FIG. 1A, exists between the quantum computing module 102 and the qubit management circuit module 104. This link / loop is compared with the communication link / loop formed between the quantum computing module 102 and the digital processing module 108, which 1) passes through the qubit management module 104, which can perform its own operations on the data circulation between the quantum computing module 102 and the digital processing module 108, because the communication between these modules has to cross a longer distance, and 2) the digital processing module 108 can generally experience a longer latency because it performs more complex processing operations. Thus, in FIG. 1A, the communication between 102 and 108 is labeled as the medium communication link / loop.An even longer waiting time occurs between the quantum computing module 102 and the external computer or computing system 130, again due to the increased distance and the complexity of the processing operations (including the communication path and both the communication link or network 120 and the possible operations considered as short and medium loops) compared to the medium link / loop, and is labeled as a long communication link / loop in FIG. 1A.

[0028] Accordingly, the embodiment of the quantum computing system 110 of FIG. 1A includes special design features that provide a hybrid computing environment that combines the processing functions and / or operations by a quantum computing portion (e.g., the quantum computing module 102) and a non-quantum classical processing portion (e.g., the qubit management circuit module 104 and the digital processing module 108), installs the qubit management circuit module 104 to be physically proximate to the quantum computing module 102, while distancing the quantum computing module 102 from the digital processing module 108, and strategically partitions and distributes different amounts and types of processing functions and / or operations of the non-quantum classical processing portion between the qubit management circuit module 104 and the digital processing module 108.

[0029] In some implementations, digital processing module 108 may include two or more different processing modules and may be designed to optimize the computing speed and performance of digital processing module 108. For example, digital processing module 108 may further be divided into a series of modules, as shown in FIG. 1B, and different temperature stages of the cryogenic system may house one or more such modules. In general, the design of the quantum computing system 110 of FIG. 1A not only manipulates the dissipation during processing operations (which favors higher temperature stages that are placed further away from quantum module 102) against its particular need for short latency (which favors close proximity to quantum module 102), but also enables the optimization of the placement of each module within the cryogenic system so as to balance the ability to efficiently utilize the volume of the cryogenic system.

[0030] Figure 1C shows an example for performing a certain processing operation in different modules within the system 110 of Figure 1A. Specifically, it shows the processing operation within the digital processing module 108, the processing operation within an additional digital processing module 109 that operates at a higher temperature than that of the digital processing module 108, and the processing operation within the qubit management circuit module 104. As a specific example, Figure 1C shows that, in light of qubit readout from the qubit management circuit module 104, based on the information from the digital processing module 108, the desired quantum gate sequence produced by the additional digital processing module 109 is sent to the digital processing module 108, thereby being processed to generate an SFQ control pulse pattern. The qubit management circuit module 104 receives such an SFQ control pulse pattern, applies the received SFQ control pulse pattern and / or magnetic flux bias to the quantum module 102, and sets the associated qubits into the quantum gate sequence. This is an example for implementing the communication between the quantum computing module 102 and the digital processing module 108, including the in - communication loop of Figure 1A, i.e., the link between the qubit management module 104 or any interconnect module 106 between the modules 102 and 108. Figure 1C further shows an example for implementing a short communication loop between the qubit management module 104 and the quantum computing module 102. The qubit readout obtained from reading the quantum computing module 102 is digitally processed by the qubit management module 104, and the processed information is further used by the qubit management circuit module 104 to apply an SFQ control pulse pattern and / or magnetic flux bias to the quantum module 102.

[0031] In various implementations, the quantum computing module 102 and non - quantum classical processing parts (e.g., the qubit management circuit module 104 and the digital processing module 108) are structured to include superconducting circuits or devices that are coupled to different cryogenic stages of a multi - stage cryogenic system, and the superconducting interconnect wires 112, 114, and 116 are provided and maintained at temperatures at different locations to transfer signals between different modules or stages. The multi - stage cryogenic system for the quantum computing system 110 may be implemented in various configurations that include a multi - stage dilution refrigerator based on a mixture of helium - 3 and helium - 4 to provide different cryogenic stages at different levels of cryogenic temperature for its operating principle. In some implementations, the cryostat system may include a nuclear demagnetization refrigerator or an adiabatic demagnetization refrigerator.

[0032] The modules within the quantum computing system 110 may be implemented in various configurations. For example, each qubit circuit for the qubits within the quantum computing module 102 may include a superconducting Josephson junction circuit, or a switching superconducting circuit different from the Josephson junction circuit. For example, the qubit management circuit module 104 may be implemented to include a superconducting Josephson junction circuit or a single - flux - quantum (SFQ) logic circuit, or a quantum flux parametron circuit such as an adiabatic quantum flux parametron circuit, or a nanowire switch, or a superconducting ferromagnetic transistor, or a superconducting spintronics device, or a field - effect superconducting device. The digital processing module 108 may be implemented to include an SFQ circuit network, a field - programmable gate array (FPGA), or one or more application - specific integrated circuits (ASICs).

[0033] In the system of FIG. 1A, an optical communication link may be used for signal transfer either as a replacement for a conductive wire or cable, or as an additional link in combination with a conductive wire or cable. The optical communication link can provide faster data transmission and increase the communication bandwidth. For example, optical communication can be used between a cryogenic stage with a maximum temperature stage (e.g., module 108 of FIG. 1A) and a room temperature stage. In an implementation, optical transmitter and receiver devices are provided in such a stage or circuit module to enable the transmission and reception of optical signals between the cryogenic stage, which is placed at the maximum temperature of the cryostat system, and the room temperature electronics for communication therebetween. In some implementations, such an optical communication link may be implemented between module 108 and a CMOS FPGA subsystem.

[0034] FIG. 1D shows an example of a quantum computing system that can perform information processing based on quantum computing using the quantum states of qubits, at least partially based on the design of FIG. 1A. The cryostat system in this example is structured and operable to provide different cryogenic stages at different temperatures of 20 mK, 0.1 K, 0.7 K, and 3 K. Different circuit modules at different cryogenic stages are interconnected by superconducting wires such as NbTi / Kapton (NbTi / polyamide) strips. The quantum computing module surrounded by the cryostat system includes a first integrated chip structured to support qubit circuits. Each qubit circuit is structured as a superconducting circuit, exhibits different quantum states as qubits, interacts quantum mechanically with other qubit circuits via quantum entanglement, and causes superposition or correlation of different quantum states of the qubit circuits. The qubit management circuit 104 module is located adjacent to the quantum computing module 102 and is coupled to be maintained at the same low cryogenic temperature as the quantum computing module. The qubit management circuit includes a second integrated chip, a qubit control circuit supported by the second integrated chip and structured to direct control signals for controlling the qubit circuits to the qubit circuits respectively, and a qubit readout circuit supported by the second integrated chip and structured to output readout signals from the qubit circuits respectively. During operation, the readout signals represent the quantum states of the qubit circuits respectively, and the qubit control circuit and the qubit readout circuit include superconducting circuits and are structured to operate using the control signals and the readout signals in a non-quantum classical manner based on digital processing. In particular, the second integrated chip is engaged with the first integrated chip to form a multi-chip module (MCM) and transfer the control signals and the readout signals.

[0035] FIG. 1E shows an example for implementing an interconnection that couples different hardware components of classical and quantum circuits in the example of FIG. 1A, 1C, or 1D. An example of the system of FIG. 1E includes at least one classical non-quantum digital processing module 108 labeled as a “classical processor chip,” at least one SFQ repeater as part of an interconnection circuitry or module 106, and at least one classical superconducting controller as part of a qubit management circuit module 104 that controls a quantum computing processor or module 102 with a plurality of qubit circuits or devices.

[0036] The interconnection of FIG. 1E is designed to include superconducting connection nodes or pads 140 and superconducting connection cables 150 for connecting classical circuits 104, 106, and 108 to a quantum computing processor or module 102. As shown, the superconducting connection node or pad 140 may be implemented as a superconducting bump in direct contact with one or more hardware components (102, 104, 106, 108) to be connected and can be used to provide a connection between the hardware component and the superconducting cable. As described with reference to FIG. 1A, the quantum computing module 102 and the qubit management circuit module 104 are installed adjacent to each other, enabling a short connection path therebetween for high-speed inter-module communication and being thermally coupled to the same cryogenic stage at the same low cryogenic temperature. In particular, the communication link or loop between the classical superconducting controller as part of the qubit management circuit module 104 and the quantum processor chip 102 should be a high-speed communication link or loop, and the superconducting bump can be used to interconnect the two modules 102 and 104 to enable a high-speed exchange of information for quantum computing operations and readout. In some implementations, the qubit management circuit module 104 containing the classical controller chip is positioned on the cold plate of a cryocooler directly above or below the quantum computing module 102, reducing noise and interference to the quantum computing operations by the qubit circuit or device inside the quantum computing module 102. In some implementations, the superconducting bump can be configured or used in the form of a strip or microstrip line, or other on-chip transmission line, and a fence or wall that produces components separating a qubit or a system of qubits from each other, to reduce mutual crosstalk between superconducting electronic elements or systems and to improve the quality factor of the resonator.

[0037] In addition to the direct electrical connection between the quantum computing module 102 and the qubit management circuit module 104, non-contact connections, such as differential capacitive coupling and magnetic coupling between qubits and passive transmission lines, for example, may be used to achieve high-speed communication, both of which provide a communication link without involving a direct connection and enable compensation for geometric misalignments between modules 102 and 104 and other components as a result of the processing process.

[0038] Quantum computing operations by qubit circuits or devices inside the quantum computing module 102 use quantum mechanical phenomena such as superposition of "0" and "1" qubit states, entanglement between qubits, and interference between probability amplitudes of non-deterministic measurement results, and perform computing operations, different from a deterministic Turing machine and a classical computer based on Boolean bits in "0" and "1" states. The superconducting qubits inside the quantum computing module 102 can be implemented by superconducting Josephson junctions. A Josephson junction is a system consisting of weakly coupled superconductors that exhibits a correlated or coherent state and behaves like a non-linear inductor that enables the construction of a quantum harmonic oscillator. The two discrete energy level states of this harmonic oscillator and their quantum superposition are used to create qubits. Using Josephson junctions, several versions of superconducting qubits, such as transmon, exmon, quantronium, fluxonium, etc., can be constructed.

[0039] The state of a qubit is controlled by applying a microwave signal to the qubit. In various implementations, the microwave signal generator may be a room temperature device, but the quantum circuit, which includes the qubit, operates at a very low cryogenic temperature to reduce unwanted decoherence of the qubit. Specifically, the wiring required to provide the microwave signal to the qubit circuit may involve different sections maintained at different temperatures from room temperature to the lowest temperature in the cryogenic stage where the quantum circuit is located, and thus can cause or introduce unwanted electrical noise or excessive heat load. Such wiring for a significant number of qubit circuits can occupy a lot of space. These factors lead to unwanted decoherence of the qubit quantum state and can pose a significant problem for the scaling up of quantum computers.To overcome this problem, various techniques may be used to control qubits within a fully integrated cryogenic and hybrid quantum-classical processor as shown in FIGS. 1A-1E, for example, the integration of superconducting qubits with classical superconducting digital logic families such as reverse quantum logic (RQL) as disclosed by Quentin P. Herr and Anna Y. Herr in the paper entitled "Ultra-low-power superconductor logic" J. Appl. Phys. 109, 103903 (2011), the use of adiabatic quantum flux parametron (AQFP) as disclosed by O. Chen, R. Cai, Y. Wang, F. Ke, T. Yamae, R. Saito, N. Takeuchi, and N. Yoshikawa in the paper entitled "Adiabatic Quantum-Flux-Parametron: Towards Building Extremely Energy-Efficient Circuits and Systems" Sci. Rep. 9, 10514 (2019), or the use of single flux quantum (SFQ) technology as disclosed by O. A. Mukhanov in the paper entitled "Energy-Efficient Single Flux Quantum Technology" IEEE Trans. Appl. Supercond. 21, 760 (2011). As part of the interconnect design for the system in FIGS. 1A-1E, qubit control can be implemented via an SFQ system for controlling the state of the qubits by applying a sequence of SFQ pulses without involving the conventional use of microwave signals as disclosed in U.S. Patent No. 9,425,804.Techniques for applying flux to a quantum-coherent superconducting circuit, as described in U.S. Patent Application Publication No. 2015 / 0263736A1, by inventors Quentin P. Herr, Ofer Naaman, and Anna Y. Herr, and assignee Northrop Grumman Systems, may also be implemented. Readout of qubits may also be implemented by circuit quantum electrodynamics measurements, as disclosed in U.S. Patent No. 9,692,423, by Robert Francis McDermott et al., and applicants Universitaet des Saarlandes, Syracuse University, and Wisconsin Alumni Research Foundation, related to "System and method for circuit quantum electrodynamics measurement". Cryogenic CMOS (cryoCMOS) techniques may also be implemented within the system of FIGS. 1A-1E to control superconducting qubits.In "Cryo-CMOS for quantum computing" in their papers titled Technical Digest - International Electron Devices Meeting, IEDM (2017), pp. 1-13. (doi: 10.1109 / IEDM.2016.7838410), see the examples disclosed by E. Charbon, F. Sebastiano, A. Vladimirescu, H. Homulle, S. Visser, L. Song, and R. M. Incandela., and in their papers titled "A 28nm Bulk-CMOS 4-to-8GHz 2mW Cryogenic Pulse Modulator for Scalable Quantum Computing" IEEE J. Solid-St. Circuits 54, 3043-3060 (2019), see the examples disclosed by J. C. Bardin et al. Those references are incorporated by reference as part of the disclosure of this patent document.

[0040] The practical implementation of the system of FIGS. 1A - 1E requires careful design of the interconnection or interface between the quantum circuit of the quantum computing module 102, which is placed at a low cryogenic temperature (e.g., a few millikelvin), and the classical processing circuit, which is placed at a higher temperature (including liquid helium temperature). The interconnection in the embodiment of FIG. 1E involves placing the quantum computing module 102 and the qubit management circuit module 104 adjacent to each other on the same cryogenic stage of a dilution refrigerator without using any superconducting cable or wire 150 between modules 102 and 104. Instead, superconducting bumps or pads 140 are used to physically bond or couple the two modules 102 and 104 together. The signal path between the two modules 102 and 104 can be implemented in various ways, including signal transmission via a conductive path formed through the superconducting bumps or pads 140 between modules 102 and 104, or signal transmission via capacitive and / or magnetic coupling between modules 102 and 104. The signal path between the two modules 102 and 104 is designed to minimize the signal transmission time (e.g., by reducing or eliminating the amount of wiring between modules 102 and 104) and to form a high-speed communication link or loop within the system as described above with respect to FIG. 1A.

[0041] Two modules 102 and 104 are supported by two IC chips. In an implementation, the two chips are coupled as an integrated unit to the same low-temperature cryogenic stage, and thus both modules 102 and 104 are operated at the same low cryogenic temperature. To form a multi-chip module (MCM), they may be stacked and bonded to each other. Superconducting bumps or pads 140 may be used as part of the coupling of the two IC chips or modules 102 and 104. The interconnections in the embodiment of FIG. 1E also implement a combination of superconducting bumps or pads 140 and superconducting cables or wires 150. The superconducting bumps or pads 140 are used at the terminals of the superconducting cables or wires 150 to connect the wire terminals to the device. For example, in FIG. 1E, it is shown that the qubit management circuit module 104 is connected via a superconducting cable or wire 150 to an interconnection circuit network or module 106, such as a digital signal conditioning circuit module. Two sets of superconducting bumps or pads 140 are used to bond the two end terminals of each superconducting cable or wire 150 to contact points on the qubit management circuit module 104 and the corresponding interconnection circuit network or module 106. The use of the superconducting bumps or pads 140 and the superconducting cables or wires 150 can be applied to connections between the digital processing module 108 and the corresponding interconnection circuit network or module 106, and to other modules such as connections between different stages of the interconnection circuit network or module 106 or between digital signal conditioning circuit modules. As shown, such superconducting cables or wires 150 with superconducting bumps or pads 140 form part of the mid-communication links and loops as described above with respect to FIG. 1A.

[0042] Figure 2 shows an example of a portion of a flexible ribbon cable 200 having a superconducting stripline and superconducting contact bumps in one implementation of the interconnect 150 shown in FIG. 1E. The exemplary flexible ribbon cable 200 includes a conductive cable 210 that is supported by or engaged with a flexible non-conductive flexible substrate or tape 220, such as a Kapton tape, and is either a superconducting stripline or a microstripline (e.g., made of Nb or NbTi among other suitable conductive metal materials). The superconducting cable 200 further includes, in FIGS. 1A - 1E, conductive bumps 212 that serve to connect the cable 210 to electronic circuits placed on solid state (typically Si) chips or modules 102, 104, 106, and 108. These bumps 212 correspond to the bumps 140 in FIG. 1E. The superconducting cable 200 further includes a superconducting metallization 230 that typically serves as a ground electrode. Using a high-bandwidth superconducting cable can enable the transmission of microwave signals and single flux quantum (SFQ) pulses between different temperature stages (e.g., between 3K and 20mK in a dilution refrigerator) with a minimal thermal conductivity. Specifically, NbTi has a very low thermal conductivity, and when using a 50μm wide microstripline, the estimated thermal load is about 40μW. It is known that SFQ pulses will not be able to remain undamaged over a large distance between the highest and lowest temperature stages due to dispersion and attenuation within the cable. Thus, typically, shorter cable sections between the 3K stage, 700mK stage, 100mK stage, and 20mK stage that are present within a dilution refrigerator are used, namely, cable section #1 from 3K to 700mK, cable section #2 from 700mK to 100mK, and cable section #3 from 100mK to 20mK. The combination of superconducting cables and intermediate repeaters is used to achieve a significant increase in wiring density and, thus, can advantageously reduce the volume or space required for such wiring within a cryostat.

[0043] Additional embodiments related to superconducting cables suitable for implementing the disclosed technology involve using a pinch-chip bond to provide a fully vertical interconnect for a large-scale array of superconducting qubits fabricated on a single Si or sapphire chip at both room temperature and cryogenic temperatures down to about 10 mK for signal transmission from DC to about 10 GHz. One example for implementing such a pinch-chip bond can be found in the 8-page document "High-Density Qubit Wiring: Pin-Chip Bonding for Fully Vertical Interconnects" by M. Mariantoni and A.V. Bardysheva in Quantum Physics 2020 (arxiv.org / pdf / 1810.08580.pdf and arxiv.org / abs / 1810.08580), which is hereby incorporated by reference as part of the disclosure of this patent document.

[0044] To minimize dispersion and attenuation within a cable section as shown in FIG. 2 and other cable implementations, each cable section can be bump-bonded to a circuit module or chip involving an electronic superconducting circuit such as a superconducting contact pad or bump and an electronic superconducting circuit within the qubit management circuit module 104 and the classical control circuit within the interconnect circuit or module 106 (e.g., including an SFQ pulse regenerator / repeater). The classical controller chip and the quantum chip 102 for the qubit management module 104 are installed in the low-temperature stage of a dilution refrigerator and may be directly bump-bonded via superconducting contact pads (bumps) on both chips using MCM techniques. The superconducting contact pads (bumps) may be mechanically soft and structured to include indium and have a superconducting transition temperature of 3.4 K. Alternatively, non-superconducting bump bonding may also be used to couple the classical controller chip 104 and the quantum chip 102, and the classical chip 104 may further be connected to other classical chips via a superconducting or non-superconducting cable (coaxial or ribbon cable).

[0045] In some implementations, the ribbon cable can be connected by connecting to a special impedance converter wafer or chip (e.g., 50 to 20 ohms), which is then bump bonded to a classical chip. The quantum chip can be connected to other quantum chips using microwave waveguides or other types of quantum links without destroying the quantum coherence between the chips. Both surfaces of each chip (quantum and classical) can be used to form circuits. These circuits can be interconnected using (e.g., superconducting) silicon through vias (TSVs) and bump bonding.

[0046] The aforementioned direct bump bonding has several advantages and serves the following purposes, namely, (1) establishing a mechanical connection between the quantum chip 102 and the classical controller chip 104, (2) minimizing the impact of noise on the quantum chip 102 and minimizing the communication time between the classical controller chip 104 and the quantum chip 102, (3) setting a defined uniform distance (the same distance across the chip) between chips 102 and 104 to establish a reproducible and invariant coupling capacitance and mutual inductance between the circuits on both chips during operation, (4) providing a galvanic connection between the grounds on both chips 102 and 104 to form a common ground between them, (5) providing a galvanic connection of the signal lines to form a superconducting lossless loop between chips 102 and 104. These loops provide a magnetic flux bias for the qubits and the couplers between the qubits, (6) providing a galvanic connection between the chips to transmit SFQ pulses between the chips, (7) providing a galvanic connection to deliver a constant or switchable current used to form a single superconducting circuit comprising elements on both chips.

[0047] The common ground and the placement and design of the superconducting bumps 140 can be done in an array, a fence, a wall, etc. Referring to FIG. 3A, shown is a schematic perspective view of a portion of a chip 1000 (typically made from Si) comprising a transmission line structure 1001 and bumps 140 residing on a metallization 1002. Some of the metallizations 1002 may be connected to the ground plane of the chip 1000, while others may be connected to other parts of the circuitry on the chip 1000. In still other applications, including those using TSVs and bump bonding, the metallization 1002 may not be present.

[0048] The bumps 140 create a fence 140’ that improves the electromagnetic insulation between the transmission line structures 1001 and reduces crosstalk therebetween. In some implementations, instead of a number of bumps 140, a fence can be made as a continuous wall 140’’ as schematically shown in FIG. 3B for the same type of transmission line structure. Also, in various implementations, the fence 140’’ or wall 140’’ can be positioned on either the quantum chip 102 or the classical chip 104.

[0049] FIG. 3C shows an example where a superconducting fence 140’ or wall 140’’ is used to form a 3D compartment 300, each comprising one or more qubits, a classical circuit 203, and a superconducting metallization 201’, which is schematically shown in FIG. 3C as a cross-section of a portion of an MCM structure. Such an arrangement results in better electromagnetic insulation of the qubits from each other (i.e., reduces crosstalk) and increases the quality factor of resonators incorporated in or connected to the qubits. This is further illustrated through the simulation results presented in FIG. 4D.

[0050] Figure 4A schematically shows a cross-section of a section of a preferred MCM structure with two chips 301 and 302, the two chips being mechanically and electrically connected via bumps 140. The upper chip 301 has metallization 201' in the form of a superconducting thin film. The bottom chip 302 has a transmission line 202 and a section of metallization 201' that serves as a ground plane for the transmission line 202. The transmission lines 1001 in FIGS. 3A - 3C and the transmission lines 202 in FIGS. 4A - 4C are shown as examples, and in general, other circuits (both classical and quantum circuits) or circuit elements can be represented by portions 1001 and 202. The central section of the metallization 201' separates the two transmission lines 202 and is connected via bumps 140 to the metallization 201' on the upper chip.

[0051] Figure 4B shows another embodiment with a structure similar to that of FIG. 4A with modifications, where the bumps 140 that connect the central section of the metallization 201' on the bottom chip to its counterpart 201' on the upper chip are absent. Figure 4C shows a cross-section of a section of the bottom chip with a transmission line 202 and metallization 201' without any bumps 140.

[0052] Figure 4D shows the results of the simulated coupling between the transmission lines 202 for each of the three cases described above. Curves 1 - 3 in FIG. 4D correspond to the cases depicted in FIGS. 4A, 4B, and 4C respectively. From these plots, it can be inferred that for the structure shown in FIG. 4A, the minimum coupling (the best result) is obtained, where in this case, the transmission lines 202 are separated from each other by the fences created by the bumps 140. A similar situation, i.e., reduction of crosstalk, will be realized in a more complex circuit, specifically when quantum circuits are separated from each other by fences 140' or continuous walls 140''.

[0053] The aforementioned coupling of the classical controller chip 104 and the quantum chip 102 in the form of an MCM can be advantageous in some implementations for one or more of the following reasons. (i) The inter-chip bonding described above enables the classical control chip 104 and the quantum chip 102 to be fabricated using different technologies that may not be fully compatible with each other. The separate processing of these chips 104 and 102 allows the chips 104 and 102 to be individually fabricated using state-of-the-art processing techniques with high quality. (ii) If both the classical control circuit 104 and the quantum circuit 102 are fabricated on the same chip, the quantum chip 102 can be subject to quasiparticle poisoning from the classical control chip 104, which has been experimentally determined to lead to enhanced decoherence. (iii) The input / output signals between the room-temperature electronics and the MCM or between the repeater and the MCM are accomplished by connecting appropriate cables to the classical control chip 104, which can reduce the impact of electrical noise from higher temperature stages on the settings for the quantum chip 102.

[0054] Examples for implementing such an MCM with respect to chips 102 and 104 are shown in FIGS. 5A and 5B. As shown, the upper quantum chip 102 contains a qubit circuit and a readout resonator. The bottom classical chip 104 includes an SFQ circuitry and a power supply line for coupling to each qubit's qubit resonator. The current bias line I BQ or I F is used to provide a magnetic flux bias current to each qubit. This magnetic flux bias current can be provided through an inductive coupling across the gap between the classical chip and the quantum chip 102 as illustrated by the current bias line I BQ . Alternatively, the current bias line is the current bias line I FAs illustrated by, an inductor extends from the classical chip 104 to the quantum chip 102 through the bump 140 and is coupled to the qubit to provide a magnetic flux bias, and can reside on the quantum chip 102 with the qubit. The current bias line I F can be configured asymmetrically, as shown in FIG. 5A, or symmetrically, as shown in FIG. 5B. The superconducting indium bump 140 also connects the ground planes of the two chips 102 and 104. Other configurations of the MCM module are also conceivable as possibilities.

[0055] FIG. 5C shows another example for implementing an MCM assembly with respect to chips 104 and 102, where, in contrast to the configuration described above in which qubits and readout resonators are both integrated on the quantum chip 102, readout resonators for each qubit are located on the classical chip 104. In various implementations, superconducting qubits can be coupled to an electromagnetic resonator for readout based on the fact that the state of the qubit (grounded or excited) induces a shift in the resonance mode of the electromagnetic resonator. Both the qubit and the readout resonator are planar and can be fabricated on the same chip as that disclosed in the paper entitled "Strong coupling of a single photon to a superconducting qubit using circuit quantum electrodynamics" by Wallraff, A., Schuster, D. I., Blais, A., Frunzio, L., Huang, R. S., Majer, J., Kumar, S., Girvin, S. M., and Schoelkopf, R. J. in Nature, 431(7005), 162 - 167 (2004).Alternatively, various quantum circuit designs explore taking advantage of having as much electromagnetic field density as possible in a lossless vacuum by coupling qubits to 3D resonant modes such as those within a 3D cavity or resonator, as described in the paper "Observation of High Coherence in Josephson Junction Qubits Measured in a Three-Dimensional Circuit QED Architecture" by Paik, H., Schuster, D. I., Bishop, L. S., Kirchmair, G., Catelani, G., Sears, A. P., Johnson, B. R., Reagor, M. J., Frunzio, L., Glazman, L. I., Girvin, S. M., Devoret, M. H., and Schoelkopf, R. J. in Physical Review Letters, 107(24), 240501 (2011).

[0056] One way to implement the design of FIG. 5C is to fabricate each qubit and its corresponding readout resonator on different substrates and package and stack them within an MCM such that they are placed in different XY planes and separated by an inter-chip distance d along the Z-axis, while designing both the qubits and the readout resonators in a planar two-dimensional (2D) configuration for each circuit. In this design, the individual elements (e.g., each qubit and its corresponding readout resonator) are 2D components that each fully reside on its own substrate, but the integration density of the device or module is increased by coupling different 2D components or circuits in a three-dimensional (3D) fashion such that the mode coupling is an out-of-plane coupling between the planar qubit circuits to a matching planar readout resonator. This configuration combines 2D components that are stacked in a 3D configuration and can thus be referred to as a “2.5D” architecture. Under this “2.5D” design, the planar readout resonator resides entirely on a classical chip and thus exhibits 2D modes within the plane of the classical chip, independent of the quantum chip that contains the corresponding qubit. When the planar readout resonator is routed close to the quantum chip, as in an MCM, there are small out-of-plane components that provide coupling between the qubit and its corresponding readout resonator, but the majority of the readout resonator modes are still 2D within the plane of the classical chip. This design is advantageous due to the simplicity of fabricating 2D circuits or components, design flexibility, and / or increased integration density.

[0057] Specifically, the embodiment of FIG. 5C schematically illustrates that the transmons in the quantum qubit chip 102 are capacitively coupled to corresponding readout resonators in the classical chip 104. In this case, the coupling occurs between two capacitor pads separated by the inter-chip distance d. The readout resonator may be implemented, for example, as a meandering coplanar waveguide (CPW) resonator or a lumped element resonator. Other qubits are also diverse, such as fluxonium, C-shunted flux qubits (CSFQ), Cooper pair boxes, or other qubits along the charge / magnetic flux spectrum. Additionally, the coupling across the gap can in fact be capacitive or inductive.

[0058] Two substrates, each supporting qubits within chip 102 and readout resonators within chip 104, may be connected by bump joints 140. In implementations where the coupling between the qubits and the readout resonators is through capacitive or inductive coupling, these joints 140 may be implemented to provide purely mechanical connection or engagement, meaning that the qubits are electrically insulated from the resonator ground plane and are thus referred to as "floating qubits". Alternatively, the bump joints may provide a superconducting connection between the ground planes on both substrates such that each qubit is a "grounded qubit". In various implementations, the classical controller chip 104 may include electronic circuitry suitable for high-speed exchange of information between chip 104 and quantum chip 102. FIG. 6 shows an embodiment of an MCM containing a classical controller chip 104 and a quantum chip 102. In FIG. 6, the qubits and readout resonators are fabricated on the upper quantum chip 102. Josephson photomultiplier tubes (JPMs) and reflectometry ports are fabricated on the bottom classical controller chip 104. The JPM is coupled to an SFQ comparator that has a digital trigger in and a digital result out. For example, the comparator may be implemented as a standard SFQ circuit element mainly used within an SFQ analog-to-digital converter. All flux lines related to the JPM and the qubits are present on the classical controller chip 104. A readout (RO) port is also added to measure the readout resonator using microwaves. A more detailed layout of the JPM-SFQ comparator circuit is shown in the embodiment of FIG. 7. As shown by the right side of FIG. 7, a loop is fabricated from the junction point of the bottom comparator to convert flux to current. This loop is coupled to the JPM inductor using mutual inductance M c and is added to the loop to remove any residual flux left in the loop as a result of switching. A small additional junction J Q Two bias currents from current sources I B1 and I B2 are used to adjust the phase of the junction points of the two comparators.

[0059] FIG. 8 shows an example of a circuit design for improving capacitive coupling between qubits belonging to a classical SFQ chip 104 and a quantum chip 102. FIG. 8 schematically shows the capacitive coupling described above. The SFQ signal from the classical chip 104 is delivered to the qubit via a driver 401, a passive transmission line (PTL) 402, and a capacitor 500 created by an overlapping area A between a part of the PTL and a part of the qubit 202. The capacitance C of this capacitor 500 m is proportional to the area A and thus to the distance d that the PTL 402 extends into the appropriate part of the qubit. Due to the non-ideal reproducibility of the technical conditions, this distance d can vary from processing step to processing step, which results in an undesirable variation in the coupling capacitance δC m ∝ δd.

[0060] FIG. 9 shows an alternative implementation to FIG. 8 for overcoming the above-described drawbacks in the design of FIG. 8. The design of FIG. 9 uses two passive transmission lines (PTLs) 402 to provide capacitive coupling and reduces the variation in capacitive coupling caused by the mismatch between the PTL 402 and the appropriate part of the qubit in the design of FIG. 8. FIG. 9 uses capacitive coupling by two capacitors formed by overlapping areas A1 and A2. For the two PTLs 402 with conductive planes within the quantum chip 202, the total coupling capacitance C m is the sum of the two capacitors represented by the overlapping areas A1 and A2, and thus, due to the following relationship, i.e., C m ∝ A1 + A2 ∝ d1 + d2; δC m ∝ δ(d1 + d2) = 0, it will be preserved regardless of the actual positions d1, d2. The advantage of the coupling design of FIG. 9 is the reproducibility of the coupling capacitance for devices processed in different processes, which is important for establishing reproducible qubit control.

[0061] The above-described embodiments related to the disclosed quantum computing system provide a unique interconnection design for different modules, enabling a practical and scalable implementation based on a new system design and a new interconnection design that reduces or eliminates direct wiring connections between room temperature and the cryogenic stage where the quantum chip is placed. Multiplexing and demultiplexing circuits are installed on the qubit management module and the digital processing module, enabling each signal line to carry signals to / from multiple qubits within the quantum array, thus reducing the amount of wiring required between modules. The disclosed system design and interconnections will enable the quantum computing system to scale using different quantum computing capabilities for different applications. In an implementation, qubit control can be implemented by installing an SFQ control chip in close proximity to the quantum circuit chip, with suitable interconnections that operate by SFQ control and at different cryogenic temperatures, for example, from liquid He temperature for classical non-quantum processing circuits or modules to millikelvin temperature for one or more quantum circuits or processors.

[0062] Implementations of various features disclosed in this patent document may be based on what is disclosed herein, in light of various technical features in the following published references, which are incorporated by reference as part of the disclosure of this patent document. 1. “Energy-Efficient Single Flux Quantum Technology” by Oleg A. Mukhanov in IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, VOL. 21, NO. 3, JUNE 2011. 2. “Cryo-CMOS for Quantum Computing” by Charbon et al. in IEEE, 2016. 3. "Design and Characterization of a 28-nm Bulk-CMOS Cryogenic Quantum Controller Dissipating Less Than 2 mW at 3 K" by Leonard Jr. et al., in IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 11, NOVEMBER 2019. 4. "Digital Coherent Control of a Superconducting Qubit" by Bardin et al., in PHYSICAL REVIEW APPLIED 11, 014009 (2019).

[0063] Although this patent document contains many details, these should be construed as descriptions of features that may be specific to particular embodiments of a particular technique rather than as limitations to any subject matter or to the scope of what may be claimed. In the context of separate embodiments, features described in this patent document may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented separately in multiple embodiments or in any suitable sub-combination. Also, features may be described above as acting in a certain combination and may further be claimed as such, but in some cases, one or more features from the claimed combination may be excluded from the combination, and the claimed combination may also cover a sub-combination or a variation of a sub-combination.

[0064] Only a few implementations and examples are described, but other implementations, improvements, and variations can be made based on what is described and illustrated in this patent document.

Claims

A system capable of information processing based at least in part on quantum computing using multiple quantum states of multiple qubits, the system comprising: A cryostat system structured to include a plurality of different cryogenic stages operable to provide a low cryogenic temperature and a plurality of higher cryogenic temperatures; A quantum computing module surrounded by the cryostat system at the low cryogenic temperature, the quantum computing module comprising a first integrated chip structured to support a plurality of qubit circuits, each qubit circuit presenting a plurality of different quantum states as a quantum mechanical system and interacting quantum mechanically with other qubit circuits via quantum entanglement to cause a superposition or correlation of the plurality of different quantum states of the plurality of qubit circuits, structured as a superconducting circuit at the low cryogenic temperature; A quantum bit management circuit module surrounded by the cryostat system, wherein the quantum bit management circuit module is arranged adjacent to the quantum computing module and coupled to be maintained at an extremely low temperature. A plurality of quantum bit control circuits are supported by a second integrated chip and structured to direct a plurality of control signals to the plurality of quantum bit circuits respectively for controlling the plurality of quantum bit circuits. A plurality of quantum bit readout circuits are supported by the second integrated chip and structured to output a plurality of readout signals from the plurality of quantum bit circuits respectively. The plurality of readout signals respectively represent a plurality of quantum states of the plurality of quantum bit circuits. The plurality of quantum bit control circuits and the plurality of quantum bit readout circuits are structured to include a plurality of superconducting circuits at the low extremely low temperature and operable to operate using the plurality of control signals and the plurality of readout signals in a non-quantum classical manner based on digital processing. The second integrated chip engages with the first integrated chip to form a multi-chip module for transferring the plurality of control signals and the plurality of readout signals between the first integrated chip and the second integrated chip. A quantum bit management circuit module A plurality of circuit modules surrounded by the cryostat system at the plurality of higher extremely low temperatures, wherein the plurality of circuit modules are structured to communicate with the quantum bit management circuit module in relation to the plurality of control signals and the plurality of readout signals. A plurality of circuit modules A plurality of conductive bumps formed to mechanically and electrically engage the first integrated chip and the second integrated chip with each other, wherein the plurality of conductive bumps are structured to separate a plurality of different quantum bit circuits on the first integrated chip and a plurality of different transmission lines on the second integrated chip. A plurality of conductive bumps A plurality of conductive wires, wherein the plurality of conductive wires are coupled between the quantum bit management circuit module and at least one of the plurality of circuit modules placed at a plurality of higher temperature stages of the cryostat system, thereby providing a plurality of communications and transferring a plurality of signals between the quantum bit management circuit module and the at least one of the plurality of circuit modules. A plurality of communication links that perform the information processing at a plurality of different speeds during the operation of the system, wherein the plurality of communication links include one or more first communication links formed between the quantum computing module and the quantum bit management circuit module, one or more second communication links formed between the quantum computing module and at least one of the plurality of circuit modules, and one or more third communication links formed between the quantum computing module and one or more processors disposed outside the cryostat system. Each of the one or more first communication links is configured to provide communication with a first communication delay, each of the one or more second communication links is configured to provide communication with a second communication delay longer than the first communication delay, and each of the one or more third communication links is configured to provide communication with a third communication delay longer than the second communication delay. A system comprising the above. Claim 2 The plurality of conductive bumps are for providing mechanical engagement between the first integrated chip and the second integrated chip, and the plurality of conductive bumps are not electrically connected to a circuit in either the first integrated chip or the second integrated chip. The system according to claim 1, wherein the quantum computing module and the quantum bit management circuit module are coupled to each other to exchange information via conductive coupling or inductive coupling. Claim 3 The system according to claim 1, wherein at least a part of the plurality of conductive bumps is connected to form a conductive path between the quantum bit management circuit module and the quantum computing module for transferring a part of the plurality of control signals and the plurality of readout signals without using other wirings between the quantum bit management circuit module and the quantum computing module.

4. The system according to claim 1, wherein the plurality of conductive bumps include a plurality of conductive insulating bumps, and the plurality of conductive insulating bumps are arranged to reduce crosstalk between the plurality of conductive wires by forming a plurality of insulating fences that separate the plurality of conductive wires.

5. The quantum computing module includes a plurality of conductive insulating bumps, and the plurality of conductive insulating bumps are arranged to reduce crosstalk between respective ones of the plurality of quantum bit circuits and to reduce decoherence of the plurality of quantum bit circuits by forming a plurality of insulating fences that separate the plurality of quantum bit circuits, the system according to claim 1.

6. The system further includes a plurality of conductive insulating walls, and the plurality of conductive insulating walls are arranged to reduce crosstalk between the plurality of conductive wires by forming a plurality of insulating walls that separate the plurality of conductive wires, the system according to claim 1.

7. The quantum computing module includes a plurality of conductive insulating walls, and the plurality of conductive insulating walls reduce crosstalk between respective ones of the plurality of quantum bit circuits and reduce decoherence of the plurality of quantum bit circuits by separating the plurality of quantum bit circuits, the system according to claim 1.

8. The quantum bit management circuit module and the quantum computing module are structured to include a capacitive coupling circuit network so as to provide a signal transmission separate from the conductive path formed by the plurality of conductive bumps by enabling capacitive coupling between the quantum bit management circuit module and the quantum computing module. The system according to claim 1.

9. The quantum bit management circuit module and the quantum computing module are structured to include a magnetic coupling circuit network so as to provide a signal transmission separate from the conductive path formed by the plurality of conductive bumps by enabling magnetic inductive coupling between the quantum bit management circuit module and the quantum computing module. The system according to claim 1.

10. The system further includes a flexible non-conductive material, on which the plurality of conductive wires are formed and separated from each other, and the flexible non-conductive material and the plurality of conductive wires form a flexible ribbon connecting at least one of the plurality of circuit modules and the quantum bit management circuit module. The system according to claim 1.

11. Each quantum bit circuit includes a superconducting Josephson junction circuit at the low cryogenic temperature. The system according to claim 1.

12. The quantum bit management circuit module includes a superconducting switching circuit different from the Josephson junction circuit. The system according to claim 1.

13. The quantum bit management circuit module includes a Josephson junction circuit. The system according to claim 1.

14. The quantum bit management circuit module includes a single flux quantum (SFQ) logic circuit. The system according to claim 1.

15. The quantum bit management circuit module includes a quantum flux parametron circuit, and the system according to claim 1.

16. The quantum bit management circuit module includes a nanowire switch, and the system according to claim 1.

17. The quantum bit management circuit module includes a superconducting ferromagnetic transistor, and the system according to claim 1.

18. The quantum bit management circuit module includes a superconducting spintronics device, and the system according to claim 1.

19. The quantum bit management circuit module includes a field effect superconducting device, and the system according to claim 1.

20. The system further includes an optical transmitter device and a receiver device that provide communication between the plurality of cryogenic stages and the plurality of room temperature electronic devices by enabling transmission and reception of optical signals between the plurality of cryogenic stages placed at the highest temperature of the cryostat system and the plurality of room temperature electronic devices, and the system according to claim 1.

21. The quantum bit management circuit module and the quantum computing module are maintained at the same low cryogenic temperature, and the system according to claim 1.

22. The quantum computing module further includes a plurality of readout resonators, the plurality of readout resonators are supported by the first integrated chip, and are structured to generate a plurality of quantum bit circuit readout signals by interacting with the plurality of quantum bit circuits respectively. The plurality of quantum bit readout circuits are supported by the second integrated chip, and are structured to receive the plurality of quantum bit circuit readout signals respectively by interacting with the plurality of readout resonators supported by the first integrated chip, and output the plurality of readout signals respectively, and the system according to claim 1.

23. The plurality of qubit readout circuits supported by the second integrated chip are structured to include a plurality of readout resonators supported by the second integrated chip, and are structured to generate a plurality of qubit circuit readout signals by interacting with the plurality of qubit circuits supported by the first integrated chip respectively. The plurality of qubit readout circuits supported by the second integrated chip are structured to receive the plurality of qubit circuit readout signals respectively by interacting with the plurality of readout resonators respectively, and to output the plurality of readout signals respectively. The system according to claim 1.

24. A method for information processing at least partially based on quantum computing using a plurality of quantum states of a plurality of qubits, the method comprising: Operating a quantum computing module comprising a first integrated chip structured to support a plurality of qubit circuits, the plurality of qubit circuits exhibiting a plurality of different quantum states as a quantum mechanical system and being operable to cause a superposition or correlation of the plurality of different quantum states of the plurality of qubit circuits by causing a quantum mechanical interaction between the plurality of qubit circuits; Causing a plurality of qubit control circuits supported by a second integrated chip to control the plurality of qubit circuits respectively by directing a plurality of control signals to the plurality of qubit circuits respectively; Operating a plurality of qubit readout circuits to output a plurality of readout signals respectively from the plurality of qubit circuits, the plurality of readout signals each representing a plurality of quantum states of the plurality of qubit circuits; Thermally coupling the plurality of qubit circuits, the plurality of qubit control circuits, and the plurality of qubit readout circuits to a common cryogenic stage; By coupling the plurality of qubit circuits, the plurality of qubit control circuits, and the plurality of qubit readout circuits via a plurality of conductive bumps that mechanically and electrically engage with each other between the first integrated chip and the second integrated chip, applying each of the plurality of control signals from the plurality of qubit control circuits to the plurality of qubit circuits, wherein the plurality of conductive bumps are structured to separate a plurality of different qubit circuits on the first integrated chip and to separate a plurality of different transmission lines on the second integrated chip, Using a plurality of conductive wires coupled between the qubit management circuit module and one or more circuit modules at one or more high temperatures higher than the temperature of the common cryogenic stage coupled to the plurality of qubit circuits, the plurality of qubit control circuits, and the plurality of qubit readout circuits, to transmit information in connection with operating the plurality of qubit circuits, the plurality of qubit control circuits, and the plurality of qubit readout circuits, Using a plurality of communication links that perform the information processing at a plurality of different speeds, the plurality of communication links including one or more first communication links formed between the quantum computing module and the qubit management circuit module, one or more second communication links formed between the quantum computing module and at least one of the plurality of qubit control circuits and the plurality of qubit readout circuits, and one or more third communication links formed between the quantum computing module and one or more processors, each of the one or more first communication links being configured to provide communication with a first communication delay, each of the one or more second communication links being configured to provide communication with a second communication delay longer than the first communication delay, and each of the one or more third communication links being configured to provide communication with a third communication delay longer than the second communication delay, A method comprising. **Claim 25**: The method according to claim 24, comprising one or more operating steps when operating the system according to any one of claims 1 to 23. **Claim 26**: The system according to claim 1, wherein the plurality of conductive bumps include a plurality of conductive superconducting bumps. **Claim 27**: The quantum computing module and the qubit management circuit module are mutually coupled to provide signal transmission between the quantum computing module and the qubit management circuit module through a conductive path formed between the quantum computing module and the qubit management circuit module using the plurality of conductive superconducting bumps, or through a capacitive coupling formed between the quantum computing module and the qubit management circuit module, or through a magnetic coupling formed between the quantum computing module and the qubit management circuit module. The system according to claim 26. **Claim 28**: The method according to claim 24, wherein the plurality of conductive bumps include a plurality of conductive superconducting bumps. **Claim 29**: The quantum computing module and the qubit management circuit module are mutually coupled to provide signal transmission between the quantum computing module and the qubit management circuit module through a conductive path formed between the quantum computing module and the qubit management circuit module using the plurality of conductive superconducting bumps, or through a capacitive coupling formed between the quantum computing module and the qubit management circuit module, or through a magnetic coupling formed between the quantum computing module and the qubit management circuit module. The method according to claim 28.

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