SYSTEM, MEDIUM AND METHOD FOR PROCESSING AN INTEGRATED SIGNAL HAVING MULTIPLE SIGNAL COMPONENTS HAVING ARBITRARY POWER ALLOCATIONS - Patent application

Abstract

To process a GNSS integration signal with multiple signal components with an arbitrary power allocation.SOLUTION: An integration signal processing unit of a GNSS receiver generates a plurality of complex rotated samples in parallel for one sample of an integration signal. The plurality of complex rotated samples (e.g., advanced complex rotated samples, delayed complex rotated samples) are accumulated in parallel in a window of arbitrary width equal to or smaller than number of code chips in a PRN code sequence. The integrated signal processing unit sequentially generates a plurality of complex rotation samples for one sample. The plurality of complex rotated samples (e.g., advanced complex rotated samples, on-time complex rotated samples, delayed complex rotated samples) are accumulated sequentially in the window. The GNSS receiver can utilize the accumulated complex rotated samples to implement a correlation technique, to implement a multipath mitigation technique, and / or to track the integration signal.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] background Technical Field The present invention relates generally to Global Navigation Satellite Systems (GNSS), and more particularly to a GNSS receiver for processing an integrated signal having multiple signal components with arbitrary power allocation.

[0002] Background information With the development of Global Navigation Satellite Systems (GNSS), an increasing number of GNSS signals are broadcast to provide diverse services (e.g., positioning, navigation, timing, etc.). To conserve resources in providing such services, multiple signals may need to be multiplexed into one composite signal. Furthermore, the composite signal may have a constant envelope property to mitigate signal distortions that may be caused, for example, by nonlinear amplification.

[0003] ACE-BOC (Asymmetric Constant Envelope Binary Offset Carrier) is a dual-frequency constant envelope multiplexing technique that allows four independent spread spectrum codes to be modulated onto two different carrier frequencies of an integrated signal with any combination of power ratios. Compared to other constant envelope multiplexing techniques, ACE-BOC can provide greater design flexibility in terms of the number of signal components, the power ratio between the components, etc. Such design flexibility can provide versatility in optimizing signaling that may be required for various services. However, the design flexibility associated with the integrated signal may result in complexity in the processing of the integrated signal.

[0004] overview In one or more embodiments, the system, medium, and method process an integrated signal having multiple signal components with arbitrary power allocation. In one embodiment, the integrated signal processing unit can generate multiple complex rotated samples in parallel for one sample of the integrated signal, thereby accumulating the multiple complex rotated samples for the sample in parallel within a window that spans any arbitrary width up to the number of code chips in a pseudorandom noise (PRN) code sequence. For example, the window can span at least 1.5 code chips (e.g., 2 code chips, 3 code chips, 10 code chips, etc.).

[0005] In one implementation, an integral signal processing unit of a global navigation satellite system (GNSS) receiver can generate a local code for a sample of an integrated signal, where the local code can correspond to a code in the integrated signal. The integral signal processing unit can select a phase rotation value and a code shift value based on the local code. For example, the phase rotation value and the code shift value can be selected from a shift / phase lookup table. The integral signal processing unit can generate an early complex rotated sample and a late complex rotated sample for the sample in parallel based on the selected phase rotation value.

[0006] The integral signal processing unit can utilize the selected code shift value to generate early and late code phase values ​​in parallel that span at least 1.5 code chips (e.g., 2 code chips), where the late code phase values ​​are offset in time by one pseudorandom noise (PRN) chip of code phase. The integral signal processing unit can utilize the early and late code phase values ​​to generate a final bin enable output from the early and late bin enable outputs. The integral signal processing unit can accumulate multiple complex rotated samples (e.g., an early complex rotated sample and a late complex rotated sample) in parallel for a single sample, utilizing the final bin enable output generated for a window that spans at least 1.5 code chips (e.g., 2 code chips).

[0007] For example, the final bin enable output can be utilized to accumulate early and late complex rotated samples in parallel within one or two of a plurality of bins spanning at least 1.5 code chips (e.g., two code chips). The plurality of bins can be used to generate correlation values ​​that may be required to implement one or more correlation techniques and / or one or more multipath mitigation techniques. Additionally or alternatively, the weighting bins can utilize the early bin enable output and the late bin enable output to accumulate early and late complex rotated samples in parallel for a window spanning 1.5 code chips (e.g., two code chips) for the purpose of tracking the integrated signal.

[0008] In one embodiment, the integrated signal processing unit can sequentially generate multiple complex rotated samples for one sample of the integrated signal, thereby sequentially accumulating multiple complex rotated samples for the sample within a window spanning at least 1.5 code chips (e.g., 3 code chips or 10 code chips). In particular, the integrated signal processing unit can generate multiple local codes for one sample of the integrated signal, where the multiple local codes correspond to codes in the integrated signal. For example, the multiple local codes can include an early version of the code in the integrated signal, a punctual version of the code in the integrated signal, and a late version of the code in the integrated signal.

[0009] The integral signal processing unit can provide one local code of the plurality of local codes to the shift / phase lookup table based on a value of a counter that starts from a minimum value and increments to a value corresponding to the number of the plurality of local codes, so that each of the plurality of local codes is sequentially provided to the shift / phase lookup table as the counter increments.

[0010] The integral signal processing unit can select a phase rotation value and a code shift value based on the provided local code. The integral signal processing unit can generate complex rotated samples based on the selected phase rotation value. The integral signal processing unit can generate code phase values ​​based on the selected code shift value by offsetting in time the selected code shift value based on the value of the counter, as necessary, such that the window spans at least 1.5 code chips (e.g., 3 code chips).

[0011] For example, a code shift value selected based on an early version of the code should not be offset in time since the counter has a value of 0. A code shift value selected based on an on-time version of the code can be offset in time by one PRN chip of code phase since the counter has a value of 1. Furthermore, a code shift value selected based on a late version of the code can be offset in time by two PRN chips of code phase since the counter has a value of 2. Thus, in this example, the window spans three code chips. Thus, in this example, complex rotation and code phase values ​​are generated sequentially for each of a plurality of local codes for a window spanning three code chips.

[0012] The integration signal processing unit can generate a bin enable output based on the generated code phase value. The integration signal processing unit can utilize the bin enable output, each generated for a window spanning at least 1.5 code chips (e.g., 3 code chips), to sequentially accumulate multiple complex rotated values ​​for a single sample. For example, the respective bin enable outputs can be utilized to sequentially accumulate multiple complex rotated samples in multiple bins spanning at least 1.5 code chips (e.g., 3 code chips). The multiple bins can be used to generate correlation values ​​that may be required to implement one or more correlation techniques and / or one or more multipath mitigation techniques. Additionally or alternatively, the weighting bins can utilize the respective bin enable outputs to sequentially accumulate multiple complex rotated samples for a window spanning 1.5 code chips (e.g., 3 code chips or 10 code chips) for the purpose of tracking the integration signal.

[0013] The following description refers to the accompanying drawings. [Brief description of the drawings]

[0014] [Figure 1]1 is a schematic block diagram of a system according to one or more embodiments described herein. [Figure 2A] FIG. 1 is a schematic block diagram of an integrated signal processing unit capable of processing an integrated signal by generating multiple complex rotated samples in parallel for one sample of the integrated signal, in accordance with one or more embodiments described herein. [Figure 2B] FIG. 11 is a schematic block diagram of another integrated signal processing unit capable of processing an integrated signal by generating multiple complex rotated samples in parallel for one sample of the integrated signal, in accordance with one or more embodiments described herein. [Figure 2C] FIG. 11 is a schematic block diagram of another integrated signal processing unit capable of processing an integrated signal by generating multiple complex rotated samples in parallel for one sample of the integrated signal, in accordance with one or more embodiments described herein. [Diagram 3] 1 is a schematic block diagram of a shift / phase lookup table according to one or more embodiments described herein. [Figure 4] FIG. 2 is a schematic block diagram of a sample enable decoder according to one or more embodiments described herein. [Diagram 5] 1 is an example flowchart for processing an integrated signal by generating multiple complex rotated samples in parallel for one sample of the integrated signal, according to one or more embodiments described herein. [Figure 6A] FIG. 1 is a schematic block diagram of an integrated signal processing unit capable of processing an integrated signal by sequentially generating multiple complex rotated samples for one sample of the integrated signal, in accordance with one or more embodiments described herein. [Figure 6B] FIG. 11 is a schematic block diagram of another integrated signal processing unit capable of processing an integrated signal by sequentially generating multiple complex rotated samples for one sample of the integrated signal, in accordance with one or more embodiments described herein. [Figure 6C] FIG. 1 is a schematic block diagram of an integrated signal processing unit capable of processing an integrated signal by sequentially generating multiple complex rotated samples for one sample of the integrated signal, in accordance with one or more embodiments described herein. [Figure 7A] FIG. 2 is a schematic block diagram of a shift table according to one or more embodiments described herein. [Figure 7B] FIG. 2 is a schematic block diagram of a sample enable decoder according to one or more embodiments described herein. [Figure 8] 1 is an example flowchart for processing an integrated signal by sequentially generating multiple complex rotated samples for one sample of the integrated signal, according to one or more embodiments described herein.

[0015] Detailed Description of the Preferred Embodiments 1, the system 100 includes one or more client devices 105 and one or more transmitters, such as one or more Global Navigation Satellite System (GNSS) satellites 110 that transmit one or more navigation signals, e.g., GNSS satellite signals (not shown). Although reference may be made to a GNSS satellite 110 that transmits a GNSS satellite signal, it is expressly contemplated that one or more embodiments described herein may be utilized with any of a variety of different transmitters, e.g., terrestrial transmitters, that transmit any of a variety of different navigation signals. Thus, the description of a GNSS satellite 110 that transmits a GNSS signal should be made for purposes of example only.

[0016] The GNSS satellites 110 may be associated with one or more satellite navigation systems, such as, but not limited to, Galileo, Beidou Navigation System (BDS), Global Positioning System (GPS), and / or GLONASS. For example, the GNSS satellites 110 may transmit one or more integrated signals based on Asymmetric Constant Envelope Binary Offset Carrier (ACE-BOC) multiplexing, i.e., integrated GNSS signals. According to one or more embodiments described herein, the integrated signals may be referred to as ACE-BOC signals. ACE-BOC multiplexing may combine up to four signal components (e.g., up to four independent bipolar direct sequence spread spectrum signals) at two different frequencies into one constant envelope integrated signal, where the signal components may have any power ratio, modulation, and code rate. For example, the four signal components may be E5a-I, E5a-Q, E5b-I, and E5b-Q of the Galileo satellite constellation, or B2a-I, B2a-Q, B2b-I, and B2b-Q of the Beidou satellite constellation.

[0017] The client device 105 is typically mobile and includes an antenna 115 and a GNSS receiver 120, i.e., a navigation receiver, having one or more processors 125 and a memory 130. For example, the client device 105 may be a mobile phone, a laptop computer, a portable computer, a personal digital assistant, etc. In addition, the GNSS receiver 120 may be a single frequency, dual frequency, or multi-frequency receiver. The memory 130 may store one or more values ​​associated with one or more embodiments described herein.

[0018] The one or more processors 125 execute an integral signal processing unit 200 (e.g., 200A, 200B, 200C, 200D, 200E, and 200F), which can process an integrated signal that may have, for example, any power allocation among the signal components, in accordance with one or more embodiments described herein.

[0019] FIG. 2A is a schematic block diagram of an integrated signal processing unit 200A capable of processing an integrated signal by generating multiple complex rotated samples in parallel for one sample of the integrated signal in accordance with one or more embodiments described herein.

[0020] According to one or more embodiments described herein, samples of an integrated signal synchronized to a sample clock 204 can be processed by generating an early complex rotated sample 215A and a late complex rotated sample 215B in parallel for each sample 201, as described in more detail below with reference to FIGS. 2A-4. The complex rotated samples 215A and 215B for a sample 201 can be accumulated in parallel in a number (N) of bins 220 spanning any arbitrary width less than or equal to the number of code chips in a pseudorandom noise (PRN) code sequence. For example, a window can span at least 1.5 code chips (e.g., 2 code chips). In one implementation, the bins 220 can accumulate (sum) the complex rotated samples for some predetermined period of time. The bins can be hardware, software, or a combination thereof.

[0021] The GNSS receiver 120 can use the accumulated complex rotated samples (e.g., 215A and 215B) within selected bins 220 and / or selected groups of bins 220 for the plurality of samples to generate correlation values ​​that may be needed to implement one or more correlation techniques and / or one or more multipath mitigation techniques and / or track an integrated signal, as described in more detail below. Additionally or alternatively, a weighting vector can be utilized with the complex rotated samples (e.g., 215A and 215B) for the plurality of samples to generate correlation values ​​that may be utilized to track an integrated signal, for example, as described in more detail below.

[0022] In one implementation, the size and / or starting points of the bins 220 and / or of the bins 220 selected in various groupings can be changed to vary the spacing and position corresponding to the complex rotated samples, etc. As an illustrative example, assume that the bins 220 of FIG. 2A include 20 bins evenly spaced across a span of two code chips. Further assume that the first 10 bins (e.g., bin 0 through bin 9) are "early bins" spanning the first code chip, and the second 10 bins (e.g., bin 10 through bin 19) are "late bins" spanning the second code chip.

[0023] Although the examples described with reference to FIGS. 2A-4 may refer to 20 bins that are evenly spaced and span two code chips, it is expressly contemplated that one or more embodiments described herein may be utilized with any number (N) of bins 220 that span at least 1.5 chips, less than 1.5 chips, or any portion of a full PRN code period. In one implementation, the bins 220 may be evenly or unevenly spaced. In one implementation, the number of bins 220 may be between 18 and 24 bins. In alternative implementations, the number of bins 220 may be any integer value. In one embodiment, a bin may correspond to a time slot or a slot of code phase values ​​that are located in a window that spans two or more code chips.

[0024] 2A, a code phase numerically controlled oscillator (NCO) 203 can utilize a code rate 205 to generate a fine code chip phase detail used to represent an estimated code phase value. For example, at each pulse of a sample clock 204 at which a sample of the integrated signal is taken, the code phase NCO 203 can generate a code phase sub-chip value that indicates the time slot in code chips relative to the sample 201. In one implementation, the code phase sub-chip value is between 0 and 0.99. In one implementation, the code rate 205 can be asynchronous to the sample clock 204.

[0025] The code phase NCO 203 or chip count 207 can drive a 4xPRN code generator 202, which can generate a local code, e.g., a pseudorandom noise (PRN) code, for the samples 201 of the integrated signal, where the local code corresponds to one of the codes in the received integrated signal. For example, the first bit (e.g., the most significant bit) of the 4-bit code corresponds to an upper frequency in-phase signal (S UI) The second bit of the four-bit code corresponds to a lower frequency in-phase signal (S LI The third bit of the four-bit code corresponds to an upper frequency quadrature signal (S UQ ) The fourth bit (e.g., the least significant bit) of the four-bit code may correspond to a lower frequency quadrature signal (S LQ ) can be accommodated.

[0026] When the sub-chip value generated by the code phase NCO 203 rolls over to one, the chip count 207 may be incremented and a signal may be sent to the 4xPRN code generator 202 indicating the start of a new code chip. Based on this signal, the 4xPRN code generator 202 may generate the next 4-bit local code. When the chip count reaches the end of its count, for example 10229, the chip count may roll back to zero and a reset signal may be sent to the 4xPRN code generator 202. In this example, the local code may be a leading version of the code in the received integrated signal. The leading version of the code may lead the code in the received integrated signal by, for example, one code chip or ½ code chip, etc.

[0027] Continuing with the example where the plurality of bins 220 includes 20 bins evenly spaced over a window of two code chips, assume also that for a pulse of the sample clock 204, the code phase NCO 203 generates a code phase sub-chip value of 0.99 and that the 4×PRN code generator 202 now generates a local code of 1010. Additionally, in this example, assume that the local code generated by the 4×PRN code generator 202 for the previous code chip was 1111.

[0028] In accordance with one or more embodiments described herein, the shift / phase lookup table 206 can be utilized by the integral signal processing unit 200A to select code shift and phase rotation values ​​based on a local code, which are used to generate an early complex rotated sample 215A and a late complex rotated sample 215B in parallel relative to the sample 201, and these complex rotated samples 215A and 215B are accumulated in parallel within a number of bins 220, e.g., one or two of 20 bins, spanning two code chips, as described in further detail below.

[0029] In particular, as described in more detail below, a phase rotation value selected from the shift / phase lookup table 206 can be used to generate an early complex rotated sample 215A and a late complex rotated sample 215B in parallel with respect to the sample 201. Additionally, as described in more detail below, a code shift value selected from the shift / phase lookup table 206 can be utilized to (1) enable one or two bins of a plurality of bins 220 (e.g., 20 bins) that span two code chips, and (2) determine which complex rotated sample is provided in the enabled bin, e.g., whether the early complex rotated sample 215A or the late complex rotated sample 215B is provided with respect to the sample 201.

[0030] A sample clock 204 may be provided to the shift / phase lookup table 206, which selects a code shift value and a phase rotation value from the shift / phase lookup table 206 for each sample 201. In addition, as known to those skilled in the art, the subcarrier mixed with the signal component of the integrated signal may be at a frequency of 15.345 MHz, while the code rate may be 10.23 MHz. Therefore, for odd code chips, the phase rotation value selected from the shift / phase lookup table 206 may need to be adjusted by 180 degrees. Therefore, the least significant bit of the chip count 207 may be provided to the shift / phase lookup table 206 to indicate whether the code chip is even or odd.

[0031] 3 is a schematic block diagram of a shift / phase lookup table 206 according to one or more embodiments described herein. The processor 125 of the GNSS receiver 120 can initialize the shift / phase lookup table 206 such that each PRN code included in column 301 has a corresponding phase rotation value in column 302 and a code shift value in column 303. In particular, the shift / phase lookup table 206 can be programmable such that the phase rotation value in column 302 and the code shift value in column 303 corresponding to the PRN codes in column 301 can be changed based on, for example, system requirements, user preferences, etc. For example, the code shift value in column 303 corresponding to the PRN codes in column 301 can be changed based on whether the system should utilize a symmetric shift or a positive shift. In addition, the code shift value and the phase rotation value corresponding to the PRN codes in column 301 can be changed based on the type of integrated signal. For example, the code shift and phase rotation values ​​in the shift / phase lookup table 206 may be varied based on whether the integrated signal is an ACE-BOC Type I signal, an ACE-BOC Type II signal, or an ACE-BOC Type III signal.

[0032] Although the shift / phase lookup table 206 includes particular values ​​in columns 301, 302, and 303, it is expressly contemplated that the shift / phase lookup table 206 may include different values ​​in accordance with one or more embodiments described herein. Additionally, although reference is made to selecting code shift values ​​and phase rotation values ​​corresponding to local codes using the shift / phase lookup table 206 of FIG. 3, it is expressly contemplated that the code shift values ​​and phase rotation values ​​corresponding to local codes may be selected in any of a variety of different manners.

[0033] As described above, in this example, a local code of 1010 is generated by the 4×PRN code generator 202. The local code of 1010 can be provided to the 4-bit encoder 304 of the shift / phase lookup table 206 and used to identify a row in column 301 that corresponds to the local code of 1010 and select a phase rotation value from column 302 and a code shift value from column 303. In this example, the local code of 1010 corresponds to the 11th row of column 301. A phase rotation value of 0.875 in the 11th row of column 302 and a code shift value of 0.250 in the 11th row of column 303, both of which correspond to the PRN code 1010, can be selected by the 4-bit encoder 304 and provided at an output of the 4-bit encoder 304. The code shift value of 0.250 can be output from the 4-bit encoder 304 and provided as an output of the shift / phase lookup table 206. In one implementation, the code shift value may be 10 bits. In one implementation, the code shift value may be sign extended to be 13 bits.

[0034] A phase rotation value of 0.875 may be output from the 4-bit encoder and provided to adder 310. If the least significant bit of the chip count 207 provided to the 1-bit encoder 306 indicates that the code chip is even, then the 1-bit encoder 306 outputs a value of 0 to the adder so that the phase rotation value of 0.875 is not modified. However, if the least significant bit of the chip count 207 indicates that the code chip is odd, then the 1-bit encoder outputs a value of π so that the phase rotation value is adjusted by 180 degrees by adder 310. In this example, it is assumed that the code chip is even. Thus, the phase rotation value of 0.875 is provided as the output of the shift / phase lookup table 206 without being adjusted by adder 310.

[0035] According to one or more embodiments described herein, a phase rotation value, e.g., 0.875, output from the shift / phase lookup table 206 can be utilized to generate an early complex rotated sample 215A and a late complex rotated sample 215B in parallel relative to the sample 201, as described in further detail below.

[0036] Returning to FIG. 2A, the carrier phase NCO 208 estimates a carrier phase value (e.g., sine and cosine transforms) based on the accumulated carrier Doppler frequency 209. The carrier phase value from the carrier phase NCO 208, which is required to correct the signal 201 for the Doppler effect, is added to the leading phase rotation value (e.g., 0.875 output from the shift / phase lookup table 206) in the summer 210A. The result of this addition can be a leading complex phase rotation value. The complex mixer 211A can mix the samples 201 (e.g., multi-bit I and Q samples) with the leading complex phase rotation value to obtain leading complex rotated samples 215A. The leading complex rotated samples 215A can be provided to the inputs of each of the multiple multiplexers 225, for example, to input A.

[0037] To generate delayed complex rotated samples 215B, a phase rotation value, for example 0.875, is delayed by 1 PRN. In particular, the phase rotation value of 0.875 is provided to a 1PRN delay unit 212A that can store a phase rotation value for a previous code chip. The phase rotation value of 0.875 provided to the 1PRN delay unit 212A can function as a signal to the 1PRN delay unit 212A indicating that the phase rotation value for the previous code chip should be provided from the 1PRN delay unit 212A to the adder 210B. In this example, as described above, the local code for the previous code chip is 1111. Based on the shift / phase lookup table 206, the phase rotation value corresponding to the PRN code 1111 is 0.125. Thus, based on the phase rotation value of 0.875 provided from the shift / phase lookup table 206 to the 1PRN delay unit 212A, the 1PRN delay unit 212A provides a phase rotation value of 0.125+0.5 for the previous code chip to the summer 210B, which adds the estimated carrier phase value to the phase rotation value of 0.625 to remove the Doppler effect.

[0038] The summation by the adder 210B may result in a delayed complex phase rotation value. The complex mixer 211B may mix the samples 201 with the delayed complex phase rotation value to obtain delayed complex rotated samples 215B. The delayed complex rotated samples 215B may be provided to a different input of each of the multiple multiplexers 225 than the input provided with the advanced complex rotated samples 215A, e.g., input B.

[0039] Thus, a single sample 201 is utilized by the integral signal processing unit 200A to generate an early complex rotated sample (215A) and a late complex rotated sample (215B) in parallel. As will be explained in more detail below, the complex rotated sample can be provided, for example, from two multiplexers 225 to two enabled bins of a number of N bins, for example 20 bins, spanning two code chips. As will be explained in more detail below, the determination of which enabled bins the early complex rotated sample and the late complex rotated sample are provided to, respectively, can be based on code shift values ​​obtained from the shift / phase lookup table 206 and the code phase NCO.

[0040] The code shift value output from the shift / phase lookup table 206 can be used to generate multiple sample code phase values, e.g., early and late sample code phase values, in parallel, across two code chips. In this example, the code shift value of 0.250 output by the shift / phase lookup table 206 is provided to a summer 210D. The summer 210D adds the code shift value of 0.250 to the code phase sub-chip value of 0.99, representing the time slot in code chips for the sample 201, provided by the code phase NCO 203, to obtain an early sample code phase value of 1.24. This early sample code phase value can be provided to an early sample enable decoder 213A. The early sample enable decoder 213A can determine which bins of the multiple bins 220 are enabled based on the provided early sample code phase value of 1.24. If the early sample code phase value is less than 1.0, the early sample code phase value may enable an early bin, e.g., one of bins 0 through 9, in accordance with one or more embodiments described herein. If the early sample code phase value is greater than 1.0, the early sample code phase value may enable a late bin, e.g., one of bins 10 through 19, in accordance with one or more embodiments described herein. In this example, an early sample code phase value of 1.24 is greater than 1.0, and therefore an early sample code phase value of 1.24 enables a late bin, as described in further detail below.

[0041] 4 is a schematic block diagram of a sample enable decoder 213, e.g., a lead sample enable decoder 213A, according to one or more embodiments described herein. The sample enable decoder 213 may include a starting position for each bin of the plurality of bins 220, which may be initialized by the processor 125. In this example, there are 20 evenly spaced bins spanning two code chips. The following table shows where each of the 20 bins may start for this example, with reference to a window spanning two code chips. [Table 1]

[0042] The leading sample code phase value may be provided to a limiter 402 of the sample enable decoder 213 such that any negative values ​​are set to zero. Alternatively, negative values ​​for the leading sample code phase value may simply be filtered out (i.e., ignored) by the integral signal processing unit 200A according to one or more embodiments described herein. In this example, the leading sample code phase value is 1.24 and therefore is not set to zero, for example. Thus, the leading sample code phase value of 1.24 is provided to each of a number of comparators 405, for example, N comparators, each of which may correspond to a different bin. Thus, in this example, there are 20 comparators corresponding to different bins of the 20 bins. Each of the plurality of comparators 405 may utilize the leading sample code phase value, for example, 1.24, to determine whether the corresponding bin should be enabled. The output of each of the multiple comparators 405, e.g., Y, may be set to a value of 1 (i.e., ←) if the bin should be enabled, or to a value of 0 (i.e., ←) if the bin should not be enabled (e.g., remains disabled).

[0043] In particular, as shown in Fig. 4, x represents a leading sample code phase value, e.g., 1.24. For each comparator except the last one, A represents a start value for the current bin and B represents a start value for the next bin. If the leading sample code phase value, e.g., x, is within a range defined by the start value of the current bin, e.g., A, and the start value of the next bin, e.g., B, it is determined that the current bin should be enabled, e.g., Y is set to a value of 1. In particular, if the leading sample code phase value, e.g., x, is greater than or equal to A and less than B, the current bin should be enabled, e.g., Y is set to a value of 1; otherwise, the bin is disabled / kept disabled, e.g., Y is set to a value of 0.

[0044] For the last comparator, A may represent the start value of the last bin and B may represent the end value of the last bin. If the leading sample code phase value, e.g. x, is within a range defined by the start value, e.g. A, of the last bin and the end value, e.g. B, of the last bin, it is determined that the last bin should be enabled, e.g. Y is set to a value of 1. In particular, if the leading sample code phase value, e.g. x, is greater than or equal to A and less than B, the last bin should be enabled, e.g. Y is set to a value of 1, otherwise the last bin is disabled / remains disabled, e.g. Y is set to a value of 0. Alternatively, the last comparator may only utilize A, which represents the start value. In this embodiment, if the leading sample code phase value, e.g. x, is greater than or equal to A, the last bin should be enabled, e.g. Y is set to a value of 1, otherwise the bin is disabled / remains disabled, e.g. Y is set to a value of 0.

[0045] In this example, the leading sample code phase value of 1.24 is utilized by each of the 20 comparators 405 to determine which bins should be enabled. In particular, in this example, the thirteenth comparator, which corresponds to bin 12, determines that the leading sample code phase value of 1.24 is within the range of 1.2(A) to 1.3(B). Thus, the output of the thirteenth comparator is an enable signal for bin 12, e.g., Y is set to a value of 1. All other comparators, e.g., comparators 1-12 and 14-20, determine that the leading sample code phase value of 1.24 is not within the ranges defined for these other comparators. Thus, the output of these other comparators is a disable bin signal, e.g., Y is set to a value of 0.

[0046] Thus, in this example, the output from enabler 410A of the leading sample enable decoder 213A is a leading bin enable output 216A for enabling bin 12 (a lagging bin) of the 20 bins. According to one embodiment, the leading bin enable output 216A may be a vector of 0's and 1's, where a 1 indicates that the bin should be enabled, while a 0 indicates that the bin should not be enabled, e.g., remains disabled. Thus, the leading bin enable output 216A in this example may be 0000 0001 0000 0000 0000, where the least significant bit of this vector represents bin 0 and the most significant bit represents bin 19. As described in further detail below, the leading bin enable output 216A output by the leading sample enable decoder 213A can be used to enable one of the multiple bins 220 and also to determine which complex rotated sample is provided in which enabled bin, e.g., whether the leading complex rotated sample 215A or the lagging complex rotated sample 215B is provided.

[0047] Returning to FIG. 2A , the code shift value obtained from the shift / phase lookup table 206, for example 0.250, may be delayed by 1 PRN to generate a delayed sample code phase value utilized to enable one of the bins 220. In particular, the code shift value of 0.250 is provided to a 1PRN delay 212B that may store a code shift value for a previous code chip. The code shift value of 0.250 provided to the 1PRN delay 212B may function as a signal to the 1PRN delay 212B indicating that the code shift value for the previous code chip should be provided from the 1PRN delay 212B to the adder 210E. In this example, as described above, the local code generated for the previous code chip is 1111. Based on the shift / phase lookup table 206, the code shift value corresponding to the PRN code 1111 is −0.250. Thus, based on the code shift value of 0.250 provided from shift / phase lookup table 206 to 1PRN delay 212B, 1PRN delay 212B may provide a code shift value of -0.250 for the previous code chip to summer 210E, which may add the code shift value of -0.250 to the code phase subchip value of 0.99 and a value of 1 to generate a late sample code phase value of 1.74 (e.g., -0.250+0.99+1). The value of 1 is added by summer 210E to offset the late sample code phase value in time by one PRN chip period (i.e., for the second code chip of a window spanning two code chips).

[0048] The 1.74 late sample code phase value may be provided to a late sample enable decoder 213B. The late sample enable decoder 213B may determine which bins of the plurality of bins 220 are enabled based on the provided 1.74 late sample code phase value. If the late sample code phase value is less than 1.0, the late sample code phase value may enable an early bin, e.g., one of bins 0-9, in accordance with one or more embodiments described herein. If the late sample code phase value is greater than 1.0, the late sample code phase value may enable a late bin, e.g., one of bins 10-19, in accordance with one or more embodiments described herein. In this example, the 1.74 late sample code phase value is greater than 1.0, and thus the 1.74 late sample code phase value enables a late bin, as described in further detail below.

[0049] In particular, referring to FIG. 4, the sample decoder 213, e.g., late sample enable decoder 213B, may utilize the final late sample code phase value 1.74 in a manner similar to that described above, where the x in FIG. 4 represents the late sample code phase value 1.74 rather than the early sample code phase value, e.g., 1.24, as described above with respect to the early sample enable decoder 213A. More specifically, in a manner similar to that described above, each of the plurality of comparators 405 may utilize the late sample code phase value, e.g., 1.74, to determine whether the corresponding bin should be enabled. In this example, the 18th comparator, which corresponds to bin 17, determines that the late sample code phase value of 1.74 is within the range of 1.7(A) to 1.8(B). Thus, the output of the 18th comparator is the enable signal for bin 17, e.g., Y is set to a value of 1. All other comparators, e.g., comparators 1 through 17, 19, and 20, determine that the late sample code phase value of 1.74 is not within the range defined with respect to these other comparators. Therefore, the outputs of these other comparators are disable bin signals, eg, Y is set to a value of 0.

[0050] Thus, in this example, the output from enabler 410A of late sample enable decoder 213B is a late bin enable output 216B for enabling bin 17. According to one embodiment, the late bin enable output 216B may be a vector of 0's and 1's, where a 1 indicates that the bin is enabled, while a 0 indicates that the bin is disabled. Thus, the late bin enable output 216B in this example may be 0010 0000 0000 0000 0000, where the least significant bit of this vector represents bin 0 and the most significant bit represents bin 19.

[0051] 2A, an early bin enable output 216A, e.g., 0000 0001 0000 0000 0000, and a late bin enable output 216B, e.g., 0010 0000 0000 0000 0000, may be provided from early sample enable decoder 213A and late sample enable decoder 213B, respectively, to OR gate 214. OR gate 214 may utilize an OR operation to generate a final bin enable output 216AB of 0010 0001 0000 0000 0000, where the least significant bit may represent bin 0 and the most significant bit may represent bin 19. The final bin enable output 216AB may be provided to a plurality of bins 220 spanning two code chips to enable none of the plurality of bins 220, enable one bin of the plurality of bins 220, or enable two bins of the plurality of bins 220. In this example, the final bin enable output 216AB is a vector of 0010 0001 0000 0000 0000 from OR gate 214 and is provided to bins 220 to enable bins 12 and 17 of the plurality of 20 bins spanning two code chips.

[0052] In particular, each bit of the final bin enable output 216AB may be provided to a corresponding bin, such that bins provided with a value of 1, e.g., a high signal, are enabled, while bins provided with a value of 0, e.g., a low signal, remain disabled. In this example, bins 12 and 17 are provided with a value of 1, e.g., a high signal, while bins 0-11, 13-16, 18, and 19 are provided with a value of 0, e.g., a low signal. Thus, bins 12 and 17 are enabled, while bins 0-11, 13-16, 18, and 19 remain disabled.

[0053] Further, as shown in FIG. 2A, the early bin enable output 216A output from the early sample enable decoder 213A can be provided to a number of multiplexers 225 to determine which complex rotated sample is provided in the enabled bins, e.g., bins 12 and 17, e.g., early complex rotated sample 215A or late complex rotated sample 215B. The number of multiplexers 225 can correspond to the number of bins 220, and each of the multiplexers 225 can be coupled to a different bin 220 as shown in FIG. 2A. For example, as shown in FIG. 2A, the first multiplexer is coupled to bin 0, the second multiplexer is coupled to bin 1, and so on. Thus, in this example, each of the 20 different multiplexers 225 is coupled to a different bin of the 20 bins spanning two code chips. In one implementation, each multiplexer 225 has an output Y, an input A for receiving the early complex rotated samples 215A, and an input B for receiving the late complex rotated samples 215B.

[0054] 2A, the leading bin enable output 216A, for example 0000 0001 0000 0000 0000, may be provided to multiplexers 225. In particular, each bit of the leading bin enable output 216A, which may be a vector, may be provided to a different multiplexer 225 corresponding to the appropriate bin. For example, the least significant bit of the leading bin enable output 216A may represent bin 0 and thus be provided to the first multiplexer 225 coupled to bin 0. The most significant bit of the leading bin enable output 216A may represent bin 19 and thus be provided to the last multiplexer (e.g., multiplexer 20) coupled to bin 19 (e.g., bin N-1).

[0055] In one implementation, a multiplexer 225 that receives a high signal (e.g., a value of 1) based on a bit of the leading bin enable output 216A provides the leading complex rotated sample 215A received at input A as an output (e.g., Y). Additionally, a multiplexer 225 that receives a low signal (e.g., a value of 0) based on a bit of the leading bin enable output 216A provides the lagging complex rotated sample 215B received at input B as an output (e.g., Y). In one implementation, only one multiplexer 225 is provided with a high signal (e.g., a value of 1), so that only one multiplexer 225 provides the leading complex rotated sample 215A as an output (e.g., Y), while all other multiplexers 225 are provided with a low signal (e.g., a value of 0), so that all other multiplexers 225 provide the lagging complex rotated sample 215B as an output (e.g., Y).

[0056] In an alternative embodiment, the multiplexer may be configured and operated in the opposite manner (not shown), in which case the leading bin enable output 216A of the leading sample enable decoder 213A is inverted, for example, utilizing an inverter (not shown) that would be placed between the OR gate 214 and the multiplexer 225. Thus, a leading bin enable output 216A of 0000 0001 0000 0000 0000 would be inverted to 1111 1110 1111 1111 1111. Thus, in this alternative embodiment, multiplexer 225 receiving a low signal (e.g., a value of 0) based on the inverted leading bin enable output would provide as an output (e.g., Y) the leading complex rotated sample received at input A. Furthermore, multiplexer 225 receiving a high signal (e.g., a value of 1) based on the inverted lead bin enable output 216A will provide as an output (e.g., Y) the lagged complex rotated sample received at input B.

[0057] The early complex rotated samples 215A and / or the late complex rotated samples 215B are then provided to the corresponding enabled bins from an output (e.g., Y) of the multiplexer 225. In this example, bins 12 and 17 are enabled based on the final bin enable output 216AB, which is a vector of 0010 0001 0000 0000 0000 from the OR gate 214, as described above. In addition, in this example, the thirteenth multiplexer coupled to the enabled bin 12 receives a high signal, e.g., a value of 1, based on the early bin enable output 216A, e.g., 0000 0001 0000 0000 0000.

[0058] Thus, the early complex rotated sample 215A received at input A of the thirteenth multiplexer 225 is provided as an output, e.g., Y, of the thirteenth multiplexer 225 and provided to the enabled bin 12 to be accumulated in this bin 12. Additionally, in this example, the eighteenth multiplexer coupled to the enabled bin 17 receives a low signal, e.g., a value of 0, based on the early bin enable output 216A. Thus, the late complex rotated sample 215B received at input B of the eighteenth multiplexer 225 is provided as an output, e.g., Y, of the eighteenth multiplexer 225 and provided to the enabled bin 17 to be accumulated in this bin 17. Since the other multiplexers 225, e.g., 1-12, 14-17, 19, and 20, are coupled to the disabled bins, the outputs from these other multiplexers 225 (e.g., the late complex rotated sample 215B) are not accumulated in the disabled bins.

[0059] Thus, as described above, two complex rotated samples, e.g., an early complex rotated sample 215A and a late complex rotated sample 215B, can be generated in parallel for a single sample 201 and accumulated in parallel in multiple bins 220 spanning two code chips. Thus, according to one or more embodiments described herein, multiple samples of an integrated signal synchronized to a sample clock 204 can be processed by generating an early complex rotated sample and a late complex rotated sample in parallel for each of the multiple samples and accumulating the complex rotated samples in multiple bins 220 spanning two code chips. The receiver can use the complex rotated samples accumulated in selected bins 220 and / or selected groups of bins 220 for the multiple samples to generate correlation values ​​that may be needed to implement one or more correlation techniques and / or one or more multipath mitigation techniques.

[0060] More generally, OR gate 214 and multiplexer 225 perform the following desired functions:

number

number

[0061] Further, the accumulated complex rotated samples can be utilized to calculate a correlation measurement that can be utilized, for example, to track an integrated signal. As shown in FIG. 2A, complex rotated samples 215A generated in parallel with samples 201(i) can be used to calculate a correlation measurement that can be utilized, for example, to track an integrated signal. i and 215B i2A, the early complex rotated samples 215A are provided from the complex mixer 211A to the first input (e.g., the top arrow) of the weighting bin 230A and the last input (e.g., the bottom arrow) of the weighting bin 230B. Also, as shown in FIG. 2A, the late complex rotated samples 215B are provided from the complex mixer 211B to the second input (e.g., the second arrow from the top) of the weighting bin 230A and the third input (e.g., the third arrow from the top) of the weighting bin 230B.

[0062] Additionally, a leading bin enable output 216A and a lagging bin enable output 216B may be provided from the leading sample enable decoder 213A and the lagging sample enable decoder 213B to the weighting bins 230A and 230B. In particular, as shown in Figure 2A, the leading bin enable output 216A is provided from the leading sample decoder 213A to input A of the weighting bins 230A and 230B. Additionally, as shown in Figure 2A, the lagging bin enable output 216B is provided from the lagging sample decoder 213B to input B of the weighting bins 230A and 230B.

[0063] In one embodiment, the complex rotated samples 215A and 215B may be accumulated within a window spanning at least 1.5 code chips, for example 2 code chips, to track the integrated signal.

[0064] In particular, the weighting bin 230A can store a weighting vector that can be utilized to generate a punctual (P) signal that can be utilized for tracking. In one implementation, the processor 125 can initialize the weighting bin 230A such that it stores a weighting vector for the P signal. In one implementation, the value for the P signal for tracking can be set as

number

number

[0065] The summation part of this equation can be implemented in adder 242. Thus, in this example with 20 bins, w P may be a vector of length 20, and w P Each weight value in can correspond to a different bin. For example, w P The first value in (W b1 ) may be the weight for bin 0, and w P The second value in (W b2 ) may be the weight for bin 1, and so on. P The weights in can be based on a variety of factors, including, but not limited to, the particular type of integrated signal (e.g., an ACE-BOC Type I signal, an ACE-BOC Type II signal, or an ACE-BOC Type III signal), the power ratio of the integrated signals, the implementation of the integrated signal, etc.

[0066] Continuing with the above example, based on the above formula, the advanced complex rotated sample 215A and w corresponding to bin 12 are P 215B and the lag complex rotated sample 215C, which corresponds to bin 17. P Utilizing the delay bin enable output 216B with weights from i In the adder 242, P i The values ​​can be summed (ie, accumulated) to generate the P signal.

[0067] Additionally, the weighting bin 230B can store a weighting vector that can be utilized to generate an early-late (EL) signal that can be utilized for tracking. In one implementation, the processor 125 can initialize the weighting bin 230B such that the weighting bin 230B stores a weighting vector for the EL signal. In one implementation, the value of the EL signal for tracking (EL i )of,

number

number

[0068] So in this example with 20 bins, W E-L may be a vector of length 20, and w E-L Each weight value in can correspond to a different bin. For example, W E-L The first value in (W b1 ) may be the weight for bin 0, and W E-L The second value in (W b2 ) may be the weight for bin 1, and so on. E-L The weights in can be based on a variety of factors, including, but not limited to, the particular type of integrated signal (e.g., an ACE-BOC Type I signal, an ACE-BOC Type II signal, or an ACE-BOC Type III signal), the power ratio of the integrated signals, the implementation of the integrated signal, etc.

[0069] Continuing with the above example, based on the above formula, the advanced complex rotated sample 215A and w corresponding to bin 12 are E-L 215B and the lag complex rotated sample 215C, which corresponds to bin 17. E-L EL i In the adder 244, EL i The values ​​can be summed (i.e., accumulated) to generate the EL signal. Thus, adders 242 and 244 sum the P and EL accumulated signals for some predetermined period of time to generate the P and EL accumulated signals, respectively. i Value and ELi Accumulate (sum up) values.

[0070] The P and EL accumulation signals from 242 and 244 may be provided to a tracking module 252, which may be external to the integral signal processing unit 200, as shown in FIG. 2A. In one embodiment, the tracking module may include a code tracking loop 253, which may be a delay locked loop (DLL) that may operate in a conventional manner. Additionally, the tracking module may include a carrier tracking loop 254, which may be a phase locked loop (PLL) or a frequency locked loop (FLL), each of which may operate in a conventional manner.

[0071] In one implementation, the tracking module receives a code error signal (Code Error )of,

number

[0072] Similarly, according to one or more embodiments described herein, the in-phase and quadrature components of the punctual signal generated by summer 242 can be provided to a carrier tracking loop 254 (e.g., a PLL or FLL) and utilized by the carrier tracking loop 254 (e.g., a PLL or FLL) to generate a new estimate of the carrier Doppler frequency 209, as known to those skilled in the art.

[0073] FIG. 2B is a schematic block diagram of another integral signal processing unit 200B that can process an integrated signal by generating multiple complex rotated samples in parallel for one sample of the integrated signal 201, according to one or more embodiments described herein. FIG. 2B is similar to FIG. 2A, but the integral signal processing unit 200B does not include bins 220. Thus, as shown in FIG. 2B, the early complex rotated sample 215A and the late complex rotated sample 215B generated in parallel for the sample 201 are provided to both weighting bins 230A and 230B to track the integrated signal as described above. Although the integral signal processing unit 200B of FIG. 2B does not include bins 220, it can utilize the weighting bins 230A and 230B to generate P and EL accumulation signals as described above with reference to FIG. 2A. The P and EL accumulation signals are provided to a tracking module 252 to generate Code for tracking as described above with reference to FIG. 2A. Error , code rate 205, and / or carrier Doppler frequency 209 may be calculated.

[0074] 2C is a schematic block diagram of another integral signal processing unit 200C that can process an integrated signal by generating multiple complex rotated samples 215A and 215B in parallel for one sample of the integrated signal, according to one or more embodiments described herein. FIG. 2C is similar to FIG. 2A, but the integral signal processing unit 200C does not include weighting bins 230A and 230B and summers 242 and 244. Thus, the integral signal processing unit 200C of FIG. 2C can accumulate complex rotated samples in selected bins 220 and / or in selected groups of bins 220 to generate correlation values ​​that may be required to implement one or more correlation techniques, and / or one or more multipath mitigation techniques, and / or one or more techniques for generating code rate (e.g., DLL) and carrier Doppler frequency estimates (e.g., PLL or FLL), as described above with reference to FIG. 2A.

[0075] 5 is an example flow chart for processing an integrated signal by generating multiple complex rotated samples in parallel for one sample of the integrated signal, according to one or more embodiments described herein. The procedure 500 starts at step 505 and proceeds to step 510 where an integrated signal is received at a GNSS antenna. In one embodiment, the integrated signal may be based on ACE-BOC multiplexing and may have multiple signal components with arbitrary power allocation.

[0076] The procedure proceeds to step 515 where a local code is generated for the samples 201 of the integrated signal, the local code corresponding to one of the codes in the received integrated signal. In one implementation, the local code may be an advanced version of the code in the integrated signal. The procedure proceeds to step 520 where a phase rotation value and a code shift value are selected based on the local code. For example, the phase rotation value and the code shift value may be selected from the shift / phase lookup table 206 as described above with reference to FIG. 3.

[0077] The procedure proceeds to step 525 where early complex rotated samples 215A and late complex rotated samples 215B are generated in parallel based on the phase rotation values ​​(e.g., early phase rotation values ​​and late phase rotation values ​​from 1PRN delay 212A) and the carrier phase values ​​estimated by carrier phase NCO 208, as described above with reference to Figure 2A. The procedure proceeds to step 530 where early code phase values ​​and late code phase values ​​are generated in parallel using the early and late code shift values ​​as described above with reference to Figure 2A. In one embodiment, the late code shift values ​​are early code shift values ​​offset in time by the period of one PRN code chip using 1PRN delay 212B, as described above with reference to Figure 2A.

[0078] The procedure proceeds to step 535, where the early and late code phase values ​​are utilized to generate a final bin enable output 216AB, which may be a vector. Thus, the early and late code phase values ​​span at least 1.5 code chips (e.g., 2 code chips), so that the vector of the final bin enable output spans at least 1.5 code chips (e.g., 2 code chips). The procedure proceeds to step 540, where multiple complex rotated samples (e.g., early complex rotated sample 215A and late complex rotated sample 215B) are accumulated in parallel for a single sample, utilizing the final bin enable output 216AB generated for a window that spans any arbitrary width less than or equal to the number of code chips in the PRN code sequence. For example, the window may span at least 1.5 code chips (e.g., 2 code chips).

[0079] For example, the final bin enable output 216AB may be utilized to accumulate early and late complex rotated samples in parallel within one or two (or none) of a plurality of bins 220 spanning at least 1.5 code chips (e.g., 2 code chips). The plurality of bins 220 may be used to generate correlation values ​​that may be required to implement one or more correlation techniques, and / or one or more multipath mitigation techniques, and / or one or more carrier Doppler frequency estimation techniques.

[0080] Additionally or alternatively, early bin enable output 216A and late bin enable output 216B can be used to accumulate early complex rotated samples 215A and late complex rotated samples 215B in parallel for samples 201 for a window spanning at least 1.5 code chips (2 code chips) using weighting bins 230A and 230B. Weighting bins 230A and 230B can be used to accumulate signals for some predetermined period of time and then can be used to track both the code and carrier of an integrated signal providing a corrected signal for code rate 205 and carrier Doppler frequency 209.

[0081] Thereafter, returning to step 510, procedure 500 is repeated so that multiple complex rotated samples can be generated and accumulated in parallel for the next sample of integrated signal 201.

[0082] 2A-2C, in addition to generating and accumulating an early complex rotated sample and a late complex rotated sample in parallel for each sample 201, one or more embodiments described herein may also sequentially generate and accumulate multiple complex rotated samples 615 (e.g., an early complex rotated sample 215A and / or a late complex rotated sample 215B) for each sample 201. Figure 6A is a schematic block diagram of an integrated signal processing unit 200D that can process an integrated signal by sequentially generating multiple complex rotated samples 615 for one sample 201 of the integrated signal, according to one or more embodiments described herein.

[0083] According to one or more embodiments described herein, samples of an integrated signal 201 synchronized to a sample clock 204 may be processed by sequentially generating multiple complex rotated samples for each sample 201 (e.g., an early complex rotated sample, an on-time complex rotated sample, and a late complex rotated sample), as described in further detail below with reference to FIG. 6A. The complex rotated samples 615 for a sample 201 may be sequentially accumulated in N bins 220 spanning any arbitrary width less than or equal to the number of code chips in the PRN code sequence. For example, the window may span at least 1.5 code chips (e.g., 3 or 10 code chips).

[0084] As an illustrative example, assume that bins 220 of Figure 6A includes 21 bins evenly spaced across a span of three code chips. Further assume that the first seven bins (e.g., bin 0 through bin 6) are "early bins" spanning the first code chip, the second seven bins (e.g., bin 7 through bin 13) are "punctual bins" spanning the second code chip, and the third seven bins (e.g., bin 14 through bin 20) are "lagging bins" spanning the third code chip.

[0085] As described in further detail below, an early complex rotated sample 615 may be generated for the sample 201 and accumulated within one of the multiple bins 220 across three code chips. An on-time complex rotated sample may then be generated for the sample 201 and accumulated within one of the multiple bins 220 across three code chips. A late complex rotated sample may then be generated for the sample 201 and accumulated within one of the multiple bins 220 across three code chips. Thus, according to one or more embodiments described herein, three complex rotated samples for a single sample 201 may be generated and accumulated sequentially within a window spanning three code chips. Although the example of FIG. 6A includes multiple evenly spaced bins 220 that span three code chips, it is expressly contemplated that one or more described embodiments may include multiple bins 220 that are unevenly spaced and span any arbitrary width up to the number of code chips in the PRN code sequence, for example, the multiple bins can span at least 1.5 code chips or more than three code chips (e.g., 10 code chips).

[0086] 6A, the 4×PRN code generator 202 can generate multiple local codes (e.g., PRN codes) that correspond to the codes in the received integrated signal. In one embodiment, the multiple local codes can be an early version of the code in the integrated signal, an on-time version of the code in the integrated signal, and a late version of the code in the integrated signal.

[0087] As mentioned above, the first bit (e.g., the most significant bit) of the four-bit code represents the upper frequency in-phase signal (S UI ) The second bit of the four-bit code corresponds to a lower frequency in-phase signal (S LIThe third bit of the four-bit code corresponds to an upper frequency quadrature signal (S UQ ) The fourth bit (e.g., the least significant bit) of the four-bit code may correspond to a lower frequency quadrature signal (S LQ ) can be accommodated.

[0088] As shown in Fig. 6A, three locally generated codes are provided to the shift table 233. Additionally, as shown in Fig. 6A, a 3x sample clock 222 is provided to the shift table 233. The 3x sample clock 222 is provided so that code shift and phase rotation values ​​can be sequentially selected from the shift / phase lookup table 206 (of the shift table 233) for each of the early, on-time, and late versions of the code for the sample 201, as described in further detail below. Additionally, similar to the initialization of the shift / phase lookup table 206 (of the shift table 233) as described above, the processor 125 of the GNSS receiver 120 can also initialize the shift table 233.

[0089] 7A is a schematic block diagram of a shift table 233 according to one or more embodiments described herein. As shown in FIG. 7A, the 3× sample clock 222 is provided as an input to a counter 601 of the shift table 233. Thus, the counter 601 can sequentially (i.e., consecutively) generate three different values ​​(e.g., 0, 1, and 2) for the samples 201 (of FIG. 6A). Based on the 3× sample clock 222, the counter 601 starts at 0, increments to 1, increments to 2, and then resets back to 0 for the next sample 201 such that three different counter values ​​are sequentially generated for each sample 201.

[0090] The value of the counter 601 may determine which version of the local code (e.g., an early version, an on-time version, or a late version) is provided to the shift / phase lookup table 206 as shown in Figure 7A for the sample 201. For example, when the counter 601 generates a value of 0, the value of 0 is provided as an input to the two-bit encoder 602, which generates a binary value of 00. In response to the generation of the binary value 00 by the two-bit encoder 602, the early version of the local code may be provided to the shift / phase lookup table 206 for the sample 201. Thus, for the early version of the local code, a phase rotation value and a code shift value may be selected from the phase / shift lookup table 206 as described above with reference to Figure 3.

[0091] When counter 601 increments to a value of 1, the value of 1 is provided as an input to 2-bit encoder 602, which generates a binary value of 01. In response to the generation of the binary value 01 by 2-bit encoder 602, an on-time version of the local code may be provided to phase / shift lookup table 206 for sample 201. Thus, for the on-time version of the local code, a phase rotation value and a code shift value may be selected from phase / shift lookup table 206 as described above with reference to FIG.

[0092] When counter 601 increments to a value of 2, the value of 2 is provided as an input to 2-bit encoder 602, which generates a binary value of 10. In response to the generation of the binary value 10 by 2-bit encoder 602, a delayed version of the local code may be provided to phase / shift lookup table 206 for sample 201. Thus, for the delayed version of the local code, a phase rotation value and a code shift value may be selected from phase / shift lookup table 206 as described above with reference to FIG.

[0093] 7A, the output from XOR gate 604 is also provided as an input to phase / shift lookup table 206 to indicate whether the code chip is even or odd, in a manner similar to that described above with reference to FIG. 3. In particular, the output of counter 601, e.g., the least significant bit of the output of counter 601, may be provided to XOR gate 604. Since the bins span three code chips in this embodiment, the least significant bit of counter 601 may be utilized in combination with the least significant bit of chip count 207 to indicate whether the code chip is even or odd. More particularly, the least significant bit of counter 601 and the least significant bit of chip count 207 may be provided to XOR gate 604. To indicate whether the code chip is even or odd, the output of XOR gate 604 may be provided to shift / phase lookup table 206, which may adjust the phase rotation value selected from the shift / phase lookup table by 180 degrees for odd chips, as described above with reference to FIG. 3.

[0094] Thus, three pairs of phase rotation and code shift values ​​for one sample 201 are sequentially generated from the shift / phase lookup table 206 based on three versions of the local code (e.g., an early, an on-time, or a late version of the code). As will be explained in more detail below, in addition to the carrier phase value estimated by the carrier phase NCO 208, the phase rotation value of the selected pair can be utilized to generate a complex rotated sample 615, while the code phase value (B) of the selected pair can be utilized to generate a bin enable output 616, which itself enables one of the multiple bins 220 spanning three code chips.

[0095] In particular, the respective code phase value (B) of each pair may be provided from the shift / phase lookup table 206 to an adder 210F of a sample enable decoder 613 as shown in Figure 7B, which is a schematic block diagram of the sample enable decoder 613 according to one or more embodiments described herein. Additionally, the value (A) from the counter 601 may be combined as the two most significant bits with a code phase sub-chip value provided by the code phase NCO 203 and representing a time slot in code chips for the sample 201. The value of the counter 601 may be combined as the two most significant bits to offset the selected code phase in time as necessary.

[0096] When the counter 601 has a value of zero and an early version of the local code is provided to the shift / phase lookup table 206, "00" (representing a value of zero) is paired as the two most significant bits of the code phase sub-chip value. Because "00" is paired as the two most significant bits, the selected code shift value (of the pair corresponding to the early version of the code) is not offset in time when the adder 210F of the sample enable decoder 613 adds the code phase sub-chip value to the selected code shift value. The output of the adder 210F may be an early sample code phase value.

[0097] When the counter has a value of one and an on-time version of the local code is provided to the shift / phase lookup table 206, a "01" (representing a value of one) is paired as the two most significant bits of the code phase sub-chip value. Because a "01" is paired as the two most significant bits, the selected code shift value (of the pair corresponding to the on-time version of the code) is offset in time by one PRN chip's worth of code phase (i.e., for the second code chip of a window spanning three code chips) when the adder 210F of the sample enable decoder 613 adds the combined value to the selected shift phase value. The output of the adder 210F may be the on-time sampled code phase value.

[0098] When the counter has a value of 2 and a delayed version of the local code is provided to the shift / phase lookup table 206, a "10" is paired as the two most significant bits of the code phase sub-chip value. Because a "10" is paired as the two most significant bits, the selected code shift value (of the pair corresponding to the delayed version of the code) is offset in time by 2 PRN chips worth of code phase (i.e., for the third code chip of a window spanning three code chips) when the adder 210F of the sample enable decoder 613 adds the combined value to the selected code shift value. The output of the adder 210F may be a delayed sample code phase value.

[0099] As discussed above with reference to FIG. 4, the sample code phase values ​​(e.g., the early code phase value, the on-time code phase value, and the late code phase value) may be utilized by each of the multiple comparators 405 of the sample enable decoder 613 of FIG. 7B to sequentially determine which bins of the multiple bins 220 across the three code chips are enabled. In one implementation, the sample code phase values ​​(e.g., the early code phase value, the on-time code phase value, and the late code phase value) may enable an early bin, e.g., one of bins 0-6, if the sample code phase value is less than 1.0. In one implementation, the sample code phase values ​​(e.g., the early code phase value, the on-time code phase value, and the late code phase value) may enable one of the on-time bins, e.g., bins 7-13, if the sample code phase value is greater than 1.0 and less than 2.0. In one implementation, a sample code phase value (e.g., an early code phase value, an on-time code phase value, and a late code phase value) may enable one of the late bins, e.g., bins 8 through 20, if the sample code phase value is greater than 2.0.

[0100] In particular, the early sample code phase value is available to each of the 21 comparators 405, which each generate one bit of a bin enable output 616 (e.g., a vector of 0's and 1's), as described above with reference to signal 216A in Figure 4. The bin enable outputs 616 may be utilized to enable bins such that early complex rotated samples generated for sample 201 as described below are accumulated in the enabled bins.

[0101] Similarly, the on-time sample code phase value is available to each of the 21 comparators 405, each of which generates one bit of a bin enable output 616 (e.g., a vector of 0's and 1's) as described above with reference to signal 216B of FIG. 4. The bin enable output 616 may again be used to enable a bin so that the on-time complex rotated samples generated for sample 201 as described below are accumulated in the enabled bins. Additionally, the late sample code phase value is available to each of the 21 comparators 405, each of which generates one bit of a bin enable output 616 (e.g., a vector of 0's and 1's) as described above. The bin enable output 616 may again be used to enable a bin so that the late complex rotated samples generated for sample 201 as described below are accumulated in the enabled bins.

[0102] Returning to Figure 6A, based on each version of the local code for sample 201, a phase rotation value and a bin enable output 616 are sequentially provided as outputs from shift table 233. In the case of an early version of the code, a phase rotation value generated from shift / phase lookup table 206 and an early bin enable output 616 are provided as outputs from shift table 233. In the case of an on-time version of the code, a phase rotation value generated from shift / phase lookup table 206 and an on-time bin enable output 616 are provided as outputs from shift table 233. In the case of a late version of the code, a phase rotation value generated from shift / phase lookup table 206 and a late bin enable output 616 are provided as outputs from shift table 233.

[0103] The bin enable outputs (e.g., an early bin enable output, an on-time enable output, and a late bin enable output) can be provided sequentially from an enabler 410B (of the shift table 233 of FIG. 7B) to form a bin enable output 616, which is connected to the bins 220 of FIG. 6A to sequentially enable the bins as described above with reference to FIG. 2A. In particular, the enabler 655 receives as inputs the 3× sample clock 222 and an enable signal from the counter 601, such that the enabler 655 provides a signal (C) to the enabler 410B, which sequentially provides the bin enable outputs 616 (e.g., three values ​​corresponding to an early bin enable output, an on-time enable output, and a late bin enable output) to sequentially enable three of the bins 220 across three code chips for a single sample 201.

[0104] The respective phase rotation values ​​output from the shift table 233 may be utilized to generate complex rotated samples 615. In particular, to remove the Doppler effect as described above with reference to FIG. 2A, the respective phase rotation values ​​may be provided to a summer 210A along with the carrier phase values ​​estimated by the carrier phase NCO 208. The results of this addition may be provided to a complex mixer 211A to be mixed with the samples 201 (e.g., multi-bit I and Q samples) to obtain the complex rotated samples 615 as described above with reference to signals 215A and 216B of FIG. 2A.

[0105] For example, phase rotation values ​​generated based on an early version of the code can be used to generate early complex rotated samples 615 with respect to sample 201. Phase rotation values ​​generated based on an on-time version of the code can be used to generate on-time complex rotated samples 615 with respect to sample 201. Phase rotation values ​​generated based on a late version of the code can be used to generate late complex rotated samples 615 with respect to sample 201.

[0106] Thus, the integral signal processing unit 200D can sequentially generate multiple complex rotated samples for a single sample 201, and can sequentially accumulate these complex rotated samples in multiple bins 220 across three code chips. In particular, the generated early complex rotated samples can be accumulated in bins of the multiple bins 220 across three code chips that are enabled based on the early bin enable data in the bin enable output 616. The generated on-time complex rotated samples can then be accumulated in bins of the multiple bins 220 across three code chips that are enabled based on the on-time bin enable data in the bin enable output 616. The generated late complex rotated samples can then be accumulated in bins of the multiple bins 220 across three code chips that are enabled based on the late bin enable data in the bin enable output 616. Thus, the early complex rotated samples, the on-time complex rotated samples, and the late complex rotated samples generated for a single sample 201 can be sequentially generated and accumulated in enabled bins across three code chips in accordance with one or more embodiments described herein.

[0107] More generally, each bin 220 may be represented by the following formula:

number

number

[0108] Thus, according to one or more embodiments described herein, multiple samples of an integrated signal synchronized to a sample clock 204 can be processed by sequentially generating an early complex rotated sample, an on-time complex rotated sample, and a late complex rotated sample for each sample 201, and accumulating these complex rotated samples into multiple bins 220 spanning three code chips. The GNSS receiver 120 can use the complex rotated samples accumulated in selected bins 220 and / or in selected groups of bins 220 to generate correlation values ​​that may be needed to perform one or more correlation techniques, and / or one or more multipath mitigation techniques, and / or carrier Doppler frequency estimation techniques.

[0109] Additionally, the complex rotated samples may be utilized to calculate correlation measurements, for example, utilizing weighted bins 630A and 630B.

[0110] In particular, the weighting bin 630A can store a weighting vector that can be utilized to generate a P signal that can be utilized for tracking. In one implementation, ik of,

number

number

[0111] So in this example with 21 bins, w p may be a vector of length 21, and w p Each weight value in can correspond to a different bin. For example, w p The first value in (W b1 ) may be the weight for bin 0, and w p The second value in (W b2 ) may be the weight for bin 1, and so on. p The weights in can be based on a variety of factors, including, but not limited to, the particular type of integrated signal (e.g., an ACE-BOC Type I signal, an ACE-BOC Type II signal, or an ACE-BOC Type III signal), the power ratio of the integrated signals, the implementation of the integrated signal, etc. i The values ​​can be summed to generate the P signal.

[0112] 6A can store a weighting vector that can be utilized to generate an EL signal that can be utilized for tracking. ik of,

number

number

[0113] So in this example with 21 bins, w E-L may be a vector of length 21, and w E-L Each weight value in can correspond to a different bin. For example, w E-L The first value in (W b1 ) may be the weight for bin 0, and w E-L The second value in (W b2 ) may be the weight for bin 1, and so on. E-LThe weights in EL can be based on a variety of factors, including, but not limited to, the particular type of integrated signal (e.g., an ACE-BOC type I signal, an ACE-BOC type II signal, or an ACE-BOC type III signal), the power ratio of the integrated signals, the implementation of the integrated signal, etc. i The values ​​can be summed to generate the EL signal.

[0114] The P signal and / or the EL signal are available to the code tracking loop 253 and the carrier tracking loop 254 as described above with reference to FIG. 2A.

[0115] FIG. 6B is a schematic block diagram of an integral signal processing unit 200E that can process an integrated signal by sequentially generating multiple complex rotated samples for one sample of the integrated signal, according to one or more embodiments described herein. FIG. 6B is similar to FIG. 6A, but the integral signal processing unit 200E does not include bins 220. Thus, as shown in FIG. 6B, multiple complex rotated samples (e.g., an early complex rotated sample, an on-time complex rotated sample, and a late complex rotated sample) generated consecutively for sample 201 are provided to both weighting bins 630A and 630B to track the integrated signal as described above. Although the integral signal processing unit 200E of FIG. 6B does not include bins 220, the weighting bins 630A and 630B can be utilized to sequentially formulate multiple complex rotated sample vectors (e.g., a late complex rotated sample, an on-time complex rotated sample, and a late complex rotated sample) to generate a P accumulation signal and an EL accumulation signal, as described above with reference to FIG. 6A. The P and EL accumulation signals are fed to a tracking module 252 to track the integrated signal. Error can be calculated and / or the tracking module 252 can utilize the timed signal to generate a new estimate of the carrier Doppler frequency 209, as described above with reference to FIG. 2A.

[0116] FIG. 6C is a schematic block diagram of an integral signal processing unit 200F that can process an integrated signal by sequentially generating multiple complex rotated samples 615 for one sample of the integrated signal according to one or more embodiments described herein. FIG. 6C is similar to FIG. 6A, but the integral signal processing unit 200F does not include weighting bins 630A and 630B and summers 242 and 244. Thus, the integral signal processing unit 200F of FIG. 6C can sequentially generate and accumulate early complex rotated samples, on-time complex rotated samples, and late complex rotated samples 615 for a single sample 201 in selected bins 220 and / or selected groups of bins 220, as described above with reference to FIG. 6A. The bins 220 can be used to generate correlation values ​​that may be required to perform one or more correlation techniques, and / or one or more multipath mitigation techniques, and / or carrier Doppler frequency estimation techniques.

[0117] 8 is an example flow chart for processing an integrated signal by sequentially generating multiple complex rotated samples for one sample of the integrated signal, according to one or more embodiments described herein. The procedure 800 starts at step 805 and proceeds to step 810 where an integrated signal is received at a GNSS antenna. In one embodiment, the integrated signal may be based on ACE-BOC multiplexing and may have multiple signal components with arbitrary power allocation.

[0118] The procedure proceeds to step 815 where multiple local codes (PRN codes) are generated for the samples 201 of the integrated signal, where the local codes correspond to the codes in the received integrated signal. In one implementation, the local codes may be an early version of the code in the integrated signal, an on-time version of the code in the integrated signal, and a late version of the code in the integrated signal.

[0119] The procedure proceeds to step 820 where one local code of the plurality of local codes is provided to the shift / phase lookup table 206. For example, referring to Figure 6A, a counter value of 0 is generated by counter 601, which causes a leading version of the code for sample 201 to be provided to shift / phase lookup table 206.

[0120] The procedure proceeds to step 825 where phase rotation and code shift values ​​are selected based on the provided local code, as described above with reference to Figures 6A, 7A, and 7B. The procedure proceeds to step 830 where complex rotated samples are generated using the selected phase rotation values ​​and the carrier phase values ​​estimated by the carrier phase NCO 208. For example, the leading complex rotated samples may be generated using phase rotation values ​​selected based on a leading version of the code, as described above with reference to Figures 6A, 7A, and 7B.

[0121] The procedure proceeds to step 835 where a code phase value is generated based on the selected code shift value by offsetting in time the selected code shift value based on the value of the counter such that the window spans any arbitrary width less than or equal to the number of code chips in the PRN code sequence. For example, the window may span at least 1.5 code chips (e.g., 3 code chips or 10 code chips). For example, the code shift value selected based on the early version of the code should not be offset in time since the counter has a value of 0. Thus, the selected code shift value may be added to the code phase sub-chip value to generate an early code phase value. However, as discussed above with reference to Figures 6A, 7A, and 7B, the code shift value selected based on the late version of the code may be offset in time by the equivalent of 2 PRN chips of the code phase since the counter has a value of 2. Thus, a "10" is combined as the two most significant bits of the code phase sub-chip value, and this combined value is added with the selected code shift value to generate a late code phase value.

[0122] The procedure proceeds to step 840 where, based on the code phase value, the bin enable output 616 is generated. For example, the leading code phase value may be utilized to determine the leading bin enable output 616, as described above with reference to Figures 6A, 7A, and 7B.

[0123] The procedure proceeds to step 845, where complex rotated samples 615 are accumulated for a single sample using the bin enable output 616 for a window spanning any arbitrary width less than or equal to the number of code chips in the PRN code sequence. For example, the window can span at least 1.5 code chips (e.g., 3 code chips or 10 code chips). For example, the complex rotated samples 615 can be accumulated in one of the plurality of bins 220 spanning at least 1.5 code chips (e.g., 3 code chips or 10 code chips) using the bin enable output 616. Additionally or alternatively, the complex rotated samples can be accumulated using the weighting bins 630A and 630B using the bin enable output 616 for a window spanning at least 1.5 code chips (e.g., 3 code chips). Weighting bins 630A and 630B can be used to accumulate the signal for some predetermined period of time and then track both the code and carrier of the integrated signal providing a corrected signal for code rate 205 and carrier Doppler frequency 209.

[0124] The procedure proceeds to step 850, where it is determined whether the counter has reached its limit. If not, the counter is incremented in step 855, after which the procedure returns to 820, whereby the integral signal processing unit (e.g., 200D-F) can sequentially generate multiple complex rotated samples 615 for the sample 201. For example, the procedure can return to step 820 to generate and accumulate on-time complex rotated samples based on code shift and phase rotation values ​​selected based on the on-time version of the code described above. The procedure can then return to step 820 again to generate and accumulate delayed complex rotated samples based on code shift and phase rotation values ​​selected based on the delayed version of the code described above. Thus, for a window that spans any arbitrary width less than or equal to the number of code chips in the PRN code sequence, e.g., at least 1.5 code chips (3 code chips or 10 code chips), an advanced complex rotated sample, an on-time complex rotated sample, and a delayed complex rotated sample are sequentially generated and accumulated for a single sample 201.

[0125] When the counter reaches its limit in step 850, the counter can be reset in step 860 and the procedure can return to step 810, thereby sequentially generating and accumulating multiple complex rotated samples (e.g., an early complex rotated sample, an on-time complex rotated sample, and a late complex rotated sample) for the next sample 201.

[0126] Advantageously, the GNSS receiver 120 can use the sequentially generated and accumulated complex rotated samples 615 within selected bins 220 and / or selected groups of bins 220 to generate correlation values ​​that may be required to perform one or more correlation techniques, and / or one or more multipath mitigation techniques, and / or carrier Doppler frequency estimation techniques. Additionally or alternatively, the sequentially generated complex rotated samples 615 can be used by weighting bins 630A and 630B to generate correlation values ​​that can be utilized to track the integrated signal.

[0127] The foregoing description of each embodiment is intended to provide illustration and description, but is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Modifications and variations are possible in light of the above teachings or may be acquired from practice of the present disclosure. For example, although a sequence of actions has been described above with reference to a flowchart, in other implementations, the order of these actions may be changed. Furthermore, the actions, operations, and steps may be performed by additional or other modules or entities, and these additional or other modules or entities may be combined or separated to form other modules or entities. Furthermore, multiple actions that are not dependent on one another may be performed in parallel. Furthermore, certain embodiments described herein may be implemented as logic that performs one or more functions. This logic may be hardware-based, software-based, or a combination of hardware-based and software-based. Some or all of the logic may be stored in one or more tangible, non-transitory computer-readable storage media, and the logic may include computer-executable instructions that can be executed by a computer. The computer-executable instructions may include instructions that implement one or more embodiments described herein. The tangible non-transitory computer readable storage medium may be volatile or non-volatile and may include, for example, flash memory, dynamic memory, removable disks, and non-removable disks. It should be understood, among other things, that the above description is intended to be interpreted as merely an example.

Claims

1. A navigation receiver configured to process an integrated signal received by an antenna, the integrated signal being based on asymmetric multiplexing: for the integrated signal having a plurality of signal components with arbitrary power allocation among the plurality of signal components, the navigation receiver includes an integrated signal processing unit implemented by a processor; The integral signal processing unit includes: generating at least one local code for samples of the integrated signal; selecting a phase rotation value and a code shift value for each local code of the at least one local code; generating one or more complex rotated samples for the samples based on the phase rotation values; Using the code shift value to determine one or more time slots of a plurality of time slots in a window spanning at least a portion of a pseudorandom noise (PRN) period of the integrated signal. It is configured as follows: Navigation receiver.

2. The integral signal processing unit includes: utilizing the code shift value to enable one or more bins of a plurality of bins spanning the portion of the PRN period; accumulating one or more of the complex rotated samples into one or more of the enabled bins It is further structured as follows: one or more of the bins correspond to one or more of the time slots, and a plurality of the bins correspond to a plurality of the time slots; the accumulated complex rotated samples in the bins for the different samples of the integrated signal are utilized by the navigation receiver to implement at least one of: (1) one or more correlation techniques; (2) one or more multipath mitigation techniques; and (3) one or more carrier Doppler frequency estimation techniques.

2. The navigation receiver of claim 1.

3. The integral signal processing unit includes: Utilizing one or more weighting vectors along with at least the one or more complex rotated samples to generate at least one of an on-time signal and an early minus late signal. It is further structured as follows: the on-time signal and the lead-minus-lag signal are utilized to track the integral signal; 2. The navigation receiver of claim 1.

4. 2. The navigation receiver of claim 1, wherein the asymmetric multiplexing is an asymmetric constant envelope binary offset carrier (ACE-BOC) multiplexing.

5. 2. The navigation receiver of claim 1, wherein the at least one local code corresponds to one or more of: (1) an early version of a code in the integrated signal; (2) an on-time version of a code in the integrated signal; and (3) a late version of a code in the integrated signal.

6. the at least one local code is a single local code; the one or more complex rotated samples include an early complex rotated sample and a late complex rotated sample generated in parallel.

2. The navigation receiver of claim 1.

7. the at least one local code includes three local codes; the one or more complex rotated samples include a sequentially generated early complex rotated sample, an on-time complex rotated sample, and a late complex rotated sample.

2. The navigation receiver of claim 1.

8. 1. A method for processing an integrated signal received at an antenna, comprising the steps of: the integrated signal has a plurality of signal components having arbitrary power allocations; The integrated signal is based on asymmetric multiplexing, The method comprises: generating at least one local code for samples of the integrated signal; selecting a phase rotation value and a code shift value for each local code of the at least one local code; generating one or more complex rotated samples for the samples based on the phase rotation values; using the code shift value to determine one or more time slots of a plurality of time slots in a window spanning at least a portion of a pseudorandom noise (PRN) period of the integrated signal; Including, method.

9. The method comprises: utilizing the code shift value to enable one or more bins of a plurality of bins spanning the portion of the PRN period; accumulating one or more of the complex rotated samples into one or more of the enabled bins; Further comprising: one or more of the bins correspond to one or more of the time slots, and a plurality of the bins correspond to a plurality of the time slots; the accumulated complex rotated samples in the bins for the different samples of the integrated signal are utilized by a navigation receiver to implement at least one of: (1) one or more correlation techniques; (2) one or more multipath mitigation techniques; and (3) one or more carrier Doppler frequency estimation techniques. The method of claim 8.

10. The method comprises: utilizing one or more weighting vectors in conjunction with at least the one or more complex rotated samples to generate at least one of an on-time signal and an early-minus-late signal. Further comprising: the on-time signal and the lead-minus-lag signal are utilized to track the integral signal; The method of claim 8.

11. 9. The method according to claim 8, wherein the asymmetric multiplexing is ACE-BOC (Asymmetric Constant Envelope Binary Offset Carrier) multiplexing.

12. 9. The method of claim 8, wherein the at least one local code corresponds to one or more of: (1) an early version of a code in the integrated signal; (2) an on-time version of a code in the integrated signal; and (3) a late version of a code in the integrated signal.

13. the at least one local code is a single local code; the one or more complex rotated samples include an early complex rotated sample and a late complex rotated sample generated in parallel. The method of claim 8.

14. the at least one local code includes three local codes; the one or more complex rotated samples include a sequentially generated early complex rotated sample, an on-time complex rotated sample, and a late complex rotated sample. The method of claim 8.

15. 9. The method of claim 8, wherein a number of the one or more complex rotated samples generated for the sample is equal to N, where N is less than or equal to a number of PRN code chips in the PRN period of the integrated signal.

16. A navigation receiver configured to process an integrated signal received by an antenna, the integrated signal being based on asymmetric multiplexing: for the integrated signal having a plurality of signal components with arbitrary power allocation among the plurality of signal components, the navigation receiver includes an integrated signal processing unit implemented by a processor; The integral signal processing unit includes: generating at least one local code for samples of the integrated signal; selecting a phase rotation value and a code shift value for each local code of the at least one local code; generating one or more complex rotated samples for the samples based on the phase rotation values; accumulating the one or more complex rotated samples into one or more bins of a plurality of bins. It is structured as follows: one or more of the bins are enabled using the code shift value; the plurality of bins span a window of any arbitrary width less than or equal to the number of code chips in a pseudorandom noise (PRN) code sequence of the integrated signal; Navigation receiver.

17. 17. The navigation receiver of claim 16, wherein the asymmetric multiplexing is an asymmetric constant envelope binary offset carrier (ACE-BOC) multiplexing.

18. 17. The navigation receiver of claim 16, wherein the accumulated complex rotated samples accumulated in the plurality of bins are utilized by the navigation receiver to implement at least one of: (1) one or more correlation techniques, (2) one or more multipath mitigation techniques, and (3) one or more carrier Doppler frequency estimation techniques.

19. 17. The navigation receiver of claim 16, wherein the accumulated complex rotated samples accumulated in the plurality of bins are utilized by the navigation receiver to track the integrated signal.

20. the at least one local code is a single local code, and the one or more complex rotated samples include early complex rotated samples and late complex rotated samples generated in parallel; or or the at least one local code includes three local codes, and the one or more complex rotated samples include a leading complex rotated sample, an on-time complex rotated sample, and a lagging complex rotated sample, which are generated sequentially.

17. The navigation receiver of claim 16.

Images