Calculation device, arbitrage trading system, calculation system, calculation method, program, and circuit information

Abstract

To output a solution of an optimization problem at high speed.SOLUTION: A search device updates respective positions and momentum of a plurality of virtual particles, for each unit time from initial time to end time. The search device, for each unit time, calculates, for each of the plurality of particles, a position at the target time of a corresponding particle, calculates, for each of a plurality of nodes, a first accumulative value by cumulatively adding positions at the target time of two or more particles corresponding to outgoing two or more directed edges, calculates, for each of the plurality of nodes, a second accumulative value by cumulatively adding positions at the target time of two or more particles corresponding to incoming two or more directed edges, and calculates, for each of the plurality of particles, a momentum at the target time of the corresponding particle on the basis of the first accumulative value and the second accumulative value.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present invention relates to a computing system, a computing method, a program, and circuit information. [Background technology]

[0002] Many of the challenges in improving the productivity of social systems can be reduced to combinatorial optimization problems. In a graph consisting of nodes (vertices) and directed edges (sides) connecting the nodes, the problem of selecting a route connecting a start node and an end node based on some evaluation function is called a path search problem. For example, an arbitrage trading problem that detects arbitrage trading opportunities such as foreign exchange is formulated as a path search problem in a directed graph. In this case, in the directed graph, the nodes correspond to currencies, the directed edges correspond to exchanges from the currency corresponding to the start node to the currency corresponding to the end node, and the weight value assigned to the directed edge corresponds to the exchange rate of the currencies.

[0003] The Ising problem, which calculates the ground state of the Ising model, is also known. The Ising problem is a combinatorial optimization problem that minimizes a cost function (Ising energy) given by a quadratic function of a variable (Ising spin) that takes two values, ±1.

[0004] The Ising problem can be expressed by an equation using bits (b) by converting the Ising spin (s) into a linear relational equation (s = 2b-1). b is a binary variable of 0 or 1. In other words, the Ising problem is the same as the problem of minimizing a cost function expressed by a quadratic function using bits (b). This type of problem is called a QUBO (quadratic unconstrained binary optimization) problem. It is known that the arbitrage trading problem can be formulated as a QUBO problem.

[0005] However, there is a demand for a device that can quickly solve such optimization problems. For example, a device is required that can quickly detect an arbitrage opportunity by detecting a closed path (a path in which the start node and end node are the same) that maximizes the gain (exchange gain) obtained as a result of the exchange from a directed graph that formulates the arbitrage problem. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Patent No. 5865456 [Patent Document 2] JP 2018-005541 A [Patent Document 3] JP 2018-010474 A [Non-patent literature]

[0007] [Non-Patent Document 1] Hayato Goto, Kosuke Tatsumura, Alexander R. Dixon, “Combinatorial optimization by simulating adiabatic bifurcations in nonlinear Hamiltonian systems”, Science Advances, Vol. 5, no. 4, eaav2372, 19 Apr. 2019 [Non-Patent Document 2] Soon Wanmei, and Heng-Qing Ye, "Currency arbitrage detection using a binary integer programming model", International Journal of Mathematical Education in Science and Technology,Volume 42, Issue 4, 369-376, 29 Nov. 2010 [Non-Patent Document 3] Gili Rosenberg, "Finding optimal arbitrage opportunities using a quantum annealer" 1QB Information Technologies Write Paper, 2016 [Non-Patent Document 4] MW Johnson et al., “Quantum annealing with manufactured spins”, Nature 473, 194-198, 11 May. 2011 Summary of the Invention [Problem to be solved by the invention]

[0008] The problem to be solved by the invention is to quickly output a solution to an optimization problem. [Means for solving the problem]

[0009] In accordance with an embodiment A computing device solves a quadratic unconstrained binary optimization (QUBO) problem that is formulated as a composite cost function using multiple binary variables, including a cost function and a penalty function based on constraint conditions. The computing device stores multiple position variables corresponding to the multiple binary variables, multiple momentum variables corresponding to the multiple binary variables, and multiple coefficients included in the composite cost function. The computing device updates the multiple position variables and the multiple momentum variables from an initial time to an end time. After reaching the end time, the computing device determines whether the multiple position variables satisfy the constraint conditions. The computing device binarizes each of the multiple position variables at the end time and outputs the binarized result as a solution to the multiple binary variables in the QUBO problem. In updating the plurality of position variables and the plurality of momentum variables, the computing device updates, for each of the plurality of binary variables, a corresponding position variable among the plurality of position variables according to a corresponding momentum variable among the plurality of momentum variables, updates, for each of the plurality of binary variables, a corresponding momentum variable among the plurality of momentum variables according to a corresponding coefficient among the plurality of position variables and the plurality of coefficients, determines whether the constraint condition is satisfied using the binarized plurality of position variables, and outputs a determination result. [Brief description of the drawings]

[0010] [Figure 1] A diagram showing a directed graph. [Diagram 2] 1A and 1B are diagrams for explaining matrices in which values ​​and variables corresponding to directed edges are stored; [Diagram 3] FIG. 1 illustrates a directed graph with weight values ​​assigned to directed edges. [Figure 4] FIG. 1 illustrates a directed graph in which bits are associated with directed edges. [Diagram 5] FIG. 1 is a diagram showing the configuration of a searching device according to a first embodiment. [Figure 6] 4 is a flowchart showing a flow of processing of the searching device according to the first embodiment. [Figure 7] FIG. 11 is a diagram showing the circuit configuration of a searching device according to a second embodiment. [Figure 8] FIG. 2 is a diagram showing a memory configuration. [Figure 9]11 is a flowchart showing a flow of processing by a searching device. [Figure 10] FIG. 1 is a diagram showing variables and values ​​input and output to a TE circuit. [Figure 11] FIG. 1 shows variables input to and output from a GC circuit. [Figure 12] A diagram showing variables and values ​​input and output to a CC circuit. [Figure 13] A diagram showing variables and values ​​input and output to an MX circuit. [Figure 14] A diagram showing the order in which variables and values ​​are read by the TE circuit. [Figure 15] A diagram showing the order in which variables and values ​​are read by the MX circuit. [Figure 16] FIG. 1 is a diagram showing the timing of TE processing, MX processing, and GC processing. [Figure 17] FIG. 1 shows the configuration of a TE circuit. [Figure 18] FIG. 1 shows the configuration of a GC circuit. [Figure 19] FIG. 13 is a diagram showing the order in which position variables are acquired by the GC circuit. [Figure 20] A diagram showing the configuration of an MX circuit. [Figure 21] FIG. 4 is a diagram showing the configuration of a normalization circuit. [Figure 22] FIG. 2 shows the configuration of a CC circuit. [Figure 23] FIG. 1 shows the first main pseudocode. [Figure 24] FIG. 2 shows the second main pseudocode. [Diagram 25] FIG. 1 shows TE pseudocode. [Figure 26] A diagram showing MX pseudocode. [Figure 27] A diagram showing a paralleled TE circuit. [Figure 28] A diagram showing a paralleled MX circuit. [Figure 29] FIG. 1 shows the configuration of a parallel GC circuit. [Diagram 30] FIG. 13 is a diagram showing the order in which position variables are acquired by a parallelized GC circuit. [Diagram 31] FIG. 13 is a diagram showing the timing of TE processing and MX processing before and after parallelization. [Diagram 32] FIG. 1 is a diagram showing the configuration of an arbitrage trading system. [Diagram 33] FIG. 2 is a diagram showing a configuration of an input management device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] (First embodiment) An optimal route problem and a method for solving the problem according to the first embodiment will be described.

[0012] (Premise) FIG. 1 is a diagram illustrating a directed graph.

[0013] The directed graph for which a path is searched includes a plurality of nodes and a plurality of directed edges. A unique index is assigned to each of the plurality of nodes. The index is an integer equal to or greater than 1. When the directed graph includes N nodes (N is an integer equal to or greater than 3), each of the plurality of nodes is assigned a unique integer between 1 and N. Note that the example in FIG. 1 shows a directed graph with N=4.

[0014] Each of the multiple directed edges has a direction and represents a path that starts from one of the multiple nodes (start node) and goes to another of the multiple nodes (end node). In this embodiment, the start node and end node of each directed edge are different. That is, in this embodiment, the directed edges do not include edges (self-loops) whose start node and end node are the same.

[0015] In the embodiment, a directed edge that goes out from an i-th node (i is an integer equal to or greater than 1 and equal to or less than N) and goes into a j-th node (j is an integer equal to or greater than 1 and equal to or less than N, and is a value different from i) is defined as e i,j In the embodiment, various values ​​and variables are handled in association with directed edges. Similarly, these values ​​and variables are identified with corresponding directed edges by subscripts.

[0016] FIG. 2 is a diagram for explaining an N×N matrix in which values ​​and variables corresponding to directed edges are stored.

[0017] In the embodiment, when the number of nodes included in the directed graph is N, these values ​​and variables are stored in a matrix of N rows by N columns. In the embodiment, the row number of the matrix represents the index of the start node of the corresponding directed edge, and the column number represents the index of the end node of the corresponding directed edge. However, since the directed edge does not include a self-loop, the matrix stores values ​​that do not affect the path search as elements of the diagonal components (components with the same row and column numbers). The example in FIG. 2 shows a matrix when N=4.

[0018] In addition, in the matrix, the row number may represent the index of the end node of the corresponding directed edge, and the column number may represent the index of the start node of the corresponding directed edge.

[0019] FIG. 3 is a diagram showing a directed graph in which weight values ​​are assigned to directed edges.

[0020] Each of the directed edges in a directed graph is assigned a weight value. If the directed graph contains N nodes, the weight value assigned to the directed edge going out of the i-th node and going into the j-th node is w i,j This is expressed as:

[0021] One of the optimal path problems is to find the shortest path through a directed graph. The solution to the shortest path problem is the path that has the smallest sum of the weights assigned to the two or more directed edges it contains.

[0022] The optimal path problem also includes the problem of finding the longest path, the problem of finding the minimum gain path, and the problem of finding the maximum gain path. The solution to the problem of finding the longest path is the path for which the sum of the inverses of the weights assigned to the two or more directed edges included is the smallest. The solution to the problem of finding the minimum gain path is the path for which the sum of the logarithms of the weights assigned to the two or more directed edges included is the smallest. The solution to the problem of finding the maximum gain path is the path for which the sum of the logarithms of the inverses of the weights assigned to the two or more directed edges included is the smallest. In other words, the longest path problem, the minimum gain path problem, and the maximum gain path problem can be solved as shortest path problems.

[0023] For example, consider the arbitrage problem of detecting arbitrage opportunities in foreign exchange. In this case, in a directed graph, nodes correspond to currencies, and directed edges correspond to exchanges from the currency of the start node to the currency of the end node. The weight value assigned to a directed edge that exits from the i-th node and enters the j-th node is expressed as in Equation (1) below.

[0024]

number

[0025] In formula (1), r i,j represents the exchange rate from the currency of the start node (i-th node) to the currency of the next node (j-th node).

[0026] In such a directed graph, the closed circuit with the smallest sum of weights assigned to two or more directed edges represents the closed circuit with the largest total rate. Therefore, the solution of the shortest path problem in such a directed graph corresponds to the solution of the arbitrage problem, which detects opportunities for foreign exchange arbitrage trading.

[0027] Also, for example, in the case of the problem of finding the shortest distance, in a directed graph, nodes correspond to points, and the weight value assigned to a directed edge represents the distance from the point of the start node to the point of the end node. In this case, the weight value is a positive value. In addition, in this case, the weight value assigned to a directed edge that exits from the i-th node and enters the j-th node is the same as the weight value assigned to a directed edge that exits from the j-th node and enters the i-th node. In other words, such a directed graph can be regarded as an undirected graph. Therefore, the problem of finding the shortest distance in an undirected graph can be solved as a shortest path problem in a directed graph.

[0028] (Problems about cycles) There are two types of optimal path problems: problems related to closed paths (loop-shaped paths) and problems related to paths connecting two different nodes. First, we explain problems related to closed paths, and then we explain problems related to paths connecting two different nodes.

[0029] 4 is a diagram showing a directed graph in which bits are associated with directed edges. The optimal path problem for a directed graph can be formulated as a 0-1 optimization problem.

[0030] When the optimal path problem of a directed graph is formulated as a 0-1 optimization problem, a bit is assigned to each of the directed edges. That is, the bits included in the 0-1 optimization problem correspond to the directed edges included in the directed graph. In this embodiment, the bit assigned to the directed edge going out from the i-th node and going into the j-th node is b i,j This is expressed as:

[0031] Furthermore, each of the multiple bits included in the 0-1 optimization problem represents whether or not the corresponding directed edge has been selected as the optimal path. In this embodiment, each of the multiple bits represents that the corresponding directed edge has been selected as the optimal path when it is 1, and represents that the corresponding directed edge has not been selected as the optimal path when it is 0. For example, in the case of an arbitrage problem, each of the multiple bits represents that an exchange is made from the currency of the start node to the currency of the end node when it is 1, and represents that an exchange is not made from the currency of the start node to the currency of the end node when it is 0.

[0032] When the optimal path problem of a directed graph is formulated as a 0-1 optimization problem, the equation to be minimized is expressed by the following equation (2).

[0033] E=M C ×C+M P ×P…(2)

[0034] C is a cost function that uses multiple bits to represent the sum of weights assigned to two or more directed edges included in the selected path. P is a penalty function that uses multiple bits to represent the constraints that satisfy the optimal path. M C and M. P is a predetermined positive constant. That is, the 0-1 optimization problem is formulated into a composite cost function E including a cost function C and a penalty function P.

[0035] In this embodiment, the cost function C is expressed as the following equation (3).

[0036]

number

[0037] Equation (3) expresses the sum (cumulative sum) of the weights assigned to two or more directed edges included in the selected path using multiple bits. Equation (3) expresses w for all combinations of i and j except when i=j. i,j ×b i,jThis is an equation that adds up all of the above.

[0038] In problems related to cycles, the penalty function P uses multiple bits to express the conditions under which a selected path forms a cycle in a directed graph. The conditions for forming a cycle in a directed graph are as follows:

[0039] The first condition is that each of the N nodes has one or less outgoing directed edges selected for the optimal path.

[0040] The second condition is that each of the N nodes has no more than one incoming directed edge selected for the optimal path.

[0041] The third condition is that for each of the N nodes, the number of outgoing directed edges selected for the optimal path is the same as the number of incoming directed edges selected for the optimal path.

[0042] The fourth condition is that a directed edge exiting the i-th node and entering the j-th node and a directed edge exiting the j-th node and entering the i-th node are not simultaneously selected as the optimal path.

[0043] A penalty function P that expresses the above conditions using a plurality of bits is expressed as in the following equation (4).

[0044]

number

[0045] The first term on the right side of equation (4) is b for all combinations of j and j' other than j=j' for any i. i,j ×b i,j´ The sum of j' and j' is further added for all i. Note that j' is an integer other than i, between 1 and N. The first term on the right side of equation (4) represents the first condition.

[0046] The second term on the right side of equation (4) is b for all combinations of i and i' other than i=i' for any j. i,j ×b i´,j The sum of i and n is further added for all j. Note that i' is an integer between 1 and N, other than j. The second term on the right side of equation (4) is an equation that expresses the second condition.

[0047] The third term in the right-hand side of equation (4) is the value in parentheses for any i and for all j. i,j From the sum of all j, j,i The third term on the right side of equation (4) is an equation that calculates the square of the subtracted value obtained by subtracting the added value of i from i. The third term on the right side of equation (4) is an equation that adds up the values ​​calculated in the parentheses for all i. The third term on the right side of equation (4) is an equation that represents the third condition.

[0048] The fourth term on the right side of equation (4) is b i,j ×b j,i The fourth term on the right side of equation (4) represents the fourth condition.

[0049] The 1 / 2 attached to all terms of the penalty function P is a coefficient to ensure that the minimum deviation of each term from 0 is 1. The penalty function P may be any other formula as long as it uses multiple bits to express the constraints that satisfy the optimal route for a closed loop. For example, the penalty function P is i,j 2 = × b i,j It may also include a formula using:

[0050] (Numerical analysis of problems related to closed circuits) The search method according to this embodiment numerically solves the values ​​of a plurality of bits included in the 0-1 optimization problem as described above, using the method disclosed in Non-Patent Document 1.

[0051] When the method described in Non-Patent Document 1 is used, a plurality of bits included in a 0-1 optimization problem are associated with a plurality of virtual particles. Therefore, the plurality of particles correspond to a plurality of directed edges included in a directed graph. In addition, the entire energy (Hamiltonian) of the plurality of particles is expressed by a 0-1 optimization problem. Then, the search method according to this embodiment calculates the values ​​of the plurality of bits by numerically solving the equation of motion of the plurality of particles using the Symplectic Euler method.

[0052] For example, the search method according to this embodiment calculates a solution to a closed-path problem by numerically solving the equations of motion of classical mechanics shown in the following equations (5), (6), (7), and (8) using the Symplectic Euler method.

[0053]

number

[0054] In the formulas (5) to (8), t represents time. i represents the index of a node and is an integer of 1 or more and N or less. j represents the index of a node and is an integer of 1 or more and N or less other than i. w i,j represents the weight value assigned to the directed edge leaving the i-th node and entering the j-th node. i,j represents the position of the particle corresponding to the directed edge that leaves the i-th node and enters the j-th node. j,i represents the position of the particle corresponding to the directed edge that leaves the jth node and enters the ith node. i,j represents the momentum of a particle corresponding to a directed edge leaving the i-th node and entering the j-th node.

[0055] In formulas (5) to (8), XR i represents the first integrated value of the i-th node. XC i represents the second integrated value of the i-th node. XR j represents the first cumulative value of the jth node. XC j represents the second integrated value of the jth node. MC and M. P represents an arbitrary constant.

[0056] Equation (5) expresses the position x of a particle corresponding to a directed edge that exits the i-th node and enters the j-th node. i,j represents the time derivative of

[0057] Equation (6) expresses the momentum y of a particle corresponding to a directed edge that exits from the i-th node and enters the j-th node. i,j Equation (6) expresses the time derivative of the composite cost function (E in equation (2)) of the 0-1 optimization problem for a loop as i,j After partial differentiation with b i,j x i,j is proportional to the expression replaced by

[0058] Equation (7) represents a first cumulative sum of two or more particle positions corresponding to two or more directed edges going out for the i-th node, while equation (8) represents a second cumulative sum of two or more particle positions corresponding to two or more directed edges going in for the j-th node.

[0059] The search method according to the present embodiment uses such formulas (5) to (8) to time-integrate the positions and momentum of each of a plurality of virtual particles for each unit time from the initial time to the end time. In this case, the search method according to the present embodiment calculates the position and momentum alternately based on the Symplectic Euler method. That is, the search method according to the present embodiment calculates the position and then the momentum for each unit time, or calculates the position and then the momentum for each unit time.

[0060] Additionally, the particle positions are constrained to a continuum representing values ​​between a first value for the corresponding bit (e.g., 0) and a second value for the corresponding bit (e.g., 1), the second value being greater than the first value.

[0061] Therefore, the search method according to this embodiment corrects the position of each of the plurality of particles to a first value (e.g., 0) for each unit time if the position is smaller than a first value, and corrects the position to a second value (e.g., 1) for each unit time if the position is larger than a second value. Furthermore, the search method according to this embodiment may correct the momentum of each of the plurality of particles to a predetermined value or a value determined by a predetermined calculation for each unit time if the position is smaller than the first value or larger than the second value.

[0062] Then, in the search method according to the present embodiment, the positions of the particles at the final time are binarized by a predetermined threshold (e.g., 0.5) and output as solutions to the bits included in the 0-1 optimization problem. A specific device for executing a process according to such a search method will be described with reference to FIG. 5 and subsequent figures.

[0063] Moreover, the search method according to this embodiment may use the following equation (9) instead of equation (6) to calculate a solution to a problem regarding a closed path.

[0064]

number

[0065] p is 0 at the initial time and 1 at the final time, and is a value that increases monotonically with each unit time. Equation (10) is the h i,j x0 represents x i,j At the initial time, N is the number of nodes in the directed graph.

[0066] Equation (9) is a function of p, which increases monotonically from 0 to 1, and h in equation (10), which depends on p, in equation (6). i,j These time-varying parameters are the sum of two types of time-varying parameters: the time derivative of the momentum at the initial time is 0, and at the end time, the term on the right side of equation (9) that does not depend on the particle position x is h i,j is a value that changes every unit time so that it becomes 0.

[0067] (Problem regarding routes between two different nodes) Problems regarding paths connecting two different nodes have a different penalty function P compared to problems regarding closed paths.

[0068] In a problem regarding a path connecting two different nodes, the penalty function P uses multiple bits to express the conditions under which the selected path forms a path connecting two nodes in a directed graph. The conditions for forming a closed path in a directed graph are as follows:

[0069] The first condition is that the start node is selected for the optimal path and has one outgoing directed edge, and the end node is selected for the optimal path and has one incoming directed edge. The second condition is that the start node selected for the optimal path has zero incoming directed edges, and the end node selected for the optimal path has zero outgoing directed edges. The third condition is that each of the N nodes has one or less outgoing directed edges selected for the optimal path.

[0070] The fourth condition is that each of the N nodes has one or less incoming directed edges selected for the optimal path.

[0071] The fifth condition is that for each of the N-2 nodes other than the start node and the end node, the number of outgoing directed edges selected for the optimal path is equal to the number of incoming directed edges selected for the optimal path.

[0072] The sixth condition is that a directed edge exiting from the i-th node and entering the j-th node and a directed edge exiting from the j-th node and entering the i-th node are not simultaneously selected as the optimal path.

[0073] The penalty function P which expresses the above conditions using a plurality of bits incorporates, for example, the following equations (21-1), (21-2), (21-3), (21-4), (21-5) and (21-6).

[0074]

number

[0075] Here, s represents a specified integer greater than or equal to 1 and less than or equal to N. v represents a specified integer other than s greater than or equal to 1 and less than or equal to N. k represents an integer greater than or equal to 1 and less than or equal to N.

[0076] Equation (21-1) is b for all j. s、j The sum of b and b is 1 for all i. i、v The value obtained by adding is 1. Equation (21-1) is an equation representing the first condition.

[0077] Equation (21-2) is b for all i i、s The sum of is 0, and for all j, b v、j The value obtained by adding is 0. Equation (21-2) is an equation expressing the second condition.

[0078] Equation (21-3) is b for all j. k、j is less than or equal to 1. Equation (21-3) represents the third condition.

[0079] Equation (21-4) is b for all i i、k is less than or equal to 1. Equation (21-4) represents the fourth condition.

[0080] Equation (21-5) is the same as b for all i except s and v. i、k and for all k except s and v, k、j Equation (21-5) represents the fifth condition.

[0081] Equation (21-6) is b i、jと b j、i This means that the value obtained by multiplying this by 0 is 0. Equation (21-6) is an equation that represents the sixth condition.

[0082] (Numerical analysis of the problem of routing between two different nodes) The search method according to this embodiment calculates a solution to a problem regarding a path connecting two different nodes by numerically solving the classical mechanics equations of motion shown in the following equations (22), (23), (24), (25), (26), and (27) using the Symplectic Euler method.

[0083]

number

[0084] In formulas (22) to (27), t represents time. i represents a node index and is an integer greater than or equal to 1 and less than or equal to N. j represents a node index and is an integer greater than or equal to 1 and less than or equal to N other than i.

[0085] In formulas (22) to (27), s represents the index of the path start node and is a specified integer greater than or equal to 1 and less than or equal to N. v represents the index of the path end node and is a specified integer greater than or equal to 1 and less than or equal to N, other than s. k represents the index of the node and is an integer greater than or equal to 1 and less than or equal to N, other than s and v. l represents the index of the node and is an integer greater than or equal to 1 and less than or equal to N, other than s, v, and k. w s,l w represents the weight value assigned to the directed edge that leaves the path start node and enters the lth node. k,v represents the weight value assigned to the directed edge leaving the kth node and entering the path end node. k,l represents the weight value assigned to the directed edge leaving the kth node and entering the lth node.

[0086] In formulas (22) to (27), x k,lrepresents the position of the particle corresponding to the directed edge that exits the kth node and enters the lth node. l,k represents the position of the particle corresponding to the directed edge that exits the lth node and enters the kth node. y s,l represents the momentum of the particle corresponding to the directed edge that leaves the path start node and enters the lth node. y k,v represents the momentum of the particle corresponding to the directed edge that exits the kth node and enters the end node. y k,l represents the momentum of the particle corresponding to the directed edge leaving the kth node and entering the lth node.

[0087] In formulas (22) to (27), XR S represents the first integrated value of the route start node. XC v represents the second integrated value of the route end node. k represents the first integrated value of the kth node. XC k represents the second integrated value of the kth node. XR l represents the first cumulative value of the l-th node. XC l represents the second integrated value of the l-th node. M C and M. P represents an arbitrary constant.

[0088] Equation (22) expresses the position x of a particle corresponding to a directed edge that exits from the i-th node and enters the j-th node. i,j represents the time derivative of

[0089] Equation (23) expresses the momentum y of the particle corresponding to the directed edge that leaves the path start node and enters the lth node. s,l Equation (23) expresses the composite cost function (E in equation (2)) of the 0-1 optimization problem for the path connecting two different nodes as b s,l After partial differentiation with b s,l x s,l is proportional to the expression replaced by

[0090] Equation (24) expresses the momentum y of the particle corresponding to the directed edge that exits the kth node and enters the path end node. k,vEquation (23) expresses the composite cost function (E in equation (2)) of the 0-1 optimization problem for the path connecting two different nodes as b k,v After partial differentiation with b k,v x k,v is proportional to the formula replaced by

[0091] Equation (25) expresses the momentum y of the particle corresponding to the directed edge that exits the kth node and enters the lth node. k,l Equation (25) expresses the time derivative of the composite cost function (E in equation (2)) of the 0-1 optimization problem for the path connecting two different nodes as b k,l After partial differentiation with b k,l x k,l is proportional to the formula replaced by

[0092] Equation (26) represents a first accumulated value obtained by accumulating the positions of two or more particles corresponding to two or more directed edges going out for the i-th node, while equation (27) represents a second accumulated value obtained by accumulating the positions of two or more particles corresponding to two or more directed edges going in for the j-th node.

[0093] The search method according to this embodiment uses such equations (22) to (27) to solve the problem regarding a path connecting two different nodes, similar to the optimization problem in the case of a closed path.

[0094] However, in the search method according to this embodiment, x s,v , x v,s , x k,s and x v,l For example, the search method according to the present embodiment solves the problem by fixing x s,v , x v,s , x k,s and x v,l is fixed to 0.

[0095] In addition, x s,v represents the position of the particle corresponding to the directed edge that exits from the path start node and enters the path end node. v,srepresents the position of the particle corresponding to the directed edge that exits from the path end node and enters the path start node. k,s represents the particle position corresponding to the directed edge that leaves the kth node and enters the path start node. v,l represents the position of the particle corresponding to the directed edge that leaves the path end node and enters the l-th node.

[0096] In addition, the search method of this embodiment may calculate a solution to a problem regarding a route connecting two different nodes using the following equations (28), (29), and (30) instead of equations (23), (24), and (25).

[0097]

number

[0098] p is a value that is 0 at the initial time and 1 at the final time, and increases monotonically for each unit time.

[0099] The following equation (31) is the h s,l The following equation (32) represents the h k,v The following equation (33) represents the h k,l x0 represents x i,j At the initial time, N is the number of nodes in the directed graph.

[0100]

number

[0101] Equation (28) is equation (23) to which a time change parameter has been added. Equation (29) is equation (24) to which a time change parameter has been added. Equation (30) is equation (25) to which a time change parameter has been added. The time change parameter is a value that changes per unit time so that the time derivative of the momentum at the initial time is 0, and h, the term on the right-hand side of equations (28), (29), and (30) that does not depend on the particle position x, is 0 at the end time.

[0102] (Search device 10) 5 is a diagram showing the configuration of the searching device 10 according to the first embodiment. The searching device 10 according to the first embodiment includes a calculation unit 12, an input unit 14, an output unit 16, and a setting unit 18.

[0103] The calculation unit 12 is realized by, for example, an information processing device. Alternatively, the calculation unit 12 may be realized by one or more processing circuits such as a CPU (Central Processing Unit) executing a program. Alternatively, the calculation unit 12 may be realized by an FPGA (Field Programmable Gate Array), a gate array, an application specific integrated circuit (ASIC), or the like.

[0104] The calculation unit 12 increases a parameter t representing time by unit time from a start time (e.g., 0). The calculation unit 12 calculates the position and momentum of each of the virtual particles by time integration for each unit time from the initial time to the end time. Then, the calculation unit 12 calculates a solution for each of the multiple bits included in the 0-1 optimization problem by binarizing the position of each of the multiple particles at the end time using a preset threshold value.

[0105] The input unit 14 acquires the position and momentum of each of the multiple particles at the start time prior to the calculation process by the calculation unit 12, and provides the position and momentum to the calculation unit 12. After the calculation process by the calculation unit 12 is completed, the output unit 16 acquires the solutions of each of the multiple bits included in the 0-1 optimization problem from the calculation unit 12. Then, the output unit 16 outputs the acquired solutions. The setting unit 18 sets each parameter for the calculation unit 12 prior to the calculation process by the calculation unit 12.

[0106] 6 is a flowchart showing a flow of processing of the searching device 10 according to the first embodiment. The calculation unit 12 of the searching device 10 executes processing according to the flowchart shown in FIG.

[0107] First, in S11, the calculation unit 12 initializes parameters. More specifically, the calculation unit 12 initializes t, p and h i,j For example, the calculation unit 12 initializes t to 0, which represents the start time. The calculation unit 12 also initializes p to 0. For example, the calculation unit 12 sets p=0 and initializes h i,j In addition, when p is not used in S17 described later, the calculation unit 12 does not initialize p. i,j If you do not use h i,j Do not initialize.

[0108] Next, the calculation unit 12 repeats the processes from S13 to S18 until t becomes greater than T (loop process between S12 and S19), where T represents the end time. This allows the calculation unit 12 to repeat the processes from S13 to S18 for each unit time from the initial time to the end time.

[0109] In S13, the calculation unit 12 calculates the position (x i,j ) is the momentum (y i,j For example, the calculation unit 12 calculates the position (x i,j) and the momentum at the previous time (y i,j ) multiplied by the unit time and added to it to get the position (x i,j More specifically, the calculation unit 12 calculates the position (x i,j ) is calculated.

[0110]

number

[0111] x on the right hand side of equation (41) i,j represents the position of the particle corresponding to the directed edge that exits from the i-th node and enters the j-th node at the previous time. i,j represents the momentum of a particle corresponding to a directed edge that exits from the i-th node and enters the j-th node at the previous time. dt represents unit time.

[0112] Next, in S14, the calculation unit 12 calculates the position (x i,j If the position (x i,j ) to a first value. In addition, the calculation unit 12 corrects the position (x i,j ) is greater than a second predetermined value, the position (x i,j ) to a second value, where the second value is greater than the first value.

[0113] When the value of the bit representing that the corresponding directed edge is not selected is 0, the first value is 0. When the value of the bit representing that the corresponding directed edge is selected is 1, the second value is 1. For example, the calculation unit 12 calculates the position (x i,j ) is less than 0, the position (x i,j For example, the calculation unit 12 sets the position (x i,j ) is greater than 1, the position (xi,j ) is set to 1. In this way, the calculation unit 12 calculates the positions (x i,j ) can be restricted to lie within the range of two possible values ​​for the bit.

[0114] In addition, the calculation unit 12 calculates the position (x i,j If the first value is smaller than the second value or the second value is larger than the second value, the momentum (y i,j ) to a predetermined value or a value determined by a predetermined calculation. For example, the calculation unit 12 corrects the position (x i,j ) is smaller than 0 or greater than 1, the momentum (y i,j ) to a predetermined value or a value determined by a predetermined operation. The predetermined value is, for example, 0. The predetermined value may be any value greater than 0 and less than or equal to 1. The predetermined operation may be, for example, an operation that generates a random number greater than or equal to 0 and less than or equal to 1.

[0115] Next, in S15, the calculation unit 12 calculates the positions (x i,j ) is added to the first integrated value (XR i More specifically, the calculation unit 12 calculates the first integrated value (XR i ) is calculated.

[0116]

number

[0117] Equation (42) is, for all j except i, x i,j The calculation unit 12 calculates the first integrated value (XR i ) to calculate the momentum (y i,j) can be easily calculated.

[0118] Next, in S16, the calculation unit 12 calculates the positions (x i,j ) is added to the second integrated value (XC j More specifically, the calculation unit 12 calculates the second integrated value (XC j ) is calculated.

[0119]

number

[0120] Equation (43) is, for all i except j, x i,j The calculation unit 12 calculates the second integrated value (XC j ) to calculate the momentum (y i,j ) can be easily calculated.

[0121] Next, in S17, the calculation unit 12 calculates the momentum (y i,j More specifically, the calculation unit 12 calculates the amount of exercise (y i,j ) to the first accumulated value of the end node (XR i ) and the second integrated value (XC i ), the first accumulated value of the starting node (XR j ) and the second integrated value (XC j ), the weight value assigned to the corresponding directed edge (w i,j ), the position at the target time (x i,j ), and the position (x j,i For example, the calculation unit 12 calculates the particle distribution based on (y i,j) and the value obtained by multiplying the time derivative of the momentum at the previous time by unit time to obtain the momentum (y i,j ) is calculated.

[0122] More specifically, the calculation unit 12 calculates the momentum (y i,j ) is calculated.

[0123]

number

[0124] In addition, y on the right side of equation (44) i,j represents the momentum of a particle corresponding to a directed edge that exits from the i-th node and enters the j-th node at the previous time. i,j / dt) represents the time derivative of the momentum of a particle corresponding to a directed edge that exits from the i-th node and enters the j-th node at the previous time. dt represents unit time.

[0125] In addition, in the case of problems involving closed circuits, the time derivative of the momentum (y i,j / dt) is calculated, for example, by equation (6) or equation (9). In the case of a problem regarding a path connecting two different nodes, the time derivative of the momentum (y i,j / dt) is calculated, for example, by equations (23), (24), and (25). In the case of a problem regarding a path connecting two different nodes, the time derivative of the momentum (y i,j / dt) is calculated, for example, by equation (28), equation (29), and equation (30).

[0126] In addition, in the case of a problem related to a closed path, in S17, the calculation unit 12 calculates the momentum (y i,j ) may be calculated in two steps using the following equations (45) and (46).

[0127]

number

number

[0128] h0 in equation (45) is expressed by the following equation (47).

[0129]

number

[0130] In this case, the calculation unit 12 may execute the calculation process of the equation (45) immediately after the process of S13.

[0131] Next, in S18, the calculation unit 12 updates the parameters. More specifically, the calculation unit 12 updates t, p and h i,j Initialize.

[0132] For example, the calculation unit 12 adds a unit time (dt) to t. The start time is 0, the end time is T, and N step times(N step is an integer equal to or greater than 2) When repeating the loop, dt = T / N step In this case, p=p+(1 / N step ) In addition, if p is not used in S17, the calculation unit 12 does not update p. i,j If you do not use h i,j Do not update.

[0133] Next, in S19, the calculation unit 12 determines whether t has exceeded the end time, that is, whether t has become greater than T. If t has not exceeded the end time, the calculation unit 12 returns the process to S13 and executes the processes from S13 to S18. If t has exceeded the end time, the calculation unit 12 advances the process to S20.

[0134] In S20, the calculation unit 12 calculates the positions (x i,j) is binarized by a preset threshold value. For example, the calculation unit 12 may binarize the positions (x i,j ) is binarized by 0.5, which is the intermediate value between the first value (0) and the second value (1). Then, the calculation unit 12 calculates the positions (x i,j ) is binarized and output as a solution (0 or 1) for each of the multiple bits involved in the 0-1 optimization problem.

[0135] As described above, the search device 10 can quickly output a solution to an optimal path problem for searching an optimal path in a directed graph. For example, the search device 10 can quickly output a solution to a problem regarding a closed path and a problem regarding a path connecting two different nodes.

[0136] Second embodiment The searching device 10 according to the second embodiment is implemented as a circuit in a semiconductor device such as an FPGA, a gate array, or an application specific integrated circuit, etc. The searching device 10 according to the second embodiment will be described below.

[0137] The searching device 10 according to the second embodiment searches a directed graph including N nodes to find a solution to an arbitrage problem that detects an opportunity for foreign exchange arbitrage.

[0138] 7 is a diagram showing a circuit configuration of a searching device 10 according to the second embodiment. The searching device 10 according to the second embodiment includes a memory 21, a control circuit 22, a first circuit 23, a second circuit 24, a binarization circuit 25, and a normalization circuit 26. The first circuit 23 includes a TE circuit 31 (self-development circuit), a GC circuit 32 (integrated value calculation circuit), and a CC circuit 33 (cost calculation circuit). The second circuit 24 includes an MX circuit 34 (many-body interaction circuit).

[0139] The searching device 10 may not include the normalization circuit 26. The first circuit 23 may not include the CC circuit 33.

[0140] The memory 21 stores a plurality of position variables, a plurality of momentum variables, a plurality of weighting values, a plurality of non-selectable flags, a plurality of first integrated values, a plurality of second integrated values, a plurality of reversal position variables, and a maximum absolute value.

[0141] The plurality of position variables correspond to the plurality of directed edges included in the directed flag, and each of the plurality of position variables represents a position of a particle associated with the corresponding directed edge.

[0142] The plurality of momentum variables correspond to the plurality of directed edges, and each of the plurality of momentum variables represents the momentum of a particle associated with the corresponding directed edge.

[0143] The weight values ​​correspond to the directed edges. Each of the weight values ​​is assigned to a corresponding directed edge. The weight values ​​are written to the memory 21 from an external device prior to the arithmetic processing by the first circuit 23 and the second circuit 24.

[0144] The multiple unselectable flags correspond to the multiple directed edges. The multiple unselectable flags indicate whether the corresponding directed edge is selectable or unselectable as a route. For example, when the multiple unselectable flags are 0, they indicate that the corresponding directed edge is selectable as a route, and when the multiple unselectable flags are 1, they indicate that the corresponding directed edge is unselectable as a route. Whether a directed edge is selectable or unselectable as a route is determined in advance by the directed graph. The multiple unselectable flags are written to the memory 21 from an external device prior to the arithmetic processing by the first circuit 23 and the second circuit 24.

[0145] The first integrated values ​​correspond to the plurality of nodes, and the second integrated values ​​correspond to the plurality of nodes.

[0146] The multiple inversion position variables correspond to the multiple directed edges. Each of the multiple inversion position variables is the same as the multiple position variables, but the correspondence between the start node and the end node is stored in an inverted manner.

[0147] The maximum absolute value is the maximum value among the absolute values ​​of the multiple weight values ​​before normalization.

[0148] The control circuit 22 is connected to the memory 21, the first circuit 23, the second circuit 24, the binarization circuit 25, and the normalization circuit 26. The control circuit 22 controls an operation for time-integrating the position variables and momentum variables corresponding to each of the multiple directed edges for each unit time from the initial time to the end time. For example, the control circuit 22 manages the unit time, manages the repetitive processing, and updates parameters. The TE circuit 31 and the MX circuit 34 execute an operation for time-integrating the position variables and momentum variables for each of the multiple directed edges for each unit time according to the control of the control circuit 22. In addition, the control circuit 22 initializes the multiple position variables and multiple momentum variables stored in the memory 21 prior to the calculation processing.

[0149] The TE circuit 31 is connected to the memory 21. The TE circuit 31 accesses the memory 21 for each unit time and executes the TE processing.

[0150] More specifically, the TE circuit 31 updates the position variable of the corresponding directed edge at the target time for each of the multiple directed edges for each unit time, according to the position variable and momentum variable at the time immediately preceding the target time of the corresponding directed edge, which is one unit time before the target time of the corresponding directed edge. This allows the TE circuit 31 to time-integrate the position variable for each of the multiple directed edges for each unit time.

[0151] Furthermore, for each of the multiple directed edges, the TE circuit 31 updates the momentum variable of the corresponding directed edge at the target time in accordance with the momentum variable at the immediately preceding time, the position variable of the corresponding directed edge at the target time, and the weight value assigned to the corresponding directed edge, for each unit time. This allows the TE circuit 31 to perform the calculation of the time integral of the momentum variable for each of the multiple directed edges up to an intermediate stage.

[0152] Furthermore, for each unit time, for each of the multiple directed edges, if the position variable of the corresponding directed edge at the target time is smaller than a predetermined first value, the TE circuit 31 corrects the position variable at the target time to a first value, and if the position variable is larger than a predetermined second value, the TE circuit 31 corrects the position variable at the target time to a second value. Note that the second value is larger than the first value. For example, for each unit time, for each of the multiple directed edges, if the position variable of the corresponding directed edge at the target time is smaller than 0, the TE circuit 31 corrects the position variable at the target time to 0, and if the position variable is larger than 1, the TE circuit 31 corrects the position variable at the target time to 1.

[0153] Furthermore, for each unit time, for each of the multiple directed edges, if the position variable at the target time is smaller than a first value (e.g., 0) or larger than a second value (e.g., 1), the TE circuit 31 corrects the momentum variable at the immediately preceding time to a predetermined value or a value determined by a predetermined calculation. The predetermined value is, for example, 0 or any value between 0 and 1. The value determined by the predetermined calculation may be, for example, a value determined by a random number in the range between 0 and 1.

[0154] Furthermore, for each of the multiple directed edges, if the non-selectable flag of the corresponding directed edge indicates non-selectable, the TE circuit 31 replaces the position variable at the target time and the momentum variable at the target time that has been updated to an intermediate stage with a predetermined value (e.g., 0).

[0155] The GC circuit 32 is connected to the memory 21. The GC circuit 32 accesses the memory 21 for each unit time and executes the GC process.

[0156] More specifically, the GC circuit 32 calculates a first integrated value by accumulating position variables at two or more target times corresponding to two or more outgoing directed edges for each of a plurality of nodes included in the directed graph for each unit time. Furthermore, the GC circuit 32 calculates a second integrated value by accumulating position variables at two or more target times corresponding to two or more incoming directed edges for each of a plurality of nodes for each unit time. The GC circuit 32 may obtain the position variables at the target time from the TE circuit 31 without going through the memory 21.

[0157] The CC circuit 33 is connected to the memory 21. The CC circuit 33 accesses the memory 21 for each unit time and executes the CC process.

[0158] More specifically, the CC circuit 33 binarizes the position variables corresponding to each of the multiple directed edges by a preset threshold value for each unit time, thereby determining whether each of the multiple directed edges has been selected as an optimal route at the target time. Next, the CC circuit 33 determines for each unit time whether two or more directed edges selected as an optimal route at the target time satisfy the constraint conditions of the optimal route. Then, if the constraint conditions are satisfied, the CC circuit 33 calculates a total weight value obtained by combining the weight values ​​assigned to the two or more selected directed edges. For example, if the constraint conditions are satisfied, the CC circuit 33 calculates a sum value obtained by adding the weight values ​​assigned to the two or more selected directed edges.

[0159] Furthermore, the CC circuit 33 calculates a total rate (sol) obtained when the exchange corresponding to the two or more directed edges is performed based on the sum of the weight values ​​assigned to the two or more selected directed edges. The CC circuit 33 outputs the calculated total rate (sol) to an external device.

[0160] The MX circuit 34 is connected to the memory 21. The MX circuit 34 accesses the memory 21 for each unit time and executes the MX process.

[0161] More specifically, for each of the multiple directed edges, the MX circuit 34 further updates the momentum variable of the corresponding directed edge at the target time based on the position variable of the corresponding directed edge at the target time and the position variables of directed edges other than the corresponding directed edge at the target time for each unit time. More specifically, for each of the multiple directed edges, the MX circuit 34 further updates the momentum variable of the corresponding directed edge at the target time after being updated by the TE circuit 31 according to the first and second integrated values ​​of the end node, the first and second integrated values ​​of the start node, the position variable of the corresponding directed edge at the target time, and the position variable of the corresponding directed edge at the target time corresponding to the directed edge opposite to the corresponding directed edge. This allows the MX circuit 34 to time-integrate the momentum variable integrated by the TE circuit 31 up to the intermediate stage up to the final stage for each of the multiple directed edges.

[0162] The binarization circuit 25 is connected to the memory 21. The binarization circuit 25 reads out from the memory 21 position variables corresponding to each of the multiple directed edges at the end time. The binarization circuit 25 calculates a solution for each of the multiple bits included in the 0-1 optimization problem by binarizing the position variables corresponding to each of the multiple directed edges at the end time using a preset threshold value. Then, the binarization circuit 25 outputs the solution for each of the multiple bits included in the 0-1 optimization problem.

[0163] The normalization circuit 26 is connected to the memory 21. When a plurality of weight values ​​are written to the memory 21 from an external device, the normalization circuit 26 performs a normalization process on each of the plurality of weight values ​​prior to the arithmetic process by the first circuit 23 and the second circuit 24. More specifically, the normalization circuit 26 normalizes each of the plurality of weight values ​​based on the maximum absolute value among the plurality of weight values, and writes the normalized plurality of weight values ​​to the memory 21. The normalization circuit 26 also writes the maximum absolute value to the memory 21.

[0164] Furthermore, when searching for a closed path as an optimal path, the normalization circuit 26 executes a correction process prior to the normalization process. When the total weight value is an added value of two or more weight values ​​assigned to two or more directed edges included in the selected path, the normalization circuit 26 performs a correction process by adding a coefficient set for the end node to the corresponding weight value for each of the directed edges and subtracting a coefficient set for the start node. Note that a coefficient is set in advance for each of the multiple nodes. The coefficient set corresponding to each of the multiple nodes is determined so that the sum of the errors from 0 of the corrected weight values ​​is minimized.

[0165] 8 is a diagram showing the configuration of memory 21. Memory 21 includes an X memory circuit 41, a Y memory circuit 42, a W memory circuit 43, a Z memory circuit 44, an XR memory circuit 45, an XC memory circuit 46, an XT memory circuit 47, and a maximum value memory circuit 48. Each of the X memory circuit 41, the Y memory circuit 42, the W memory circuit 43, the Z memory circuit 44, the XR memory circuit 45, the XC memory circuit 46, the XT memory circuit 47, and the maximum value memory circuit 48 has a read port and a write port, and data is read from and written to each of them independently of each other.

[0166] The X memory circuit 41 stores the position matrix (X mem ) The position matrix stores N×N position variables. In the position matrix, the row number represents the index of the start node in the directed edge, and the column number represents the index of the end node in the directed edge. The position matrix stores each of the N×N position variables as an element of the row number and column number of the corresponding directed edge. For example, the position matrix stores the position variable corresponding to the directed edge exiting from the i-th node and entering the j-th node as the element of the i-th row and j-th column.

[0167] Note that the directed graph does not include a directed edge of a self-loop (a directed edge going out from the i-th node and going into the i-th node). Therefore, the position matrix stores 0, a value that does not affect the route search, as an element of the diagonal component with the same row number and column number.

[0168] The Y memory circuit 42 stores the momentum matrix (Y mem ) is stored in the momentum matrix. The momentum matrix stores N×N momentum variables. In the momentum matrix, the row numbers represent the index of the start node in the directed edge, and the column numbers represent the index of the end node in the directed edge. The momentum matrix stores each of the N×N momentum variables as an element of the row number and column number of the corresponding directed edge. Note that the momentum matrix stores 0, a value that does not affect the path search, as an element of the diagonal component with the same row number and column number.

[0169] The W memory circuit 43 stores the weight value matrix (W mem ) is stored in the weight value matrix. The weight value matrix stores N x N weight values. In the weight value matrix, the row number represents the index of the start node in a directed edge, and the column number represents the index of the end node in a directed edge. The weight value matrix stores each of the N x N weight values ​​as an element of the row number and column number of the corresponding directed edge. Note that the weight value matrix stores 0, a value that does not affect the route search, as an element of the diagonal component with the same row number and column number.

[0170] The Z memory circuit 44 stores the flag matrix (Z mem ) The flag matrix stores N x N unselectable flags. In the flag matrix, the row numbers represent the index of the start node in a directed edge, and the column numbers represent the index of the end node in a directed edge. The flag matrix stores each of the N x N flags as an element of the row number and column number of the corresponding directed edge. The flag matrix stores 1, which indicates that the route is unselectable, as an element of the diagonal component with the same row number and column number.

[0171] The XR memory circuit 45 stores the first integrated value array (XR mem ) is stored. The first accumulated value array stores N first accumulated values. In the first accumulated value array, the array number represents the index of the node. The first accumulated value array stores each of the N first accumulated values ​​as an element of the array number of the corresponding node.

[0172] The XC memory circuit 46 stores the second integrated value array (XC mem ) is stored. The second accumulated value array stores N second accumulated values. In the second accumulated value array, the array number represents the index of the node. The second accumulated value array stores each of the N second accumulated values ​​as an element of the array number of the corresponding node.

[0173] The XT memory circuit 47 stores the inversion position matrix (XT mem ) is stored. The inverted position matrix stores N×N position variables arranged in a reversed manner. In the inverted position matrix, the row numbers represent the index of the end node in the directed edge, and the column numbers represent the index of the start node in the directed edge. The inverted position matrix stores each of the N×N position variables as an element of the row number and column number of the corresponding directed edge. For example, the position matrix stores the position variable corresponding to the directed edge exiting from the i-th node and entering the j-th node as the element of the j-th row and i-th column. Note that the inverted position matrix stores 0, a value that does not affect the route search, as an element of the diagonal components with the same row number and column number.

[0174] The maximum value memory circuit 48 stores the maximum absolute value (absmax) of the multiple weight values ​​before normalization.

[0175] 9 is a flowchart showing the flow of processing of the searching device 10. The searching device 10 according to the second embodiment executes processing according to the flow shown in FIG.

[0176] First, in S31, the normalization circuit 26 executes normalization processing and correction processing. Note that, if the normalization processing and correction processing have already been executed for the multiple weight values ​​stored in the memory 21, the normalization circuit 26 does not execute the processing of S31.

[0177] Next, in S32, the control circuit 22 initializes a parameter (p). p is 0 at the initial time. Furthermore, the control circuit 22 initializes a plurality of position variables stored in the X memory circuit 41 included in the memory 21 to arbitrary values. Furthermore, the control circuit 22 initializes a plurality of momentum variables stored in the Y memory circuit 42 included in the memory 21 to arbitrary values.

[0178] Next, in S33, the TE circuit 31 executes the TE process. Next, in S34, the GC circuit 32 executes the GC process. Next, in S35, the CC circuit 33 executes the CC process. The TE circuit 31, the GC circuit 32, and the CC circuit 33 repeatedly execute the processes of S33, S34, and S35 for each of the N×N directed edges. The loop process (first loop) of S33, S34, and S35 is completed within the first circuit 23. In S36, when the processes of S33 and S34 have been executed N×N times (Yes in S36), the control circuit 22 advances the process to S37. Note that the control circuit 22 may advance the process to S37 even if all the processes of S35 are not completed. In this case, the processes of S35 and S37 are executed in parallel.

[0179] In S37, the MX circuit 34 executes the MX process. The MX circuit 34 repeatedly executes the process of S37 for each of the N×N directed edges. The loop process (second loop) of S37 is completed within the second circuit 24. In S38, when the process of S37 has been executed N×N times (Yes in S37), the control circuit 22 advances the process to S39.

[0180] In S39, the control circuit 22 updates the parameter (p). The control circuit 22, the first circuit 23, and the second circuit 24 repeat the process from S33 to S39 (third loop) a predetermined number of times.

[0181] When the first circuit 23 executes the process from S33 to S39 (third loop) once, it can time-integrate the position variable for a unit time. When the first circuit 23 and the second circuit 24 execute the process from S33 to S39 (third loop) once, it can time-integrate the momentum variable for a unit time. When the first circuit 23 executes the process from S33 to S39 (third loop) a predetermined number of steps, it can time-integrate the position variable and the momentum variable from the initial time to the end time.

[0182] In S40, if the processing from S33 to S39 has been repeated a predetermined number of steps (Yes in S40), the control circuit 22 advances the processing to S41.

[0183] In S41, the binarization circuit 25 calculates a solution for each of the multiple bits included in the 0-1 optimization problem. Then, the binarization circuit 25 outputs the solution for each of the multiple bits included in the 0-1 optimization problem. The search device 10 repeatedly executes the processes from S31 to S41, for example, at regular intervals.

[0184] 10 is a diagram showing variables and values ​​input and output to the TE circuit 31. The TE circuit 31 reads from the memory 21 the position variable (X i,j ), momentum variable (Y i,j ), weight value (w i,j ) and the unselectable flag (z i,j The TE circuit 31 then executes the TE process for each of the N×N directed edges to obtain the position variable (X i,j ), inversion position variable (XT j,i ) and the momentum variable (Y i,j ) and write it to the memory 21.

[0185] 11 is a diagram showing variables input and output to the GC circuit 32. After the TE process is performed by the TE circuit 31, the GC circuit 32 reads from the memory 21 the position variables (X i,jThe GC circuit 32 reads out the position variable (X i,j ) may be obtained.

[0186] Each time the GC circuit 32 executes the TE process on the position variables for one row, it calculates the first integrated value (XR i ) and writes it to the memory 21. Furthermore, every time the GC circuit 32 executes the TE process on the position variables for one column, the GC circuit 32 generates a second integrated value (XC j ) and write it to the memory 21.

[0187] 12 is a diagram showing variables and values ​​input and output to the CC circuit 33. After the TE process is performed by the TE circuit 31, the CC circuit 33 reads from the memory 21 the position variables (X i,j ) and weight values ​​(w i,j The CC circuit 33 reads out the position variable (X i,j In addition, the CC circuit 33 may read the maximum absolute value (absmax) from the memory 21.

[0188] The CC circuit 33 calculates the sum of the weight values ​​by executing CC processing for all N×N directed edges. Then, the CC circuit 33 calculates a total rate (sol) obtained when exchanges corresponding to two or more directed edges are made based on the sum of the weight values ​​assigned to the two or more selected directed edges, and outputs the total rate (sol) to the outside.

[0189] 13 is a diagram showing variables and values ​​input and output to the MX circuit 34. The MX circuit 34 reads, from the memory 21, the position variable (X i,j ), momentum variable (Y i,j ), inversion position variable (XT i,j ), the first accumulated value of the starting node (XR i ) and the second integrated value (XC i ), and the first accumulated value of the end node (XR j) and the second integrated value (XC j The MX circuit 34 then executes the MX process for each of the N×N directed edges to obtain the momentum variable (Y i,j ) and write it to memory 21.

[0190] FIG. 14 is a diagram showing the order in which variables and values ​​are read by the TE circuit 31.

[0191] The TE circuit 31 reads the position matrix (X mem ) one by one from the position variable (x in That is, the TE circuit 31 reads out the position variable (X 1,1 ), a 1-by-2 location variable (X 1,2 ), …, the location variable in the Nth row (N-1) column (X N,N-1 ), the N-by-N location variable (X N,N ), one by one for the position variable (x in In this case, the TE circuit 31 reads the position variable (x in ) is read.

[0192] In addition, the TE circuit 31 calculates the momentum matrix (Y mem ) to find the momentum variable (y in ) stored in the W memory circuit 43 one by one. mem ) to find the weight value (w in ) stored in the Z memory circuit 44 one by one. mem ) to the row and column numbers that are the same as the position variable, in ) one by one.

[0193] Then, the TE circuit 31 performs pipeline processing to update the position variable (x out) and the updated momentum variable (y out ) and writes it to the X memory circuit 41 and the Y memory circuit 42. That is, the TE circuit 31 generates the position variable (X i,j ) and other data sets are read, and then a certain pipeline latency (λ TE ) the updated position variable (X i,j ) and the momentum variable (Y i,j ) to the X memory circuit 41 and the Y memory circuit 42. Note that the TE circuit 31 writes the updated position variable (X i,j ) is also written into the XT memory circuit 47 with the rows and columns reversed.

[0194] FIG. 15 is a diagram showing the order in which variables and values ​​are read by the MX circuit 34. As shown in FIG.

[0195] The MX circuit 34 reads the position matrix (X mem ) one by one from the position variable (x in That is, the MX circuit 34 reads out the position variable (X 1,1 ), a 1-by-2 location variable (X 1,2 ), …, the location variable in the Nth row (N-1) column (X N,N-1 ), the N-by-N location variable (X N,N ), one by one for the position variable (x in In this case, the MX circuit 34 reads the position variable (x in ) is read.

[0196] In addition, the MX circuit 34 calculates the momentum matrix (Y mem ) to find the momentum variable (y in In addition, the MX circuit 34 reads out the inversion position matrix (XT mem ) to the inverted position variable (xt in ) is read.

[0197] In addition, the MX circuit 34 reads the first integrated value array (XR mem ) to the first integrated value (wri in ), and the first integrated value (wrj in In addition, the MX circuit 34 reads out the second integrated value array (XC mem ) to the second integrated value (wci in ), and the second integrated value (wcj in ) is read out.

[0198] Then, the MX circuit 34 performs pipeline processing to update the momentum variable (y out ) and writes it to the Y memory circuit 42. That is, the MX circuit 34 generates the position variable (X i,j ) and other data sets are read, and then a certain pipeline latency (λ MX ) the updated momentum variable (Y i,j ) is written into the Y memory circuit 42.

[0199] 16 is a diagram showing the timing of the TE process, the MX process, and the GC process. The searching device 10 repeatedly executes the TE process, the MX process, and the GC process a predetermined number of times.

[0200] The TE circuit 31 sequentially reads out the position variables and momentum variables at the immediately preceding time from the memory 21 for each directed edge, calculates the position variables at the target time and the momentum variables at the target time during the update for each directed edge, and writes them to the memory 21. Therefore, the TE circuit 31 calculates the first position variable (the position variable in the first row and first column (X 1,1 The TE circuit 31 reads the last position variable (the position variable (X N,N The time required to write the data in the memory 21 is (N×N+λ TE) clock cycles. In this way, since the TE circuit 31 executes pipeline processing, the TE processing is performed in one step for (N×N+λ TE ) clock cycles.

[0201] The MX circuit 34 sequentially reads out the position variable at the target time and the momentum variable at the target time during the update from the memory 21 for each directed edge, calculates the momentum variable at the target time after the update for each directed edge, and writes it to the memory 21. Therefore, the MX circuit 34 calculates the first position variable (the position variable in the first row and first column (X 1,1 From the timing when the MX circuit 34 reads out the last momentum variable (the momentum variable (Y N,N The time required to write the data in the memory 21 is (N×N+λ MX ) clock cycles. In this way, since the MX circuit 34 executes pipeline processing, the MX processing is performed in one step in (N×N+λ MX ) clock cycles.

[0202] The GC circuit 32 sequentially obtains the position variable at the target time for each directed edge from the TE circuit 31 or the memory 21, calculates the first and second integrated values ​​for each node, and writes them to the memory 21. The GC circuit 32 also executes pipeline processing in the same way. The pipeline latency in the GC circuit 32 is λ GC Therefore, the GC circuit 32 performs GC processing for (N×N+λ GC ) clock cycles.

[0203] Here, the GC circuit 32 can execute the GC process in parallel with the TE process. However, the GC circuit 32 does not execute the TE process because the TE circuit 31 does not execute the first position variable (the position variable in the first row and first column (X 1,1 )) and then starts GC processing. Therefore, the GC circuit 32 outputs λ TE After the TE process has ended, the GC circuit 32 starts the GC process. GC After this time has elapsed, the GC process ends.

[0204] The MX circuit 34 executes the MX processing after the TE processing and the GC processing are completed. That is, the MX circuit 34 executes the MX processing so as not to overlap with the period during which the TE circuit 31 executes the TE processing. In other words, the TE circuit 31 executes the TE processing so as not to overlap with the period during which the MX circuit 34 executes the MX processing. Similarly, the MX circuit 34 executes the MX processing so as not to overlap with the period during which the GC circuit 32 executes the GC processing. In other words, the GC circuit 32 executes the GC processing so as not to overlap with the period during which the MX circuit 34 executes the MX processing. Therefore, the MX circuit 34 starts the MX processing from λ after the GC circuit 32 executes the GC processing, that is, after the TE processing is completed. GC After this time has elapsed, MX processing begins.

[0205] The CC circuit 33 also performs pipeline processing. The pipeline latency in the CC circuit 33 is λ CC Therefore, the CC circuit 33 performs CC processing in one step (N×N+λ CC ) clock cycles.

[0206] The CC circuit 33 can execute the CC processing in parallel with the TE processing. Also, the MX circuit 34 can execute the MX processing even if the CC processing is not completed. Therefore, the CC circuit 33 may execute the CC processing in parallel with the MX processing, as long as the CC processing can be completed at least by the time the MX processing is completed.

[0207] From the above, the processing time for one step by the search device 10 is {2(N×N)+λ TE +λ GC +λ MX} clock cycles. STEP When the steps are repeated N times, the total processing time by the search device 10 is STEP ×{2(N×N)+λ TE +λ GC +λ MX} clock cycles. If N is sufficiently large, the total processing time by the search device 10 is NSTEP ×2(N×N).

[0208] FIG. 17 is a diagram showing a configuration of the TE circuit 31. As shown in FIG.

[0209] The TE circuit 31 calculates the position variable (x in ), and the momentum variable at the previous time (y in ) for each clock cycle. in ) and the unselectable flag (z in ) to get the

[0210] In addition, the TE circuit 31 calculates the position variable (x out ) for each clock cycle. The TE circuit 31 also outputs the momentum variable (y out ) to output.

[0211] The TE circuit 31 includes a position update circuit 51, a limit circuit 52, a momentum update circuit 53, and a mask circuit .

[0212] The position update circuit 51 includes an FY circuit 57 and a first adder 58 .

[0213] The FY circuit 57 calculates the momentum variable (y in The FY circuit 57 obtains the momentum variable (y in ) to calculate the position update amount (dx), where dt is a constant representing unit time. dx=FY(y in )=y in ×dt…(61)

[0214] The first adder 58 calculates the position variable (x in), and the position update amount (dx) output by the FY circuit 57. The first adder 58 calculates the position variable (x in ) and the position update amount (dx) to output the position variable (nx1) at the target time. nx1=x in +dx…(62)

[0215] The position update circuit 51 outputs a position variable (nx1) at a target time every clock cycle. Also, the position update circuit 51 outputs a momentum variable (y in ) is output as the momentum variable (ny1) at the previous time.

[0216] Such a position update circuit 51 can calculate the position variable of the corresponding directed edge at the target time for each of the multiple directed edges based on the position variable and momentum variable at the immediately preceding time. Therefore, the position update circuit 51 can integrate the position variable for each of the multiple directed edges over a unit time.

[0217] The limiting circuit 52 includes a first multiplexer 60 , a first comparator 61 , a second multiplexer 62 , a third multiplexer 63 , and a second comparator 64 .

[0218] The first multiplexer 60 selects +1 or 0 under the control of the first comparator 61, and outputs it as the position variable (nx2) at the target time. The first comparator 61 determines for each clock cycle whether the position variable (nx1) at the target time output from the position update circuit 51 is greater than 0.5. If nx1 is greater than 0.5, the first comparator 61 causes the first multiplexer 60 to output +1, and if nx1 is equal to or less than 0.5, the first comparator 61 causes the first multiplexer 60 to output 0.

[0219] The second multiplexer 62, in accordance with the control of the second comparator 64, selects the position variable (nx1) at the target time output from the position update circuit 51 or the position variable (nx2) at the target time output from the first multiplexer 60, and outputs it as the position variable (nx3) at the target time.

[0220] The third multiplexer 63 selects either the momentum variable (ny1) at the immediately preceding time output from the position update circuit 51 or 0 according to the control of the second comparator 64, and outputs it as the momentum variable (ny2) at the immediately preceding time.

[0221] The second comparator 64 determines, for each clock cycle, whether the position variable (nx1) at the target time output from the position update circuit 51 is greater than 1 or less than 0, or whether the position variable (nx1) at the target time output from the position update circuit 51 is greater than 0 and less than 1.

[0222] When nx1 is equal to or greater than 0 and equal to or less than 1, the second comparator 64 causes the second multiplexer 62 to select the position variable (nx1) at the target time output from the position update circuit 51, and output it as the position variable (nx3) at the target time. Furthermore, when nx1 is equal to or greater than 0 and equal to or less than 1, the second comparator 64 causes the third multiplexer 63 to select the momentum variable (ny1) at the immediately preceding time output from the position update circuit 51, and output it as the momentum variable (ny2) at the immediately preceding time.

[0223] If nx1 is greater than 1 or less than 0, the second comparator 64 causes the second multiplexer 62 to select the position variable (nx2) at the target time output from the first multiplexer 60 and output it as the position variable (nx3) at the target time. Furthermore, if nx1 is greater than 1 or less than 0, the second comparator 64 causes the third multiplexer 63 to select 0 and output it as the momentum variable (ny2) at the immediately preceding time.

[0224] Such a limiting circuit 52 can, for each unit time, correct the position variable at a target time for each of a plurality of directed edges to 0 if the position variable of the corresponding directed edge at the target time is smaller than 0, and can correct the position variable at the target time to 1 if the position variable is larger than 1. Furthermore, for each of a plurality of directed edges, if the position variable at the target time is smaller than 0 or larger than 1, the limiting circuit 52 can correct the momentum variable at the immediately preceding time to 0.

[0225] The momentum updating circuit 53 includes an FX circuit 65, a FW circuit 66, and a second adder 67.

[0226] The FX circuit 65 acquires, for each clock cycle, the position variable (nx3) at the target time output from the limiting circuit 52. The FX circuit 65 calculates, for each clock cycle, the first momentum update amount (dy1) by executing the operation of equation (63) on the position variable (nx3) at the target time. dy1=FX(nx3)=-dt×(1-p)×(nx3-x0)…(63)

[0227] Note that p is a parameter that increases monotonically for each unit time, and is 0 at the initial time and 1 at the end time. x0 is a position variable at the initial time.

[0228] The FW circuit 66 calculates the weight value (w in The FW circuit 66 obtains a weight value (w in ) to calculate the second momentum update amount (dy2). dy2 = FW(w in )=-dt×M C ×[p×w in -(1-p)×w0]…(64)

[0229] In addition, w o is expressed by equation (65). w o =-(M P / M C)×x0×(2×N-3)…(65)

[0230] M P and M. C is a predetermined constant, and N is the number of nodes in the directed graph.

[0231] The second adder 67 acquires, for each clock cycle, the momentum variable (ny2) at the immediately preceding time output from the limiting circuit 52, the first momentum update amount (dy1) output from the FX circuit 65, and the second momentum update amount (dy2) output from the FW circuit 66. The second adder 67 outputs the momentum variable (ny3) at the target time by adding, for each clock cycle, the position variable (ny2) at the immediately preceding time, the first momentum update amount (dy1), and the second momentum update amount (dy2), as shown in equation (66). ny3 = ny2 + dy1 + dy2 … (66)

[0232] The momentum update circuit 53 outputs the momentum variable (ny3) at the target time for each clock cycle.

[0233] Such a momentum update circuit 53 can calculate the momentum variable of the corresponding directed edge at the target time for each of the multiple directed edges based on the momentum variable at the immediately preceding time, the position variable of the corresponding directed edge at the target time, and the weight value assigned to the corresponding directed edge. This allows the momentum update circuit 53 to execute the calculation of the integral of the momentum variable for a unit time up to the middle stage for each of the multiple directed edges.

[0234] The mask circuit 54 includes a fourth multiplexer 68 and a fifth multiplexer 69 .

[0235] The fourth multiplexer 68 outputs a non-selectable flag (z in The fourth multiplexer 68 obtains a non-selectable flag (z in) is 0, the position variable (nx3) at the target time output from the limiting circuit 52 is converted into the position variable (x out ) The fourth multiplexer 68 also outputs a selection disable flag (z in ) is 1, then we assign 0 to the position variable (x out )

[0236] The fifth multiplexer 69 outputs a non-selectable flag (z in The fifth multiplexer 69 obtains a non-selectable flag (z in ) is 0, the momentum variable (ny3) at the target time output from the momentum update circuit 53 is converted into the momentum variable (y out ) and outputs the selection disabled flag (z in ) is 1, then set 0 to the momentum variable after TE processing (y out )

[0237] Such a mask circuit 54 can replace, for each of a plurality of directed edges, the position variable at the target time and the momentum variable at the target time with a predetermined value of 0 if the unselectable flag of the corresponding directed edge indicates that it is unselectable.

[0238] Fig. 18 is a diagram showing the configuration of the GC circuit 32, together with the XR memory circuit 45 and the XC memory circuit 46. Fig. 19 is a diagram showing the order in which the GC circuit 32 acquires position variables and the order in which the first integrated value and the second integrated value are calculated.

[0239] The GC circuit 32 calculates the position variable (x in More specifically, the GC circuit 32 obtains a position variable (X 1,1 ) to the N-row N-column location variable (X N,N ), the position variable after TE processing (x in) to get the

[0240] The GC circuit 32 includes a row-wise accumulating circuit 71 (ACC(r)), N sixth multiplexers 72, N third comparators 73, and N column-wise accumulating circuits 74 (ACC(c)).

[0241] The row-direction accumulating circuit 71 calculates the position variable (x in The row-wise accumulating circuit 71 obtains the obtained position variable (x in In this case, the row-wise accumulating circuit 71 accumulates the position variables for each row, that is, for every N rows, as shown in FIG.

[0242] The row-wise accumulation circuit 71 converts the calculated accumulated value into a first integrated value (xr out ) in the row direction. As a result, the row direction accumulation circuit 71 outputs N first accumulated values ​​(xr out The row-wise accumulating circuit 71 calculates the N first integrated values ​​(xr out ) are stored in the XR memory circuit 45. mem ) as an element of the corresponding array number.

[0243] The N sixth multiplexers 72 correspond to the N columns. Each of the N sixth multiplexers 72 receives a position variable (x in Each of the N sixth multiplexers 72 obtains the obtained position variable (x in ) or 0.

[0244] The N third comparators 73 correspond to the N columns. Each of the N third comparators 73 calculates the obtained position variable (x in Each of the N third comparators 73 judges whether the column number of the acquired position variable (x in) is the corresponding column, the corresponding sixth multiplexer 72 is input with the position variable (x in Each of the N third comparators 73 outputs the obtained position variable (x in ) is not the corresponding column, it causes the corresponding sixth multiplexer 72 to output 0.

[0245] The N column-wise accumulating circuits 74 correspond to the N columns. Each of the N column-wise accumulating circuits 74 accumulates all the position variables (N×N clock cycles' worth of position variables (x in Each of the N sixth multiplexers 72 outputs the position variables other than the corresponding column as 0. Therefore, each of the N column-wise accumulating circuits 74 accumulates the N position variables (x in ) can be accumulated and the accumulated value can be output.

[0246] Each of the N column-wise accumulation circuits 74 converts the calculated accumulated value into the second accumulation value (xc out Each of the N column-wise accumulation circuits 74 outputs the calculated second accumulated value (xc out ) is added to the second integrated value array (XC mem ) as an element of the corresponding array number.

[0247] FIG. 20 is a diagram showing the configuration of the MX circuit 34. As shown in FIG.

[0248] The MX circuit 34 calculates the position variable (x in ), the inversion position variable after TE processing (xt in ) and the momentum variable after TE processing (y in In addition, the MX circuit 34 obtains a position variable (x in The first integral value (xri in ), and the position variable (x in The first cumulative value (xrj inIn addition, the MX circuit 34 obtains a position variable (x in The second cumulative value (xci in ), and the position variable (x in The second cumulative value (xcj in ) to get the

[0249] Then, the MX circuit 34 calculates the momentum variable (y out ) to output.

[0250] The MX circuit 34 includes an FM circuit 77 and a third adder 78 .

[0251] The FM circuit 77 includes a first multiplier 79, a second multiplier 80, a third multiplier 81, a first subtractor 82, a second subtractor 83, a third subtractor 84, a first internal adder 85, a second internal adder 86, and a fourth multiplier 87.

[0252] The first multiplier 79 outputs the first integrated value (xri in The second multiplier 80 multiplies the second integrated value (xcj in ) by 2. The third multiplier 81 multiplies the position variable (x in ) by 2.

[0253] The first subtractor 82 subtracts the output value (2×(xri in )) to the second integrated value (xci in The second subtractor 83 subtracts the output value (2×(xcj in )) to the first integrated value (xrj in The third subtractor 84 subtracts the inversion position variable (xt in ), the output value of the third multiplier 81 (2 × (x in )) is subtracted.

[0254] The first internal adder 85 adds the output value of the first subtractor 82 and the output value of the second subtractor 83. The second internal adder 86 adds the output value of the first internal adder 85 and the output value of the third subtractor 84. The fourth multiplier 87 multiplies the output value of the second internal adder 86 by dt×M P Multiply by.

[0255] The FM circuit 77 as described above calculates the third momentum update amount (dy3) by executing the operation of equation (67) for each clock cycle. dy3=dt×M P ×{2×xri in +2×xcj in -xci in -xrj in +xt in -2×(x in )}…(67)

[0256] The third adder 78 calculates the momentum variable (y in ) and the third momentum update amount (dy3) output by the FM circuit 77. The third adder 78 obtains the momentum variable (y in ) and the third momentum update (dy3), the momentum variable (y out ) to output. y out =y in +dy3…(68)

[0257] Such an MX circuit 34 can further update, for each of a plurality of directed edges, the momentum variable of the corresponding directed edge at the target time after being updated by the TE circuit 31, according to the first and second integrated values ​​of the end node, the first and second integrated values ​​of the start node, the position variable of the corresponding directed edge at the target time, and the position variable of the corresponding directed edge in the opposite direction to the corresponding directed edge at the target time. In this way, the MX circuit 34 can integrate, for each of a plurality of directed edges, the momentum variable time-integrated by the TE circuit 31 up to the intermediate stage, for a unit time up to the final stage.

[0258] 21 is a diagram showing the configuration of the normalization circuit 26. The normalization circuit 26 receives a plurality of weight values ​​(w in ) is written, the weight values ​​(w in ) to get the

[0259] The normalization circuit 26 includes an error minimization section 90 and a maximum value adjustment section 91 .

[0260] The error minimization unit 90 calculates the exchange rate from the i-th node to the j-th node as r i,j If the exchange rate is r i,j ´=(a i / a j )×r i,j Each of the weight values ​​is corrected so that i is the coefficient set for the i-th node. j is the coefficient set for the jth node.

[0261] When calculating a solution to an arbitrage problem, the search device 10 searches for a closed path as the optimal path. Therefore, when all exchange rates assigned to the directed edges included in the closed path are multiplied, a is canceled, so even if such a correction is made, the total weight value of the optimal path does not change.

[0262] Also, r i,j When a′ is close to 1, the search device 10 can calculate the total weight value with high accuracy. i and a j is r i,j The weight value is preset so that w′ is close to 1. In this embodiment, the weight value is i,j =-log(r i,j ) In this embodiment, therefore, w' i,j =-log(a i / a j (r i,j ) is preset so that it is close to 0.

[0263] w´ i,j is as close to 0 as possible i and a j For example, by using the least squares method, w´ i,j It can be calculated by minimizing the sum of squares of w' i,j is as close to 0 as possible i and a j can be derived by minimizing equation (71).

[0264]

number

[0265] α where equation (71) is minimized i and α j can be calculated by solving the simultaneous equations of equation (72).

[0266]

number

[0267] The error minimization unit 90 calculates a coefficient (a i ) is preset. The coefficient (a i ) is calculated in advance by solving the simultaneous equations of equation (72), for example.

[0268] Maximum value adjustment section 91 acquires the multiple weight values ​​corrected by error minimization section 90. Maximum value adjustment section 91 normalizes each of the multiple weight values ​​based on the maximum absolute value (absmax) of the multiple weight values.

[0269] More specifically, the maximum value adjustment unit 91 detects the maximum absolute value (absmax) from the corrected weight values. Then, the maximum value adjustment unit 91 divides the corrected weight values ​​by the maximum absolute value (absmax). In this way, the maximum value adjustment unit 91 can normalize the weight values ​​so that the maximum absolute value becomes 1.

[0270] The normalization circuit 26 calculates the multiple weight values ​​(w out ) into the W memory circuit 43 in the memory 21. The normalization circuit 26 also writes the maximum absolute value (absmax) detected by the maximum value adjustment unit 91 into the maximum value memory circuit 48 in the memory 21.

[0271] Such a normalization circuit 26 normalizes a plurality of weight values, thereby enabling the sum of the weights to be calculated with high accuracy.

[0272] FIG. 22 is a diagram showing a configuration of the CC circuit 33. As shown in FIG.

[0273] The CC circuit 33 calculates the position variable (x in More specifically, the CC circuit 33 acquires the position matrix (X mem ) one by one from the position variable (x in The CC circuit 33 reads out the position variable (x in ) may be obtained.

[0274] The CC circuit 33 calculates the position variable (x in ) and the weight value (w in More specifically, the CC circuit 33 acquires the weighting value matrix (W mem ) one by one from the weight value (w in ) is read.

[0275] The CC circuit 33 includes a seventh multiplexer 101, a fourth comparator 102, an eighth multiplexer 103, a first accumulator 104, a ninth multiplexer 105, a fifth comparator 106, N tenth multiplexers 107, N sixth comparators 108, N second accumulators 109, N eleventh multiplexers 110, N seventh comparators 111, N third accumulators 112, a twelfth multiplexer 113, a decision circuit 114, and an exponentiation circuit 115.

[0276] The seventh multiplexer 101 outputs 0 or 1 under the control of the fourth comparator 102 every clock cycle.

[0277] The fourth comparator 102 calculates the position variable (x in The fourth comparator 102 obtains the obtained position variable (x in The fourth comparator 102 determines whether the position variable (x in If x is greater than 0.5, the seventh multiplexer 101 outputs a 1, and the position variable (x in ) is equal to or less than 0.5, the seventh multiplexer 101 outputs 0. That is, the fourth comparator 102 outputs the position variable (x in ) is binarized using a threshold and the resulting bit (b) is output.

[0278] The eighth multiplexer 103 selects a weight value (w in ) or 0. More specifically, the eighth multiplexer 103 outputs the weight value (w in ) and outputs 0 if bit (b) is 0. That is, the eighth multiplexer 103 outputs a weight value (w in ) and outputs 0 if it is not included in the optimal route.

[0279] The first accumulator 104 accumulates the weight values ​​output from the eighth multiplexer 103 for each clock cycle. More specifically, the first accumulator 104 accumulates the weight values ​​for N×N clock cycles from row 1, column 1 to row N, column N. The eighth multiplexer 103 outputs the weight value of a directed edge not included in the optimal path as 0. Therefore, the first accumulator 104 can accumulate the weight values ​​corresponding to all directed edges selected as the optimal path. That is, the first accumulator 104 can generate the total weight value of all directed edges selected as the optimal path. After completing the processing of N×N clock cycles from row 1, column 1 to row N, column N, the first accumulator 104 outputs the accumulated weight value as the total weight value (cost).

[0280] The ninth multiplexer 105 obtains, for each clock cycle, the bit (b) output from the seventh multiplexer 101. The ninth multiplexer 105 outputs the bit (b) or 0 under the control of the fifth comparator .

[0281] The fifth comparator 106 calculates the position variable (x in ) and obtains the row number and column number of the first multiplexer 105. The fifth comparator 106 determines whether the row number and column number match. If the row number and column number match, the fifth comparator 106 causes the ninth multiplexer 105 to output 0 for each clock cycle, and if the row number and column number do not match, the fifth comparator 106 causes the ninth multiplexer 105 to output bit (b). That is, if the row number and column number match, the fifth comparator 106 sets bit (b) to 0 since there is no directed edge.

[0282] The N tenth multiplexers 107 correspond to the N rows. Each of the N tenth multiplexers 107 acquires the bit (b) output from the ninth multiplexer 105 for each clock cycle. Each of the N tenth multiplexers 107 outputs the acquired bit (b) or 0 according to the control of the corresponding sixth comparator 108.

[0283] The N sixth comparators 108 are associated with the N rows. Each of the N sixth comparators 108 determines whether the row number of the acquired bit (b) is the corresponding row for each clock cycle. If the row number of the acquired bit (b) is the corresponding row, each of the N sixth comparators 108 causes the corresponding tenth multiplexer 107 to output bit (b). If the row number of the acquired bit (b) is not the corresponding row, each of the N sixth comparators 108 causes the corresponding tenth multiplexer 107 to output 0.

[0284] The N second accumulating adders 109 correspond to the N rows. Each of the N second accumulating adders 109 accumulates all bits (N×N clock cycles worth of bits (b)) output from the corresponding tenth multiplexer 107. Each of the N tenth multiplexers 107 outputs position variables other than the corresponding row as 0. Therefore, each of the N second accumulating adders 109 accumulates the bit (b) in the clock cycle in which the bit (b) included in the corresponding row is acquired. This allows each of the N second accumulating adders 109 to output a row-wise accumulated value (xr_b[k]) obtained by accumulating the N bits (b) included in the corresponding row. Here, k is any integer from 1 to N.

[0285] The N eleventh multiplexers 110 correspond to the N columns. Each of the N eleventh multiplexers 110 acquires the bit (b) output from the ninth multiplexer 105 for each clock cycle. Each of the N eleventh multiplexers 110 outputs the acquired bit (b) or 0 according to the control of the corresponding seventh comparator 111.

[0286] The N seventh comparators 111 are associated with the N columns. Each of the N seventh comparators 111 determines whether the column number of the acquired bit (b) is the corresponding column for each clock cycle. If the column number of the acquired bit (b) is the corresponding column, each of the N seventh comparators 111 causes the corresponding eleventh multiplexer 110 to output bit (b). If the column number of the acquired bit (b) is not the corresponding column, each of the N seventh comparators 111 causes the corresponding eleventh multiplexer 110 to output 0.

[0287] The N third accumulators 112 correspond to the N columns. Each of the N third accumulators 112 accumulates all bits (N×N clock cycles worth of bits (b)) output from the corresponding eleventh multiplexer 110. Each of the N eleventh multiplexers 110 outputs position variables other than the corresponding column as 0. Therefore, each of the N third accumulators 112 accumulates the bit (b) in the clock cycle in which the bit (b) included in the corresponding column is acquired. As a result, each of the N third accumulators 112 can output a column-wise accumulated value (xc_b[k]) obtained by accumulating the N bits (b) included in the corresponding column.

[0288] After completing the processing of N×N clock cycles from row 1, column 1 to row N, column N, the 12th multiplexer 113 outputs the sum of the weights (cost) output from the first accumulator 104 or 0, according to the control of the decision circuit 114.

[0289] After completing N×N clock cycles of processing from row 1, column 1 to row N, column N, the decision circuit 114 decides whether or not the optimal path is a closed path based on the N row-wise accumulated values ​​(xr_b[k]) and the N column-wise accumulated values ​​(xc_b[k]).

[0290] For example, the decision circuit 114 decides that a closed path is not formed if the formula (81) is satisfied, and decides that a closed path is formed if the formula (81) is not satisfied.

[0291]

number

[0292] The formula (81) is a decision formula for determining whether any of (xr_b[k]>1), (xc_b[k]>1), or (xr_b[k]!=xc_b[k]) is satisfied.

[0293] (xr_b[k]>1) means that if at least one of the N row-wise accumulated values ​​(xr_b[k]) is greater than 1 (i.e., 2 or greater), then no cycle is formed.

[0294] (xc_b[k]>1) means that if at least one of the N column-wise accumulated values ​​(xc_b[k]) is greater than 1 (i.e., 2 or greater), then no cycle is formed.

[0295] (xr_b[k]!=xc_b[k]) means that if the row-wise accumulated value (xr_b[k]) and the column-wise accumulated value (xc_b[k]), which have the same row number and column number, are not identical, they do not form a cycle.

[0296] If the decision circuit 114 determines that the optimal route is a closed path, it causes the sum of the weights (cost) to be output from the twelfth multiplexer 113. If the decision circuit 114 determines that the optimal route is not a closed path, it causes the twelfth multiplexer 113 to output 0.

[0297] After completing the processing of N×N clock cycles from row 1, column 1 to row N, column N, the exponentiation circuit 115 executes the operation of the following equation (82).

[0298]

number

[0299] That is, the power circuit 115 performs an exponentiation operation on the value obtained by multiplying the sum of the weights (cost) and the maximum absolute value (absmax) by -1, with the exponent being 10. In this way, the power circuit 115 can calculate the total rate (sol) obtained when exchanges corresponding to two or more directed edges included in the optimal route are made.

[0300] (Pseudocode) Fig. 23 is a diagram showing a first main pseudo code 1111. Fig. 24 is a diagram showing a second main pseudo code 1112 following the first main pseudo code 1111. As an example, the searching device 10 executes the pseudo codes shown in Figs. 23 and 24 in the order of line numbers.

[0301] Line 10 is the code that assigns 0 to p and ph.

[0302] Line 11 is the code that repeats lines 11 to 58. Line 11 is the code that assigns 1 to ncycle in the first loop, adds 1 to ncycle for each loop, and executes the process repeatedly under the condition that ncycle is less than or equal to Ncycle.

[0303] Lines 12 and 13 are code fragments that add dp to p and dph to ph. Line 14 is code fragments that assign 0 to cost. Lines 15 and 16 are code fragments that assign 0 to arrays xr_b[node] and xc_b[node].

[0304] Line 17 is the code that repeats lines 17 to 48. Line 17 assigns 0 to i in the first loop, adds 1 to i for each loop, and executes the process repeatedly under the condition that i is smaller than node.

[0305] Line 18 is the code that repeats lines 18 to 47. Line 18 assigns 0 to j in the first loop, adds 1 to j for each loop, and executes the process repeatedly under the condition that j is smaller than node.

[0306] Line 19 is the code that causes xout and yout to be defined.

[0307] Line 21 is the code that calls and executes the TE function. The TE function is a function that executes TE processing. Line 21 is the code that passes X[i][j], Y[i][j], w[i][j], and z[i][j] to the TE function, and receives xout and yout from the TE function. X[i][j] is the position variable of row i, column j. Y[i][j] is the momentum variable of row i, column j. w[i][j] is the weight value of row i, column j. z[i][j] is the non-selectable flag of row i, column j.

[0308] Lines 23, 24, and 25 are the code that stores xout in X[i][j], xout in XT[j][i], and yout in Y[i][j]. XT[j][i] is the inversion position variable for row j and column i.

[0309] Lines 27 and 28 are a block of code that executes GC processing. Line 27 is code that executes the process of adding xout to XR[i], provided that i = j is not true. Line 28 is code that executes the process of adding xout to XC[j], provided that j = i is not true. XR[i] is the first accumulated value for the i-th node. XC[j] is the second accumulated value for the j-th node.

[0310] Lines 30 to 46 are the code that executes CC processing. Lines 30 and 31 are the code that executes the process of substituting true for b if xout is greater than 0.5, substituting false for b if it is not greater than 0.5, and substituting false for b if i=j regardless of xout.

[0311] Lines 32 to 35 are a group of codes that, if b is true, add w[i][j] to cost, add 1 to xr_b[i], and add 1 to array xc_b[j].

[0312] Line 37 is the code that executes the process of assigning false to the constraint.

[0313] Line 38 is the code that repeats lines 38 to 42. Line 38 assigns 0 to k in the first loop, adds 1 to k for each loop, and executes the loop on the condition that k is smaller than node.

[0314] Line 39 is the code that determines whether any of the following is satisfied: (xr_b[k]>1), (xc_b[k]>1), or (xr_b[k]!=xc_b[k]). Line 40 is the code that executes the process of assigning true to the constraint if the code in line 39 is satisfied.

[0315] Lines 43 and 44 are the code that executes the process of substituting 0 for cost if the constraint is true.

[0316] Line 46 is the code that multiplies the cost by the maximum absolute value (absmax) and then multiplies the result by -1, and raises the power of 10. sol represents the total rate obtained when making exchanges corresponding to two or more directed edges included in the optimal path.

[0317] Line 49 is the code that repeats lines 49 to 57. Line 49 assigns 0 to i in the first loop, adds 1 to i for each loop, and executes the loop on the condition that i is smaller than node.

[0318] Line 50 is the code that repeats lines 50 to 56. Line 50 assigns 0 to j in the first loop, adds 1 to j for each loop, and executes the loop on the condition that j is smaller than node.

[0319] Line 51 is the code that defines yout.

[0320] Line 53 is code that calls and executes the MX function. The MX function is a function that executes the process of MX processing that corresponds to the FM circuit 77. Line 53 is code that passes XR[i], XC[j], XC[i], XR[j], XT[i][j], and X[i][j] to the MX function, and receives yout from the MX function.

[0321] Line 55 is the code that subtracts yout from Y[i][j].

[0322] Fig. 25 is a diagram showing the TE pseudo code 1113. When the TE function is called in line 21, the searching device 10 executes the pseudo code shown in Fig. 25 in numerical order.

[0323] Line 111 is the code that defines the function that receives xin, yin, win, and zin, and outputs xout and yout. Note that xin is assigned X[i][j]. yin is assigned Y[i][j]. win is assigned w[i][j]. zin is assigned z[i][j].

[0324] Lines 112 and 113 are code that defines nx1, nx2, nx3, ny1, ny2, and ny3. Line 115 is code that executes the process of substituting yin for ny1. Line 116 is code that calculates xin+dt×yin and substitutes the result of the calculation for nx1.

[0325] Line 118 is code that assigns 1 to nx2 if nx1 is greater than 0.5, and assigns 0 to nx2 if nx1 is 0.5 or less.

[0326] Lines 120 to 122 are a block of code that, if nx1 is greater than 1 or less than 0, assigns nx2 to nx3 and 0 to ny1. Lines 123 to 125 are a block of code that, if nx1 is greater than 0 and less than 1, assigns nx1 to nx3 and ny1 to ny2.

[0327] Line 129 is the code that calculates {ny2-dt×(1-p)×(nx3-x0)-dt×Mc×(ph×win+(1-ph)×w0)} and assigns the result to ny3. Note that dt, x0, Mc, and w0 are predetermined constants.

[0328] Line 130 is code that assigns 0 to xout if zin is true, and assigns nx3 to xout if zin is false. Line 131 is code that assigns 0 to yout if zin is true, and assigns ny3 to yout if zin is false.

[0329] Fig. 26 is a diagram showing the MX pseudo code 1114. When the MX function is called in line 53, the searching device 10 executes the pseudo code shown in Fig. 26 in numerical order.

[0330] Line 211 is the code that defines receiving XRi, XCj, XCi, XRj, XTij, and Xij, and outputting yout. Note that XRi is assigned XR[i]. XCj is assigned XC[j]. XCi is assigned XC[i]. XRj is assigned XR[j]. XTij is assigned XT[i][j]. Xij is assigned X[i][j].

[0331] Line 212 is code that calculates dt×Mp×{2×XRi+2×XCj-XCi-XRj+XTij-2×Xij} and assigns the calculation result to yout. Note that Mp is a predetermined constant.

[0332] (parallelization) FIG. 27 is a diagram showing a TE circuit 31 in parallel.

[0333] The TE circuit 31 may include multiple sub TE circuits 210 (multiple sub self-developing circuits). The TE circuit 31 may include, for example, two or more and (N×N) or less sub TE circuits 210. The multiple sub TE circuits 210 have the same configuration as the TE circuit 31 and execute TE processing in parallel with each other.

[0334] Each of the multiple sub-TE circuits 210 reads out the position variable at the immediately preceding time, the momentum variable at the immediately preceding time, the weight value, and the non-selectable flag for a directed edge different from the other sub-TE circuits 210 among the multiple directed edges from the memory 21. Then, each of the multiple sub-TE circuits 210 executes TE processing for a directed edge different from the other sub-TE circuits 210 among the multiple directed edges, and then writes the position variable at the target time and the momentum variable at the target time being updated to the memory 21.

[0335] Furthermore, when the TE circuit 31 includes a plurality of sub-TE circuits 210, the memory 21 stores the position variable (X i,j ), momentum variable (Y i,j ), weight value (w i,j ) and the unselectable flag (z i,j) can be read out.

[0336] For example, the TE circuit 31 includes N sub TE circuits 210 corresponding to N rows in a matrix with N rows and N columns. By including N sub TE circuits 210, the TE circuit 31 can facilitate processing for reading and writing N×N position variables and the like.

[0337] In this case, the X memory circuit 41 includes N sub-X memory circuits 220 corresponding to the N rows. Each of the N sub-X memory circuits 220 stores N position variables (X i,j ) to remember.

[0338] Similarly, the Y memory circuit 42 includes N sub-Y memory circuits 222 corresponding to the N rows. Each of the N sub-Y memory circuits 222 stores the N momentum variables (Y i,j ) to remember.

[0339] Similarly, the W memory circuit 43 includes N sub-W memory circuits 224 corresponding to the N rows. Each of the N sub-W memory circuits 224 stores N weight values ​​(w i,j ) to remember.

[0340] Similarly, the Z memory circuit 44 includes N sub-Z memory circuits 226 corresponding to the N rows. Each of the N sub-Z memory circuits 226 stores N non-selectable flags (z i,j ) to remember.

[0341] Each of the N sub-TE circuits 210 receives a position variable (X i,j ), momentum variable (Y i,j ), weight value (w i,j ) and the unselectable flag (z i,j ) is read out. This allows the TE circuit 31 to perform TE processing on N rows in parallel.

[0342] FIG. 28 is a diagram showing the MX circuits 34 in parallel.

[0343] The MX circuit 34 may include a plurality of sub-MX circuits 230 (a plurality of sub-multi-body interaction circuits). The plurality of sub-MX circuits 230 may include, for example, two or more (N×N) or less sub-MX circuits 230. The plurality of sub-MX circuits 230 have the same configuration as the MX circuit 34 and execute MX processing in parallel with each other.

[0344] Each of the multiple sub-MX circuits 230 reads out from the memory 21 the position variable at the target time, the inverted position variable, and the momentum variable at the target time during the update for a directed edge of the multiple directed edges different from the other sub-MX circuits 230. Furthermore, each of the multiple sub-MX circuits 230 reads out from the memory 21 the first and second accumulated values ​​of the end node and the first and second accumulated values ​​of the start node for a directed edge of the multiple directed edges different from the other sub-MX circuits 230. Then, each of the multiple sub-MX circuits 230 writes the momentum variable at the target time after updating to the memory 21 after performing MX processing for a directed edge of the multiple directed edges different from the other sub-MX circuits 230.

[0345] Furthermore, when the MX circuit 34 includes multiple sub-MX circuits 230, the memory 21 stores the position variables (X i,j ), inversion position variable (XT j,i ), momentum variable (Y i,j ), the first accumulated value of the end node (XR i ) and the second integrated value (XC i ), and the first cumulative value of the start node (XR j ) and the second integrated value (XC j ), it includes a number of ports corresponding to a number of sub-MX circuits 230 so that it can read out the

[0346] For example, the MX circuit 34 includes N sub MX circuits 230 corresponding to N rows in a matrix with N rows and N columns. By including N sub MX circuits 230, the MX circuit 34 can facilitate processing for reading and writing N×N position variables, etc.

[0347] In this case, the X memory circuit 41 includes N sub X memory circuits 220 corresponding to the N rows, and the Y memory circuit 42 includes N sub Y memory circuits 222 corresponding to the N rows.

[0348] Further, the XR memory circuit 45 includes N sub-XR memory circuits 242 corresponding to the N rows. Each of the N sub-XR memory circuits 242 stores the first integrated value (XR i ) to remember.

[0349] The XC memory circuit 46 also includes N sub-XC memory circuits 244 corresponding to the N columns. Each of the N sub-XC memory circuits 244 stores the second integrated value (XC j ) to remember.

[0350] The XT memory circuit 47 includes N sub-XT memory circuits 246 corresponding to the N rows. Each of the N sub-XT memory circuits 246 stores N inversion position variables (XT j,i ) to remember.

[0351] Each of the N sub-MX circuits 230 receives a position variable (X i,j ), momentum variable (Y i,j ), and the inversion position variable (XT j,i Each of the N sub-MX circuits 230 also reads out the first integrated value (XR i ) and the second integrated value (XC i ), and the first cumulative value of the start node (XR j ) and the second integrated value (XCj ), which allows the MX circuit 34 to execute MX processing on N rows in parallel.

[0352] Fig. 29 is a diagram showing the configuration of the parallelized GC circuit 32, together with the XR memory circuit 45 and the XC memory circuit 46. Fig. 30 is a diagram showing the order in which the parallelized GC circuit 32 acquires position variables and the order in which the first integrated value and the second integrated value are calculated.

[0353] When the GC circuit 32 performs the TE process on N rows in parallel, the GC circuit 32 obtains N first integrated values ​​(xr out ) and N second accumulated values ​​(xc out In this case, the GC circuit 32 can calculate the N position variables (x in ) to get the

[0354] The parallelized GC circuit 32 includes N row-wise accumulators 262 , a sum adder 264 , and a demultiplexer 266 .

[0355] The N row-wise accumulators 262 correspond to the N rows. Each of the N row-wise accumulators 262 calculates the N position variables (x in )(N clock cycles of position variable (x in )) contained in the corresponding row. Thus, each of the N row-wise accumulators 262 accumulates the N position variables (x in ) can be accumulated and the accumulated value can be output.

[0356] Each of the N row-wise accumulators 262 converts the calculated accumulated value into the first accumulated value (xr out Each of the N row-wise accumulators 262 outputs the calculated first integrated value (xr out ) is written to the corresponding sub-XR memory circuit 242 included in the XR memory circuit 45.

[0357] The sum adder 264 adds N position variables (x in That is, the sum adder 264 sums the N position variables (x in 30, the sum adder 264 adds the N position variables (x in ) can be accumulated and the accumulated value can be output.

[0358] The demultiplexer 266 selects the N sub XC memory circuits 244 included in the XC memory circuit 46 one by one for each clock cycle. The demultiplexer 266 converts the sum output from the sum adder 264 into the second accumulated value (xc out Then, the demultiplexer 266 outputs the second accumulated value (xc out ) to write

[0359] FIG. 31 is a diagram showing the timing of TE processing and MX processing before and after parallelization.

[0360] When TE processing is performed in parallel for every N rows, the TE circuit 31 performs one step of processing as follows: (N+λ TE ) clock cycles. When MX processing is performed in parallel for every N rows, the MX circuit 34 performs processing for one step in (N+λ MX When GC processing is performed in parallel for every N rows, the GC circuit 32 performs processing for one step in (N+λ GC ) clock cycles.

[0361] Here, the GC circuit 32 can execute the GC processing in parallel with the TE processing. The MX circuit 34 starts the λ 2 processing after the GC circuit 32 executes the GC processing, that is, after the TE processing is completed. GC After this time has elapsed, MX processing begins.

[0362] From the above, the processing time for one step by the search device 10 parallelized for every N rows is {(2×N)+λ TE +λ GC +λ MX} clock cycles. STEP When the steps are repeated N times, the total processing time by the search device 10 is STEP ×{(2×N)+λ TE +λ GC +λ MX} clock cycles.

[0363] The search device 10 may perform parallel processing at a degree of parallelism other than every N rows. For example, the search device 10 may divide the entire processing into two or four. The search device 10 may also perform parallel processing by dividing the entire processing into N×N.

[0364] The search device 10 according to the second embodiment as described above can quickly output a solution to an optimal path problem for searching an optimal path in a directed graph with a simple configuration.

[0365] Third embodiment Next, an arbitrage trading system 300 according to the third embodiment will be described.

[0366] FIG. 32 is a diagram showing the configuration of an arbitrage trading system 300.

[0367] The arbitrage trading system 300 is an example of a search system incorporating the search device 10 according to the second embodiment described with reference to Fig. 7 to Fig. 31. In this embodiment, the arbitrage trading system 300 performs foreign exchange trading. However, the arbitrage trading system 300 may be applied to arbitrage trading of any kind, not limited to foreign exchange.

[0368] The arbitrage trading system 300 includes a search device 10 , a receiving device 312 , a UDP processing unit 314 , an input management device 316 , a trading device 318 , a TCP processing unit 320 , and a transmitting device 322 .

[0369] The searching device 10 is the device described with reference to Figures 7 to 31. For example, the searching device 10 is a semiconductor device implemented as a dedicated circuit in an FPGA, a gate array, an application specific integrated circuit, or the like.

[0370] Each of the multiple nodes in the directed graph searched by the search device 10 corresponds to a trading target of arbitrage trading. In this example, each of the multiple nodes corresponds to a currency.

[0371] In addition, each of the multiple directed edges corresponds to an exchange from a trading object corresponding to the start node to a trading object corresponding to the end node. In this example, each of the multiple directed edges corresponds to an exchange from a currency corresponding to the start node to a currency corresponding to the end node.

[0372] Each of the weights represents a logarithmic value of the exchange rate when an exchange corresponding to the assigned directed edge is made. In this example, the exchange rate when exchanging from a currency (i) corresponding to the start node to a currency (j) corresponding to the end node is expressed as r i,j Then, the weight value w i,j is -log(r i,j )

[0373] The search device 10 detects, as the optimal route, a closed path for which the cumulative sum of two or more weight values ​​assigned to the route is the smallest. i,j But +log(r i,j ), the search device 10 may detect, as the optimal route, a closed path for which the cumulative sum of two or more weight values ​​assigned to the route is the largest.

[0374] The search device 10 calculates a plurality of bits (b i,j ) is output as the search result of the optimal route. i,j ) represents 1 if the corresponding directed edge is included in the optimal path, and 0 if the corresponding directed edge is not included in the optimal path.

[0375] Furthermore, the search device 10 calculates a total rate (sol) when two or more exchanges corresponding to two or more directed edges included in the detected optimal path are made. The total rate (sol) is expressed as sol=Π(r i,j bi,j The total rate (sol) is expressed as sol=exp{Σ(w i,j ×b i,j )}.

[0376] In addition, the search device 10 searches for and outputs an optimal route at regular intervals. For example, the search device 10 searches for and outputs an optimal route at regular intervals (for example, N STEP ×{2(N×N)+λ TE +λ GC +λ MX} clock cycles). The searching device 10 may search for and output the optimal route when triggered by receiving an event packet.

[0377] The receiving device 312 receives an event packet from a market server via a network. The event packet includes information indicating a weight value assigned to at least one of the multiple directed edges. For example, the event packet includes an exchange rate corresponding to one of the directed edges.

[0378] In this example, the event packet includes header information, a pair ID, a selling price (Bid), and a buying price (Ask). The pair ID is identification information for identifying a pair of currency (i) and currency (j). Note that currency (i) is the currency corresponding to the i-th node of the directed graph. Also, currency (j) is the currency corresponding to the j-th node of the directed graph.

[0379] The selling price (Bid) is the exchange rate (r i,j ) The buying price (Ask) represents the exchange rate (r j,i ) and r j,i =1 / Ask. The selling price (Bid) and buying price (Ask) usually do not match.

[0380] The market server broadcasts the event packets at irregular intervals. The receiver 312 sequentially receives the event packets that are irregularly transmitted, and provides them to the UDP processor 314.

[0381] The UDP processing unit 314 processes the event packet provided by the receiving device 312 in accordance with a communication protocol, and extracts information identifying a directed edge and information indicating a weight value (e.g., an exchange rate) from the event packet.

[0382] In this example, the event packet is a packet conforming to the UDP (User Datagram Protocol) protocol. Therefore, in this example, the UDP processing unit 314 executes processing conforming to the UDP protocol to extract the pair ID, the selling price (Bid), and the buying price (Ask).

[0383] The input management device 316 internally stores a plurality of weight values ​​corresponding to a plurality of directed edges. Each time an event packet is received, the input management device 316 acquires information indicating a weight value to be assigned to at least one directed edge contained in the event packet from the UDP processing unit 314. The input management device 316 generates a weight value based on information contained in the acquired event packet and rewrites one of the plurality of stored weight values.

[0384] In this example, the input management device 316 acquires a pair ID, a selling price (Bid), and a buying price (Ask) from the UDP processing unit 314 every time an event packet is received. Every time an event packet is received, the input management device 316 performs a negative logarithm operation on the selling price (Bid) to obtain a weight value (w i,j ) and rewrites the corresponding weight value stored internally. In addition, the input management device 316 performs a positive logarithm operation on the selling price (Ask) every time an event packet is received, thereby generating a weight value (wj,i ) and rewrites the corresponding weight values ​​stored internally.

[0385] Then, the input management device 316 rewrites the weight values ​​stored in the memory 21 of the search device 10 at regular intervals. For example, when the search device 10 rewrites the weight values ​​at regular intervals (for example, N STEP ×{2(N×N)+λ TE +λ GC +λ MX} clock cycles). In this case, the input management device 316 executes the search process repeatedly for a predetermined time (for example, N STEP ×{2(N×N)+λ TE +λ GC +λ MX} clock cycles), the input management device 316 rewrites the multiple weight values ​​stored in the memory 21. i,j ) If none of these have changed, the rewriting process may be skipped.

[0386] Furthermore, the input management device 316 rewrites all of the weight values ​​stored in the search device 10 in a lump. For example, if the search device 10 stores N×N weight values, the input management device 316 rewrites all of the N×N weight values. For example, the input management device 316 and the search device 10 may be connected by N×N×Wdata wires. Here, Wdata is the number of bits required to represent one weight value. The input management device 316 may rewrite the N×N weight values ​​stored in the search device 10 in a lump in one clock cycle. This allows the input management device 316 to rewrite the weight values ​​stored in the search device 10 in a short time.

[0387] The trading device 318 receives a plurality of bits (b i,j ) and the total rate (sol). The transaction device 318 obtains a number of bits (b i,j) and the total rate (sol), the trading device 318 determines whether to execute an arbitrage transaction corresponding to two or more directed edges included in the optimal path. For example, the trading device 318 determines to execute an arbitrage transaction when the total rate (sol) is greater than a predetermined threshold.

[0388] When it is determined that arbitrage trading is to be performed, the trading device 318 generates an order packet instructing the execution of exchanges corresponding to the two or more directed edges selected as the optimal path. Note that the trading device 318 may generate an order packet for the subsequent directed edge after confirming a contract for any one of the directed edges for two or more exchanges corresponding to the two or more directed edges selected as the optimal path.

[0389] The TCP processing unit 320 performs information processing according to a communication protocol on the order packet generated by the trading device 318. In this example, the order packet is a packet that conforms to the TCP (Transmission Control Protocol). Therefore, the TCP processing unit 320 includes the order packet in a packet that conforms to the TCP protocol.

[0390] The transmitting device 322 transmits the order packet output from the TCP processing unit 320 via a network to a buying and selling server that executes the transaction of the target item.

[0391] FIG. 33 is a diagram showing the configuration of the input management device 316. As shown in FIG.

[0392] The input manager 316 includes a forwarding circuit 332 , a handling circuit 334 , and an address decoder 336 .

[0393] The transfer circuit 332 includes a plurality of buffer memories 340 corresponding to each of a plurality of directed edges included in the directed graph. Each of the plurality of buffer memories 340 stores a weight value assigned to the corresponding directed edge.

[0394] In this example, the transfer circuit 332 includes N×N buffer memories 340. The N×N buffer memories 340 are divided into a UT part 342, an LT part 344, and a DI part 346.

[0395] The UT part 342 stores weight values belonging to the upper triangular components (UT) in the matrix. That is, the UT part 342 stores weight values corresponding to directed edges representing exchanges from the currency corresponding to the i-th node to the currency corresponding to the j-th node where i < j. The UT part 342 includes N×(N - 1) / 2 buffer memories 340.

[0396] The LT part 344 stores weight values belonging to the lower triangular components (LT) in the matrix. That is, the LT part 344 stores weight values corresponding to directed edges representing exchanges from the currency corresponding to the j-th node to the currency corresponding to the i-th node where i < j. The LT part 344 includes N×(N - 1) / 2 buffer memories 340.

[0397] The DI part 346 stores weight values belonging to the diagonal components in the matrix. The DI part 346 includes N buffer memories 340.

[0398] In this example, each of the N×N buffer memories 340 is a D-type flip-flop capable of storing multi-valued data. In this case, the buffer memory 340 includes an input terminal D, an enable terminal EN, and an output terminal Q.

[0399] Every time an event packet is received, the handling circuit 334 acquires a pair ID, a bid value (Bid), and an ask value (Ask).

[0400] Every time an event packet is received, the handling circuit 334 performs a negative logarithm operation (-log(Bid)) on the bid value (Bid), thereby obtaining a weight value (w) corresponding to a directed edge representing an exchange from the currency (i) corresponding to the i-th node to the currency (j) corresponding to the j-th node. i,jHandling circuitry 334 may include dedicated circuitry to perform a negative logarithm operation (-log(Bid)). Handling circuitry 334 calculates the calculated weight value (w i,j ) is applied in parallel to all input terminals D of N×(N−1) / 2 buffer memories 340 included in the UT unit 342.

[0401] Furthermore, the handling circuit 334 performs a positive logarithm operation (+log(Ask)) on the bid price (Ask) each time an event packet is received, to calculate a weight value (w j,i Handling circuit 334 may include dedicated circuitry to perform a positive logarithmic operation (+log(Bid)). Handling circuit 334 calculates the calculated weight value (w j,i ) is applied in parallel to all input terminals D of the N×(N−1) / 2 buffer memories 340 included in the LT unit 344.

[0402] The handling circuit 334 calculates a weight value (w i,j ) and the weight value (w j,i ) is output at the same time.

[0403] The handling circuit 334 identifies a currency pair (a pair of currency (i) and currency (j)) based on the pair ID each time an event packet is received. The handling circuit 334 provides an address representing the identified currency pair to the address decoder 336.

[0404] Based on the address representing the currency pair, the address decoder 336 selects a corresponding one of the N×(N-1) / 2 buffer memories 340 included in the UT unit 342. Also, based on the address representing the currency pair, the address decoder 336 selects a corresponding one of the N×(N-1) / 2 buffer memories 340 included in the LT unit 344.

[0405] The address decoder 336 applies a selection signal (Select out ) is given.

[0406] Each of the N×(N−1) / 2 buffer memories 340 included in the UT unit 342 receives a selection signal (Select out ) is given, the weight value given from the input terminal D is taken in. Therefore, the buffer memory 340 corresponding to the exchange from currency (i) to currency (j) included in the UT unit 342 takes in the weight value (w i,j ) can be captured and stored internally.

[0407] In addition, each of the N×(N−1) / 2 buffer memories 340 included in the LT section 344 also has a selection signal (Select out ) is given, the weight value given from the input terminal D is taken in. Therefore, the buffer memory 340 corresponding to the exchange from currency (j) to currency (i) included in the LT unit 344 takes in the weight value (w j,i ) can be captured and stored internally.

[0408] At system startup, a control signal (Cntrol) is provided to an enable terminal EN of each of the N buffer memories 340 included in the DI unit 346, and an initial value (Clinit) of the weight value is provided to an input terminal D. The initial value (Clinit) of the weight value is a value that does not affect the total value of the weight values, for example, 0.

[0409] Then, the transfer circuit 332 collectively writes the N×N weight values ​​stored in the N×N buffer memories 340 into the memory 21 included in the search device 10. For example, the transfer circuit 332 writes the N×N weight values ​​stored in the N×N buffer memories 340 into the memory 21 included in the search device 10 after a predetermined period of time (for example, NSTEP ×{2(N×N)+λ TE +λ GC +λ MX} clock cycle), the N×N weight values ​​stored in the memory 21 are rewritten all at once.

[0410] In the input management device 316, the handling circuit 334 before the transfer circuit 332 performs a logarithmic operation on the selling price (Bid) and the buying price (Ask) every time an event packet is received. The transfer circuit 332 rewrites two weight values ​​every time an event packet is received. The transfer circuit 332 outputs N×N weight values ​​to the search device 10 in a batch asynchronously with the reception of the event packet. If the input management device 316 performs a logarithmic operation at a stage subsequent to the transfer circuit 332, it must perform N×N logarithmic operations in parallel. In contrast, the input management device 316 of this embodiment performs a logarithmic operation in the handling circuit 334 before the transfer circuit 332. As a result, the input management device 316 of this embodiment can perform the logarithmic operation with a small circuit configuration.

[0411] Furthermore, the transfer circuit 332 transmits N×N weight values ​​to the search device 10 in, for example, one clock cycle, and updates the N×N weight values ​​stored in the memory 21 of the search device 10. Therefore, the transfer circuit 332 can update the N×N weight values ​​stored in the memory 21 of the search device 10 in a short period of time. This enables the search device 10 to quickly detect an optimal route in response to changes in exchange rates.

[0412] Furthermore, the transfer circuit 332 may store N×N exchange rates in addition to the N×N weight values. In this case, the handling circuit 334 also transmits the exchange rates (selling price (Bid) and the reciprocal of the buying price (1 / Ask)) included in the event packet to the transfer circuit 332, and stores them in the corresponding buffer memory 340. Then, the transfer circuit 332 transmits the N×N exchange rates in addition to the N×N weight values ​​to the memory 21 of the search device 10. This allows the search device 10 to easily perform a normalization operation on the N×N weight values ​​using the N×N exchange rates.

[0413] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0414] 10 Search device 12 Arithmetic section 14 Input section 16 Output section 18 Setting section 21 Memory 22 Control circuit 23 1st circuit 24 2nd circuit 25 Binarization circuit 26 Normalization circuit 31 TE Circuit 32 GC circuit 33 CC circuit 34 MX circuit 41 X memory circuit 42 Y memory circuit 43W memory circuit 44 Z memory circuit 45 XR memory circuit 46 XC memory circuit 47 XT memory circuit 48 Maximum value memory circuit 51 Position update circuit 52 Limiting Circuit 53 Momentum update circuit 54 Mask Circuit 57 FY circuit 58 First Adder 60 First Multiplexer 61 First Comparator 62 Second Multiplexer 63 3rd multiplexer 64 Second Comparator 65 FX circuit 66 FW circuit 67 Second Adder 68 4th multiplexer 69 5th multiplexer 71 Row-wise accumulating circuit 72 6th multiplexer 73 Third Comparator 74 Column-wise accumulating circuit 77 FM Circuit 78 Third Adder 79 First Multiplier 80 Second Multiplier 81 Third multiplier 82 First subtractor 83 Second subtractor 84 Third subtractor 85 First internal adder 86 Second internal adder 87 4th multiplier 90 Error minimization section 91 Maximum value adjustment section 101 7th multiplexer 102 4th Comparator 103 8th Multiplexer 104 First Accumulator 105 9th Multiplexer 106 5th Comparator 107 10th multiplexer 108 6th Comparator 109 Second Accumulator 110 11th multiplexer 111 7th Comparator 112 3rd accumulator 113 12th Multiplexer 114 Judgment circuit 115 Power Circuit 210 Sub TE Circuit 220 Sub-X memory circuit 222 Sub Y memory circuit 224 Sub-W memory circuit 226 Sub-Z Memory Circuit 230 Sub MX Circuit 242 Sub-XR memory circuit 244 Sub-XC memory circuit 246 Sub-XT memory circuit 262 Row-wise Accumulator 264 Total Adder 266 Demultiplexer 300 Arbitrage Trading System 312 Receiving Equipment 314 UDP processing section 316 Input Management Device 318 Trading Equipment 320 TCP processing section 322 Transmitting Equipment 332 Transfer Circuit 334 Handling Circuit 336 Address Decoder 340 Buffer Memory 342 UT section 344 LT section 346 DI Department

Claims

1. A computing device for solving a quadratic unconstrained binary optimization (QUBO) problem, which is formulated as a composite cost function using multiple binary variables, including a cost function and a penalty function based on constraints, comprising: storing a plurality of position variables corresponding to the plurality of binary variables, a plurality of momentum variables corresponding to the plurality of binary variables, and a plurality of coefficients included in the composite cost function; updating the plurality of position variables and the plurality of momentum variables from an initial time to an end time; After the end time is reached, determining whether the plurality of position variables satisfy the constraint condition; binarizing each of the plurality of position variables at the end time and outputting the binarized variables as a solution to the plurality of binary variables in the QUBO problem; In updating the plurality of position variables and the plurality of momentum variables, For each of the plurality of binary variables, updating a corresponding one of the plurality of position variables in response to a corresponding one of the plurality of momentum variables; For each of the plurality of binary variables, updating a corresponding one of the plurality of momentum variables in response to the plurality of position variables and a corresponding coefficient of the plurality of coefficients; Using the binarized plurality of position variables, it is determined whether or not the constraint condition is satisfied, and a determination result is output. computing device.

2. In updating the plurality of position variables and the plurality of momentum variables, processing is switched depending on whether the constraint condition is satisfied. The computing device of claim 1 .

3. In updating the plurality of position variables and the plurality of momentum variables, if the constraint condition is satisfied, a cost obtained by applying binarized values ​​of the plurality of position variables to the cost function is output, and if the constraint condition is not satisfied, the cost is not output.

3. The computing device of claim 2.

4. The method of claim 4 updates the plurality of position variables and the plurality of momentum variables for each unit time, determines whether the plurality of position variables satisfy the constraint condition for each unit time, and outputs the determination result.

4. A computing device according to any one of claims 1 to 3.

5. The QUBO problem is a problem of searching for an optimal path in a directed graph, the plurality of position variables correspond to a plurality of directed edges included in the directed graph; the plurality of momentum variables correspond to the plurality of directed edges; the coefficients correspond to weight values ​​assigned to the directed edges; The constraint condition is a condition that restricts a path in the directed graph.

5. A computing device according to any one of claims 1 to 4.

6. An arbitrage trading system for instructing arbitrage trading, comprising: A receiving device; An input management device; A computing device according to claim 5; A trading device; A transmitting device; Equipped with Each of the plurality of nodes included in the directed graph corresponds to a trading object; each of the plurality of directed edges corresponds to an exchange of a trade object corresponding to a start node to a trade object corresponding to an end node; Each of the plurality of weight values ​​represents a logarithmic value of an exchange rate when an exchange corresponding to the assigned directed edge is made; the calculation device detects, as the optimal route, a route for which an accumulated sum value of the weight values ​​assigned among the plurality of weight values ​​is maximum or minimum; The receiving device acquires an event packet including an exchange rate corresponding to any one of the plurality of directed edges from a market server; the input management device generates a weight value of a corresponding directed edge based on the acquired event packet, and rewrites the weight value in a memory included in the computing device; the trading device generates an order packet instructing to execute an exchange corresponding to two or more directed edges selected as the optimal path according to a total rate when an exchange corresponding to two or more directed edges included in the optimal path detected by the computing device is executed; The transmitting device transmits the order packet to a trading server, The computing device determines whether the optimal route forms a closed loop in determining whether the constraint condition is satisfied. Arbitrage trading system.

7. A computing system comprising: A computing device according to any one of claims 1 to 5; a receiving device for receiving a packet including information representing a portion of the plurality of coefficients; a transfer circuit including a buffer memory for storing the plurality of coefficients; Equipped with The transfer circuit includes: When the receiving device receives the packet, the part of the coefficients indicated by information included in the received packet among the plurality of coefficients stored in the buffer memory is rewritten in accordance with the information included in the received packet; At a predetermined timing, all of the plurality of coefficients stored in the buffer memory are written at once to a memory included in the computing device. Calculation system.

8. A calculation method for solving a quadratic unconstrained binary optimization (QUBO) problem, which is formulated as a composite cost function using a plurality of binary variables, including a cost function and a penalty function based on constraint conditions, by an information processing device, comprising: the information processing device stores a plurality of position variables corresponding to the plurality of binary variables, a plurality of momentum variables corresponding to the plurality of binary variables, and a plurality of coefficients included in the composite cost function; the information processing device updates the plurality of position variables and the plurality of momentum variables from an initial time to an end time; the information processing device determines whether or not the plurality of position variables satisfy the constraint condition after the end time is reached; the information processing device binarizes each of the plurality of position variables at the end time and outputs the binarized variables as a solution to the plurality of binary variables in the QUBO problem; In updating the plurality of position variables and the plurality of momentum variables, for each of the plurality of binary variables, the information processing device updating a corresponding position variable of the plurality of position variables in response to a corresponding momentum variable of the plurality of momentum variables; updating a corresponding momentum variable of the plurality of momentum variables in response to the plurality of position variables and a corresponding coefficient of the plurality of coefficients; Furthermore, the information processing device uses the binarized position variables to determine whether or not the constraint condition is satisfied, and outputs a determination result. Calculation method.

9. A program for causing an information processing device to function as a computing device for solving a quadratic unconstrained binary optimization (QUBO) problem, the QUBO problem being formulated as a composite cost function using multiple binary variables, the composite cost function including a cost function and a penalty function based on constraint conditions, comprising: the information processing device stores a plurality of position variables corresponding to the plurality of binary variables, a plurality of momentum variables corresponding to the plurality of binary variables, and a plurality of coefficients included in the composite cost function; causing the information processing device to update the plurality of position variables and the plurality of momentum variables from an initial time to an end time; causing the information processing device to determine whether or not the plurality of position variables satisfy the constraint condition after the end time is reached; causing the information processing device to binarize each of the plurality of position variables at the end time and output the binarized variables as a solution to the plurality of binary variables in the QUBO problem; In updating the plurality of position variables and the plurality of momentum variables, for each of the plurality of binary variables, updating a corresponding position variable among the plurality of position variables in response to a corresponding momentum variable among the plurality of momentum variables; updating a corresponding momentum variable of the plurality of momentum variables in response to the plurality of position variables and a corresponding coefficient of the plurality of coefficients; Furthermore, the information processing device is caused to determine whether or not the constraint condition is satisfied using the binarized plurality of position variables, and to output a result of the determination. program.

10. Circuit information describing a circuit configuration, the circuit information being written in a hardware description language, The circuit is caused to function as a computing device that solves a quadratic unconstrained binary optimization (QUBO) problem that is formulated as a composite cost function using a plurality of binary variables, the composite cost function including a cost function and a penalty function based on a constraint condition; The computing device comprises: storing a plurality of position variables corresponding to the plurality of binary variables, a plurality of momentum variables corresponding to the plurality of binary variables, and a plurality of coefficients included in the composite cost function; updating the plurality of position variables and the plurality of momentum variables from an initial time to an end time; After the end time is reached, determining whether the plurality of position variables satisfy the constraint condition; binarizing each of the plurality of position variables at the end time and outputting the binarized variables as a solution to the plurality of binary variables in the QUBO problem; In updating the plurality of position variables and the plurality of momentum variables, For each of the plurality of binary variables, updating a corresponding one of the plurality of position variables in response to a corresponding one of the plurality of momentum variables; For each of the plurality of binary variables, updating a corresponding one of the plurality of momentum variables in response to the plurality of position variables and a corresponding one of the plurality of coefficients; Using the binarized plurality of position variables, it is determined whether or not the constraint condition is satisfied, and a determination result is output. Circuit information.

11. Circuit information to be written into a reconfigurable semiconductor device in order to operate the reconfigurable semiconductor device, comprising: The reconfigurable semiconductor device is caused to function as a computing device that solves a quadratic unconstrained binary optimization (QUBO) problem, the quadratic unconstrained binary optimization problem being formulated as a composite cost function using a plurality of binary variables, the composite cost function including a cost function and a penalty function based on a constraint condition; The computing device comprises: storing a plurality of position variables corresponding to the plurality of binary variables, a plurality of momentum variables corresponding to the plurality of binary variables, and a plurality of coefficients included in the composite cost function; updating the plurality of position variables and the plurality of momentum variables from an initial time to an end time; After the end time is reached, determining whether the plurality of position variables satisfy the constraint condition; binarizing each of the plurality of position variables at the end time and outputting the binarized variables as a solution to the plurality of binary variables in the QUBO problem; In updating the plurality of position variables and the plurality of momentum variables, For each of the plurality of binary variables, updating a corresponding one of the plurality of position variables in response to a corresponding one of the plurality of momentum variables; For each of the plurality of binary variables, updating a corresponding one of the plurality of momentum variables in response to the plurality of position variables and a corresponding coefficient of the plurality of coefficients; Using the binarized plurality of position variables, it is determined whether or not the constraint condition is satisfied, and a determination result is output. Circuit information.

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