Transmitting device and transmitting method

Abstract

To secure an excellent communication quality in a data transmission using an LDPC code.SOLUTION: In group-wise interleaving, an LDPC code having a code length N of 17280 bits is interleaved in units of 0 to 47 bit groups of 360 bits. In group-wise deinterleaving, the group-wise interleaved LDPC code is restored to an original ordering thereof. The present technique can be applied to, for example, a case of data transmission using an LDPC code.SELECTED DRAWING: Figure 85

Description

[Technical field]

[0001] The present technology relates to a transmission device and a transmission method, and in particular to a transmission device and a transmission method that enable good communication quality to be ensured in data transmission using, for example, an LDPC code. [Background technology]

[0002] Low Density Parity Check (LDPC) codes have high error correction capabilities, and in recent years have been widely adopted in transmission methods for digital broadcasting, such as DVB (Digital Video Broadcasting)-S.2, DVB-T.2, and DVB-C.2 in Europe, and ATSC (Advanced Television Systems Committee) 3.0 in the United States (see, for example, Non-Patent Document 1).

[0003] Recent research has shown that LDPC codes, like turbo codes, can achieve performance approaching the Shannon limit as the code length is increased. In addition, LDPC codes have the property that the minimum distance is proportional to the code length, and therefore have good block error probability characteristics. Another advantage is that the so-called error floor phenomenon observed in the decoding characteristics of turbo codes and the like hardly occurs. [Prior art documents] [Non-patent literature]

[0004] [Non-Patent Document 1] ATSC Standard:Physical Layer Protocol(A / 322), 7 September 2016 Summary of the Invention [Problem to be solved by the invention]

[0005] In data transmission using an LDPC code, for example, the LDPC code is made into a symbol (symbolized) for orthogonal modulation (digital modulation) such as QPSK (Quadrature Phase Shift Keying), and the symbol is mapped to a signal point of the orthogonal modulation and transmitted.

[0006] Data transmission using LDPC codes as described above is becoming more widespread worldwide, and there is a demand to ensure good communication (transmission) quality.

[0007] The present technology has been made in view of these circumstances, and makes it possible to ensure good communication quality in data transmission using LDPC codes. [Means for solving the problem]

[0008] A first transmission method / apparatus of the present technology includes an encoding step / unit that performs LDPC encoding based on a check matrix of an LDPC code having a code length N of 17280 bits and a coding rate r of 3 / 16, a group-wise interleaving step / unit that performs group-wise interleaving of the LDPC code in units of 360-bit bit groups, and a mapping step / unit that maps the LDPC code to one of four signal points of QPSK (Quadrature Phase Shift Keying) in units of 2 bits, and in the group-wise interleaving, the (i+1)th bit group from the beginning of the LDPC code is defined as bit group i, and a sequence of bit groups 0 to 47 of the 17280-bit LDPC code is mapped to bit group i. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 and interleaving in the order of the above, the parity check matrix includes an A matrix at the top left of the parity check matrix, which has M1 rows and K columns, represented by a predetermined value M1 and an information length K=N×r of the LDPC code, a B matrix of a staircase structure adjacent to the right of the A matrix, which has M1 rows and M1 columns, a Z matrix which is a zero matrix adjacent to the right of the B matrix, which has M1 rows and N-K-M1 columns, a C matrix adjacent below the A matrix and the B matrix, which has N-K-M1 rows and K+M1 columns, and a D matrix which is an identity matrix adjacent to the right of the C matrix, which has N-K-M1 rows and N-K-M1 columns, the predetermined value M1 is 1440, the A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table that represents the positions of elements of 1 in the A matrix and the C matrix for every 360 columns, 10 1155 1332 1608 8228 8253 11662 483 1297 1433 4678 5776 10410 13553 862 967 1036 1842 2950 10129 12042 258 872 1037 7129 9442 9491 10644 215 260 590 6003 7554 10499 197 521 1190 1670 3696 4410 4436 4686 5350 5651 7397 7503 8553 9844 10729 11421 11605 11742 11835 12338 12422 288 560 1427 1492 1932 3255 4508 4628 5259 5881 6136 8019 8152 8192 8230 8669 8880 10289 11160 11665 12374 694 1175 1205 2363 2756 2962 3097 3374 4268 4811 6072 6393 6942 9514 9733 10681 11081 11360 12386 13467 13980 25 1200 1266 3036 3441 4940 5161 5254 7231 7585 8088 9414 10217 10349 10409 11177 12151 12497 12934 13123 14029 2599 5475 6890 7755 8567 9088 11980 2708 2836 6062 6328 8890 9831 11173 2522 2634 4989 6831 9523 10731 12107 4738 5653 7862 11986 12773 12839 13045 is A transmission method / apparatus.

[0009] In the first transmission method / apparatus of the present technology, LDPC coding is performed based on a check matrix of an LDPC code with a code length N of 17280 bits and a coding rate r of 3 / 16, and group-wise interleaving is performed to interleave the LDPC code in units of 360-bit bit groups. Then, the LDPC code is mapped to one of four signal points of QPSK (Quadrature Phase Shift Keying) in units of 2 bits. In the group-wise interleaving, the (i+1)th bit group from the beginning of the LDPC code is defined as bit group i, and the arrangement of bit groups 0 to 47 of the 17280-bit LDPC code is defined as bit group i. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 The parity check matrix includes an A matrix at the top left of the parity check matrix, which has M1 rows and K columns and is represented by a predetermined value M1 and an information length K=N×r of the LDPC code, a B matrix of a staircase structure adjacent to the right of the A matrix, which has M1 rows and M1 columns, a Z matrix which is a zero matrix adjacent to the right of the B matrix, which has M1 rows and N-K-M1 columns, a C matrix adjacent below the A matrix and the B matrix, which has N-K-M1 rows and K+M1 columns, and a D matrix which is an identity matrix adjacent to the right of the C matrix, which has N-K-M1 rows and N-K-M1 columns, the predetermined value M1 is 1440, the A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table which represents the positions of elements of 1 in the A matrix and the C matrix for every 360 columns, 10 1155 1332 1608 8228 8253 11662 483 1297 1433 4678 5776 10410 13553 862 967 1036 1842 2950 10129 12042 258 872 1037 7129 9442 9491 10644 215 260 590 6003 7554 10499 197 521 1190 1670 3696 4410 4436 4686 5350 5651 7397 7503 8553 9844 10729 11421 11605 11742 11835 12338 12422 288 560 1427 1492 1932 3255 4508 4628 5259 5881 6136 8019 8152 8192 8230 8669 8880 10289 11160 11665 12374 694 1175 1205 2363 2756 2962 3097 3374 4268 4811 6072 6393 6942 9514 9733 10681 11081 11360 12386 13467 13980 25 1200 1266 3036 3441 4940 5161 5254 7231 7585 8088 9414 10217 10349 10409 11177 12151 12497 12934 13123 14029 2599 5475 6890 7755 8567 9088 11980 2708 2836 6062 6328 8890 9831 11173 2522 2634 4989 6831 9523 10731 12107 4738 5653 7862 11986 12773 12839 13045 It has become.

[0010] A first receiving device / method of the present technology includes a coding step of performing LDPC coding based on a check matrix of an LDPC code having a code length N of 17280 bits and a coding rate r of 3 / 16, a group-wise interleaving step of performing group-wise interleaving of the LDPC code in units of 360-bit bit groups, and a mapping step of mapping the LDPC code to one of four signal points of QPSK (Quadrature Phase Shift Keying) in units of 2 bits, wherein in the group-wise interleaving, the (i+1)th bit group from the beginning of the LDPC code is defined as bit group i, and a sequence of bit groups 0 to 47 of the 17280-bit LDPC code is defined as bit group i. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 and interleaving in the order of the above, the parity check matrix includes an A matrix at the top left of the parity check matrix, which has M1 rows and K columns, represented by a predetermined value M1 and an information length K=N×r of the LDPC code, a B matrix of a staircase structure adjacent to the right of the A matrix, which has M1 rows and M1 columns, a Z matrix which is a zero matrix adjacent to the right of the B matrix, which has M1 rows and N-K-M1 columns, a C matrix adjacent below the A matrix and the B matrix, which has N-K-M1 rows and K+M1 columns, and a D matrix which is an identity matrix adjacent to the right of the C matrix, which has N-K-M1 rows and N-K-M1 columns, the predetermined value M1 is 1440, the A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table that represents the positions of elements of 1 in the A matrix and the C matrix for every 360 columns, 10 1155 1332 1608 8228 8253 11662 483 1297 1433 4678 5776 10410 13553 862 967 1036 1842 2950 10129 12042 258 872 1037 7129 9442 9491 10644 215 260 590 6003 7554 10499 197 521 1190 1670 3696 4410 4436 4686 5350 5651 7397 7503 8553 9844 10729 11421 11605 11742 11835 12338 12422 288 560 1427 1492 1932 3255 4508 4628 5259 5881 6136 8019 8152 8192 8230 8669 8880 10289 11160 11665 12374 694 1175 1205 2363 2756 2962 3097 3374 4268 4811 6072 6393 6942 9514 9733 10681 11081 11360 12386 13467 13980 25 1200 1266 3036 3441 4940 5161 5254 7231 7585 8088 9414 10217 10349 10409 11177 12151 12497 12934 13123 14029 2599 5475 6890 7755 8567 9088 11980 2708 2836 6062 6328 8890 9831 11173 2522 2634 4989 6831 9523 10731 12107 4738 5653 7862 11986 12773 12839 13045 The receiving device / method includes a decoding unit / step for decoding the LDPC code obtained from data transmitted by the transmission method.

[0011] In the first receiving device / method of the present technology, the LDPC code obtained from data transmitted by a first transmitting method is decoded.

[0012] A second transmission method / apparatus of the present technology includes an encoding step / unit that performs LDPC encoding based on a check matrix of an LDPC code having a code length N of 17280 bits and a coding rate r of 5 / 16, a group-wise interleaving step / unit that performs group-wise interleaving of the LDPC code in units of bit groups of 360 bits, and a mapping step / unit that maps the LDPC code to one of four signal points of QPSK (Quadrature Phase Shift Keying) in units of 2 bits, and in the group-wise interleaving, the (i+1)th bit group from the beginning of the LDPC code is defined as bit group i, and a sequence of bit groups 0 to 47 of the 17280-bit LDPC code is defined as bit group i. 19 33 45 22 43 23 46 32 11 40 13 34 14 47 0 12 6 26 37 4 5 17 25 30 39 29 27 28 10 21 36 9 3 20 24 42 7 41 44 38 15 8 31 16 2 1 35 18 and interleaving in the order of the above, the parity check matrix includes an A matrix at the top left of the parity check matrix, which has M1 rows and K columns, represented by a predetermined value M1 and an information length K=N×r of the LDPC code, a B matrix of a staircase structure adjacent to the right of the A matrix, which has M1 rows and M1 columns, a Z matrix which is a zero matrix adjacent to the right of the B matrix, which has M1 rows and N-K-M1 columns, a C matrix adjacent below the A matrix and the B matrix, which has N-K-M1 rows and K+M1 columns, and a D matrix which is an identity matrix adjacent to the right of the C matrix, which has N-K-M1 rows and N-K-M1 columns, the predetermined value M1 is 720, the A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table that represents the positions of elements of 1 in the A matrix and the C matrix for every 360 columns, 301 342 350 1797 7970 8230 10820 11305 139 530 615 1566 6290 6425 9185 9466 48 419 444 1773 3213 4793 8594 10480 246 455 531 3011 5845 7383 8393 10709 39 262 290 3282 5208 9539 10955 11204 234 267 623 1033 1537 8766 11527 11557 494 661 671 1123 4497 ​​6601 6715 10473 164 425 436 3259 4505 5614 8192 10221 326 377 477 7699 10162 11174 11878 206 360 557 891 930 1847 2427 3888 4491 6494 6911 8084 8945 9549 402 588 657 888 3271 4858 5257 6398 6631 6972 9678 11140 11159 11398 39 111 168 1192 1879 3121 3127 5987 8385 8488 9302 9884 10891 11879 639 640 693 1477 1790 2442 3388 3547 4622 6890 7315 7478 7905 11518 337 544 604 1184 1238 1334 2434 5239 6832 7770 9123 9397 9646 10254 32 77 604 762 1428 2756 2758 6854 7193 7311 7517 9105 10765 11173 910 1918 2342 3280 3362 3913 4586 6316 7693 8878 10922 11145 11863 790 1177 1386 1961 2437 3571 5179 5961 8222 9195 9569 10414 11498 The present invention relates to a transmission method / apparatus.

[0013] In the second transmission method / apparatus of the present technology, LDPC coding is performed based on a check matrix of an LDPC code with a code length N of 17280 bits and a coding rate r of 5 / 16, and group-wise interleaving is performed to interleave the LDPC code in units of 360-bit bit groups. Then, the LDPC code is mapped to one of four signal points of QPSK (Quadrature Phase Shift Keying) in units of 2 bits. In the group-wise interleaving, the (i+1)th bit group from the beginning of the LDPC code is defined as bit group i, and the arrangement of bit groups 0 to 47 of the 17280-bit LDPC code is defined as bit group i. 19 33 45 22 43 23 46 32 11 40 13 34 14 47 0 12 6 26 37 4 5 17 25 30 39 29 27 28 10 21 36 9 3 20 24 42 7 41 44 38 15 8 31 16 2 1 35 18 The parity check matrix includes an A matrix at the top left of the parity check matrix, which has M1 rows and K columns and is represented by a predetermined value M1 and an information length K=N×r of the LDPC code, a B matrix of a staircase structure adjacent to the right of the A matrix, which has M1 rows and M1 columns, a Z matrix which is a zero matrix adjacent to the right of the B matrix, which has M1 rows and N-K-M1 columns, a C matrix adjacent below the A matrix and the B matrix, which has N-K-M1 rows and K+M1 columns, and a D matrix which is an identity matrix adjacent to the right of the C matrix, which has N-K-M1 rows and N-K-M1 columns, the predetermined value M1 is 720, the A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table which represents the positions of elements of 1 in the A matrix and the C matrix for every 360 columns, 301 342 350 1797 7970 8230 10820 11305 139 530 615 1566 6290 6425 9185 9466 48 419 444 1773 3213 4793 8594 10480 246 455 531 3011 5845 7383 8393 10709 39 262 290 3282 5208 9539 10955 11204 234 267 623 1033 1537 8766 11527 11557 494 661 671 1123 4497 ​​6601 6715 10473 164 425 436 3259 4505 5614 8192 10221 326 377 477 7699 10162 11174 11878 206 360 557 891 930 1847 2427 3888 4491 6494 6911 8084 8945 9549 402 588 657 888 3271 4858 5257 6398 6631 6972 9678 11140 11159 11398 39 111 168 1192 1879 3121 3127 5987 8385 8488 9302 9884 10891 11879 639 640 693 1477 1790 2442 3388 3547 4622 6890 7315 7478 7905 11518 337 544 604 1184 1238 1334 2434 5239 6832 7770 9123 9397 9646 10254 32 77 604 762 1428 2756 2758 6854 7193 7311 7517 9105 10765 11173 910 1918 2342 3280 3362 3913 4586 6316 7693 8878 10922 11145 11863 790 1177 1386 1961 2437 3571 5179 5961 8222 9195 9569 10414 11498 It has become.

[0014] A second receiving apparatus / method of the present technology includes a coding step of performing LDPC coding based on a parity check matrix of an LDPC code having a code length N of 17280 bits and a coding rate r of 5 / 16, a group-wise interleaving step of performing group-wise interleaving of the LDPC code in units of 360-bit bit groups, and a mapping step of mapping the LDPC code to one of four signal points of QPSK (Quadrature Phase Shift Keying) in units of 2 bits, wherein in the group-wise interleaving, the (i+1)th bit group from the beginning of the LDPC code is defined as bit group i, and a sequence of bit groups 0 to 47 of the 17280-bit LDPC code is defined as bit group i. 19 33 45 22 43 23 46 32 11 40 13 34 14 47 0 12 6 26 37 4 5 17 25 30 39 29 27 28 10 21 36 9 3 20 24 42 7 41 44 38 15 8 31 16 2 1 35 18 and interleaving in the order of the above, the parity check matrix includes an A matrix at the top left of the parity check matrix, which has M1 rows and K columns, represented by a predetermined value M1 and an information length K=N×r of the LDPC code, a B matrix of a staircase structure adjacent to the right of the A matrix, which has M1 rows and M1 columns, a Z matrix which is a zero matrix adjacent to the right of the B matrix, which has M1 rows and N-K-M1 columns, a C matrix adjacent below the A matrix and the B matrix, which has N-K-M1 rows and K+M1 columns, and a D matrix which is an identity matrix adjacent to the right of the C matrix, which has N-K-M1 rows and N-K-M1 columns, the predetermined value M1 is 720, the A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table that represents the positions of elements of 1 in the A matrix and the C matrix for every 360 columns, 301 342 350 1797 7970 8230 10820 11305 139 530 615 1566 6290 6425 9185 9466 48 419 444 1773 3213 4793 8594 10480 246 455 531 3011 5845 7383 8393 10709 39 262 290 3282 5208 9539 10955 11204 234 267 623 1033 1537 8766 11527 11557 494 661 671 1123 4497 ​​6601 6715 10473 164 425 436 3259 4505 5614 8192 10221 326 377 477 7699 10162 11174 11878 206 360 557 891 930 1847 2427 3888 4491 6494 6911 8084 8945 9549 402 588 657 888 3271 4858 5257 6398 6631 6972 9678 11140 11159 11398 39 111 168 1192 1879 3121 3127 5987 8385 8488 9302 9884 10891 11879 639 640 693 1477 1790 2442 3388 3547 4622 6890 7315 7478 7905 11518 337 544 604 1184 1238 1334 2434 5239 6832 7770 9123 9397 9646 10254 32 77 604 762 1428 2756 2758 6854 7193 7311 7517 9105 10765 11173 910 1918 2342 3280 3362 3913 4586 6316 7693 8878 10922 11145 11863 790 1177 1386 1961 2437 3571 5179 5961 8222 9195 9569 10414 11498 The receiving device / method includes a decoding unit / step for decoding the LDPC code obtained from data transmitted by the transmission method.

[0015] In the second receiving device / method of the present technology, the LDPC code obtained from data transmitted by the second transmission method is decoded.

[0016] A third transmission method / apparatus of the present technology includes an encoding step / unit that performs LDPC encoding based on a check matrix of an LDPC code having a code length N of 17280 bits and a coding rate r of 7 / 16, a group-wise interleaving step / unit that performs group-wise interleaving of the LDPC code in units of bit groups of 360 bits, and a mapping step / unit that maps the LDPC code to one of four signal points of QPSK (Quadrature Phase Shift Keying) in units of 2 bits, and in the group-wise interleaving, the (i+1)th bit group from the beginning of the LDPC code is defined as bit group i, and a sequence of bit groups 0 to 47 of the 17280-bit LDPC code is defined as bit group i. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 the LDPC code includes information bits and parity bits, the check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the information matrix portion is represented by a check matrix initial value table, the check matrix initial value table is a table representing the position of one element of the information matrix portion for every 360 columns, 193 217 530 596 789 1340 1569 1662 1887 1889 2299 2610 2629 2790 3464 3607 3935 4439 5460 5721 5758 6094 6280 6350 6449 6613 6682 6826 6906 7048 7425 8229 8627 8679 8735 8814 9079 9146 435 572 815 903 1063 1962 1989 2215 2417 2862 2914 3182 3980 4414 4566 4895 4950 5163 5336 5388 5642 5764 6586 6719 6787 7262 7609 8000 8561 8790 9027 9334 9358 9420 9444 9553 9614 250 3557 3865 4350 4394 4644 5303 6590 8377 8497 9655 21 602 1038 1212 1243 3938 4136 5620 6516 6777 8226 134 214 1550 1554 1615 3178 5113 5163 5201 7168 7574 134 2692 3810 4954 6766 2394 4734 5731 7427 7653 509 1009 3867 5069 9121 540 2975 6248 4 831 3592 503 1385 7170 348 7774 8897 67 3553 5134 623 6525 8314 2871 7545 8960 4330 4839 7689 4793 5327 8046 2877 3422 8836 2069 7584 9102 1376 3862 4352 4693 7147 9461 The present invention relates to a transmission method / apparatus.

[0017] In the third transmission method / apparatus of the present technology, LDPC coding is performed based on a check matrix of an LDPC code with a code length N of 17280 bits and a coding rate r of 7 / 16, and group-wise interleaving is performed to interleave the LDPC code in units of 360-bit bit groups. Then, the LDPC code is mapped to one of four signal points of QPSK (Quadrature Phase Shift Keying) in units of 2 bits. In the group-wise interleaving, the (i+1)th bit group from the beginning of the LDPC code is defined as bit group i, and the arrangement of bit groups 0 to 47 of the 17280-bit LDPC code is defined as bit group i. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 The LDPC code includes information bits and parity bits, the check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the information matrix portion is represented by a check matrix initial value table, and the check matrix initial value table is a table representing the position of an element of the information matrix portion for every 360 columns, 193 217 530 596 789 1340 1569 1662 1887 1889 2299 2610 2629 2790 3464 3607 3935 4439 5460 5721 5758 6094 6280 6350 6449 6613 6682 6826 6906 7048 7425 8229 8627 8679 8735 8814 9079 9146 435 572 815 903 1063 1962 1989 2215 2417 2862 2914 3182 3980 4414 4566 4895 4950 5163 5336 5388 5642 5764 6586 6719 6787 7262 7609 8000 8561 8790 9027 9334 9358 9420 9444 9553 9614 250 3557 3865 4350 4394 4644 5303 6590 8377 8497 9655 21 602 1038 1212 1243 3938 4136 5620 6516 6777 8226 134 214 1550 1554 1615 3178 5113 5163 5201 7168 7574 134 2692 3810 4954 6766 2394 4734 5731 7427 7653 509 1009 3867 5069 9121 540 2975 6248 4 831 3592 503 1385 7170 348 7774 8897 67 3553 5134 623 6525 8314 2871 7545 8960 4330 4839 7689 4793 5327 8046 2877 3422 8836 2069 7584 9102 1376 3862 4352 4693 7147 9461 It has become.

[0018] A third receiving apparatus / method of the present technology includes a coding step of performing LDPC coding based on a check matrix of an LDPC code having a code length N of 17280 bits and a coding rate r of 7 / 16, a group-wise interleaving step of performing group-wise interleaving of the LDPC code in units of 360-bit bit groups, and a mapping step of mapping the LDPC code to one of four signal points of QPSK (Quadrature Phase Shift Keying) in units of 2 bits, wherein in the group-wise interleaving, the (i+1)th bit group from the beginning of the LDPC code is defined as bit group i, and a sequence of bit groups 0 to 47 of the 17280-bit LDPC code is defined as bit group i. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 the LDPC code includes information bits and parity bits, the check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the information matrix portion is represented by a check matrix initial value table, the check matrix initial value table is a table representing the position of one element of the information matrix portion for every 360 columns, 193 217 530 596 789 1340 1569 1662 1887 1889 2299 2610 2629 2790 3464 3607 3935 4439 5460 5721 5758 6094 6280 6350 6449 6613 6682 6826 6906 7048 7425 8229 8627 8679 8735 8814 9079 9146 435 572 815 903 1063 1962 1989 2215 2417 2862 2914 3182 3980 4414 4566 4895 4950 5163 5336 5388 5642 5764 6586 6719 6787 7262 7609 8000 8561 8790 9027 9334 9358 9420 9444 9553 9614 250 3557 3865 4350 4394 4644 5303 6590 8377 8497 9655 21 602 1038 1212 1243 3938 4136 5620 6516 6777 8226 134 214 1550 1554 1615 3178 5113 5163 5201 7168 7574 134 2692 3810 4954 6766 2394 4734 5731 7427 7653 509 1009 3867 5069 9121 540 2975 6248 4 831 3592 503 1385 7170 348 7774 8897 67 3553 5134 623 6525 8314 2871 7545 8960 4330 4839 7689 4793 5327 8046 2877 3422 8836 2069 7584 9102 1376 3862 4352 4693 7147 9461 The receiving device / method includes a decoding unit / step for decoding the LDPC code obtained from data transmitted by the transmission method.

[0019] In the third receiving device / method of the present technology, the LDPC code obtained from data transmitted by the third transmission method is decoded.

[0020] A fourth transmission method / apparatus of the present technology includes an encoding step / unit that performs LDPC encoding based on a check matrix of an LDPC code having a code length N of 17280 bits and a coding rate r of 9 / 16, a group-wise interleaving step / unit that performs group-wise interleaving of the LDPC code in units of 360-bit bit groups, and a mapping step / unit that maps the LDPC code to one of four signal points of QPSK (Quadrature Phase Shift Keying) in units of 2 bits, and in the group-wise interleaving, the (i+1)th bit group from the beginning of the LDPC code is defined as bit group i, and a sequence of bit groups 0 to 47 of the 17280-bit LDPC code is mapped to bit group i. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 the LDPC code includes information bits and parity bits, the check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the information matrix portion is represented by a check matrix initial value table, the check matrix initial value table is a table representing the position of one element of the information matrix portion for every 360 columns, 42 549 1187 1203 1694 1741 2290 2776 2839 2886 3435 3503 3697 4031 4580 4627 5176 5223 5539 5772 6368 6917 6964 7513 13 192 415 563 699 934 1176 1484 1855 2426 3147 3369 3389 4068 4380 4578 4618 4937 4989 5381 5910 6281 6831 7202 1319 1687 2423 3518 3737 4273 5242 6209 6535 6966 7397 1273 2244 2896 3018 3949 4065 4414 4763 5461 5673 7555 344 735 1706 2320 2669 3367 3800 5112 6201 6857 7248 33 1088 1439 2013 2881 3774 3936 5447 5810 6697 7368 615 1580 2410 2698 3801 4182 4991 5483 6046 6292 6538 4564 4745 6784 550 3081 7463 950 2455 2786 1218 2118 6232 3475 4980 6548 4769 5585 6837 450 1681 3707 4038 4889 7174 1432 5762 6265 60 2951 6848 2766 3597 4872 140 2141 4243 874 4142 7054 807 2368 5619 3391 6408 6657 2073 2609 6079 1558 4944 5690 276 875 4345 3273 3767 7300 2695 6102 6743 The present invention relates to a transmission method / apparatus.

[0021] In a fourth transmission method / apparatus of the present technology, LDPC coding is performed based on a check matrix of an LDPC code with a code length N of 17280 bits and a coding rate r of 9 / 16, and group-wise interleaving is performed to interleave the LDPC code in units of 360-bit bit groups. Then, the LDPC code is mapped to one of four signal points of QPSK (Quadrature Phase Shift Keying) in units of 2 bits. In the group-wise interleaving, the (i+1)th bit group from the beginning of the LDPC code is defined as bit group i, and the arrangement of bit groups 0 to 47 of the 17280-bit LDPC code is defined as bit group i. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 The LDPC code includes information bits and parity bits, the check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the information matrix portion is represented by a check matrix initial value table, and the check matrix initial value table is a table representing the position of an element of the information matrix portion for every 360 columns, 42 549 1187 1203 1694 1741 2290 2776 2839 2886 3435 3503 3697 4031 4580 4627 5176 5223 5539 5772 6368 6917 6964 7513 13 192 415 563 699 934 1176 1484 1855 2426 3147 3369 3389 4068 4380 4578 4618 4937 4989 5381 5910 6281 6831 7202 1319 1687 2423 3518 3737 4273 5242 6209 6535 6966 7397 1273 2244 2896 3018 3949 4065 4414 4763 5461 5673 7555 344 735 1706 2320 2669 3367 3800 5112 6201 6857 7248 33 1088 1439 2013 2881 3774 3936 5447 5810 6697 7368 615 1580 2410 2698 3801 4182 4991 5483 6046 6292 6538 4564 4745 6784 550 3081 7463 950 2455 2786 1218 2118 6232 3475 4980 6548 4769 5585 6837 450 1681 3707 4038 4889 7174 1432 5762 6265 60 2951 6848 2766 3597 4872 140 2141 4243 874 4142 7054 807 2368 5619 3391 6408 6657 2073 2609 6079 1558 4944 5690 276 875 4345 3273 3767 7300 2695 6102 6743 It has become.

[0022] A fourth receiving apparatus / method of the present technology includes a coding step of performing LDPC coding based on a parity check matrix of an LDPC code having a code length N of 17280 bits and a coding rate r of 9 / 16, a group-wise interleaving step of performing group-wise interleaving of the LDPC code in units of 360-bit bit groups, and a mapping step of mapping the LDPC code to one of four signal points of QPSK (Quadrature Phase Shift Keying) in units of 2 bits, wherein in the group-wise interleaving, the (i+1)th bit group from the beginning of the LDPC code is defined as bit group i, and a sequence of bit groups 0 to 47 of the 17280-bit LDPC code is mapped to bit group i. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 the LDPC code includes information bits and parity bits, the check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the information matrix portion is represented by a check matrix initial value table, the check matrix initial value table is a table representing the position of one element of the information matrix portion for every 360 columns, 42 549 1187 1203 1694 1741 2290 2776 2839 2886 3435 3503 3697 4031 4580 4627 5176 5223 5539 5772 6368 6917 6964 7513 13 192 415 563 699 934 1176 1484 1855 2426 3147 3369 3389 4068 4380 4578 4618 4937 4989 5381 5910 6281 6831 7202 1319 1687 2423 3518 3737 4273 5242 6209 6535 6966 7397 1273 2244 2896 3018 3949 4065 4414 4763 5461 5673 7555 344 735 1706 2320 2669 3367 3800 5112 6201 6857 7248 33 1088 1439 2013 2881 3774 3936 5447 5810 6697 7368 615 1580 2410 2698 3801 4182 4991 5483 6046 6292 6538 4564 4745 6784 550 3081 7463 950 2455 2786 1218 2118 6232 3475 4980 6548 4769 5585 6837 450 1681 3707 4038 4889 7174 1432 5762 6265 60 2951 6848 2766 3597 4872 140 2141 4243 874 4142 7054 807 2368 5619 3391 6408 6657 2073 2609 6079 1558 4944 5690 276 875 4345 3273 3767 7300 2695 6102 6743 The receiving device / method includes a decoding unit / step for decoding the LDPC code obtained from data transmitted by the transmission method.

[0023] In the fourth receiving device / method of the present technology, the LDPC code obtained from data transmitted by a fourth transmission method is decoded.

[0024] A fifth transmission method / apparatus of the present technology includes an encoding step / unit that performs LDPC encoding based on a check matrix of an LDPC code having a code length N of 17280 bits and a coding rate r of 11 / 16, a group-wise interleaving step / unit that performs group-wise interleaving of the LDPC code in units of 360-bit bit groups, and a mapping step / unit that maps the LDPC code to one of four signal points of QPSK (Quadrature Phase Shift Keying) in units of 2 bits, and in the group-wise interleaving, a bit group (i+1) from the beginning of the LDPC code is defined as bit group i, and a sequence of bit groups 0 to 47 of the 17280-bit LDPC code is defined as bit group i. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 the LDPC code includes information bits and parity bits, the check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the information matrix portion is represented by a check matrix initial value table, the check matrix initial value table is a table representing the position of one element of the information matrix portion for every 360 columns, 91 382 494 654 681 695 1643 2171 2576 3027 3115 3390 3633 3644 3812 3883 4474 4607 4674 384 396 982 988 1053 1867 2215 2345 2472 3323 3503 3573 3883 4159 4576 4917 5104 5130 456 580 1590 1715 1786 1843 1934 2251 2261 2466 2525 2958 3467 4334 4530 4779 4885 5021 227 381 394 502 1059 1108 1480 1508 1523 1620 1840 1996 2436 2989 3716 3957 4072 4243 4482 4517 4717 4910 5105 5220 5238 5279 376 957 1706 2028 2228 2439 2552 4249 5234 89 676 1098 1103 1127 1449 1605 2362 4640 66 613 1692 1901 2247 3025 3244 4864 5050 1628 2015 2596 521 802 3804 3178 4080 5057 344 3486 3948 595 2538 2964 300 1355 3476 1292 2761 4819 462 773 3996 133 3494 4342 37 3698 4382 345 3624 4745 124 4197 4978 873 2686 4266 989 2966 4180 1468 1932 4913 1140 4164 5060 3361 4952 5287 2584 4646 5260 809 2481 4893 1201 1532 3877 128 2430 4279 621 4810 5249 200 717 5066 2283 2998 4164 704 2587 4736 106 2080 3279 The present invention relates to a transmission method / apparatus.

[0025] In a fifth transmission method / apparatus of the present technology, LDPC coding is performed based on a check matrix of an LDPC code with a code length N of 17280 bits and a coding rate r of 11 / 16, and group-wise interleaving is performed to interleave the LDPC code in units of 360-bit bit groups. Then, the LDPC code is mapped to one of four signal points of QPSK (Quadrature Phase Shift Keying) in units of 2 bits. In the group-wise interleaving, the (i+1)th bit group from the beginning of the LDPC code is defined as bit group i, and the arrangement of bit groups 0 to 47 of the 17280-bit LDPC code is defined as bit group i. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 The LDPC code includes information bits and parity bits, the check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the information matrix portion is represented by a check matrix initial value table, and the check matrix initial value table is a table representing the position of an element of the information matrix portion for every 360 columns, 91 382 494 654 681 695 1643 2171 2576 3027 3115 3390 3633 3644 3812 3883 4474 4607 4674 384 396 982 988 1053 1867 2215 2345 2472 3323 3503 3573 3883 4159 4576 4917 5104 5130 456 580 1590 1715 1786 1843 1934 2251 2261 2466 2525 2958 3467 4334 4530 4779 4885 5021 227 381 394 502 1059 1108 1480 1508 1523 1620 1840 1996 2436 2989 3716 3957 4072 4243 4482 4517 4717 4910 5105 5220 5238 5279 376 957 1706 2028 2228 2439 2552 4249 5234 89 676 1098 1103 1127 1449 1605 2362 4640 66 613 1692 1901 2247 3025 3244 4864 5050 1628 2015 2596 521 802 3804 3178 4080 5057 344 3486 3948 595 2538 2964 300 1355 3476 1292 2761 4819 462 773 3996 133 3494 4342 37 3698 4382 345 3624 4745 124 4197 4978 873 2686 4266 989 2966 4180 1468 1932 4913 1140 4164 5060 3361 4952 5287 2584 4646 5260 809 2481 4893 1201 1532 3877 128 2430 4279 621 4810 5249 200 717 5066 2283 2998 4164 704 2587 4736 106 2080 3279 It has become.

[0026] A fifth receiving apparatus / method of the present technology includes a coding step of performing LDPC coding based on a parity check matrix of an LDPC code having a code length N of 17280 bits and a coding rate r of 11 / 16, a group-wise interleaving step of performing group-wise interleaving of the LDPC code in units of 360-bit bit groups, and a mapping step of mapping the LDPC code to one of four signal points of QPSK (Quadrature Phase Shift Keying) in units of 2 bits, wherein in the group-wise interleaving, the (i+1)th bit group from the beginning of the LDPC code is defined as bit group i, and a sequence of bit groups 0 to 47 of the 17280-bit LDPC code is mapped to bit group i. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 the LDPC code includes information bits and parity bits, the check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the information matrix portion is represented by a check matrix initial value table, the check matrix initial value table is a table representing the position of one element of the information matrix portion for every 360 columns, 91 382 494 654 681 695 1643 2171 2576 3027 3115 3390 3633 3644 3812 3883 4474 4607 4674 384 396 982 988 1053 1867 2215 2345 2472 3323 3503 3573 3883 4159 4576 4917 5104 5130 456 580 1590 1715 1786 1843 1934 2251 2261 2466 2525 2958 3467 4334 4530 4779 4885 5021 227 381 394 502 1059 1108 1480 1508 1523 1620 1840 1996 2436 2989 3716 3957 4072 4243 4482 4517 4717 4910 5105 5220 5238 5279 376 957 1706 2028 2228 2439 2552 4249 5234 89 676 1098 1103 1127 1449 1605 2362 4640 66 613 1692 1901 2247 3025 3244 4864 5050 1628 2015 2596 521 802 3804 3178 4080 5057 344 3486 3948 595 2538 2964 300 1355 3476 1292 2761 4819 462 773 3996 133 3494 4342 37 3698 4382 345 3624 4745 124 4197 4978 873 2686 4266 989 2966 4180 1468 1932 4913 1140 4164 5060 3361 4952 5287 2584 4646 5260 809 2481 4893 1201 1532 3877 128 2430 4279 621 4810 5249 200 717 5066 2283 2998 4164 704 2587 4736 106 2080 3279 The receiving device / method includes a decoding unit / step for decoding the LDPC code obtained from data transmitted by the transmission method.

[0027] In the fifth receiving device / method of the present technology, the LDPC code obtained from data transmitted by a fifth transmitting method is decoded.

[0028] A sixth transmission method / apparatus of the present technology includes an encoding step / unit that performs LDPC encoding based on a check matrix of an LDPC code having a code length N of 17280 bits and a coding rate r of 13 / 16, a group-wise interleaving step / unit that performs group-wise interleaving of the LDPC code in units of 360-bit bit groups, and a mapping step / unit that maps the LDPC code to one of four signal points of QPSK (Quadrature Phase Shift Keying) in units of 2 bits, and in the group-wise interleaving, a bit group (i+1) from the beginning of the LDPC code is defined as bit group i, and a sequence of bit groups 0 to 47 of the 17280-bit LDPC code is defined as bit group i. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 the LDPC code includes information bits and parity bits, the check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the information matrix portion is represented by a check matrix initial value table, the check matrix initial value table is a table representing the position of one element of the information matrix portion for every 360 columns, 225 274 898 916 1020 1055 1075 1179 1185 1343 1376 1569 1828 1972 2852 2957 3183 548 602 628 928 1077 1474 1557 1598 1935 1981 2110 2472 2543 2594 2721 2884 2981 59 69 518 900 1158 1325 1367 1480 1744 2069 2119 2406 2757 2883 2914 2966 3232 1330 1369 1712 2133 2206 2487 2596 2606 2612 2666 2726 2733 2754 2811 2948 3030 391 542 689 748 810 1716 1927 2006 2296 2340 2357 2514 2797 2887 2896 3226 256 410 799 1126 1377 1409 1518 1619 1829 2037 2303 2324 2472 2475 2874 2992 862 1522 1905 809 842 945 561 1001 2857 2132 2592 2905 217 401 1894 11 30 1860 210 1188 2418 1372 2273 2455 407 2537 2962 939 2401 2677 2521 3077 3173 1374 2250 2423 23 188 1320 472 714 2144 2727 2755 2887 1814 2824 2852 148 1695 1845 595 1059 2702 1879 2480 2578 17 411 559 146 783 2154 951 1391 1979 1507 1613 3106 642 882 2356 1008 1324 3125 196 1794 2474 1129 1544 2931 765 1681 2591 1550 1936 3048 1596 1607 2794 156 1053 2926 1246 1996 3179 348 752 1943 The present invention relates to a transmission method / apparatus.

[0029] In a sixth transmission method / apparatus of the present technology, LDPC coding is performed based on a check matrix of an LDPC code with a code length N of 17280 bits and a coding rate r of 13 / 16, and group-wise interleaving is performed to interleave the LDPC code in units of 360-bit bit groups. Then, the LDPC code is mapped to one of four signal points of QPSK (Quadrature Phase Shift Keying) in units of 2 bits. In the group-wise interleaving, the (i+1)th bit group from the beginning of the LDPC code is defined as bit group i, and the arrangement of bit groups 0 to 47 of the 17280-bit LDPC code is defined as bit group i. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 The LDPC code includes information bits and parity bits, the check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the information matrix portion is represented by a check matrix initial value table, and the check matrix initial value table is a table representing the position of an element of the information matrix portion for every 360 columns, 225 274 898 916 1020 1055 1075 1179 1185 1343 1376 1569 1828 1972 2852 2957 3183 548 602 628 928 1077 1474 1557 1598 1935 1981 2110 2472 2543 2594 2721 2884 2981 59 69 518 900 1158 1325 1367 1480 1744 2069 2119 2406 2757 2883 2914 2966 3232 1330 1369 1712 2133 2206 2487 2596 2606 2612 2666 2726 2733 2754 2811 2948 3030 391 542 689 748 810 1716 1927 2006 2296 2340 2357 2514 2797 2887 2896 3226 256 410 799 1126 1377 1409 1518 1619 1829 2037 2303 2324 2472 2475 2874 2992 862 1522 1905 809 842 945 561 1001 2857 2132 2592 2905 217 401 1894 11 30 1860 210 1188 2418 1372 2273 2455 407 2537 2962 939 2401 2677 2521 3077 3173 1374 2250 2423 23 188 1320 472 714 2144 2727 2755 2887 1814 2824 2852 148 1695 1845 595 1059 2702 1879 2480 2578 17 411 559 146 783 2154 951 1391 1979 1507 1613 3106 642 882 2356 1008 1324 3125 196 1794 2474 1129 1544 2931 765 1681 2591 1550 1936 3048 1596 1607 2794 156 1053 2926 1246 1996 3179 348 752 1943 It has become.

[0030] A sixth receiving apparatus / method of the present technology includes a coding step of performing LDPC coding based on a check matrix of an LDPC code having a code length N of 17280 bits and a coding rate r of 13 / 16, a group-wise interleaving step of performing group-wise interleaving of the LDPC code in units of 360-bit bit groups, and a mapping step of mapping the LDPC code to one of four signal points of QPSK (Quadrature Phase Shift Keying) in units of 2 bits, wherein in the group-wise interleaving, the (i+1)th bit group from the beginning of the LDPC code is defined as bit group i, and a sequence of bit groups 0 to 47 of the 17280-bit LDPC code is mapped to bit group i. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 the LDPC code includes information bits and parity bits, the check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the information matrix portion is represented by a check matrix initial value table, the check matrix initial value table is a table representing the position of one element of the information matrix portion for every 360 columns, 225 274 898 916 1020 1055 1075 1179 1185 1343 1376 1569 1828 1972 2852 2957 3183 548 602 628 928 1077 1474 1557 1598 1935 1981 2110 2472 2543 2594 2721 2884 2981 59 69 518 900 1158 1325 1367 1480 1744 2069 2119 2406 2757 2883 2914 2966 3232 1330 1369 1712 2133 2206 2487 2596 2606 2612 2666 2726 2733 2754 2811 2948 3030 391 542 689 748 810 1716 1927 2006 2296 2340 2357 2514 2797 2887 2896 3226 256 410 799 1126 1377 1409 1518 1619 1829 2037 2303 2324 2472 2475 2874 2992 862 1522 1905 809 842 945 561 1001 2857 2132 2592 2905 217 401 1894 11 30 1860 210 1188 2418 1372 2273 2455 407 2537 2962 939 2401 2677 2521 3077 3173 1374 2250 2423 23 188 1320 472 714 2144 2727 2755 2887 1814 2824 2852 148 1695 1845 595 1059 2702 1879 2480 2578 17 411 559 146 783 2154 951 1391 1979 1507 1613 3106 642 882 2356 1008 1324 3125 196 1794 2474 1129 1544 2931 765 1681 2591 1550 1936 3048 1596 1607 2794 156 1053 2926 1246 1996 3179 348 752 1943 The receiving device / method includes a decoding unit / step for decoding the LDPC code obtained from data transmitted by the transmission method.

[0031] In the sixth receiving device / method of the present technology, the LDPC code obtained from data transmitted by a sixth transmitting method is decoded.

[0032] The transmitting device and the receiving device may be independent devices or may be internal blocks constituting a single device. Effect of the Invention

[0033] According to the present technology, good communication quality can be ensured in data transmission using LDPC codes.

[0034] Note that the effects described herein are not necessarily limited to those described herein, and may be any of the effects described in this disclosure. [Brief description of the drawings]

[0035] [Figure 1] FIG. 2 is a diagram illustrating a check matrix H of an LDPC code. [Diagram 2] 1 is a flowchart illustrating a procedure for decoding an LDPC code. [Diagram 3] FIG. 2 is a diagram illustrating an example of a check matrix of an LDPC code. [Figure 4] FIG. 13 is a diagram illustrating an example of a Tanner graph of a parity check matrix. [Diagram 5] FIG. 13 is a diagram illustrating an example of a variable node. [Figure 6] FIG. 2 is a diagram illustrating an example of a check node. [Figure 7] 1 is a diagram illustrating an example of the configuration of an embodiment of a transmission system to which the present technology is applied. [Figure 8] 2 is a block diagram showing an example of the configuration of a transmission device 11. FIG. [Figure 9] 13 is a block diagram showing an example of the configuration of a bit interleaver 116. FIG. [Figure 10] FIG. 13 is a diagram illustrating an example of a check matrix. [Figure 11] FIG. 13 is a diagram illustrating an example of a parity matrix. [Figure 12] 1 is a diagram illustrating a check matrix of an LDPC code defined in the DVB-T.2 standard. [Figure 13] 1 is a diagram illustrating a check matrix of an LDPC code defined in the DVB-T.2 standard. [Figure 14] FIG. 1 is a diagram illustrating an example of a Tanner graph for decoding an LDPC code. [Figure 15]FIG. 1 is a diagram showing an example of a parity matrix HT having a staircase structure and a Tanner graph corresponding to the parity matrix HT. [Figure 16] 11 is a diagram showing an example of a parity matrix HT of a check matrix H corresponding to an LDPC code after parity interleaving. FIG. [Figure 17] 11 is a flowchart illustrating an example of processing performed by the bit interleaver 116 and the mapper 117. [Figure 18] 2 is a block diagram showing an example of the configuration of an LDPC encoder 115. FIG. [Figure 19] 11 is a flowchart illustrating an example of a process of the LDPC encoder 115. [Figure 20] FIG. 13 is a diagram showing an example of a parity check matrix initial value table with a coding rate of 1 / 4 and a code length of 16200. [Figure 21] 11 is a diagram for explaining a method of obtaining a check matrix H from a check matrix initial value table. FIG. [Figure 22] FIG. 2 is a diagram illustrating a structure of a check matrix. [Diagram 23] FIG. 13 is a diagram illustrating an example of a check matrix initial value table. [Figure 24] 13 is a diagram for explaining matrix A generated from the check matrix initial value table. FIG. [Diagram 25] FIG. 1 is a diagram for explaining parity interleaving of a B matrix. [Figure 26] 11 is a diagram illustrating a C matrix generated from a check matrix initial value table. FIG. [Figure 27] FIG. 1 is a diagram for explaining parity interleaving of a D matrix. [Figure 28] FIG. 13 is a diagram showing a parity check matrix obtained by performing column permutation as parity deinterleaving to restore parity interleaving to its original state. [Figure 29] FIG. 13 is a diagram showing a transformed check matrix obtained by performing row permutation on a check matrix. [Diagram 30] FIG. 13 is a diagram illustrating an example of a check matrix initial value table for a Type A code where N=17280 bits and r=2 / 16. [Diagram 31] FIG. 13 is a diagram showing an example of a check matrix initial value table for a Type A code where N=17280 bits and r=3 / 16. [Diagram 32] FIG. 13 is a diagram showing an example of a check matrix initial value table for a type-A code where N=17280 bits and r=4 / 16. [Diagram 33] FIG. 13 is a diagram showing an example of a check matrix initial value table for a type-A code where N=17280 bits and r=5 / 16. [Diagram 34] FIG. 11 is a diagram showing an example of a check matrix initial value table for a type-A code where N=17280 bits and r=6 / 16. [Diagram 35] FIG. 11 is a diagram showing an example of a check matrix initial value table for a type-A code where N=17280 bits and r=7 / 16. [Diagram 36] FIG. 13 is a diagram showing an example of a check matrix initial value table for a Type B code where N=17280 bits and r=7 / 16. [Figure 37] FIG. 13 is a diagram showing an example of a check matrix initial value table for a Type B code where N=17280 bits and r=8 / 16. [Figure 38] FIG. 13 is a diagram showing an example of a check matrix initial value table for a Type B code where N=17280 bits and r=9 / 16. [Figure 39] FIG. 13 is a diagram showing an example of a check matrix initial value table for a Type B code where N=17280 bits and r=10 / 16. [Diagram 40] FIG. 13 is a diagram showing an example of a check matrix initial value table for a Type B code where N=17280 bits and r=11 / 16. [Diagram 41] FIG. 13 is a diagram showing an example of a check matrix initial value table for a Type B code where N=17280 bits and r=12 / 16. [Diagram 42] FIG. 13 is a diagram showing an example of a check matrix initial value table for a Type B code where N=17280 bits and r=13 / 16. [Diagram 43] FIG. 11 is a diagram showing an example of a check matrix initial value table for a Type B code where N=17280 bits and r=14 / 16. [Diagram 44]FIG. 13 is a diagram showing an example of a Tanner graph of an ensemble of degree sequences with column weight 3 and row weight 6. [Diagram 45] FIG. 13 is a diagram showing an example of a Tanner graph of a multi-edge type ensemble. [Diagram 46] FIG. 1 is a diagram illustrating a parity check matrix of the Type A method. [Figure 47] FIG. 1 is a diagram illustrating a parity check matrix of the Type A method. [Figure 48] FIG. 1 is a diagram illustrating a check matrix of the Type B method. [Figure 49] FIG. 1 is a diagram illustrating a check matrix of the Type B method. [Figure 50] FIG. 13 is a diagram showing a check matrix initial value table for the new type-A code with N=17280 bits and r=4 / 16. [Figure 51] FIG. 13 is a diagram showing parameters of a check matrix H of a new type-A code with r=4 / 16. [Figure 52] FIG. 13 is a diagram showing a check matrix initial value table for the new type-B code with N=17280 bits and r=9 / 16. [Diagram 53] FIG. 13 is a diagram showing parameters of a check matrix H of a new type-B code with r=9 / 16. [Figure 54] FIG. 11 is a diagram illustrating an example of coordinates of a UC signal point when the modulation method is QPSK. [Figure 55] FIG. 11 is a diagram showing an example of the coordinates of signal points of a 2D-NUC when the modulation method is 16QAM. [Figure 56] FIG. 11 is a diagram showing an example of the coordinates of signal points of 1D-NUC when the modulation method is 1024QAM. [Figure 57] FIG. 1 is a diagram showing the relationship between a 1024QAM symbol y and a position vector u. [Figure 58] FIG. 1 is a diagram illustrating an example of coordinates zq of a signal point of QPSK-UC. [Figure 59] FIG. 1 is a diagram illustrating an example of coordinates zq of a signal point of QPSK-UC. [Figure 60] FIG. 11 is a diagram illustrating an example of coordinates zq of a signal point of 16QAM-UC. [Figure 61]FIG. 11 is a diagram illustrating an example of coordinates zq of a signal point of 16QAM-UC. [Figure 62] FIG. 11 is a diagram illustrating an example of coordinates zq of a signal point of 64QAM-UC. [Figure 63] FIG. 11 is a diagram illustrating an example of coordinates zq of a signal point of 64QAM-UC. [Figure 64] FIG. 13 is a diagram illustrating an example of coordinates zq of a signal point of 256QAM-UC. [Figure 65] FIG. 13 is a diagram illustrating an example of coordinates zq of a signal point of 256QAM-UC. [Figure 66] FIG. 11 is a diagram illustrating an example of coordinates zq of a signal point of 1024QAM-UC. [Figure 67] FIG. 11 is a diagram illustrating an example of coordinates zq of a signal point of 1024QAM-UC. [Figure 68] FIG. 13 is a diagram illustrating an example of coordinates zq of a signal point of 4096QAM-UC. [Figure 69] FIG. 13 is a diagram illustrating an example of coordinates zq of a signal point of 4096QAM-UC. [Figure 70] FIG. 13 is a diagram illustrating an example of coordinates zs of a signal point of 16QAM-2D-NUC. [Figure 71] FIG. 13 is a diagram illustrating an example of the coordinates zs of a signal point of 64QAM-2D-NUC. [Figure 72] FIG. 13 is a diagram showing an example of the coordinates zs of a signal point of 256QAM-2D-NUC. [Figure 73] FIG. 13 is a diagram showing an example of the coordinates zs of a signal point of 256QAM-2D-NUC. [Figure 74] FIG. 11 is a diagram showing an example of coordinates zs of a signal point of 1024QAM-1D-NUC. [Figure 75] FIG. 1 is a diagram showing the relationship between a 1024QAM symbol y and a position vector u. [Figure 76] FIG. 11 is a diagram showing an example of the coordinates zs of a signal point of 4096QAM-1D-NUC. [Figure 77] 1 is a diagram showing the relationship between a 4096QAM symbol y and a position vector u. [Figure 78] 1 is a diagram showing the relationship between a 4096QAM symbol y and a position vector u. [Figure 79] FIG. 2 is a diagram for explaining block interleaving performed by block interleaver 25. [Figure 80] FIG. 2 is a diagram for explaining block interleaving performed by block interleaver 25. [Figure 81] FIG. 2 is a diagram for explaining group-wise interleaving performed by group-wise interleaver 24. [Figure 82] FIG. 11 is a diagram illustrating a first example of a GW pattern for an LDPC code having a code length N of 17280 bits. [Figure 83] FIG. 11 is a diagram illustrating a second example of a GW pattern for an LDPC code having a code length N of 17280 bits. [Figure 84] FIG. 11 is a diagram illustrating a third example of a GW pattern for an LDPC code having a code length N of 17280 bits. [Figure 85] FIG. 11 is a diagram illustrating a fourth example of a GW pattern for an LDPC code having a code length N of 17280 bits. [Figure 86] FIG. 5 is a diagram illustrating a fifth example of a GW pattern for an LDPC code having a code length N of 17280 bits. [Figure 87] FIG. 13 is a diagram showing a sixth example of a GW pattern for an LDPC code having a code length N of 17280 bits. [Figure 88] FIG. 13 is a diagram showing a seventh example of a GW pattern for an LDPC code having a code length N of 17280 bits. [Figure 89] FIG. 13 is a diagram illustrating an eighth example of a GW pattern for an LDPC code having a code length N of 17280 bits. [Figure 90] FIG. 13 is a diagram showing a ninth example of a GW pattern for an LDPC code having a code length N of 17280 bits. [Figure 91] FIG. 10 is a diagram illustrating a tenth example of a GW pattern for an LDPC code having a code length N of 17280 bits. [Figure 92] FIG. 11 is a diagram showing an eleventh example of a GW pattern for an LDPC code having a code length N of 17280 bits. [Figure 93]FIG. 12 is a diagram illustrating a twelfth example of a GW pattern for an LDPC code having a code length N of 17280 bits. [Figure 94] FIG. 13 is a diagram showing a thirteenth example of a GW pattern for an LDPC code having a code length N of 17280 bits. [Figure 95] FIG. 14 is a diagram showing a fourteenth example of a GW pattern for an LDPC code having a code length N of 17280 bits. [Figure 96] FIG. 15 is a diagram showing a 15th example of a GW pattern for an LDPC code having a code length N of 17280 bits. [Figure 97] FIG. 16 is a diagram illustrating a 16th example of a GW pattern for an LDPC code having a code length N of 17280 bits. [Figure 98] FIG. 17 is a diagram showing a 17th example of a GW pattern for an LDPC code having a code length N of 17280 bits. [Figure 99] FIG. 18 is a diagram illustrating an 18th example of a GW pattern for an LDPC code having a code length N of 17280 bits. [Figure 100] FIG. 19 is a diagram showing a 19th example of a GW pattern for an LDPC code having a code length N of 17280 bits. [Figure 101] FIG. 20 is a diagram illustrating a twentieth example of a GW pattern for an LDPC code having a code length N of 17280 bits. [Figure 102] FIG. 21 is a diagram showing a 21st example of a GW pattern for an LDPC code having a code length N of 17280 bits. [Figure 103] FIG. 22 is a diagram illustrating a 22nd example of a GW pattern for an LDPC code having a code length N of 17280 bits. [Figure 104] FIG. 23 is a diagram showing a 23rd example of a GW pattern for an LDPC code having a code length N of 17280 bits. [Figure 105] FIG. 24 is a diagram showing a 24th example of a GW pattern for an LDPC code having a code length N of 17280 bits. [Figure 106] FIG. 25 is a diagram illustrating a 25th example of a GW pattern for an LDPC code having a code length N of 17280 bits. [Figure 107]FIG. 26 is a diagram illustrating a 26th example of a GW pattern for an LDPC code having a code length N of 17280 bits. [Figure 108] FIG. 27 is a diagram illustrating a 27th example of a GW pattern for an LDPC code having a code length N of 17280 bits. [Figure 109] FIG. 28 is a diagram illustrating a 28th example of a GW pattern for an LDPC code having a code length N of 17280 bits. [Figure 110] FIG. 29 is a diagram showing a 29th example of a GW pattern for an LDPC code having a code length N of 17280 bits. [Figure 111] FIG. 30 is a diagram illustrating a 30th example of a GW pattern for an LDPC code having a code length N of 17280 bits. [Figure 112] FIG. 31 is a diagram showing a 31st example of a GW pattern for an LDPC code having a code length N of 17280 bits. [Figure 113] FIG. 13 is a diagram illustrating a 32nd example of a GW pattern for an LDPC code having a code length N of 17280 bits. [Fig. 114] FIG. 33 is a diagram showing a 33rd example of a GW pattern for an LDPC code having a code length N of 17280 bits. [Fig. 115] FIG. 34 is a diagram showing a 34th example of a GW pattern for an LDPC code having a code length N of 17280 bits. [Fig. 116] FIG. 35 is a diagram showing a 35th example of a GW pattern for an LDPC code having a code length N of 17280 bits. [Fig. 117] FIG. 36 is a diagram illustrating a 36th example of a GW pattern for an LDPC code having a code length N of 17280 bits. [Fig. 118] FIG. 37 is a diagram showing a 37th example of a GW pattern for an LDPC code having a code length N of 17280 bits. [Figure 119] FIG. 38 is a diagram illustrating a 38th example of a GW pattern for an LDPC code having a code length N of 17280 bits. [Figure 120] FIG. 13 is a diagram showing a 39th example of a GW pattern for an LDPC code having a code length N of 17280 bits. [Figure 121]FIG. 40 is a diagram illustrating a 40th example of a GW pattern for an LDPC code having a code length N of 17280 bits. [Figure 122] FIG. 41 is a diagram showing a 41st example of a GW pattern for an LDPC code having a code length N of 17280 bits. [Figure 123] FIG. 42 is a diagram illustrating a 42nd example of a GW pattern for an LDPC code having a code length N of 17280 bits. [Figure 124] FIG. 43 is a diagram showing a 43rd example of a GW pattern for an LDPC code having a code length N of 17280 bits. [Fig. 125] FIG. 44 is a diagram showing a 44th example of a GW pattern for an LDPC code having a code length N of 17280 bits. [Fig. 126] FIG. 45 is a diagram showing a 45th example of a GW pattern for an LDPC code having a code length N of 17280 bits. [Figure 127] 2 is a block diagram showing an example of the configuration of a receiving device 12. FIG. [Figure 128] 13 is a block diagram showing an example of the configuration of a bit deinterleaver 165. FIG. [Figure 129] 11 is a flowchart illustrating an example of processing performed by the demapper 164, the bit deinterleaver 165, and the LDPC decoder 166. [Fig. 130] FIG. 2 is a diagram illustrating an example of a check matrix of an LDPC code. [Fig. 131] 11 is a diagram showing an example of a matrix (transformed parity check matrix) obtained by performing row permutation and column permutation on a parity check matrix. FIG. [Fig. 132] FIG. 13 is a diagram showing an example of a transformed check matrix divided into 5×5 units. [Fig. 133] FIG. 11 is a block diagram showing an example of the configuration of a decoding device that performs P node operations collectively. [Fig. 134] 2 is a block diagram showing an example of the configuration of an LDPC decoder 166. FIG. [Fig. 135] FIG. 2 is a diagram for explaining block deinterleaving performed by block deinterleaver 54. [Fig. 136] 13 is a block diagram showing another example configuration of the bit deinterleaver 165. FIG. [Fig. 137] It is a block diagram showing a first configuration example of a receiving system to which the receiving device 12 can be applied. [Fig. 138] It is a block diagram showing a second configuration example of a receiving system to which the receiving device 12 can be applied. [Figure 139] It is a block diagram showing a third configuration example of a receiving system to which the receiving device 12 can be applied. [Fig. 140] It is a block diagram showing a configuration example of an embodiment of a computer to which the present technology is applied.

Embodiments for Carrying Out the Invention

[0036] Hereinafter, embodiments of the present technology will be described. Prior to that, the LDPC code will be described.

[0037] <LDPC Code>

[0038] Note that the LDPC code is a linear code and does not necessarily have to be binary. Here, it will be described as being binary.

[0039] The LDPC code is most characterized in that the parity check matrix defining the LDPC code is sparse. Here, a sparse matrix is a matrix in which the number of "1"s in the elements of the matrix is very small (a matrix in which most elements are 0).

[0040] FIG. 1 is a diagram showing an example of the parity check matrix H of the LDPC code.

[0041] In the parity check matrix H of FIG. 1, the weight (column weight) (number of "1"s) (weight) of each column is "3", and the weight (row weight) of each row is "6".

[0042] In encoding with the LDPC code (LDPC encoding), for example, a generator matrix G is generated based on the parity check matrix H, and this generator matrix G is multiplied by binary information bits to generate a codeword (LDPC code).

[0043] Specifically, the coding device that performs LDPC coding first generates a transposed matrix H T Between the formula GH T Here, when generator matrix G is a K×N matrix, the encoding device multiplies generator matrix G by a bit string (vector u) of K information bits to generate a codeword c (=uG) of N bits. The codeword (LDPC code) generated by this encoding device is received at the receiving side via a predetermined communication path.

[0044] Decoding of LDPC codes is an algorithm proposed by Gallager called Probabilistic Decoding, and can be performed by a message passing algorithm using belief propagation on a so-called Tanner graph consisting of variable nodes (also called message nodes) and check nodes. Hereinafter, variable nodes and check nodes will be referred to simply as nodes where appropriate.

[0045] FIG. 2 is a flowchart showing the procedure for decoding an LDPC code.

[0046] In the following, the real value (received LLR) that expresses the likelihood of the value being "0" of the i-th code bit of the LDPC code (one codeword) received on the receiving side as a log likelihood ratio is referred to as the received value u 0i Also, the message output from the check node is called u j Let the message output from the variable node be v i Let us assume that.

[0047] First, in decoding an LDPC code, as shown in FIG. 2, in step S11, an LDPC code is received, and a message (check node message) u jis initialized to "0", and a variable k, which is an integer and serves as a counter for repeated processing, is initialized to "0", and the process proceeds to step S12. In step S12, the received value u 0i Based on this, the message (variable node message) v is generated by performing the calculation (variable node calculation) shown in Eq. (1). i is required, and this message v i Based on this, the message u is generated by performing the operation (check node operation) shown in equation (2). j is required.

[0048]

number

[0049]

number

[0050] Here, d in Eq. (1) and Eq. (2) v and d c are parameters that can be arbitrarily selected and indicate the number of "1"s in the vertical direction (columns) and horizontal direction (rows) of the check matrix H. For example, in the case of an LDPC code ((3,6) LDPC code) for a check matrix H with a column weight of 3 and a row weight of 6 as shown in FIG. 1, d v =3,d c =6.

[0051] In the variable node operation of formula (1) and the check node operation of formula (2), messages input from edges (lines connecting variable nodes and check nodes) that are trying to output messages are not included in the operation, so the range of operation is 1 to d v -1 or 1 to d cThe check node operation of equation (2) is actually performed by creating a table of function R(v1, v2) shown in equation (3), which is defined as one output for two inputs v1 and v2, in advance, and using this table continuously (recursively) as shown in equation (4).

[0052]

number

[0053]

number

[0054] In step S12, the variable k is further incremented by "1", and the process proceeds to step S13. In step S13, it is determined whether or not the variable k is greater than a predetermined number of iterative decoding cycles C. If it is determined in step S13 that the variable k is not greater than C, the process returns to step S12, and the same processes are repeated thereafter.

[0055] Also, in step S13, if it is determined that the variable k is greater than C, the process proceeds to step S14, where the message v i is calculated and output, and the LDPC code decoding process is completed.

[0056]

number

[0057] Here, the calculation of formula (5) is different from the variable node calculation of formula (1) in that it returns messages u from all edges connected to the variable node. j This is done using

[0058] FIG. 3 is a diagram showing an example of a parity check matrix H of a (3,6) LDPC code (coding rate 1 / 2, code length 12).

[0059] In the parity check matrix H in FIG. 3, the column weight is 3 and the row weight is 6, similarly to FIG.

[0060] FIG. 4 is a diagram showing a Tanner graph of the parity check matrix H in FIG.

[0061] Here, in Figure 4, a plus sign "+" indicates a check node, and an equal sign "=" indicates a variable node. The check nodes and variable nodes correspond to the rows and columns of the parity check matrix H, respectively. The connections between the check nodes and variable nodes are edges, which correspond to the elements "1" of the parity check matrix.

[0062] That is, when the element in the j-th row and i-th column of the parity check matrix is ​​1, the i-th variable node from the top (the node marked "=") and the j-th check node from the top (the node marked "+") in Fig. 4 are connected by a branch. The branch indicates that the code bit corresponding to the variable node has a constraint corresponding to the check node.

[0063] In a Sum Product Algorithm, which is a decoding method for LDPC codes, variable node calculations and check node calculations are performed repeatedly.

[0064] FIG. 5 is a diagram showing variable node operations performed at the variable node.

[0065] At the variable node, the message v corresponding to the branch to be calculated is i is the set of messages u1 and u2 from the remaining branches connected to the variable node, and the received value u 0i The messages corresponding to the other edges can be calculated in a similar manner.

[0066] FIG. 6 is a diagram illustrating check node operations performed at a check node.

[0067] Here, the check node operation of formula (2) can be rewritten as formula (6) using the relationship of the formula a×b=exp{ln(|a|)+ln(|b|)}×sign(a)×sign(b), where sign(x) is 1 when x≧0 and −1 when x<0.

[0068]

number

[0069] If we define the function φ(x) as φ(x)=ln(tanh(x / 2)) for x≧0, then the formula φ -1 (x)=2tanh -1 (e -x ) holds, so equation (6) can be transformed into equation (7).

[0070]

number

[0071] At the check node, the check node operation of equation (2) is performed according to equation (7).

[0072] That is, at the check node, as shown in Figure 6, the message u corresponding to the branch to be calculated is j is calculated by the check node calculation of formula (7) using messages v1, v2, v3, v4, and v5 from the remaining branches connected to the check node. Messages corresponding to other branches are calculated in the same way.

[0073] The function φ(x) in equation (7) is expressed as φ(x)=ln((e x +1) / (e x -1), and for x>0, φ(x)=φ -1 (x). The functions φ(x) and φ -1 When (x) is implemented in hardware, it may be implemented using a look-up table (LUT), but both will use the same LUT.

[0074] <Example of a transmission system configuration using this technology>

[0075] FIG. 7 is a diagram showing an example of the configuration of an embodiment of a transmission system to which the present technology is applied (a system refers to a logical collection of multiple devices, and it does not matter whether the devices are located in the same housing or not).

[0076] In FIG. 7, the transmission system includes a transmitting device 11 and a receiving device 12 .

[0077] The transmitting device 11 transmits (broadcasts) (transmits), for example, a television broadcast program, etc. That is, the transmitting device 11 encodes target data to be transmitted, such as image data and audio data as a program, into an LDPC code, and transmits the encoded data via a communication path 13, such as a satellite line, terrestrial wave, or cable (wired line).

[0078] The receiving device 12 receives the LDPC code transmitted from the transmitting device 11 via the communication path 13, decodes it into target data, and outputs it.

[0079] Here, the LDPC code used in the transmission system of FIG. 7 is known to exhibit extremely high performance in an AWGN (Additive White Gaussian Noise) communication channel.

[0080] On the other hand, burst errors and erasures may occur in the communication path 13. For example, in an OFDM (Orthogonal Frequency Division Multiplexing) system, particularly when the communication path 13 is a terrestrial wave, in a multipath environment where the D / U (Desired to Undesired Ratio) is 0 dB (Undesired = echo power is equal to Desired = main path power), the power of a specific symbol may become 0 (erasure) depending on the delay of the echo (path other than the main path).

[0081] Even in the case of flutter (a communication channel with zero delay and where an echo with a Doppler frequency is added), if the D / U is 0 dB, the Doppler frequency can cause the power of the entire OFDM symbol at a specific time to become 0 (erasure).

[0082] Furthermore, burst errors may occur due to the condition of the wiring from a receiving section (not shown) such as an antenna that receives a signal from the transmitting device 11 to the receiving device 12, or due to instability in the power supply of the receiving device 12.

[0083] On the other hand, in decoding the LDPC code, in the variable node corresponding to the column of the check matrix H, and in turn, the code bit of the LDPC code (the received value u 0i Since the variable node calculation of equation (1) involves the addition of (a), if an error occurs in the code bit used in the variable node calculation, the accuracy of the obtained message decreases.

[0084] In decoding an LDPC code, at a check node, the check node calculation of equation (7) is performed using a message obtained at a variable node connected to that check node. Therefore, if there are a large number of check nodes where multiple connected variable nodes (corresponding code bits of the LDPC code) simultaneously have errors (including erasures), the decoding performance deteriorates.

[0085] That is, for example, when two or more variable nodes connected to the check node are simultaneously erased, the check node returns to all the variable nodes a message with equal probability of the value being 0 and the value being 1. In this case, the check node returning the message with equal probability does not contribute to one decoding process (one set of variable node calculation and check node calculation), and as a result, the decoding process needs to be repeated many times, degrading the decoding performance and increasing the power consumption of the receiving device 12 that decodes the LDPC code.

[0086] Therefore, in the transmission system of FIG. 7, it is possible to improve the tolerance to burst errors and erasures while maintaining the performance in an AWGN communication path (AWGN channel).

[0087] <Configuration example of the transmitting device 11>

[0088] FIG. 8 is a block diagram showing an example of the configuration of the transmission device 11 of FIG.

[0089] In the transmitting device 11, one or more input streams as target data are supplied to a mode adaptation / multiplexer 111.

[0090] The mode adaptation / multiplexer 111 performs processing such as mode selection and multiplexing of one or more input streams supplied thereto as necessary, and supplies the resulting data to a padder 112 .

[0091] The padder 112 performs necessary zero padding (insertion of nulls) on the data from the mode adaptation / multiplexer 111 and supplies the resulting data to a BB scrambler 113.

[0092] The BB scrambler 113 performs BB scrambling (Base-Band Scrambling) on ​​the data from the padder 112 and supplies the resulting data to a BCH encoder 114 .

[0093] The BCH encoder 114 BCH-encodes the data from the BB scrambler 113, and supplies the resulting data to an LDPC encoder 115 as LDPC target data that is to be LDPC-encoded.

[0094] The LDPC encoder 115 (encoding unit) performs LDPC encoding on the LDPC target data from the BCH encoder 114 according to, for example, a check matrix in which the parity matrix, which is the part corresponding to the parity bits of the LDPC code, has a dual diagonal structure, and outputs an LDPC code in which the LDPC target data is information bits.

[0095] That is, the LDPC encoder 115 performs LDPC encoding on the LDPC target data, for example, into an LDPC code (corresponding to a parity check matrix) defined in a predetermined standard such as DVB-S.2, DVB-T.2, DVB-C.2, ATSC3.0, or another LDPC code, and outputs the resulting LDPC code.

[0096] Here, the LDPC code specified in the DVB-S.2 and ATSC3.0 standards is an IRA (Irregular Repeat Accumulate) code, and the parity matrix (part or all) in the check matrix of the LDPC code has a staircase structure. The parity matrix and the staircase structure will be described later. The IRA code is described, for example, in "Irregular Repeat-Accumulate Codes," H. Jin, A. Khandekar, and RJ McEliece, in Proceedings of 2nd International Symposium on Turbo codes and Related Topics, pp. 1-8, Sept. 2000.

[0097] The LDPC code output by the LDPC encoder 115 is supplied to a bit interleaver 116 .

[0098] The bit interleaver 116 performs bit interleaving, which will be described later, on the LDPC code from the LDPC encoder 115 , and supplies the bit-interleaved LDPC code to a mapper 117 .

[0099] The mapper 117 performs orthogonal modulation (multi-level modulation) by mapping the LDPC code from the bit interleaver 116 to a signal point representing one symbol of orthogonal modulation in units of one or more code bits (symbol units) of the LDPC code.

[0100] That is, the mapper 117 performs orthogonal modulation by mapping the LDPC code from the bit interleaver 116 to a signal point determined by a modulation method that performs orthogonal modulation of the LDPC code on a constellation that is an IQ plane defined by an I axis representing an I component in phase with the carrier wave and a Q axis representing a Q component orthogonal to the carrier wave.

[0101] The number of signal points of the constellation used in the modulation method of the quadrature modulation performed by the mapper 117 is 2m In this case, the m-bit code bits of the LDPC code are treated as a symbol (1 symbol), and the mapper 117 divides the LDPC code from the bit interleaver 116 into 2 m are mapped to a signal point representing a symbol among the signal points.

[0102] Here, the modulation method of the quadrature modulation performed by the mapper 117 includes, for example, modulation methods defined in the standards such as DVB-S.2 and ATSC3.0, and other modulation methods, that is, for example, BPSK (Binary Phase Shift Keying), QPSK (Quadrature Phase Shift Keying), 8PSK (Phase-Shift Keying), 16APSK (Amplitude Phase-Shift Keying), 32APSK, 16QAM (Quadrature Amplitude Modulation), 16QAM, 64QAM, 256QAM, 1024QAM, 4096QAM, 4PAM (Pulse Amplitude Modulation), etc. In the mapper 117, which modulation method is used for the quadrature modulation is set in advance according to, for example, the operation of the operator of the transmission device 11.

[0103] The data obtained by the processing in the mapper 117 (the mapping result of mapping symbols to signal points) is supplied to a time interleaver 118 .

[0104] The time interleaver 118 performs time interleaving (interleaving in the time direction) on a symbol-by-symbol basis on the data from the mapper 117, and supplies the resulting data to a SISO / MISO (Single Input Single Output / Multiple Input Single Output) encoder) 119.

[0105] The SISO / MISO encoder 119 performs space-time coding on the data from the time interleaver 118 and supplies the result to a frequency interleaver 120 .

[0106] The frequency interleaver 120 performs frequency interleaving (interleaving in the frequency direction) on a symbol-by-symbol basis on the data from the SISO / MISO encoder 119 , and supplies the data to a frame builder & resource allocation unit (Frame Builder & Resource Allocation) 131 .

[0107] On the other hand, the BCH encoder 121 is supplied with control data (signalling) for transmission control, such as BB signaling (Base Band Signalling) (BB Header), for example.

[0108] The BCH encoder 121 BCH-encodes the control data supplied thereto in the same manner as the BCH encoder 114 , and supplies the resulting data to the LDPC encoder 122 .

[0109] The LDPC encoder 122 LDPC-encodes the data from the BCH encoder 121 as LDPC target data in the same manner as the LDPC encoder 115 , and supplies the resulting LDPC code to the mapper 123 .

[0110] Similar to mapper 117, mapper 123 performs orthogonal modulation by mapping the LDPC code from LDPC encoder 122 to a signal point representing one symbol of orthogonal modulation in units of one or more code bits (symbol units) of the LDPC code, and supplies the resulting data to frequency interleaver 124.

[0111] Similar to the frequency interleaver 120 , the frequency interleaver 124 performs frequency interleaving on the data from the mapper 123 in symbol units, and supplies the data to a frame builder / resource allocation unit 131 .

[0112] The frame builder / resource allocation unit 131 inserts pilot symbols into required positions in the data (symbols) from the frequency interleavers 120 and 124, and constructs a frame consisting of a predetermined number of symbols (e.g., a PL (Physical Layer) frame, a T2 frame, a C2 frame, etc.) from the resulting data (symbols), and supplies it to an OFDM generation unit 132.

[0113] The OFDM generating unit 132 generates an OFDM signal corresponding to the frame from the frame supplied from the frame builder / resource allocating unit 131, and transmits the signal via the communication path 13 (FIG. 7).

[0114] The transmitting device 11 can be configured without some of the blocks shown in FIG. 8, such as the time interleaver 118, the SISO / MISO encoder 119, the frequency interleaver 120, and the frequency interleaver 124.

[0115] <Example of the configuration of the bit interleaver 116>

[0116] FIG. 9 is a block diagram showing an example of the configuration of the bit interleaver 116 in FIG.

[0117] The bit interleaver 116 has a function of interleaving data, and is made up of a parity interleaver 23 , a group-wise interleaver 24 , and a block interleaver 25 .

[0118] The parity interleaver 23 performs parity interleaving to interleave the parity bits of the LDPC code from the LDPC encoder 115 at the positions of other parity bits, and supplies the LDPC code after the parity interleaving to the group-wise interleaver 24.

[0119] The group-wise interleaver 24 performs group-wise interleaving on the LDPC code from the parity interleaver 23, and supplies the LDPC code after the group-wise interleaving to the block interleaver 25.

[0120] Here, in the group-wise interleaving, the LDPC code for one code is divided into 360-bit units equal to the parallel factor P described later from the beginning, and the 360 bits of one division are interleaved in bit group units with the LDPC code from the parity interleaver 23.

[0121] When performing group-wise interleaving, the error rate can be improved compared to the case where group-wise interleaving is not performed. As a result, good communication quality can be ensured in data transmission.

[0122] The block interleaver 25 performs block interleaving for demultiplexing the LDPC code from the group-wise interleaver 24. For example, the LDPC code for one code is symbolized into m-bit symbols which are the unit of mapping, and supplied to the mapper 117 (FIG. 8).

[0123] Here, in the block interleaving, for example, columns as storage areas for storing a predetermined number of bits in the column (vertical) direction are arranged in the row (horizontal) direction by a number equal to the number of bits m of the symbol. The LDPC code from the group-wise interleaver 24 is written in the column direction and read in the row direction, so that the LDPC code is symbolized into m-bit symbols.

[0124] <Check Matrix of LDPC Code>

[0125] FIG. 10 is a diagram showing an example of the check matrix H used for LDPC encoding in the LDPC encoder 115 of FIG. 8.

[0126] The check matrix H has an LDGM (Low-Density Generation Matrix) structure, and the information matrix H A and the parity matrix H corresponding to the parity bits T Therefore, the formula H = [H A |H T ](information matrix H A The elements of are the left elements, and the parity matrix H T The right-hand elements of the matrix are

[0127] Here, the number of information bits and the number of parity bits among the code bits of one LDPC code (one code word) are called the information length K and the parity length M, respectively, and the number of code bits of one LDPC code (one code word) is called the code length N (=K+M).

[0128] The information length K and parity length M for an LDPC code with a certain code length N are determined by the coding rate. Also, the check matrix H is a matrix with M×N rows and N columns (a matrix with M rows and N columns). A is an M × K matrix, and the parity matrix H T is an M × M matrix.

[0129] FIG. 11 shows a parity matrix H of a check matrix H used for LDPC encoding in the LDPC encoder 115 of FIG. T FIG.

[0130] Parity matrix H of check matrix H used for LDPC encoding by LDPC encoder 115 T For example, a parity matrix H similar to the check matrix H of the LDPC code defined in standards such as DVB-T.2 is used. T can be adopted.

[0131] Parity matrix H of the check matrix H of the LDPC code specified in standards such as DVB-T.2 TAs shown in FIG. 11, the parity matrix H T The row weight is 1 for the first row and 2 for all remaining rows. The column weight is 1 for the last column and 2 for all remaining columns.

[0132] As mentioned above, the parity matrix H T An LDPC code for a check matrix H having a staircase structure can be easily generated by using the check matrix H.

[0133] That is, the LDPC code (one code word) is represented by a row vector c, and the column vector obtained by transposing the row vector is represented by c. T In addition, the information bit portion of row vector c, which is an LDPC code, is represented by row vector A, and the parity bit portion is represented by row vector T.

[0134] In this case, row vector c can be expressed as c = [A|T] (a row vector with the elements of row vector A as the left elements and the elements of row vector T as the right elements) with row vector A as the information bits and row vector T as the parity bits.

[0135] The check matrix H and the row vector c=[A|T] as the LDPC code are expressed by the formula Hc T = 0, and the formula Hc T = 0, the row vector T as the parity bit that constitutes the row vector c = [A|T] is the check matrix H = [H A |H T ]'s parity matrix H T When the step structure shown in FIG. 11 is used, the formula Hc T = 0 column vector Hc T This can be found sequentially (in order) by setting the elements of each row to 0, starting from the first row.

[0136] FIG. 12 is a diagram for explaining a check matrix H of an LDPC code defined in standards such as DVB-T.2.

[0137] The first KX columns of the check matrix H of an LDPC code defined in standards such as DVB-T.2 have a column weight of X, the next K3 columns have a column weight of 3, the next M-1 columns have a column weight of 2, and the last column has a column weight of 1.

[0138] Here, KX+K3+M-1+1 is equal to the code length N.

[0139] FIG. 13 is a diagram showing the column numbers KX, K3, and M, and the column weight X for each coding rate r of the LDPC code defined in standards such as DVB-T.2.

[0140] Standards such as DVB-T.2 prescribe LDPC codes with code lengths N of 64,800 bits and 16,200 bits.

[0141] For an LDPC code with a code length N of 64,800 bits, eleven nominal rates 1 / 4, 1 / 3, 2 / 5, 1 / 2, 3 / 5, 2 / 3, 3 / 4, 4 / 5, 5 / 6, 8 / 9, and 9 / 10 are specified, and for an LDPC code with a code length N of 16,200 bits, ten nominal rates 1 / 4, 1 / 3, 2 / 5, 1 / 2, 3 / 5, 2 / 3, 3 / 4, 4 / 5, 5 / 6, and 8 / 9 are specified.

[0142] Hereinafter, a code length N of 64,800 bits will also be referred to as 64 kbits, and a code length N of 16,200 bits will also be referred to as 16 kbits.

[0143] Regarding LDPC codes, the code bits corresponding to columns with larger column weights in the parity check matrix H tend to have lower error rates.

[0144] In the check matrix H defined in standards such as DVB-T.2 and shown in Figures 12 and 13, the column weight tends to be larger toward the beginning (left side). Therefore, for the LDPC code corresponding to the check matrix H, the code bits at the beginning tend to be more resistant to errors (more resistant to errors), and the code bits at the end tend to be more vulnerable to errors.

[0145] <Parity interleave>

[0146] 14 to 16, the parity interleaving by the parity interleaver 23 of FIG. 9 will be described.

[0147] FIG. 14 is a diagram showing an example (part of) a Tanner graph of a parity check matrix of an LDPC code.

[0148] As shown in Fig. 14, when two or more of the variable nodes (corresponding code bits) connected to the check node simultaneously become erroneous such as erasure, the check node returns a message to all variable nodes connected to the check node, with equal probability that the value is 0 and that the value is 1. For this reason, when multiple variable nodes connected to the same check node simultaneously become erroneous such as erasure, the decoding performance deteriorates.

[0149] Incidentally, the LDPC code output by the LDPC encoder 115 in FIG. 8 is an IRA code, similar to the LDPC code defined in standards such as DVB-T.2, and the parity matrix H T As shown in Figure 11, it has a staircase structure.

[0150] Figure 15 shows the parity matrix H T and its parity matrix H T FIG. 1 is a diagram showing an example of a Tanner graph corresponding to

[0151] A in Fig. 15 shows the step structure of the parity matrix H TFIG. 15B shows an example of the parity matrix H T The Tanner graph corresponding to

[0152] The parity matrix H has a step structure. T In the parity matrix H, elements with a value of 1 are adjacent (except for the first row). T In the Tanner graph of, the parity matrix H T Two adjacent variable nodes corresponding to a column of two adjacent elements with a value of 1 are connected to the same check node.

[0153] Therefore, when parity bits corresponding to the above-mentioned two adjacent variable nodes become erroneous at the same time due to a burst error, erasure, or the like, the check nodes connected to the two variable nodes (variable nodes that use the parity bits to find a message) corresponding to the two erroneous parity bits return messages with equal probability of being 0 and 1 to the variable nodes connected to those check nodes, degrading the decoding performance.And, when the burst length (the number of consecutive erroneous parity bits) becomes large, the number of check nodes that return messages with equal probability increases, further degrading the decoding performance.

[0154] Therefore, in order to prevent the above-mentioned degradation of decoding performance, the parity interleaver 23 (FIG. 9) performs parity interleaving to interleave the parity bits of the LDPC code from the LDPC encoder 115 at the positions of other parity bits.

[0155] FIG. 16 shows a parity matrix H of a check matrix H corresponding to an LDPC code after parity interleaving performed by the parity interleaver 23 in FIG. T FIG.

[0156] Here, the information matrix H of the check matrix H corresponding to the LDPC code output by the LDPC encoder 115 is Ahas a cyclic structure, similar to the information matrix of the check matrix H corresponding to the LDPC code defined in standards such as DVB-T.2.

[0157] A cyclic structure refers to a structure in which a column is equal to a cyclic shift of another column, and includes, for example, a structure in which the position of 1 in each row of each of P columns is cyclically shifted in the column direction by a predetermined value, such as a value proportional to the value q obtained by dividing the first column of the P columns by the parity length M. Hereinafter, the P columns in the cyclic structure will be referred to as a parallel factor as appropriate.

[0158] As described with reference to Figs. 12 and 13, there are two types of LDPC codes defined in standards such as DVB-T.2, with code lengths N of 64,800 bits and 16,200 bits, and for both of these two types of LDPC codes, the parallel factor P is defined as 360, which is one of the divisors of the parity length M excluding 1 and M.

[0159] Furthermore, the parity length M is a value other than a prime number expressed by the formula M=q×P=q×360, with the value q varying depending on the encoding rate. Therefore, like the parallel factor P, the value q is one of the divisors of the parity length M other than 1 and M, and is obtained by dividing the parity length M by the parallel factor P (the product of P and q, which are divisors of the parity length M, is the parity length M).

[0160] As described above, the parity interleaver 23 interleaves the K+qx+y+1-th code bit of the code bits of the N-bit LDPC code into the K+Py+x+1-th code bit position, where K is the information length, x is an integer greater than or equal to 0 and less than P, and y is an integer greater than or equal to 0 and less than q, as parity interleaving.

[0161] The K+qx+y+1th code bit and the K+Py+x+1th code bit are both parity bits since they are code bits after the K+1th bit. Therefore, according to parity interleaving, the position of the parity bit of the LDPC code is moved.

[0162] With such parity interleaving, variable nodes (corresponding parity bits) connected to the same check node are separated by the parallel factor P, i.e., 360 bits in this case. Therefore, if the burst length is less than 360 bits, it is possible to avoid a situation in which multiple variable nodes connected to the same check node experience an error at the same time, thereby improving resistance to burst errors.

[0163] In addition, the LDPC code after parity interleaving in which the K+qx+y+1th code bit is interleaved at the K+Py+x+1th code bit position matches the LDPC code of a check matrix (hereinafter also referred to as a transformed check matrix) obtained by performing column permutation in which the K+qx+y+1th column of the original check matrix H is replaced with the K+Py+x+1th column.

[0164] Furthermore, in the parity matrix of the converted check matrix, as shown in FIG. 16, a quasi-cyclic structure appears with P columns (360 columns in FIG. 16) as a unit.

[0165] Here, the pseudo-cyclic structure means a structure in which all but a few parts are cyclic structures.

[0166] The transformed check matrix obtained by performing column permutation equivalent to parity interleaving on the check matrix of the LDPC code defined in standards such as DVB-T.2 has a 360 row by 360 column portion in the upper right corner of the transformed check matrix (the shift matrix described below) that is missing one element of 1 (it becomes an element of 0). In that respect, it is not a (completely) cyclic structure, but rather a quasi-cyclic structure.

[0167] The conversion check matrix for the check matrix of the LDPC code output by the LDPC encoder 115 has a quasi-cyclic structure, similar to the conversion check matrix for the check matrix of the LDPC code defined in standards such as DVB-T.2.

[0168] In addition, the transformed check matrix in Figure 16 is a matrix in which, in addition to column permutation equivalent to parity interleaving, row permutation (row permutation) has also been performed on the original check matrix H so that the transformed check matrix is ​​composed of the constituent matrices described below.

[0169] FIG. 17 is a flowchart illustrating the processing performed by the LDPC encoder 115, the bit interleaver 116, and the mapper 117 in FIG.

[0170] The LDPC encoder 115 waits for the LDPC target data to be supplied from the BCH encoder 114, and in step S101, encodes the LDPC target data into an LDPC code based on the parity check matrix, supplies the LDPC code to the bit interleaver 116, and the process proceeds to step S102.

[0171] In step S102, the bit interleaver 116 performs bit interleaving on the LDPC code from the LDPC encoder 115, and supplies the symbols obtained by the bit interleaving to the mapper 117, and the process proceeds to step S103.

[0172] That is, in step S102, in the bit interleaver 116 (FIG. 9), the parity interleaver 23 performs parity interleaving on the LDPC code from the LDPC encoder 115, and supplies the LDPC code after the parity interleaving to the group-wise interleaver 24.

[0173] The group-wise interleaver 24 performs group-wise interleaving on the LDPC code from the parity interleaver 23 , and supplies the result to a block interleaver 25 .

[0174] The block interleaver 25 performs block interleaving on the LDPC code after group-wise interleaving by the group-wise interleaver 24 , and supplies the m-bit symbol obtained as a result to the mapper 117 .

[0175] In step S103, the mapper 117 converts the symbols from the block interleaver 25 into binary symbols determined by the modulation method of the quadrature modulation performed by the mapper 117. m signal points and orthogonally modulated, and the resulting data is supplied to a time interleaver 118.

[0176] As described above, by performing parity interleaving or group-wise interleaving, it is possible to improve the error rate when a plurality of code bits of an LDPC code are transmitted as one symbol.

[0177] Here, in FIG. 9, for ease of explanation, parity interleaver 23, which is a block that performs parity interleaving, and groupwise interleaver 24, which is a block that performs groupwise interleaving, are configured separately, but parity interleaver 23 and groupwise interleaver 24 can be configured as an integrated unit.

[0178] In other words, both parity interleaving and group-wise interleaving can be performed by writing and reading code bits to memory, and can be represented by a matrix that converts the address at which the code bits are written (write address) into the address at which the code bits are read (read address).

[0179] Therefore, if a matrix obtained by multiplying a matrix representing a parity interleaving and a matrix representing a group-wise interleaving is obtained, by those matrices, by converting the code bits, parity interleaving can be performed, and further, a result of group-wise interleaving the LDPC code after the parity interleaving can be obtained.

[0180] In addition to the parity interleaver 23 and the group-wise interleaver 24, the block interleaver 25 can also be integrally configured.

[0181] That is, the block interleaving performed by the block interleaver 25 can also be represented by a matrix that converts the write address of the memory storing the LDPC code into the read address.

[0182] Therefore, if a matrix obtained by multiplying a matrix representing a parity interleaving, a matrix representing a group-wise interleaving, and a matrix representing a block interleaving is obtained, by those matrices, parity interleaving, group-wise interleaving, and block interleaving can be performed collectively.

[0183] Note that one or both of the parity interleaving and the group-wise interleaving can be not performed.

[0184] <Configuration example of LDPC encoder 115>

[0185] FIG. 18 is a block diagram showing a configuration example of the LDPC encoder 115 of FIG. 8.

[0186] Note that the LDPC encoder 122 of FIG. 8 is also configured in the same manner.

[0187] As described with reference to FIGS. 12 and 13, in standards such as DVB-T.2, LDPC codes with two code lengths N of 64800 bits and 16200 bits are defined.

[0188] For an LDPC code with a code length N of 64,800 bits, eleven coding rates are specified: 1 / 4, 1 / 3, 2 / 5, 1 / 2, 3 / 5, 2 / 3, 3 / 4, 4 / 5, 5 / 6, 8 / 9, and 9 / 10. For an LDPC code with a code length N of 16,200 bits, ten coding rates are specified: 1 / 4, 1 / 3, 2 / 5, 1 / 2, 3 / 5, 2 / 3, 3 / 4, 4 / 5, 5 / 6, and 8 / 9 (Figures 12 and 13).

[0189] The LDPC encoder 115 can perform, for example, such encoding (error correction encoding) using an LDPC code with each coding rate having a code length N of 64,800 bits or 16,200 bits, based on a check matrix H prepared for each code length N and each coding rate.

[0190] In addition, the LDPC encoder 115 can perform LDPC encoding based on a parity check matrix H of an LDPC code having a code length N of 17280 bits or any other arbitrary code length N and a coding rate r of 2 / 16, 3 / 16, 4 / 16, 5 / 16, 6 / 16, 7 / 16, 8 / 16, 9 / 16, 10 / 16, 11 / 16, 12 / 16, 13 / 16, 14 / 16 or any other arbitrary coding rate r.

[0191] The LDPC encoder 115 includes an encoding processing unit 601 and a storage unit 602 .

[0192] The encoding processing unit 601 is composed of a coding rate setting unit 611, an initial value table reading unit 612, a check matrix generation unit 613, an information bit reading unit 614, an encoding parity calculation unit 615, and a control unit 616, and performs LDPC encoding of the LDPC target data supplied to the LDPC encoder 115, and supplies the resulting LDPC code to the bit interleaver 116 (FIG. 8).

[0193] That is, the coding rate setting unit 611 sets the code length N and coding rate r of the LDPC code, and other specific information for specifying the LDPC code, in response to, for example, an operation by an operator.

[0194] The initial value table reading unit 612 reads from the storage unit 602 a check matrix initial value table, which will be described later, indicating a check matrix of an LDPC code specified by the specification information set by the coding rate setting unit 611 .

[0195] The check matrix generating unit 613 generates a check matrix H based on the check matrix initial value table read by the initial value table reading unit 612, and stores the check matrix H in the storage unit 602. For example, the check matrix generating unit 613 generates an information matrix H corresponding to an information length K (=code length N-parity length M) according to the code length N and coding rate r set by the coding rate setting unit 611. A The check matrix H is generated by arranging elements of 1 in the column direction at a period of 360 columns (parallel factor P), and is stored in the storage unit 602.

[0196] The information bit reading unit 614 reads (extracts) information bits of an information length K from the LDPC target data supplied to the LDPC encoder 115.

[0197] The encoded parity calculation unit 615 reads out the check matrix H generated by the check matrix generation unit 613 from the memory unit 602, and uses the check matrix H to calculate parity bits for the information bits read out by the information bit reading unit 614 based on a predetermined formula, thereby generating a codeword (LDPC code).

[0198] The control unit 616 controls each block constituting the encoding processing unit 601 .

[0199] In the storage unit 602, for example, a plurality of check matrix initial value tables corresponding to a plurality of coding rates shown in Fig. 12 and Fig. 13 for each code length N of 64800 bits, 16200 bits, etc., a check matrix initial value table corresponding to each coding rate of 2 / 16, 3 / 16, 4 / 16, 5 / 16, 6 / 16, 7 / 16, 8 / 16, 9 / 16, 10 / 16, 11 / 16, 12 / 16, 13 / 16, 14 / 16 for code length N of 17280 bits, and other check matrix initial value tables of check matrix H of LDPC code of arbitrary code length N and arbitrary coding rate r are stored.In addition, the storage unit 602 temporarily stores data required for the processing of the encoding processing unit 601.

[0200] FIG. 19 is a flowchart illustrating an example of the processing of the LDPC encoder 115 in FIG.

[0201] In step S201, the coding rate setting unit 611 sets the code length N and coding rate r for performing LDPC coding, and other specific information for specifying the LDPC code.

[0202] In step S202, the initial value table reading unit 612 reads from the storage unit 602 a predetermined check matrix initial value table specified by the code length N, the coding rate r, and the like, which are specified information set by the coding rate setting unit 611.

[0203] In step S203, the check matrix generation unit 613 uses the check matrix initial value table read out from the memory unit 602 by the initial value table reading unit 612 to determine (generate) a check matrix H of the LDPC code having the code length N and coding rate r set by the coding rate setting unit 611, and supplies the check matrix H to the memory unit 602 for storage.

[0204] In step S204, the information bit reading unit 614 reads out information bits of an information length K (=N×r) corresponding to the code length N and coding rate r set by the coding rate setting unit 611 from the LDPC target data supplied to the LDPC encoder 115, and also reads out the check matrix H calculated by the check matrix generation unit 613 from the storage unit 602 and supplies it to the encoding parity calculation unit 615.

[0205] In step S205, the encoded parity calculation unit 615 uses the information bits from the information bit reading unit 614 and the check matrix H to sequentially calculate parity bits of the codeword c that satisfies equation (8).

[0206] Hc T =0 (8)

[0207] In equation (8), c represents a row vector as a codeword (LDPC code), and T represents the transpose of the row vector c.

[0208] Here, as described above, in the row vector c as an LDPC code (one code word), when the information bit portion is represented by row vector A and the parity bit portion is represented by row vector T, the row vector c can be expressed by the equation c = [A|T] with row vector A as the information bit and row vector T as the parity bit.

[0209] The check matrix H and the row vector c=[A|T] as the LDPC code are expressed by the formula Hc T = 0, and the formula Hc T = 0, the row vector T as the parity bit that constitutes the row vector c = [A|T] is the check matrix H = [H A |H T ]'s parity matrix H T When the step structure shown in FIG. 11 is used, the formula Hc T = 0 column vector Hc TThis can be calculated sequentially by setting the elements of each row to 0, starting from the first row.

[0210] The encoded parity calculation unit 615 calculates a parity bit T for the information bit A from the information bit reading unit 614, and outputs a codeword c = [A|T] represented by the information bit A and the parity bit T as the LDPC encoding result of the information bit A.

[0211] After that, in step S206, the control unit 616 judges whether or not to end the LDPC encoding. In step S206, if it is judged that the LDPC encoding is not to end, that is, for example, if there is still LDPC target data to be LDPC encoded, the process returns to step S201 (or step S204), and the processes of steps S201 (or step S204) to S206 are repeated.

[0212] Also, in step S206, if it is determined that the LDPC encoding is to be ended, that is, for example, if there is no LDPC target data to be LDPC encoded, LDPC encoder 115 ends the process.

[0213] For the LDPC encoder 115, a check matrix initial value table (representing a check matrix) of LDPC codes having various code lengths N and coding rates r can be prepared in advance. The LDPC encoder 115 can perform LDPC encoding into LDPC codes having various code lengths N and coding rates r by using a check matrix H generated from the check matrix initial value table prepared in advance.

[0214] <Example of check matrix initial value table>

[0215] The check matrix initial value table is, for example, an information matrix H corresponding to an information length K according to the code length N and the coding rate r of the LDPC code (LDPC code defined by the check matrix H) of the check matrix H. AThis is a table that indicates the position of elements of 1 in (FIG. 10) for each of 360 columns (parallel factor P), and is created in advance for each parity check matrix H of each code length N and each coding rate r.

[0216] That is, the check matrix initial value table includes at least the information matrix H A Represents the position of elements with a value of 1 for every 360 columns (parallel factor P).

[0217] In addition, the check matrix H contains a parity matrix H T All of the check matrices have a step structure, and the parity matrix H T There is a parity check matrix in which a part of it has a staircase structure and the remaining part is a diagonal matrix (unit matrix).

[0218] Below, the parity matrix H T The representation method of the parity check matrix initial value table, which represents a parity check matrix in which a part of the matrix is ​​a staircase structure and the remaining part is a diagonal matrix, is also called the Type A method. T The representation method of the check matrix initial value table representing the check matrix in which all of the check matrices have a staircase structure is also called the Type B method.

[0219] An LDPC code for a check matrix represented by a check matrix initial value table of the Type A method is also called a Type A code, and an LDPC code for a check matrix represented by a check matrix initial value table of the Type B method is also called a Type B code.

[0220] The designations "Type A" and "Type B" are based on the ATSC 3.0 standard. For example, ATSC 3.0 uses both Type A and Type B codes.

[0221] In addition, type B coding is adopted in DVB-T.2 and the like.

[0222] FIG. 20 is a diagram showing an example of a parity check matrix initial value table of the Type B method.

[0223] That is, FIG. 20 shows a check matrix initial value table (representing check matrix H) for a type B code having a code length N of 16,200 bits and a coding rate (the notational coding rate in DVB-T.2) r of 1 / 4, as specified in the DVB-T.2 standard.

[0224] The check matrix generating unit 613 (FIG. 18) uses the check matrix initial value table of the Type B method to obtain the check matrix H as follows.

[0225] FIG. 21 is a diagram for explaining a method of obtaining a check matrix H from a check matrix initial value table of the Type B method.

[0226] That is, FIG. 21 shows a check matrix initial value table for a type B code having a code length N of 16200 bits and a coding rate r of 2 / 3, which is defined in the DVB-T.2 standard.

[0227] The check matrix initial value table of the Type B method is an information matrix H corresponding to an information length K according to the code length N and the coding rate r of the LDPC code. A H, the row number of the element that is 1 in the 1+360×(i-1)th column of the check matrix H (the row number of the 1st row of the check matrix H is 0) is listed as the number of column weights of the 1+360×(i-1)th column.

[0228] Here, the parity matrix H corresponding to the parity length M of the check matrix H of the Type B method is T Since (FIG. 10) is determined to have a staircase structure as shown in FIG. 15, the information matrix H corresponding to the information length K is determined by the check matrix initial value table. A If (FIG. 10) can be obtained, the check matrix H can be obtained.

[0229] The number of rows k+1 of the check matrix initial value table of the Type B method varies depending on the information length K.

[0230] The relationship of equation (9) holds between the information length K and the number of rows (k+1) of the parity check matrix initial value table.

[0231] K = (k + 1) × 360 (9)

[0232] Here, 360 in equation (9) is the parallel factor P described with reference to FIG.

[0233] In the parity check matrix initial value table in FIG. 21, 13 numerical values ​​are arranged in the first to third rows, and 3 numerical values ​​are arranged in the fourth to k+1 rows (the 30th row in FIG. 21).

[0234] Therefore, the column weight of the parity check matrix H obtained from the parity check matrix initial value table in FIG. 21 is 13 from the 1st column to the 1+360×(3−1)−1th column, and is 3 from the 1+360×(3−1)th column to the Kth column.

[0235] The first row of the parity check matrix initial value table in Figure 21 is 0, 2084, 1613, 1548, 1286, 1460, 3196, 4297, 2481, 3369, 3451, 4620, 2622, which indicates that in the first column of parity check matrix H, the elements of the rows with row numbers 0, 2084, 1613, 1548, 1286, 1460, 3196, 4297, 2481, 3369, 3451, 4620, 2622 are 1 (and the other elements are 0).

[0236] In addition, the second row of the parity check matrix initial value table in Figure 21 is 1,122,1516,3448,2880,1407,1847,3799,3529,373,971,4358,3108, which indicates that in the 361st (=1+360×(2-1))th column of parity check matrix H, the elements of the rows with row numbers 1,122,1516,3448,2880,1407,1847,3799,3529,373,971,4358,3108 are 1.

[0237] As described above, the check matrix initial value table is the information matrix H A Represents the position of elements with a value of 1 in every 360 columns.

[0238] Columns other than the 1+360×(i-1)th column of the check matrix H, i.e., each column from the 2+360×(i-1)th column to the 360×ith column, are arranged by periodically cyclically shifting an element of 1 in the 1+360×(i-1)th column, as determined by the check matrix initial value table, downward (downward in the column) according to the parity length M.

[0239] That is, for example, the 2+360×(i-1)th column is the 1+360×(i-1)th column cyclically shifted downward by M / 360(=q), and the next 3+360×(i-1)th column is the 1+360×(i-1)th column cyclically shifted downward by 2×M / 360(=2×q) (the 2+360×(i-1)th column cyclically shifted downward by M / 360(=q)).

[0240] Now, let the value in the i-th row (i-th from the top) and j-th column (j-th from the left) of the check matrix initial value table be h i,j The row number of the j-th element of 1 in the w-th column of the check matrix H is expressed as H w-j Then, the row number H of the element of 1 in the w-th column, which is a column other than the 1+360×(i-1)-th column of the check matrix H, is w-j can be calculated using equation (10).

[0241] H w-j =mod(h i,j +mod((w-1),P)×q,M) (10)

[0242] Here, mod(x,y) means the remainder when x is divided by y.

[0243] Moreover, P is the above-mentioned parallel factor, which in this embodiment is 360, similar to the standards such as DVB-T.2 and ATSC3.0. Furthermore, q is a value M / 360 obtained by dividing the parity length M by the parallel factor P (=360).

[0244] The check matrix generating unit 613 (FIG. 18) identifies the row number of the element equal to 1 in the 1+360×(i−1)th column of the check matrix H, using the check matrix initial value table.

[0245] Furthermore, the check matrix generation unit 613 (FIG. 18) calculates the row number H of the element 1 in the w-th column, which is a column other than the 1+360×(i−1)-th column of the check matrix H. w-j is calculated according to equation (10), and a check matrix H is generated in which the elements of the row numbers obtained above are set to 1.

[0246] FIG. 22 is a diagram showing the structure of parity check matrix H of the Type A method.

[0247] The check matrix of the Type A method is made up of an A matrix, a B matrix, a C matrix, a D matrix, and a Z matrix.

[0248] Matrix A is an upper left matrix of parity check matrix H, with M1 rows and K columns, expressed by a predetermined value M1 and information length K of the LDPC code=code length N×coding rate r.

[0249] The B matrix is ​​a step structure matrix adjacent to the right of the A matrix, with M1 rows and M1 columns.

[0250] The C matrix is ​​a matrix adjacent below the A matrix and the B matrix, with N-K-M1 rows and K+M1 columns.

[0251] The D matrix is ​​an identity matrix adjacent to the right of the C matrix, with N-K-M1 rows and N-K-M1 columns.

[0252] The Z matrix is ​​a zero matrix (0 matrix) adjacent to the right of the B matrix, with M1 rows and NK-M1 columns.

[0253] In the type A check matrix H composed of the above-mentioned A matrices through D matrices and Z matrix, the A matrix and a part of the C matrix constitute an information matrix, and the remaining parts of the B matrix, the C matrix, the D matrix, and the Z matrix constitute a parity matrix.

[0254] Since matrix B is a matrix with a staircase structure and matrix D is a unit matrix, a part of the parity matrix of check matrix H of the Type A method (the part of matrix B) has a staircase structure and the remaining part (the part of matrix D) is a diagonal matrix (unit matrix).

[0255] Like the information matrix of the parity check matrix H of the Type B method, the A matrix and the C matrix have a cyclic structure for each column of the parallel factor P (e.g., 360 columns), and the parity check matrix initial value table of the Type A method represents the positions of elements of 1 in the A matrix and the C matrix for every 360 columns.

[0256] Here, as described above, the A matrix and a part of the C matrix constitute an information matrix, so it can be said that the Type A method check matrix initial value table, which represents the positions of elements of 1 in the A matrix and the C matrix every 360 columns, at least represents the positions of elements of 1 in the information matrix every 360 columns.

[0257] In addition, since the Type A method parity check matrix initial value table represents the positions of elements of 1 in the A matrix and C matrix every 360 columns, it can also be said that it represents the positions of elements of 1 in a part of the parity check matrix (the remaining part of the C matrix) every 360 columns.

[0258] FIG. 23 is a diagram showing an example of a parity check matrix initial value table of the Type A method.

[0259] That is, FIG. 23 shows an example of a parity check matrix initial value table representing a parity check matrix H with a code length N of 35 bits and a coding rate r of 2 / 7.

[0260] The Type A method check matrix initial value table is a table that represents the positions of elements of 1 in the A matrix and the C matrix for each parallel factor P, and in its i-th row, the row numbers of elements of 1 in the 1+P×(i-1)th column of check matrix H (row numbers assuming that the row number of the 1st row of check matrix H is 0) are listed in the same order as the column weight of the 1+P×(i-1)th column.

[0261] For ease of explanation, it is assumed here that the parallel factor P is 5, for example.

[0262] The check matrix H of the Type A system has parameters M1, M2, Q1, and Q2.

[0263] M1 (FIG. 22) is a parameter that determines the size of the B matrix, and takes a value that is a multiple of the parallel factor P. By adjusting M1, the performance of the LDPC code changes, and it is adjusted to a predetermined value when determining the check matrix H. Here, it is assumed that 15, which is three times the parallel factor P=5, is adopted as M1.

[0264] M2 (FIG. 22) is the value M-M1 obtained by subtracting M1 from the parity length M.

[0265] Here, the information length K is N×r=35×2 / 7=10, and the parity length M is NK=35-10=25, so M2 is M-M1=25-15=10.

[0266] Q1 is calculated according to the equation Q1=M1 / P, and represents the number of cyclic shifts (number of rows) in the A matrix.

[0267] In other words, the columns other than the 1+P×(i-1)th column of the A matrix of the check matrix H of the Type A method, i.e., each column from the 2+P×(i-1)th column to the P×ith column, are arranged by periodically cyclically shifting an element of 1 in the 1+P×(i-1)th column determined by the check matrix initial value table downward (downward in the column), and Q1 represents the number of cyclic shifts in the A matrix.

[0268] Q2 is calculated according to the equation Q2=M2 / P, and represents the number of cyclic shifts (number of rows) in the C matrix.

[0269] In other words, columns other than the 1+P×(i-1)th column of the C matrix of the check matrix H of the Type A method, i.e., each column from the 2+P×(i-1)th column to the P×ith column, are arranged by periodically cyclically shifting elements of 1 in the 1+P×(i-1)th column determined by the check matrix initial value table downward (downward in the column), and Q2 represents the number of cyclic shifts in the C matrix.

[0270] Here, Q1 is M1 / P=15 / 5=3, and Q2 is M2 / P=10 / 5=2.

[0271] In the parity check matrix initial value table of FIG. 23, three numerical values ​​are listed in the first and second rows, and one numerical value is listed in the third to fifth rows. According to this arrangement of numerical values, the column weights of the A matrix and C matrix portions of the parity check matrix H obtained from the parity check matrix initial value table of FIG. 23 are 3 from the 1=1+5×(1-1)th column to the 10=5×2nd column, and 1 from the 11=1+5×(3-1)th column to the 25=5×5th column.

[0272] That is, the first row of the parity check matrix initial value table in FIG. 23 is 2, 6, 18, which indicates that in the first column of the parity check matrix H, the elements in the rows with row numbers 2, 6, 18 are 1 (and the other elements are 0).

[0273] In this case, the A matrix (Figure 22) is a matrix with 15 rows and 10 columns (M1 rows and K columns), and the C matrix (Figure 22) is a matrix with 10 rows and 25 columns (NK-M1 rows and K+M1 columns), so the rows with row numbers 0 to 14 of the check matrix H are rows of the A matrix, and the rows with row numbers 15 to 24 of the check matrix H are rows of the C matrix.

[0274] Therefore, of the rows with row numbers 2, 6, and 18 (hereinafter referred to as rows #2, #6, #18, etc.), rows #2 and #6 are rows of the A matrix, and row #18 is a row of the C matrix.

[0275] The second row of the parity check matrix initial value table in FIG. 23 is 2, 10, 19, which indicates that the elements of rows #2, #10, and #19 in the 6th (=1+5×(2−1)) column of parity check matrix H are 1.

[0276] Here, in the 6th (=1+5×(2−1)) column of parity check matrix H, of rows #2, #10, and #19, rows #2 and #10 are rows of the A matrix, and row #19 is a row of the C matrix.

[0277] The third row of the parity check matrix initial value table in FIG. 23 is 22, which indicates that the element of row #22 in the 11th (=1+5×(3−1)) column of parity check matrix H is 1.

[0278] Here, in the 11th (=1+5×(3−1)) column of parity check matrix H, row #22 is a row of the C matrix.

[0279] Similarly, the 19 in the 4th row of the parity check matrix initial value table of FIG. 23 indicates that the element of row #19 in the 16th (=1+5×(4-1)) column of parity check matrix H is 1, and the 15 in the 5th row of the parity check matrix initial value table of FIG. 23 indicates that the element of row #15 in the 21st (=1+5×(5-1)) column of parity check matrix H is 1.

[0280] As described above, the parity check matrix initial value table indicates the positions of elements of 1 in the A matrix and C matrix of the parity check matrix H for each parallel factor P=5 columns.

[0281] Columns other than the 1+5×(i-1)th column of the A matrix and C matrix of the check matrix H, i.e., each column from the 2+5×(i-1)th column to the 5×ith column, are arranged by periodically cyclically shifting elements of 1 in the 1+5×(i-1)th column determined by the check matrix initial value table downward (downward in the column direction) according to parameters Q1 and Q2.

[0282] That is, for example, the 2+5×(i-1)th column of matrix A is the 1+5×(i-1)th column cyclically shifted downward by Q1 (=3), and the next 3+5×(i-1)th column is the 1+5×(i-1)th column cyclically shifted downward by 2×Q1 (=2×3) (the 2+5×(i-1)th column cyclically shifted downward by Q1).

[0283] For example, the 2+5×(i-1)th column of matrix C is the 1+5×(i-1)th column cyclically shifted downward by Q2 (=2), and the next 3+5×(i-1)th column is the 1+5×(i-1)th column cyclically shifted downward by 2×Q2 (=2×2) (the 2+5×(i-1)th column cyclically shifted downward by Q2).

[0284] FIG. 24 is a diagram showing matrix A generated from the check matrix initial value table of FIG.

[0285] In matrix A in FIG. 24, elements of rows #2 and #6 in the 1st (=1+5×(1−1)) column are 1, in accordance with the first row of the parity check matrix initial value table in FIG.

[0286] Each of the columns from the 2nd (=2+5×(1-1)) to the 5th (=5+5×(1-1)) is a cyclic shift of the previous column downward by Q1=3.

[0287] Furthermore, in matrix A in FIG. 24, elements in rows #2 and #10 of the 6th (=1+5×(2−1)) column are 1, in accordance with the second row of the parity check matrix initial value table in FIG.

[0288] Each column from the 7th (=2+5×(2-1)) column to the 10th (=5+5×(2-1)) column is a cyclic shift of the previous column downward by Q1=3.

[0289] FIG. 25 is a diagram showing parity interleaving of a B matrix.

[0290] The check matrix generating unit 613 (FIG. 18) uses a check matrix initial value table to generate an A matrix, and places a B matrix of a staircase structure to the right of the A matrix. Then, the check matrix generating unit 613 regards the B matrix as a parity matrix, and performs parity interleaving so that adjacent elements of 1 in the B matrix of the staircase structure are separated by a parallel factor P=5 in the row direction.

[0291] FIG. 25 shows the A and B matrices after parity interleaving of the B matrix of FIG.

[0292] FIG. 26 is a diagram showing a C matrix generated from the parity check matrix initial value table of FIG.

[0293] 26, the element in row #18 of the 1st (=1+5×(1−1))th column of parity check matrix H is 1, in accordance with the first row of the parity check matrix initial value table in FIG.

[0294] Each column from the 2nd (=2+5×(1-1)) to the 5th (=5+5×(1-1)) columns of matrix C is a cyclic shift of the previous column downward by Q2=2.

[0295] Furthermore, in matrix C of FIG. 26, in accordance with the second to fifth rows of the parity check matrix initial value table of FIG. 23, the elements of row #19, the 6th (=1+5×(2-1)) column, row #22, the 11th (=1+5×(3-1)) column, row #19, the 16th (=1+5×(4-1)) column, and row #15, the 21st (=1+5×(5-1)) column of parity check matrix H are 1.

[0296] Furthermore, each of the columns from the 7th (=2+5×(2-1)) to the 10th (=5+5×(2-1)), each of the columns from the 12th (=2+5×(3-1)) to the 15th (=5+5×(3-1)), each of the columns from the 17th (=2+5×(4-1)) to the 20th (=5+5×(4-1)), and each of the columns from the 22nd (=2+5×(5-1)) to the 25th (=5+5×(5-1)) are cyclically shifted downward by Q2=2 from the previous column.

[0297] The check matrix generation unit 613 (FIG. 18) generates matrix C using the check matrix initial value table, and places matrix C below matrix A and matrix B (after parity interleaving).

[0298] Furthermore, parity check matrix generation section 613 places matrix Z to the right of matrix B, and matrix D to the right of matrix C, thereby generating parity check matrix H shown in FIG.

[0299] FIG. 27 is a diagram showing parity interleaving of a D matrix.

[0300] After generating the parity check matrix H of FIG. 26, the parity check matrix generation unit 613 regards the D matrix as a parity matrix and performs parity interleaving (of only the D matrix) so that elements of 1 in odd rows and the next even rows of the unit matrix D matrix are separated in the row direction by a parallel factor P=5.

[0301] FIG. 27 shows the parity check matrix H after performing parity interleaving of the D matrix on the parity check matrix H in FIG.

[0302] The LDPC encoder 115 (the encoding parity calculation unit 615 (FIG. 18)) performs LDPC encoding (generation of an LDPC code) using, for example, the check matrix H in FIG.

[0303] Here, the LDPC code generated using the parity check matrix H in Fig. 27 is an LDPC code that has been parity interleaved, and therefore, for the LDPC code generated using the parity check matrix H in Fig. 27, there is no need to perform parity interleaving in the parity interleaver 23 (Fig. 9). In other words, since the LDPC code generated using the parity check matrix H after parity interleaving of the D matrix is ​​an LDPC code that has been parity interleaved, the parity interleaving in the parity interleaver 23 is skipped for such an LDPC code.

[0304] FIG. 28 is a diagram showing a parity check matrix H in which column permutation is performed on the B matrix, part of the C matrix (the part of the C matrix that is placed under the B matrix), and the D matrix of the parity check matrix H in FIG. 27 as parity deinterleaving that restores the parity interleaving.

[0305] The LDPC encoder 115 can perform LDPC encoding (generation of an LDPC code) using the parity check matrix H in FIG.

[0306] When LDPC coding is performed using the check matrix H in Fig. 28, an LDPC code that is not parity interleaved is obtained by the LDPC coding. Therefore, when LDPC coding is performed using the check matrix H in Fig. 28, parity interleaving is performed in the parity interleaver 23 (Fig. 9).

[0307] FIG. 29 is a diagram showing a converted parity check matrix H obtained by performing row permutation on the parity check matrix H in FIG.

[0308] As will be described later, the conversion check matrix is ​​a matrix expressed by a combination of a P×P unit matrix, a quasi-unit matrix in which one or more of the 1s in the unit matrix are changed to 0, a shift matrix obtained by cyclically shifting a unit matrix or a quasi-unit matrix, a sum matrix which is the sum of two or more of a unit matrix, a quasi-unit matrix, or a shift matrix, and a P×P 0 matrix.

[0309] By using the converted parity check matrix for decoding an LDPC code, it is possible to employ an architecture for simultaneously performing P check node operations and variable node operations in decoding the LDPC code, as will be described later.

[0310] <New LDPC code>

[0311] In data transmission using LDPC codes, one method for ensuring good communication quality is to use LDPC codes with good performance.

[0312] A new LDPC code with good performance (hereinafter, also referred to as a new LDPC code) will be described below.

[0313] As the new LDPC code, for example, a type A code or type B code can be adopted in which the parallel factor P is 360, which is the same as that of DVB-T.2, ATSC3.0, etc., and which corresponds to a check matrix H having a cyclic structure.

[0314] The LDPC encoder 115 (FIGS. 8 and 18) can perform LDPC encoding into an LDPC code using a check matrix initial value table (a check matrix H obtained from) of an LDPC code having a code length N longer than 64 k bits, for example, 69120 bits, and a coding rate r of, for example, 2 / 16, 3 / 16, 4 / 16, 5 / 16, 6 / 16, 7 / 16, 8 / 16, 9 / 16, 10 / 16, 11 / 16, 12 / 16, 13 / 16, or 14 / 16.

[0315] Furthermore, the LDPC encoder 115 can perform LDPC encoding into a new LDPC code based on a check matrix initial value table (a check matrix H obtained from) of a new LDPC code in which the code length N is shorter than 64 k bits, for example, 17280 bits (17 k bits), and the coding rate r is, for example, 2 / 16, 3 / 16, 4 / 16, 5 / 16, 6 / 16, 7 / 16, 8 / 16, 9 / 16, 10 / 16, 11 / 16, 12 / 16, 13 / 16, or 14 / 16.

[0316] When LDPC encoding is performed to obtain a new LDPC code having a code length N of 17280 bits, a check matrix initial value table for the new LDPC code is stored in the storage unit 602 of the LDPC encoder 115 (FIG. 8).

[0317] FIG. 30 is a diagram showing an example of a check matrix initial value table (for the Type A method) representing a check matrix H of a Type A code (hereinafter also referred to as a Type A code where r=2 / 16) as a new LDPC code having a code length N of 17280 bits and a coding rate r of 2 / 16.

[0318] FIG. 31 is a diagram showing an example of a parity check matrix initial value table indicating a parity check matrix H of a type A code (hereinafter also referred to as a type A code where r=3 / 16) as a new LDPC code having a code length N of 17280 bits and a coding rate r of 3 / 16.

[0319] FIG. 32 is a diagram showing an example of a parity check matrix initial value table indicating a parity check matrix H of a type A code (hereinafter also referred to as a type A code where r=4 / 16) as a new LDPC code having a code length N of 17280 bits and a coding rate r of 4 / 16.

[0320] FIG. 33 is a diagram showing an example of a parity check matrix initial value table indicating a parity check matrix H of a type A code (hereinafter also referred to as a type A code where r=5 / 16) as a new LDPC code having a code length N of 17280 bits and a coding rate r of 5 / 16.

[0321] FIG. 34 is a diagram showing an example of a parity check matrix initial value table indicating a parity check matrix H of a type A code (hereinafter also referred to as a type A code where r=6 / 16) as a new LDPC code having a code length N of 17280 bits and a coding rate r of 6 / 16.

[0322] FIG. 35 is a diagram showing an example of a parity check matrix initial value table indicating a parity check matrix H of a type A code (hereinafter also referred to as a type A code where r=7 / 16) as a new LDPC code having a code length N of 17280 bits and a coding rate r of 7 / 16.

[0323] FIG. 36 is a diagram showing an example of a parity check matrix initial value table (for the Type B method) that represents a parity check matrix H of a Type B code (hereinafter also referred to as a Type B code where r=7 / 16) as a new LDPC code having a code length N of 17280 bits and a coding rate r of 7 / 16.

[0324] FIG. 37 is a diagram showing an example of a parity check matrix initial value table that indicates a parity check matrix H of a Type B code (hereinafter also referred to as a Type B code where r=8 / 16) as a new LDPC code having a code length N of 17280 bits and a coding rate r of 8 / 16.

[0325] FIG. 38 is a diagram showing an example of a parity check matrix initial value table that indicates a parity check matrix H of a Type B code (hereinafter also referred to as a Type B code where r=9 / 16) as a new LDPC code having a code length N of 17280 bits and a coding rate r of 9 / 16.

[0326] FIG. 39 is a diagram showing an example of a parity check matrix initial value table indicating a parity check matrix H of a Type B code (hereinafter also referred to as a Type B code with r=10 / 16) as a new LDPC code having a code length N of 17280 bits and a coding rate r of 10 / 16.

[0327] FIG. 40 is a diagram showing an example of a parity check matrix initial value table that indicates a parity check matrix H of a Type B code (hereinafter also referred to as a Type B code where r=11 / 16) as a new LDPC code having a code length N of 17280 bits and a coding rate r of 11 / 16.

[0328] FIG. 41 is a diagram showing an example of a parity check matrix initial value table indicating a parity check matrix H of a Type B code (hereinafter also referred to as a Type B code with r=12 / 16) as a new LDPC code having a code length N of 17280 bits and a coding rate r of 12 / 16.

[0329] FIG. 42 is a diagram showing an example of a parity check matrix initial value table that indicates a parity check matrix H of a Type B code (hereinafter also referred to as a Type B code with r=13 / 16) as a new LDPC code having a code length N of 17280 bits and a coding rate r of 13 / 16.

[0330] FIG. 43 is a diagram showing an example of a parity check matrix initial value table indicating a parity check matrix H of a Type B code (hereinafter also referred to as a Type B code where r=14 / 16) as a new LDPC code having a code length N of 17280 bits and a coding rate r of 14 / 16.

[0331] The new LDPC code is an LDPC code with good performance.

[0332] Here, an LDPC code with good performance is an LDPC code obtained from an appropriate check matrix H.

[0333] An appropriate check matrix H is, for example, an LDPC code obtained from the check matrix H with low E s / N0 or E b / N o A check matrix satisfies certain conditions and reduces the bit error rate (BER) (and frame error rate (FER)) when transmitted at a signal power to noise power ratio (SPR) per bit.

[0334] For example, an appropriate check matrix H can be obtained by combining LDPC codes obtained from various check matrices that satisfy a certain condition with a low E s / N o This can be obtained by performing a simulation to measure the BER when transmitting at .

[0335] The predetermined conditions that an appropriate check matrix H should satisfy include, for example, that the analysis results obtained by a code performance analysis method called Density Evolution are good, that there is no loop of elements of 1, called cycle 4, and so on.

[0336] Here, the information matrix H A It is known that if elements of 1 are concentrated, such as in cycle 4, the decoding performance of the LDPC code deteriorates. For this reason, it is desirable that cycle 4 does not exist in the parity check matrix H.

[0337] In the parity check matrix H, the minimum length of a loop formed by elements of 1 is called a girth. The absence of a cycle of 4 means that the girth is greater than 4.

[0338] The predetermined conditions that an appropriate check matrix H should satisfy can be appropriately determined from the viewpoint of improving the decoding performance of the LDPC code, facilitating (simplifying) the decoding process of the LDPC code, and so on.

[0339] 44 and 45 are diagrams for explaining density evolution that obtains analysis results as predetermined conditions that an appropriate parity check matrix H should satisfy.

[0340] Density evolution is a code analysis method that calculates the expected error probability for an ensemble of LDPC codes with a code length N of ∞, characterized by a degree sequence (described later).

[0341] For example, in an AWGN channel, if the noise variance is increased from 0, the expected error probability of a certain ensemble is initially 0, but once the noise variance exceeds a certain threshold, it is no longer 0.

[0342] According to density evolution, the performance of the ensemble (the appropriateness of the check matrix) can be determined by comparing the noise variance threshold (hereinafter referred to as the performance threshold) at which the expected value of the error probability is no longer zero.

[0343] It should be noted that, for a specific LDPC code, if the ensemble to which that LDPC code belongs is determined and density evolution is performed on that ensemble, the rough performance of that LDPC code can be predicted.

[0344] Therefore, if an ensemble with good performance is found, a good LDPC code can be found from among the LDPC codes that belong to that ensemble.

[0345] Here, the above-mentioned degree sequence indicates the proportion of variable nodes and check nodes having each weight value with respect to the code length N of the LDPC code.

[0346] For example, a regular (3,6) LDPC code with a coding rate of 1 / 2 belongs to an ensemble characterized by a degree sequence in which all variable nodes have a weight (column weight) of 3 and all check nodes have a weight (row weight) of 6.

[0347] Figure 44 shows the Tanner graph of such an ensemble.

[0348] In the Tanner Bluff of Figure 44, there are N variable nodes, indicated by circles (○) in the figure, which is equal to the code length N, and there are N / 2 check nodes, indicated by squares (□) in the figure, which is equal to the code length N multiplied by the coding rate 1 / 2.

[0349] Each variable node has three edges connected to it, equal to the column weight, so there are a total of 3N edges connecting the N variable nodes.

[0350] Also, each check node has 6 edges connected to it, equal to the row weight. Therefore, there are a total of 3N edges connecting to the N / 2 check nodes.

[0351] Furthermore, in the Tanner graph of Figure 44, there is one interleaver.

[0352] The interleaver randomly rearranges the 3N branches connected to the N variable nodes, and then connects each rearranged branch to one of the 3N branches connected to the N / 2 check nodes.

[0353] There are only (3N)! (=(3N)×(3N-1)×···×1) possible permutations of the 3N branches connected to N variable nodes in the interleaver. Therefore, an ensemble characterized by a degree sequence in which all variable nodes have a weight of 3 and all check nodes have a weight of 6 is a set of (3N)! LDPC codes.

[0354] In a simulation to find a high-performance LDPC code (appropriate check matrix), a multi-edge type ensemble was used in density evolution.

[0355] In the multi-edge type, the interleaver through which the branches connected to the variable nodes and the branches connected to the check nodes pass is divided into multiple (multi-edge), which allows for more precise characterization of the ensemble.

[0356] Figure 45 shows an example of a Tanner graph for a multi-edge type ensemble.

[0357] In the Tanner graph of FIG. 45, there are two interleavers: a first interleaver and a second interleaver.

[0358] In addition, in the Tanner graph of Figure 45, there is only v1 variable node with one edge connecting to the first interleaver and zero edges connecting to the second interleaver, there is only v2 variable node with one edge connecting to the first interleaver and two edges connecting to the second interleaver, and there is only v3 variable node with zero edges connecting to the first interleaver and two edges connecting to the second interleaver.

[0359] Furthermore, in the Tanner graph of Figure 45, there are only c1 check nodes with two edges connecting to the first interleaver and zero edges connecting to the second interleaver, only c2 check nodes with two edges connecting to the first interleaver and two edges connecting to the second interleaver, and only c3 check nodes with zero edges connecting to the first interleaver and three edges connecting to the second interleaver.

[0360] Here, density evolution and its implementation are described, for example, in "On the Design of Low-Density Parity-Check Codes within 0.0045 dB of the Shannon Limit", SY Chung, GD Forney, TJ Richardson, R. Urbanke, IEEE Communications Leggers, VOL. 5, NO. 2, Feb. 2001.

[0361] In a simulation to find a new LDPC code (check matrix), the BER starts to drop (become smaller) due to the multi-edge type density evolution. b We found an ensemble where the performance threshold, i.e., / N0 (signal power to noise power ratio per bit), is below a specified value, and from among the LDPC codes belonging to that ensemble, we selected the LDPC code that reduces the BER when using one or more orthogonal modulations such as QPSK as the LDPC code with good performance.

[0362] The new LDPC code (the check matrix initial value table representing the check matrix of the new LDPC code) was obtained by the above simulation.

[0363] Therefore, the new LDPC code can ensure good communication quality in data transmission.

[0364] FIG. 46 is a diagram for explaining column weights of a check matrix H of a type-A code as a new LDPC code.

[0365] As for the check matrix H of the type-A code, as shown in FIG. 46, the column weight of the first K1 columns of the A matrix and the C matrix is ​​represented as X1, the column weight of the subsequent K2 columns of the A matrix and the C matrix is ​​represented as X2, the column weight of the further subsequent K3 columns of the A matrix and the C matrix is ​​represented as X3, and the column weight of the further subsequent M1 columns of the C matrix is ​​represented as XM1.

[0366] Note that K1+K2+K3 is equal to the information length K, and M1+M2 is equal to the parity length M. Therefore, K1+K2+K3+M1+M2 is equal to the code length N=17280 bits.

[0367] As for the check matrix H of the type A code, the column weight of the 1st column to the M1-1th column of the B matrix is ​​2, and the column weight of the M1th column (the last column) of the B matrix is ​​1. Furthermore, the column weight of the D matrix is ​​1, and the column weight of the Z matrix is ​​0.

[0368] FIG. 47 is a diagram showing parameters of the check matrix H of the type-A code (represented by the check matrix initial value tables) of FIGS.

[0369] The parameters K, X1, K1, X2, K2, X3, K3, XM1, M1, and M2 of the check matrix H of the type A code for r=2 / 16, 3 / 16, 4 / 16, 5 / 16, 6 / 16, and 7 / 16 are as shown in FIG.

[0370] The parameters X1, K1, X2, K2, X3, K3, XM1, and M1 (or M2) are set so as to further improve the performance (e.g., error rate, etc.) of the LDPC code.

[0371] FIG. 48 is a diagram for explaining column weights of a check matrix H of a type-B code as a new LDPC code.

[0372] As for the check matrix H of a Type B code, as shown in FIG. 48, the column weight of the first to last KX1 columns is represented as X1, the column weight of the subsequent KX2 column is represented as X2, the column weight of the subsequent KX3 column is represented as X3, the column weight of the subsequent KX4 column is represented as X4, and the column weight of the subsequent KY1 column is represented as Y1.

[0373] Note that KX1+KX2+KX3+KX4+KY1 is equal to the information length K, and KX1+KX2+KX3+KX4+KY1+M is equal to the code length N=17280 bits.

[0374] Furthermore, in the parity check matrix H of the type B code, of the last M columns, the column weight of M−1 columns excluding the last column is 2, and the column weight of the last column is 1.

[0375] FIG. 49 is a diagram showing parameters of the check matrix H of the type B code (represented by the check matrix initial value tables) in FIGS.

[0376] The parameters K, X1, KX1, X2, KX2, X3, KX3, X4, KX4, Y1, KY1, and M of the check matrix H of type B code for r=7 / 16, 8 / 16, 9 / 16, 10 / 16, 11 / 16, 12 / 16, 13 / 16, and 14 / 16 are as shown in FIG. 49.

[0377] The parameters X1, KX1, X2, KX2, X3, KX3, X4, KX4, Y1, and KY1 are set so as to further improve the performance of the LDPC code.

[0378] The new LDPC code achieves a good BER / FER and a capacity (channel capacity) close to the Shannon limit.

[0379] 50 to 53 are diagrams for explaining other examples of the new LDPC code.

[0380] That is, FIG. 50 is a diagram showing an example of a check matrix initial value table representing a check matrix H of a type A code (hereinafter also referred to as a new type A code with r=4 / 16) provided by the Japan Broadcasting Corporation as a new LDPC code having a code length N of 17280 bits and a coding rate r of 4 / 16.

[0381] FIG. 51 is a diagram showing parameters of a parity check matrix H of a new type A code with r=7 / 16 provided by the Japan Broadcasting Corporation.

[0382] The parameters K, X1, K1, X2, K2, X3, K3, XM1, M1, and M2 are the parameters described in Figure 46, and the parameters K, X1, K1, X2, K2, X3, K3, XM1, M1, and M2 of the check matrix H of the new type A code with r = 4 / 16 are as shown in Figure 51.

[0383] FIG. 52 is a diagram showing an example of a check matrix initial value table representing a check matrix H of a Type B code (hereinafter also referred to as a new Type B code with r=9 / 16) provided by the Japan Broadcasting Corporation as a new LDPC code having a code length N of 17280 bits and a coding rate r of 9 / 16.

[0384] FIG. 53 is a diagram showing parameters of the parity check matrix H of the new type B code with r=9 / 16 provided by the Japan Broadcasting Corporation.

[0385] The parameters K, X1, KX1, X2, KX2, X3, KX3, X4, KX4, Y1, KY1, and M are the parameters described in Figure 48, and the parameters K, X1, KX1, X2, KX2, X3, KX3, X4, KX4, Y1, KY1, and M of the check matrix H of the new type B code with r=9 / 16 are as shown in Figure 52.

[0386] <Constellation>

[0387] 54 to 78 are diagrams showing examples of constellations that can be used in the transmission system of FIG.

[0388] In the transmission system of FIG. 7, for example, for MODCOD, which is a combination of a modulation method (MODulation) and an LDPC code (CODe), a constellation to be used in that MODCOD can be set.

[0389] For a MODCOD of 1, one or more constellations can be set.

[0390] Constellations include UC (Uniform Constellation), in which the signal points are arranged uniformly, and NUC (Non Uniform Constellation), in which the signal points are not arranged uniformly.

[0391] In addition, there are many types of NUCs, such as 1D-NUC (1-dimensional (M 2 There are constellations called 2D-NUC (2-dimensional (QQAM) non-uniform constellation) and 2D-NUC (2-dimensional (QQAM) non-uniform constellation).

[0392] In general, 1D-NUC provides a better BER than UC, and 2D-NUC provides a better BER than 1D-NUC.

[0393] The constellation for the QPSK modulation method is UC. For example, UC or 2D-NUC can be used as a constellation for 16QAM, 64QAM, 256QAM, etc., and for example, UC or 1D-NUC can be used as a constellation for 1024QAM, 4096QAM, etc.

[0394] In the transmission system of FIG. 7, for example, constellations defined in ATSC3.0, DVB-C.2, and the like, as well as various other constellations that improve the error rate, can be used.

[0395] That is, when the modulation scheme is QPSK, for example, the same UC can be used for each coding rate r of the LDPC code.

[0396] In addition, when the modulation method is 16QAM, 64QAM, or 256QAM, for example, the same UC can be used for each coding rate r of the LDPC code. Furthermore, when the modulation method is 16QAM, 64QAM, or 256QAM, for example, different 2D-NUC can be used for each coding rate r of the LDPC code.

[0397] In addition, when the modulation method is 1024QAM or 4096QAM, for example, the same UC can be used for each coding rate r of the LDPC code. Furthermore, when the modulation method is 1024QAM or 4096QAM, for example, different 1D-NUC can be used for each coding rate r of the LDPC code.

[0398] Here, UC of QPSK is also written as QPSK-UC, and m QAM UC, 2 m Also written as QAM-UC. m QAM 1D-NUC and 2D-NUC are, respectively, m QAM-1D-NUC and 2 m Also written as QAM-2D-NUC.

[0399] Below, we will explain some of the constellations specified in ATSC3.0.

[0400] FIG. 54 is a diagram showing the coordinates of signal points of QPSK-UC used for all coding rates of LDPC codes defined in ATSC3.0 when the modulation scheme is QPSK.

[0401] In FIG. 54, "Input Data cell y" represents a 2-bit symbol to be mapped to QPSK-UC, and "Constellation point z s " is the signal point z s The coordinates of the signal point z s The index s of the signal point z q The index q of each symbol represents the discrete time of the symbols (the time interval between one symbol and the next).

[0402] In Figure 54, signal point z s The coordinates of are expressed in the form of complex numbers, with j representing the imaginary unit (√(-1)).

[0403] FIG. 55 is a diagram showing the coordinates of signal points of 16QAM-2D-NUC used for coding rates r(CR)=2 / 15, 3 / 15, 4 / 15, 5 / 15, 6 / 15, 7 / 15, 8 / 15, 9 / 15, 10 / 15, 11 / 15, 12 / 15, 13 / 15 of the LDPC code specified in ATSC3.0 when the modulation method is 16QAM.

[0404] In FIG. 55, like FIG. 54, signal point z s The coordinates of are expressed in the form of complex numbers, with j representing the imaginary unit.

[0405] In FIG. 55, w#k represents the coordinates of the signal point in the first quadrant of the constellation.

[0406] In 2D-NUC, the signal points in the second quadrant of the constellation are arranged at positions obtained by moving the signal points in the first quadrant symmetrically with respect to the Q axis, the signal points in the third quadrant of the constellation are arranged at positions obtained by moving the signal points in the first quadrant symmetrically with respect to the origin, and the signal points in the fourth quadrant of the constellation are arranged at positions obtained by moving the signal points in the first quadrant symmetrically with respect to the I axis.

[0407] Here, the modulation method is 2 mIn the case of QAM, m bits are treated as one symbol, and each symbol is mapped to a signal point corresponding to that symbol.

[0408] An m-bit symbol can be, for example, 0 to 2 m It can be expressed as an integer value of -1, but now, b=2 m / 4 means 0 to 2 m The symbols y(0), y(1), . . . , y(2 m -1) can be classified into four symbols: y(0) through y(b-1), y(b) through y(2b-1), y(2b) through y(3b-1), and y(3b) through y(4b-1).

[0409] In FIG. 55, the suffix k of w#k takes an integer value ranging from 0 to b-1, and w#k represents the coordinates of a signal point corresponding to symbol y(k) ranging from symbols y(0) to y(b-1).

[0410] The coordinates of the signal point corresponding to symbol y(k+b) in the range of symbols y(b) to y(2b-1) are represented by -conj(w#k), the coordinates of the signal point corresponding to symbol y(k+2b) in the range of symbols y(2b) to y(3b-1) are represented by conj(w#k), and the coordinates of the signal point corresponding to symbol y(k+3b) in the range of symbols y(3b) to y(4b-1) are represented by -w#k.

[0411] Here, conj(w#k) represents the complex conjugate of w#k.

[0412] For example, when the modulation method is 16QAM, the m=4-bit symbols y(0), y(1), . . . , y(15) are 4 / 4=4, the symbols are classified into four: y(0) through y(3), y(4) through y(7), y(8) through y(11), and y(12) through y(15).

[0413] Among the symbols y(0) to y(15), for example, the symbol y(12) is a symbol y(k+3b)=y(0+3×4) in the range of symbols y(3b) to y(4b-1), where k=0, and therefore the coordinates of the signal point corresponding to the symbol y(12) are -w#k=-w0.

[0414] Now, if the coding rate r(CR) of the LDPC code is, for example, 9 / 15, according to FIG. 55, when the modulation method is 16QAM and the coding rate r is 9 / 15, w0 is 0.2386+j0.5296, so the coordinate −w0 of the signal point corresponding to the symbol y(12) is −(0.2386+j0.5296).

[0415] FIG. 56 is a diagram showing an example of the coordinates of signal points of 1024QAM-1D-NUC used for coding rates r(CR)=2 / 15, 3 / 15, 4 / 15, 5 / 15, 6 / 15, 7 / 15, 8 / 15, 9 / 15, 10 / 15, 11 / 15, 12 / 15, 13 / 15 of the LDPC code specified in ATSC3.0 when the modulation method is 1024QAM.

[0416] In FIG. 56, u#k is the signal point z of 1D-NUC. s The real part of the complex number Re(z s ) and imaginary part Im(z s ) and are the components of a vector u=(u0, u1, ..., u#V-1), called the position vector. The number V of components u#k of a position vector u is given by the formula V=√(2 m ) / 2.

[0417] FIG. 57 is a diagram showing the relationship between the 1024QAM symbol y and the position vector u (its component u#k).

[0418] Now, let us consider the 10-bit symbol y of 1024QAM, starting from its leading bit (most significant bit), as y 0,s ,y 1,s ,y 2,s ,y 3,s ,y 4,s,y 5,s ,y 6,s ,y 7,s ,y 8,s ,y 9,s This will be expressed as:

[0419] A in Figure 57 represents the even-numbered 5 bits of symbol y. 1,s ,y 3,s ,y 5,s ,y 7,s ,y 9,s and the signal point z corresponding to the symbol y s The real part of the coordinate system Re(z s ) represents the correspondence with u#k.

[0420] B in Figure 57 shows the odd-numbered 5 bits of symbol y 0,s ,y 2,s ,y 4,s ,y 6,s ,y 8,s and the signal point z corresponding to the symbol y s Imaginary Part Im(z s ) represents the correspondence with u#k.

[0421] 1024QAM 10-bit symbol y=(y 0,s ,y 1,s ,y 2,s ,y 3,s ,y 4,s ,y 5,s ,y 6,s ,y 7,s ,y 8,s ,y 9,s ) is, for example, (0,0,1,0,0,1,1,1,0,0), then the odd-numbered 5 bits (y 0,s ,y 2,s ,y 4,s ,y 6,s ,y 8,s ) is (0,1,0,1,0), and the even-numbered 5 bits (y 1,s ,y 3,s ,y 5,s ,y 7,s ,y 9,s ) is (0,0,1,1,0).

[0422] In FIG. 57A, the even-numbered 5 bits (0,0,1,1,0) are associated with u11, and therefore the signal point z corresponding to the symbol y=(0,0,1,0,0,1,1,1,0,0) s The real part of Re(z s ) becomes u11.

[0423] In FIG. 57B, the odd-numbered 5 bits (0,1,0,1,0) are associated with u3, and therefore the signal point z corresponding to the symbol y=(0,0,1,0,0,1,1,1,0,0) s Imaginary Part Im(z s ) becomes u3.

[0424] On the other hand, if the coding rate r of the LDPC code is, for example, 6 / 15, according to the above-mentioned FIG. 56, for 1D-NUC used when the modulation method is 1024QAM and the coding rate of the LDPC code r(CR)=6 / 15, u3 is 0.1295 and u11 is 0.7196.

[0425] Therefore, the signal point z corresponding to the symbol y=(0,0,1,0,0,1,1,1,0,0) s The real part of Re(z s ) becomes u11=0.7196, and the imaginary part Im(z s ) results in u3 = 0.1295. As a result, the signal point z corresponding to the symbol y = (0,0,1,0,0,1,1,1,0,0) s The coordinates of are expressed as 0.7196+j0.1295.

[0426] In addition, the signal points of 1D-NUC are arranged in a grid pattern on lines parallel to the I axis and on lines parallel to the Q axis in the constellation. However, the intervals between signal points are not constant. In addition, when transmitting signal points (data mapped to them), the average power of the signal points on the constellation can be normalized. Normalization is performed by taking the root mean square of the absolute values ​​of all the signal points (coordinates of the signal points) on the constellation as P ave Then, the mean square P aveSquare root of √P ave The reciprocal of 1 / (√P ave ) for each signal point z s This can be done by multiplying

[0427] In the transmission system of FIG. 7, the above-mentioned constellations defined in ATSC3.0 can be used.

[0428] 58 to 69 are diagrams showing the coordinates of UC signal points defined in DVB-C.2.

[0429] That is, FIG. 58 shows the coordinates z of the signal point of QPSK-UC (UC of QPSK) specified in DVB-C.2. q The real part of Re(z q ) is a diagram showing the coordinates z q Imaginary Part Im(z q ) is a diagram showing the same.

[0430] Figure 60 shows the coordinates z of the signal point of 16QAM-UC (UC of 16QAM) specified in DVB-C.2. q The real part of Re(z q ) is a diagram showing the coordinates z q Imaginary Part Im(z q ) is a diagram showing the same.

[0431] Figure 62 shows the coordinates z of the signal point of 64QAM-UC (UC of 64QAM) specified in DVB-C.2. q The real part of Re(z q ) is a diagram showing the coordinates z q Imaginary Part Im(z q ) is a diagram showing the same.

[0432] Figure 64 shows the coordinates z of the signal point of 256QAM-UC (UC of 256QAM) specified in DVB-C.2.q The real part of Re(z q ) is a diagram showing the coordinates z q Imaginary Part Im(z q ) is a diagram showing the same.

[0433] Figure 66 shows the coordinates z of the signal point of 1024QAM-UC (UC of 1024QAM) specified in DVB-C.2. q The real part of Re(z q ) is a diagram showing the coordinates z q Imaginary Part Im(z q ) is a diagram showing the same.

[0434] Figure 68 shows the coordinates z of the signal point of 4096QAM-UC (UC of 4096QAM) specified in DVB-C.2. q The real part of Re(z q ) is a diagram showing the coordinates z q Imaginary Part Im(z q ) is a diagram showing the same.

[0435] In addition, in FIG. 58 to FIG. 69, y i,q is 2 m It represents the (i+1)th bit from the beginning of the m-bit QAM symbol (for example, 2 bits in QPSK). In addition, when transmitting (the data mapped to) a UC signal point, the average power of the signal points on the constellation can be normalized. Normalization is done by taking the root mean square of the absolute values ​​of all the signal points (coordinates) on the constellation as P ave Then, the mean square P ave Square root of √P ave The reciprocal of 1 / (√P ave ) for each signal point z q This can be done by multiplying

[0436] In the transmission system of FIG. 7, the UC defined in DVB-C.2 as described above can be used.

[0437] That is, for the new LDPC codes (corresponding to the parity check matrix initial value tables) in Figures 30 to 43, 50, and 52, where the code length N is 17280 bits and the coding rates r are 2 / 16, 3 / 16, 4 / 16, 5 / 16, 6 / 16, 7 / 16, 8 / 16, 9 / 16, 10 / 16, 11 / 16, 12 / 16, 13 / 16, and 14 / 16, respectively, the UCs shown in Figures 58 to 69 can be used.

[0438] 70 to 78 are diagrams showing examples of the coordinates of NUC signal points that can be used for the new LDPC codes in FIGS. 30 to 43, 50, and 52, where the code length N is 17280 bits and the coding rate r is 2 / 16, 3 / 16, 4 / 16, 5 / 16, 6 / 16, 7 / 16, 8 / 16, 9 / 16, 10 / 16, 11 / 16, 12 / 16, 13 / 16, and 14 / 16.

[0439] That is, FIG. 70 is a diagram showing an example of the coordinates of signal points of 16QAM-2D-NUC that can be used for the new LDPC code.

[0440] FIG. 71 is a diagram showing an example of the coordinates of signal points of 64QAM-2D-NUC that can be used for the new LDPC code.

[0441] 72 and 73 are diagrams showing examples of the coordinates of signal points of 256QAM-2D-NUC that can be used for the new LDPC code.

[0442] It should be noted that FIG. 73 is a sequel to FIG.

[0443] In Figs. 70 to 73, similarly to Fig. 55, the signal point z s The coordinates of are expressed in the form of complex numbers, with j representing the imaginary unit.

[0444] 70 to 73, w#k represents the coordinates of a signal point in the first quadrant of the constellation, similarly to FIG.

[0445] Here, as explained in FIG. 55, the m-bit symbol is divided into 0 to 2 m Let b be expressed as an integer value of -1, and b = 2. m / 4 means 0 to 2 m The symbols y(0), y(1), . . . , y(2 m -1) can be classified into four symbols: y(0) through y(b-1), y(b) through y(2b-1), y(2b) through y(3b-1), and y(3b) through y(4b-1).

[0446] In Figures 70 to 73, as in Figure 55, the suffix k of w#k takes an integer value ranging from 0 to b-1, and w#k represents the coordinates of the signal point corresponding to symbol y(k) ranging from symbols y(0) to y(b-1).

[0447] Furthermore, in Figures 70 to 73, similar to Figure 55, the coordinates of the signal point corresponding to symbol y(k+3b) in the range of symbols y(3b) to y(4b-1) are represented by -w#k.

[0448] However, in Figure 55, the coordinates of the signal point corresponding to symbol y(k+b) in the range of symbols y(b) to y(2b-1) are represented by -conj(w#k), and the coordinates of the signal point corresponding to symbol y(k+2b) in the range of symbols y(2b) to y(3b-1) are represented by conj(w#k), but in Figures 70 to 73, the sign of conj is reversed.

[0449] That is, in Figures 70 to 73, the coordinates of the signal point corresponding to symbol y(k+b) in the range of symbols y(b) to y(2b-1) are represented by conj(w#k), and the coordinates of the signal point corresponding to symbol y(k+2b) in the range of symbols y(2b) to y(3b-1) are represented by -conj(w#k).

[0450] FIG. 74 is a diagram showing an example of the coordinates of signal points of 1024QAM-1D-NUC that can be used for the new LDPC code.

[0451] That is, FIG. 74 shows the signal point z of 1024QAM-1D-NUC. s The real part of the complex number Re(z s ) and imaginary part Im(z s ) and the position vector u (its component u_k).

[0452] FIG. 75 is a diagram showing the relationship between the 1024QAM symbol y and the position vector u (component u#k) of FIG.

[0453] That is, let us consider a 10-bit symbol y of 1024QAM, starting from its leading bit (most significant bit), as follows: 0,s ,y 1,s ,y 2,s ,y 3,s ,y 4,s ,y 5,s ,y 6,s ,y 7,s ,y 8,s ,y 9,s This will be expressed as:

[0454] A in Figure 75 shows the odd-numbered 5 bits (from the beginning) of the 10-bit symbol y. 0,s ,y 2,s ,y 4,s ,y 6,s ,y 8,s and the signal point z corresponding to the symbol y s The real part of (coordinates) Re(z s ) and the position vector u_k.

[0455] B in Figure 75 shows the even-numbered 5 bits y of the 10-bit symbol y. 1,s ,y 3,s ,y 5,s ,y 7,s ,y 9,s and the signal point z corresponding to the symbol y s Imaginary Part Im(z s) and the position vector u_k.

[0456] The 10-bit symbol y of 1024QAM corresponds to the signal point z of 1024QAM-1D-NUC defined in Figures 74 and 75. s When the signal point z is mapped to s The method of determining the coordinates is the same as that explained with reference to Figures 56 and 57, so the explanation will be omitted.

[0457] FIG. 76 is a diagram showing an example of the coordinates of signal points of 4096QAM-1D-NUC that can be used for the new LDPC code.

[0458] That is, FIG. 76 shows the signal point z of 4096QAM-1D-NUC. s The real part of the complex number Re(z s ) and imaginary part Im(z s ) and the position vector u(u#k).

[0459] 77 and 78 are diagrams showing the relationship between the symbol y of 4096QAM and the position vector u (component u#k) of FIG.

[0460] That is, let us consider a 12-bit symbol y of 4096QAM, starting from its leading bit (most significant bit), as follows: 0,s ,y 1,s ,y 2,s ,y 3,s ,y 4,s ,y 5,s ,y 6,s ,y 7,s ,y 8,s ,y 9,s ,y 10,s ,y 11,s This will be expressed as:

[0461] Figure 77 shows the odd-numbered 6 bits y of the 12-bit symbol y. 0,s ,y 2,s ,y 4,s ,y 6,s ,y 8,s ,y 10,sand the signal point z corresponding to the symbol y s The real part of Re(z s ) and the position vector u_k.

[0462] Figure 78 shows the even-numbered 6 bits y of the 12-bit symbol y. 1,s ,y 3,s ,y 5,s ,y 7,s ,y 9,s ,y 11,s and the signal point z corresponding to the symbol y s Imaginary Part Im(z s ) and the position vector u_k.

[0463] The 12-bit symbol y of 4096QAM corresponds to the signal point z of 4096QAM-1D-NUC defined in Figures 76 to 78. s When the signal point z is mapped to s The method of determining the coordinates is the same as that explained with reference to Figures 56 and 57, so the explanation will be omitted.

[0464] In addition, when transmitting the signal points (data mapped to) of the NUC in Figures 70 to 78, the average power of the signal points on the constellation can be normalized. Normalization is performed by taking the root mean square of the absolute values ​​of all the signal points (coordinates) on the constellation as P ave Then, the mean square P ave Square root of √P ave The reciprocal of 1 / (√P ave ) for each signal point z s In addition, in FIG. 57, odd-numbered bits of symbol y are multiplied by signal point z s Imaginary Part Im(z s ), and the even-numbered bits of the symbol y correspond to the signal point z s The real part of Re(z s), but in Figures 75, 77, and 78, the odd-numbered bits of the symbol y correspond to the signal point z s The real part of Re(z s ), and the even-numbered bits of the symbol y correspond to the signal point z s Imaginary Part Im(z s ) is associated with a position vector u_k representing the

[0465] <Block Interleaver 25>

[0466] FIG. 79 is a diagram for explaining the block interleaving performed in the block interleaver 25 of FIG.

[0467] Block interleaving is performed by dividing an LDPC code of one codeword, from the beginning, into a portion called part 1 and a portion called part 2.

[0468] If the length (number of bits) of part 1 is represented as Npart1 and the length of part 2 is represented as Npart2, then Npart1+Npart2 is equal to the code length N.

[0469] Conceptually, in block interleaving, columns as storage areas for storing Npart1 / m bits are arranged in a column (vertical) direction as one direction, and the number m, which is equal to the number of bits m of a symbol, is arranged in a row direction perpendicular to the column direction, and each column is divided from the top into small units of 360 bits, which is the parallel factor P. These small units of columns are also called column units.

[0470] In block interleaving, as shown in FIG. 79, part 1 of an LDPC code of one codeword is written from the top to the bottom (column direction) of the first column unit of a column, from left to right toward the column.

[0471] Then, when writing to the first column unit of the rightmost column is completed, as shown in FIG. 79, the process returns to the leftmost column, and writing is performed from top to bottom of the second column unit of the column, proceeding from left to right columns, and so on until part 1 of the LDPC code for one codeword is written.

[0472] When writing of part 1 of the LDPC code of one codeword is completed, part 1 of the LDPC code is read out in m-bit units in the row direction from the first row of all m columns, as shown in FIG.

[0473] The m-bit units of part 1 are fed as m-bit symbols from the block interleaver 25 to the mapper 117 (FIG. 8).

[0474] Part 1 is read out in m-bit units, sequentially moving down the m columns, and when reading of part 1 is completed, part 2 is divided into m-bit units from the beginning and supplied as m-bit symbols from block interleaver 25 to mapper 117.

[0475] Therefore, part 1 is symbolized while being interleaved, and part 2 is symbolized sequentially, divided into m bits, without being interleaved.

[0476] The length of the column, Npart1 / m, is a multiple of 360, which is the parallel factor P. In this way, an LDPC code of one code word is divided into part 1 and part 2 so that Npart1 / m is a multiple of 360.

[0477] FIG. 80 is a diagram showing examples of part 1 and part 2 of an LDPC code with a code length N of 17280 bits when the modulation scheme is QPSK, 16QAM, 64QAM, and 256QAM, respectively.

[0478] When the modulation method is QPSK, 16QAM, 64QAM, or 256QAM, in each case, part 1 is 17280 bits and part 2 is 0 bit.

[0479] <Group-wise interleaving>

[0480] FIG. 81 is a diagram for explaining group-wise interleaving performed in group-wise interleaver 24 of FIG.

[0481] In group-wise interleaving, as shown in FIG. 81, an LDPC code of one codeword is divided into 360-bit units, which is equal to the parallel factor P, from the beginning of the codeword. The 360 ​​bits of each division are treated as a bit group, and the LDPC code of one codeword is interleaved in bit group units according to a predetermined pattern (hereinafter also referred to as a GW pattern).

[0482] Here, when an LDPC code of one codeword is divided into bit groups, the (i+1)th bit group from the beginning will hereinafter also be referred to as bit group i.

[0483] When the parallel factor P is 360, for example, an LDPC code with a code length N of 1800 bits is divided into 5 (=1800 / 360) bit groups, namely, bit groups 0, 1, 2, 3, and 4. Furthermore, for example, an LDPC code with a code length N of 69120 bits is divided into 192 (=69120 / 360) bit groups, namely, bit groups 0, 1, . . . , 191. Furthermore, for example, an LDPC code with a code length N of 17280 bits is divided into 48 (=17280 / 360) bit groups, namely, bit groups 0, 1, . . . , 47.

[0484] Hereinafter, the GW pattern shall be represented by a sequence of numbers representing bit groups. For example, for an LDPC code of five bit groups 0, 1, 2, 3, 4 with a code length N of 1800 bits, for example, the GW pattern 4, 2, 0, 3, 1 represents interleaving (rearranging) the sequence of bit groups 0, 1, 2, 3, 4 into the sequence of bit groups 4, 2, 0, 3, 1. Note that for the sequence of bit groups and the GW pattern, in addition to being represented by a comma-separated sequence of numbers representing bit groups (e.g., 4, 2, 0, 3, 1), it can also be represented by a space-separated sequence of numbers representing bit groups (e.g., 4 2 0 3 1).

[0485] For example, now, let the (i + 1)-th code bit from the beginning of an LDPC code with a code length N of 1800 bits be represented by x i as follows.

[0486] In this case, according to the group-wise interleaving of the GW pattern 4, 2, 0, 3, 1, the 1800-bit LDPC code {x0, x1,..., x 1799} is interleaved into the sequence of {x 1440 , x 1441 ,..., x 1799}, {x 720 , x 721 ,..., x 1079}, {x0, x1,..., x 359}, {x 1080 , x 1081 ,..., x 1439}, {x 360 , x 361 ,..., x 719}.

[0487] The GW pattern can be set for each code length N of the LDPC code, for each coding rate r, for each modulation method, for each constellation, and further for each combination of two or more of the code length N, coding rate r, modulation method, and constellation.

[0488] <Examples of GW Patterns for LDPC Codes>

[0489] FIG. 82 is a diagram illustrating a first example of a GW pattern for an LDPC code having a code length N of 17280 bits.

[0490] According to the GW pattern in FIG. 82, the sequence of bit groups 0 to 47 of the 17280-bit LDPC code is 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 are interleaved in the sequence.

[0491] FIG. 83 is a diagram illustrating a second example of a GW pattern for an LDPC code having a code length N of 17280 bits.

[0492] According to the GW pattern in FIG. 83, the arrangement of bit groups 0 to 47 of the 17280-bit LDPC code is 19 33 45 22 43 23 46 32 11 40 13 34 14 47 0 12 6 26 37 4 5 17 25 30 39 29 27 28 10 21 36 9 3 20 24 42 7 41 44 38 15 8 31 16 2 1 35 18 are interleaved in the sequence.

[0493] FIG. 84 is a diagram illustrating a third example of a GW pattern for an LDPC code having a code length N of 17280 bits.

[0494] According to the GW pattern in FIG. 84, the sequence of bit groups 0 to 47 of the 17280-bit LDPC code is 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 are interleaved in the sequence.

[0495] FIG. 85 is a diagram illustrating a fourth example of a GW pattern for an LDPC code having a code length N of 17280 bits.

[0496] According to the GW pattern in FIG. 85, the sequence of bit groups 0 to 47 of the 17280-bit LDPC code is 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 are interleaved in the sequence.

[0497] FIG. 86 is a diagram illustrating a fifth example of a GW pattern for an LDPC code having a code length N of 17280 bits.

[0498] According to the GW pattern in FIG. 86, the arrangement of bit groups 0 to 47 of the 17280-bit LDPC code is 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 are interleaved in the sequence.

[0499] FIG. 87 is a diagram illustrating a sixth example of a GW pattern for an LDPC code having a code length N of 17280 bits.

[0500] According to the GW pattern in FIG. 87, the sequence of bit groups 0 to 47 of the 17280-bit LDPC code is 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 are interleaved in the sequence.

[0501] FIG. 88 is a diagram illustrating a seventh example of a GW pattern for an LDPC code having a code length N of 17280 bits.

[0502] According to the GW pattern in FIG. 88, the arrangement of bit groups 0 to 47 of the 17280-bit LDPC code is 0 34 30 6 11 35 5 24 4 13 15 16 3 31 39 40 37 47 28 12 36 42 33 22 20 8 9 44 29 18 25 21 23 10 14 26 45 7 27 46 1 2 17 41 19 43 38 32 are interleaved in the sequence.

[0503] FIG. 89 is a diagram illustrating an eighth example of a GW pattern for an LDPC code having a code length N of 17280 bits.

[0504] According to the GW pattern in FIG. 89, the arrangement of bit groups 0 to 47 of the 17280-bit LDPC code is 33 16 0 26 35 31 21 34 42 43 32 29 7 47 37 28 5 9 30 25 3 17 23 24 41 45 20 12 27 39 8 4 1 6 2 38 10 40 18 19 46 11 36 13 22 14 15 44 are interleaved in the sequence.

[0505] FIG. 90 is a diagram illustrating a ninth example of a GW pattern for an LDPC code having a code length N of 17280 bits.

[0506] According to the GW pattern in FIG. 90, the sequence of bit groups 0 to 47 of the 17280-bit LDPC code is 41 10 21 37 9 8 11 27 16 23 25 2 34 7 29 28 5 15 31 45 4 43 33 22 18 13 35 30 6 12 44 1 20 40 42 39 19 17 36 38 26 0 32 3 47 14 24 46 are interleaved in the sequence.

[0507] FIG. 91 is a diagram illustrating a tenth example of a GW pattern for an LDPC code having a code length N of 17280 bits.

[0508] According to the GW pattern in FIG. 91, the sequence of bit groups 0 to 47 of the 17280-bit LDPC code is 15 21 29 10 12 32 1 9 31 47 23 30 26 18 0 28 7 20 43 44 3 45 5 17 16 46 40 39 6 38 34 36 22 33 27 24 25 13 14 37 19 8 42 11 4 2 35 41 are interleaved in the sequence.

[0509] FIG. 92 is a diagram illustrating an eleventh example of a GW pattern for an LDPC code having a code length N of 17280 bits.

[0510] According to the GW pattern in FIG. 92, the sequence of bit groups 0 to 47 of the 17280-bit LDPC code is 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 are interleaved in the sequence.

[0511] FIG. 93 is a diagram illustrating a twelfth example of a GW pattern for an LDPC code having a code length N of 17280 bits.

[0512] According to the GW pattern in FIG. 93, the arrangement of bit groups 0 to 47 of the 17280-bit LDPC code is 31 23 1 42 36 25 47 3 12 30 32 8 11 27 21 40 16 13 34 4 26 35 46 20 29 28 5 43 18 39 24 14 0 10 7 41 37 9 38 33 2 6 19 45 17 15 22 44 are interleaved in the sequence.

[0513] FIG. 94 is a diagram illustrating a thirteenth example of a GW pattern for an LDPC code having a code length N of 17280 bits.

[0514] According to the GW pattern in FIG. 94, the arrangement of bit groups 0 to 47 of the 17280-bit LDPC code is 46 11 23 33 10 0 17 47 20 5 38 29 28 16 41 27 2 31 43 37 34 12 35 24 21 44 40 36 32 39 4 19 26 6 30 9 42 1 22 8 3 45 14 15 13 7 25 18 are interleaved in the sequence.

[0515] FIG. 95 is a diagram illustrating a 14th example of a GW pattern for an LDPC code having a code length N of 17280 bits.

[0516] According to the GW pattern in FIG. 95, the sequence of bit groups 0 to 47 of the 17280-bit LDPC code is 16 32 33 43 3 29 0 22 40 24 44 8 20 13 15 45 7 34 39 42 25 28 18 26 38 10 11 41 47 23 6 1 14 4 12 31 21 19 37 36 30 5 46 27 35 2 9 17 are interleaved in the sequence.

[0517] FIG. 96 is a diagram illustrating a fifteenth example of a GW pattern for an LDPC code having a code length N of 17280 bits.

[0518] According to the GW pattern in FIG. 96, the arrangement of bit groups 0 to 47 of the 17280-bit LDPC code is 23 42 33 17 37 2 22 14 21 0 12 44 30 1 25 35 46 13 10 24 20 15 45 31 41 43 28 36 16 4 32 18 3 6 34 11 40 5 38 27 29 8 26 7 39 9 47 19 are interleaved in the sequence.

[0519] FIG. 97 is a diagram illustrating a 16th example of a GW pattern for an LDPC code having a code length N of 17280 bits.

[0520] According to the GW pattern in FIG. 97, the arrangement of bit groups 0 to 47 of the 17280-bit LDPC code is 7 0 8 39 17 3 32 2 13 19 16 14 5 10 27 35 45 26 44 43 11 24 28 34 20 29 22 41 18 9 37 12 21 4 46 33 15 36 42 1 40 25 23 30 6 38 31 47 are interleaved in the sequence.

[0521] FIG. 98 is a diagram illustrating a 17th example of a GW pattern for an LDPC code having a code length N of 17280 bits.

[0522] According to the GW pattern in FIG. 98, the arrangement of bit groups 0 to 47 of the 17280-bit LDPC code is 1 28 12 35 23 36 24 17 10 14 15 37 18 13 41 38 33 29 16 21 27 4 9 31 45 40 0 ​​46 7 43 30 34 8 44 47 2 20 6 42 3 22 39 5 32 11 19 25 26 are interleaved in the sequence.

[0523] FIG. 99 is a diagram showing an 18th example of a GW pattern for an LDPC code having a code length N of 17280 bits.

[0524] According to the GW pattern in FIG. 99, the sequence of bit groups 0 to 47 of the 17280-bit LDPC code is 9 8 3 40 27 4 7 45 28 29 14 41 20 6 21 5 36 12 31 39 30 15 37 10 34 25 1 47 26 13 32 43 44 24 33 16 42 2 22 19 18 35 23 46 11 17 38 0 are interleaved in the sequence.

[0525] FIG. 100 is a diagram showing a 19th example of a GW pattern for an LDPC code having a code length N of 17280 bits.

[0526] According to the GW pattern of FIG. 100, the sequence of bit groups 0 to 47 of the 17280-bit LDPC code is 12 42 40 41 20 18 27 24 39 6 0 15 8 31 10 3 13 46 4 37 33 25 44 2 16 23 28 14 17 43 45 1 35 38 26 21 36 22 47 11 34 29 30 32 19 7 5 9 are interleaved in the sequence.

[0527] FIG. 101 is a diagram illustrating a 20th example of a GW pattern for an LDPC code having a code length N of 17280 bits.

[0528] According to the GW pattern in FIG. 101, the sequence of bit groups 0 to 47 of the 17280-bit LDPC code is 33 18 21 29 14 4 35 32 26 15 11 6 1 47 38 17 45 27 2 5 16 12 23 25 3 0 42 13 41 46 9 24 40 43 7 31 39 34 30 20 8 36 22 10 19 28 37 44 are interleaved in the sequence.

[0529] FIG. 102 is a diagram illustrating a 21st example of a GW pattern for an LDPC code having a code length N of 17280 bits.

[0530] According to the GW pattern in FIG. 102, the sequence of bit groups 0 to 47 of the 17280-bit LDPC code is 7 28 41 8 6 12 14 47 4 38 32 37 23 33 15 46 22 0 34 24 40 45 27 19 43 11 36 9 17 21 31 44 2 1 26 13 42 30 35 5 29 25 16 20 39 10 18 3 are interleaved in the sequence.

[0531] FIG. 103 is a diagram illustrating a 22nd example of a GW pattern for an LDPC code having a code length N of 17280 bits.

[0532] According to the GW pattern in FIG. 103, the sequence of bit groups 0 to 47 of the 17280-bit LDPC code is 30 14 40 26 21 5 12 3 18 17 11 38 4 46 7 31 0 1 27 36 8 10 2 22 13 9 37 42 41 32 15 39 23 25 34 24 35 28 20 16 19 33 6 43 29 45 47 44 are interleaved in the sequence.

[0533] FIG. 104 is a diagram illustrating a 23rd example of a GW pattern for an LDPC code having a code length N of 17280 bits.

[0534] According to the GW pattern in FIG. 104, the sequence of bit groups 0 to 47 of the 17280-bit LDPC code is 23 20 14 9 44 41 19 36 38 13 16 28 0 8 2 39 31 29 21 10 11 33 32 27 46 7 5 35 26 1 43 40 37 17 47 30 6 18 15 42 3 25 4 22 24 12 45 34 are interleaved in the sequence.

[0535] FIG. 105 is a diagram illustrating a 24th example of a GW pattern for an LDPC code having a code length N of 17280 bits.

[0536] According to the GW pattern in FIG. 105, the sequence of bit groups 0 to 47 of the 17280-bit LDPC code is 37 30 14 13 2 31 27 9 46 41 47 18 23 28 43 10 39 42 16 22 36 8 33 32 4 1 45 19 12 6 35 0 24 25 15 38 44 7 26 21 34 40 29 20 11 5 17 3 are interleaved in the sequence.

[0537] FIG. 106 is a diagram illustrating a 25th example of a GW pattern for an LDPC code having a code length N of 17280 bits.

[0538] According to the GW pattern in FIG. 106, the sequence of bit groups 0 to 47 of the 17280-bit LDPC code is 6 28 25 38 43 11 21 31 47 8 17 39 23 27 30 32 3 35 12 7 1 16 18 36 10 24 41 4 44 22 5 33 46 29 0 26 9 42 37 45 15 40 2 19 14 20 34 13 are interleaved in the sequence.

[0539] FIG. 107 is a diagram illustrating a 26th example of a GW pattern for an LDPC code having a code length N of 17280 bits.

[0540] According to the GW pattern in FIG. 107, the sequence of bit groups 0 to 47 of the 17280-bit LDPC code is 39 11 12 7 3 1 40 31 27 0 45 42 6 5 24 36 46 19 34 22 29 13 35 2 17 33 20 14 15 25 38 9 41 30 44 18 8 28 37 4 32 47 16 43 21 23 26 10 are interleaved in the sequence.

[0541] FIG. 108 is a diagram illustrating a 27th example of a GW pattern for an LDPC code having a code length N of 17280 bits.

[0542] According to the GW pattern of FIG. 108, the arrangement of bit groups 0 to 47 of the 17280-bit LDPC code is 7 19 31 20 36 35 2 4 46 12 28 21 39 43 26 23 32 5 37 3 11 34 18 45 24 1 13 47 10 27 0 9 33 25 8 40 6 16 22 29 42 38 14 44 41 17 30 15 are interleaved in the sequence.

[0543] FIG. 109 is a diagram illustrating a 28th example of a GW pattern for an LDPC code having a code length N of 17280 bits.

[0544] According to the GW pattern in FIG. 109, the sequence of bit groups 0 to 47 of the 17280-bit LDPC code is 12 7 39 31 30 44 14 33 35 17 37 27 2 28 9 26 32 3 46 0 34 6 43 25 21 47 18 45 5 20 13 38 11 29 16 36 8 40 15 41 10 23 1 19 4 22 42 24 are interleaved in the sequence.

[0545] FIG. 110 is a diagram illustrating a 29th example of a GW pattern for an LDPC code having a code length N of 17280 bits.

[0546] According to the GW pattern in FIG. 110, the sequence of bit groups 0 to 47 of the 17280-bit LDPC code is 20 19 13 25 32 9 5 24 39 4 29 40 14 18 43 46 21 44 10 15 35 3 23 47 37 12 30 33 27 36 8 28 38 7 42 22 2 0 6 16 45 26 17 11 31 34 41 1 are interleaved in the sequence.

[0547] FIG. 111 is a diagram illustrating a 30th example of a GW pattern for an LDPC code having a code length N of 17280 bits.

[0548] According to the GW pattern in FIG. 111, the sequence of bit groups 0 to 47 of the 17280-bit LDPC code is 19 20 44 3 6 28 13 15 16 24 9 34 39 8 17 40 29 31 22 10 11 7 35 42 23 2 14 37 33 1 26 45 38 12 47 30 5 18 46 0 41 27 4 21 43 25 36 32 are interleaved in the sequence.

[0549] FIG. 112 is a diagram illustrating a 31st example of a GW pattern for an LDPC code having a code length N of 17280 bits.

[0550] According to the GW pattern in FIG. 112, the sequence of bit groups 0 to 47 of the 17280-bit LDPC code is 4 26 7 21 43 42 33 17 35 19 10 39 27 13 18 34 38 3 28 36 1 5 44 37 16 30 14 9 32 47 29 2 31 23 0 24 11 8 6 46 40 45 15 22 25 20 12 41 are interleaved in the sequence.

[0551] FIG. 113 is a diagram illustrating a 32nd example of a GW pattern for an LDPC code having a code length N of 17280 bits.

[0552] According to the GW pattern in FIG. 113, the sequence of bit groups 0 to 47 of the 17280-bit LDPC code is 8 28 33 21 1 39 34 7 0 17 5 41 23 2 14 10 29 25 13 18 35 38 27 44 20 32 31 11 40 30 24 3 36 22 15 37 16 6 42 45 19 47 12 26 43 9 46 4 are interleaved in the sequence.

[0553] FIG. 114 is a diagram illustrating a 33rd example of a GW pattern for an LDPC code having a code length N of 17280 bits.

[0554] According to the GW pattern in FIG. 114, the sequence of bit groups 0 to 47 of the 17280-bit LDPC code is 0 39 23 44 19 21 35 13 36 27 47 3 31 11 9 41 43 8 14 26 6 5 15 16 38 7 32 22 30 33 37 40 28 45 12 24 17 42 20 29 1 4 10 2 25 18 46 34 are interleaved in the sequence.

[0555] FIG. 115 is a diagram illustrating a 34th example of a GW pattern for an LDPC code having a code length N of 17280 bits.

[0556] According to the GW pattern in FIG. 115, the sequence of bit groups 0 to 47 of the 17280-bit LDPC code is 11 0 42 24 46 27 25 3 1 41 22 40 19 18 14 36 33 4 47 12 39 30 13 5 2 7 31 9 38 35 15 43 45 44 28 20 32 21 26 23 6 10 8 37 17 34 29 16 are interleaved in the sequence.

[0557] FIG. 116 is a diagram illustrating a 35th example of a GW pattern for an LDPC code having a code length N of 17280 bits.

[0558] According to the GW pattern in FIG. 116, the sequence of bit groups 0 to 47 of the 17280-bit LDPC code is 5 45 42 35 13 41 2 29 15 11 16 0 8 1 33 34 44 7 43 22 24 19 9 38 18 12 26 20 28 21 10 30 40 6 46 37 47 17 3 32 4 39 23 25 36 14 31 27 are interleaved in the sequence.

[0559] FIG. 117 is a diagram illustrating a 36th example of a GW pattern for an LDPC code having a code length N of 17280 bits.

[0560] According to the GW pattern in FIG. 117, the sequence of bit groups 0 to 47 of the 17280-bit LDPC code is 18 16 21 2 43 10 44 42 19 15 20 26 1 38 46 28 17 29 6 22 7 32 31 30 24 3 8 9 12 37 47 40 39 5 35 11 25 45 34 33 23 4 14 27 13 41 36 0 are interleaved in the sequence.

[0561] FIG. 118 is a diagram illustrating a 37th example of a GW pattern for an LDPC code having a code length N of 17280 bits.

[0562] According to the GW pattern in FIG. 118, the sequence of bit groups 0 to 47 of the 17280-bit LDPC code is 28 9 4 27 17 10 12 6 19 30 1 23 39 14 38 34 46 8 15 43 13 47 0 44 7 24 45 18 25 29 37 42 22 31 11 36 20 32 41 33 2 26 21 5 3 16 40 35 are interleaved in the sequence.

[0563] FIG. 119 is a diagram illustrating a 38th example of a GW pattern for an LDPC code having a code length N of 17280 bits.

[0564] According to the GW pattern in FIG. 119, the sequence of bit groups 0 to 47 of the 17280-bit LDPC code is 5 37 36 38 16 21 41 44 10 18 26 27 15 1 43 2 33 14 9 30 8 12 23 4 13 35 31 3 34 19 42 47 46 29 0 25 20 17 39 45 28 6 22 11 32 40 24 7 are interleaved in the sequence.

[0565] FIG. 120 is a diagram illustrating a 39th example of a GW pattern for an LDPC code having a code length N of 17280 bits.

[0566] According to the GW pattern in FIG. 120, the sequence of bit groups 0 to 47 of the 17280-bit LDPC code is 11 1 12 21 13 15 24 36 34 0 37 9 14 39 19 16 17 28 40 29 23 46 30 38 33 3 6 18 26 7 27 45 10 25 4 42 31 43 35 32 5 8 44 41 47 22 20 2 are interleaved in the sequence.

[0567] FIG. 121 is a diagram showing a 40th example of a GW pattern for an LDPC code having a code length N of 17280 bits.

[0568] According to the GW pattern in FIG. 121, the sequence of bit groups 0 to 47 of the 17280-bit LDPC code is 3 41 6 42 21 2 25 45 8 39 34 26 47 43 23 20 13 16 38 24 5 40 0 ​​11 7 31 32 15 36 33 9 12 10 30 29 14 18 35 46 4 28 19 1 44 37 27 17 22 are interleaved in the sequence.

[0569] FIG. 122 is a diagram illustrating a 41st example of a GW pattern for an LDPC code having a code length N of 17280 bits.

[0570] According to the GW pattern in FIG. 122, the sequence of bit groups 0 to 47 of the 17280-bit LDPC code is 40 42 11 10 15 6 34 37 16 45 25 47 32 8 17 26 29 7 18 21 46 44 28 27 20 38 43 36 33 5 24 9 13 2 0 4 39 31 1 22 30 12 14 41 23 3 19 35 are interleaved in the sequence.

[0571] FIG. 123 is a diagram illustrating a 42nd example of a GW pattern for an LDPC code having a code length N of 17280 bits.

[0572] According to the GW pattern in FIG. 123, the sequence of bit groups 0 to 47 of the 17280-bit LDPC code is 6 0 20 18 37 27 39 3 1 2 46 11 24 36 14 15 4 16 10 13 35 23 26 30 19 42 7 9 33 40 12 34 22 5 28 21 32 38 44 25 17 41 29 45 8 47 31 43 are interleaved in the sequence.

[0573] FIG. 124 is a diagram illustrating a 43rd example of a GW pattern for an LDPC code having a code length N of 17280 bits.

[0574] According to the GW pattern in FIG. 124, the sequence of bit groups 0 to 47 of the 17280-bit LDPC code is 8 25 12 9 26 37 35 28 14 5 6 2 29 38 22 31 11 21 17 33 42 43 36 45 20 27 44 13 16 46 10 30 3 32 19 1 15 4 18 40 47 7 34 24 41 23 39 0 are interleaved in the sequence.

[0575] FIG. 125 is a diagram illustrating a 44th example of a GW pattern for an LDPC code having a code length N of 17280 bits.

[0576] According to the GW pattern in FIG. 125, the sequence of bit groups 0 to 47 of the 17280-bit LDPC code is 7 17 26 27 9 39 46 47 32 12 35 25 14 11 22 23 16 29 38 33 34 4 40 10 5 18 37 1 24 44 30 3 0 45 28 13 15 20 6 21 31 19 2 8 41 36 42 43 are interleaved in the sequence.

[0577] FIG. 126 is a diagram illustrating a 45th example of a GW pattern for an LDPC code having a code length N of 17280 bits.

[0578] According to the GW pattern in FIG. 126, the sequence of bit groups 0 to 47 of the 17280-bit LDPC code is 11 14 32 27 44 43 0 47 1 8 35 33 7 2 41 15 13 4 23 30 16 42 46 24 9 17 21 20 18 5 19 12 3 34 28 40 39 37 31 38 45 36 6 22 26 10 25 29 are interleaved in the sequence.

[0579] The above-mentioned first to forty-fifth examples of GW patterns for an LDPC code having a code length N of 17280 bits can be applied to any combination of an LDPC code having a code length N of 17280 bits, any coding rate r, any modulation scheme, and any constellation.

[0580] However, for group-wise interleaving, the error rate can be further improved for each combination by setting the GW pattern to be applied for each combination of the code length N of the LDPC code, the coding rate r of the LDPC code, the modulation method, and the constellation.

[0581] The GW pattern in FIG. 82 can achieve a particularly good error rate by applying it to a combination of the type A code of r=3 / 16 (corresponding to the parity check matrix initial value table) in FIG. 31, QPSK, and QPSK-UC in FIG. 58 and FIG. 59.

[0582] The GW pattern in FIG. 83 can achieve a particularly good error rate by applying it to, for example, the type A code of r=5 / 16 in FIG. 33, QPSK, and the combination of QPSK-UC in FIGS. 58 and 59.

[0583] The GW pattern in FIG. 84 can achieve a particularly good error rate by applying it to, for example, the type B code of r=7 / 16 in FIG. 36, QPSK, and the combination of QPSK-UC in FIGS. 58 and 59.

[0584] The GW pattern in FIG. 85 can achieve a particularly good error rate by applying it to, for example, the new type B code with r=9 / 16 in FIG. 52, QPSK, and the combination of QPSK-UC in FIGS. 58 and 59.

[0585] The GW pattern in FIG. 86 can achieve a particularly good error rate by applying it to, for example, the type B code of r=11 / 16 in FIG. 40, QPSK, and the combination of QPSK-UC in FIGS. 58 and 59.

[0586] The GW pattern in FIG. 87 can achieve a particularly good error rate by applying it to, for example, the type B code of r=13 / 16 in FIG. 42, QPSK, and the combination of QPSK-UC in FIGS. 58 and 59.

[0587] The GW pattern of FIG. 88 can achieve a particularly good error rate by applying it to, for example, a combination of the Type A code of r=3 / 16 of FIG. 31, 16QAM, and 16QAM-UC of FIG. 60 and FIG. 61.

[0588] The GW pattern in FIG. 89 can achieve a particularly good error rate by applying it to a combination of, for example, the type A code of r=5 / 16 in FIG. 33, 16QAM, and 16QAM-UC in FIG. 60 and FIG. 61.

[0589] The GW pattern in FIG. 90 can achieve a particularly good error rate by applying it to a combination of, for example, the Type B code of r=7 / 16 in FIG. 36, 16QAM, and 16QAM-UC in FIGS. 60 and 61.

[0590] The GW pattern in FIG. 91 can achieve a particularly good error rate by applying it to a combination of the new type B code of r=9 / 16 in FIG. 52, 16QAM, and 16QAM-UC in FIGS. 60 and 61, for example.

[0591] The GW pattern in FIG. 92 can achieve a particularly good error rate by applying it to, for example, a combination of the Type B code of r=11 / 16 in FIG. 40, 16QAM, and 16QAM-UC in FIGS. 60 and 61.

[0592] The GW pattern in FIG. 93 can achieve a particularly good error rate by applying it to a combination of, for example, the Type B code of r=13 / 16 in FIG. 42, 16QAM, and 16QAM-UC in FIG. 60 and FIG. 61.

[0593] The GW pattern in FIG. 94 can achieve a particularly good error rate by applying it to a combination of, for example, the type A code of r=2 / 16 in FIG. 30, 16QAM, and 16QAM-2D-NUC in FIG.

[0594] The GW pattern in FIG. 95 can achieve a particularly good error rate by applying it to a combination of the new type A code of r=4 / 16 in FIG. 50, 16QAM, and 16QAM-2D-NUC in FIG.

[0595] The GW pattern in FIG. 96 can achieve a particularly good error rate by applying it to a combination of, for example, the type A code of r=6 / 16 in FIG. 34, 16QAM, and 16QAM-2D-NUC in FIG.

[0596] The GW pattern in FIG. 97 can achieve a particularly good error rate by applying it to a combination of, for example, the type B code of r=8 / 16 in FIG. 37, 16QAM, and 16QAM-2D-NUC in FIG.

[0597] The GW pattern in FIG. 98 can achieve a particularly good error rate by applying it to a combination of, for example, the type B code of r=10 / 16 in FIG. 39, 16QAM, and 16QAM-2D-NUC in FIG.

[0598] The GW pattern in FIG. 99 can achieve a particularly good error rate by applying it to a combination of, for example, the Type B code of r=12 / 16 in FIG. 41, 16QAM, and 16QAM-2D-NUC in FIG.

[0599] The GW pattern in FIG. 100 can achieve a particularly good error rate by applying it to a combination of, for example, the type B code of r=14 / 16 in FIG. 43, 16QAM, and 16QAM-2D-NUC in FIG.

[0600] The GW pattern of FIG. 101 can achieve a particularly good error rate by applying it to a combination of, for example, the Type A code of r=2 / 16 of FIG. 30, 64QAM, and 64QAM-UC of FIG. 62 and FIG. 63.

[0601] The GW pattern in FIG. 102 can achieve a particularly good error rate by applying it to a combination of the new type A code of r=4 / 16 in FIG. 50, 64QAM, and 64QAM-UC in FIGS. 62 and 63, for example.

[0602] The GW pattern of FIG. 103 can achieve a particularly good error rate by applying it to, for example, a combination of the Type A code of r=6 / 16 of FIG. 34, 64QAM, and 64QAM-UC of FIG. 62 and FIG. 63.

[0603] The GW pattern of FIG. 104 can achieve a particularly good error rate by applying it to, for example, a combination of the Type B code of r=8 / 16 of FIG. 37, 64QAM, and 64QAM-UC of FIG. 62 and FIG. 63.

[0604] The GW pattern of FIG. 105 can achieve a particularly good error rate by applying it to, for example, a combination of the Type B code of r=10 / 16 of FIG. 39, 64QAM, and 64QAM-UC of FIG. 62 and FIG. 63.

[0605] The GW pattern of FIG. 106 can achieve a particularly good error rate by applying it to, for example, a combination of the Type B code of r=12 / 16 of FIG. 41, 64QAM, and 64QAM-UC of FIG. 62 and FIG. 63.

[0606] The GW pattern of FIG. 107 can achieve a particularly good error rate by applying it to, for example, a combination of the Type B code of r=14 / 16 of FIG. 43, 64QAM, and 64QAM-UC of FIG. 62 and FIG. 63.

[0607] The GW pattern in FIG. 108 can achieve a particularly good error rate by applying it to a combination of, for example, the Type A code of r=3 / 16 in FIG. 31, 64QAM, and 64QAM-2D-NUC in FIG.

[0608] The GW pattern in FIG. 109 can achieve a particularly good error rate by applying it to a combination of, for example, the type A code of r=5 / 16 in FIG. 33, 64QAM, and 64QAM-2D-NUC in FIG.

[0609] The GW pattern in FIG. 110 can achieve a particularly good error rate by applying it to a combination of, for example, the type B code of r=7 / 16 in FIG. 36, 64QAM, and 64QAM-2D-NUC in FIG.

[0610] The GW pattern in FIG. 111 can achieve a particularly good error rate by applying it to a combination of the new type B code with r=9 / 16 in FIG. 52, 64QAM, and 64QAM-2D-NUC in FIG. 71, for example.

[0611] The GW pattern in FIG. 112 can achieve a particularly good error rate by applying it to a combination of the type B code of r=11 / 16 in FIG. 40, 64QAM, and 64QAM-2D-NUC in FIG. 71, for example.

[0612] The GW pattern in FIG. 113 can achieve a particularly good error rate by applying it to a combination of, for example, the type B code of r=13 / 16 in FIG. 42, 64QAM, and 64QAM-2D-NUC in FIG.

[0613] The GW pattern in FIG. 114 can achieve a particularly good error rate by applying it to, for example, a combination of the Type A code of r=3 / 16 in FIG. 31, 256QAM, and 256QAM-UC in FIGS. 64 and 65.

[0614] The GW pattern in FIG. 115 can achieve a particularly good error rate by applying it to a combination of, for example, the Type A code of r=5 / 16 in FIG. 33, 256QAM, and 256QAM-UC in FIGS. 64 and 65.

[0615] The GW pattern of FIG. 116 can achieve a particularly good error rate by applying it to a combination of, for example, the Type B code of r=7 / 16 of FIG. 36, 256QAM, and 256QAM-UC of FIG. 64 and FIG. 65.

[0616] The GW pattern in FIG. 117 can achieve a particularly good error rate by applying it to a combination of the new type B code with r=9 / 16 in FIG. 52, 256QAM, and 256QAM-UC in FIGS. 64 and 65, for example.

[0617] The GW pattern of FIG. 118 can achieve a particularly good error rate by applying it to a combination of, for example, the Type B code of r=11 / 16 of FIG. 40, 256QAM, and 256QAM-UC of FIG. 64 and FIG. 65.

[0618] The GW pattern in FIG. 119 can achieve a particularly good error rate by applying it to a combination of, for example, the Type B code of r=13 / 16 in FIG. 42, 256QAM, and 256QAM-UC in FIGS. 64 and 65.

[0619] The GW pattern in FIG. 120 can achieve a particularly good error rate by applying it to a combination of, for example, the type A code of r=2 / 16 in FIG. 30, 256QAM, and 256QAM-2D-NUC in FIG. 72 and FIG. 73.

[0620] The GW pattern in FIG. 121 can achieve a particularly good error rate by applying it to a combination of the new type A code with r=4 / 16 in FIG. 50, 256QAM, and 256QAM-2D-NUC in FIGS. 72 and 73.

[0621] The GW pattern in FIG. 122 can achieve a particularly good error rate by applying it to a combination of, for example, the type A code of r=6 / 16 in FIG. 34, 256QAM, and 256QAM-2D-NUC in FIG. 72 and FIG. 73.

[0622] The GW pattern in FIG. 123 can achieve a particularly good error rate by applying it to a combination of, for example, the type B code of r=8 / 16 in FIG. 37, 256QAM, and 256QAM-2D-NUC in FIG. 72 and FIG. 73.

[0623] The GW pattern in FIG. 124 can achieve a particularly good error rate by applying it to a combination of, for example, the Type B code of r=10 / 16 in FIG. 39, 256QAM, and 256QAM-2D-NUC in FIG. 72 and FIG. 73.

[0624] The GW pattern in FIG. 125 can achieve a particularly good error rate by applying it to a combination of, for example, the Type B code of r=12 / 16 in FIG. 41, 256QAM, and 256QAM-2D-NUC in FIG. 72 and FIG. 73.

[0625] The GW pattern of FIG. 126 can achieve a particularly good error rate by applying it to a combination of, for example, the type B code of r=14 / 16 of FIG. 43, 256QAM, and 256QAM-2D-NUC of FIG. 72 and FIG. 73.

[0626] <Configuration example of receiving device 12>

[0627] FIG. 127 is a block diagram showing an example of the configuration of the receiving device 12 of FIG.

[0628] The OFDM operation unit 151 receives an OFDM signal from the transmitting device 11 (FIG. 7) and performs signal processing on the OFDM signal. Data obtained by the signal processing by the OFDM operation unit 151 is supplied to a frame management unit 152.

[0629] The frame management unit 152 processes (frame interprets) frames composed of data supplied from the OFDM processing unit 151, and supplies the resulting target data signal and control data signal to frequency deinterleavers 161 and 153, respectively.

[0630] The frequency deinterleaver 153 performs frequency deinterleaving on the data from the frame management unit 152 in units of symbols, and supplies the result to a demapper 154 .

[0631] The demapper 154 performs orthogonal demodulation by demapping (signal point arrangement decoding) the data (constellation data) from the frequency deinterleaver 153 based on the signal point arrangement (constellation) determined by the orthogonal modulation performed on the transmitting device 11 side, and supplies the resulting data (LDPC code (likelihood)) to an LDPC decoder 155.

[0632] The LDPC decoder 155 (decoding unit) performs LDPC decoding on the LDPC code from the demapper 154, and supplies the resulting LDPC target data (here, a BCH code) to a BCH decoder 156.

[0633] The BCH decoder 156 performs BCH decoding on the LDPC target data from the LDPC decoder 155, and outputs the resulting control data (signaling).

[0634] On the other hand, the frequency deinterleaver 161 performs frequency deinterleaving on the data from the frame management unit 152 in units of symbols, and supplies the result to a SISO / MISO decoder 162 .

[0635] The SISO / MISO decoder 162 performs space-time decoding on the data from the frequency deinterleaver 161 and supplies the decoded data to a time deinterleaver 163 .

[0636] The time deinterleaver 163 performs time deinterleaving on the data from the SISO / MISO decoder 162 on a symbol-by-symbol basis, and supplies the result to a demapper 164 .

[0637] The demapper 164 performs orthogonal demodulation by demapping (signal point arrangement decoding) the data (constellation data) from the time deinterleaver 163 based on the signal point arrangement (constellation) determined by the orthogonal modulation performed on the transmitting device 11 side, and supplies the resulting data to a bit deinterleaver 165.

[0638] The bit deinterleaver 165 performs bit deinterleaving on the data from the demapper 164, and supplies the LDPC code (the likelihood of the LDPC code), which is the bit deinterleaved data, to the LDPC decoder 166.

[0639] The LDPC decoder 166 performs LDPC decoding on the LDPC code from the bit deinterleaver 165, and supplies the resulting LDPC target data (here, a BCH code) to a BCH decoder 167.

[0640] The BCH decoder 167 performs BCH decoding on the LDPC target data from the LDPC decoder 155 , and supplies the resulting data to a BB descrambler 168 .

[0641] The BB descrambler 168 performs BB descrambling on the data from the BCH decoder 167 and supplies the resulting data to a null deletion unit (Null Deletion) 169 .

[0642] The null deletion unit 169 deletes the nulls inserted by the padder 112 in FIG. 8 from the data from the BB descrambler 168 and supplies the data to a demultiplexer 170.

[0643] The demultiplexer 170 separates one or more streams (target data) multiplexed into the data from the null deletion unit 169, performs necessary processing on the separated data, and outputs the separated data as an output stream.

[0644] The receiving device 12 can be configured without some of the blocks shown in Fig. 127. That is, for example, when the transmitting device 11 (Fig. 8) is configured without the time interleaver 118, the SISO / MISO encoder 119, the frequency interleaver 120, and the frequency interleaver 124, the receiving device 12 can be configured without the time deinterleaver 163, the SISO / MISO decoder 162, the frequency deinterleaver 161, and the frequency deinterleaver 153, which are blocks corresponding to the time interleaver 118, the SISO / MISO encoder 119, the frequency interleaver 120, and the frequency interleaver 124 of the transmitting device 11, respectively.

[0645] <Example of the configuration of the bit deinterleaver 165>

[0646] FIG. 128 is a block diagram showing an example of the configuration of the bit deinterleaver 165 of FIG.

[0647] The bit deinterleaver 165 is made up of a block deinterleaver 54 and a group-wise deinterleaver 55, and performs (bit) deinterleaving of the symbol bits of the symbols that are the data from the demapper 164 (FIG. 127).

[0648] That is, the block deinterleaver 54 performs block deinterleaving (the inverse process of block interleaving) corresponding to the block interleaving performed by the block interleaver 25 in FIG. 9 on the symbol bits of the symbols from the demapper 164, that is, block deinterleaving that returns the positions of the code bits (of the likelihoods) of the LDPC code rearranged by the block interleaving to their original positions, and supplies the resulting LDPC code to the group-wise deinterleaver 55.

[0649] The group-wise deinterleaver 55 performs group-wise deinterleaving (the inverse process of group-wise interleaving) on ​​the LDPC code from the block deinterleaver 54, which corresponds to the group-wise interleaving performed by the group-wise interleaver 24 in FIG. 9. In other words, the group-wise deinterleaver 55 performs group-wise deinterleaving to return the code bits of the LDPC code, whose order has been changed on a bit group basis by the group-wise interleaving described in FIG. 81, to their original order by rearranging them on a bit group basis.

[0650] Here, when the LDPC code supplied from the demapper 164 to the bit deinterleaver 165 has been subjected to parity interleaving, group-wise interleaving, and block interleaving, the bit deinterleaver 165 can perform all of the following: parity deinterleaving corresponding to parity interleaving (the inverse process of parity interleaving, i.e., parity deinterleaving that returns the code bits of the LDPC code whose order has been changed by parity interleaving to their original order), block deinterleaving corresponding to block interleaving, and group-wise deinterleaving corresponding to group-wise interleaving.

[0651] However, in bit deinterleaver 165 of FIG. 128, a block deinterleaver 54 that performs block deinterleaving corresponding to block interleaving, and a group-wise deinterleaver 55 that performs group-wise deinterleaving corresponding to group-wise interleaving are provided, but a block that performs parity deinterleaving corresponding to parity interleaving is not provided, and parity deinterleaving is not performed.

[0652] Therefore, the LDPC decoder 166 is supplied with an LDPC code that has been subjected to block deinterleaving and group-wise deinterleaving but not parity deinterleaving from the bit deinterleaver 165 (the group-wise deinterleaver 55 thereof).

[0653] The LDPC decoder 166 performs LDPC decoding of the LDPC code from the bit deinterleaver 165 based on a transformed parity check matrix obtained by performing at least column permutation equivalent to parity interleaving on the type B parity check matrix H used for LDPC encoding by the LDPC encoder 115 in FIG. 8, or a transformed parity check matrix (FIG. 29) obtained by performing row permutation on the type A parity check matrix (FIG. 27), and outputs the data obtained as a result of the decoding of the LDPC target data.

[0654] FIG. 129 is a flowchart explaining the processing performed by the demapper 164, the bit deinterleaver 165, and the LDPC decoder 166 in FIG.

[0655] In step S111, the demapper 164 demaps and orthogonally demodulates the data from the time deinterleaver 163 (data on the constellation mapped to signal points), and supplies the data to the bit deinterleaver 165, and the process proceeds to step S112.

[0656] In step S112, the bit deinterleaver 165 deinterleaves (bit deinterleaves) the data from the demapper 164, and the process proceeds to step S113.

[0657] That is, in step S112, in the bit deinterleaver 165, the block deinterleaver 54 performs block deinterleaving on the data (symbols) from the demapper 164, and supplies the resulting code bits of the LDPC code to the group-wise deinterleaver 55.

[0658] The group-wise deinterleaver 55 performs group-wise deinterleaving on the LDPC code from the block deinterleaver 54, and supplies the LDPC code (the likelihood of the LDPC code) obtained as a result to the LDPC decoder 166.

[0659] In step S113, the LDPC decoder 166 performs LDPC decoding of the LDPC code from the group-wise deinterleaver 55 based on the check matrix H used for LDPC encoding by the LDPC encoder 115 of FIG. 8, that is, based on a converted check matrix obtained from the check matrix H, for example, and outputs the data obtained as a result to the BCH decoder 167 as the decoded result of the LDPC target data.

[0660] In addition, in FIG. 128, as in the case of FIG. 9, for ease of explanation, the block deinterleaver 54 that performs block deinterleaving and the group-wise deinterleaver 55 that performs group-wise deinterleaving are configured separately, but the block deinterleaver 54 and the group-wise deinterleaver 55 can be configured as an integrated unit.

[0661] Furthermore, in the case where group-wise interleaving is not performed in transmitting device 11, receiving device 12 can be configured without providing group-wise deinterleaver 55 that performs group-wise deinterleaving.

[0662] <LDPC Decoding>

[0663] The LDPC decoding performed by the LDPC decoder 166 in FIG. 127 will be further described.

[0664] In the LDPC decoder 166 in FIG. 127, as described above, block deinterleaving and group-wise deinterleaving are performed on the LDPC code from the group-wise deinterleaver 55, and LDPC decoding of the LDPC code without parity deinterleaving is performed on the type B check matrix H used by the LDPC encoder 115 in FIG. 8 for LDPC encoding. It is performed using a transformed check matrix obtained by performing at least column permutation corresponding to parity deinterleaving on the check matrix H, or a transformed check matrix (FIG. 29) obtained by performing row permutation on the type A check matrix (FIG. 27).

[0665] Here, LDPC decoding using a transformed check matrix has been previously proposed (see, for example, Patent No. 4224777), which can suppress the circuit scale and keep the operating frequency within a sufficiently achievable range.

[0666] Therefore, first, with reference to FIGS. 130 to 133, the previously proposed LDPC decoding using a transformed check matrix will be described.

[0667] FIG. 130 is a diagram showing an example of the check matrix H of an LDPC code with a code length N of 90 and a coding rate of 2 / 3.

[0668] In FIG. 130 (similarly in FIGS. 131 and 132 to be described later), 0 is represented by a period (.).

[0669] In the check matrix H of FIG. 130, the parity matrix has a staircase structure.

[0670] FIG. 131 is a diagram showing the check matrix H' obtained by performing the row permutation of Equation (11) and the column permutation of Equation (12) on the check matrix H of FIG. 130.

[0671] Line replacement: 6s+t+1st line → 5t+s+1st line (11)

[0672] Column replacement: 6x+y+61st column → 5y+x+61st column (12)

[0673] In formulas (11) and (12), s, t, x, and y are integers in the ranges of 0≦s<5, 0≦t<6, 0≦x<5, and 0≦t<6, respectively.

[0674] According to the row permutation of equation (11), lines 1, 7, 13, 19, and 25, which have a remainder of 1 when divided by 6, are permuted into lines 1, 2, 3, 4, and 5, respectively; lines 2, 8, 14, 20, and 26, which have a remainder of 2 when divided by 6, are permuted into lines 6, 7, 8, 9, and 10, respectively.

[0675] Furthermore, according to the column permutation in equation (12), for columns 61 and onwards (parity matrix), columns 61, 67, 73, 79, and 85, which have a remainder of 1 when divided by 6, are permuted into columns 61, 62, 63, 64, and 65, respectively, and columns 62, 68, 74, 80, and 86, which have a remainder of 2 when divided by 6, are permuted into columns 66, 67, 68, 69, and 70, respectively.

[0676] In this manner, the matrix obtained by permuting rows and columns on the parity check matrix H in FIG. 130 is the parity check matrix H' in FIG.

[0677] Here, even if row permutation is performed on the check matrix H, the arrangement of the code bits of the LDPC code is not affected.

[0678] In addition, the column permutation in equation (12) corresponds to the above-mentioned parity interleaving in which the K+qx+y+1th code bit is interleaved at the K+Py+x+1th code bit position, where the information length K is 60, the parallel factor P is 5, and the divisor q (=M / P) of the parity length M (here, 30) is 6.

[0679] Therefore, the check matrix H' in Figure 131 is a transformed check matrix obtained by at least performing column permutation to replace the K+qx+y+1th column of the check matrix H in Figure 130 (hereinafter referred to as the original check matrix, as appropriate) with the K+Py+x+1th column.

[0680] For the converted parity check matrix H' in FIG. 131, when the LDPC code of the original parity check matrix H in FIG. 130 is multiplied by the same permutation as in equation (12), a zero vector is output. In other words, if the row vector c obtained by performing the column permutation in equation (12) on the row vector c as the LDPC code (one codeword) of the original parity check matrix H is expressed as c', then, according to the nature of the parity check matrix, Hc T is a 0 vector, so H'c' T Naturally, this is also a zero vector.

[0681] From the above, the converted parity check matrix H' in FIG. 131 is a parity check matrix of an LDPC code c' obtained by performing column permutation of equation (12) on the LDPC code c of the original parity check matrix H.

[0682] Therefore, by performing column permutation of equation (12) on the LDPC code c of the original check matrix H, and then decoding (LDPC decoding) the LDPC code c' after the column permutation using the converted check matrix H' in FIG. 131, and then performing the inverse permutation of the column permutation of equation (12) on the decoded result, it is possible to obtain the same decoding result as when the LDPC code of the original check matrix H is decoded using that check matrix H.

[0683] FIG. 132 is a diagram showing the converted parity check matrix H' in FIG. 131, in which intervals are provided in units of a 5×5 matrix.

[0684] In FIG. 132, the conversion check matrix H' is expressed as a combination of a 5×5 (=P×P) unit matrix, which is the parallel factor P; a matrix in which one or more of the 1s in the unit matrix have become 0 (hereinafter referred to as a quasi-unit matrix, as appropriate); a matrix obtained by cyclic shifting a unit matrix or a quasi-unit matrix (hereinafter referred to as a shift matrix, as appropriate); a sum of two or more unit matrices, quasi-unit matrices, or shift matrices (hereinafter referred to as a sum matrix, as appropriate); and a 5×5 zero matrix.

[0685] It can be said that the conversion check matrix H' in Fig. 132 is composed of a 5x5 identity matrix, a quasi-identity matrix, a shift matrix, a sum matrix, and a 0 matrix. Therefore, these 5x5 matrices (identity matrix, quasi-identity matrix, shift matrix, sum matrix, and 0 matrix) constituting the conversion check matrix H' are hereinafter referred to as constituent matrices as appropriate.

[0686] To decode an LDPC code of a parity check matrix represented by a P×P configuration matrix, an architecture that simultaneously performs P check node operations and variable node operations can be used.

[0687] FIG. 133 is a block diagram showing an example of the configuration of a decoding device that performs such decoding.

[0688] That is, FIG. 133 shows an example of the configuration of a decoding device that decodes an LDPC code using a transformed check matrix H′ in FIG. 132 obtained by performing at least the column permutation of equation (12) on the original check matrix H in FIG. 130.

[0689] The decoding device of FIG. 133 includes an edge data storage memory 300 consisting of six FIFOs 3001 to 3006, a selector 301 for selecting one of the FIFOs 3001 to 3006, a check node calculation unit 302, two cyclic shift circuits 303 and 308, and 18 FIFOs 3041 to 3044. 18 The edge data storage memory 304 includes FIFOs 3041 to 3044. 18a receive data memory 306 for storing receive data, a variable node calculation unit 307, a decoded word calculation unit 309, a receive data rearrangement unit 310, and a decoded data rearrangement unit 311.

[0690] First, a method of storing data in the edge data storage memories 300 and 304 will be described.

[0691] The edge data storage memory 300 is composed of six FIFOs 3001 to 3006, the number of which is obtained by dividing the number of rows of the conversion check matrix H' in FIG. 132 (30) by the number of rows of the constituent matrix (parallel factor P) (5). y (y=1,2,...,6) consists of a number of storage areas, and each storage area can simultaneously read and write messages corresponding to five edges, which are the number of rows and columns (parallel factor P) of the configuration matrix. y The number of stages of the storage area is 9, which is the maximum number of 1s (Hamming weights) in the row direction of the conversion check matrix in FIG.

[0692] The FIFO 3001 stores data corresponding to the positions of 1 from the first row to the fifth row of the conversion check matrix H' in FIG. 132 (message v from the variable node). i) are stored in a form in which each row is packed horizontally (ignoring 0). That is, if the j-th row and i-th column are represented as (j,i), the first-stage storage area of ​​the FIFO 3001 stores data corresponding to the positions of 1 in the 5×5 unit matrix from (1,1) to (5,5) of the conversion check matrix H'. The second-stage storage area stores data corresponding to the positions of 1 in the shift matrix from (1,21) to (5,25) of the conversion check matrix H' (a shift matrix in which the 5×5 unit matrix is ​​cyclically shifted by three places to the right). Similarly, the third- to eighth-stage storage areas store data in association with the conversion check matrix H'. The ninth-stage storage area stores data corresponding to the positions of 1 in the shift matrix from (1,86) to (5,90) of the conversion check matrix H' (a shift matrix in which the 1 in the first row of the 5×5 unit matrix is ​​replaced with 0 and cyclically shifted by one place to the left).

[0693] FIFO3002 stores data corresponding to the positions of 1 from the 6th row to the 10th row of the conversion check matrix H' in FIG. 132. That is, the first-stage storage area of ​​FIFO3002 stores data corresponding to the positions of 1 in the first shift matrix constituting the sum matrix from (6,1) to (10,5) of the conversion check matrix H' (the sum matrix being the sum of the first shift matrix obtained by cyclically shifting a 5×5 unit matrix to the right by one place and the second shift matrix obtained by cyclically shifting the matrix to the right by two places). Also, the second-stage storage area stores data corresponding to the positions of 1 in the second shift matrix constituting the sum matrix from (6,1) to (10,5) of the conversion check matrix H'.

[0694] In other words, for a constituent matrix with a weight of 2 or more, when the constituent matrix is ​​expressed as a sum of a P×P unit matrix with a weight of 1, a quasi-unit matrix in which one or more of the 1 elements of the unit matrix have become 0, or a shift matrix obtained by cyclically shifting a unit matrix or a quasi-unit matrix, data corresponding to the positions of 1 in the unit matrix, quasi-unit matrix, or shift matrix with a weight of 1 (messages corresponding to branches belonging to the unit matrix, quasi-unit matrix, or shift matrix) are stored at the same address (the same FIFO among FIFOs 3001 to 3006).

[0695] Similarly, in the storage areas in the third to ninth stages, data is stored in association with the converted check matrix H'.

[0696] Similarly, FIFOs 3003 to 3006 store data in association with the conversion check matrix H'.

[0697] The edge data storage memory 304 is made up of 18 FIFOs 3041 to 3044, which are obtained by dividing the number of columns of the conversion check matrix H', 90, by the number of columns of the constituent matrix (parallel factor P), 5. 18 It is composed of FIFO304. x (x=1,2,...,18) consists of memory areas of multiple stages, and the memory areas of each stage can simultaneously read and write messages corresponding to five branches, which is the number of rows and columns of the constituent matrix (parallel factor P).

[0698] The FIFO 3041 stores data corresponding to the positions of 1 in the first to fifth columns of the conversion check matrix H′ in FIG. 132 (message u from the check node). j ) are stored in a vertically packed manner (ignoring zeros) in each column. That is, the first-stage memory area of ​​FIFO 3041 stores data corresponding to the positions of 1 in the 5×5 unit matrix from (1,1) to (5,5) of the conversion check matrix H'. The second-stage memory area stores data corresponding to the positions of 1 in the first shift matrix constituting the sum matrix from (6,1) to (10,5) of the conversion check matrix H' (the sum matrix being the sum of a first shift matrix obtained by cyclically shifting a 5×5 unit matrix to the right by one position and a second shift matrix obtained by cyclically shifting the 5×5 unit matrix to the right by two positions). The third-stage memory area stores data corresponding to the positions of 1 in the second shift matrix constituting the sum matrix from (6,1) to (10,5) of the conversion check matrix H'.

[0699] That is, for a constituent matrix with a weight of 2 or more, when the constituent matrix is ​​expressed as a sum of a P×P unit matrix with a weight of 1, a quasi-unit matrix in which one or more of the 1 elements of the unit matrix are changed to 0, or a shift matrix obtained by cyclically shifting a unit matrix or a quasi-unit matrix, data corresponding to the position of 1 in the unit matrix, quasi-unit matrix, or shift matrix with a weight of 1 (messages corresponding to branches belonging to the unit matrix, quasi-unit matrix, or shift matrix) is stored at the same address (FIFO 3041 to 3044). 18 The data is stored in the same FIFO.

[0700] Similarly, in the fourth and fifth storage areas, data is stored in association with the transformed check matrix H'. The number of storage areas in the FIFO 3041 is five, which is the maximum number of 1's (Hamming weights) in the row direction in the first to fifth columns of the transformed check matrix H'.

[0701] Similarly, the FIFOs 3042 and 3043 store data in association with the conversion check matrix H', and each has a length (number of stages) of 5. 12 Similarly, FIFO 304 stores data in association with the conversion check matrix H′, and each has a length of 3. 13 or 304 18 Similarly, data is stored in association with the converted check matrix H′, and each has a length of 2.

[0702] Next, the operation of the decoding device in FIG. 133 will be described.

[0703] The edge data storage memory 300 is composed of six FIFOs 3001 to 3006, and selects a FIFO from the FIFOs 3001 to 3006 to store data according to information (Matrix data) D312 indicating which row of the conversion check matrix H' in FIG. 132 the five messages D311 supplied from the cyclic shift circuit 308 in the previous stage belong to, and stores the five messages D311 in the selected FIFO in sequence. When reading data, the edge data storage memory 300 reads the five messages D3001 in sequence from the FIFO 3001 and supplies them to the selector 301 in the next stage. After finishing reading the messages from the FIFO 3001, the edge data storage memory 300 also reads messages in sequence from the FIFOs 3002 to 3006 and supplies them to the selector 301.

[0704] The selector 301 selects five messages from the FIFO from which data is currently being read out of the FIFOs 3001 to 3006 in accordance with the select signal D301, and supplies them to the check node calculation unit 302 as message D302.

[0705] The check node calculation unit 302 is composed of five check node calculators 3021 to 3025, and receives a message D302 (D3021 to D3025) (message v in equation (7)) supplied through the selector 301. i ) is used to perform check node calculation according to equation (7), and the five messages D303 (D3031 to D3035) obtained as a result of the check node calculation (message u in equation (7) j ) is supplied to the cyclic shift circuit 303.

[0706] The cyclic shift circuit 303 cyclically shifts the five messages D3031 to D3035 calculated by the check node calculation unit 302 based on information (Matrix data) D305 indicating how many cyclic shifts the original unit matrix (or quasi-unit matrix) in the converted parity check matrix H' that corresponds to the corresponding branch is made by, and supplies the result to the branch data storage memory 304 as a message D304.

[0707] The edge data storage memory 304 includes 18 FIFOs 3041 to 3044. 18 The FIFO for storing data is selected from FIFOs 3041 to 3044 according to information D305 indicating which row of the conversion check matrix H' the five messages D304 supplied from the previous stage cyclic shift circuit 303 belong to. 18 Then, the edge data storage memory 304 selects one of the messages D3061 from the FIFO 3041 and sequentially stores the five messages D304 in the selected FIFO. When reading data, the edge data storage memory 304 sequentially reads the five messages D3061 from the FIFO 3041 and supplies them to the next stage selector 305. After finishing reading data from the FIFO 3041, the edge data storage memory 304 sequentially reads the five messages D3061 from the FIFO 3042 to 3044. 18 , and supplies the messages to the selector 305.

[0708] The selector 305 selects one of the FIFOs 3041 to 3044 according to the select signal D307. 18 Among these, the five messages from the FIFO from which data is currently being read are selected and supplied to the variable node calculation unit 307 and the decoded word calculation unit 309 as message D308.

[0709] On the other hand, the received data rearrangement unit 310 rearranges the LDPC code D313 corresponding to the parity check matrix H in FIG. 130 received through the communication path 13 by performing column permutation of equation (12), and supplies the result as received data D314 to the received data memory 306. The received data memory 306 calculates and stores received LLRs (log-likelihood ratios) from the received data D314 supplied from the received data rearrangement unit 310, and supplies the received LLRs in groups of five to the variable node calculation unit 307 and the decoded word calculation unit 309 as received values ​​D309.

[0710] The variable node calculation unit 307 is composed of five variable node calculators 3071 to 3075, and receives a message D308 (D3081 to D3085) (message u in formula (1)) supplied through the selector 305.j ) and five received values ​​D309 (received values ​​u 0i ) to perform a variable node operation according to the formula (1), and the message D310 (D3101 to D3105) obtained as a result of the operation (message v in the formula (1) i ) to the cyclic shift circuit 308.

[0711] The cyclic shift circuit 308 cyclically shifts the messages D3101 to D3105 calculated by the variable node calculation unit 307 based on information indicating how many cyclic shifts the original unit matrix (or quasi-unit matrix) in the conversion check matrix H' that the corresponding edge is obtained by, and supplies the result to the edge data storage memory 300 as message D311.

[0712] By performing the above operations once, one decoding (variable node calculation and check node calculation) of the LDPC code can be performed. After the decoding device in Fig. 133 decodes the LDPC code a predetermined number of times, the decoded word calculation unit 309 and the decoded data rearrangement unit 311 obtain and output the final decoding result.

[0713] That is, the decoded word calculation unit 309 is composed of five decoded word calculators 3091 to 3095, and the five messages D308 (D3081 to D3085) (message u in formula (5)) output by the selector 305 are j ) and five received values ​​D309 (received values ​​u 0i ), and in the final stage of multiple decoding operations, calculates a decoding result (decoded word) based on equation (5), and supplies the resulting decoded data D315 to the decoded data rearrangement unit 311.

[0714] The decoded data rearrangement unit 311 performs the inverse permutation of the column permutation in equation (12) on the decoded data D315 supplied from the decoded word calculation unit 309, thereby rearranging the order, and outputs the result as the final decoded result D316.

[0715] As described above, by performing row permutation and / or column permutation on the parity check matrix (original parity check matrix), a P×P identity matrix, a quasi-identity matrix with one or more of its elements changed to 0, a shift matrix obtained by cyclically shifting an identity matrix or a quasi-identity matrix, a unit matrix, a quasi-identity matrix, or a sum matrix which is a sum of a plurality of shift matrices, and a combination of P×P 0 matrices, that is, a parity check matrix (transformed parity check matrix) that can be expressed by a combination of constituent matrices, it becomes possible to adopt an architecture for simultaneously performing P check node operations and variable node operations, which is a number smaller than the number of rows and columns of the parity check matrix, for decoding LDPC codes.When adopting an architecture for simultaneously performing P node operations (check node operations and variable node operations), which is a number smaller than the number of rows and columns of the parity check matrix, it is possible to suppress the operating frequency to a feasible range and perform a large number of repeated decodings, compared to the case where node operations are performed simultaneously for a number equal to the number of rows and columns of the parity check matrix.

[0716] The LDPC decoder 166 constituting the receiving device 12 in FIG. 127 performs LDPC decoding by simultaneously performing P check node operations and variable node operations, similar to the decoding device in FIG. 133, for example.

[0717] That is, for the sake of simplicity, if the parity check matrix of the LDPC code output by the LDPC encoder 115 constituting the transmitting device 11 in FIG. 8 is, for example, the parity check matrix H shown in FIG. 130 in which the parity matrix has a staircase structure, then in the parity interleaver 23 of the transmitting device 11, parity interleaving is performed to interleave the K+qx+y+1-th code bit at the K+Py+x+1-th code bit position by setting the information length K to 60, the parallel factor P to 5, and the divisor q (=M / P) of the parity length M to 6, respectively.

[0718] As described above, this parity interleaving corresponds to the column permutation in equation (12), and therefore LDPC decoder 166 does not need to perform the column permutation in equation (12).

[0719] For this reason, in the receiving device 12 of FIG. 127, as described above, an LDPC code that has not been subjected to parity deinterleaving, that is, an LDPC code in a state in which the column permutation of equation (12) has been performed, is supplied from the group-wise deinterleaver 55 to the LDPC decoder 166, and the LDPC decoder 166 performs processing similar to that of the decoding device of FIG. 133, except that the column permutation of equation (12) is not performed.

[0720] 134 is a diagram showing an example of the configuration of the LDPC decoder 166 in FIG.

[0721] In FIG. 134, LDPC decoder 166 is configured in the same manner as the decoding device in FIG. 133 except that received data rearrangement section 310 in FIG. 133 is not provided, and performs the same processing as the decoding device in FIG. 133 except that column permutation in equation (12) is not performed, so a description thereof will be omitted.

[0722] As described above, the LDPC decoder 166 can be configured without providing the received data rearrangement section 310, and therefore the size can be reduced compared to the decoding device in FIG.

[0723] In addition, in order to simplify the explanation in Figures 130 to 134, the code length N of the LDPC code is set to 90, the information length K is set to 60, the parallel factor (number of rows and columns of the constituent matrix) P is set to 5, and the divisor q (=M / P) of the parity length M is set to 6, but the code length N, information length K, parallel factor P, and divisor q (=M / P) are not limited to the values ​​mentioned above.

[0724] That is, in the transmitting device 11 of FIG. 8, the LDPC encoder 115 outputs an LDPC code having, for example, a code length N of 64800, 16200, 69120, 17280, etc., an information length K of N-Pq (=NM), a parallel factor P of 360, and a divisor q of M / P. The LDPC decoder 166 of FIG. 134 is applicable to the case where LDPC decoding is performed by simultaneously performing P check node operations and variable node operations on such an LDPC code.

[0725] Furthermore, if after LDPC decoder 166 decodes the LDPC code, the parity portion of the decoded result is not necessary and only the information bits of the decoded result are output, LDPC decoder 166 can be configured without decoded data rearrangement unit 311.

[0726] <Example of the configuration of the block deinterleaver 54>

[0727] FIG. 135 is a diagram for explaining the block deinterleaving performed in the block deinterleaver 54 in FIG.

[0728] In block deinterleaving, the reverse process of the block interleaving by the block interleaver 25 described in FIG. 79 is performed, so that the arrangement of the code bits of the LDPC code is restored to the original arrangement.

[0729] That is, in block deinterleaving, for example, similarly to block interleaving, the arrangement of the code bits of the LDPC code is restored to the original arrangement by writing and reading the LDPC code into m columns, which is equal to the number of bits m of a symbol.

[0730] However, in block deinterleaving, the LDPC codes are written in the same order as the LDPC codes are read in block interleaving, and further, in block deinterleaving, the LDPC codes are read in the same order as the LDPC codes are written in block interleaving.

[0731] That is, for part 1 of the LDPC code, as shown in Fig. 135, from the first row of all m columns, part 1 of the LDPC code, which is an m-bit symbol unit, is written in the row direction. That is, the code bits of the LDPC code, which is an m-bit symbol, are written in the row direction.

[0732] Writing of part 1 in m-bit units is performed sequentially toward the bottom row of m columns, and when writing of part 1 is completed, reading of part 1 is performed from the top of the first column unit in the column downward, toward the left to right columns, as shown in FIG. 135.

[0733] When reading up to the rightmost column is completed, as shown in FIG. 135, returning to the leftmost column, reading part 1 from the top to bottom of the second column unit of the column is performed from left to right columns, and so on in the same manner as above, reading part 1 of the LDPC code of one codeword.

[0734] When reading of part 1 of the LDPC code of one codeword is completed, for part 2, which is an m-bit symbol unit, the m-bit symbol unit is sequentially concatenated after part 1, and the symbol-unit LDPC code is thereby returned to the arrangement of code bits of the original LDPC code of one codeword (the LDPC code before block interleaving).

[0735] <Another configuration example of the bit deinterleaver 165>

[0736] FIG. 136 is a block diagram showing another example of the configuration of the bit deinterleaver 165 of FIG.

[0737] In the figure, parts corresponding to those in FIG. 128 are given the same reference numerals, and their explanations will be omitted below as appropriate.

[0738] That is, the bit deinterleaver 165 in FIG. 136 has the same configuration as that in FIG. 128, except that a parity deinterleaver 1011 is newly provided.

[0739] 136, the bit deinterleaver 165 is made up of a block deinterleaver 54, a group-wise deinterleaver 55, and a parity deinterleaver 1011, and performs bit deinterleaving of the code bits of the LDPC code from the demapper 164.

[0740] That is, the block deinterleaver 54 performs block deinterleaving (the inverse process of block interleaving) on ​​the LDPC code from the demapper 164, which corresponds to the block interleaving performed by the block interleaver 25 of the transmitting device 11, i.e., block deinterleaving that returns the positions of the code bits swapped by the block interleaving to their original positions, and supplies the resulting LDPC code to the group-wise deinterleaver 55.

[0741] The group-wise deinterleaver 55 performs group-wise deinterleaving on the LDPC code from the block deinterleaver 54, which corresponds to the group-wise interleaving as rearrangement processing performed by the group-wise interleaver 24 of the transmission device 11.

[0742] The LDPC code resulting from the group-wise deinterleaving is supplied from the group-wise deinterleaver 55 to a parity deinterleaver 1011 .

[0743] The parity deinterleaver 1011 performs parity deinterleaving (the inverse process of parity interleaving) on ​​the code bits after group-wise deinterleaving in the group-wise deinterleaver 55, which corresponds to the parity interleaving performed by the parity interleaver 23 of the transmitting device 11, i.e., parity deinterleaving that returns the code bits of the LDPC code whose order has been changed by the parity interleaving to their original order.

[0744] The LDPC code obtained as a result of the parity deinterleaving is supplied from the parity deinterleaver 1011 to the LDPC decoder 166 .

[0745] Therefore, in the bit deinterleaver 165 of FIG. 136, an LDPC code that has been block deinterleaved, group-wise deinterleaved, and parity deinterleaved, that is, an LDPC code obtained by LDPC encoding in accordance with the parity check matrix H, is supplied to the LDPC decoder 166.

[0746] The LDPC decoder 166 performs LDPC decoding of the LDPC code from the bit deinterleaver 165 by using the parity check matrix H used by the LDPC encoder 115 of the transmission device 11 for LDPC encoding.

[0747] That is, for the Type B method, the LDPC decoder 166 performs LDPC decoding of the LDPC code from the bit deinterleaver 165 using the parity check matrix H (of the Type B method) that the LDPC encoder 115 of the transmitting device 11 used for LDPC encoding, or using a transformed parity check matrix obtained by performing at least column permutation equivalent to parity interleaving on the parity check matrix H. Also, for the Type A method, the LDPC decoder 166 performs LDPC decoding of the LDPC code from the bit deinterleaver 165 using a parity check matrix (FIG. 28) obtained by performing column permutation on the parity check matrix (FIG. 27) (of the Type A method) that the LDPC encoder 115 of the transmitting device 11 used for LDPC encoding, or a transformed parity check matrix (FIG. 29) obtained by performing row permutation on the parity check matrix (FIG. 27) used for LDPC encoding.

[0748] 136, an LDPC code obtained by LDPC encoding according to check matrix H is supplied from (parity deinterleaver 1011 of) bit deinterleaver 165 to LDPC decoder 166. In this case, when LDPC decoding of the LDPC code is performed using check matrix H of the type B method itself used for LDPC encoding by LDPC encoder 115 of transmitting device 11, or a check matrix (FIG. 28) obtained by applying column permutation to the check matrix of the type A method (FIG. 27) used for LDPC encoding, LDPC decoder 166 can be configured, for example, as a decoding device that performs LDPC decoding by a full serial decoding method in which calculations of messages (check node messages, variable node messages) are performed sequentially for each node, or as a decoding device that performs LDPC decoding by a full parallel decoding method in which calculations of messages are performed simultaneously (in parallel) for all nodes.

[0749] Furthermore, in the LDPC decoder 166, when LDPC decoding of the LDPC code is performed using a transformed check matrix obtained by performing at least column permutation equivalent to parity interleaving on the check matrix H of the Type B method used for LDPC encoding by the LDPC encoder 115 of the transmitting device 11, or a transformed check matrix (FIG. 29) obtained by performing row permutation on the check matrix H of the Type A method used for LDPC encoding (FIG. 27), the LDPC decoder 166 is a decoding device with an architecture that simultaneously performs P (or a divisor of P other than 1) check node operations and variable node operations, and can be configured as a decoding device (FIG. 133) having a received data rearrangement unit 310 that rearranges the code bits of the LDPC code by performing column permutation similar to the column permutation (parity interleaving) for obtaining the transformed check matrix on the LDPC code.

[0750] In FIG. 136, for ease of explanation, the block deinterleaver 54 that performs block deinterleaving, the group-wise deinterleaver 55 that performs group-wise deinterleaving, and the parity deinterleaver 1011 that performs parity deinterleaving are each configured separately, but two or more of the block deinterleaver 54, group-wise deinterleaver 55, and parity deinterleaver 1011 can be configured integrally, similar to the parity interleaver 23, group-wise interleaver 24, and block interleaver 25 of the transmitting device 11.

[0751] <Example of receiving system configuration>

[0752] FIG. 137 is a block diagram showing a first example configuration of a receiving system to which the receiving device 12 can be applied.

[0753] In FIG. 137, the receiving system includes an acquisition unit 1101, a transmission path decoding unit 1102, and an information source decoding unit 1103.

[0754] The acquisition unit 1101 acquires a signal including an LDPC code obtained by LDPC encoding at least LDPC target data such as image data and audio data of a program via a transmission path (communication path) not shown, such as terrestrial digital broadcasting, satellite digital broadcasting, a CATV network, the Internet, or other networks, and supplies the signal to a transmission path decoding processing unit 1102.

[0755] Here, when the signal acquired by the acquisition unit 1101 is broadcast from a broadcast station via terrestrial waves, satellite waves, a CATV (Cable Television) network, etc., the acquisition unit 1101 is configured with a tuner, an STB (Set Top Box), etc. When the signal acquired by the acquisition unit 1101 is transmitted by multicast from a web server, such as IPTV (Internet Protocol Television), the acquisition unit 1101 is configured with a network I / F (Interface) such as a NIC (Network Interface Card).

[0756] The transmission path decoding processing unit 1102 corresponds to the receiving device 12. The transmission path decoding processing unit 1102 performs a transmission path decoding process including at least a process of correcting an error occurring in the transmission path on the signal acquired by the acquisition unit 1101 via the transmission path, and supplies the resulting signal to the information source decoding processing unit 1103.

[0757] In other words, the signal acquired by the acquisition unit 1101 via the transmission path is a signal obtained by at least performing error correction coding to correct errors that occur on the transmission path, and the transmission path decoding processing unit 1102 performs transmission path decoding processing such as error correction processing on such a signal.

[0758] Here, examples of error correction coding include LDPC coding, BCH coding, etc. Here, at least LDPC coding is performed as the error correction coding.

[0759] Furthermore, the transmission path decoding process may include demodulation of a modulated signal.

[0760] The information source decoding unit 1103 performs information source decoding on the signal that has been subjected to the transmission channel decoding process, which includes at least a process of expanding compressed information to the original information.

[0761] In other words, the signal acquired by the acquisition unit 1101 via the transmission path may have been subjected to compression encoding, which compresses the information in order to reduce the amount of data such as images and audio.In this case, the information source decoding processing unit 1103 performs information source decoding processing, such as a process of expanding the compressed information to the original information (decompression processing), on the signal that has been subjected to transmission path decoding processing.

[0762] In addition, if the signal acquired by the acquisition unit 1101 via the transmission path has not been compression-encoded, the information source decoding processing unit 1103 does not perform processing to expand the compressed information to the original information.

[0763] Here, the decompression process includes, for example, MPEG decoding, etc. In addition, the transmission path decoding process may include descrambling and the like in addition to the decompression process.

[0764] In the receiving system configured as described above, in the acquisition unit 1101, for example, data such as images and audio are subjected to compression encoding such as MPEG encoding, and the signal that has been further subjected to error correction encoding such as LDPC encoding is acquired via the transmission path and supplied to the transmission path decoding processing unit 1102.

[0765] In the transmission path decoding processing unit 1102, the signal from the acquisition unit 1101 is subjected to transmission path decoding processing, such as processing similar to that performed by the receiving device 12, and the resulting signal is supplied to the information source decoding processing unit 1103.

[0766] The information source decoding processor 1103 performs information source decoding such as MPEG decoding on the signal from the transmission path decoding processor 1102, and outputs the resulting image or sound.

[0767] The receiving system of FIG. 137 as described above can be applied to, for example, a television tuner that receives television broadcasts as digital broadcasts.

[0768] In addition, the acquisition unit 1101, the transmission path decoding processing unit 1102, and the information source decoding processing unit 1103 can each be configured as a single independent device (hardware (IC (Integrated Circuit) etc.) or software module).

[0769] In addition, with regard to the acquisition unit 1101, the transmission path decoding processing unit 1102, and the information source decoding processing unit 1103, it is possible to configure a set of the acquisition unit 1101 and the transmission path decoding processing unit 1102, a set of the transmission path decoding processing unit 1102 and the information source decoding processing unit 1103, or a set of the acquisition unit 1101, the transmission path decoding processing unit 1102, and the information source decoding processing unit 1103 as a single independent device.

[0770] FIG. 138 is a block diagram showing a second example configuration of a receiving system to which the receiving device 12 can be applied.

[0771] In the figure, parts corresponding to those in FIG. 137 are given the same symbols, and their explanations will be omitted below as appropriate.

[0772] The receiving system of Figure 138 is similar to that of Figure 137 in that it has an acquisition unit 1101, a transmission path decoding processing unit 1102, and an information source decoding processing unit 1103, but differs from that of Figure 137 in that an output unit 1111 is newly provided.

[0773] The output unit 1111 is, for example, a display device that displays an image or a speaker that outputs sound, and outputs images, sound, and the like as signals output from the information source decoding processing unit 1103. That is, the output unit 1111 displays an image or outputs sound.

[0774] The receiving system in FIG. 138 as described above can be applied to, for example, a TV (television receiver) that receives television broadcasts as digital broadcasts, a radio receiver that receives radio broadcasts, and the like.

[0775] If the signal acquired by the acquisition unit 1101 has not been subjected to compression encoding, the signal output by the transmission path decoding processing unit 1102 is supplied to the output unit 1111 .

[0776] FIG. 139 is a block diagram showing a third example configuration of a receiving system to which the receiving device 12 can be applied.

[0777] In the figure, parts corresponding to those in FIG. 137 are given the same symbols, and their explanations will be omitted below as appropriate.

[0778] The receiving system in FIG. 139 is common to the case in FIG. 137 in that it includes an acquisition unit 1101 and a transmission path decoding processing unit 1102.

[0779] However, the receiving system in FIG. 139 differs from that in FIG. 137 in that the information source decoding processing unit 1103 is not provided and a recording unit 1121 is newly provided.

[0780] The recording unit 1121 records (stores) the signal (for example, TS packets of MPEG TS) output by the transmission path decoding processing unit 1102 in a recording (storage) medium such as an optical disk, a hard disk (magnetic disk), or a flash memory.

[0781] The receiving system of FIG. 139 as described above can be applied to a recorder for recording television broadcasts.

[0782] In addition, in FIG. 139, the receiving system is configured to include an information source decoding processing unit 1103, and the signal after information source decoding processing has been performed by the information source decoding processing unit 1103, i.e., the image and audio obtained by decoding, can be recorded in a recording unit 1121.

[0783] <An embodiment of the computer>

[0784] Next, the above-mentioned series of processes can be performed by hardware or software. When the series of processes is performed by software, a program constituting the software is installed in a general-purpose computer or the like.

[0785] FIG. 140 shows an example of the configuration of an embodiment of a computer in which a program for executing the series of processes described above is installed.

[0786] The program can be recorded in advance on the hard disk 705 or ROM 703 as a recording medium built into the computer.

[0787] Alternatively, the program can be temporarily or permanently stored (recorded) in a removable recording medium 711 such as a flexible disk, a CD-ROM (Compact Disc Read Only Memory), an MO (Magneto Optical) disk, a DVD (Digital Versatile Disc), a magnetic disk, a semiconductor memory, etc. Such a removable recording medium 711 can be provided as a so-called package software.

[0788] In addition to being installed in a computer from the removable recording medium 711 as described above, the program can also be transferred wirelessly to a computer from a download site via an artificial satellite for digital satellite broadcasting, or transferred to a computer by wire via a network such as a LAN (Local Area Network) or the Internet, and the computer can receive the program transferred in this manner via communication unit 708 and install it in its built-in hard disk 705.

[0789] The computer includes a CPU (Central Processing Unit) 702. An input / output interface 710 is connected to the CPU 702 via a bus 701. When a command is input to the CPU 702 via the input / output interface 710 by a user operating an input unit 707 including a keyboard, a mouse, a microphone, etc., the CPU 702 executes a program stored in a ROM (Read Only Memory) 703 in accordance with the command. Alternatively, the CPU 702 loads into a RAM (Random Access Memory) 704 a program stored in a hard disk 705, a program transferred from a satellite or a network, received by a communication unit 708, and installed in the hard disk 705, or a program read from a removable recording medium 711 mounted on a drive 709 and installed in the hard disk 705. As a result, the CPU 702 executes the process according to the above-mentioned flowchart or the process performed by the configuration of the above-mentioned block diagram. Then, the CPU 702 outputs the processing results from an output unit 706 consisting of an LCD (Liquid Crystal Display) and a speaker, etc., via an input / output interface 710, or transmits the results from a communication unit 708, or even records the results on a hard disk 705, as necessary.

[0790] Here, in this specification, the processing steps that describe a program for causing a computer to perform various processes do not necessarily have to be processed chronologically in the order described in the flowchart, but also include processes that are executed in parallel or individually (for example, parallel processing or processing by objects).

[0791] The program may be processed by one computer, or may be distributed among multiple computers, and may be transferred to a remote computer for execution.

[0792] The embodiments of the present technology are not limited to the above-described embodiments, and various modifications are possible without departing from the gist of the present technology.

[0793] For example, the above-mentioned new LDPC code (its check matrix initial value table) and GW pattern can be used for satellite lines, terrestrial waves, cables (wired lines), and other communication paths 13 (FIG. 7). Furthermore, the new LDPC code and GW pattern can be used for data transmission other than digital broadcasting.

[0794] In addition, in this specification, for the sake of easy understanding of the description, it is assumed that the LDPC encoder 115 (FIG. 8) performs encoding into an LDPC code based on a check matrix, but the check matrix and the check matrix initial value table are equivalent information, and encoding into an LDPC code based on a check matrix includes encoding into an LDPC code based on a check matrix initial value table. Similarly, in the LDPC decoder 166 (FIG. 127), decoding into an LDPC code based on a check matrix includes decoding into an LDPC code based on a check matrix initial value table.

[0795] It should be noted that the effects described in this specification are merely examples and are not limiting, and other effects may also be obtained. [Explanation of symbols]

[0796] 11 transmitter, 12 receiver, 23 parity interleaver, 24 group-wise interleaver, 25 block interleaver, 54 block deinterleaver, 55 group-wise deinterleaver, 111 mode adaptation / multiplexer, 112 padder, 113 BB scrambler, 114 BCH encoder, 115 LDPC encoder, 116 bit interleaver, 117 mapper, 118 time interleaver, 119 SISO / MISO encoder, 120 frequency interleaver, 121 BCH encoder, 122 LDPC encoder, 123 mapper, 124 frequency interleaver, 131 frame builder / resource allocation unit, 132 OFDM generator, 151 OFDM processor, 152 frame manager, 153 frequency deinterleaver, 154 Demapper, 155 LDPC decoder, 156 BCH decoder, 161 Frequency deinterleaver, 162 SISO / MISO decoder, 163 Time deinterleaver, 164 Demapper, 165 Bit deinterleaver, 166 LDPC decoder, 167 BCH decoder, 168 BB descrambler, 169 Null deletion unit, 170 Demultiplexer, 300 Edge data storage memory, 301 Selector, 302 Check node calculation unit, 303 Cyclic shift circuit, 304 Edge data storage memory, 305 Selector, 306 Received data memory, 307 Variable node calculation unit, 308 Cyclic shift circuit, 309 Decoded word calculation unit, 310 Received data rearrangement unit, 311 Decoded data rearrangement unit, 601 Encoding unit, 602 storage unit, 611 coding rate setting unit, 612 initial value table reading unit, 613 check matrix generation unit, 614 information bit reading unit, 615 coding parity calculation unit, 616 control unit, 701 bus, 702 CPU, 703 ROM, 704 RAM, 705 hard disk, 706 output unit, 707 input unit, 708 communication unit, 709 drive, 710 input / output interface, 711, removable recording medium, 1001 reverse exchange unit, 1002 memory,1011 parity deinterleaver, 1101 acquisition unit, 1101 transmission path decoding processing unit, 1103 information source decoding processing unit, 1111 output unit, 1121 recording unit,

Claims

1. A coding step of performing LDPC coding based on a check matrix of an LDPC code having a code length N of 17280 bits and a coding rate r of 9 / 16; a group-wise interleaving step of performing group-wise interleaving on the LDPC code in units of 360-bit bit groups; a mapping step of mapping the LDPC code to one of four signal points of QPSK (Quadrature Phase Shift Keying) in units of 2 bits; Including, In the group-wise interleaving, the (i+1)th bit group from the beginning of the LDPC code is defined as bit group i, and the sequence of bit groups 0 to 47 of the 17280-bit LDPC code is defined as bit group 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Interleaved in the sequence of The LDPC code includes information bits and parity bits, the check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the information matrix section is represented by a parity check matrix initial value table; The parity check matrix initial value table is a table representing the position of an element of 1 in the information matrix section for every 360 columns, 42 549 1187 1203 1694 1741 2290 2776 2839 2886 3435 3503 3697 4031 4580 4627 5176 5223 5539 5772 6368 6917 6964 7513 13 192 415 563 699 934 1176 1484 1855 2426 3147 3369 3389 4068 4380 4578 4618 4937 4989 5381 5910 6281 6831 7202 1319 1687 2423 3518 3737 4273 5242 6209 6535 6966 7397 1273 2244 2896 3018 3949 4065 4414 4763 5461 5673 7555 344 735 1706 2320 2669 3367 3800 5112 6201 6857 7248 33 1088 1439 2013 2881 3774 3936 5447 5810 6697 7368 615 1580 2410 2698 3801 4182 4991 5483 6046 6292 6538 4564 4745 6784 550 3081 7463 950 2455 2786 1218 2118 6232 3475 4980 6548 4769 5585 6837 450 1681 3707 4038 4889 7174 1432 5762 6265 60 2951 6848 2766 3597 4872 140 2141 4243 874 4142 7054 807 2368 5619 3391 6408 6657 2073 2609 6079 1558 4944 5690 276 875 4345 3273 3767 7300 2695 6102 6743 is Transmission method.

2. A coding unit that performs LDPC coding based on a check matrix of an LDPC code having a code length N of 17280 bits and a coding rate r of 9 / 16; A group-wise interleaving unit that performs group-wise interleaving to interleave the LDPC code in units of 360-bit bit groups; a mapping unit that maps the LDPC code to one of four signal points of QPSK (Quadrature Phase Shift Keying) in units of 2 bits; Including, In the group-wise interleaving, the (i+1)th bit group from the beginning of the LDPC code is defined as bit group i, and the sequence of bit groups 0 to 47 of the 17280-bit LDPC code is defined as bit group 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Interleaved in the sequence of The LDPC code includes information bits and parity bits, the check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the information matrix section is represented by a parity check matrix initial value table; The parity check matrix initial value table is a table representing the position of an element of 1 in the information matrix section for every 360 columns, 42 549 1187 1203 1694 1741 2290 2776 2839 2886 3435 3503 3697 4031 4580 4627 5176 5223 5539 5772 6368 6917 6964 7513 13 192 415 563 699 934 1176 1484 1855 2426 3147 3369 3389 4068 4380 4578 4618 4937 4989 5381 5910 6281 6831 7202 1319 1687 2423 3518 3737 4273 5242 6209 6535 6966 7397 1273 2244 2896 3018 3949 4065 4414 4763 5461 5673 7555 344 735 1706 2320 2669 3367 3800 5112 6201 6857 7248 33 1088 1439 2013 2881 3774 3936 5447 5810 6697 7368 615 1580 2410 2698 3801 4182 4991 5483 6046 6292 6538 4564 4745 6784 550 3081 7463 950 2455 2786 1218 2118 6232 3475 4980 6548 4769 5585 6837 450 1681 3707 4038 4889 7174 1432 5762 6265 60 2951 6848 2766 3597 4872 140 2141 4243 874 4142 7054 807 2368 5619 3391 6408 6657 2073 2609 6079 1558 4944 5690 276 875 4345 3273 3767 7300 2695 6102 6743 is Transmitting device.

Images