Display device and driving method thereof

Abstract

To automatically correct and optimize data output timing of a data driving section by a mutual linkage between a timing control section and the data driving section and improve driving safety and output accuracy of the data driving section.SOLUTION: A display device includes a display panel for displaying an image, a gate driving section connected to the display panel, a data driving section connected to the display panel, and a timing control section for controlling the gate driving section and the data driving section. The data driving section senses a gate signal output from the gate driving section, and data output timing is controlled on the basis of an operation of another device or a signal generated from it together with the sensed gate signal.SELECTED DRAWING: Figure 9

Description

[Technical field]

[0001] This application claims priority to Korean Patent Application No. 10-2021-0128016, filed on September 28, 2021.

[0002] The present disclosure relates to a display device and a driving method thereof. [Background technology]

[0003] With the development of information technology, the market for display devices, which are a connecting medium between users and information, is expanding. Therefore, the use of display devices such as light emitting display devices (LEDs), quantum dot display devices (QDDs), and liquid crystal display devices (LCDs) is increasing.

[0004] The display device includes a display panel including sub-pixels, a driver that outputs a driving signal for driving the display panel, and a power supply that generates power to be supplied to the display panel or the driver.

[0005] Such a display device can display an image by selecting a specific subpixel to transmit light or directly emit light when driving signals, such as scan signals and data signals, are supplied to the subpixels formed in the display panel. Summary of the Invention [Problem to be solved by the invention]

[0006] Thus, the present disclosure is directed to a display device and method of driving the same that substantially obviates one or more problems due to limitations or shortcomings in the prior art.

[0007] SUMMARY OF THE PRESENT EMBODIMENT An object of the present invention is to automatically correct and optimize the data output timing of a data driver by interlocking between a timing controller and a data driver, and to improve the driving safety and output accuracy of the data driver. [Means for solving the problem]

[0008] Additional advantages, objects, and features of the present invention are set forth in part herein, and may be realized and obtained by the structure particularly pointed out in the written description, claims, and appended drawings.

[0009] Therefore, a display device is provided that includes a display panel for displaying an image, a gate driver connected to the display panel, a data driver connected to the display panel, and a timing control unit for controlling the gate driver and the data driver, and the data driver senses a gate signal output from the gate driver and controls data output timing based on the sensed gate signal as well as the operation of other devices (e.g., other components or control units) or signals generated therefrom.

[0010] The data driver may include at least two sensing terminals connected to two points of a gate line or a dummy gate line located on the display panel to sense a gate signal output from the gate driver.

[0011] The at least two sensing terminals may be located at one outermost edge and the other outermost edge of the data driver.

[0012] The data driver may control a data output timing based on a gate start pulse and the gate signal applied to the gate driver.

[0013] The data driver may control a data output timing based on a source output enable signal and the gate signal applied to the data driver.

[0014] The data driver may have a data output timing controlled based on a data output signal and the gate signal via an interface connected between the timing controller and the data driver.

[0015] The data driver may include at least two data drivers electrically connected to each other via a delay pulse line that inputs and outputs a pulse including data output delay information of another device or itself.

[0016] The data driver may include a signal sensing unit that calculates a logic high start time, a logic high end time, and a logic high maintenance time of the gate signal based on the gate signal output from the gate driver, a gate start pulse applied to the gate driver, and a voltage that maintains the same level as the gate high of the gate signal. The logic high may be understood as a parameter (e.g., voltage) value indicating that the digital signal is 1 (on state). Thus, the logic high start time may be understood as the time when the digital signal changes to 1, the logic high end time may be understood as the time when the digital signal changes from 1, and the logic high maintenance time may be understood as the time when the logic high remains 1 (e.g., maintained at 1).

[0017] A method of driving a display device including a display panel for displaying an image, a gate driver connected to the display panel, a data driver connected to the display panel, and a timing controller for controlling the gate driver and the data driver is also provided. The method of driving the display device includes sensing a gate signal output from the gate driver, calculating a data output delay of the data driver based on the gate signal, and setting a data output timing of the data driver based on the data output delay.

[0018] The data output timing of the data driver may be controlled based on a gate start pulse and the gate signal applied to the gate driver, or based on a source output activation signal and the gate signal applied to the data driver, or based on a data output signal and the gate signal via an interface connected between the timing control unit and the data driver.

[0019] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. Effect of the Invention

[0020] The present invention has an advantage that the data output timing of the data driver can be automatically corrected and optimized by interlocking between the timing controller and the data driver. In addition, the present invention senses the gate signal through the gate line, and refers to and analyzes the operation of other devices and signals generated therefrom to control the data output timing, thereby improving the driving safety and output accuracy of the data driver. [Brief description of the drawings]

[0021] [Figure 1] FIG. 1 is a block diagram illustrating a light emitting display device. [Diagram 2] FIG. 2 is a diagram illustrating a configuration of the sub-pixel illustrated in FIG. [Figure 3a] FIG. 13 is a diagram showing an example of the arrangement of a gate-in-panel type gate driver; [Figure 3b] FIG. 13 is a diagram showing an example of the arrangement of a gate-in-panel type gate driver; [Figure 4] FIG. 2 is a diagram showing an example of the configuration of a device related to a gate-in-panel type gate driver; [Diagram 5] FIG. 2 is a diagram showing an example of the configuration of a device related to a gate-in-panel type gate driver; [Figure 6]FIG. 2 is a diagram for explaining an outline of a data output timing automatic correction method according to the first embodiment. [Figure 7] FIG. 2 is a diagram for explaining an outline of a data output timing automatic correction method according to the first embodiment. [Figure 8] FIG. 2 is a diagram for explaining an outline of a data output timing automatic correction method according to the first embodiment. [Figure 9] 4 is a diagram illustrating a configuration example of a timing controller and a data driver according to the first embodiment; [Figure 10] 10 is an internal block diagram of a first data driver shown in FIG. 9; [Figure 11] FIG. 1 is a partial configuration diagram of a large-sized light-emitting display device. [Figure 12] 12 is an exemplary diagram showing a gate signal sensed through a gate line of FIG. 11; [Figure 13] 13 is an exemplary diagram for explaining delay characteristics of a gate signal based on a part of FIG. 12. FIG. [Figure 14] FIG. 2 is a first exemplary diagram showing a configuration of a signal sensing unit; [Figure 15] FIG. 2 is a second exemplary diagram showing the configuration of the signal sensing unit; [Figure 16] FIG. 13 is a third exemplary diagram showing the configuration of the signal sensing unit. [Figure 17] FIG. 17 is a fourth exemplary diagram showing the configuration of the signal sensing unit. [Figure 18] 13 is a diagram illustrating an example of a data driver including a timing setting unit according to a second embodiment of the present invention. [Figure 19] FIG. 11 is a diagram illustrating a configuration example of a data driver according to a second embodiment of the present invention. [Figure 20] 20 is an internal block diagram of a first data driver shown in FIG. 19; [Figure 21] FIG. 1 is a partial configuration diagram of a large-sized light-emitting display device. [Figure 22] 13 is a diagram illustrating a driving method of a light emitting display device according to a second embodiment. FIG. [Figure 23] 13 is a diagram illustrating a method of driving a light emitting display device according to a third embodiment. FIG. [Figure 24] 13 is a diagram illustrating a method of driving a light emitting display device according to a fourth embodiment. FIG. [Diagram 25] 13 is a diagram illustrating an example of a data driver including a timing setting unit according to a fifth embodiment of the present invention. [Figure 26] 13 is a diagram illustrating an example of the configuration of a data driver connected by a delay pulse line according to a fifth embodiment of the present invention. FIG. [Figure 27] 27 is an internal block diagram of a first data driver shown in FIG. 26. FIG. [Figure 28] FIG. 1 is a partial configuration diagram of a large-sized light-emitting display device. [Figure 29] 13 is a diagram illustrating a method of driving a light emitting display device according to a fifth embodiment of the present invention. FIG. [Diagram 30] FIG. 13 is a diagram illustrating a method of driving a light emitting display device according to a sixth embodiment. [Diagram 31] 11 is an exemplary diagram showing a method for adjusting output timing applicable to the second, third and sixth embodiments. FIG. [Diagram 32] FIG. 13 is an exemplary diagram showing a method for adjusting output timing applicable to the fourth and sixth embodiments. [Diagram 33] FIG. 11 is an exemplary diagram showing a method for adjusting output timing applicable to the first to sixth embodiments. [Diagram 34] FIG. 13 is an exemplary diagram showing a method for adjusting output timing applicable to the fifth and sixth embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] Reference will now be made in detail to the preferred embodiments, which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used throughout the drawings to refer to the same or like parts.

[0023] The display device according to the present disclosure may be embodied in, but is not limited to, a television, a video player, a personal computer (PC), a home theater, an automotive electronic device, a smartphone, etc. The display device according to the present disclosure may be embodied in, for example, a light emitting display device (LED) (which may include an OLED display device), a quantum dot display device (QDD), a liquid crystal display device (LCD), etc. However, for convenience of explanation, the following description will be exemplified by a light emitting display device that directly emits light based on an inorganic light emitting diode or an organic light emitting diode.

[0024] FIG. 1 is a block diagram illustrating a light emitting display device, and FIG. 2 is a diagram illustrating a configuration of a subpixel of FIG.

[0025] As shown in FIGS. 1 and 2, the light emitting display device may include an image supplier 110, a timing controller 120, a gate driver 130, a data driver 140, a display panel 150, a power supplier 180, and the like.

[0026] The image supply unit (set or host system) 110 can output various driving signals together with an image data signal supplied from the outside or an image data signal stored in an internal memory. The image supply unit 110 can supply the data signal and various driving signals to the timing control unit 120.

[0027] The timing controller 120 may output a gate timing control signal GDC for controlling the operation timing of the gate driver 130, a data timing control signal DDC for controlling the operation timing of the data driver 140, and various synchronous signals (vertical synchronous signal Vsync, horizontal synchronous signal Hsync), etc. The timing controller 120 may supply a data signal DATA supplied from the image supplier 110 to the data driver 140 together with the data timing control signal DDC. The timing controller 120 may be formed in the form of an integrated circuit (IC) and mounted on a printed circuit board, but is not limited thereto.

[0028] The gate driver 130 may output a gate signal (or a scan signal) in response to a gate timing control signal GDC provided from the timing controller 120. The gate driver 130 may provide gate signals to sub-pixels included in the display panel 150 via gate lines GL1 to GLm. The gate driver 130 may be formed in an IC form or directly on the display panel 150 in a gate in panel manner, but is not limited thereto.

[0029] The data driver 140 may sample and latch the data signal DATA in response to a data timing control signal DDC etc. provided from the timing controller 120, and may convert the digital data signal into an analog data voltage based on a gamma reference voltage and output the analog data voltage. The data driver 140 may provide data voltages to sub-pixels included in the display panel 150 via the data lines DL1 to DLn. The data driver 140 may be formed in an IC form and mounted on the display panel 150 or on a printed circuit board, but is not limited thereto.

[0030] The power supply unit 180 may generate a first power supply of high potential and a second power supply of low potential based on an external input voltage supplied from the outside, and output the first power supply and the second power supply through a first power supply line EVDD and a second power supply line EVSS. The power supply unit 180 may generate and output not only the first power supply and the second power supply, but also voltages required for driving the gate driver 130 (e.g., gate voltages including a gate high voltage and a gate low voltage) and voltages required for driving the data driver 140 (drain voltages and half drain voltages).

[0031] The display panel 150 can display an image in response to driving signals including gate signals and data voltages, a first power supply, and a second power supply. Sub-pixels of the display panel 150 directly emit light. The display panel 150 can be manufactured from a rigid or flexible substrate such as glass, silicon, or polyimide. The sub-pixels that emit light can include pixels including red, green, and blue, or pixels including red, green, blue, and white.

[0032] For example, one subpixel SP may be connected to a first data line DL1, a first gate line GL1, a first power line EVDD, and a second power line EVSS, and may include a pixel circuit including a switching transistor, a driving transistor, a capacitor, an organic light emitting diode, etc. The subpixel SP used in the light emitting display directly emits light, and therefore has a complex circuit configuration. In addition, there are various compensation circuits for compensating for deterioration of the organic light emitting diode that emits light, as well as the driving transistor that supplies a driving current to the organic light emitting diode, etc. Therefore, it should be noted that the subpixel SP is illustrated in FIG. 1 in a schematic block form.

[0033] Meanwhile, in the above description, the timing control unit 120, the gate driver 130, the data driver 140, etc. are described as separate components, but depending on the implementation of the light emitting display device, one or more of the timing control unit 120, the gate driver 130, and the data driver 140 may be integrated into a single IC.

[0034] 3a and 3b are diagrams showing an example of the arrangement of a gate-in-panel type gate driver, and FIGS. 4 and 5 are diagrams showing an example of the configuration of a device related to the gate-in-panel type gate driver.

[0035] As shown in Figures 3a and 3b, the gate-in-panel type gate drivers 130a and 130b are disposed in a non-display area NA of a display panel 150. As shown in Figure 3a, the gate drivers 130a and 130b may be disposed in the left and right non-display areas NA of the display panel 150. Also, as shown in Figure 3b, the gate drivers 130a and 130b may be disposed in the top and bottom non-display areas NA of the display panel 150.

[0036] Although the gate drivers 130a and 130b are illustrated and described as being arranged in the non-display area NA located on the left / right or top / bottom of the display area AA as an example, only one may be arranged on the left, right, top or bottom.

[0037] 4, the gate driver of the gate-in-panel type may include a shift register 131 and a level shifter 135. The level shifter 135 may generate a clock signal Clks and a start signal Vst (e.g., a gate-in-panel start signal such as a gate start pulse) based on the signal and voltage output from the timing controller 120 and the power supplier 180. The clock signal Clks may be generated in the form of K phases (K is an integer equal to or greater than 2) having different phases, such as 2 phases, 4 phases, or 8 phases.

[0038] The shift register 131 operates in response to signals Clks, Vst, etc. output from the level shifter 135, and can output gate signals Gate[1] to Gate[m] that can turn on or off transistors formed in the display panel. The shift register 131 can be formed as a thin film on the display panel in a gate-in-panel manner. Therefore, 130a and 130b shown in Figures 3a and 3b can correspond to the shift register 131.

[0039] 4 and 5, the level shifter 135, unlike the shift register 131, can be formed independently in an IC form or can be included within the power supply unit 180. However, this is merely an exemplary configuration, and the present disclosure is not limited thereto.

[0040] 6 to 8 are diagrams for explaining an outline of the data output timing automatic correction method according to the first embodiment.

[0041] 6 to 8, the light emitting display device according to the present disclosure can automatically correct the data output timing of the data driver 140 by interlocking (i.e., cooperation or interaction) between the timing control unit (T-CON) 120 and the data driver (SD-IC) 140. In particular, the data driver (SD-IC) 140 senses a gate signal through a gate line and refers to and analyzes the operation of or signals generated from other devices, thereby allowing the data driver 140 to automatically control the data output timing (this will be described as follows). Here, the term "other devices" may be understood to mean other components such as a controller. For example, such other components may be at least one of the data driver 140, another data driver 140B of the display device, a timing control unit, the timing setting unit 128 of the timing control unit 120, the timing setting unit 128 of the data driver 140, or the timing control unit 145 of the data driver 140, the timing setting unit 128 of the other data driver 140B, or the timing control unit 145 of the other data driver 140B.

[0042] Although the embodiments describe the data driver sensing the gate signal and the delay of the gate signal, it is understood that the sensing may be performed by another component or IC. Thus, in some embodiments, the gate signal may be sensed by a component other than the data driver. The other component may include two sensing terminals that operate in the same manner as the data driver sensing terminals described herein. The sensing terminals are positioned to sense the gate signal at a location corresponding to the location of the data driver.

[0043] First, a gate start pulse GSP may be applied to the gate driver (GD-IC or GIP) and the data driver (SD-IC) 140 (S110). Here, the gate start pulse GSP may be implemented to be simultaneously transmitted to the gate driver (GD-IC) and the data driver (SD-IC) 140.

[0044] Then, the data driver (SD-IC) 140 can be controlled to sense a dummy gate line transmitting a dummy gate signal or a gate line transmitting a gate signal (S120). Here, the data driver (SD-IC) 140 can be implemented to sense the dummy gate line, thereby improving driving safety. This is because the dummy gate line does not induce RC deviation due to, for example, sensing line connection.

[0045] Then, the data driver (SD-IC) 140 can be controlled to calculate a data output delay based on a signal timing delay (hereinafter, referred to as a delay characteristic) using the sensed gate signal (S130).

[0046] Then, the data output timing and delay timing of the data driver (SD-IC) 140 can be set based on the data output delay (S140).

[0047] Then, the data output timing of the data driver 140 can be automatically corrected according to the set data output timing and delay timing (S150).

[0048] In the first embodiment, the timing controller (T-CON) 120 and the data driver (SD-IC) 140 are implemented as separate ICs. In this manner, when the timing controller (T-CON) 120 and the data driver (SD-IC) 140 are implemented as separate ICs, the data driver 140 can sense a gate signal transmitted through a dummy gate line transmitting a dummy gate signal or a gate line transmitting a gate signal to provide gate line driving timing information (Gate Line Timing) (i.e., timing characteristics of a gate signal, for example, TDR (T_Delay Rising), TDF (T_Delay Falling), THS (T_High Start), THE (T_High End), etc., which will be described later). The timing controller 120 can provide data output timing information for automatically correcting the data output timing of the data driver 140 based on the gate line timing information (Gate Line Timing) transmitted from the data driver 140.

[0049] This method can automatically correct the data output timing of the data driver 140. For example, the gate signal delay graph of Figure 8 shows the gate signal delay for each position of the gate line.

[0050] The first embodiment will be described in more detail below, but in the following description, a case where a data driver senses a dummy gate line to provide gate line timing information will be taken as an example.

[0051] FIG. 9 is a diagram showing an example of the configuration of a timing controller and a data driver according to the first embodiment, and FIG. 10 is an internal block diagram of the first data driver shown in FIG.

[0052] As shown in FIG. 9, the first data driver 140A and the second data driver 140B can be electrically connected to a gate start pulse line GSPL to which a gate start pulse GSP is transmitted and a gate line (or a dummy gate line) DGL to which a gate signal is transmitted.

[0053] The first data driver 140A may have sensing terminals connected to a first sensing point SENP1 of the gate line DGL and a second sensing point SENP2 spaced apart from the first sensing point SENP1, and the second data driver 140B may have sensing terminals connected to a third sensing point SENP3 of the gate line DGL and a fourth sensing point SENP4 spaced apart from the third sensing point SENP3.

[0054] As can be seen from the illustrated diagram, the data drivers 140A and 140B may receive a gate start pulse to determine the delay characteristic of the sensed gate signal, and may sense the gate signal output from the gate driver by at least two sensing terminals provided (e.g., corresponding to positions) at the left and right outermost edges, respectively. The at least two sensing terminals may be located at one and the other outermost edges (i.e., both ends) of the data drivers 140A and 140B. The left and right outermost edges may be the outermost edges of a specific data driver (e.g., the first data driving unit 140A or the second data driving unit 140B). Alternatively, at least two sensing terminals may be located at one and the other outermost edges (i.e., both ends) of the data driving units 140A and 140B. In this way, the distance between sensing points on the gate lines (or dummy gate lines) is maximized, and the sensing accuracy of the gate signal is improved.

[0055] The data drivers 140A and 140B can transmit gate line timing information, which is provided by the gate start pulse and the sensed gate signal, to the timing controller 120 via the gate line timing line GLT.

[0056] The timing control unit 120 can transmit data output timing information (Data Output Timing) provided by timing information (Gate Line Timing) to the data drivers 140A and 140B via a data output timing line DOT.

[0057] 10, the first data driver 140A may include a serial-parallel controller, a shift register, a latch, a digital converter DAC, a multi-channel output unit Multi-channel Output, a first signal sensing unit SENC1, a second signal sensing unit SENC2, a timing control unit Timing Control (also called a controller or timing control), an amplifier G / A, an analog-digital converter ADC, a sampling circuit, and a signal transmission unit TX, etc. The second data driver 140B may include the same configuration as the first data driver 140A.

[0058] The serial-parallel controller may be configured to control a shift register and a latch in order to convert a data signal applied from the outside in a serial system into a parallel system.

[0059] The shift register and the latch can be configured to convert and store a data signal applied in a serial system into a parallel system under the control of a serial-parallel controller.

[0060] The digital conversion unit DAC may convert the parallel digital data signals output from the latches Latch into analog data voltages. The multi-channel output unit Multi-channel Output may be configured to output analog data voltages to the data lines DL1 to DLn.

[0061] The timing control unit (Timing Control) may be configured to perform a function of controlling the operation timing of devices included in the first data driver 140A.

[0062] The sampling circuit unit Sample Circuit may be configured to sense and sample characteristics of elements included in the subpixels through reference lines arranged together with the data lines. The amplification unit G / A may be configured to amplify a sampling value output from the sampling circuit unit Sample Circuit. The analog-to-digital conversion unit ADC may be configured to convert an analog-type sampling value output from the amplification unit G / A into a digital-type sampling value. The signal transmission unit TX may be configured to transmit a digital-type sampling value to the timing control unit.

[0063] The amplifier G / A, analog-to-digital converter ADC, sampling circuit Sample Circuit, and signal transmission unit TX are components for compensating elements (e.g., driving transistors, organic light-emitting diodes, etc.) included in the subpixels, and may be omitted.

[0064] The first signal sensing unit SENC1 and the second signal sensing unit SENC2 may be configured to sense a gate signal through a gate line and provide and output gate line timing information. The first signal sensing unit SENC1 may sense a first point of the gate line through a first sensing terminal SENT1 connected to the first sensing line, and the second signal sensing unit SENC2 may sense a second point of the gate line through a second sensing terminal SENT2 connected to the second sensing line.

[0065] Hereinafter, a large-sized light emitting display including four data drivers and one timing controller, in which gate signals are applied to the left and right sides, will be described as an example.

[0066] FIG. 11 is a partial configuration diagram of a large light emitting display device, FIG. 12 is an example diagram showing a gate signal sensed through a gate line of FIG. 11, and FIG. 13 is an example diagram for explaining the delay characteristics of the gate signal based on a part of FIG. 12.

[0067] 11 to 13, the large-sized light emitting display device may include at least four data drivers 140A to 140D. The first and second data drivers 140A and 140B may apply data signals to a left display area based on a center line of the display panel, and the third and fourth data drivers 140C and 140D may apply data signals to a right display area based on the center line of the display panel.

[0068] The dummy gate line DGL transmitting the gate signals GateL and GateR and the gate start pulse line GSP transmitting the gate start pulse GSPL may be disposed in a display area or a non-display area of ​​the display panel.

[0069] The first to fourth data drivers 140A to 140D may be commonly connected to a gate start pulse line GSP. The first data driver 140A may sense the first side gate signal GateL from a first point and a second point of the dummy gate line DGL. The second data driver 140B may sense the first side gate signal GateL from a third point and a fourth point of the dummy gate line DGL. The third data driver 140C may sense the second side gate signal GateR from a fifth point and a sixth point of the dummy gate line DGL. The fourth data driver 140D may sense the second side gate signal GateR from a seventh point and an eighth point of the dummy gate line DGL.

[0070] To explain a part of the first data driver 140A representatively, the first signal sensing unit SENC1 may include a gate signal sensing unit 141 to which the first sensing signal SEN1 is applied, and a timing counter unit 143 to which a gate start pulse GSP is applied. The gate signal sensing unit 141 may be configured to sense a gate signal for each point on the gate line DGL. The timing counter unit 143 may be configured to count the start and end times of the gate start pulse GSP.

[0071] The dummy gate line DGL can simultaneously transmit a first side (left side) gate signal GateL output from a gate driver arranged in a first side (left side) non-display area and a second side (right side) gate signal GateR output from a gate driver arranged in a second side (right side) non-display area.

[0072] However, referring to FIG. 12 and FIG. 11 together, the delay characteristic of the gate signal may deepen (i.e., distortion or delay) from the input point [1] where the first side gate signal GateL is applied to the first point [3], the second point [4], the third point [5], and the fourth point [6]. Conversely, the delay characteristic of the gate signal may deepen from the input point [2] where the second side gate signal GateR is applied to the eighth point

[10] , the seventh point [9], the sixth point [8], and the fifth point [7]. That is, the fourth point [6], which is the furthest from the input point [1] where the first side gate signal GateL is applied, and the fifth point [7], which is the furthest from the input point [2] where the second side gate signal GateR is applied, may be the points where the delay (and / or distortion) characteristic of the gate signal deepens (i.e., becomes maximum or noticeable).

[0073] 11 to 13 together, it can be seen that the gate signal sensed from the first point [3] may exhibit a delay characteristic compared to the input point [1] where the first side gate signal GateL is applied. This may also be the case for the second side gate signal GateR applied from the opposite side of the first side gate signal GateL. The first point ([3]) is referenced here for illustrative purposes, and the same or similar delay characteristic may be present for the gate signal sensed at any other point. However, the delay characteristic sensed at other points may have a different value or magnitude.

[0074] Factors that indicate the delay characteristics of a gate signal include TDR (T_Delay Rising), TDF (T_Delay Falling), THS (T_High Start), THE (T_High End), etc. These are explained as follows.

[0075] TDR can be a factor that indicates the time it takes for the gate signal at the first point [3] to rise from logic low L to logic high H after a delay time is placed with respect to the logic high start time of the gate signal at the input point [1]. TDF can be a factor that indicates the time it takes for the gate signal at the first point [3] to fall from logic high H to logic low L after a delay time is placed with respect to the logic low start time of the gate signal at the input point [1]. THS can be a factor that indicates the logic high H start time of the gate signal at the first point [3], and THE can be a factor that indicates the logic high H end time of the gate signal at the first point [3].

[0076] In addition, TR can be a factor that indicates the time it takes for the gate signal at the first point [3] to rise from logic low L to logic high H, THW can be a factor that indicates the logic high H maintenance time (or pulse width) of the gate signal at the first point [3], and TF can be a factor that indicates the time it takes for the gate signal at the first point [3] to fall from logic high H to logic low L.

[0077] Therefore, if a gate start pulse GSP which indicates the start of output of the gate signal is applied and the gate signal Gate is sensed from multiple points, the delay characteristic of the gate signal can be known.

[0078] For this purpose, the first signal sensing unit SENC1 can be understood to include a gate signal sensing unit 141 capable of sensing a gate signal for each location and a timing counter unit 143. Thus, the first signal sensing unit SENC1 can count the start and end times of the gate start pulse GSP. And, the timing control unit 120 can be understood to include a timing setting unit 128 providing data output timing information (Data Output Timing) for automatically correcting the data output timing of the data driver 140 based on the delay characteristic of the gate signal. For example, the data output timing can be corrected based on THS and THE (or THW) or other characteristics shown in FIG. 13 showing the delay characteristic of the gate signal.

[0079] Hereinafter, various examples of a signal sensing unit (eg, the gate signal sensing unit 141 in FIG. 11) for detecting the delay characteristic of a gate signal will be described.

[0080] FIG. 14 is a first exemplary diagram showing the configuration of the signal sensing unit, FIG. 15 is a second exemplary diagram showing the configuration of the signal sensing unit, FIG. 16 is a third exemplary diagram showing the configuration of the signal sensing unit, and FIG. 17 is a fourth exemplary diagram showing the configuration of the signal sensing unit.

[0081] 14, the gate signal sensing unit 141 may include first to third comparators CMP1, CMP2, and CMP3, and the timing counter unit 143 may include first and second counter units CNT1 and CNT2. That is, each of the first and second signal sensing units SENC1 and SENC2 may be composed of three comparators and two counters.

[0082] The first comparator CMP1 may have a non-inverting terminal (+) connected to the sensing line SENL, an inverting terminal (-) connected to the reference line REFL, and an output terminal connected to a first input terminal of the first counter unit CNT1. The reference line REFL may be connected to a voltage source capable of maintaining the same level as a gate high of a gate signal. The output of the first comparator CMP1 may be used as a signal capable of generating a positive edge of a sensing line triggered. In this specification, the positive edge of a sensing line may be understood to mean a time when a signal of a sensing line transitions from a logic low to a logic high or from an off signal to an on signal.

[0083] The second comparator CMP2 may have an inverting terminal (-) connected to the sensing line SENL, a non-inverting terminal (+) connected to the reference line REFL, and an output terminal connected to a first input terminal of the second counter unit CNT2. The output of the second comparator CMP2 may be used as a signal that can generate a trigger (Negative Edge of Sensing Line Triggered) at the negative edge of the sensing line. In this specification, the negative edge of the sensing line may be understood to mean the time when the signal of the sensing line transitions from logic high to logic low or from an on signal to an off signal.

[0084] The third comparator CMP3 has an inverting terminal (-) connected to the reference line REFL, a non-inverting terminal (+) connected to the gate start pulse line GSPL, and an output terminal connected to the second input terminal of the first counter unit CNT1 and the second input terminal of the second counter unit CNT2. The output of the third comparator CMP3 can be used as a signal that can generate a trigger (Positive Edge of GSP Triggered) at the positive edge of the gate start pulse.

[0085] The first counter unit CNT1 can generate and output a signal THS indicating a logic high start time of the gate signal by starting counting based on the output of the third comparator CMP3 and stopping counting based on the output of the first comparator CMP1.

[0086] The second counter unit CNT2 starts counting based on the output of the third comparator CMP3 and stops counting based on the output of the second comparator CMP2, thereby generating and outputting a signal THE indicating the logic high end time of the gate signal.

[0087] 15, the gate signal sensing unit 141 may include first to third comparators CMP1, CMP2, and CMP3, and the timing counter units CNT1 and CNT2 may include first and second counter units CNT1 and CNT2. That is, the first and second signal sensing units SENC1 and SENC2 may be composed of three comparators and two counters.

[0088] The first comparator CMP1 may have a non-inverting terminal (+) connected to the sensing line SENL, an inverting terminal (-) connected to the reference line REFL, and an output terminal connected to a first input terminal of the first counter unit CNT1 and a second input terminal of the second counter unit CNT2. The reference line REFL may be connected to a voltage source capable of maintaining the same level as a gate high of a gate signal. The output of the first comparator CMP1 may be used as a signal capable of generating a positive edge of a sensing line triggered.

[0089] The second comparator CMP2 may have an inverting terminal (-) connected to the sensing line SENL, a non-inverting terminal (+) connected to the reference line REFL, and an output terminal connected to a first input terminal of the second counter unit CNT2. The output of the second comparator CMP2 may be used as a signal capable of generating a trigger at the negative edge of the sensing line.

[0090] The third comparator CMP3 has an inverting terminal (-) connected to the reference line REFL, a non-inverting terminal (+) connected to the gate start pulse line GSPL, and an output terminal connected to the second input terminal of the first counter unit CNT1. The output of the third comparator CMP3 can be used as a signal that can generate a trigger (Positive Edge of GSP Triggered) at the positive edge of the gate start pulse.

[0091] The first counter unit CNT1 can generate and output a signal THS indicating a logic high start time of the gate signal by starting counting based on the output of the third comparator CMP3 and stopping counting based on the output of the first comparator CMP1.

[0092] The second counter unit CNT2 starts counting based on the output of the first comparator CMP1 and stops counting based on the output of the second comparator CMP2, and can generate and output a signal THW that indicates the logic high H maintenance time (or pulse width) of the gate signal.

[0093] 16, the gate signal sensing unit 141 may include first to third comparators CMP1, CMP2, and CMP3 together with the analog-to-digital conversion unit ADC, and the timing counter units CNT1 and CNT2 may include first and second counter units CNT1 and CNT2. That is, the first and second signal sensing units SENC1 and SENC2 may be composed of one analog-to-digital conversion unit, three comparators, and two counters.

[0094] The analog-to-digital converter ADC has an input terminal connected to the sensing line SENL and an output terminal connected to a non-inverting terminal (+) of the first comparator CMP1 and an inverting terminal (-) of the second comparator CMP2. The analog-to-digital converter ADC can output 0 or 1 in response to a logic state of the gate signal.

[0095] The first comparator CMP1 may have a non-inverting terminal (+) connected to an output terminal of the analog-to-digital conversion unit ADC, an inverting terminal (-) connected to a threshold voltage line THL, and an output terminal connected to a first input terminal of the first counter unit CNT1. The threshold voltage line THL may be connected to a device capable of applying a signal equal to logic high 1. The output of the first comparator CMP1 may be used as a signal capable of generating a trigger at the positive edge of the sensing line.

[0096] The second comparator CMP2 may have an inverting terminal (-) connected to an output terminal of the analog-to-digital conversion unit ADC, a non-inverting terminal (+) connected to the threshold voltage line THL, and an output terminal connected to a first input terminal of the second counter unit CNT2. The output of the second comparator CMP2 may be used as a signal capable of generating a trigger at a negative edge of the sensing line.

[0097] The third comparator CMP3 has an inverting terminal (-) connected to the reference line REFL, a non-inverting terminal (+) connected to the gate start pulse line GSPL, and an output terminal connected to the second input terminal of the first counter unit CNT1 and the second input terminal of the second counter unit CNT2. The output of the third comparator CMP3 can be used as a signal that can generate a trigger (Positive Edge of GSP Triggered) at the positive edge of the gate start pulse.

[0098] The first counter unit CNT1 can generate and output a signal TADC obtained by digitizing the gate signal in a manner that starts counting based on the output of the third comparator CMP3 and stops counting based on the output of the first comparator CMP1.

[0099] The second counter unit CNT2 starts counting based on the output of the third comparator CMP3 and stops counting based on the output of the second comparator CMP2, thereby generating and outputting a signal THE indicating the logic high end time of the gate signal.

[0100] 17, the gate signal sensing unit 141 may include first to third comparators CMP1, CMP2, and CMP3 together with the analog-to-digital conversion unit ADC, and the timing counter units CNT1 and CNT2 may include first and second counter units CNT1 and CNT2. That is, the first and second signal sensing units SENC1 and SENC2 may be composed of one analog-to-digital conversion unit, three comparators, and two counters.

[0101] The analog-to-digital converter ADC has an input terminal connected to the sensing line SENL and an output terminal connected to a non-inverting terminal (+) of the first comparator CMP1 and an inverting terminal (-) of the second comparator CMP2. The analog-to-digital converter ADC can output 0 or 1 in response to a logic state of the gate signal.

[0102] The first comparator CMP1 may have a non-inverting terminal (+) connected to an output terminal of the analog-to-digital conversion unit ADC, an inverting terminal (-) connected to a threshold voltage line THL, and an output terminal connected to a first input terminal of the first counter unit CNT1 and a second input terminal of the second counter unit CNT2. The threshold voltage line THL may be connected to a device capable of applying a signal equal to logic high 1. The output of the first comparator CMP1 may be used as a signal capable of generating a trigger at the positive edge of the sensing line.

[0103] The second comparator CMP2 may have an inverting terminal (-) connected to an output terminal of the analog-to-digital conversion unit ADC, a non-inverting terminal (+) connected to the threshold voltage line THL, and an output terminal connected to a first input terminal of the second counter unit CNT2. The output of the second comparator CMP2 may be used as a signal capable of generating a trigger at a negative edge of the sensing line.

[0104] The third comparator CMP3 has an inverting terminal (-) connected to the reference line REFL, a non-inverting terminal (+) connected to the gate start pulse line GSPL, and an output terminal connected to the second input terminal of the first counter unit CNT1 and the second input terminal of the second counter unit CNT2. The output of the third comparator CMP3 can be used as a signal that can generate a trigger (Positive Edge of GSP Triggered) at the positive edge of the gate start pulse.

[0105] The first counter unit CNT1 can generate and output a signal TADC obtained by digitizing the gate signal in a manner that starts counting based on the output of the third comparator CMP3 and stops counting based on the output of the first comparator CMP1.

[0106] The second counter unit CNT2 starts counting based on the output of the first comparator CMP1 and stops counting based on the output of the second comparator CMP2, and can generate and output a signal THW indicating the logic high H maintenance time (or pulse width) of the gate signal.

[0107] A second embodiment including a timing setting unit for providing data output timing information within a data driver will now be described.

[0108] FIG. 18 is an example diagram showing a data driver including a timing setting unit according to a second embodiment, FIG. 19 is an example diagram showing the configuration of a data driver according to the second embodiment, FIG. 20 is an internal block diagram of the first data driver shown in FIG. 19, and FIG. 21 is a partial configuration diagram of a large light emitting display device.

[0109] As shown in Fig. 18, the data driver 140 may further include a timing setting unit (Timing Setting) for providing data output timing information for automatically correcting the data output timing of the data driver 140 based on gate line timing information transmitted from the data driver. This is different from the first embodiment in that the timing setting unit of the timing control unit 120 is used for this purpose. As shown in Fig. 19, even when the data driver 140 further includes a timing setting unit (Timing Setting), the first data driver 140A and the second data driver 140B may be electrically connected to a gate start pulse line GSPL to which a gate start pulse GSP is transmitted and a gate line (or a dummy gate line) DGL to which a gate signal is transmitted.

[0110] 20, the first data driver 140A may include a serial-parallel controller, a shift register, a latch, a digital converter DAC, a multi-channel output unit Multi-channel Output, a first signal sensing unit SENC1, a second signal sensing unit SENC2, a controller (e.g., a timing controller), an amplifier G / A, an analog-digital converter ADC, a sampling circuit, and a signal transmission unit TX, as in the first embodiment. However, unlike the first embodiment, the first data driver 140A may include a timing setting unit. In the embodiment shown in FIG. 20, the second data driver 140B may include the same configuration as the first data driver 140A.

[0111] 21, when implemented as a large-sized light emitting display device, it may include at least four data drivers 140A-140D, similar to the first embodiment. The first and second data drivers 140A and 140B may apply data signals to a left display area based on the center line of the display panel, and the third and fourth data drivers 140C and 140D may apply data signals to a right display area based on the center line of the display panel.

[0112] The first signal sensing unit SENC1 may include a gate signal sensing unit 141 to which the first sensing signal SEN1 is applied and a timing counter unit 143 to which a gate start pulse GSP is applied, similar to the first embodiment. The second signal sensing unit SENC2 may also be configured similarly to the first signal sensing unit SENC1.

[0113] Hereinafter, a method for driving the light emitting display device according to the second embodiment will be described.

[0114] FIG. 22 is a diagram for explaining a driving method of a light emitting display device according to a second embodiment. Please note that in FIG. 22, steps 1 to 10 are described in order to facilitate understanding of the flow of the driving method. However, steps 1 to 10 do not have to be performed in the described order. In addition, it is described that the timing setting unit 148 and the timing control unit 145 (also called a control unit or timing control) of the data driver perform parallel control at the same time, while the gate signal sensing unit 141 and the timing counter unit 143 perform serial control at different times, but this should be construed as an example for facilitating understanding. In other words, the control methods performed within the same configuration may be performed at the same time or at different times depending on the configuration, algorithm, reaction speed, etc. of the device.

[0115] 22, first, (1) a gate start pulse GSP can be output from the timing control unit 120. Then, (2) a first point of the gate line can be sensed through a first sensing line SENL1 ​​connected to the gate signal sensing unit 141 of the data driver. Then, (3) a second point of the gate line can be sensed through a second sensing line SENL2 connected to the gate signal sensing unit 141 of the data driver.

[0116] Then, (4) a gate start pulse GSP (e.g., gate start pulse timing) may be sensed by the timing counter unit 143 of the data driver. Then, (5) a logic high start time THS1 of the first point gate signal from the first point of the gate line may be sensed by the timing counter unit 143 of the data driver. Then, (6) a logic high start time THS2 of the second point gate signal from the second point of the gate line may be sensed by the timing counter unit 143 of the data driver. Then, (7) a logic high end time THE1 of the first point gate signal from the first point of the gate line may be sensed by the timing counter unit 143 of the data driver. Then, (8) a logic high end time THE2 of the second point gate signal from the second point of the gate line may be sensed by the timing counter unit 143 of the data driver.

[0117] Then, the (9) timing setting unit 148 of the data driver can calculate the difference between the logic high start time THS1 of the first point gate signal and the gate start pulse GSP. At the same time, the (9) timing setting unit 148 of the data driver can calculate the difference between the logic high start time THS1 of the first point gate signal and the logic high end time THE1 of the first point gate signal. At the same time, the (9) timing setting unit 148 of the data driver can divide the difference between the logic high start time THS1 of the first point gate signal and the logic high start time THS2 of the second point gate signal by the number of output channels of the data driver. At the same time, the (9) timing setting unit 148 of the data driver can calculate the difference between the logic high start time THS1 of the first point gate signal and the logic high start time THS2 of the second point gate signal. Here, the delay value according to the output channel direction of the data driver can be determined depending on whether the difference between the two values ​​is a positive number or a negative number.

[0118] Then, the timing controller 145 of the (10) data driver can control the data output start timing according to the difference between the logic high start time THS1 of the first point gate signal and the gate start pulse GSP. At the same time, the timing controller 145 of the (10) data driver can control the data output width according to the difference between the logic high start time THS1 of the first point gate signal and the logic high end time THE1 of the first point gate signal. At the same time, the timing controller 145 of the (10) data driver can control the delay value between the data output channels according to a value obtained by dividing the difference between the logic high start time THS1 of the first point gate signal and the logic high start time THS2 of the second point gate signal by the number of output channels of the data driver. At the same time, the timing controller 145 of the (10) data driver can control the delay value according to the output channel direction of the data driver according to the difference between the logic high start time THS1 of the first point gate signal and the logic high start time THS2 of the second point gate signal. For example, if the difference between the two values ​​is positive, the delay value increases, but if it is negative, the delay value decreases. Therefore, the delay value increases from point 1 [3] to point 2 [4] in Figure 21, but decreases from point 8

[10] to point 7 [9].

[0119] In the second embodiment, the method of automatically correcting the data output timing of the data driver after sensing the delay characteristic of each gate signal position by the gate start pulse GSP has been described as an example.

[0120] However, the embodiment may utilize a source output enable signal (a signal to activate the output of a data signal, SOE) output from the timing control unit 120 and applied to the data driver, instead of the gate start pulse GSP. For example, the source output enable signal (SOE) may be a signal that controls the output of the data driver to be transmitted to a pixel. Here, the output of the data driver starts at the start time of the source output enable signal (SOE), and the output width is based on the width of the source output enable signal (SOE). In addition, the present disclosure may utilize a data output signal EPI Data (hereinafter, an interface data output signal) via an interface connected between the timing control unit 120 and the data driver, instead of the gate start pulse GSP. For example, the data output signal (EPI Data) may be a signal that determines a voltage output from the data driver, and the level of the output voltage of the data driver is determined according to the interface data output signal (EPI Data). In some implementations, the source output enable signal (SOE) may be implemented as a data packet in the data output signal (EPI Data). Therefore, in the following, the third and fourth embodiments will be described taking the source output enable signal SOE or the interface data output signal EPI Data as an example.

[0121] Meanwhile, when using the source output enable signal SOE or the interface data output signal EPI Data, sensing of the gate signal or gate start pulse may be omitted. However, since sensing at least the gate signal can improve the accuracy of the output timing, the following description will be given as an example including sensing of the gate signal.

[0122] FIG. 23 is a diagram for explaining a method for driving a light emitting display device according to a third embodiment. Note that in FIG. 23 as well, steps 1 to 10 are listed in order to facilitate understanding of the flow of the driving method. Meanwhile, the third embodiment also differs from the second embodiment in that the gate start pulse GSP is replaced with a source output activation signal SOE, and therefore only those points related to this will be explained. However, steps 1 to 10 do not have to be performed in the listed order.

[0123] 23, first, (1) a source output enable signal SOE can be output from the timing control unit 120. Then, (2) a first point of the gate line can be sensed through a first sensing line SENL1 ​​connected to the gate signal sensing unit 141 of the data driver. Then, (3) a second point of the gate line can be sensed through a second sensing line SENL2 connected to the gate signal sensing unit 141 of the data driver.

[0124] Then, (4) a logic high start time THS1 of the first point gate signal from the first point of the gate line may be sensed by the timing counter unit 143 of the data driver. Then, (5) a logic high start time THS2 of the second point gate signal from the second point of the gate line may be sensed by the timing counter unit 143 of the data driver. Then, (6) a logic high end time THE1 of the first point gate signal from the first point of the gate line may be sensed by the timing counter unit 143 of the data driver. Then, (7) a logic high end time THE2 of the second point gate signal from the second point of the gate line may be sensed by the timing counter unit 143 of the data driver.

[0125] Then, the timing setting unit 148 of the (8) data driver can calculate the difference between the logic high start time THS1 of the first point gate signal and the source output enable signal SOE. At the same time, the timing setting unit 148 of the (8) data driver can correct the width of the source output enable signal SOE according to (and based on) the difference between the logic high start time THS1 of the first point gate signal and the logic high end time THE1 of the first point gate signal. At the same time, the timing setting unit 148 of the (8) data driver can divide the difference between the logic high start time THS1 of the first point gate signal and the logic high start time THS2 of the second point gate signal by the number of output channels of the data driver. At the same time, the timing setting unit 148 of the (8) data driver can calculate the difference between the logic high start time THS1 of the first point gate signal and the logic high start time THS2 of the second point gate signal.

[0126] Next, (9) the timing controller 145 of the data driver can control the data output width according to the width of the corrected source output enable signal SOE. As can be seen from this flow, when the source output enable signal SOE is used, it is not necessary to sense the gate start pulse GSP. Therefore, the data driver can omit a terminal for applying the gate start pulse GSP and a step for sensing the gate start pulse GSP.

[0127] Fig. 24 is a diagram for explaining a driving method of a light emitting display device according to a fourth embodiment. Note that in Fig. 24 as well, steps 1 to 9 are described in order to facilitate understanding of the flow of the driving method. Meanwhile, the fourth embodiment differs from the second embodiment in that the gate start pulse GSP is replaced with an interface data output signal EPI Data, and therefore only the points related to this are described. However, steps 1 to 9 do not have to be performed in the order described.

[0128] 24, first, (1) an interface data output signal EPI Data can be generated from the timing control unit 120. Then, (2) a first point of the gate line can be sensed through a first sensing line SENL1 ​​connected to the gate signal sensing unit 141 of the data driver. Then, (3) a second point of the gate line can be sensed through a second sensing line SENL2 connected to the gate signal sensing unit 141 of the data driver.

[0129] Then, (4) the timing counter unit 143 of the data driver may sense the input timing of the interface data output signal EPI Data. Then, (5) the timing counter unit 143 of the data driver may sense a logic high start time THS1 of the first point gate signal from the first point of the gate line. Then, (6) the timing counter unit 143 of the data driver may sense a logic high start time THS2 of the second point gate signal from the second point of the gate line. Then, (7) the timing counter unit 143 of the data driver may sense a logic high end time THE1 of the first point gate signal from the first point of the gate line. Then, (8) the timing counter unit 143 of the data driver may sense a logic high end time THE2 of the second point gate signal from the second point of the gate line.

[0130] Then, (9) the timing setting unit 148 of the data driver can calculate the difference between the logic high start time THS1 of the first point gate signal and the input timing of the interface data output signal EPI Data, and (10) the timing control unit 145 of the data driver can control the data output start timing according to the difference between the logic high start time THS1 of the first point gate signal and the input timing of the interface data output signal EPI Data.

[0131] Hereinafter, a fifth embodiment will be described in which data output delay information can be exchanged between data drivers via a delay pulse line (or an option line).

[0132] FIG. 25 is an example diagram showing a data driver including a timing setting unit according to the fifth embodiment, FIG. 26 is an example diagram showing the configuration of a data driver connected by a delay pulse line according to the fifth embodiment, FIG. 27 is an internal block diagram of the first data driver shown in FIG. 26, and FIG. 28 is a partial configuration diagram of a large light emitting display device.

[0133] As shown in Fig. 25, the data driver 140 may further include a timing setting unit (Timing Setting) for providing data output timing information, as in the second embodiment. As shown in Fig. 26, the first data driver 140A and the second data driver 140B may be electrically connected to a gate start pulse line GSPL to which a gate start pulse GSP is transmitted, a gate line (or a dummy gate line) DGL to which a gate signal is transmitted, and a delay pulse line DPL.

[0134] The delay pulse line DPL is a line that transmits a delay pulse DP capable of informing data output delay information. The first data driver 140A can receive a delay pulse DP from the outside, add a value capable of informing its own data output state to the adjacent second data driver 140B, and output the delay pulse DP. The second data driver 140B can control its own data output timing according to the delay pulse DP output from the first data driver 140A. For example, the second data driver 140B can be configured to control the output timing of its first output channel to follow the output timing of the last output channel of the first data driver 140A according to the delay pulse DP output from the first data driver 140A.

[0135] As shown in FIG. 27, the first data driver 140A, like the second embodiment, may include a serial-parallel controller, a shift register, a latch, a digital converter DAC, a multi-channel output unit Multi-channel Output, a first signal sensing unit SENC1, a second signal sensing unit SENC2, a control unit (also referred to as a timing controller in this specification) Timing Control, a timing setting unit Timing Setting, an amplifier G / A, an analog-digital converter ADC, a sampling circuit Sample Circuit, and a signal transmission unit TX.

[0136] Meanwhile, the serial-parallel controller may include a first pulse input terminal connected to a first delay pulse line DPL1 and a second pulse input terminal connected to a second delay pulse line DPL2 in order to transmit and receive delay pulses through a delay pulse line DPL as shown in Fig. 26. The delay pulses inputted or outputted through the first delay pulse line DPL1 and the second delay pulse line DPL2 may be transmitted to the serial-parallel controller, the signal sensing units SENC1 and SENC2, the latch, the timing control unit Timing Control, and the timing setting unit Timing Setting.

[0137] In addition, the serial-parallel controller can output an output control signal LDOS that can control data output to the latch based on the delay pulse. Also, the serial-parallel controller can receive an output end signal LCOS that indicates the output timing of the last output channel from the latch in order to control (change) and output the delay pulse.

[0138] 28, when implemented as a large-sized light emitting display device, it may include at least four data drivers 140A-140D, similar to the second embodiment. The first and second data drivers 140A and 140B may apply data signals to a left display area based on the center line of the display panel, and the third and fourth data drivers 140C and 140D may apply data signals to a right display area based on the center line of the display panel.

[0139] The first signal sensing unit SENC1 may include a gate signal sensing unit 141 to which the first sensing signal SEN1 is applied and a timing counter unit 143 to which a gate start pulse GSP is applied, as in the second embodiment. The second signal sensing unit SENC2 may be configured similarly to the first signal sensing unit SENC1. In addition, the timing control unit Timing Control and the timing setting unit Timing Setting may receive a delay pulse DP to perform a function of controlling their own data output timing.

[0140] Hereinafter, a driving method of the light emitting display according to the fifth embodiment will be described, taking as an example the operation of the second data driver to which a delayed pulse can be applied from the first data driver.

[0141] Fig. 29 is a diagram for explaining a method for driving a light emitting display device according to a fifth embodiment. Note that in Fig. 29, steps 1 to 12 are described in order to facilitate understanding of the flow of the driving method. However, steps 1 to 12 do not have to be performed in the order described.

[0142] 29, first, (1) a delay pulse DP may be output from the first data driver 140A, then, (2) a third point of the gate line may be sensed through a third sensing line SENL3 connected to the gate signal sensing unit 141 of the second data driver, and then, (3) a fourth point of the gate line may be sensed through a fourth sensing line SENL4 connected to the gate signal sensing unit 141 of the second data driver.

[0143] Then, (4) the timing counter unit 143 of the second data driver 140B may count a delay time for the first data driver 140A. Then, (5) the timing counter unit 143 of the second data driver may sense a logic high start time THS1 of the gate signal from the third point of the gate line to the third point. Then, (6) the timing counter unit 143 of the second data driver may sense a logic high start time THS2 of the gate signal from the fourth point of the gate line to the fourth point. Then, (7) the timing counter unit 143 of the second data driver may sense a logic high end time THE1 of the gate signal from the third point of the gate line to the third point. Then, (8) the timing counter unit 143 of the second data driver may sense a logic high end time THE2 of the gate signal from the fourth point of the gate line to the fourth point.

[0144] Then, (9) the timing setting unit 148 of the second data driver can calculate a delay time between the first data driver and the second data driver. At the same time, (9) the timing setting unit 148 of the second data driver can calculate a difference between the logic high start time THS1 of the third point gate signal and the logic high end time THE1 of the third point gate signal. At the same time, (9) the timing setting unit 148 of the second data driver can divide the difference between the logic high start time THS1 of the third point gate signal and the logic high start time THS2 of the fourth point gate signal by the number of output channels of the second data driver. At the same time, (9) the timing setting unit 148 of the second data driver can calculate a difference between the logic high start time THS1 of the third point gate signal and the logic high start time THS2 of the fourth point gate signal. Here, a delay value according to the output channel direction of the data driver can be determined depending on whether the difference between the two values ​​is a positive number or a negative number.

[0145] Then, the timing controller 145 of the (10) second data driver can control (correct) the data output start timing based on the delay timing between the first data driver and the second data driver. At the same time, the controller 145 of the (10) second data driver can control the data output width according to the difference between the logic high start time THS1 of the third point gate signal and the logic high end time THE1 of the third point gate signal. At the same time, the timing controller 145 of the (10) second data driver can control the delay value between the data output channels based on the difference between the logic high start time THS1 of the third point gate signal and the logic high start time THS2 of the fourth point gate signal divided by the number of output channels of the second data driver. At the same time, (10) the timing control unit 145 of the second data driver can control the output channel direction delay value (Direction of Channel Delay) of the second data driver according to the difference between the logic high start time THS1 of the third point gate signal and the logic high start time THS2 of the fourth point gate signal.

[0146] Then, (11) a signal indicating that the output timing of the last output channel (Last Channel Output Timing) has occurred can be calculated by the timing setting unit 148 of the second data driver. Then, (12) the timing control unit 145 of the second data driver can control the delay pulse timing (DP Timing) to be transmitted to the next data driver (e.g., the third data driver) based on the signal indicating that the output timing of the last output channel (Last Channel Output Timing) has occurred.

[0147] Meanwhile, in order to improve driving safety and output accuracy when automatically correcting the data output timing, the embodiment may combine at least any two of the above-mentioned embodiments. The correction of the data output timing will be described as follows. However, the operation of the second data driver to which a delay pulse can be applied from the first data driver will be described as an example.

[0148] Fig. 30 is a diagram for explaining a method for driving a light emitting display device according to a sixth embodiment. Note that in Fig. 30, steps 1 to 17 are written in order to facilitate understanding of the flow of the driving method. However, steps 1 to 17 do not have to be performed in the order written.

[0149] 30, first, (1) a gate start pulse GSP can be output from the timing control section 120. Next, (2) a source output enable signal SOE can be output from the timing control section 120, and an interface data output signal EPI Data can be generated.

[0150] Then, (3) a delay pulse DP can be output from the first data driver 140A. Then, (4) a third point of the gate line can be sensed through a third sensing line SENL3 connected to the gate signal sensing unit 141 of the second data driver. Then, (5) a fourth point of the gate line can be sensed through a fourth sensing line SENL4 connected to the gate signal sensing unit 141 of the second data driver.

[0151] Then, (6) the gate start pulse GSP may be sensed by the timing counter 143 of the second data driver. Then, (7) the input timing of the interface data output signal EPI Data may be sensed by the timing counter 143 of the second data driver. Then, (8) the delay time for the first data driver 140A may be counted by the timing counter 143 of the second data driver.

[0152] Then, (9) a logic high start time THS1 of the gate signal at the third point from the third point of the gate line may be sensed by the timing counter unit 143 of the second data driver. Then, (10) a logic high start time THS2 of the gate signal at the fourth point from the fourth point of the gate line may be sensed by the timing counter unit 143 of the second data driver. Then, (11) a logic high end time THE1 of the gate signal at the third point from the third point of the gate line may be sensed by the timing counter unit 143 of the second data driver. Then, (12) a logic high end time THE2 of the gate signal at the fourth point from the fourth point of the gate line may be sensed by the timing counter unit 143 of the second data driver.

[0153] Then, the (13) timing setting unit 148 of the second data driver can calculate the difference between the logic high start time THS1 of the third point gate signal and the gate start pulse GSP. At the same time, the (13) timing setting unit 148 of the second data driver can calculate the difference between the logic high start time THS1 of the third point gate signal and the input timing of the interface data output signal EPI Data. At the same time, the (13) timing setting unit 148 of the second data driver can calculate the difference between the logic high start time THS1 of the third point gate signal and the source output activation signal SOE. At the same time, the (13) timing setting unit 148 of the second data driver can calculate the delay time between the first data driver and the second data driver. At the same time, the (13) timing setting unit 148 of the second data driver can correct the width of the source output activation signal SOE according to the difference between the logic high start time THS1 of the third point gate signal and the logic high end time THE1 of the third point gate signal. At the same time, (13) the difference between the logic high start time THS1 of the gate signal at the third point and the logic high start time THS2 of the gate signal at the fourth point can be divided by the number of output channels of the second data driver by the timing setting unit 148 of the second data driver. At the same time, (13) the difference between the logic high start time THS1 of the gate signal at the third point and the logic high start time THS2 of the gate signal at the fourth point can be calculated by the timing setting unit 148 of the second data driver. Here, depending on whether the difference between the two values ​​is a positive number or a negative number, a delay value according to the output channel direction of the data driver can be determined.

[0154] Then, (14) the timing setting unit 148 of the second data driver can select and output at least one of (A) a difference between the logic high start time THS1 of the gate signal at the third point and the gate start pulse GSP, (B) a difference between the logic high start time THS1 of the gate signal at the first point and the input timing of the interface data output signal EPI Data, (C) a difference between the logic high start time THS1 of the gate signal at the third point and the source output activation signal SOE, and (D) a delay time between the first data driver and the second data driver, so as to control the output timing (Start Timing).

[0155] Then, the timing controller 145 of the (15) second data driver can control (correct) the data output start timing based on at least one selected from (A), (B), (C), and (D). At the same time, the timing controller 145 of the (15) second data driver can control the data output width according to the difference between the logic high start time THS1 of the third point gate signal and the logic high end time THE1 of the third point gate signal. At the same time, the timing controller 145 of the (15) second data driver can control the delay value between the data output channels according to a value obtained by dividing the difference between the logic high start time THS1 of the third point gate signal and the logic high start time THS2 of the fourth point gate signal by the number of output channels of the second data driver. At the same time, (15) the timing control unit 145 of the second data driver can control the output channel direction delay value (Direction of Channel Delay) of the second data driver according to the difference between the logic high start time THS1 of the third point gate signal and the logic high start time THS2 of the fourth point gate signal.

[0156] Next, (16) a signal indicating that the output timing of the last output channel has occurred can be calculated by the timing setting unit 148 of the second data driver.

[0157] Next, (17) the timing control unit 145 of the second data driver can control the delay pulse timing (DP Timing) to be transmitted to the next data driver (e.g., the third data driver) based on a signal indicating that the last output channel output timing (Last Channel Output Timing) has occurred.

[0158] An example of a method for adjusting the output timing in the above-mentioned embodiment will now be described.

[0159] FIG. 31 is an example diagram showing a method of adjusting output timing applicable to the second, third and sixth embodiments, FIG. 32 is an example diagram showing a method of adjusting output timing applicable to the fourth and sixth embodiments, FIG. 33 is an example diagram showing a method of adjusting output timing applicable to the first to sixth embodiments, and FIG. 34 is an example diagram showing a method of adjusting output timing applicable to the fifth and sixth embodiments.

[0160] As shown in Fig. 31, the second, third and sixth embodiments can control the data output timing by the source output enable signal SOE. The data signal DATA can be output as D00, D01, D02, etc., every time the source output enable signal SOE is generated as a logic high H. However, if a delayed source output enable signal SOE' is provided by delaying the start time TS and end time TE of the source output enable signal SOE, a delayed data signal Data' output timing can be generated.

[0161] As shown in FIG. 32, in the fourth and sixth embodiments, the data output timing can be controlled by the interface data output signal EPI Data. The data signal DATA can be output as D00, D01, D02, etc. each time the interface data output signal EPI Data is generated (generated in packet form) such as EP10, EP11, EP12, etc. However, if a delayed interface data output signal EPI Data’ is provided by delaying the interface data output signal EPI Data like TED, the output timing of the delayed data signal Data’ can be generated.

[0162] As shown in FIG. 33, in the first to sixth embodiments, the data output timing can be controlled based on the delay value between the output channels of the data driving unit. The data signal DATA can be output as D00, D01, D02, etc. at the same time for all channels. However, if the delay value between the output channels is delayed so as to gradually increase like T1 < T2 < T3, the output timing of the delayed data signal Data’ between the output channels can be generated.

[0163] In FIG. 33, an example is given where it gradually increases as “T2 = T1 + Delay (delay value) * 1”, “T3 = T1 + Delay (delay value) * 2”, “T (Channel No, number of channels) = T1 + Delay (delay value) * (channel No - 1)”, but this is only an example and the embodiments are not limited to this.

[0164] As shown in Fig. 34, the fifth and sixth embodiments can control the data output timing based on the delay pulse applied to the data driver. For example, the first data driver SD-IC_A can receive a basic delay value SD-IC Delay from the timing control unit T-CON. The first data driver SD-IC_A can transmit a delay pulse DP to the second data driver SD-IC_B with the basic delay value SD-IC Delay, or can change the delay pulse DP reflecting its own data output state and transmit it to the second data driver SD-IC_B.

[0165] Therefore, the first data driver SD-IC_A can output a data signal #2Data in a general form (undelayed form) such as D00, D01, D02, etc., while the second data driver SD-IC_B can output a data signal #1Data in a form delayed by a time corresponding to the delay pulse DP, such as D00, D01, D02, etc.

[0166] In addition, as can be seen by referring to the above-mentioned embodiments, in order to facilitate understanding, the configurations and methods of the apparatus related to the data output timing automatic correction method have been described, but it should be understood that one or more of the embodiments can be combined.

[0167] As described above, the embodiment has an effect of automatically correcting and optimizing the data output timing of the data driver by, for example, interlocking between the timing controller and the data driver. Also, the embodiment has an effect of improving the driving safety and output accuracy of the data driver by sensing the gate signal through the gate line and referring to and analyzing the operation of other devices (or components) or signals generated therefrom to control the data output timing.

[0168] It will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments without departing from the scope of the appended claims, and therefore the present disclosure is intended to cover such modifications and variations provided they come within the scope of the appended claims and their equivalents.

[0169] This disclosure further includes the following clauses:

[0170] Clause 1 A display panel for displaying an image; a gate driver connected to the display panel; a data driver connected to the display panel; a timing controller for controlling the gate driver and the data driver, The data driver senses the gate signal output from the gate driver, and controls data output timing based on the sensed gate signal as well as the operation of another device or a signal generated therefrom.

[0171] Clause 2 The display device described in clause 1, wherein the data driver includes at least two sensing terminals connected to two points of a gate line or a dummy gate line located on the display panel to sense a gate signal output from the gate driver.

[0172] Clause 3 3. The display device according to claim 2, wherein the at least two sensing terminals are located on one side and the other side of the outermost shell of the data driver.

[0173] Clause 4 4. The display device according to any one of clauses 1 to 3, wherein the data driver controls data output timing based on a gate start pulse applied to the gate driver and the gate signal.

[0174] Clause 5 5. The display device of any one of clauses 1 to 4, wherein the data driver controls a data output timing based on a source output activation signal and the gate signal applied to the data driver.

[0175] Clause 6 A display device described in any one of clauses 1 to 5, wherein the data output timing of the data driver is controlled based on a data output signal and the gate signal via an interface coupled between the timing control unit and the data driver.

[0176] Clause 7 The display device described in any one of clauses 1 to 6, wherein the data driver includes at least two data drivers electrically connected to each other via a delay pulse line that inputs and outputs pulses including data output delay information of another device or its own.

[0177] Clause 8 The data driver includes: a gate signal output from the gate driver; a gate start pulse applied to the gate driver; A display device described in any one of clauses 1 to 7, comprising a signal sensing unit that calculates a logic high start time, a logic high end time and a logic high maintenance time of the gate signal based on a voltage that maintains the same level as the gate high of the gate signal.

[0178] Clause 9 A method for driving a display device, comprising: a display panel for displaying an image; a gate driver connected to the display panel; a data driver connected to the display panel; and a timing controller for controlling the gate driver and the data driver, sensing a gate signal output from the gate driver; calculating a data output delay of the data driver based on the gate signal; setting a data output timing of the data driver based on the data output delay.

[0179] Clause 10 The data output timing of the data driver is The gate driver is controlled based on a gate start pulse and the gate signal, is controlled based on a source output enable signal and the gate signal applied to the data driver; 10. The method of claim 9, wherein the timing controller and the data driver are controlled based on a data output signal and the gate signal via an interface connected between the timing controller and the data driver. [Explanation of symbols]

[0180] 120 Timing control section 130 Gate driver 140 Data Drive Unit 150 Display Panel 141 Gate signal sensing section 143 Timing counter section 145 Control Unit 148 Timing setting section

Claims

1. A display panel (150) for displaying images; a gate driving circuit (130) connected to the display panel (150); a data driving circuit (140) connected to the display panel (150); a timing control unit (120) for controlling the gate driving circuit (130) and the data driving circuit (140); A display device comprising: The data driving circuit (140) Sensing a gate signal output from the gate driving circuit (130); The timing controller 120 controls the data output timing of the data driving circuit 140 based on the sensed gate signal and a gate start pulse GSP that is directly and simultaneously applied to the gate driving circuit 130 and the data driving circuit 140 from the timing controller 120. It is structured as follows: The data output timing is as follows: The gate start pulse (GSP) from the timing control unit (120) is applied to the data driving circuit (140); The gate signal output from the gate driving circuit (130) is sensed by the data driving circuit (140); A data output delay is calculated by the data driving circuit (140) based on the gate start pulse (GSP) and the sensed gate signal; The data output timing and delay timing of the data driving circuit (140) are set based on the data output delay; and The data output timing is controlled by the set data output timing and delay timing. A display device controlled by the flow.

2. The data driving circuit (140) is configured to control the data output timing of the data driving circuit (140) based on the sensed gate signal and the gate start pulse (GSP) as well as the operation of a component of the display device or a signal generated therefrom, 2. The display device of claim 1, wherein the component is at least one of a timing setting section (128) of the timing control section (120), a timing setting section (128) of the data driving circuit (140), or a timing control section (145) of the data driving circuit (140).

3. 3. The display device of claim 1, wherein the data driving circuit (140) includes at least two sensing terminals (SENP1, SENP2, SENP3, SENP4) connected to different points of the gate lines (GL1, GLm) or dummy gate lines (DGL) located on the display panel, and the at least two sensing terminals are configured to sense the gate signal output from the gate driving circuit (130) in the data driving circuit (140).

4. The display device of claim 3 , wherein the at least two sensing terminals (SENP1, SENP2, SENP3, SENP4) are located at both ends of the data driving circuit (140).

5. 3. The display device of claim 2, wherein the data driving circuit (140) includes at least two data driving circuits (140A, 140B) electrically connected to each other via a delay pulse line (DPL), and the delay pulse line (DPL) transmits a pulse including data output delay information between the at least two data driving circuits (140A, 140B).

6. A method for driving a display device including a display panel (150) for displaying an image, a gate driving circuit (130) connected to the display panel (150), a data driving circuit (140) connected to the display panel (150), and a timing controller (120) for controlling the gate driving circuit (130) and the data driving circuit (140), sensing a gate signal output from the gate driving circuit; controlling a data output timing of the data driving circuit (140) based on the sensed gate signal and a gate start pulse (GSP) directly and simultaneously applied from the timing control unit (120) to the gate driving circuit (130) and the data driving circuit (140); Including, The data output timing is A gate start pulse (GSP) from the timing control unit (120) is applied to the data driving circuit (140); The gate signal output from the gate driving circuit (130) is sensed by the data driving circuit (140); A data output delay is calculated by the data driving circuit (140) based on the gate start pulse (GSP) and the sensed gate signal; The data output timing and delay timing of the data driving circuit (140) are set based on the data output delay; The data output timing is controlled by the set data output timing and delay timing. A method controlled by the flow.

7. controlling the data output timing of the data driving circuit (140) based on the sensed gate signal and the gate start pulse (GSP) as well as an operation of a component of the display device or a signal generated therefrom; 7. The method of claim 6, wherein the component is at least one of a timing setting section (128) of the timing control section (120), a timing setting section (128) of the data driving circuit (140), or a timing control section (145) of the data driving circuit (140).

8. 4. The display device of claim 3, wherein the data driving circuit (140) includes at least two signal sensing circuits (SENC1, SENC2) connected to the at least two sensing terminals (SENP1, SENP2, SENP3, SENP4), and the at least two signal sensing circuits (SENC1, SENC2) are configured to sense a gate signal output from the gate driving circuit (130).

9. 9. The display device of claim 8, wherein each of the at least two signal sensing circuits (SENC1, SENC2) includes a gate signal sensing unit (141) configured to sense a gate signal output from the gate driving circuit (130) and a timing counter unit (143) configured to count a start time and an end time of the gate start pulse (GSP).

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