Neutron detector, its manufacturing method using boron as neutron conversion layer and conformal doping

Abstract

A thermal neutron detector and method for manufacturing the same are provided. The thermal neutron detector can dually use boron in a semiconductor substrate, both in a neutron conversion layer and as a conformal doping source. The neutron detector can be a microstructure diode with a cavity having a depth of 60 microns or less. The cavity can be filled with boron and diffused into the semiconductor substrate by a diffusion annealing process.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Provisional Application No. 62 / 968,373, filed January 31, 2020, the entire contents of which are incorporated by reference, including any figures or tables. [Background technology]

[0002] In semiconductor radiation detectors, the incident radiation interacts with the detector material to generate electron-hole pairs. The generated charges are collected by the respective electrodes, generating an electrical pulse with information about the type, energy, arrival time, and flux of the particle. The most important features of semiconductor detectors are their excellent energy resolution due to their low ionization potential and their compact size, which makes them ideal for use in radiation detection applications. Since the primary ionized material must be collected to directly measure the energy of the nuclear radiation, the condensed phase, which has a higher density than gases, results in a more efficient stopping of radiation particles per unit length. Also, metals, used for radiation shielding, are not good candidates for condensed phase neutron detectors, since they allow rapid recombination of the generated charges and insulators inhibit the collection of these charges. For these reasons, semiconductors are considered the only good option for widespread use as radiation detectors.

[0003] Silicon and germanium are the most commonly used semiconductor materials in solid-state ionization chambers. Semiconductors based on other materials have been investigated but have proven difficult to scale for commercial applications due to inherent drawbacks such as availability, environmental hazards, and manufacturing techniques. Neutrons do not cause direct ionization of the detector, so they rely on secondary effects. The most common reactions used to generate charged particles from neutron interactions are: 10 B(n,α) 7 Li and 6 Li(n,α) 3H reaction (Non-Patent Documents 1, 2, 3). When thermal neutrons collide with a conversion material, primary reaction products such as alpha, gamma, and nucleons are generated. As the charged reaction products travel through the detection medium, secondary reaction products are generated by ionization, ultimately giving an electrical signal indicating the detection of a thermal neutron. In a typical planar neutron detector, the primary reaction product generated by neutron absorption is an alpha particle, which then ionizes a semiconductor detector, typically operated under reverse bias, generating electron-hole pairs. These generated charges are separated by an applied electric field and collected at the contacts. Solid-state thermal neutron detectors are small, operate at low voltages, and are more stable against vibration-induced noise compared to gas-based detectors. Despite these advantages, the maximum detection efficiency of thin-film-coated planar detectors is limited to 5% compared to 70% for helium-based gas detectors (Non-Patent Document 4). [Prior art documents] [Non-patent literature]

[0004] [Non-Patent Document 1] G. Knoll, Radiation Detection and Measurement, Third. John Wiley & Sons, Ltd., 2000. [Non-Patent Document 2] W. Price, Nuclear Radiation Detection, 2nd ed. McGraw Hill, New York, 1964. [Non-Patent Document 3] N. Tsoulfanidis, Measurement and Detection of Radiation, 2nd ed. Taylor and Francis, New York, 1995. [Non-Patent Document 4] D. S. McGregor, M. D. Hammig, Y. H. Yang, H. K. Gersch, and R. T. Klann, "Design considerations for thin film coated semiconductor thermal neutron detectors - I: Basics regarding alpha particle emitting neutron reactive films," Nucl. Instruments Methods Phys. Res. Sect. A Accel. Spectrometers, Detect. Assoc. Equip., vol. 500, no. 1-3, pp. 272-308, 2003. [Non-Patent Document 5] A. N. Caruso, "The physics of solid-state neutron detector materials and geometries.," J. Phys. Condens. Matter, vol. 22, no. 44, p. 443201, 2010. [Non-Patent Document 6] R. G. Fronk et al., "Microstructured Semiconductor Neutron Detectors (MSND) and Instrumentation." [Non-Patent Document 7] R. G. Fronk, "Dual-side etched microstructured semiconductor neutron detectors, an abstract of a dissertation," 2011. [Non-Patent Document 8] D. S. McGregor, S. L. Bellinger, and J. Kenneth Shultis, "Present status of microstructured semiconductor neutron detectors," J. Cryst. Growth, vol. 379, pp. 99-110, 2013. [Non-Patent Document 9] T. C. Unruh, D. S. McGregor, J. K. Shultis, W. J. McNeil, and S. L. Bellinger, "Microstructured semiconductor neutron detectors," Nucl. Instruments Methods Phys. Res. Sect. A Accel. Spectrometers, Detect. Assoc. Equip., vol. 608, no. 1, pp. 125-131, 2009. [Non-Patent Document 10] J. K. Shultis and D. S. Mcgregor, "Design and performance considerations for perforated semiconductor thermal-neutron detectors," 2009. [Non-Patent Document 11] Runkle, R. C.; Bernstein, A.; Vanier, P. E. Securing special nuclear material: Recent advances in neutron detection and their role in nonproliferation. J. Appl. Phys. 2010, 108, 111101. [Non-Patent Document 12] Ahmed, S. N. Physics and Engineering of Radiation Detection, 2nd ed.; Elsevier B.V., 2015; pp 137-143.

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[0005] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention provides a novel and advantageous thermal neutron detector and method for its manufacture. The thermal neutron detector is an isotopically enriched boron (e.g., 10-boron ( 10 B) or boron-containing materials (e.g. 10 The neutron detector has a high detection efficiency made possible by the dual use of a neutron conversion layer and a conformal doping source, both of which are made of a B-containing material. The neutron detector can be a microstructured diode (e.g., a PIN or PN diode) in which cavities are etched into a semiconductor substrate. The cavities can have any suitable type of geometry (e.g., trenches, circular holes, square holes, triangular holes), can all have the same type of geometry, can exhibit a different type of geometry from other cavities of the diode, some cavities can share a geometry with other cavities, have a different geometry from other cavities, or a combination thereof. The cavities can be formed by etch-forming a powder (e.g., 10 B powder, 10 B4C, 10The cavity may be filled with enriched boron or a boron-containing material, such as boron carbide (e.g., BO). The substrate with the filled cavity is then heat treated for solid-state diffusion of the boron into the semiconductor (e.g., silicon or germanium) substrate to provide a continuous conformal conductive layer over the entire exposed surface of the cavity. The cavity may be a variable depth microstructure, with a typical depth of 500 micrometers (μm) or less (e.g., 60 μm or less). The boron (e.g., 10 B) The filling is boron (e.g., 10 B) Acts as a neutron transmutation to initiate a transition reaction, emitting alpha particles that are detected by a diode (e.g., a PIN or PN diode). Boron can also be used as a solid diffusion source of boron into silicon to perform conformal doping of microstructured diodes, greatly increasing the neutron detection efficiency and greatly reducing the manufacturing complexity of the device.

[0006] In one embodiment, a method of manufacturing a thermal neutron detector includes n-doping a first surface of a semiconductor substrate, p-doping a second surface of the semiconductor substrate opposite the first surface with a p-type dopant material, etching a microstructure into the second surface of the semiconductor substrate, backfilling the p-type dopant material in the microstructure, and performing a diffusion anneal on the semiconductor substrate having the p-type dopant material backfilled in the microstructure such that at least one element of the p-type dopant material (e.g., boron) diffuses into the semiconductor substrate. Each microstructure of the microstructures etched into the second surface of the semiconductor substrate has a depth of 500 μm or less (e.g., 60 μm or less). The method further includes depositing an insulating layer dielectric on the second surface of the semiconductor substrate prior to p-doping the second surface of the semiconductor substrate to leave an active pattern exposed on the second surface, and the active pattern is p-doped. The p-type dopant material includes boron, but the embodiment is not limited thereto. The p-type dopant material can be, for example, 10 B powder. In some embodiments, the microstructures can also be etched into the first surface of the semiconductor substrate.

[0007] In another embodiment, the thermal neutron detector comprises a semiconductor substrate comprising a microstructure on its first surface, the semiconductor substrate comprising an n-doped portion formed by n-type doping on a second surface opposite the first surface of the semiconductor substrate, and a p-doped portion formed by p-type doping on the first surface of the semiconductor substrate using a p-type dopant material. The p-type dopant material is filled into the microstructure, and a diffusion anneal is performed on the semiconductor substrate having the p-type dopant material backfilled in the microstructure, such that at least one element of the p-type dopant material diffuses through the sidewalls of the microstructure into the semiconductor substrate. If at least one element of the p-type dopant material (e.g. boron) diffuses through the sidewalls of the microstructure into the semiconductor substrate as a result of the diffusion anneal, this results in a structural difference compared to a neutron detector not formed in this way, leading to a very high neutron detection efficiency (see, for example, Figures 6a and 6b). The second surface may also have a microstructure. Each of the microstructures on the first surface and / or the second surface of the semiconductor substrate has a depth of 500 μm or less (e.g., 60 μm or less). The p-type dopant material can include, but is not limited to, boron. The p-type dopant material can be, for example, 10 B powder may also be used. [Brief description of the drawings]

[0008] [Figure 1] 1 illustrates a process flow for a method of manufacturing a neutron detector according to an embodiment of the present invention. [Figure 2a] 1 is a plot of relative counts versus channel comparing neutron detection with planar PIN diodes and microstructure diodes. The high count curve is for the microstructure diode (12.5% ​​efficiency compared to 3.5% efficiency for the planar diode). [Figure 2b] 1 shows a top view of the geometry used to create the microstructure in the microstructure diode, according to one embodiment of the present invention. [Figure 2c]1 is a scanning electron microscope (SEM) image showing a cross-sectional view of a microstructure PIN diode according to one embodiment of the present invention. [Figure 3a] A plot of current (in amperes (A)) versus voltage (in volts (V)) showing leakage current in planar and microstructured diodes with boron-10 (10B) annealing but without conformal doping. In both cases, the diode active area is 100 millimeters squared (mm2). The curve with the higher current (circular data points) is for the microstructured diode. [Figure 3b] A plot of relative counts vs. channel comparing thermal neutron detection by planar PIN diodes and microstructured diodes filled with 10 B but without conformal doping. The curve with the higher counts is for the planar diode (3.5% efficiency compared to <1% for the microstructured diode without conformal doping). [Figure 4a] 1 is a plot of current (A) versus voltage (V) showing leakage current for microstructure diodes with different diode areas. The highest curve (triangle data points) is for a diode area of ​​100 mm2, the median curve (circle data points) is for a diode area of ​​50 mm2, and the lowest curve (square data points) is for a diode area of ​​25 mm2. [Figure 4b] 1 is a plot of leakage current density (A / mm) versus diode area (mm2) for planar and microstructure diodes. The curve with the higher values ​​(square data points) is for the microstructure diode, and the curve with the lower values ​​(circle data points) is for the planar diode. [Figure 5a] FIG. 1 shows surface treatments in microstructured diodes to reduce leakage currents and their effect on neutron detection efficiency (cited from Non-Patent Document 8), showing a cross-section of a selectively diffused diode with an oxide layer. [Figure 5b]FIG. 1 shows surface treatments in microstructured diodes to reduce leakage current and their effect on neutron detection efficiency (cited from Non-Patent Document 8), showing a cross-sectional view of conformal doping. [Figure 5c] FIG. 1 shows surface treatments in microstructured diodes to reduce leakage current and their effect on neutron detection efficiency (cited from Non-Patent Document 8) and shows plots of leakage current (A) versus reverse voltage (V) for different diodes. [Figure 5d] FIG. 1 shows surface treatments on microstructured diodes to reduce leakage current and their effect on neutron detection efficiency (cited from Non-Patent Document 8) and shows plots of neutron detection for different diodes. [Figure 6a] 1 is a plot of current (A) versus voltage (V) showing leakage current for a planar diode, a microstructured diode without 10B anneal, and a microstructured diode with 10B anneal (950° C.). The diode active area for all diodes is 100 mm2. The curve with the highest value at −1 V (circular data points) is for the microstructured diode without anneal, the curve with the median value at −1 V (square data points) is for the planar diode, and the curve with the lowest value at −1 V (triangle data points) is for the microstructured diode with 10B anneal. [Figure 6b] 1 is a plot of relative counts versus channel comparing thermal neutron detection (using a 252Cf source) with planar, microstructured PIN diodes, and conformally doped microstructured diodes. The curve with the highest count value is for the conformally doped microstructured diode (12.5% ​​efficiency), the curve with the median value is for the planar diode (3.5% efficiency), and the curve with the lowest value is for the microstructured PIN diode without conformal doping (<1% efficiency). [Figure 7] 1 is a plot of sheet resistance or resistivity (ohms per square (Ω / square)) versus anneal time (minutes) showing the resistance of a substrate (eg, silicon) after a 10B fill and anneal process. [Figure 8a] FIG. 1 is a plot of intrinsic efficiency (%) versus semiconductor width (in micrometers (μm)) for different sizes of microstructure apertures in a microstructure diode. Each size microstructure had a circular hole geometry with a depth of 40 μm. The curve with the highest value (circular data point) is for the 4 μm aperture, the curve with the median value (square data point) is for the 3 μm aperture, and the curve with the lowest value (triangle data point) is for the 8 μm aperture. The large triangle at the bottom right of the plot shows the experimentally obtained intrinsic efficiency with the 8 μm aperture. [Figure 8b] 1 shows a plot of intrinsic efficiency (%) versus semiconductor width (μm) for different shaped openings for a 4 μm wide opening. The curve with the highest value at 3.0 μm (triangle data points) is for the square hole, the curve with the median value at 3.0 μm (square data points) is for the trench, and the curve with the lowest value at 3.0 μm (circle data points) is for the circular hole. [Figure 9] 3 illustrates a process flow for a method of manufacturing a neutron detector in accordance with an embodiment of the present invention. [Figure 10] 1 illustrates a process flow for a centrifugation process for backfilling a microstructure diode 10B according to an embodiment of the present invention. [Figure 11] 1 shows a schematic diagram of a fabricated microstructure diode according to an embodiment of the present invention. [Figure 12] A plot of sheet resistance (Rs, Ω / square) versus anneal time (t, min) is shown, illustrating the effect of doping using isotopically enriched 10B in intrinsic silicon, where an anneal time of 0 minutes refers to the sheet resistance of the substrate (approximately 105 Ω / square). The inset is a plot of voltage (V) versus current density (Amps per square centimeter / (A / cm2)) showing the effect on the diode leakage current before and after diffusion as a result of annealing. [Figure 13] 1 shows a schematic diagram of a thermal neutron detector according to an embodiment of the present invention, in which 10B and silicon are listed as p-type dopant and substrate materials, respectively, by way of example only and not by way of limitation. [Figure 14] 1 is a scanning electron microscope image of a cross section of a narrow trench densely packed with 10B by centrifugation according to an embodiment of the present invention. [Figure 15] 1 shows a plot of hole separation (in micrometers (μm)) versus neutron detection efficiency (%), showing the results of a Monte Carlo simulation of a microstructure detector with circular holes of various diameters. The curve with triangular data points is for an 8 μm diameter, the curve with circular data points is for a 6 μm diameter, and the curve with square data points is for a 4 μm diameter. [Figure 16] A plot of relative counts versus channels is shown comparing thermal neutron detection with conformally doped planar diodes and microstructured diodes (circular hole design). The curve with the highest counts is for the conformally doped microstructured diode (12.5% ​​efficiency) and the curve with the lowest counts is for the planar diode (3.5% efficiency). [Figure 17] 1 shows a plot of neutron detection efficiency (%) versus trench spacing (μm) comparing theoretically simulated and experimental efficiencies of a microstructure neutron detector with a trench design. The detector geometry is shown in the inset. The curves with circular data points are for the experimental results and the curves with square data points are for the theoretical data points. [Figure 18] FIG. 1 shows a schematic diagram of the setup showing the electronics used by the microstructure detector for neutron detection. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention provides a novel and advantageous thermal neutron detector and method for its manufacture. The thermal neutron detector is an isotopically enriched boron detector, e.g., 10-boron ( 10 B) or boron-containing materials (e.g. 10The neutron detector has a high detection efficiency made possible by the dual use of a neutron conversion layer (e.g., a B-containing material) both in the neutron conversion layer and as a conformal doping source. The neutron detector can be a microstructured diode (e.g., a PIN or PN diode) in which cavities are etched into a semiconductor substrate. The cavities can have any suitable type of geometry (e.g., trenches, circular holes, square holes, triangular holes), can all have the same type of geometry, can exhibit a different type of geometry from other cavities of the diode, some cavities can share a geometry with other cavities, have a different geometry from other cavities, or a combination thereof. The cavities can be formed by etch-forming a powder (e.g., 10 The cavity may be filled with enriched boron or a boron-containing material, such as boron-containing fluoride (B powder). The substrate with the filled cavity is then heat treated for solid-state diffusion of the boron into the semiconductor (e.g., silicon or germanium) substrate to provide a continuous conformal conductive layer over the entire exposed surface of the cavity. The cavity has a depth of 60 μm or less. The boron (e.g., 10 B) The filling is boron (e.g., 10 B) acts as a neutron transmutation to initiate a transition reaction, emitting alpha particles that are detected by a diode (e.g., a PIN or PN diode). Boron can also be used as a solid diffusion source of boron into silicon to conformally dope microstructure diodes to greatly increase the neutron detection efficiency of the device. Boron is described herein as a p-type dopant by way of example only and not by way of limitation. Other p-type dopants can be used.

[0010] When the term "about" is used in conjunction with a numerical value, the value is intended to be in the range of 95%-105% of the value, i.e., the value is understood to be + / - 5% of the stated value. For example, "about 1 kg" means 0.95 kg to 1.05 kg.

[0011] Three-dimensional (3D) microstructured semiconductor detectors have shown promise as highly efficient solid-state thermal neutron detectors. These microstructured detectors may be, for example, reverse-biased PIN diodes with a cavity etched into them, followed by backfilling with a neutron conversion material so that the diode can detect neutrons. In an embodiment of the invention, the neutron conversion material is: 10 B (or 10 In one embodiment, the neutron detecting element may be boron (or a boron-containing material), such as a B-containing material, and the same material may be used as a boron source for conformal doping to increase the neutron detection efficiency of the device.

[0012] FIG. 1 shows a process flow for a method of manufacturing a neutron detector according to an embodiment of the present invention. FIG. 9 also shows a process flow for manufacturing a neutron detector. With reference to FIGS. 1 and 9, n (e.g., n+ or n++) doping is performed on a first surface of a semiconductor substrate (e.g., the "backside" of the substrate). The semiconductor substrate shown in FIG. 1 is an intrinsic silicon wafer, but this is for illustrative purposes only, and any suitable semiconductor substrate can be used (e.g., germanium or n-type or p-type silicon). Next, a deposition is performed (e.g., an insulating layer dielectric (ILD)) and the active patterns on the second surface of the semiconductor substrate opposite the first surface (e.g., the "frontside" of the substrate) are left exposed. Next, p (e.g., p+ or p++) doping is performed in the active patterns / areas. Next, a microstructure is etched on the second surface of the substrate (e.g., the frontside) and boron backfilling is performed in the microstructure. Then, a diffusion anneal is performed on the substrate so that the backfilled boron diffuses into the substrate. Electrical contacts can be deposited on the first and second surfaces (e.g., backside and frontside) of the substrate, respectively. The doping source for p-doping is 10 B (or 10 The boron (or boron-containing material) may be a boron (or boron-containing material) such as a B-containing material, which may be the same material used for the boron backfilling.

[0013] P-doping can be performed by any suitable method known in the art, for example, spin-on glass doping. N-doping can be performed by any suitable method known in the art, for example, solid diffusion. Phosphorus and / or lithium can be used as dopants for n-doping, but the embodiments are not limited thereto. During etching of the microstructure, any suitable etching method known in the art can be used, for example, a thin layer of metal can be used as a hard mask to form the pattern, and the microstructure can be etched by a dry etching process (for example, reactive ion etching (RIE)) or a wet etching process. Backfilling can be performed by any suitable method known in the art, for example, by centrifugation or sedimentation. A diffusion anneal can be performed to diffuse boron into the sidewalls of the etched microstructure. Electrical contacts can be made from any suitable material known in the art, for example, aluminum-silicon (Al-Si) ohmic contacts, and can be deposited using any suitable method known in the art, for example, by sputtering.

[0014] In a particular embodiment, the neutron detector can be fabricated using a silicon wafer (e.g., a 525 micron float-zone silicon wafer with a resistivity of greater than 10 kΩ-cm). The entire backside of the wafer can be doped with phosphorous and / or lithium, for example, by solid-state diffusion. The front side of the wafer can then be patterned to open up the active areas and then doped with boron (e.g., 10 B). The thin metal layer can be used as a hard mask to pattern and etch the microstructures by a dry etching process. The hard mask can be removed after etching the microstructures, and the microstructures can then be doped with boron (e.g., 10B). Another diffusion anneal is performed to diffuse the centrifuged boron into the sidewalls of the etched microstructure. Finally, Al-Si ohmic contacts are deposited by sputtering on both the front and back sides of the wafer to complete the PIN diode.

[0015] Microstructured silicon diodes advantageously increase neutron detection efficiency as the microstructure increases the active detection area. Related art devices use very deep trenches (>60 μm deep) filled with lithium fluoride, which acts as a neutron conversion layer. In embodiments of the invention, boron (e.g., 10 A shallow cavity (e.g., <60 μm deep) filled with ZnSe (A) exhibits high detection efficiency comparable to that of a deep trench. Figure 2a shows the neutron detection efficiency using a planar PIN diode compared to that of a microstructure diode with a circular cavity 8 microns in diameter and 40 microns deep (according to an embodiment of the present invention). With reference to Figure 2a, the efficiency of the diode of the embodiment of the present invention is more than 3.5 times higher than the efficiency of the planar diode.

[0016] When RIE is used to fabricate the microstructures, surface damage can result from the RIE process that can adversely affect diode performance and detection efficiency. Neutron detection is performed by sensing the change in diode current under reverse bias. Therefore, the PIN diode must have as low a leakage current (i.e., current under reverse bias) as possible. Damage from the etching process and the presence of dangling bonds in the now exposed substrate surface (e.g., silicon substrate surface) can increase the leakage current of the microstructure diode and thus reduce the detection efficiency. Figure 3a is a plot of current (Amperes (A)) versus voltage (Volts (V)); 10 Figure 1 shows the leakage current in planar and microstructured diodes with .B annealing but without conformal doping. In both cases, the diode active area is 100 square millimeters (mm 2) Figure 3b is a plot of relative counts versus channel; 10 3a and 3b show a comparison of thermal neutron detection by planar PIN diodes and microstructured diodes with B annealing but without conformal doping. Referring to Fig. 3a and 3b, the planar diode has a detection efficiency more than 3.5 times higher than the microstructured diode without conformal doping.

[0017] The adverse effect of etching the microstructure becomes more pronounced as the diode area increases. Surface defects increase with increasing detection area, and higher leakage currents are observed. This can be seen in Figures 4a and 4b, where the former is a 25 mm PIN structure after the microstructure is etched. 2 , 50mm 2 , and 100 mm 2 The current-voltage (IV) characteristics of the fabricated diode in the area of ​​25 mm 2 The leakage current observed in does not significantly affect neutron detection performance, but larger area diodes may be required for detectors to monitor specific nuclear materials over a large area (e.g., urban networks, port detectors, mobile units, and handheld detectors). Figures 5a and 5b show methods to reduce leakage current on microstructure diodes, and Figures 5c and 5d show the IV characteristics and neutron detection of diodes using these techniques (Non-Patent Document 8).

[0018] Methods used to help reduce leakage current (i.e., passivate defects created during the etching process) include thermal oxidation, oxide coating, and conformal doping. In thermal oxidation, a thin layer of silicon dioxide (SiO2) is thermally grown on the exposed silicon surface by diffusing an oxidant into the substrate at high temperature and reacting with it. Conformal growth is achieved while the oxidant is in the gas phase and travels all around and inside the cavity. In oxide coating, a conformal coating technique such as atomic layer deposition (ALD) or plasma enhanced chemical vapor deposition (PECVD) is used to deposit a thin oxide film. In conformal doping, the sidewalls of the microstructure are diffused to form a conformal PN junction to passivate the etch damage at the exposed silicon surface. Referring to Figures 5c and 5d, conformal doping gives the best results.

[0019] In an embodiment of the present invention, conformal doping can be achieved in a very simple manner by solid-phase diffusion of boron into a substrate (e.g., silicon). 10 B) The filling is not only used as a neutron conversion layer, but also as a boron source for conformal doping of the substrate (e.g., silicon). The conformal doping passivates the damaged surface and forms a conductive layer throughout the cavity, giving a better electric field distribution. Figure 6a shows 10 B filling process and annealing after manufacturing 100mm 2 The I-V characteristics of the active region are shown in Fig. 6b, and the neutron detection curve is shown in Fig. 6b. The leakage current is significantly reduced and the thermal neutron detection efficiency is significantly increased with boron conformal doping.

[0020] FIG. 7 is a plot of sheet resistance or resistivity (ohms per square (Ω / square)) versus anneal time (minutes); 10 7 shows the resistivity of a substrate (eg, silicon) after the B filling and annealing process. Referring to FIG. 7, the diffusion of boron into the substrate (eg, silicon) is confirmed by the sheet resistance of the substrate after the heat treatment. 10The B layer was carefully removed to access the substrate surface, resulting in the results in FIG.

[0021] Any shape, width / diameter, and depth (up to 60 μm) can be used for the microstructure. Figures 8a and 8b show the results for different aperture diameters (Figure 8a) and geometries (Figure 8b). Neutron detection efficiencies up to 37% were achieved in simulations using different shapes and sizes.

[0022] Embodiments of the present invention utilize boron-filled materials as a neutron conversion layer and as a boron source for conformal doping. Shallow microstructures (up to 500 μm deep (e.g., up to 60 μm deep)) can be used while achieving high thermal neutron detection efficiency compared to related art devices. The devices and methods of the present invention are simple and cost-effective for conformal doping of semiconductor (e.g., silicon) microstructures.

[0023] The embodiments of the present invention and its many advantages will be understood from the following examples, which are given by way of illustration. The following examples are illustrative of some of the methods, applications, embodiments, and variations of the present invention. They are, of course, not to be considered as limiting the present invention. Numerous variations and modifications can be made with respect to the present invention.

[0024] Example 1 Neutron detectors were fabricated using prime single-side polished n-type float zone wafers with resistivity >10,000 Ω-cm as substrates. A standard oxide strip using buffered oxide etch (BOE) was performed on the untreated wafer before growing a protective thermal oxide layer at 1000 °C for 90 min, which acts as a diffusion mask during later steps. The oxide on the backside of the wafer was stripped using BOE, while protecting the oxide on the frontside. Just before doping the backside of the wafer, a well-known RCA clean was performed on the wafer to remove any organic material, particulates, or trace metals. The sample was then quickly transferred to a phosphorus doping furnace and solid-state diffusion was performed at 950 °C for 30 min to form a highly conductive n++ film over the entire backside of the wafer. After diffusion, the thin glass layer formed during diffusion and the thermal oxide grown in the previous step were removed using BOE until hydrophobicity on the wafer was visually confirmed. A piranha clean followed by a hydrofluoric acid (HF) strip was performed to remove any organic residues remaining from the previous step. Immediately after cleaning, another insulating layer dielectric (ILD) stack was grown to act as a diffusion mask during frontside doping while protecting the doped backside until needed. The first layer of ILD was oxide thermally grown at 1000°C for 40 minutes, followed by deposition of the second layer, silicon nitride, by low pressure chemical vapor deposition (LP-CVD). S1813 photoresist was used to pattern the frontside of the wafer and open the diffusion windows. RIE was used to remove the ILD stack in the diffusion windows, followed by oxide strip with BOE until hydrophobicity was visually confirmed. The photoresist was then stripped and a second RCA clean was performed to prepare the wafer for the boron diffusion process.

[0025] A thin layer of Borofilm-100 spin-on glass (SOG) dopant was coated onto the cleaned wafer and then baked at 200°C for 20 minutes to remove the solvent. This was followed by doping at 950°C for 15 minutes to drive the boron dopant into the exposed silicon surface. The residual glass layer from the SOG was removed using BOE as was done previously on the other side of the wafer. A very thin layer of aluminum was deposited by electron beam evaporation to act as a hard mask during the deep silicon etching (DSE) process to etch the microstructures. As previously described, the microstructures were patterned in the aluminum using S1813 photoresist. The photoresist was removed and then the microstructures were etched using a regular DSE process with the patterned aluminum as the hard mask. The aluminum hard mask was then removed after etching and a piranha clean was performed to remove any polymer deposited during the DSE process, followed by an HF clean. A premetal clean was performed until hydrophobicity was observed immediately prior to metal deposition using BOE. The wafer was quickly transferred to a sputter tool to deposit 300 nm of aluminum-silicon contacts. The base pressure was at least about 1×10 -7 Torr. A final lithography step using S1813 was performed to define the aluminum contacts in the active area by etching the aluminum using an aluminum etchant at 40 °C. A hard-baked S1813 photoresist was then used to protect the front side of the wafer, and the ILD stack on the back side of the wafer was removed as done before. Once hydrophobicity of the back side was observed, the front side photoresist was stripped and then another pre-metal cleaning was performed on the back side before the contacts were deposited by sputtering. The contacts were then annealed in forming gas at 430 °C for 30 minutes as the final step in the fabrication process.

[0026] The IV characteristics were measured using a Keithley 4200-SCS and an HP4284A precision LCR meter to measure the capacitance-voltage (CV) of the device. For radiation detection, polonium-210 (Po-210) was used as the alpha source and californium-252 (Cf-252) was used as the neutron source. An Ortec 142A preamplifier was used to apply bias and amplify the preamplifier of the pulses emanating from the radiation source, and pulse shaping was performed using an Ortec 575 shaping amplifier. Finally, an Ortec EASY-MCA-2K multichannel analyzer was used to create bins in which the pulses were counted.

[0027] Several different experiments were performed to obtain IV characteristics neutron detection results and sheet resistance. The results are shown in Figures 2a, 3a, 3b, 4a, 4b, 6a, 6b, and 7. These results have been described herein above. Figures 8a and 8b show the results of simulations performed to simulate the intrinsic efficiency of diodes of embodiments of the invention with different aperture diameters (circular hole geometry with a depth of 40 μm, Figure 8a) and different geometries (with a constant aperture width / diameter of 4 μm, Figure 8b).

[0028] Example 2 10 Neutron detectors were fabricated by doping B powder. 10 B powder was suspended in ethanol, dispersed on a planar silicon wafer, and annealed at 950 °C. After annealing, the residual boron powder was removed and the surface was cleaned with HF to remove the thermal oxide that had grown during annealing. Since the silicon wafer was n-type, 10 In order for B to be a p+ doping, the wafer had to be counter doped first.

[0029] The diode manufacturing process is shown in Figures 9, 10, and 11. 4Top-grade single-side polished n-type float zone wafers with resistivity of Ω-cm were used as substrates. A 200 nm thick thermal oxide layer was grown, which acts as a diffusion mask during later fabrication steps. A buffered oxide etch (BOE) was used to remove any oxide on the backside of the wafer. An RCA clean was then performed to remove any organic material, particulates, or trace metals. The substrate was quickly transferred for phosphorus doping using solid-state diffusion. This resulted in the formation of a highly conductive n+ layer on the backside of the wafer, as shown in step 1 of Figure 9. A piranha clean was followed by a hydrofluoric acid (HF) strip to remove any organic residues, and an insulating dielectric (ILD) stack was deposited. The ILD acts as a diffusion barrier during frontside doping while protecting the backside of the wafer. The ILD stack includes 200 nm thick silicon oxide and 50 nm low-pressure chemical vapor deposition (LP-CVD) deposited silicon nitride. The front side of the wafer was then patterned to open diffusion windows in the dielectric stack (step 1) and a second RCA clean was performed to prepare the front side of the wafer for the boron diffusion process using a thin layer of Borofilm-100SOG dopant. After spinning the Borofilm, the wafer was annealed at 950°C for 15 minutes to drive the boron dopant into the exposed silicon surface. This forms a p+ layer on the patterned front side of the wafer as shown in step 2 of Figure 9. Next, a thin layer of aluminum was deposited to act as a hard mask for the deep silicon etching (DSE) process. The microstructures were then etched using the DSE process. The aluminum hard mask was removed after the DSE etch and a piranha clean was performed to remove the polymer deposited during the DSE process.

[0030] Following microstructure definition and etching, commercially available 99.9% pure enriched boron (96% 10 B) (most of which have a particle size of 100-500 nm) was used to fill the etched cavities. First, 10A suspension of B powder was prepared and centrifugation was used to backfill the microstructures. For the centrifugation process, the (previously diced) microstructure wafer was placed, trench-side up, in a perforated sample holder at the bottom of a centrifuge tube. The tube was then filled with ethanol- 10 The B suspension was loaded and spun at 7000 rpm in a Beckmann-Coulter ultracentrifuge. This process is shown in Figure 9 (Step 3): 10 The B powder is pumped from the suspension into the trenches of the microstructure wafer. 10 Powder B is collected and reused. Figure 10 shows a schematic of the filling process.

[0031] Next, 10 The B-filled microstructure was annealed at 950°C to conformally dope in the trenches (step 3), as well as partially sintered to further densify the fill. This step was followed by a pre-metal cleaning using BOE and a 300 nm aluminum-silicon (Al-Si) contact on the front side of the wafer. A final lithography step was performed to define the contacts in the active area by etching the Al-Si contact. The final step in the fabrication process was the deposition of the back contact, followed by an anneal at 430°C in forming gas (step 4 in Figure 9). Figure 11 shows the 200 mm 2 1 shows a fully fabricated microstructured element of

[0032] A schematic diagram of the test setup is shown in Figure 18. The neutron source consisted of moderated Californium-252 ( 252 Cf) was used. The thermal neutron flux at the measurement position was 9900 thermal neutrons / mm 2 The pulses were measured at 100 Hz to 100 Hz, with a typical pulse width of 100 Hz / hour. An Ortec 142A preamplifier was used to bias the diode and preamplify the pulses generated by the alpha in the diode. Pulse shaping was performed with an Ortec 575 shaping amplifier. An Ortec EASY-MCA-2K multichannel analyzer was used to measure the pulses / channel.

[0033] Figure 12 shows 10 The B solution successfully doped silicon after annealing, with a 5 Ω / square to about 8×10 2 This result shows that the sheet resistance is effectively reduced to Ω / square, which is approximately 2×10 compared to the sheet resistance typically obtained using conventional spin-on-glass (SOG) technology. 2 Ω / square) and is shown by an asterisk in FIG. 12. The reduction in sheet resistance is 10 The B doping increases the doping concentration, indicating that the silicon is changed from n-type to p-type by counterdoping. The doping concentration saturated after 15 minutes of annealing. This diffusion also resulted in a continuous p+-n junction in the microstructure diode, as evidenced by the reduction in leakage current density of the undoped and doped microstructure diodes, respectively. This is shown in the inset of Figure 12. The lower leakage current indicates reduced etching damage of the surface states during trench formation. This low leakage current achieved by conformal doping is important for achieving high neutron detection efficiency.

[0034] Example 3 Using Monte Carlo nuclear particle (MCNP) simulations, two fundamental microstructural designs, (a) circular holes and (b) trenches, are considered and compared with geometries for neutron detection.

[0035] The expected thermal neutron detection efficiency for the microstructured diodes was first simulated using the MCNP code (v6.2) (see also 31 and 32, which are incorporated by reference in their entirety). Using a neutron capture ion algorithm, 10 B(n,α) 7 By the reaction of Li 10 Neutron capture in the B film was examined. The charge accumulated by the alpha particles in the bulk of the diode was then determined using the pulse height tally tool of MCNP.

[0036] The schematic geometry of the detector used in this analysis is shown in Figure 13. A circular hole geometry was chosen for the simulation and experimental studies because of its potential physical robustness. The circular geometry is 10 In addition to the B-filled microstructure, a 3 μm thick 10 Figure 14 includes layer B. 10 Scanning electron microscope (SEM) cross-section of a B-filled microstructure. The depth of the microstructure was kept constant at 40 μm since approximately 90% of the thermal neutrons are captured at this depth (or within this range). Varying the hole size and spacing results in an efficiency of approximately 13% at 4 μm hole spacing, as shown in Figure 15. However, decreasing the hole spacing to 2 μm results in an efficiency of up to 26%. The larger the diameter, the longer it takes for the neutrons to reach the semiconductor. 10 The efficiency appeared to be inversely proportional to the hole size, as more alpha particles were captured in the B layer. 10 This is directly related to the approximately 3 μm region of alpha particles in the B-transmutation material. Therefore, by reducing the hole size and spacing, the probability of the charged particles reaching the space charge region in the silicon increases, resulting in higher neutron detection efficiency.

[0037] Example 4 200mm 2 The thermal neutron detection performance of both planar and microstructured diodes with regions (according to embodiments of the present invention) was compared with that of the planar and microstructured diodes moderated with high density polyethylene. 252 The measurements were performed using a Cf source. The detector was aligned vertically in a stainless steel darkroom under vacuum 15 cm from the neutron source. The thermal neutron flux at this position (9900 neutrons / mm 2The intrinsic thermal neutron detection efficiency (TFE) was determined using a calibrated neutron detector with 30% efficiency before measurements were performed. The intrinsic thermal neutron detection efficiency of a planar detector fabricated using the same process flow was about 3.5% with a lower discriminator of 300 keV. Conformal doping increases the probability of charges reaching the depletion region of the diode before recombination, increasing the thermal neutron detection efficiency to 12.5% ​​(Figure 16). Using a conformal doping process to eliminate the etching damage of the sidewalls of the microstructure while creating a continuous p+ layer, good thermal neutron detection efficiency is obtained. This is in good agreement with MCNP simulations, as shown in Figure 15. Compared to a planar detector of the same area, the thermal neutron detection efficiency of a 200 mm 2 The increase in total counts per channel of the microstructure detector is shown in FIG. 16. The results show that conformal doping of the microstructure detector increases the thermal neutron detection efficiency. The increased efficiency is due to the larger active area in the conformally doped diode compared to the planar detector. Similarly, the large amount of neutrons in the microstructure detector 10 The presence of B increases the probability of neutron interaction. The combination of these two effects results in higher neutron detection efficiency in conformally doped microstructure detectors when compared to planar detectors.

[0038] It can be seen that the incorporation of conformally doped sidewalls in a circular hole microstructure design provides a substantial improvement over planar detectors. The poor performance of this hole design compared to a trench is due to the low doping rate in the hole compared to a trench for a given dimension. 10 This is because B is relatively rare.

[0039] Example 5 The neutron detection efficiency of devices with trench microstructures at a constant trench width of 4 μm was tested. The results are shown in FIG. 17. By decreasing the spacing between trenches from 4 μm to 2 μm, the experimental efficiency increased from about 14% to 21%. By decreasing the spacing between trenches to 2 μm, the detectors detected more neutrons compared to those with 4 μm-spaced trenches. 10B. Furthermore, silicon can have 10 A thickness of about 1.3 μm is required to capture the alphas generated by B. Thus, a 2 μm spacing between the trenches is sufficient to completely absorb the energy deposited by the alphas. This allows more neutrons to interact with the neutron conversion material, resulting in an increase in neutron detection efficiency.

[0040] The efficiencies obtained from the experimental results follow the same trend as the MCNP simulation efficiencies, as shown in Figure 17. Compared to the MCNP simulation efficiencies, the experimental efficiencies are within 15% and 25% for detectors with circular hole and trench geometries, respectively. The discrepancy in the intrinsic thermal neutron detection efficiency is due to the presence of small impurities in the microstructure. 10 This is due to the difference in packing density of B. 10 The packing density of B was assumed to be 100%, which is like a solid block of material with 100% microstructural packing, giving the maximum possible conversion efficiency. However, in such experiments 10 Complete filling of B powder is not practical.

[0041] Generally, isotopic enrichment 10 The dual use of B powder as a neutron conversion material and conformal doping source was demonstrated. Experimental results confirmed the thermal neutron detection efficiency predicted using MCNP simulations. The improved efficiency of the microstructured diodes was due to the backfilling effect. 10 Diffusion of B into the semiconductor results in conformal doping of the sidewalls and improved charge collection. Further evidence of conformal doping was demonstrated by the reduction in leakage current in fine-structured diodes.

[0042] The examples and embodiments described herein are for illustrative purposes only, and various modifications or changes in light thereof will be suggested to those skilled in the art, which are intended to be included within the spirit and scope of the present specification.

[0043] All patents, patent applications, provisional applications, and publications mentioned or cited in this specification (including those in the "Prior Art Documents" section) are incorporated by reference in their entirety, including all figures and tables, to the extent they do not contradict the explicit teachings of this specification.

Claims

1. 1. A method of manufacturing a thermal neutron detector, comprising the steps of: n-type doping a first surface of a semiconductor substrate; doping a second surface of the semiconductor substrate opposite the first surface with a p-type dopant material; Etching a feature on the second surface of the semiconductor substrate; backfilling the p-type dopant material from the microstructure by centrifugation; performing a diffusion anneal on the semiconductor substrate having the p-type dopant material backfilled into the microstructure such that at least one element of the p-type dopant material diffuses into the semiconductor substrate and the p-type dopant material is partially sintered; The method, wherein the p-type dopant material comprises boron powder and the at least one element of the p-type dopant material comprises boron.

2. 10. The method of claim 1, wherein each of the microstructures etched into the second surface of the semiconductor substrate has a depth of 500 μm or less.

3. 3. The method of claim 1, further comprising depositing an insulating layer dielectric on the second surface of the semiconductor substrate before performing p-type doping on the second surface of the semiconductor substrate, leaving an active pattern exposed on the second surface, and the p-type doping is performed on the active pattern.

4. The method according to any one of claims 1 to 3, wherein the n-type doping uses an n-type dopant material comprising at least one of phosphorus and lithium.

5. The p-type dopant material is boron-10 ( １０ The method according to any one of claims 1 to 4, further comprising:

6. The p-type dopant material is １０ The method according to claim 5, wherein the powder is B powder.

7. The method of any of claims 1 to 6, further comprising depositing a first electrical contact on the first surface of the semiconductor substrate and depositing a second electrical contact on the second surface of the semiconductor substrate.

8. The method according to any of the preceding claims, wherein the microstructures are etched into the second surface of the semiconductor substrate using reactive ion etching (RIE).

9. The method according to any of the preceding claims, wherein the microstructures are etched into the second surface of the semiconductor substrate using a wet etching process.

10. The method according to any of the preceding claims, wherein the p-type doping is performed by spin-on-glass doping and the n-type doping is performed by solid-state diffusion.

11. The method according to any of the preceding claims, wherein at least one of the microstructures etched into the second surface of the semiconductor substrate has a circular hole geometry.

12. The method according to any of the preceding claims, wherein at least one of the microstructures etched into the second surface of the semiconductor substrate has a square hole geometry.

13. The method according to any of the preceding claims, wherein at least one of the microstructures etched into the second surface of the semiconductor substrate has a trench geometry.

14. 14. The method according to any of claims 1 to 13, wherein each of the microstructures etched into the second surface of the semiconductor substrate has a circular hole geometry with an opening radius of 4 μm and a depth of 60 μm or less.

15. each of the microstructures etched into the second surface of the semiconductor substrate has a depth of 60 μm or less; The method further comprises: depositing an insulating layer dielectric on the second surface of the semiconductor substrate prior to the p-type doping of the second surface of the semiconductor substrate to leave an active pattern exposed on the second surface, and performing the p-type doping on the active pattern; depositing a first electrical contact on the first surface of the semiconductor substrate and depositing a second electrical contact on the second surface of the semiconductor substrate; The p-type dopant material is １０ A powder containing B, the microstructure is etched into the second surface of the semiconductor substrate using RIE; 10. The method of claim 1, wherein at least one of the microstructures etched into the second surface of the semiconductor substrate has a circular hole geometry, a square hole geometry, or a trench geometry.

16. The method according to any of claims 1 to 15, wherein the thermal neutron detection efficiency of the manufactured thermal neutron detector is about 12.5%.

17. The method according to any of claims 1 to 15, wherein the thermal neutron detection efficiency of the produced thermal neutron detector is about 21%.

18. The method according to any of the preceding claims, wherein the thermal neutron detection efficiency of the manufactured thermal neutron detector is in the range of 12.5% ​​to 21%.

19. A semiconductor substrate including a microstructure having a plurality of cavities on a first surface thereof, the semiconductor substrate comprising: an n-doped portion formed by n-type doping on a second surface of the semiconductor substrate opposite to the first surface; a p-doped portion formed on the first surface of the semiconductor substrate by p-type doping using a p-type dopant material; a conformal conductive layer formed by diffusing at least one element of the p-type dopant material into the semiconductor substrate through an inner surface of the cavity; Including, the p-type dopant material is filled and densified within the cavity; Each cavity of the microstructure in the first surface of the semiconductor substrate has a depth of 500 μm or less. A thermal neutron detector, wherein the p-type dopant material comprises boron and the at least one element of the p-type dopant material comprises boron.

20. The p-type dopant material is １０ 20. A thermal neutron detector as claimed in claim 19, comprising B.

21. 21. A thermal neutron detector as claimed in claim 19 or 20, further comprising a first electrical contact on the first surface of the semiconductor substrate and a second electrical contact on the second surface of the semiconductor substrate.

22. A thermal neutron detector according to any of claims 19 to 21, wherein at least one of the microstructures etched into the second surface of the semiconductor substrate has a circular hole geometry, a square hole geometry, or a trench geometry.

23. A thermal neutron detector as claimed in any one of claims 19 to 22, wherein each of the microstructures etched into the second surface of the semiconductor substrate has a circular hole geometry with an opening radius of 4 μm and a depth of 60 μm or less.

24. A thermal neutron detector according to any one of claims 19 to 23, wherein the thermal neutron detection efficiency of the thermal neutron detector is about 12.5%.

25. A thermal neutron detector according to any one of claims 19 to 23, wherein the thermal neutron detection efficiency of the thermal neutron detector is about 21%.

26. A thermal neutron detector according to any one of claims 19 to 23, wherein the thermal neutron detection efficiency of the thermal neutron detector is in the range of 12.5% ​​to 21%.

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