Display substrate and its manufacturing method, and display device

Abstract

A display substrate, a manufacturing method thereof, and a display device. The display substrate includes a display area (AA) and a peripheral area (NA), the peripheral area (NA) includes a first scan drive circuit (G1) and a second scan drive circuit (G2) located on a first side of the display area (AA), the peripheral area (NA) further includes a binding area (B) located on a second side of the display area (AA) adjacent to the first side, the peripheral area (NA) includes an organic insulating layer (101), the organic insulating layer (101) includes an elongated first groove (1011) that at least locally covers the first scan drive circuit (G1) and at least locally covers the second scan drive circuit (G2) and extends substantially along a first direction, thereby exposing a portion (G2) between the first scan drive circuit (G1) and the second scan drive circuit, the first groove (1011) further extends from the first side to a second side and extends to the second side substantially along a second direction, the second direction intersecting the first direction. The first groove (1011) in the peripheral area (NA) of the display substrate can effectively block the passage of impurities such as water and oxygen into the display area (AA), and further provides protection for the display area (AA) of the display substrate.

Description

[Technical field]

[0001] This application claims priority to Chinese patent application having application number 202010366290.7, filed on April 30, 2020, the entire contents of which are hereby incorporated by reference into this application.

[0002] An embodiment of the present disclosure relates to a display substrate, a manufacturing method thereof, and a display device. [Background technology]

[0003] OLED (Organic Light Emitting Diode) display devices have a series of advantages, such as self-luminance, high contrast, high resolution, wide viewing angle, low power consumption, fast response speed, and a manufacturing process compatible with thin film transistor (TFT) processes. As such, they have become one of the important development directions for the new generation of display devices, and are therefore attracting more and more attention.

[0004] In an OLED device, the structures located in the peripheral area other than the display area need to be reasonably designed in order to provide a certain protection for the structures in the display area, for example to prevent impurities in the external environment from entering the display area and adversely affecting the display effect of the display area. Summary of the Invention [Means for solving the problem]

[0005] At least one embodiment of the present disclosure provides a display substrate, the display substrate including a display area and a peripheral area located around the display area, the peripheral area including a first scan drive circuit and a second scan drive circuit located on a first side of the display area, the first scan drive circuit located on a side of the second scan drive circuit closer to the display area, the peripheral area further including a binding area located on a second side of the display area adjacent to the first side, the peripheral area including an organic insulating layer, the organic insulating layer including a first elongated groove at least locally covering the first scan drive circuit and at least locally covering the second scan drive circuit and extending substantially along a first direction, thereby exposing a portion between the first scan drive circuit and the second scan drive circuit, the first groove further extending from the first side to the second side, and extending to the second side substantially along a second direction, the second direction intersecting the first direction.

[0006] For example, a display substrate according to at least one embodiment of the present disclosure further includes a base substrate, the first scanning drive circuit, the second scanning drive circuit, and the organic insulating layer are disposed on the base substrate, the display substrate further includes a first power wiring located on the base substrate and located in the peripheral region, the first power wiring includes a first portion extending along the first direction on the second side and a second portion extending along the second direction, the first groove at least locally overlaps with the first portion of the first power wiring in a direction perpendicular to the base substrate, the organic insulating layer further includes a blocking wall located on an edge portion of the first portion of the first power wiring along the second direction, the first groove is separated at the blocking wall, and the blocking wall covers the edge portion of the first portion of the first power wiring along the second direction.

[0007] For example, a display substrate according to at least one embodiment of the present disclosure further includes a second power wiring located on the base substrate and located in the peripheral region, and in a direction perpendicular to the base substrate, the first groove does not overlap with the second power wiring.

[0008] For example, in a display substrate according to at least one embodiment of the present disclosure, the second power supply wiring is located on a side of the first power supply wiring away from the display area, the second power supply wiring includes a first portion extending along the first direction on the second side and a second portion extending along the second direction, and at least a portion of the first groove is between the second portion of the first power supply wiring and the second portion of the second power supply wiring.

[0009] For example, in the display substrate according to at least one embodiment of the present disclosure, a first portion of the first power supply wiring and a first portion of the second power supply wiring are electrically connected to the binding region.

[0010] For example, in a display substrate according to at least one embodiment of the present disclosure, the display area includes a pixel array, the pixel array includes a plurality of sub-pixels arranged in an array, each of the plurality of sub-pixels includes a row scanning signal, a row scanning signal end, a light emission control signal end and a data signal end for receiving a row scanning signal, a light emission control signal and a data signal, respectively, and is configured to operate based on the scanning signal, the light emission control signal and the data signal, the first scanning drive circuit is a row scanning drive circuit and is configured to provide the row scanning signal, and the second scanning drive circuit is a light emission scanning drive circuit and is configured to provide the light emission control signal.

[0011] For example, in a display substrate according to at least one embodiment of the present disclosure, the peripheral region further includes an electrostatic discharge circuit electrically connected to one end of the first scanning driving circuit and the second scanning driving circuit, respectively, and the first groove is such that a positive projection on a plane on which the electrostatic discharge circuit is located passes through the electrostatic discharge circuit, and in a direction perpendicular to the base substrate, the first groove does not expose the electrostatic discharge circuit.

[0012] For example, in a display substrate according to at least one embodiment of the present disclosure, a first width of a portion of the first groove on the first side is smaller than a second width of a portion of the first groove on the second side, and the second width is 2 to 3 times the first width.

[0013] For example, in a display substrate according to at least one embodiment of the present disclosure, the display region includes a pixel array, the pixel array includes a plurality of sub-pixels arranged in an array, each of the plurality of sub-pixels includes a light-emitting element and a pixel driving circuit, the pixel driving circuit is disposed on the base substrate, the display region further includes a planarization layer located on a side of the pixel driving circuit away from the base substrate, the light-emitting element is located on a side of the planarization layer away from the base substrate, and the organic insulating layer is disposed in the same layer as the planarization layer.

[0014] For example, in a display substrate according to at least one embodiment of the present disclosure, the first scan driving circuit, the second scan driving circuit and the electrostatic discharge circuit are disposed in the same layer as the pixel driving circuit.

[0015] For example, in a display substrate according to at least one embodiment of the present disclosure, the peripheral region further includes a first barrier wall located on a side of the second scanning driving circuit away from the display region, and the organic insulating layer further includes a second groove located between the second scanning driving circuit and the first barrier wall, and the second groove surrounds the periphery of the display region.

[0016] For example, in a display substrate according to at least one embodiment of the present disclosure, the peripheral region further includes a second barrier wall located on a side of the first barrier wall away from the display region, and the organic insulating layer further includes a third groove located between the first barrier wall and the second barrier wall, and the third groove surrounds the periphery of the display region.

[0017] For example, in a display substrate according to at least one embodiment of the present disclosure, the organic insulating layer further includes a fourth groove located on a side of the second barrier wall away from the display area, and the fourth groove surrounds the periphery of the display area.

[0018] For example, in a display substrate according to at least one embodiment of the present disclosure, the display region further includes a pixel definition layer located on a side of a planarization layer away from the pixel driving circuit, and a spacer layer located on a side of the pixel definition layer away from the planarization layer, and the first barrier wall is disposed in the same layer as at least a portion of the organic insulating layer, the pixel definition layer, and the spacer layer.

[0019] For example, in a display substrate according to at least one embodiment of the present disclosure, the second barrier wall is disposed in the same layer as at least a portion of the organic insulating layer, the pixel definition layer and the spacer layer, and in a direction perpendicular to the display substrate, the height of the second barrier wall is greater than the height of the first barrier wall.

[0020] For example, in a display substrate according to at least one embodiment of the present disclosure, the pixel driving circuit includes a thin film transistor, the thin film transistor includes a gate and a source / drain, and the first power wiring and the second power wiring are arranged in the same layer as the source / drain.

[0021] At least one embodiment of the present disclosure further provides a display device, which includes any one of the display substrates according to the embodiments of the present disclosure.

[0022] At least one embodiment of the present disclosure further provides a manufacturing method for a display substrate, the manufacturing method including: forming a display area and a peripheral area located around the display area; forming a first scan drive circuit and a second scan drive circuit located on a first side of the display area in the peripheral area; the first scan drive circuit is formed on a side of the second scan drive circuit closer to the display area, and forming a binding region in the peripheral area located on a second side of the display area adjacent to the first side; the manufacturing method further includes forming an organic insulating layer in the peripheral area, the organic insulating layer at least locally covers the first scan drive circuit, at least locally covers the second scan drive circuit, and includes a first elongated groove extending approximately along a first direction to expose a portion between the first scan drive circuit and the second scan drive circuit, the first groove extends from the first side to the second side, and extends to the second side approximately along a second direction, and the second direction intersects with the first direction.

[0023] For example, a manufacturing method of a display substrate according to at least one embodiment of the present disclosure includes providing a base substrate, wherein the first scanning drive circuit, the second scanning drive circuit, and the organic insulating layer are formed on the base substrate; and forming a first power wiring on the base substrate and in the peripheral region, wherein the first power wiring includes a first portion extending along the first direction on the second side and a second portion extending along the second direction, wherein in a direction perpendicular to the base substrate, the first groove at least locally overlaps with the first portion of the first power wiring, and the organic insulating layer further includes a blocking wall located on an edge portion of the first portion of the first power wiring along the second direction, the first groove being separated at the blocking wall, and the blocking wall covering the edge portion of the first portion of the first power wiring along the second direction.

[0024] For example, a manufacturing method for a display substrate according to at least one embodiment of the present disclosure further includes forming a second power wiring on the base substrate and in the peripheral region, and in a direction perpendicular to the base substrate, the first groove does not overlap with the second power wiring. [Brief description of the drawings]

[0025] In order to more clearly describe the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments are briefly introduced below. Obviously, the drawings in the following description do not limit the present disclosure, but are only related to some embodiments of the present disclosure.

[0026] [Figure 1] FIG. 2 is a schematic plan view of a display substrate. [Diagram 2] FIG. 2 is a schematic plan view of a portion of a display substrate according to at least one embodiment of the present disclosure. [Diagram 3] FIG. 13 is a schematic plan view of another portion of a display substrate according to at least one embodiment of the present disclosure. [Figure 4A] FIG. 2 is a schematic plan view of another portion of a display substrate according to at least one embodiment of the present disclosure. [Figure 4B] FIG. 2 is a schematic plan view of another portion of a display substrate according to at least one embodiment of the present disclosure. [Diagram 5] FIG. 2 is a circuit diagram of a pixel driving circuit of a display substrate according to at least one embodiment of the present disclosure. [Figure 6] FIG. 2 is a schematic cross-sectional view of a display area of ​​a display substrate according to at least one embodiment of the present disclosure. [Figure 7] FIG. 3 is a schematic cross-sectional view taken along line AA in FIG. 2. [Figure 8] FIG. 1 is a schematic plan view of a display substrate according to at least one embodiment of the present disclosure. [Figure 9] FIG. 3 is a schematic cross-sectional view taken along line BB in FIG. 2. [Figure 10A] FIG. 4 is an enlarged schematic view of the portion circled by the dashed line in FIG. [Figure 10B] FIG. 10B is a schematic cross-sectional view taken along line CC in FIG. 10A. [Figure 10C] FIG. 10B is a schematic cross-sectional view taken along line DD in FIG. 10A. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] In order to more clearly describe the objectives, technical solutions and advantages of the present disclosure, the technical solutions of the embodiments of the present disclosure will be described below clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is obvious that the described embodiments are only some embodiments of the present disclosure, and not all embodiments. Based on the described embodiments of the present disclosure, any other embodiments that a person skilled in the art can obtain without creative labor are all within the scope of protection of the present disclosure.

[0028] Unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meanings understood by those skilled in the art. The terms "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are merely used to distinguish different components. Similar terms such as "comprise" and "included" mean that the element or thing appearing before the term includes the element or thing listed after the term and their equivalents, but do not exclude other elements or things. Similar terms such as "connected" and "connected to each other" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "upper", "lower", "left", "right" and the like are merely used to indicate relative positional relationships, and when the absolute position of the described object is changed, the relative positional relationships may change accordingly.

[0029] The display area of ​​the OLED display substrate includes a driving circuit layer, a light emitting element, and a sealing layer covering the light emitting element, and the sealing layer protects the driving circuit layer and the light emitting element so as to prevent impurities in the external environment from entering the inside of the display area and damaging the structures of the driving circuit layer and the light emitting element. The inventors of the present disclosure have noticed that since the driving circuit layer and between the driving circuit layer and the display device generally have one or more insulating layers, when at least a part of these insulating layers is hydrophilic and has a crack, etc., the sealing layer is damaged, so that impurities such as external water and oxygen can enter the inside of the display area along the insulating layer, and further destroy the structures of the driving circuit layer and the light emitting element, forming an invalid area in the display area that cannot display normally, and the invalid area continues to expand.

[0030] In some embodiments, a groove is formed in the insulating layer to block the extension path through which impurities such as water and oxygen can enter the display area.

[0031] For example, FIG. 1 shows a schematic plan view of a display device, in which an insulating layer in a peripheral region other than the display region AA has a groove 1, and the groove 1 surrounds the upper side, left side, and right side of the display region AA, thereby blocking the extension path of impurities such as water and oxygen on the upper side, left side, and right side of the display region AA. In some embodiments, the insulating layer in the peripheral region further has a groove 2, and the groove 2 is located below the display region AA, thereby blocking the extension path of impurities such as water and oxygen on the lower side of the display region AA. However, since there are large areas between the groove 1 and the groove 2 where no groove is installed, there is a possibility that a diffusion path of impurities such as water and oxygen will be formed in these areas, which will cause a large risk of failure in the display region AA.

[0032] At least one embodiment of the present disclosure provides a display substrate, a manufacturing method thereof, and a display device, the display substrate including a display area and a peripheral area located around the display area, the peripheral area including a first scan drive circuit and a second scan drive circuit located on a first side of the display area, the first scan drive circuit located on a side of the second scan drive circuit close to the display area, the peripheral area further including a binding area located on a second side of the display area adjacent to the first side, the peripheral area including an organic insulating layer, the organic insulating layer including an elongated first groove at least locally covering the first scan drive circuit and at least locally covering the second scan drive circuit and extending substantially along a first direction to expose a portion between the first scan drive circuit and the second scan drive circuit, the first groove further extending from the first side to a second side, and extending to the second side substantially along the second direction, the second direction intersecting the first direction. The organic insulating layer in the peripheral region of the display substrate basically includes a first groove surrounding the periphery of the display region, which can effectively block the passage of impurities such as water and oxygen from entering the display region, and can protect the display region, and at least a part of the first groove is located between the first and second scan driving circuits in the peripheral region, so that the display region can be protected at a position closer to the display region.

[0033] Hereinafter, a display substrate, a manufacturing method thereof, and a display device according to embodiments of the present disclosure will be described in detail and non-limitingly with reference to several specific embodiments.

[0034] 2 shows a schematic plan view of a display substrate according to at least one embodiment of the present disclosure, and as shown in FIG. 2, the display substrate includes a display area AA and a peripheral area NA located around the display area. The peripheral area NA includes a first scanning drive circuit G1 and a second scanning drive circuit G2 located on a first side (e.g., the left side in the figure) of the display area AA, and a certain distance is provided between the first scanning drive circuit G1 and the second scanning drive circuit G2, the first scanning drive circuit G1 is located on the side of the second scanning drive circuit G2 close to the display area AA, and the peripheral area NA further includes a binding area B located on a second side (e.g., the lower side in the figure) of the display area AA adjacent to the first side, and the peripheral area NA includes an organic insulating layer 101, which at least locally covers the first scanning drive circuit G1 and at least locally covers the second scanning drive circuit G2, thereby protecting the circuit structure of the first scanning drive circuit G1 and the second scanning drive circuit G2. For example, the organic insulating layer 101 includes an elongated first groove 1011 extending substantially along a first direction (vertical direction in the figure) so as to expose a portion between the first scanning drive circuit G1 and the second scanning drive circuit G2, i.e., a portion of the organic insulating layer 101 located between the first scanning drive circuit G1 and the second scanning drive circuit G2 is removed to form the first groove 1011. For example, the first groove 1011 further extends from the first side to the second side, and extends on the second side substantially along the second direction, where the second direction intersects with the first direction.

[0035] For example, the first scanning drive circuit G1 and the second scanning drive circuit G2 are arranged along the first side, and for example, their respective extension lengths are approximately equivalent to the length of the display area AA on the first side. The first groove 1011 is formed in an elongated shape and extends between the first scanning drive circuit G1 and the second scanning drive circuit G2 approximately along the first direction.

[0036] For example, in some embodiments, the second direction is perpendicular to the first direction. For example, in the embodiment shown in FIG. 1, the first groove 1011 extends along the left edge of the display area AA to the first side, and the first groove 1011 extends from the first side to the second side, and then continues to extend along the lower edge of the display area AA to the second side. In this way, the first groove 1011 can achieve the technical effect of effectively blocking impurities such as water and oxygen from entering the display area AA around the display area AA.

[0037] For example, in some embodiments, the display substrate includes a base substrate, and structures such as the first scan driving circuit G1, the second scan driving circuit G2 and the organic insulating layer 101 are disposed on the base substrate.

[0038] For example, Figure 3 is an enlarged schematic diagram of the dashed frame on the right side in Figure 2. As shown in Figure 3, the display substrate is located on the base substrate and further includes a first power supply wiring 102 located in the peripheral area NA, and the first power supply wiring includes a first portion 102A extending along the first direction on the second side and a second portion 102B extending along the second direction. In a direction perpendicular to the base substrate, the first groove 1011 at least locally overlaps with the first portion 102A of the first power wiring, for example, the organic insulating layer 101 further includes a blocking wall 1012 located at an edge portion along the second direction of the first portion 102A of the first power wiring, and the first groove 1011 is separated at the blocking wall 1012, i.e., the portion of the organic insulating layer 101 located at the edge portion along the second direction of the first portion 102A of the first power wiring is not removed, and the material of the organic insulating layer 101 is retained, thereby forming the blocking wall 1012 that blocks the first groove 1011, and at this time, the blocking wall 1012 covers the edge portion along the second direction of the first portion 102A of the first power wiring. As a result, the blocking wall 1012 provides a protective effect for the edge portion along the second direction of the first portion 102A of the first power supply wiring, and prevents the material of the first power supply wiring 102 at said edge portion from being damaged during the manufacturing process of the display substrate, for example from being eroded by an etching solution.

[0039] 3, in some embodiments, the display substrate further includes a second power wiring 103 located on the base substrate and located in the peripheral region NA, and the first groove 1011 does not overlap the second power wiring 103 in a direction perpendicular to the base substrate. Thus, the first groove 1011 does not expose the second power wiring 103, and the organic insulating layer 101 covers the second power wiring 103 at least at the edge of the second power wiring 103, thereby protecting the second power wiring 103 and preventing the material of the second power wiring 103 from being damaged, for example, eroded by an etching solution, during the manufacturing process of the display substrate.

[0040] For example, in some embodiments, the first power supply wiring 102 is a wiring VDD for providing a high-level power supply signal, and the second power supply wiring 103 is a wiring VSS for providing a low-level power supply signal.

[0041] For example, Fig. 4A is an enlarged schematic diagram of the dashed line frame on the left side in Fig. 2, and as shown in Fig. 3 and Fig. 4A, the second power supply wiring 103 is located on the side away from the display area AA of the first power supply wiring 102. For example, the second power supply wiring 103 includes a first portion 103A extending along the first direction on the second side and a second portion 103B extending along the second direction, and at least a part of the first recessed groove 1011, for example, portion 1011B, is located between the second portion 102B of the first power supply wiring and the second portion 103B of the second power supply wiring.

[0042] 2, in some embodiments, the first portion 102A of the first power wiring and the first portion 103A of the second power wiring are electrically connected to the binding region B. For example, in FIG. 4A, the lower ends of the first portion 102A of the first power wiring and the first portion 103A of the second power wiring extend to the binding region B. For example, the binding region B includes a plurality of contact pads, and the lower ends of the first portion 102A of the first power wiring and the first portion 103A of the second power wiring are electrically connected (i.e., bound) to these contact pads, respectively, thereby binding the first power wiring 102 and the second power wiring 103 to the binding region B.

[0043] 2, in some embodiments, the display substrate further includes a driving circuit D, such as a chip IC or a flexible circuit board FPC, located on the side of the binding region B away from the display region AA, and the binding region B is electrically connected to the driving circuit D by a plurality of wires, thereby electrically connecting the first power wiring 102 and the second power wiring 103 to the driving circuit D, and further using the driving circuit D to provide electrical signals to the first power wiring 102 and the second power wiring 103. For example, the display substrate may be a flexible display substrate, and the driving circuit D may be bent and installed on the non-display side of the display substrate, thereby reducing the area of ​​the peripheral region on the display side of the display substrate, and further reducing the frame of the display substrate, thereby realizing a larger screen of the display substrate.

[0044] For example, Fig. 4B is a schematic plan view of a portion of the peripheral area NA located on the second side of the display area AA. In some embodiments, as shown in Fig. 4B, the first power wiring 102 is a wiring layer continuously arranged on the second side of the display area AA, so that the first portion 102A of the first power wiring 102 has two edges at both the left and right ends in the second direction. For example, the organic insulating layer 101 has a blocking wall 1012 at both of the two edges, and the first groove 1011 is separated at the two edges, so that the blocking wall 1012 protects the first power wiring 102 at the two edges.

[0045] For example, in some embodiments, the display substrate is a flexible display substrate, and further includes a folding region W between the display region AA and the binding region B, and the driving circuit D is installed on the non-display side of the display substrate by folding the folding region W. For example, the first portion 102A of the first power wiring 102 and the first portion 103A of the second power wiring are electrically connected to the binding region B by the folding region W. For example, the binding region B has a plurality of connection wirings, and the lower ends of the first portion 102A of the first power wiring 102 and the first portion 103A of the second power wiring are electrically connected to one end of the connection wiring in the folding region W, respectively, and the other ends of the connection wiring in the folding region W are electrically connected to the binding region B, thereby electrically connecting the first portion 102A of the first power wiring 102 and the first portion 103A of the second power wiring to the binding region B.

[0046] For example, in some embodiments, the display area AA of the display substrate includes a pixel array including a plurality of sub-pixels arranged in an array, each of the plurality of sub-pixels including a light-emitting element and a pixel driving circuit, and the pixel driving circuit includes a row scanning signal end, a light emission control signal end and a data signal end for receiving a row scanning signal, a light emission control signal and a data signal, respectively, and is configured to operate based on the row scanning signal, the light emission control signal and the data signal.

[0047] For example, the first scan driving circuit G1 is a row scan driving circuit configured to provide row scan signals, and the second scan driving circuit G2 is an emission scan driving circuit configured to provide emission control signals. For example, the first scan driving circuit G1 includes a plurality of cascaded first shift register units, each including a first scan signal output end, each of which corresponds to a plurality of rows of sub-pixels in the display area AA, and is connected to the row scan signal end of the sub-pixels by a corresponding conductor line. The second scan driving circuit G2 includes a plurality of cascaded second shift register units, each including a second scan signal output end, each of which corresponds to a plurality of rows of sub-pixels in the display area AA, and is connected to the emission control signal end of the sub-pixels by a corresponding conductor line.

[0048] The embodiments of the present disclosure do not limit the specific structures of the first scan driving circuit G1 and the second scan driving circuit G2. For example, the plurality of first shift register units included in the first scan driving circuit G1 or the plurality of second shift register units included in the second scan driving circuit G2 may have a 4T1C structure, i.e., include at least four transistors and one capacitor (FIG. 7 only shows one transistor for reference), thereby respectively realizing functions such as signal input, signal output, register reset, etc., and may include more transistors and / or capacitors, for example, by adding sub-circuits for realizing functions such as pull-up node control, pull-down node control, noise reduction, etc., to realize more stable input, output and reset.

[0049] In addition, the first scanning drive circuit and the second scanning drive circuit described in the embodiments of the present disclosure each include structures such as thin film transistors, capacitors, and connecting wiring between them, but do not include external signal wiring connected to the above structures of the first scanning drive circuit and the second scanning drive circuit.

[0050] For example, in some embodiments, the wiring in the peripheral area NA is arranged axially symmetrically. For example, as shown in FIG. 2, the display substrate further includes a first scanning drive circuit G1 and a second scanning drive circuit G2 located on a third side opposite to the first side of the display area AA, and together provide row scanning signals and light emission control signals to a plurality of sub-pixels. For example, the vertical center line of the display area AA in FIG. 2 is taken as the axis of symmetry, and the first scanning drive circuit G1 and the second scanning drive circuit G2 located on the first side and the third side are arranged axially symmetrically. For example, in some embodiments, the vertical center line of the display area AA in FIG. 2 is taken as the axis of symmetry, and the first power wiring 102 is arranged axially symmetrically on the second side of the display area AA, and the organic insulating layer 101 includes two blocking walls 1012 arranged axially symmetrically, and the first groove 1011 is blocked by the two blocking walls 1012.

[0051] For example, Figure 5 shows a circuit diagram of a pixel driving circuit. In some embodiments, as shown in Figure 5, the pixel driving circuit may be a 7T1C pixel driving circuit, including a plurality of thin film transistors T1, T2, T3, T4, T5, T6 and T7, a storage capacitor C, and has a row scanning signal end S, a light emission control signal end M and a data signal end D, which are respectively for receiving a row scanning signal, a light emission control signal and a data signal.

[0052] For example, the first gate of the first thin film transistor T1 is electrically connected to the third drain D3 of the third thin film transistor T3 and the fourth drain D4 of the fourth thin film transistor T4. The first source S1 of the first thin film transistor T1 is electrically connected to the second drain D2 of the second thin film transistor T2 and the fifth drain D5 of the fifth thin film transistor T5. The first drain D1 of the first thin film transistor T1 is electrically connected to the third source S3 of the third thin film transistor T3 and the sixth source S6 of the sixth thin film transistor T6.

[0053] For example, the second gate of the second thin film transistor T2 is configured at a row scanning signal end S to receive a row scanning signal, the second source S2 of the second thin film transistor T2 is configured at a data signal end D electrically connected to the data line to receive a data signal, and the second drain D2 of the second thin film transistor T2 is electrically connected to the first source S1 of the first thin film transistor T1.

[0054] For example, the third gate of the third thin film transistor T3 is configured at the row scanning signal end S to receive a row scanning signal, the third source S3 of the third thin film transistor T3 is electrically connected to the first drain D1 of the first thin film transistor T1, and the second drain electrode D3 of the second thin film transistor T3 is electrically connected to the first gate of the first thin film transistor T1.

[0055] For example, the fourth gate G4 of the fourth thin film transistor T4 is configured as a reset signal terminal to receive a reset signal, the fourth source S4 of the fourth thin film transistor T4 is configured to be electrically connected to the initialization line RL to receive an initialization signal, and the fourth drain D4 of the fourth thin film transistor T4 is electrically connected to the first gate of the first thin film transistor T1.

[0056] For example, the fifth gate of the fifth thin film transistor T5 is configured to be connected to the emission control signal terminal M to receive the emission control signal, the fifth source S5 of the fifth thin film transistor T5 is configured to be electrically connected to the first power supply wiring VDD to receive the first power supply signal, and the fifth drain D5 of the fifth thin film transistor T5 is electrically connected to the first source S1 of the first thin film transistor T1.

[0057] For example, the sixth gate of the sixth thin film transistor T6 is configured at the emission control signal terminal M to receive the emission control signal, the sixth source S6 of the sixth thin film transistor T6 is electrically connected to the first drain D1 of the first thin film transistor T1, and the sixth drain D6 of the sixth thin film transistor T6 is electrically connected to the anode layer of the light-emitting element EM.

[0058] For example, the seventh gate of the seventh thin film transistor T7 is configured as a reset signal terminal to receive a reset signal, the seventh source S7 of the seventh thin film transistor T7 is electrically connected to the anode layer of the light emitting element EM, and the seventh drain D7 of the seventh thin film transistor T7 is configured to be electrically connected to the initialization line RL to receive an initialization signal. For example, the seventh drain D7 of the seventh thin film transistor T7 can be connected to the fourth source S4 of the fourth thin film transistor T4 to realize electrical connection with the initialization line RL.

[0059] For example, the storage capacitor includes a first capacitor plate 1031 and a second capacitor plate 1032. The second capacitor plate 1032 is electrically connected to the first power supply line VDD, and the first capacitor electrode CE1 is electrically connected to the first gate of the first thin film transistor T1 and the third drain D3 of the third thin film transistor T3.

[0060] For example, the cathode layer of the light-emitting element EM is electrically connected to the second power supply wiring VSS.

[0061] One of the first power supply wiring VDD and the second power supply wiring VSS is a power supply wiring for providing a high voltage, and the other is a power supply wiring for providing a low voltage. For example, the first power supply wiring VDD provides a constant first voltage, which is a positive voltage. The second power supply wiring VSS provides a constant second voltage, which may be a negative voltage, etc. For example, in some examples, the second voltage may be a ground voltage. Also, the reset signal and the initialization signal may be the same signal. For example, the first scanning drive circuit G1 and the second scanning drive circuit G2 are electrically connected to the row scanning signal terminal S and the light emission control signal M, respectively, to provide a row scanning signal and a light emission control signal, respectively.

[0062] For example, in some embodiments, as shown in FIG. 4A, the peripheral area NA of the display substrate further includes an electrostatic discharge circuit E electrically connected to one end of the first scanning driving circuit G1 and the second scanning driving circuit G2, and the orthogonal projection of the first groove 1011 on the plane where the electrostatic discharge circuit E is located passes through the electrostatic discharge circuit, and the first groove 1011 does not expose the electrostatic discharge circuit E in the direction perpendicular to the base substrate. For example, the electrostatic discharge circuit E includes a portion disposed in the same layer as the source drain (described later) of the thin film transistor T of the pixel driving circuit, and the first groove 1011 does not overlap with the portion in the direction perpendicular to the base substrate. Thus, the organic insulating layer 101 further completely covers the electrostatic discharge circuit E, thereby protecting the circuit structure of the electrostatic discharge circuit E from being damaged, for example, eroded by an etching solution, during the manufacturing process of the display substrate. Since the electrical signals transmitted through the first scan driving circuit G1 and the second scan driving circuit G2 may have a large difference at different times, there may be residual signals when the signals change between high and low levels, and signal crosstalk may occur. An electrostatic discharge circuit is installed at one end of the first scan driving circuit G1 and the second scan driving circuit G2 to process the electrical signals of the first scan driving circuit G1 and the second scan driving circuit G2, and to eliminate such crosstalk.

[0063] 4A, in some embodiments, a first width of a portion 1011A on a first side of the first groove 1011 is smaller than a second width of a portion 1011B on a second side of the first groove 1011, and the second width is two to three times the first width. For example, in some examples, the first width of the portion 1011A on the first side of the first groove 1011 may be 9 μm to 11 μm, for example 10 μm, and the second width of the portion 1011B on the second side of the first groove 1011 may be 20 μm to 30 μm, for example 25 μm.

[0064] The width of the first groove 1011 means the size of the first groove 1011 in a direction perpendicular to the extension direction of the first groove 1011. Since the circuit arrangement on the first side of the display area AA is dense, the width of the portion 1011A on the first side of the first groove 1011 is narrow, and the area of ​​the first side of the peripheral area NA can be reduced, thereby realizing a narrow frame. Since the circuit arrangement on the second side of the display area AA is relatively sparse, the width of the portion 1011B on the second side of the first groove 1011 is increased, further improving the effect of the first groove 1011 in blocking impurities such as water and oxygen.

[0065] 6 shows a partial schematic cross-sectional view of one sub-pixel in the display area AA, and as shown in FIG. 6, each sub-pixel includes a light-emitting element EM and a pixel driving circuit, and the pixel driving circuit is disposed on the base substrate 110 and includes structures such as a thin-film transistor T (e.g., the above-mentioned sixth thin-film transistor T6) and a storage capacitor C. For example, the display area AA further includes a planarization layer 1016 located on the side of the pixel driving circuit away from the base substrate 110, and the light-emitting element EM is located on the side of the planarization layer 1016 away from the base substrate 110. For example, the organic insulating layer 101 in the peripheral area NA is disposed in the same layer as the planarization layer 1016.

[0066] In addition, in the embodiments of the present disclosure, "located in the same layer" means that the two functional or structural layers are formed in the same layer in the hierarchical structure of the display substrate and made of the same material, i.e., in the manufacturing process, the two functional or structural layers may be formed in the same material layer and can be patterned by the same patterning process to form the required patterns and structures.

[0067] For example, in some embodiments, the first scan driving circuit G1, the second scan driving circuit G2 and the electrostatic discharge circuit E are located on the same layer as the pixel driving circuit.

[0068] For example, as shown in FIG. 6, the thin film transistor T of the pixel driving circuit includes an active layer 1021, a gate 1022, a gate insulating layer 1014 (e.g., including a first gate insulating layer 1014A and a second gate insulating layer 1014B), an interlayer insulating layer 1015, and a source-drain electrode (including a source 1023 and a drain 1024) arranged in sequence on the base substrate 110. The storage capacitor C of the pixel driving circuit includes a first capacitor plate 1031 and a second capacitor plate 1032. The light emitting element EM includes an anode layer 1041, a light emitting layer 1042, and a cathode layer 1043. The anode layer 1041 is connected to the source 1023 of the thin film transistor through a via in the planarization layer 1016. For example, a first capacitor plate 1031 is located on the same layer as the gate 1022 , and a second capacitor plate 1032 is between the gate insulation layer 1014 and the interlayer insulation layer 1015 .

[0069] For example, FIG. 7 is a schematic cross-sectional view taken along line AA in FIG. 2, showing the cross-sectional configuration of the first scan driving circuit G1 and the second scan driving circuit G2. As shown in FIG. 7, the first scan driving circuit G1 includes structures such as a thin film transistor T10 and a wiring S10, and the second scan driving circuit G2 includes structures such as a thin film transistor T20 and a wiring S20. The thin film transistors T10 and T20 also have structures such as an active layer, a gate electrode, and a source / drain electrode. For example, the thin film transistors T10 and T20 are disposed in the same layer as the thin film transistor T in the pixel driving circuit, that is, the thin film transistors T10 and T20 are disposed in the same layer as the corresponding layer in the thin film transistor T of the pixel driving circuit. For example, the wiring S10 and the wiring S20 may be disposed in the same layer as the second capacitor plate 1032. This can simplify the manufacturing process of the display substrate. For example, in some embodiments, as shown in FIG. 2, the peripheral area NA of the display substrate may further include a first barrier wall 104 located on the side of the second scanning driving circuit G2 away from the display area AA, and the organic insulating layer 101 may further include a second groove 111 located between the second scanning driving circuit G2 and the first barrier wall 104, i.e., the second groove 111 is formed by removing a portion of the organic insulating layer 101 located between the second scanning driving circuit G2 and the first barrier wall 104. The second groove 111 surrounds the periphery of the display area AA, for example, the second groove 111 has an endless ring shape, thereby completely surrounding the periphery of the display area AA. As a result, the second groove 111 can achieve the technical effect of preventing impurities such as water and oxygen from entering the display area AA on the side of the first groove 1011 away from the display area AA.

[0070] For example, in some embodiments, as shown in FIG. 2, the peripheral area NA of the display substrate further includes a second barrier wall 105 located on the side of the first barrier wall 104 away from the display area AA, and the organic insulating layer 101 further includes a third groove 112 located between the first barrier wall 104 and the second barrier wall 105, i.e., the third groove 112 is formed by removing a portion of the organic insulating layer 101 located between the first barrier wall 104 and the second barrier wall 105. The third groove 112 surrounds the periphery of the display area AA, for example, the third groove 112 has an endless ring shape, thereby completely surrounding the periphery of the display area AA. Thus, the third groove 112 can achieve a multiple blocking effect together with the first groove 1011 and the second groove 111, thereby preventing impurities such as water and oxygen from entering the display area AA.

[0071] For example, in some embodiments, as shown in FIG. 2, the organic insulating layer 101 further includes a fourth groove 113 located on the side of the second barrier wall 105 away from the display area AA, that is, the part of the organic insulating layer 101 located on the side of the second barrier wall 105 away from the display area AA is removed to form the fourth groove 113. The fourth groove 113 surrounds the periphery of the display area AA. For example, the fourth groove 113 has an endless ring shape, thereby completely surrounding the periphery of the display area AA. Thus, as shown in FIG. 8, the fourth groove 113 can realize a multi-blocking effect around the display area AA together with the first groove 1011, the second groove 111 and the third groove 112, thereby preventing impurities such as water and oxygen from entering the display area AA, and further effectively protecting the internal structure of the display area AA.

[0072] 6, the display area AA further includes a pixel definition layer 1017 (for defining a plurality of sub-pixels) located on a side of the planarization layer 1016 away from the pixel driving circuitry, and a spacer layer 1018 located on a side of the pixel definition layer 1017 away from the planarization layer 1016. For example, the first barrier wall 104 is disposed in the same layer as at least a part of the planarization layer 1016, the pixel definition layer 1017, and the spacer layer 1018.

[0073] For example, in some embodiments, the second barrier wall 105 is disposed in the same layer as at least a portion of the planarization layer 1016, the pixel definition layer 1017 and the spacer layer 1018, and in a direction perpendicular to the display substrate 110, the height of the second barrier wall 105 is greater than the height of the first barrier wall 104.

[0074] For example, Fig. 9 is a schematic cross-sectional view taken along line BB in Fig. 2, thereby showing the cross-sectional structures of the first barrier wall 104 and the second barrier wall 105. As shown in Fig. 9, in one example, the first barrier wall 104 includes three sub-layers, which are disposed in the same layer as the organic insulating layer 101, the pixel defining layer 1017, and the spacer layer 1018, respectively. The second barrier wall 105 also includes three sub-layers, which are disposed in the same layer as the organic insulating layer 1016, the pixel defining layer 1017, and the spacer layer 1018, respectively. For example, the height of the first sub-layer 104A of the first barrier wall 104 is smaller than the height of the first sub-layer 105A of the second barrier wall 105, thereby making the overall height of the first barrier wall 104 smaller than the overall height of the second barrier wall 105. For example, the first sub-layer 104A of the first barrier wall 104 and the first sub-layer 105A of the second barrier wall 105 are both disposed in the same layer as the organic insulating layer 101, but the first sub-layer 104A of the first barrier wall 104 is thinned during the manufacturing process, so that the height of the first sub-layer 104A of the first barrier wall 104 is smaller than the height of the first sub-layer 105A of the second barrier wall 105. For example, in some examples, the height of the first barrier wall 104 is 0.8 μm to 1 μm, for example 0.9 μm, and the height of the second barrier wall 105 is 1.2 to 1.5 μm, for example 1.4 μm. As a result, the first barrier wall 104 and the second barrier wall 105 form barrier walls with different heights in the peripheral area NA, which extends the path through which impurities such as water and oxygen enter the display area AA, thereby achieving the effect of protecting the display area AA.

[0075] For example, in another embodiment, the first barrier wall 104 may be disposed in the same layer as the pixel defining layer 1017 and the spacer layer 1018, and the second barrier wall 105 may be disposed in the same layer as the organic insulating layer 1016, the pixel defining layer 1017, and the spacer layer 1018, such that the overall height of the first barrier wall 104 is smaller than the overall height of the second barrier wall 105. Or, the first barrier wall 104 may be disposed in the same layer as the organic insulating layer 1016 and the pixel defining layer 1017, and the second barrier wall 105 may be disposed in the same layer as the organic insulating layer 1016, the pixel defining layer 1017, and the spacer layer 1018, such that the overall height of the first barrier wall 104 is smaller than the overall height of the second barrier wall 105. The embodiments of the present disclosure are not limited to the specific manner of disposing the first barrier wall 104 and the second barrier wall 105.

[0076] For example, in some embodiments, the first power wiring 102 and the second power wiring 103 are disposed in the same layer as the source and drain of the thin film transistor T, thereby simplifying the manufacturing process of the display substrate. For example, the first power wiring 102, the second power wiring 103, and the source and drain of the thin film transistor T can adopt metal materials or alloy materials such as titanium, aluminum, copper, or molybdenum. For example, the first power wiring 102, the second power wiring 103, and the source and drain of the thin film transistor T can have a single-layer or multi-layer metal structure, for example a three-layer metal layer structure, such as titanium / aluminum / titanium, molybdenum / aluminum / molybdenum, titanium / copper / titanium, or molybdenum / copper / molybdenum, etc.

[0077] Because the middle layer in the three-layer structure, for example an aluminum layer, is relatively active, if the edges of the first power wiring 102 and the second power wiring 103 are exposed, an etchant used in a subsequent manufacturing process of the display substrate, for example an etchant used to etch the anode layer 1041 of the light emitting element EM, may etch the first power wiring 102 and the second power wiring 103, and further destroy the structures of the first power wiring 102 and the second power wiring 103. In the embodiment of the present disclosure, the organic insulating layer 101 in the peripheral area NA covers at least the edges of the first power wiring 102 and the second power wiring 103, thereby protecting the structures of the first power wiring 102 and the second power wiring 103.

[0078] For example, Fig. 10A shows the structure within the dashed circle in Fig. 3, and Fig. 10B is a schematic cross-sectional view taken along line CC in Fig. 10A. As shown in Fig. 10B, the blocking wall 1012 of the organic insulating layer 101 covers the edge of the first portion 102A of the first power supply wiring 102 along the second direction (i.e., the left edge in the figure). This prevents the active metal layer in the middle layer from being exposed when the first power supply wiring 102 has a three-layer metal structure, thereby avoiding the risk of etching.

[0079] For example, in some embodiments, as shown in FIG. 10B, the length of the blocking wall 1012 in the extension direction of the first groove 1011 (the horizontal direction in the figure) is 25 μm to 35 μm, for example 30 μm, the length of the portion where the blocking wall 1012 covers the first power supply wiring 102 (i.e., the portion of the first power supply wiring 102 located in the dashed line frame on the right side in the figure) is approximately 10 μm to 20 μm, for example 15 μm, and the length of the portion where the blocking wall 1012 does not cover the first power supply wiring 102 (i.e., the portion of the first power supply wiring 102 located in the dashed line frame on the left side in the figure) is approximately 10 μm to 20 μm, for example 15 μm.

[0080] For example, FIG. 10C is a schematic cross-sectional view taken along line DD in FIG. 10A. As shown in FIGS. 10B and 10C, the display substrate further includes a wiring L1 and a wiring L2 located on the side of the first power supply wiring 102 closer to the base substrate 110. For example, the wiring L1 and the wiring L2 are electrically connected to the first scanning drive circuit G1 and the second scanning drive circuit G2, respectively, and are for providing electrical signals to the first scanning drive circuit G1 and the second scanning drive circuit G2. For example, the wiring L1 is disposed in the same layer as the second capacitor plate 1032 of the storage capacitor C, and the wiring L2 is disposed in the same layer as the gate 1022 of the thin film transistor T and the first capacitor plate 1031 of the storage capacitor C. This simplifies the manufacturing process of the display substrate.

[0081] 6, in some embodiments, the display substrate may further include a blocking layer 1112 and a buffer layer 1013 disposed on the base substrate 110, the blocking layer 1112 can prevent impurities such as water and oxygen from penetrating into functional structures such as thin film transistors T from the base substrate 110, and the buffer layer 1013 can provide a flat surface to facilitate the installation of other functional layers of the display substrate. The blocking layer 1112 and the buffer layer 1013 can both play a role in protecting other functional structures on the base substrate 110.

[0082] 6, the display substrate may further include a sealing layer EN, which includes a first inorganic sealing layer 1051, a first organic sealing layer 1052, and a second inorganic sealing layer 1053, which are sequentially stacked on a base substrate 110. Thus, the sealing layer EN forms a multi-layer seal with respect to the display substrate, and can protect the display substrate.

[0083] For example, in some embodiments, the base substrate 110 may be a flexible substrate such as polyimide (PI). For example, the materials of the gate 1022, the first capacitor plate 1031 and the second capacitor plate 1032 include metal or alloy materials such as aluminum, titanium, cobalt, copper, etc. The active layer 1021 may include materials such as polysilicon and metal oxide. The blocking layer 1112, the buffer layer 1013, the gate insulating layer 1014 (including the first gate insulating layer 1014A and the second gate insulating layer 1014B), the interlayer insulating layer 1015, and the first inorganic sealing layer 1051 and the second inorganic sealing layer 1053 of the encapsulation layer EN may include inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. For example, the planarization layer 1016, the organic insulating layer 101, the pixel definition layer 1017, the spacer layer 1018, and the first organic encapsulation layer 1052 of the encapsulation layer EN may employ organic insulating materials such as polyimide, resin, etc. The embodiments of the present disclosure do not limit the materials of each functional layer, and the materials of each functional layer are not limited to the above examples.

[0084] At least one embodiment of the present disclosure further provides a display device, which includes any one of the display substrates according to the embodiments of the present disclosure. The display device may be a product or part having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital camera, a navigation system, etc. The embodiments of the present disclosure do not limit the type of the display device.

[0085] At least one embodiment of the present disclosure further provides a method for manufacturing a display substrate, the method including forming a display area and a peripheral area located around the display area, the forming the peripheral area includes forming a first scan driving circuit and a second scan driving circuit located on a first side of the display area in the peripheral area, the first scan driving circuit is formed on a side of the second scan driving circuit close to the display area, and a binding area is formed on a second side of the display area adjacent to the first side in the peripheral area, the method further includes forming an organic insulating layer in the peripheral area, the organic insulating layer includes a first elongated groove at least locally covering the first scan driving circuit and at least locally covering the second scan driving circuit and extending substantially along a first direction to expose a portion between the first scan driving circuit and the second scan driving circuit, the first groove extends from the first side to the second side and extends along the second direction to the second side, the second direction intersects with the first direction.

[0086] For example, in some embodiments, a manufacturing method for a display substrate includes providing a base substrate, wherein a first scanning driving circuit, a second scanning driving circuit, and an organic insulating layer are formed on the base substrate; and forming a first power wiring on the base substrate and in the peripheral region, wherein the first power wiring includes a first portion extending along a first direction to a second side and a second portion extending along the second direction, wherein in a direction perpendicular to the base substrate, the first groove at least locally overlaps with the first portion of the first power wiring, and the organic insulating layer further includes a blocking wall located on an edge portion of the first portion of the first power wiring along the second direction, wherein the first groove is separated at the blocking wall, and the blocking wall covers the edge portion of the first portion of the first power wiring along the second direction.

[0087] For example, in some embodiments, the method for manufacturing a display substrate further includes forming a second power wiring on the base substrate and in the peripheral region, where the first groove does not overlap with the second power wiring in a direction perpendicular to the base substrate.

[0088] For example, in some embodiments, as shown in FIG. 6 , the display region includes a pixel array, the pixel array includes a plurality of sub-pixels arranged in an array, each of the plurality of sub-pixels includes a light-emitting element and a pixel driving circuit, the pixel driving circuit is formed on a base substrate, a planarization layer is formed on a side of the pixel driving circuit away from the base substrate, and the light-emitting element is formed on a side of the planarization layer away from the base substrate, for example, an organic insulating layer in the peripheral region is formed in the same layer as the planarization layer, for example adopting the same material layer and formed by the same patterning process, thereby simplifying the manufacturing process of the display substrate.

[0089] For example, the primary patterning process includes steps of forming a photoresist, exposing, developing, and etching, etc. The embodiments of the present disclosure do not specifically limit the manner in which each of the constituent layers and the functional layers is formed.

[0090] For example, in some embodiments, the pixel driving circuit includes a thin film transistor, the thin film transistor includes structures such as a gate and a source / drain, and the first power wiring and the second power wiring are disposed in the same layer as the source / drain.

[0091] For example, in some embodiments, the first scan driving circuit, the second scan driving circuit and the electrostatic discharge circuit are formed in the same layer as the pixel driving circuit, as shown in Figures 6 and 7. For example, the first scan driving circuit and the second scan driving circuit each include a thin film transistor, and the thin film transistors of the first scan driving circuit and the second scan driving circuit are formed in the same layer as the corresponding layer of the thin film transistor of the pixel driving circuit.

[0092] For example, in some embodiments, as shown in Figures 2, 6 and 9, forming the peripheral region further includes forming a first barrier wall on a side of the second scanning driving circuit away from the display area, and the organic insulating layer forms a second groove between the second scanning driving circuit and the first barrier wall, and the second groove surrounds the periphery of the display area.

[0093] For example, forming the peripheral region further includes forming a second barrier wall on a side of the first barrier wall away from the display region, and the organic insulating layer forms a third groove between the first barrier wall and the second barrier wall, and the third groove surrounds the periphery of the display region.

[0094] For example, the organic insulating layer further defines a fourth groove on a side of the second barrier wall away from the display area, and the fourth groove surrounds the periphery of the display area.

[0095] For example, forming the display area further includes forming a pixel definition layer on a side of the planarization layer away from the pixel driving circuit, and forming a spacer layer on a side of the pixel definition layer away from the planarization layer, and the first barrier wall is formed in the same layer as at least a part of the organic insulating layer, the pixel definition layer, and the spacer layer. For example, the second barrier wall is formed in the same layer as at least a part of the organic insulating layer, the pixel definition layer, and the spacer layer, and the height of the second barrier wall is higher than the height of the first barrier wall in a direction perpendicular to the display substrate. The specific aspects of the first barrier wall and the second barrier wall can be referred to the above examples, and the description will be omitted here.

[0096] In the display substrate according to the embodiment of the present disclosure, or the display substrate obtained by using the manufacturing method according to the embodiment of the present disclosure, the organic insulating layer in the peripheral region of the display substrate basically includes a first groove surrounding the periphery of the display region, and the first groove can effectively block the passage of impurities such as water and oxygen into the display region, and further provide a protective effect for the display region. In addition, at least a part of the first groove is located between the first scanning driving circuit and the second scanning driving circuit in the peripheral region, so that the display region can be protected at a position closer to the display region. In addition, the first groove does not expose the edges of the first power wiring and the second wiring located below the organic insulating layer, so that the organic insulating layer can further effectively protect the first power wiring and the second power wiring. In addition, the peripheral region further includes structures such as a second groove, a third groove, a fourth groove, a first barrier wall, and a second barrier wall, and these structures, together with the first groove, can effectively prevent impurities such as water and oxygen from entering the display region, thereby protecting the display region and improving the reliability of the display substrate.

[0097] The following points require further clarification:

[0098] (1) The drawings of the embodiments of the present disclosure relate only to the structures of the embodiments of the present disclosure, and other structures may refer to conventional designs.

[0099] (2) For clarity, in the figures illustrating the embodiments of the present disclosure, the thicknesses of layers or regions are expanded or reduced, i.e., the figures are not drawn to scale. It is understood that when an element such as a layer, film, region, or substrate is referred to as being located "on" or "below" another element, the element may be located "directly" on or "below" the other element, or intermediate elements may be present.

[0100] (3) Where there are no conflicts, the embodiments and features of the embodiments of the present disclosure can be combined with each other to obtain new embodiments.

[0101] The above are merely specific embodiments of the present disclosure, and the scope of protection of the present disclosure is not limited thereto, but should be based on the scope of protection of the claims. [Explanation of symbols]

[0102] 101 Organic insulating layer 1011 First groove AA display area B Binding region G1 First scan driver circuit G2 Second scan driver circuit NA peripheral area

Claims

1. A display substrate including a display area and a peripheral area located around the display area, the peripheral region includes a first scan drive circuit and a second scan drive circuit located on a first side of the display region, the first scan drive circuit being located on a side of the second scan drive circuit closer to the display region, the peripheral region further includes a binding region located on a second side of the display region adjacent to the first side; the peripheral region includes an organic insulating layer, the organic insulating layer at least locally covers the first scan driving circuit, at least locally covers the second scan driving circuit, and includes a first elongated groove extending substantially along a first direction, thereby exposing a portion between the first scan driving circuit and the second scan driving circuit; The first groove further extends from the first side to the second side and extends toward the second side substantially along a second direction, the second direction intersecting the first direction; Further comprising a base substrate; the first scanning driving circuit, the second scanning driving circuit, and the organic insulating layer are disposed on the base substrate; the display substrate further includes a first power supply wiring located on the base substrate and located in the peripheral region, the first power supply wiring including a first portion extending along the first direction on the second side and a second portion extending along the second direction, a first portion of the first power supply wiring and a second portion of the first power supply wiring, the first portion of the first power supply wiring being electrically connected to the first insulating layer, the first portion of the first power supply wiring being electrically connected to the first insulating layer, the first portion of the first power supply wiring being electrically connected to the first insulating layer, the second portion of the first power supply wiring being electrically connected to the first insulating layer,

2. a second power supply wiring located on the base substrate and located in the peripheral region; The display substrate according to claim 1 , wherein the first groove does not overlap the second power wiring in a direction perpendicular to the base substrate.

3. the second power supply wiring is located on a side of the first power supply wiring that is away from the display area, and the second power supply wiring includes a first portion that extends along the first direction on the second side, and a second portion that extends along the second direction; The display substrate according to claim 2 , wherein at least a portion of the first groove is located between the second portion of the first power supply line and the second portion of the second power supply line.

4. The display substrate of claim 3 , wherein the first portion of the first power supply wiring and the first portion of the second power supply wiring are electrically connected to the binding region.

5. the display area includes a pixel array, the pixel array includes a plurality of sub-pixels arranged in an array, each of the plurality of sub-pixels includes a row scanning signal end, a light emission control signal end and a data signal end for receiving a row scanning signal, a light emission control signal and a data signal, respectively, and is configured to operate based on the row scanning signal, the light emission control signal and the data signal; the first scan drive circuit is a row scan drive circuit and is configured to provide the row scan signal; The display substrate according to claim 1 , wherein the second scanning drive circuit is a light emission scanning drive circuit, and is configured to provide the light emission control signal.

6. the peripheral region further includes an electrostatic discharge circuit electrically connected to one end of the first scan driving circuit and one end of the second scan driving circuit, A display substrate according to any one of claims 2 to 4, wherein a positive projection of the first groove on a plane in which the electrostatic discharge circuit is located passes through the electrostatic discharge circuit, and in a direction perpendicular to the base substrate, the first groove does not expose the electrostatic discharge circuit.

7. A display substrate as described in any one of claims 1 to 4, wherein a first width of a portion of the first groove on the first side is smaller than a second width of a portion of the first groove on the second side, and the second width is 2 to 3 times the first width.

8. the display region includes a pixel array, the pixel array includes a plurality of sub-pixels arranged in an array, each of the plurality of sub-pixels includes a light-emitting element and a pixel driving circuit; the pixel driving circuit is disposed on the base substrate, the display region further includes a planarization layer located on a side of the pixel driving circuit away from the base substrate, the light emitting element is located on a side of the planarization layer away from the base substrate, The display substrate according to claim 6 , wherein the organic insulating layer is disposed in the same layer as the planarizing layer.

9. The display substrate of claim 8 , wherein the first scan driving circuit, the second scan driving circuit and the electrostatic discharge circuit are disposed on the same layer as the pixel driving circuit.

10. the peripheral region further includes a first barrier wall located on a side of the second scan driving circuit away from the display region; 10. The display substrate of claim 8, wherein the organic insulating layer further includes a second groove located between the second scanning driving circuit and the first barrier wall, the second groove surrounding the periphery of the display area.

11. the peripheral region further includes a second barrier wall located on a side of the first barrier wall away from the display region, The display substrate of claim 10 , wherein the organic insulating layer further includes a third groove located between the first barrier wall and the second barrier wall, the third groove surrounding the periphery of the display area.

12. The display substrate of claim 11 , wherein the organic insulating layer further includes a fourth groove located on a side of the second barrier wall away from the display area, the fourth groove surrounding the periphery of the display area.

13. the display region further includes a pixel definition layer located on a side of a planarization layer away from the pixel driving circuit, and a spacer layer located on a side of the pixel definition layer away from the planarization layer; 13. The display substrate of claim 11, wherein the first barrier wall is disposed in the same layer as at least a part of the organic insulating layer, the pixel defining layer and the spacer layer.

14. 14. The display substrate of claim 13, wherein the second barrier wall is disposed in the same layer as at least a portion of the organic insulating layer, the pixel defining layer, and the spacer layer, and the height of the second barrier wall is greater than the height of the first barrier wall in a direction perpendicular to the display substrate.

15. The pixel driving circuit includes a thin film transistor, the thin film transistor includes a gate and a source drain; 15. The display substrate according to claim 8, wherein the first power supply wiring and the second power supply wiring are provided in the same layer as the source / drain.

16. A display device comprising a display substrate according to any one of claims 1 to 15.

17. A method for manufacturing a display substrate, the method comprising the steps of: forming a display area and a peripheral area around the display area; forming a first scan drive circuit and a second scan drive circuit in the peripheral area, the first scan drive circuit being formed on a side of the second scan drive circuit closer to the display area; and forming a binding area in the peripheral area, the binding area being located on a second side of the display area adjacent to the first side. The manufacturing method further includes forming an organic insulating layer in the peripheral region, the organic insulating layer at least locally covering the first scan drive circuit, at least locally covering the second scan drive circuit, and including an elongated first groove extending substantially along a first direction, thereby exposing a portion between the first scan drive circuit and the second scan drive circuit, the first groove extending from the first side to the second side, and extending to the second side substantially along a second direction, the second direction intersecting the first direction, providing a base substrate, the first scan driving circuit, the second scan driving circuit and the organic insulating layer being formed on the base substrate; forming a first power supply wiring on the base substrate and in the peripheral region, the first power supply wiring including a first portion extending along the first direction on the second side and a second portion extending along the second direction; a first insulating layer that is formed on the first power supply wiring and a second insulating layer that is formed on the first power supply wiring, the first insulating layer being separated from the first insulating layer by a first insulating layer, the first insulating layer being separated from the first insulating layer by a first insulating layer, the second insulating layer being separated from the first insulating layer by a first insulating layer,

18. forming a second power supply wiring on the base substrate and in the peripheral region; The method of claim 17 , wherein the first groove does not overlap the second power wiring in a direction perpendicular to the base substrate.

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