Display device

Abstract

To provide a display device with less bright spot defects.SOLUTION: A display device according to an exemplary embodiment of the present disclosure comprises a substrate, a plurality of sub pixels provided on the substrate, a light-emitting element provided on one of the sub pixels, and a pixel circuit provided on the sub pixel to drive the light-emitting element. The pixel circuit comprises: a driving transistor having a gate electrode with a dual gate structure, a source electrode, and a drain electrode, the driving transistor being connected between a high-potential power line and the light-emitting element; and a capacitor connected between the high-potential power line and a node between the source electrode and the drain electrode of the driving transistor.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present specification relates to a display device, and more particularly to a display device with improved bright spot defects. [Background technology]

[0002] Display devices used in computer monitors, TVs, mobile phones, etc. include organic light emitting displays (OLEDs), which emit light themselves, and liquid crystal displays (LCDs), which require a separate light source.

[0003] Display devices are now used in a wide variety of applications, including not only computer monitors and TVs but also personal portable devices. Research is currently underway into display devices that have a large display area while being reduced in volume and weight.

[0004] Meanwhile, the display device includes a plurality of sub-pixels, which are the smallest units constituting a screen, and the plurality of sub-pixels include light emitting elements and driving transistors for driving the light emitting elements. However, there may be characteristic deviations of the driving transistors of the plurality of sub-pixels, or the luminance between the sub-pixels may be non-uniform due to deterioration of the light emitting elements, etc. Therefore, it is possible to internally sense and compensate for the deviations between the sub-pixels by adding a plurality of transistors and capacitors to each of the plurality of sub-pixels. Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a display device that reduces fluctuations in node voltage between a source electrode and a drain electrode of a driving transistor due to a kickback phenomenon when a switching transistor is turned off.

[0006] Another object of the present invention is to provide a display device that minimizes fluctuations in the gate-source voltage of a driving transistor due to a kickback phenomenon during a holding period.

[0007] Still another problem to be solved by the present specification is to provide a display device in which leakage current from a drive transistor is reduced during a holding period.

[0008] It is still another object of the present invention to provide a display device that reduces voltage fluctuations in the gate electrodes of driving transistors and the resulting bright spot defects.

[0009] The subject of the present specification is not limited to the subject mentioned above, and other subjects not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0010] In order to solve the above-mentioned problems, a display device according to an embodiment of the present specification includes a substrate, a plurality of sub-pixels on the substrate, a light-emitting element on one of the plurality of sub-pixels, and a pixel circuit provided on the sub-pixel for driving the light-emitting element, the pixel circuit including a gate electrode, a source electrode, and a drain electrode having a dual gate structure, a driving transistor connected between a high potential power supply wiring and the light-emitting element, and a capacitor connected between a node between the source electrode and the drain electrode of the driving transistor and the high potential power supply wiring. Thus, a capacitor for buffering voltage fluctuations of a fifth node can be formed to reduce gate-source voltage fluctuations of the driving transistor.

[0011] In one embodiment, a display device includes a substrate, a plurality of subpixels on the substrate, a light-emitting element on a subpixel among the plurality of subpixels, and a pixel circuit provided on the subpixel and configured to operate the light-emitting element, the pixel circuit including an active layer, a gate electrode on the active layer, a drive transistor including a source electrode and a drain electrode electrically connected to the active layer, the drive transistor being connected between a high potential power supply line and the light-emitting element, and a capacitor including a first capacitor electrode connected to the high potential power supply line and a second capacitor electrode connected to a node between the source electrode and the drain electrode of the drive transistor, the first capacitor electrode overlapping a portion of the active layer.

[0012] Further details of the embodiments are included in the detailed description and the drawings. Effect of the Invention

[0013] The present invention can reduce the fluctuation in voltage of the gate electrode of the driving transistor due to the kickback phenomenon when the switching transistor is turned off.

[0014] The present specification can reduce the fluctuation of the drive current supplied from the drive transistor to the light emitting element.

[0015] The present disclosure can reduce the gate-source voltage fluctuation of the drive transistor during the hold period.

[0016] The present disclosure can reduce the decrease in voltage of the gate electrode of the drive transistor during the hold period.

[0017] The present invention can reduce the voltage fluctuation of the gate electrode of the driving transistor during the holding period, and reduce bright spot defects during the light emission period.

[0018] The effects of the present specification are not limited to the above-mentioned examples, and various other effects are included in the present specification. [Brief description of the drawings]

[0019] [Figure 1] FIG. 1 is a plan view of a display device according to an embodiment of the present specification. [Diagram 2] FIG. 2 is a circuit diagram of a sub-pixel of a display device according to an embodiment of the present specification. [Diagram 3] 1 is a driving timing diagram of a sub-pixel of a display device according to an embodiment of the present specification. [Figure 4] 13 is a graph comparing the off-state current of a transistor with a single gate structure and a transistor with a dual gate structure. [Diagram 5] 1 is a schematic cross-sectional view of a display device according to an embodiment of the present specification. [Figure 6] FIG. 11 is a schematic cross-sectional view of a display device according to a comparative example. [Figure 7a] FIG. 11 is a waveform diagram showing a voltage change at a fifth node of a display device according to a comparative example and an example of this specification. [Figure 7b] 11 is a waveform diagram showing a voltage change at a second node of a display device according to a comparative example and an example of this specification. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] The advantages and features of the present invention, and the methods for achieving the same, will become apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be embodied in various different forms, and the embodiments are provided solely for the purpose of making the disclosure of the present invention complete and fully conveying the scope of the invention to those skilled in the art to which the present invention pertains.

[0021] The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of this specification are illustrative, and the specification is not limited to the matters illustrated. The same reference symbols refer to the same components throughout the specification. In addition, in explaining this specification, if it is determined that a specific description of related known technology may unnecessarily cloud the gist of this specification, the detailed description will be omitted. When "includes," "has," "is made," etc. are used in this specification, other parts may be added since "only" is not used. When a component is expressed in the singular, it includes the case where it includes a plural, unless otherwise expressly stated.

[0022] When interpreting elements, they are interpreted as including a margin of error even if there is no other explicit description.

[0023] When describing a positional relationship, for example when describing the positional relationship of two parts using "on top of," "at the top of," "at the bottom of," "next to," etc., one or more other parts may be located between the two parts, so long as "immediately" or "directly" is not used.

[0024] When an element or layer is referred to as "on" another element or layer, this includes the case where the element or layer is directly on top of the other element, or has other layers or elements interposed therebetween.

[0025] In addition, although the terms "first", "second" and the like are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, the first component referred to below may be the second component within the technical concept of this specification.

[0026] Like reference numbers refer to like elements throughout the specification.

[0027] The area and thickness of each component shown in the drawings are shown for convenience of explanation, and the present specification is not necessarily limited to the area and thickness of the components shown.

[0028] The features of the various embodiments of this specification may be combined or combined with each other, either partially or in whole, and may be technically interlocked and driven in various ways, and each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

[0029] Various embodiments of the present specification will now be described in detail with reference to the accompanying drawings.

[0030] 1 is a plan view of a display device according to an embodiment of the present disclosure, in which only a substrate 110 and a plurality of sub-pixels SP are shown among various components of a display device 100 for ease of explanation.

[0031] The substrate 110 is a component for supporting various components included in the display device 100 and may be made of an insulating material. For example, the substrate 110 may be made of glass or resin. The substrate 110 may also be made of a polymer or plastic such as polyimide (PI), polyethylene terephthalate (PET), acrylonitrile-butadiene-styrene copolymer (ABS), polymethyl methacrylate (PMMA), polyethylene naphthalate (PEN), polycarbonate (PC), polyethersulfone (PES), polyarylate (PAR), polysulfone (PSF), or cycloolefin copolymer, cyclic olefin copolymer (COC), triacetyl cellulose (TAC) film, polyvinyl alcohol (PVA) film, polystyrene (PS), etc., and may be made of a material having flexibility.

[0032] The substrate 110 includes a display area AA and a non-display area NA.

[0033] The display area AA is an area in which a plurality of sub-pixels SP are arranged and an image is displayed. Each of the sub-pixels SP is an individual unit that emits light, and a light-emitting element and a pixel circuit may be formed in each of the sub-pixels SP. The light-emitting element may vary depending on the type of the display device 100. For example, when the display device 100 is an organic light-emitting display device, the light-emitting element may be an organic light-emitting element including an anode, an organic layer, and a cathode. In addition, a micro LED (light-emitting diode), a quantum dot light-emitting diode (QLED) including a quantum dot (QD), or the like may be used as the light-emitting element. The light-emitting element may be an inorganic light-emitting diode.

[0034] The non-display area NA is an area where no image is displayed. The non-display area NA is adjacent to the display area AA. More specifically, the non-display area NA is adjacent to the display area AA so as to surround the display area AA. The non-display area NA is an area where various wirings, driving ICs, etc. for driving the sub-pixels SP arranged in the display area AA are arranged. For example, various ICs and driving circuits such as gate driver ICs and data driver ICs may be arranged in the non-display area NA. Meanwhile, the non-display area NA may be located on the rear surface of the substrate 110, i.e., on the surface where the sub-pixels SP are not present, or may be omitted, and is not limited to what is shown in the drawings.

[0035] In the following, the sub-pixels SP will be described in more detail with reference to FIGS.

[0036] Fig. 2 is a circuit diagram of a sub-pixel of a display device according to an embodiment of the present specification. Fig. 3 is a driving timing diagram of a sub-pixel of a display device according to an embodiment of the present specification.

[0037] Referring to FIG. 2, each of the sub-pixels SP includes a light-emitting element EL and a pixel circuit for driving the light-emitting element EL. The pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a driving transistor DT, a first capacitor C1, and a second capacitor C2. This can be called a "6T2C" structure because it includes six transistors and two capacitors. The embodiments of the present disclosure are not limited thereto. For example, more transistors and capacitors may be included, or some transistors and capacitors may be omitted or combined with other transistors and capacitors.

[0038] Each of the multiple sub-pixels SP is connected to a first scan wiring that supplies a first scan signal Scan1, a second scan wiring that supplies a second scan signal Scan2, a data wiring that supplies a data voltage Vdata, an emission control wiring that supplies a light emission control signal EM, a reference wiring that supplies a reference voltage Vref, an initialization wiring that supplies an initialization voltage Vini, a high potential power supply wiring that supplies a high potential power supply voltage VDD, and a low potential power supply wiring that supplies a low potential power supply voltage VSS.

[0039] Meanwhile, the transistors of the sub-pixels SP may be different types of transistors. For example, one of the transistors may be a transistor having an oxide semiconductor as an active layer. The oxide semiconductor material has a low off-current, and is therefore suitable for a switching transistor that has a short turn-on time and maintains a long turn-off time.

[0040] As another example, another of the plurality of transistors may be a transistor having a low temperature polysilicon (LTPS) active layer. Polysilicon material has high mobility, low power consumption, and excellent reliability, and therefore may be suitable for use as a driving transistor.

[0041] The plurality of transistors may be N-type transistors or P-type transistors. In an N-type transistor, the carriers are electrons, so that electrons can flow from the source electrode to the drain electrode, and a current can flow from the drain electrode to the source electrode. In a P-type transistor, the carriers are holes, so that holes can flow from the source electrode to the drain electrode, and a current can flow from the source electrode to the drain electrode. For example, one of the plurality of transistors may be an N-type transistor, and another of the plurality of transistors may be a P-type transistor.

[0042] In the following description, it is assumed that the transistors are P-type transistors, but this is not intended to be limiting.

[0043] First, the first transistor T1 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the first transistor T1 is connected to the first scan line, and the source electrode and the drain electrode are connected between the data line and a first node N1. The first transistor T1 is turned on by a first scan signal Scan1 of a low level to transmit a data voltage Vdata to the first node N1.

[0044] The second transistor T2 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the second transistor T2 is connected to the second scan line, and the source electrode and the drain electrode are connected to the second node N2 and the third node N3, respectively. In one embodiment, as shown in FIG. 2, the second transistor T2 has a dual gate structure. The second transistor T2 can be turned on by a low level second scan signal Scan2 to electrically connect the second node N2 and the third node N3 together. Thus, the driving transistor DT can be diode-connected by the turned-on second transistor T2, and the threshold voltage of the driving transistor DT can be sensed.

[0045] The third transistor T3 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the third transistor T3 is connected to a light emission control wiring (e.g., a light emission wiring), and the source electrode and the drain electrode are connected to the reference wiring and the first node N1. The third transistor T3 is turned on by a low-level light emission control signal EM to transmit the reference voltage Vref to the first node N1.

[0046] The fourth transistor T4 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the fourth transistor T4 is connected to the light emission control line, the source electrode is connected to the third node N3, and the drain electrode is connected to the fourth node N4. The fourth transistor T4 is turned on by a low level light emission control signal EM to electrically connect the third node N3 and the fourth node N4 and transmit a driving current to the light emitting element EL.

[0047] The fifth transistor T5 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the fifth transistor T5 is connected to the second scan line, the source electrode is connected to the initialization line, and the drain electrode is connected to the fourth node N4. The fifth transistor T5 is turned on by the second scan signal Scan2 at a low level to transmit the initialization voltage Vini to the fourth node N4.

[0048] The driving transistor DT includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the first driving transistor DT is connected to the second node N2, the source electrode is connected to the high potential power supply wiring, and the drain electrode is connected to the third node N3. In one embodiment, as shown in FIG. 2, the first driving transistor DT has a dual gate structure. The driving transistor DT can control the driving current applied to the light emitting element by the gate-source voltage Vgs.

[0049] The first capacitor C1 includes a plurality of first capacitor electrodes. One of the first capacitor electrodes is connected to a first node N1, and the other first capacitor electrode is a gate electrode of the driving transistor DT and may be electrically connected to a second node N2. The first capacitor C1 is charged with a data voltage Vdata reflecting a threshold voltage of the driving transistor DT, and the voltage of the gate electrode of the driving transistor DT can be kept constant for one frame.

[0050] The second capacitor C2 includes a plurality of second capacitor electrodes, one of which is connected to the high potential power supply line and the other of which is connected to the fifth node N5. The second capacitor can reduce the voltage fluctuation of the gate electrode of the driving transistor DT when the second transistor T2 is turned on or off, and a more detailed description will be given later with reference to Figures 5 to 7b.

[0051] The light-emitting element EL includes an anode and a cathode. The anode of the light-emitting element EL is connected to the fourth node N4, and the cathode is connected to a low-potential power supply line to which a low-potential power supply voltage VSS is supplied. Therefore, the light-emitting element EL can emit light based on the driving current transmitted from the driving transistor DT to the anode.

[0052] 3, the subpixel SP may operate in the order of a first period Δt1, a second period Δt2, a third period Δt3, and a fourth period Δt4. The first period Δt1 may be an initialization period, the second period Δt2 may be a sampling period after the initialization period, the third period Δt3 may be a sustain period after the sampling period, and the fourth period Δt4 may be a light-emitting period after the sampling period.

[0053] First, during the first period Δt1 which is the initialization period, the emission control signal EM of low level is outputted from the emission control line, the first scan signal Scan1 of high level is outputted to the first scan line, and the second scan signal Scan2 of low level is outputted to the second scan line, so that the second transistor T2, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are turned on and the first transistor is turned off. The first node N1 may be initialized to the reference voltage Vref through the turned on third transistor T3, and the fourth node N4 may be initialized to the initialization voltage Vini through the turned on fifth transistor T5. The initialization voltage Vini transmitted to the fourth node N4 is transmitted to the third node N3 and the second node N2 through the turned on fourth transistor T4 and second transistor T2, so that the third node N3 and the second node N2 may also be initialized to the initialization voltage Vini. Thus, the voltages of the nodes can be initialized during the first period Δt1.

[0054] Then, during the second period Δt2, which is a sampling period, the first scan signal Scan1 of low level is output to the first scan line, the light emission control signal EM of high level is output to the light emission control line, and the second scan signal Scan2 of low level is output to the second scan line. The first transistor T1 is turned on by the first scan signal Scan1 of low level, and the data voltage Vdata may be transmitted to the first node N1. Then, the light emission control signal EM of high level is output, and the third transistor T3 and the fourth transistor T4 may be turned off. Finally, the driving transistor DT may be in a diode connection state by the turned-on second transistor T2, and the difference voltage between the high potential power supply voltage VDD and the threshold voltage may be sampled and supplied to the second node N2. Thus, during the second period Δt2, the threshold voltage of the driving transistor DT is sensed, and the fifth transistor T5 is turned on to initialize the light emitting element EL.

[0055] Next, during the third period Δt3, which is a sustain period, a first scan signal Scan1 of high level is output to the first scan line, and a second scan signal Scan2 of high level is output to the second scan line, so that the first transistor T1, the second transistor T2, and the fifth transistor T5 are turned off, a light emission control signal EN of high level is output to the light emission control line, and the third transistor T3 and the fourth transistor T4 are turned off. The data voltage Vdata input during the previous second period Δt2 may be maintained by the storage capacitor during the third period Δt3. The third period Δt3 is a period in which a time difference is provided between the second period Δt2 and the fourth period Δt4, which is a light emission period, so that the second period Δt2 and the fourth period Δt4 do not overlap.

[0056] Finally, during the fourth period Δt4, which is the light-emitting period, a low-level light-emitting control signal EM is output to the light-emitting control wiring. The reference voltage Vref is applied to the first node N1 through the turned-on third transistor T3, and the voltage of the first node N1 becomes the difference voltage between the reference voltage Vref and the data voltage Vdata. The second node N2 is connected to the first node N1 through the first capacitor C1, and such a voltage fluctuation can also be reflected in the second node N2. During the fourth period Δt4, the gate-source voltage Vgs of the driving transistor DT is set to a value (Vdata-Vref+Vth) obtained by subtracting the reference voltage Vref from the data voltage Vdata and adding the threshold voltage Vth to the data voltage Vdata, thereby controlling the driving current. Then, the driving transistor DT supplies the driving current to the light-emitting element EL through the turned-on fourth transistor T4, and the light-emitting element EL can emit light.

[0057] Meanwhile, in the display device 100 according to one embodiment of the present specification, the driving transistor DT is configured as a transistor having a dual gate structure, and a pair of gates are disposed on the active layer ACT, thereby minimizing bright spot defects due to off-current in the driving transistor DT.

[0058] FIG. 4 is a graph comparing the off-state current of a transistor with a single gate structure and a transistor with a dual gate structure.

[0059] First, a small amount of current may flow even in a transistor that is in a turned-off state. That is, when a transistor is in a turned-off state, an off-current may flow. This off-current may cause an image to be displayed at a brightness higher than the brightness intended to be displayed in the sub-pixel SP, or may cause a bright spot defect in which a sub-pixel SP that should not emit light emits light.

[0060] 4, it can be seen that when a transistor is turned off at about −2 V, a small amount of current flows even in a voltage region lower than −2 V. It can also be seen that the off current of a transistor with a dual gate structure having two gate electrodes is generally lower than that of a transistor with a single gate electrode having only one gate electrode.

[0061] In a transistor with a dual gate structure, the current is controlled by two gate electrodes, so that the current flow can be controlled more easily than in a transistor with a single gate electrode, which controls the current only by one gate electrode. In addition, in a transistor with a dual gate structure, a pair of channels is formed in the active layer, and the number of junctions, i.e., junctions that are junctions between the source region and the drain region of the active layer and the channel region, can be increased. For example, a junction between an undoped region and a doped region of the active layer is further formed between the source electrode and the drain electrode, and the number of junctions can be increased. In this case, leakage current can be generated by carriers tunneled as a depletion region generated by an electric field applied to the junctions becomes larger. Therefore, in a transistor with a dual gate structure, the number of junctions increases, and the strength of the electric field applied to each junction can be weakened, and in particular, the strength of the electric field applied to the junction of the drain region to which the drain electrode is connected can be weakened, thereby reducing the depletion region, and thus the leakage current due to the tunneling of carriers can be reduced. Therefore, compared to a transistor with a single gate structure, a transistor with a dual gate structure can have a reduced off current.

[0062] Therefore, in the display device 100 according to an embodiment of the present specification, the driving transistor DT is configured as a transistor having a dual gate structure, thereby reducing leakage current and minimizing bright spot defects.

[0063] Meanwhile, since the driving transistor DT is configured in a dual gate structure, a fifth node N5 may be formed between the source electrode and the drain electrode of the driving transistor DT. However, when the second transistor T2 is turned off, a kickback phenomenon may cause a voltage fluctuation around the second transistor T2, for example, a voltage of the fifth node N5 between the source electrode and the drain electrode of the driving transistor DT may fluctuate. For example, if the second transistor T2 is a P-type transistor, when the second transistor T2 is turned off, the voltage around the second transistor T2 may fluctuate in an upward direction. Also, the second node N2 adjacent to the fifth node N5 may fluctuate in voltage due to coupling with the fifth node N5, which may cause a problem of leakage current. Therefore, in the display device 100 according to an embodiment of the present specification, a second capacitor C2 may be added to minimize the fluctuation in the voltage of the fifth node N5 and the voltage of the second node N2.

[0064] FIG. 5 is a schematic cross-sectional view of a display device according to an embodiment of the present specification. FIG. 6 is a schematic cross-sectional view of a display device according to a comparative example. FIG. 7a is a waveform diagram showing a voltage change at the fifth node of a display device according to a comparative example and an embodiment of the present specification. FIG. 7b is a waveform diagram showing a voltage change at the second node of a display device according to a comparative example and an embodiment of the present specification. For convenience of explanation, FIGS. 5 and 6 show a schematic cross-sectional structure of a driving transistor DT.

[0065] The display device 10 according to the comparative example includes the same components as the display device 100 according to the embodiment of the present specification, except for the second capacitor C2. That is, the subpixel SP of the display device 10 according to the comparative example does not include the second capacitor C2, but includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a driving transistor DT, a first capacitor C1, and a light-emitting element EL.

[0066] First, referring to FIG. 5, a display device 100 according to an embodiment of the present disclosure includes a substrate 110, a buffer layer 111, a gate insulating layer 112, an interlayer insulating layer 113, a driving transistor DT, and a second capacitor C2.

[0067] A buffer layer 111 is disposed on the substrate 110. The buffer layer 111 can reduce the penetration of moisture or impurities through the substrate 110. The buffer layer 111 can be, for example, but is not limited to, a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx). However, the buffer layer 111 may be omitted depending on the type of substrate 110 or the type of transistor, and is not limited to this.

[0068] The drive transistor DT is disposed on the buffer layer 111. The drive transistor DT includes an active layer ACT, a pair of gate electrodes GE (eg, a plurality of gate electrodes), a source electrode SE, and a drain electrode DE.

[0069] An active layer ACT is disposed on the buffer layer 111. The active layer ACT may be made of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polysilicon. The oxide semiconductor has an excellent effect of preventing leakage current and can be a material with a relatively low manufacturing cost. The oxide semiconductor may be a metal oxide such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti), or a combination of a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti), or a metal and its oxide. Specifically, examples of oxide semiconductors include, but are not limited to, zinc oxide (ZnO), zinc oxide-tin oxide (ZTO), zinc oxide-indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium-gallium-zinc oxide (IGZO), indium-zinc-tin oxide (IZTO), indium zinc oxide (IZO), indium gallium-tin oxide (IGTO), and indium gallium oxide (IGO). The polycrystalline semiconductor material of the present invention has high mobility due to the high speed of movement of carriers such as electrons and holes, low power consumption, and excellent reliability. The amorphous semiconductor may be amorphous silicon (Si). However, the present disclosure is not limited to these.

[0070] A gate insulating layer 112 is disposed on the active layer ACT. The gate insulating layer 112 is an insulating layer for insulating the active layer ACT from the gate electrode GE, and may be composed of a single layer or multiple layers of silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiONx), but is not limited thereto. The active layer ACT connected between the source electrode SE and the drain electrode DE may correspond to a fifth node N5.

[0071] A pair of gate electrodes GE are disposed on the gate insulating layer 112. The pair of gate electrodes GE are disposed at a distance from each other as shown in FIG. 5. The pair of gate electrodes GE may be made of a conductive material such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. The pair of gate electrodes GE may correspond to a second node N2.

[0072] An interlayer insulating layer 113 is disposed on the pair of gate electrodes GE. Contact holes are formed in the interlayer insulating layer 113 for connecting the source electrode SE and the drain electrode DE to the active layer ACT, respectively. The interlayer insulating layer 113 is an insulating layer for protecting the structure below the interlayer insulating layer 113, and may be composed of a single layer or multiple layers of silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiONx), but is not limited thereto.

[0073] A source electrode SE and a drain electrode DE electrically connected to the active layer ACT are disposed on the interlayer insulating layer 113. The source electrode SE and the drain electrode DE may be made of a conductive material, for example, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. In this case, although not shown in the drawing, the source electrode SE may be electrically connected to a high-potential power supply wiring.

[0074] A second capacitor C2 is disposed on the substrate 110. The second capacitor C2 includes a 2-1 capacitor electrode C2a disposed between the substrate 110 and the buffer layer 111 and a 2-2 capacitor electrode C2b disposed on the buffer layer 111. The 2-1 capacitor electrode C2a is disposed between the substrate 110 and the buffer layer 111, and may be electrically connected to a high-potential power supply wiring. The 2-2 capacitor electrode C2b is a part of the active layer ACT between the source electrode SE and the drain electrode DE of the driving transistor DT, and may overlap the region between a pair of gate electrodes GE. That is, the 2-2 capacitor electrode C2b may be integrated with the active layer ACT. Therefore, the part of the active layer ACT constituting the 2-2 capacitor electrode C2b does not overlap the pair of gate electrodes GE. The 2-1 capacitor electrode C2a may overlap the 2-2 capacitor electrode C2b (e.g., a part of the active layer ACT) with the buffer layer 111 interposed therebetween to form the second capacitor C2.

[0075] 6, the display device 10 according to the comparative example is substantially the same as the display device 100 according to the embodiment of the present specification in other respects, except that the display device 10 does not include a second capacitor C2. The display device 10 according to the comparative example includes a substrate 110, a buffer layer 111, a gate insulating layer 112, an interlayer insulating layer 113, and a driving transistor DT, and does not include a separate capacitor electrode disposed between the substrate 110 and the buffer layer 111.

[0076] Meanwhile, when a switching transistor such as the second transistor T2 is turned off, the voltage of the surrounding node is distorted, and a kickback phenomenon may occur, which makes it impossible to output the target brightness. For example, during the third period Δt3 when the second transistor T2 is turned off from the turned on state, a problem occurs in which the voltage of the gate electrode GE of the driving transistor DT fluctuates due to the kickback phenomenon. Specifically, at the moment when the second transistor T2 is turned off, the voltage of the fifth node N5 between the source electrode SE and drain electrode DE of the driving transistor DT may instantaneously rise to a voltage higher than the high potential power supply voltage VDD.

[0077] In this case, the voltage of the fifth node N5 becomes higher than the high potential power supply voltage VDD, and a leakage current flows from the fifth node N5 toward the high potential power supply wiring side, and the voltage of the fifth node N5 may fluctuate in a decreasing direction. Such a leakage current increases the voltage on the source electrode side, and the gate-source voltage Vgs of the driving transistor DT increases, which may ultimately cause a bright spot defect.

[0078] In addition, the fifth node N5, i.e., the region between the source electrode SE and drain electrode DE of the driving transistor DT, is adjacent to the gate electrode GE of the driving transistor DT, and therefore the voltage of the gate electrode GE and the second node N2 may vary together. The fifth node N5 and the second node N2 are disposed adjacent to each other to form a kind of capacitor, and the fifth node N5 and the second node N2 are coupled to each other so that the voltage of the second node N2 may vary according to the voltage variation of the fifth node N5.

[0079] The third period Δt3 during which the voltage fluctuation of the fifth node N5 occurs is a period during which the data voltage Vdata applied during the previous second period Δt2 should be maintained. However, the voltage fluctuation of the fifth node N5 and the voltage fluctuation of the second node N2 coupled to the fifth node N5 may cause the brightness of the light emitted from the sub-pixel SP to be higher than designed, or may cause a bright spot defect in which the sub-pixel SP that should not emit light emits light.

[0080] 7a, in the display device 10 according to the comparative example, at the moment when the third period Δt3 in which the second transistor T2 is turned off starts, the voltage of the fifth node N5 may rise due to the kickback phenomenon. Then, a leakage current may flow from the fifth node N5, which momentarily has a voltage higher than the high potential power supply voltage VDD, to the high potential power supply line, and the voltage of the fifth node N5 may gradually decrease. Therefore, due to the kickback phenomenon, the voltage of the fifth node N5 may rise momentarily and then gradually decrease, and finally the voltage of the fifth node N5 may decrease.

[0081] 7b, the second node N2 adjacent to the fifth node N5 is coupled to the fifth node N5, so that the voltage of the second node N2 also rises and then decreases instantaneously when the third period Δt3 begins. Therefore, when the second transistor T2 is turned off, the voltage of the fifth node N5 fluctuates due to the kickback phenomenon, and the voltage of the second node N2 also fluctuates due to coupling with the fifth node N5, so that the driving current that finally flows in the fourth period Δt4 also changes.

[0082] As a result, the voltage of the fifth node N5 and the voltage of the second node N2 coupled to the fifth node N5 may decrease, and the gate-source voltage Vgs of the driving transistor DT may increase, and the driving current supplied to the light-emitting element EL during the fourth period Δt4 may increase from the driving current previously designed, causing the brightness of the light emitted from the light-emitting element EL to increase more than that actually intended to be displayed, or it may become difficult to express low gray levels in the sub-pixel SP that displays low gray levels, degrading the overall display quality.

[0083] In contrast, in the display device 100 according to an embodiment of the present specification, the second capacitor C2 is connected to the fifth node N5, and the voltage of the fifth node N5 can be prevented from fluctuating due to the kickback phenomenon. The second capacitor C2 connects the fifth node N5 to a high-potential power supply line, which is a stable DC power supply, and can buffer the voltage of the fifth node N5 from fluctuating due to the kickback phenomenon. That is, the second capacitor C2 connected to the fifth node N5 can function to maintain the voltage of the fifth node N5. Therefore, the second capacitor C2 can maintain the gate-source voltage Vgs of the driving transistor DT constant during the third period Δt3 without increasing due to the kickback phenomenon.

[0084] In comparison with the display device 10 according to the comparative example, in the display device 100 according to the embodiment of the present specification, it can be seen that the voltage fluctuation width of the fifth node N5 is reduced at the moment when the third period Δt3 in which the second transistor T2 is turned off starts. And, the voltage fluctuation width of the fifth node N5 is reduced, and the voltage fluctuation width of the second node N2 may also be reduced. Therefore, in the display device 100 according to the embodiment of the present specification, the fluctuation of the gate-source voltage Vgs of the driving transistor DT is reduced, and the driving current that was previously intended to be supplied to the light emitting element EL can be supplied as it is. Therefore, the display device 100 according to the embodiment of the present specification includes the second capacitor C2 configured to reduce the voltage fluctuation of the fifth node N5, and can minimize the rise of the gate-source voltage Vgs of the driving transistor DT due to the kickback phenomenon and the resulting bright spot defect.

[0085] A display device according to an embodiment of the present specification can be described as follows.

[0086] A display device according to one embodiment of the present specification includes a substrate on which a plurality of subpixels are defined, a light-emitting element arranged in each of the plurality of subpixels, and a pixel circuit arranged in each of the plurality of subpixels for driving the light-emitting element, the pixel circuit including a driving transistor having a dual-gate structure connected between a high-potential power supply wiring and the light-emitting element, and a second capacitor connected between a fifth node between a source electrode and a drain electrode of the driving transistor and the high-potential power supply wiring.

[0087] According to another feature of the present specification, the pixel circuit may further include a first transistor connected between the data line and the first node, a first capacitor connected between the first node and a second node connected to a gate electrode of the driving transistor, a second transistor connected between the second node and a third node connected to a drain electrode of the driving transistor, a third transistor connected between the first node and a reference line, a fourth transistor connected between a fourth node connected to an anode of the light-emitting element and the third node, and a fifth transistor connected between the fourth node and an initialization line.

[0088] According to still another feature herein, the second transistor and the drive transistor may be P-type transistors.

[0089] According to still another feature of the present disclosure, the second node and the fifth node may be coupled and configured such that a voltage fluctuation at the fifth node causes a voltage fluctuation at the second node.

[0090] According to still another feature of the present specification, the pixel circuit is configured to be driven in an initialization period, a sampling period, a holding period, and a light emission period in that order, and the second transistor may be turned on in the sampling period and turned off in the holding period.

[0091] According to still another feature of the present disclosure, the second capacitor may be configured to reduce a voltage fluctuation of the fifth node due to a kick-back when the second transistor is turned off during the hold period.

[0092] According to still other features herein, the second capacitor can be configured to reduce voltage fluctuations at the second node during the hold period.

[0093] According to still another feature of the present disclosure, the second capacitor can be configured to maintain the gate-source voltage Vgs of the drive transistor constant during the hold period.

[0094] According to still another feature of the present specification, the second capacitor includes a 2-1 capacitor electrode and a 2-2 capacitor electrode overlapping each other, the driving transistor includes an active layer, a pair of gate electrodes arranged on the active layer, and source and drain electrodes arranged on the pair of gate electrodes and electrically connected to the active layer, the 2-1 capacitor electrode being electrically connected to a high potential power supply wiring, and the 2-2 capacitor electrode being electrically connected to the active layer.

[0095] According to still another feature of the present specification, the semiconductor device may further include a buffer layer disposed between the 2-1 capacitor electrode and an active layer of the driving transistor, and a gate insulating layer disposed between the active layer of the driving transistor and a pair of gate electrodes of the driving transistor, the 2-2 capacitor electrode being a part of the active layer overlapping a region between the gate electrodes of the driving transistor, and the 2-2 capacitor electrode overlaps with the 2-1 capacitor electrode across the buffer layer to form a second capacitor.

[0096] According to still other features herein, the pair of gate electrodes may correspond to a second node, and the active layer may correspond to a fifth node.

[0097] Although the embodiments of the present specification have been described in more detail with reference to the accompanying drawings, the present specification is not necessarily limited to such embodiments, and various modifications can be made within the scope of the technical idea of ​​the present specification. Therefore, the embodiments disclosed in the present specification are for illustration purposes, not for limiting the technical idea of ​​the present specification, and the scope of the technical idea of ​​the present specification is not limited by such embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. [Explanation of symbols]

[0098] 100 display device 110 Substrate C1 First capacitor C2 Second capacitor

Claims

1. A substrate; A plurality of sub-pixels on the substrate; a light-emitting element on one of the plurality of sub-pixels; a pixel circuit provided on the sub-pixel and configured to drive the light-emitting element; The pixel circuit includes: a driving transistor including an active layer, a pair of gate electrodes on the active layer, and source and drain electrodes provided on the pair of gate electrodes and electrically connected to the active layer, the driving transistor being connected between a high-potential power supply wiring and the light-emitting element; a capacitor connected between the high-potential power supply wiring and a node between the source electrode and the drain electrode of the driving transistor.

2. The pixel circuit includes: a first transistor connected between the data wiring line and a first node; another capacitor connected between the first node and a second node, the gate electrode of the driving transistor being connected to the second node; a second transistor connected between the second node and a third node, the drain electrode of the driving transistor being connected to the third node; a third transistor connected between the first node and a reference line; a fourth transistor connected between the third node and a fourth node, the fourth transistor having an anode of the light emitting element connected to the fourth node; 2. The display device according to claim 1, further comprising: a fifth transistor connected between the fourth node and the initialization wiring.

3. The pixel circuit includes:

3. The display device according to claim 2, wherein the first transistor has a gate electrode connected to a first scan line, the second transistor has a gate electrode connected to a second scan line, the third transistor has a gate electrode connected to a light emission control line, the fourth transistor has a gate electrode connected to the light emission control line, and the fifth transistor has a gate electrode connected to the second scan line.

4. The display device according to claim 2 , wherein each of the second transistor and the driving transistor is a P-type transistor.

5. The display device according to claim 3 , wherein the second node and the node are capacitively coupled, and a voltage fluctuation at the node causes a voltage fluctuation at the second node.

6. the pixel circuit is configured to be driven in the order of an initialization period, a sampling period after the initialization period, a retention period after the sampling period, and a light emission period after the sampling period; 5. The display device according to claim 4, wherein the second transistor is turned on in the sampling period and turned off in the holding period.

7. during the initialization period, a voltage of the first node is initialized as a voltage supplied via the reference wiring, and voltages of the second node, the third node, and the fourth node are initialized as voltages supplied via initialization wirings; In the sampling period, a threshold voltage of the driving transistor is sampled to initialize the light emitting element; In a retention period, the other capacitor retains a data voltage supplied via a data line; 7. The display device according to claim 6, wherein during a light emission period, a driving current is passed to the light emitting element via the fourth transistor that is turned on.

8. 7. The display device of claim 6, wherein the capacitor reduces a voltage fluctuation of the node caused by a kick-back when the second transistor is turned off during the hold period.

9. The display device according to claim 8 , wherein the capacitor reduces a voltage fluctuation of the second node during the holding period.

10. The display device according to claim 8 , wherein the capacitor maintains a gate-source voltage of the drive transistor constant during the hold period.

11. The capacitor includes a first capacitor electrode and a second capacitor electrode that overlap each other, The display device according to claim 2 , wherein the first capacitor electrode is electrically connected to the high potential power supply wiring, and the second capacitor electrode is electrically connected to the active layer.

12. a buffer layer between the first capacitor electrode and the active layer of the driving transistor; a gate insulating layer between the active layer of the driving transistor and the pair of gate electrodes of the driving transistor; the second capacitor electrode is a portion of the active layer that does not overlap the gate electrodes of the pair of driving transistors; The display device of claim 11 , wherein the capacitor includes the second capacitor electrode and the first capacitor electrode overlapping the first capacitor electrode with the buffer layer interposed therebetween.

13. the pair of gate electrodes corresponds to the second node; The display device of claim 12 , wherein the active layer corresponds to the node.

14. A substrate; A plurality of sub-pixels on the substrate; a light-emitting element provided in one of the plurality of sub-pixels; a pixel circuit provided on the sub-pixel and configured to drive the light-emitting element; The pixel circuit includes: a driving transistor having an active layer, a pair of gate electrodes on the active layer, and a source electrode and a drain electrode provided on the pair of gate electrodes and electrically connected to the active layer, the driving transistor being connected between a high-potential power supply wiring and the light-emitting element; A display device having a first capacitor electrode connected to the high potential power supply wiring and a second capacitor electrode connected to a node between a source electrode and a drain electrode of the driving transistor, the first capacitor electrode including a capacitor overlapping a portion of the active layer.

15. The display device according to claim 14 , wherein the gate electrodes of the pair of gate electrodes are spaced apart from each other, and the second capacitor electrode is a portion of the active layer that overlaps the first capacitor electrode.

16. 16. The display of claim 15, wherein the portion of the active layer that overlaps the first capacitor electrode does not overlap the pair of gate electrodes.

17. 17. The display of claim 16, wherein a portion of the active layer is a node between the source electrode and the drain electrode of the drive transistor.

18. a buffer layer between the first capacitor electrode of the capacitor and the active layer of the driving transistor; The display device according to claim 16, further comprising a gate insulating layer between the active layer and the pair of gate electrodes of the driving transistor.

19. The pixel circuit further comprises: a first transistor having a source electrode connected to a data line, a drain electrode connected to a first node, and a gate electrode connected to a first scan line for supplying a first scan signal; another capacitor including a first capacitor electrode connected to the first node and a second capacitor electrode connected to a second node, the gate electrode of the driving transistor being connected to the second capacitor electrode at the second node; a second transistor having a source electrode connected to the second capacitor electrode of the other capacitor and to the gate electrode of the driving transistor at the second node, a drain electrode connected to the drain electrode of the driving transistor at a third node, and a gate electrode connected to a second scan line that supplies a second scan signal; a third transistor including a source electrode connected to the drain electrode of the first transistor and the first capacitor electrode of the other capacitor at the first node, a drain electrode connected to a reference wiring that supplies a reference voltage, and a gate electrode connected to a light emission wiring that supplies a light emission signal; a fourth transistor having a source electrode connected to the drain electrode of the second transistor and the drain electrode of the driving transistor at the third node, a drain electrode connected to an anode electrode of the light emitting element at a fourth node, and a gate electrode connected to the gate electrode of the third transistor and the light emitting wiring; 15. The display device of claim 14, further comprising: a fifth transistor having a source electrode connected to the drain electrode of the fourth transistor and the anode electrode of the light-emitting element of the fourth node, a drain electrode connected to an initialization wiring that supplies an initialization voltage, and a gate electrode connected to the gate electrode of the second transistor and the second scan wiring.

20. The display device according to claim 19 , wherein the second transistor and the driving transistor are P-type transistors.

21. the pixel circuit is configured to operate in the order of an initialization period, a sampling period after the initialization period, a retention period after the sampling period, and a light emission period after the sampling period; 20. The display device according to claim 19, wherein the second transistor is turned on during the sampling period and the second transistor is turned off during the holding period.

22. 22. The display device according to claim 21, wherein the capacitor reduces a fluctuation in voltage of the node between the source electrode and the drain electrode of the drive transistor in response to the second transistor being turned off during the hold period.

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