Image forming device

Abstract

To reduce switching noise caused by multiple exposure.SOLUTION: An image forming device comprises: an exposure device that has a chip in which a first light-emitting element row and a second light-emitting element row which are formed of a plurality of light-emitting elements are arranged in sequence, and performs, by the second light-emitting element row, multiple exposure at a portion exposed by the first light-emitting element row; and a controller that transmits a signal for controlling the exposure device. The exposure device sets a first pulse signal for making the first light-emitting element row emit light on the basis of a first delay time from an input timing of a line synchronization signal to a first start timing of starting a light emission and a first pulse width from the first start timing to a first finish timing of finishing the light emission; and sets a second pulse signal for making the second light-emitting element row emit light on the basis of a second delay time which is different from the first delay time from the input timing of the line synchronization signal to a second start timing of starting a light emission and a second pulse width that is same as the first pulse width from the second start timing to a second finish timing of finishing the light emission.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] The present invention relates to an image forming apparatus equipped with an exposure device that exposes a photoconductor. [Background technology]

[0002] In electrophotographic image forming devices such as printers, a method is generally known in which a photosensitive drum is exposed to light using an exposure device using LEDs or organic electroluminescence (EL) to form a latent image. The exposure device is composed of a row of light emitting elements arranged in the direction of the rotation axis (longitudinal direction) of the photosensitive drum, and a rod lens array that forms an image of the light from the row of light emitting elements on the photosensitive drum. The LEDs and organic electroluminescence are known to have a surface-emitting shape in which the direction of irradiation of light from the light emitting surface is the same as the rod lens array.

[0003] Here, the longitudinal length of the light-emitting element row is determined according to the image area width on the photosensitive drum, and the spacing between the light-emitting elements is determined according to the printer's resolution. For example, in the case of a 1200 dpi printer, the pixel spacing is 21.16 μm (omitted after the third decimal point), so the spacing between the light-emitting elements is also 21.16 μm. Printers using such an exposure device use fewer parts than laser scanning printers that deflect and scan a laser beam with a polygon motor, making it easier to make the device smaller and less expensive.

[0004] Organic EL has a lower light emission intensity than lasers and LEDs. Therefore, some light emitting devices secure the required light intensity by arranging multiple light emitting elements in a row of light emitting elements arranged in the longitudinal direction of the photosensitive drum, and also arranging multiple light emitting element rows in the rotation direction perpendicular to the longitudinal direction of the photosensitive drum, and exposing the same location on the photosensitive drum multiple times using the multiple light emitting element rows. For example, Patent Document 1 has a feature in that light emitting points are arranged two-dimensionally and arranged in a way that allows multiple exposure. This type of configuration makes it possible to form a latent image on the photosensitive drum even with a low-light-intensity organic EL. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2016-124264 A Summary of the Invention [Problem to be solved by the invention]

[0006] However, in a printer that performs multiple exposure, multiple light-emitting elements arranged in the longitudinal direction of the photosensitive drum and in a direction perpendicular to the longitudinal direction are simultaneously turned on in accordance with a line synchronization signal. This causes a problem in that the number of signals that change simultaneously is large, resulting in large switching noise.

[0007] SUMMARY OF THE PRESENT EMBODIMENT An object of the present invention is to reduce switching noise that accompanies multiple exposure. [Means for solving the problem]

[0008] A representative configuration of the present invention for achieving the above object includes a photoconductor, a chip in which a first light-emitting element row formed of a plurality of light-emitting elements arranged along a first direction which is a rotation axis direction of the photoconductor, and a second light-emitting element row formed of the plurality of light-emitting elements arranged along the first direction are sequentially arranged in a second direction perpendicular to the first direction, an exposure device that performs multiple exposure with the second light-emitting element row at an exposure position exposed by the first light-emitting element row on the photoconductor, and a controller that transmits a signal to the exposure device for controlling the exposure device, the exposure device having a first delay time from an input timing of a line synchronization signal to a first start timing at which light emission starts, and a first delay time for the first start timing. a first pulse signal for causing the first light-emitting element row to emit light based on a first pulse width from the input timing of the line synchronization signal to a first end timing at which the light emission ends by the input timing of the next line synchronization signal of the line synchronization signal, and a second pulse signal for causing the second light-emitting element row to emit light based on a second delay time different from the first delay time from the input timing of the line synchronization signal to a second start timing at which the light emission starts and a second pulse width the same as the first pulse width from the second start timing to a second end timing at which the light emission ends by the input timing of the next line synchronization signal of the line synchronization signal, and the light emission of each light-emitting element row is started and ended according to the settings. Effect of the Invention

[0009] According to the present invention, it is possible to reduce switching noise that accompanies multiple exposure. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a schematic cross-sectional view showing an overall configuration of an image forming apparatus. [Diagram 2] (a) and (b) are diagrams showing the positional relationship between the exposure head and the photosensitive drum. [Diagram 3] (a)(b)(c) Illustrative diagram of printed circuit board [Figure 4] An explanatory diagram of the configuration of a light-emitting element array chip. [Diagram 5] An explanatory diagram of the configuration of the light-emitting unit [Figure 6] (a) and (b) are diagrams for explaining the arrangement of light-emitting elements, and (c) and (d) are diagrams showing the appearance of light-emitting element spots. [Figure 7] Image controller and printed circuit board block diagram [Figure 8] Circuit block diagram in the light-emitting element array chip of the first embodiment [Figure 9] Block diagram of image data storage unit [Figure 10] 1 is a timing chart showing the operation of an image data storage unit; [Figure 11] 1 is a timing chart showing the operation of an image data storage unit; [Figure 12] 1A is a block diagram of a pulse signal generating unit according to a first embodiment of the present invention; FIG. 1B is a timing chart of the pulse signal generating unit; [Figure 13] (a) Block diagram of the analog section, (b) Explanation of the driver circuit [Figure 14] Block diagram of the lighting control unit of the first embodiment [Figure 15] FIG. 1 is a table showing the setting values ​​set in the pulse signal generating unit of the first embodiment. [Figure 16] Circuit block diagram in the light-emitting element array chip of the second embodiment [Figure 17] (a) is a block diagram of a pulse signal generating unit according to a second embodiment; (b) is a table showing setting values ​​set in the pulse signal generating unit according to the second embodiment. [Figure 18] (a) and (b) Illustrative diagram of pixels created by multiple exposures [Figure 19] 1A and 1B are timing charts of a pulse signal generating unit according to a second embodiment of the present invention. [Figure 20] 1A, 1B, and 1C are explanatory diagrams of light-emitting sections of a light-emitting element row in a chip according to Example 2. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. However, the dimensions, materials, shapes, and relative positions of the components described in the following embodiments may be changed as appropriate depending on the configuration of the device to which the present invention is applied and various conditions, and are not intended to limit the scope of the present invention to these alone.

[0012] Example 1 (Overall configuration of image forming apparatus) The electrophotographic image forming apparatus in this embodiment will be briefly described. The overall configuration of the image forming apparatus is shown in Fig. 1. This image forming apparatus is composed of a scanner unit 100, an image creating unit 103, a fixing unit 104, a paper feed / transport unit 105, and a printer control unit (not shown) that controls these units.

[0013] The scanner unit 100 illuminates a document placed on a document table, optically reads the document image, and converts the image into an electrical signal to create image data. The image creating unit 103 rotates a photosensitive drum 102 as an image carrier (photosensitive body), and charges the photosensitive drum 102 with a charger 107. An exposure head 106 as an exposure device emits light according to the image data, and focuses the light emitted from the chip surfaces of the arrayed light-emitting element groups on the photosensitive drum 102 to form an electrostatic latent image. A developer 108 develops toner for the electrostatic latent image formed on the photosensitive drum 102. The developed toner image is transferred onto paper conveyed on a transfer belt 111. The image creating unit has four image creating units that perform the series of electrophotographic processes (charging, exposure, development, transfer), and forms a full-color image by arranging them in the order of cyan (C), magenta (M), yellow (Y), and black (K). The four imaging units sequentially perform image formation operations for magenta, yellow, and black after a predetermined time has elapsed since the start of image formation by the cyan imaging unit.

[0014] In the paper feed / transport section 105, paper is fed as a recording medium from a paper feed unit designated in advance among the internal paper feed units 109a and 109b, the external paper feed unit 109c, and the manual paper feed unit 109d, and the fed paper is transported to the registration rollers 110. The registration rollers 110 transport the paper onto the transfer belt 111 at the timing when the toner image formed in the image forming section 103 is transferred onto the paper. An optical sensor 113 is disposed at a position facing the transfer belt 111, and detects the position of a test chart printed on the transfer belt 111 in order to derive the amount of color misregistration between the image forming units. The amount of color misregistration derived here is notified to the image controller section 700 (see FIG. 7), and the image position of each color is corrected. This control allows a full-color toner image without color misregistration to be transferred onto the paper. The fixing unit 104 is made up of a combination of rollers, has a built-in heat source such as a halogen heater, and uses heat and pressure to melt and fix the toner on the paper onto which the toner image has been transferred from the transfer belt 111. The paper with the fixed image is discharged by paper discharge rollers 112 to the outside of the image forming apparatus.

[0015] The printer control unit (not shown) communicates with the MFP control unit that controls the entire MFP, and executes control according to the instructions, while managing the status of the above-mentioned scanner, image creation, fixing, and paper feed / transport units, and issues instructions so that the entire unit operates smoothly and in harmony. Note that MFP is an abbreviation for multi-function printer, and the entire MFP refers to the entire image forming device. Here, a multi-function multifunction machine (multifunction printer) that combines the functions of printer, copy, image reading, and fax in one unit is shown as an example of the image forming device, but it is not limited to this.

[0016] (Exposure head configuration) The exposure head 106 serving as an exposure device for exposing the photosensitive drum 102 will be described with reference to Fig. 2. Fig. 2(a) and Fig. 2(b) show the arrangement of the exposure head 106 with respect to the photosensitive drum 102, and the manner in which light emitted from a light-emitting element group 201 is collected on the photosensitive drum 102 by a rod lens array 203.

[0017] The exposure head 106 and the photosensitive drum 102 are attached to the image forming apparatus by means of attachment members (not shown). The exposure head 106 is composed of a light emitting element group 201, a printed circuit board 202 on which the light emitting element group 201 is mounted, a rod lens array 203, and a housing 204 to which the rod lens array 203 and the printed circuit board 202 are attached. The exposure head 106 is assembled and adjusted individually in the factory, and focus adjustment is performed to adjust the spot at the light condensing position to a predetermined size, and light amount adjustment is performed. Here, the distance between the photosensitive drum 102 and the rod lens array 203 and the distance between the rod lens array 203 and the light emitting element group 201 are arranged to be a predetermined interval, so that the light emitted from the light emitting element group 201 is imaged on the photosensitive drum 102. For this reason, during focus adjustment, the attachment position of the rod lens array 203 is adjusted so that the distance between the rod lens array 203 and the light emitting element group 201 is a desired value. When adjusting the light amount, each light emitting element is caused to emit light individually and in sequence, and the drive current of each light emitting element is adjusted so that the light condensed via the rod lens array 203 has a predetermined light amount.

[0018] (Board configuration) Fig. 3 shows a printed circuit board 202 on which light-emitting element groups 201 are arranged. Fig. 3(a) shows the surface opposite to the surface on which light-emitting element groups 201 are mounted (hereinafter referred to as the light-emitting element non-mounting surface), and Fig. 3(b) shows the surface on which light-emitting element groups 201 are mounted (hereinafter referred to as the light-emitting element mounting surface). The printed circuit board 202 is a board on which components can be mounted on both the non-mounting surface shown in Fig. 3(a) and the mounting surface shown in Fig. 3(b).

[0019] As shown in FIG. 3B, a light emitting element group 201 consisting of a plurality of light emitting elements is mounted on the light emitting element mounting surface of the printed circuit board 202. The light emitting element group 201 is configured by arranging 20 light emitting element array chips 400-1 to 400-20 in a staggered pattern. In each light emitting element array chip, 748 light emitting elements are arranged in the longitudinal direction, which is the first direction of the chip, and six rows in the lateral direction, which is the second direction perpendicular to the first direction, at a predetermined resolution pitch. In this embodiment, the pitch of adjacent light emitting elements in both the longitudinal and lateral directions of the chip is a pitch of 1200 dpi resolution (approximately 21.16 μm), and the distance from end to end of the 748 light emitting points in the longitudinal direction in the chip is approximately 15.8 mm. By arranging 20 chips in the light emitting element group 201, the number of light emitting elements that can be exposed in the longitudinal direction of the photosensitive drum 102 is 14960 elements, and an image corresponding to an image width of approximately 316 mm can be formed. The light-emitting element array chips 400-1 to 400-20 are arranged in two rows in a staggered pattern, with each row aligned along the longitudinal direction of the printed circuit board 202. FIG. 3(c) shows the boundary between the chips of the light-emitting element array chip 400. Even at the boundary between the chips, the longitudinal pitch of the light-emitting elements is the pitch of a resolution of 1200 dpi (approximately 21.16 μm). The chips are arranged so that the distance (S in the figure) between the light-emitting points of the two rows is approximately 105 μm (equivalent to 5 pixels at 1200 dpi).

[0020] The distance between the light emitting points in the longitudinal direction of the exposure head 106 (L in the figure) is about 21.16 μm (one pixel at 1200 dpi). Note that in the present invention, the distances S and L between the light emitting element array chips do not have to be limited to the above-mentioned values.

[0021] 3(a), a connector 305 for connecting a control signal for controlling the light-emitting element array chip from the image controller unit 700 (see FIG. 7) and a power supply line is disposed on the non-light-emitting element mounting surface of the printed circuit board 202. Each light-emitting element array chip 400 is driven via the connector 305.

[0022] (Configuration of light-emitting element array chip) FIG. 4 shows an outline of the planar configuration of the light-emitting element array chip 400. The direction of the arrow X in the figure is the direction of the rotation axis (longitudinal direction) of the photosensitive drum 102, which is the first direction of the chip. The direction of the arrow Y is the rotation direction of the photosensitive drum 102, which is the second direction perpendicular to the first direction of the chip. The light-emitting element array chip 400 has a light-emitting section 404 including a plurality of light-emitting elements and wire bonding pads (WB pads) 408 formed on a light-emitting substrate 402. The light-emitting substrate 402 has a built-in circuit section 406 for controlling the light-emitting section 404. The circuit section 406 is configured to include both an analog driving circuit and a digital control circuit. Power supply to the circuit section 406 and input and output of signals from outside the light-emitting element array chip 400 are performed through the wire bonding pads 408.

[0023] (Configuration of the light-emitting part) The light emitting section 404 will be described with reference to FIG. 5. The arrow Z direction in the figure is perpendicular to the arrow X direction and the arrow Y direction, and is the direction in which light is emitted from the light emitting section 404. FIG. 5 is a schematic diagram of a part of the cross section of the AA section in FIG. 4, one light emitting element, and its surroundings. A plurality of lower electrodes 504, a light emitting layer 506, and an upper electrode 508 are formed on the light emitting substrate 402. The lower electrode 504 is an independent electrode, and the upper electrode 508 is a common electrode. As shown in FIG. 5, the lower electrodes 504 are formed with a width W in the arrow X direction in the figure, and with a predetermined interval d between the lower electrodes 504 adjacent in the arrow X direction. The light emitting layer 506 is formed between the lower electrode 504 and the upper electrode 508. The light emitting layer 506 may be formed continuously or may be divided into portions of approximately the same size as the lower electrode 504. The light emitting element 602 is formed by one independent lower electrode 504, the portion surrounded by the light emitting layer 506, and the upper electrode 508. A desired electrode is selected from the plurality of lower electrodes 504, and a current is applied to the light-emitting layer 506 through the selected lower electrode 504 and upper electrode 508, causing the light-emitting layer 506 at a location corresponding to the selected lower electrode 504 to emit light as emitted light 510 through the upper electrode 508. The lower electrode 504 is preferably made of a metal having a high reflectance to the emission wavelength of the light-emitting layer 506, and Ag is used in this embodiment. Alternatively, Al or its alloy may be used. The upper electrode 508 is preferably transparent to the emission wavelength of the light-emitting layer 506, and indium tin oxide (ITO) is used in this embodiment. In this embodiment, an organic EL film is used as the light-emitting layer 506, but it may be an inorganic EL layer or the like other than an organic EL layer.

[0024] (Arrangement of light-emitting parts) The arrangement of the light-emitting section 404 will be described with reference to Fig. 6(a) and Fig. 6(b). Fig. 6(a) is a diagram showing the arrangement of light-emitting elements in the light-emitting section 404. As shown in Fig. 6(a), the light-emitting section 404 is configured by arranging a plurality of light-emitting elements 602 in a row. The plurality of light-emitting elements 602 are arranged in a row in the direction of the arrow X in the figure at a predetermined interval (for example, a pitch of 21.16 µm at 1200 dpi), and are also arranged in a plurality in the direction of the arrow Y, forming a plurality of light-emitting element rows (604-1 to 604-m in Fig. 6(a)).

[0025] In other words, the light emitting section 404 is configured by sequentially arranging light emitting element rows 604, each of which is formed of a plurality of light emitting elements 602 arranged along the direction of the arrow X, which is a first direction, in the direction of the arrow Y, which is a second direction perpendicular to the first direction. Specifically, the light emitting section 404 has n light emitting elements 602 arranged in a row in the direction of the arrow X at predetermined intervals to form the light emitting element row 604. The light emitting section 404 is configured by sequentially arranging m light emitting element rows 604 thus formed (first light emitting element row 604-1, second light emitting element row 604-2, ... mth light emitting element row 604-m) in the direction of the arrow Y.

[0026] In the figure, W1 is the width of the light emitting element 602 in the direction of the arrow X, and d1 is the distance between adjacent light emitting elements 602 in the direction of the arrow X. When the light emitting layer 506 is sufficiently thin, the size of the light emitting element 602 is substantially the same as the lower electrode 504, and W1 may be regarded as W in FIG. 5, and d1 as d in FIG. 5. The width W2 of the light emitting element 602 in the direction of the arrow Y, the distance d2, and the number of rows m of the light emitting element rows 604 may be determined in consideration of the scanning speed in the direction of the arrow Y, the required amount of light, and the resolution. In this embodiment, the width W1 is 20.9 μm, the distance d1 is 0.26 μm, and the light emitting elements are arranged at a pitch of 21.16 μm. The width W2 is 20.9 μm, the same as the width W1, and the width d2 is 0.26 μm, the same as the width d1, and the light emitting elements are arranged at a pitch of 21.16 μm. The number of rows m is 6.

[0027] Fig. 6(b) is a schematic cross-sectional view of a light-emitting element row 604-1. As shown in Fig. 6(b), the lower electrodes 504 are arranged in the direction of the arrow X in the figure with a width W1 and an interval d1. Each light-emitting element 602 is composed of a portion where each lower electrode 504 faces an upper electrode 508, and a light-emitting layer 506 therebetween. As an example of the configuration of an individual light-emitting element, a light-emitting element 602-13 is shown in the portion surrounded by a dotted line in Fig. 6(b).

[0028] When the light-emitting elements arranged in the direction of the arrow Y in FIG. 6(a) are turned on simultaneously, they are exposed at different positions on the photosensitive drum 102 in the rotation direction of the photosensitive drum 102 at intervals of W2+d2. By shifting the timing of turning on each light-emitting element in time according to the rotation speed of the photosensitive drum 102, it becomes possible to expose at approximately the same position on the photosensitive drum 102. The state in which the light-emitting elements arranged in the direction of the arrow Y are exposed at approximately the same position is called multiple exposure. For example, the exposure position (approximately the same position) exposed by the first light-emitting element row 604-1 shown in FIG. 6(a) is multiple-exposed by the second light-emitting element row 604-2.

[0029] 6(c) and 6(d) show the state of spots of the light-emitting elements. Here, the case where two light-emitting elements arranged in the direction of the arrow Y are exposed on the photosensitive drum will be described as an example. FIG. 6(c) is a diagram showing the state of spots when two light-emitting elements arranged in the direction of the arrow Y are simultaneously turned on. Since the two light-emitting elements 602-m1 and 602-m2 are arranged in the direction of the arrow Y, when they emit light simultaneously, the spots on the photosensitive drum 102 are also formed side by side in the direction of the arrow Y. FIG. 6(d) is a diagram showing the state of spots when the lighting timing of the light-emitting element 602 downstream in the rotation direction is delayed according to the formula (1) according to the rotation direction and rotation speed Vdr (mm / s) of the photosensitive drum 102. Note that FIG. 6(d) shows the case where the light-emitting element 602-m2 is multiple-exposed to the exposure position exposed by the light-emitting element 602-m1 on the photosensitive drum. Here, assuming that the width of the light emitting element 602 is W2 (μm) and the interval between the light emitting elements 602 is d2 (μm), the timing Tdelay(s) at which the spot positions (exposure positions) on the photosensitive drum coincide is expressed by equation (1).

[0030] Tdelay = ((W2 + d2) ÷ 1000) ÷ Vdr Equation (1)

[0031] In this embodiment, an emission signal is generated so that the maximum emission time Tw(s) of each pixel is equal to one line time in the direction of the arrow Y, and is expressed by equation (2) using the resolution (e.g., 1200 dpi) and the rotation speed Vdr.

[0032] Tw=(25.4÷1200)÷Vdr Formula (2)

[0033] Multiple exposure enables exposure at the same position on the photosensitive drum using multiple light-emitting elements, and the amount of light received by the photosensitive drum 102 can be increased in proportion to the number of light-emitting elements arranged in the direction of the arrow Y. In this embodiment, one light-emitting element array chip has six light-emitting elements (light-emitting element row) arranged in the direction of the arrow Y, and a pixel is formed by exposing the same position on the photosensitive drum six times.

[0034] (Control Block) 7 shows a block diagram of the image controller unit 700 and the printed circuit board 202. In this embodiment, for the sake of simplicity, processing of a single color will be described, but similar processing is also performed simultaneously in parallel for four colors.

[0035] (Image controller) The image controller unit 700 is provided on the side of a device (here, an image forming device) different from the printed circuit board 202. The image controller unit 700 transmits signals for controlling the printed circuit board 202 to the printed circuit board 202. The signals are a chip select signal indicating the effective range of image data, a clock signal, image data, a signal indicating the division of each line of image data (hereinafter referred to as a line synchronization signal), and a communication signal with the CPU 703. Each of the signals is transmitted to the light emitting element array chip 400 in the printed circuit board 202 via a chip select signal line cs_x705, a clock signal line clk706, an image data signal line data707, a line synchronization signal line lsync_x708, and a communication signal line 709. The image controller unit 700 processes the image data and the print timing. The image controller unit 700 has an image data generation unit 701, a chip data conversion unit 702, a CPU 703, and a synchronization signal generation unit 704.

[0036] The image data generating unit 701 performs dithering processing on image data received from the scanner unit 100 or from outside the image forming apparatus at a resolution instructed by the CPU 703 to generate image data for print output. In this embodiment, the dithering processing is performed at a resolution of 1200 dpi. The image data is also assumed to represent two gradations with a 1-bit width.

[0037] The synchronization signal generating unit 704 generates a line synchronization signal. The CPU 703 specifies the time interval of the signal period to the synchronization signal generating unit 704, taking the period in which the surface of the photosensitive drum 102 moves in the rotation direction by a pixel size of 1200 dpi (approximately 21.16 μm) for a predetermined rotation speed of the photosensitive drum 102 as one line period. For example, when printing at a speed of 200 mm / s in the paper transport direction, the time interval is specified as one line period of 105.8 μs (two decimal places and below are omitted). The speed in the paper transport direction is calculated by the CPU 703 using the setting value (fixed value) of the printing speed set in the speed control means (not shown) of the photosensitive drum.

[0038] The chip data conversion unit 702 divides one line of image data for each light emitting element array chip in synchronization with a line synchronization signal generated by a synchronization signal generation unit 704, and sends the divided image data to the printed circuit board 202 together with a clock signal and a chip select signal.

[0039] (Printed circuit board) Next, a description will be given of the configuration of the printed circuit board 202. The printed circuit board 202 has a plurality of light-emitting element array chips 400 and a head information storage unit 710.

[0040] The head information storage unit 710 is a storage device that stores head information such as the amount of light emitted and mounting position information of each light-emitting element array chip 400, and is connected to the CPU 703 via a communication signal line 709. The clock signal line 706, the image data signal line 707, the line synchronization signal line 708, and the communication signal line 709 are connected to all of the light-emitting element array chips 400. The chip select signal line 705 is connected to the input of the light-emitting element array chip 400-1. Furthermore, the chip select signal line 705 is connected to the input of the light-emitting element array chip 400-2 via a signal line 711-1, and the output of the light-emitting element array chip 400-1 is connected to the input of the light-emitting element array chip 400-2 via a signal line 711-2. In this way, the chip select signal line 705 is cascade-connected. In each light-emitting element array chip 400, the light-emitting element is caused to emit light based on the setting values ​​set by the input chip select signal, clock signal, line synchronization signal, image data signal, and communication signal. In addition, a chip select signal for the next chip is generated.

[0041] (Digital circuit block inside the chip) 8 shows a circuit block diagram in the light-emitting element array chip 400. The circuit section 406 in the light-emitting element array chip 400 consists of a digital section 800 and an analog section 806. The digital section 800 has the function of generating a pulse signal for emitting light from the light-emitting elements based on a preset value, a chip select signal, an image data signal, and a line synchronization signal, synchronized with a clock signal, and sending the pulse signal to the analog section 806, as well as the function of generating a chip select signal for the next chip from the input chip select signal.

[0042] The communication IF unit 801 controls writing and reading of setting values ​​to and from the register unit 802 based on a communication signal from the CPU 703 .

[0043] The register unit 802 stores setting values ​​necessary for operation. These setting values ​​include exposure timing information used in the image data storage unit 804, width information and delay information of the pulse signal generated by the pulse signal generation unit 805, and setting information of the drive current set by the analog unit 806.

[0044] The chip select signal generator 803 delays the input chip select signal and generates a chip select signal for the next chip.

[0045] The image data storage unit 804 holds image data while the input chip select signal is valid, and outputs the image data to the lighting control unit 807 in synchronization with the line synchronization signal. Details will be described later.

[0046] A pulse signal generating unit 805 (805-0 to 805-5) is provided for each light emitting element column 604 (604-1 to 604-6). The pulse signal generating unit 805 generates a pulse signal required for lighting up the light emitting element in the corresponding light emitting element column based on the width information (pulse width) and delay information (delay time) of the pulse signal set in the register unit 802, and outputs the pulse signal to a lighting control unit 807. Details will be described later.

[0047] The lighting control unit 807 controls, for each light emitting element, whether or not to output a pulse signal from the pulse signal generating unit 805 to the analog unit 806, based on image data from the image data storage unit 804. Details will be described later.

[0048] An analog section 806 generates a signal required to drive a light emitting element based on the pulse signal generated by the digital section 800. Details will be described later.

[0049] Next, a description will be given of the operation of the image data storage unit 804. FIG.

[0050] In this embodiment, the chip select signal is cs_x, the line synchronization signal is lsync_x, and they are negative logic signals, but they may be positive logic. The clock signal is clk, and the image data signal is data. The clock gate circuit 810 outputs the logical product of the inverted signal of the chip select signal cs_x and the clock signal clk, and outputs the clock signal s_clk to the flip-flop circuit 811 only when cs_x is valid. The flip-flop circuit 811 receives the image data signal data input to the image data storage unit 804 as its original input, and the same number of light emitting elements (748 in this embodiment) as the number of light emitting elements provided in the longitudinal direction of the light emitting element array chip are connected in series. The flip-flop circuit 811 operates with the clock signal s_clk sent from the clock gate circuit 810.

[0051] The flip-flop circuits will be described below. As representatives, flip-flop circuits 812-000, 813-000, 814-000, 815-000, 816-000, and 817-000 will be described. The same applies to the other flip-flop circuits 812-001 to 812-747, 813-001 to 813-747, 814-001 to 814-747, 815-001 to 815-747, 816-001 to 816-747, and 817-001 to 817-747.

[0052] The flip-flop circuit 812-000 receives the output (dly_data_000) of the flip-flop circuit 811-000 as an input and operates with the line synchronization signal lsync_x. The output (buf_data_0_000) of the flip-flop circuit 812-000 is input to the lighting control unit 807 and the flip-flop circuit 813-000. The flip-flop circuit 813-000 receives the output (buf_data_0_000) of the flip-flop circuit 812-000 as an input and operates with the line synchronization signal lsync_x. The output (buf_data_1_000) of the flip-flop circuit 813-000 is input to the flip-flop circuit 814-000 and the lighting control unit 807. The flip-flop circuit 814-000 receives the output (buf_data_1_000) of the flip-flop circuit 813-000 as an input and operates with the line synchronization signal lsync_x. The output (buf_data_2_000) of the flip-flop circuit 814-000 is input to the flip-flop circuit 815-000 and the lighting control unit 807. The flip-flop circuit 815-000 receives the output (buf_data_2_000) of the flip-flop circuit 814-000 as an input and operates with the line synchronization signal lsync_x. The output (buf_data_3_000) of the flip-flop circuit 815 is input to the flip-flop circuit 816-000 and the lighting control unit 807. The flip-flop circuit 816-000 receives the output (buf_data_3_000) of the flip-flop circuit 815-000 as an input, and operates with the line synchronization signal lsync_x. The output (buf_data_4_000) of the flip-flop circuit 816-000 is input to the flip-flop circuit 817-000 and the lighting control unit 807. The flip-flop circuit 817-000 receives the output (buf_data_4_000) of the flip-flop circuit 816-000 as an input, and operates with the line synchronization signal lsync_x. The output (buf_data_5_000) of the flip-flop circuit 817-000 is input to the lighting control unit 807.

[0053] FIG. 10 is a timing chart showing the operation of the image data storage unit 804 in the longitudinal direction of the photosensitive drum. The signal names in the diagram are shown in FIG. 9. Between time T0 and time T1, when cs_x=0 is captured by the rising edge of clk, the image data is shifted in order from data → dly_data_000 → dly_data_001 → .... When cs_x=0, the clock signal is input in the same number as the number of light-emitting elements in the longitudinal direction of the photosensitive drum, that is, 748. In this way, one line's worth of image data is stored in dly_data_000 to dly_data_747. After time T1, cs_x=1, so the data is stored without being shifted. When lsync_x=0 is captured at the rising edge of clk at time T2, image data for one line is shifted simultaneously as buf_data_0_000 to buf_data_0_000, dly_data_001 to buf_data_0_001, . . . and output to the lighting control unit 807.

[0054] Fig. 11 is a timing chart showing the operation in the rotation direction of the photosensitive drum of the image data storage unit 804. Fig. 11 representatively describes the output buf_data_0_000 of flip-flop circuit 812-000, the output buf_data_1_000 of flip-flop circuit 813-000, the output buf_data_2_000 of flip-flop circuit 814-000, the output buf_data_3_000 of flip-flop circuit 815-000, the output buf_data_4_000 of flip-flop circuit 816-000, and the output buf_data_5_000 of flip-flop circuit 817-000 shown in Fig. 9. The same is true for all of the outputs buf_data_0_001 to buf_data_0_747, buf_data_1_001 to buf_data_1_747, buf_data_2_001 to buf_data_2_747, buf_data_3_001 to buf_data_3_747, buf_data_4_001 to buf_data_4_747, and buf_data_5_001 to buf_data_5_747 of the other flip-flop circuits shown in FIG.

[0055] As shown in the figure, each time lsync_x=0 is input, the value shifts from dly_data_000 to buf_data_0_000, from buf_data_0_000 to buf_data_1_000, and so on. Therefore, the value B000 of dly_data_000 at time T0 is output to the lighting control unit 807 as buf_data_0_000 at time T1, buf_data_1_000 at time T2, buf_data_2_000 at time T3, and so on. Multiple exposure is realized by connecting buf_data_0_000, buf_data_1_000, buf_data_2_000, buf_data_3_000, buf_data_4_000, and buf_data_5_000 in order from the light-emitting element that is exposed first on the photosensitive drum.

[0056] Next, the pulse signal generating unit (pulse signal generating circuit) 805 will be described. There are the same number of pulse signal generating units 805 (805-0 to 805-5) as the number of light emitting element rows, but they all have the same structure. Therefore, pulse signal generating unit 805-0 will be described here as an example. Figure 12(a) shows a block diagram of the pulse signal generating circuit, and Figure 12(b) shows an operation timing chart of the pulse signal generating circuit.

[0057] The pulse signal generating unit 805-0 includes an output determining unit 903 and a counter unit 904.

[0058] The counter unit 904 counts the clock and resets the count at each period c of the line synchronization signal (timing C1 and timing C2 in FIG. 12(b)).

[0059] The output determination unit 903 generates a pulse signal according to the count, pulse width b, and delay time a. The output determination unit 903 generates a pulse signal that makes the output High when the count generated by the counter unit 904 becomes the delay time a (timing A in FIG. 12(b)) and makes the output Low when the count becomes a+b after the time of pulse width b has elapsed (timing B in FIG. 12(b)).

[0060] The delay time a and pulse width b are transmitted from the register unit 802, and their values ​​can be changed in units of clock cycles by rewriting the register unit 802. The delay time a corresponds to the time that determines the timing at which light emission starts for each cycle of the line synchronization signal. The pulse width b corresponds to the lighting time of the light-emitting element, and is roughly proportional to the amount of light emitted by the light-emitting element. Therefore, the pulse width b is adjusted so as to obtain the necessary integrated amount of light on the photosensitive drum surface. The delay time a and pulse width b that determine the timing at which light emission starts can be set individually by the pulse signal generating units 805-0 to 805-5 for each row of light-emitting elements. Therefore, the delay time a and pulse width b for the pulse signal generating unit 805-0 are represented as a0 and b0, respectively. Similarly, the delay time a and pulse width b for pulse signal generation unit 805-1 are represented as a1 and b1, the delay time a and pulse width b for pulse signal generation unit 805-2 are represented as a2 and b2, the delay time a and pulse width b for pulse signal generation unit 805-3 are represented as a3 and b3, the delay time a and pulse width b for pulse signal generation unit 805-4 are represented as a4 and b4, and the delay time a and pulse width b for pulse signal generation unit 805-5 are represented as a5 and b5.

[0061] Each pulse signal generating unit 805 generates a pulse signal (line_pulse) for each light-emitting element row to emit light based on the delay time (delay setting value a) from the input timing of the line synchronization signal to the start timing at which light emission begins, and the pulse width (pulse width setting value b) from the start timing to the end timing at which the light emission ends.

[0062] In other words, the pulse signal generating unit 805 sets the delay time and the pulse width for each light emitting element row. Here, the light emitting element row refers to each of a plurality of light emitting element rows arranged in order in the drum rotation direction in one light emitting element array chip. In this embodiment, a configuration is exemplified in which one light emitting element array chip has 6 light emitting element rows (first, second, third, fourth, fifth, and sixth light emitting element rows) arranged in order in the drum rotation direction.

[0063] The pulse signal generating unit 805-0 generates a first pulse signal (line_pulse_0) for causing the first light-emitting element row to emit light based on a first delay time (delay setting value a0) from the input timing C1 of the line synchronization signal to the first start timing at which light emission starts, and a first pulse width (pulse width setting value b0) from the first start timing to the first end timing at which the light emission ends by the input timing C2 of the next line synchronization signal.

[0064] The pulse signal generating unit 805-1 generates a second pulse signal (line_pulse_1) for causing the second light-emitting element row to emit light based on a second delay time (delay setting value a1) that is different from the first delay time (delay setting value a0) from the input timing C1 of the line synchronization signal to the second start timing at which light emission starts, and a second pulse width (pulse width setting value b1) that is the same as the first pulse width (pulse width setting value b0) from the second start timing to the second end timing at which the light emission ends by the input timing C2 of the next line synchronization signal.

[0065] Here, the setting values ​​for setting the pulse signal for each light-emitting element row satisfy a0≠a1, b0=b1, and a0+b0≠a1+b1 when the first delay time of the first light-emitting element row is set to delay setting value a0, the first pulse width is set to pulse width setting value b0, and the second delay time of the second light-emitting element row is set to delay setting value a1, and the second pulse width is set to pulse width setting value b1.

[0066] The third pulse signal (line_pulse_2) of the third light-emitting element row, the fourth pulse signal (line_pulse_3) of the fourth light-emitting element row, the fifth pulse signal (line_pulse_4) of the fifth light-emitting element row, and the sixth pulse signal (line_pulse_5) of the sixth light-emitting element row are also generated in a similar manner to the relationship between the first pulse signal of the first light-emitting element row and the second pulse signal of the second light-emitting element row.

[0067] That is, the delay setting value, which is the delay time a of each light-emitting element row, satisfies a0≠a1≠a2≠a3≠a4≠a5 in order to shift the pulse signals that change simultaneously. Also, the pulse width setting value, which is the pulse width b, satisfies b5=b4=b3=b2=b1=b0. Also, the delay setting values ​​a0 to a5 and the pulse width setting values ​​b0 to b5 satisfy a0+b0≠a1+b1≠a2+b2≠a3+b3≠a4+b4≠a5+b5. By setting in this way, even during multiple exposure, the start timing (timing A in FIG. 12(b)) of each pulse signal transitioning from Low to High does not overlap, and the end timing (timing B in FIG. 12(b)) of each pulse signal transitioning from High to Low does not overlap. According to this setting, the light emission of each light-emitting element row starts and ends. Therefore, there is no timing when the pulse signals of a plurality of light emitting element rows arranged in the drum rotation direction in one light emitting element array chip change simultaneously, making it possible to reduce switching noise.

[0068] In this embodiment, the pulse width is the same for the pulse signals in which the start and end timings of the light emitting element rows for each period of the line synchronization signal do not overlap, so that the integrated light amount of each light emitting element row can be kept uniform even if the drive current set in the analog section described later does not need to be changed for each pulse signal.

[0069] Next, the lighting control unit 807 will be described with reference to Fig. 14. Fig. 14 is a block diagram of the lighting control unit 807.

[0070] The lighting control unit 807 controls whether or not to output a pulse signal for each light-emitting element column generated by the pulse signal generating units 805-0 to 805-5 to the analog unit 806 for each light-emitting element in accordance with the image data input from the image data storage unit 804.

[0071] The output pulse signals el_pulse_0_000 to el_pulse_0_747 correspond to the light emitting elements 602-11 to 602-1748. The output pulse signals el_pulse_1_000 to el_pulse_1_747 correspond to the light emitting elements 602-21 to 602-2748. The output pulse signals el_pulse_2_000 to el_pulse_2_747 correspond to the light emitting elements 602-31 to 602-3748. The output pulse signals el_pulse_3_000 to el_pulse_3_747 correspond to the light emitting elements 602-41 to 602-4748. The output pulse signals el_pulse_4_000 to el_pulse_4_747 correspond to the light emitting elements 602-51 to 602-5748. The output pulse signals el_pulse_5_000 to el_pulse_5_747 correspond to the light emitting elements 602-61 to 602-6748.

[0072] The lighting control unit 807 is provided with AND gates 1200 the number of which corresponds to the number of light-emitting elements. Note that in this embodiment, both the image signals buf_data_0_000 to buf_data_5_747 from the image data storage unit 804 and the pulse signals line_pulse_0 to line_pulse_5 from the pulse signal generation unit 805 (805-0 to 805-5) are positive logic, and the output pulse signals el_pulse_0_000 to el_pulse_5_747 to the analog unit indicate lighting when they are 1, so AND gates are used, but if any of the inputs and outputs is negative logic, a logic gate corresponding to that may be used.

[0073] The AND gates 1200-0-000 to 1200-0-747 receive the pulse signal line_pulse_0 generated by the pulse signal generating unit 805-0 in common at one end and the image signals buf_data_0_000 to buf_data_0_747 at the other end, respectively. The AND gates 1200-0-000 to 1200-0-747 output the logical products of both signals as el_pulse_0_000 to el_pulse_0_747.

[0074] The AND gates 1200-1-000 to 1200-1-747 receive the pulse signal line_pulse_1 generated by the pulse signal generating unit 805-1 in common to one input, and the image signals buf_data_1_000 to buf_data_1_747 to the other input, respectively. The AND gates 1200-1-000 to 1200-1-747 output the logical products of both signals as el_pulse_1_000 to el_pulse_1_747.

[0075] The AND gates 1200-2-000 to 1200-2-747 receive the pulse signal line_pulse_2 generated by the pulse signal generating unit 805-2 in common at one end and the image signals buf_data_2_000 to buf_data_2_747 at the other end, respectively. The AND gates 1200-2-000 to 1200-2-747 output the logical products of both signals as el_pulse_2_000 to el_pulse_2_747.

[0076] The AND gates 1200-3-000 to 1200-3-747 receive the pulse signal line_pulse_3 generated by the pulse signal generating unit 805-3 in common at one end and the image signals buf_data_3_000 to buf_data_3_747 at the other end, respectively. The AND gates 1200-3-000 to 1200-3-747 output the logical products of both signals as el_pulse_3_000 to el_pulse_3_747.

[0077] The AND gates 1200-4-000 to 1200-4-747 receive the pulse signal line_pulse_4 generated by the pulse signal generating unit 805-4 in common at one end and the image signals buf_data_4_000 to buf_data_4_747 at the other end, respectively. The AND gates 1200-4-000 to 1200-4-747 output the logical products of both signals as el_pulse_4_000 to el_pulse_4_747.

[0078] The AND gates 1200-5-000 to 1200-5-747 receive the pulse signal line_pulse_5 generated by the pulse signal generating unit 805-5 in common at one end and the image signals buf_data_5_000 to buf_data_5_747 at the other end, respectively. The AND gates 1200-5-000 to 1200-5-747 output the logical products of both signals as el_pulse_5_000 to el_pulse_5_747.

[0079] As described above, whether or not to output the pulse signal generated for each light emitting element row to the analog unit 806 is controlled by the value of the image data signal.

[0080] Next, the analog unit 806 will be described. Fig. 13(a) shows a block diagram of the analog unit 806. In this embodiment, for the sake of simplicity, the analog unit 806 will be described by illustrating drive units 1001-1 and 1001-2 that drive two light-emitting elements (602-11 and 602-21). However, it is assumed that the analog unit 806 has similar drive units formed corresponding to all light-emitting elements of the light-emitting element group 201.

[0081] In the lighting control unit 807, a pulse signal for controlling the ON timing of the light emitting element is generated, and the pulse signal is input to the driving units 1001-1 and 1001-2 via signal lines 1006-1 and 1006-2. The DAC 1002 (digital-analog converter) supplies an analog voltage for determining a driving current to the driving units 1001-1 and 1001-2 via a signal line 1003 based on the data set in the register unit 802. The driving unit selection unit 1007 supplies a driving unit select signal for selecting a driving unit to the driving units 1001-1 and 1001-2 via signal lines 1004 and 1005 based on the data set in the register unit 802. The driving unit select signal is generated so that only the signal connected to the selected driving unit becomes High. For example, when the driving unit 1001-1 is selected, High is supplied only to the signal line 1004, and Low is supplied to the signal lines connected to other driving units such as the signal line 1005. The analog voltage input via signal line 1003 is set for each of drive units 1001-1 and 1001-2 at the timing selected by drive unit selection unit 1007 (the timing when the drive unit select signal goes High). CPU 703 (see FIG. 7) sequentially selects drive units via register unit 802 and sets a voltage corresponding to the selected drive unit, thereby setting analog voltages for all drive units with one DAC 1002. By the above-mentioned operation, analog voltages and pulse signals that determine the drive current are input to drive units 1001-1 and 1001-2, and the drive current and light emission time of each light emitting element (602-11, 602-21) are independently controlled by a drive circuit described below.

[0082] FIG. 13(b) shows the circuit of the driving unit 1001-1. Note that the driving units (for example, 1001-2) for other light emitting elements are also driven by a similar circuit. The MOSFET 1102 supplies a driving current to the light emitting element 602-11 according to the gate voltage value, and controls the current so that the driving current is turned off (turned off) when the gate voltage is at a low level. A pulse signal transmission line 1006 is connected to the gate of the MOSFET 1104, and when the pulse signal is high, the voltage charged in the capacitor 1106 is transferred to the MOSFET 1102. The MOSFET 1107 is connected to the gate of the driving unit select signal (transmitted from a signal line 1004) transmitted from the driving unit selection unit 1007. When the received driving unit select signal is high, the MOSFET 1107 turns on and charges the analog voltage output from the DAC 1002 (transmitted from a signal line 1003) in the capacitor 1106. In this embodiment, the DAC 1002 sets an analog voltage in the capacitor 1106 at a timing before image formation, and keeps the voltage level by turning off the MOSFET 1107 during the image formation period. With the above operation, the MOSFET 1102 supplies a drive current to the light emitting element 602-11 in response to the set analog voltage and the pulse signal. If the input capacitance of the light emitting element 602-11 is large and the response speed when turned off is slow, the MOSFET 1103 can speed up the turn-off speed. A signal obtained by logically inverting the pulse signal by the inverter 1105 is input to the gate of the MOSFET 1103. When the pulse signal is Low, the gate of the MOSFET 1103 becomes High, and the charge charged in the input capacitance of the light emitting element 602-11 is forcibly discharged.

[0083] Here, the delay time a and pulse width b set in the pulse signal generating units 805-0 to 805-5 corresponding to each light emitting element row will be specifically described. In this embodiment, the delay time a and pulse width b set in the pulse signal generating units 805-0 to 805-5 corresponding to each light emitting element row are set according to the table shown in Fig. 15. Note that the setting values ​​shown in Fig. 15 are merely examples and are not limited thereto, and should be set appropriately as necessary.

[0084] In Fig. 15, the target circuits are pulse signal generating units 805-0 to 805-5 corresponding to each light-emitting element column shown in Fig. 8. The set values ​​of delay time a and pulse width b are signals from register unit 802, and are set in the pulse signal generating units corresponding to each light-emitting element column. The values ​​of delay time a and pulse width b set in pulse signal generating units 805-0 to 805-5 corresponding to each light-emitting element column shown in Fig. 15 are determined so as to satisfy the following conditions.

[0085] The delay time a, which is condition 1, is a different value for each light-emitting element column. That is, the set value of the delay time a set in the pulse signal generating unit 805 corresponding to each light-emitting element column satisfies a0 ≠ a1 ≠ a2 ≠ a3 ≠ a4 ≠ a5. The set value 10 of the delay time a shown in FIG. 15 is the set value a0 of the delay time a set in the pulse signal generating unit 805-0 corresponding to the light-emitting element column 604-1. The set value 20 of the delay time a is the set value a1 of the delay time a set in the pulse signal generating unit 805-1 corresponding to the light-emitting element column 604-2. The set value 30 of the delay time a is the set value a2 of the delay time a set in the pulse signal generating unit 805-2 corresponding to the light-emitting element column 604-3. The set value 40 of the delay time a is the set value a3 of the delay time a set in the pulse signal generating unit 805-3 corresponding to the light-emitting element column 604-4. The setting value 50 of the delay time a is the setting value a4 of the delay time a set in the pulse signal generating unit 805-4 corresponding to the light-emitting element column 604-5. The setting value 50 of the delay time a is the setting value a5 of the delay time a set in the pulse signal generating unit 805-5 corresponding to the light-emitting element column 604-6.

[0086] The result of adding the delay time a and the pulse width b, which is condition 2, is a different value for each light-emitting element column. That is, the result of adding the set value of the delay time a and the set value of the pulse width b corresponding to each light-emitting element column satisfies a0+b0≠a1+b1≠a2+b2≠a3+b3≠a4+b4≠a5+b5. The set value of the pulse width b satisfies b0=b1=b2=b3=b4=b5.

[0087] Condition 1 is a condition for shifting the timing at which light emission starts in each light-emitting element column for each period of the line synchronization signal, thereby preventing light-emitting elements in different light-emitting element columns from lighting up at the same time.

[0088] Condition 2 is a condition for shifting the timing of ending light emission of each light emitting element column for each period of the line synchronization signal, thereby preventing light emitting elements in different light emitting element columns from being turned off at the same time.

[0089] As described above, in this embodiment, the two-dimensionally arranged light-emitting elements are divided into several regions (in this embodiment, six regions are formed with each light-emitting element row as one region), and the timing for starting and turning off the light-emitting elements in each region is shifted. This reduces the number of simultaneous switching events per period of the line synchronization signal, thereby reducing switching noise.

[0090] Example 2 An image forming apparatus equipped with an exposure head according to Example 2 will be described. In this example, the overall configuration of the image forming apparatus and the basic configuration of the exposure head are the same as those in Example 1. In this example, the pulse signal generating unit 1405 in the digital unit 800 in the light-emitting element array chip 400 and the connection of its signal line are different from those in Example 1. In this example, the differences from Example 1 will be described.

[0091] In the first embodiment, the light emitting elements of each light emitting element row are exposed multiple times at the same exposure position to form pixels of each line, but the timings at which light emission starts and ends are different for each light emitting element row. Therefore, the pixels of each line (light emitting element row) form latent images at different positions relative to the rotation direction of the photosensitive drum 102. Specifically, as shown in FIG. 18(a), the latent image formed by the light emitting elements of the second light emitting element row 604-2 differs in position in the drum rotation direction from the latent image formed by the light emitting elements of the first light emitting element row 604-1 by the difference between the delay setting value a0 and the delay setting value a1, which are delay times. Therefore, the latent image formed by the multiple exposure may be blurred.

[0092] Therefore, in this embodiment, when the exposure position exposed by the first light emitting element row 604-1 is subjected to multiple exposure by the second light emitting element row 604-2, the following procedure is taken.

[0093] That is, a pulse signal for causing the second light-emitting element row 604-2 to emit light is set in the period of the line synchronization signal for multiple exposure in the second light-emitting element row 604-2, based on the first delay time T set for the first light-emitting element row 604-1 in the period of the line synchronization signal immediately preceding that.

[0094] Furthermore, a pulse signal for causing the first light emitting element row 604-1 to emit light is set based on a delay time different from the first delay time T set for the first light emitting element row 604-1 in the period of the immediately preceding line synchronization signal.

[0095] A specific description will be given with reference to Figs. 16 to 20.

[0096] 16 shows a circuit block diagram in the light-emitting element array chip 400 in the second embodiment. Compared to the first embodiment, the configuration of the pulse signal generating unit (pulse signal generating circuit) 1405 corresponding to each light-emitting element column in the light-emitting element array chip is different. In this embodiment, the pulse signal generating units 1405-0 to 1405-5 of each light-emitting element column are connected to the previous-stage pulse signal generating unit and the next-stage pulse signal generating unit by a signal line that transmits a delay time signal so that the delay time signal set in the previous-stage pulse signal generating unit is transmitted to the next-stage pulse signal generating unit. That is, the pulse signal generating unit 1405-0, which is the previous-stage pulse signal generating unit, is connected to the pulse signal generating unit 1405-1, which is the next-stage pulse signal generating unit, by a signal line. Similarly, pulse signal generating unit 1405-1 is connected to pulse signal generating unit 1405-2 of the next stage, pulse signal generating unit 1405-2 is connected to pulse signal generating unit 1405-3 of the next stage, pulse signal generating unit 1405-3 is connected to pulse signal generating unit 1405-4 of the next stage, and pulse signal generating unit 1405-4 is connected to pulse signal generating unit 1405-5 of the next stage. Details of this delay time signal will be described later.

[0097] 17(a) is a block diagram of the pulse signal generating unit (pulse signal generating circuit) 1405. The pulse signal generating units 1405 (1405-0 to 1405-5) are provided for each of the light emitting element columns 604 (604-1 to 604-6). There are as many pulse signal generating units 1405 (1405-0 to 1405-5) as there are light emitting element columns, but they all have the same structure.

[0098] The pulse signal generating unit 1405 includes an output determining unit 903 and a counter unit 904. The operations of the counter unit 904 and the output determining unit 903 are similar to those in the first embodiment.

[0099] Furthermore, the pulse signal generating unit 1405 has a random number generating unit 1501 and a previous stage delay time storage unit 1502. The random number generating unit 1501 is a delay time generating unit that generates a different delay time for each period of the line synchronization signal. The previous stage delay time storage unit 1502 is a delay time storage unit that stores a delay time set for the light emitting element row.

[0100] In the pulse signal generating unit 805 of the first embodiment, the delay time a in FIG. 12(a) is a signal from the register unit 802, and any value can be set in the register unit 802. In this embodiment, the signal corresponding to the delay time a is the delay time T, and this delay time T can be selected from the following two types of signals. The selection of this delay time T is determined by the delay time selection s. The delay time selection s is a signal from the register unit 802, and can be selected by rewriting the register unit 802.

[0101] The two types of signals selected as the delay time T will be described. One of the two types of signals is a random number generated by the random number generating unit 1501. This random number is generated by the random number generating unit 1501, and the value is updated every time the line synchronization signal is asserted. The random number can be generated by writing the random numbers in advance to a memory and sequentially reading them out, or by generating them as pseudo-random numbers using an M sequence consisting of a shift register and an exclusive OR. The other of the two types of signals is a delay time signal of the previous stage. Here, the previous stage refers to the pulse signal generating unit corresponding to the first light-emitting element row as seen from the pulse signal generating unit corresponding to the second light-emitting element row when multiple exposure is performed with the second light-emitting element row at an exposure position exposed with the first light-emitting element row. Therefore, when the pulse signal generating unit 1405 shown in FIG. 12(a) is the pulse signal generating unit 1405-1 corresponding to the second light-emitting element row, the previous stage delay time signal and the next stage delay time signal are as follows.

[0102] The previous stage delay time signal is the next stage delay time signal output by the pulse signal generating unit 1401-0 corresponding to the first light emitting element column to the pulse signal generating unit 1405-1 corresponding to the second light emitting element column. Similarly, the previous stage delay time signal is the next stage delay time signal output by the pulse signal generating unit 1401-1 corresponding to the second light emitting element column to the pulse signal generating unit 1401-2 corresponding to the third light emitting element column. The previous stage delay time signal is the next stage delay time signal output by the pulse signal generating unit 1401-2 corresponding to the third light emitting element column to the pulse signal generating unit 1401-3 corresponding to the fourth light emitting element column. The previous stage delay time signal is the next stage delay time signal output by the pulse signal generating unit 1401-3 corresponding to the fourth light emitting element column to the pulse signal generating unit 1401-4 corresponding to the fifth light emitting element column. The previous stage delay time signal is a next stage delay time signal output by the pulse signal generation unit 1401-4 corresponding to the fifth light emitting element column to the pulse signal generation unit 1401-5 corresponding to the sixth light emitting element column. However, since the pulse signal generation unit 1401-0 has no previous stage, the delay time selection s is set to 0. Each previous stage delay time storage unit 502 after the pulse signal generation unit 1405-1 updates the input previous stage delay time signal (next stage delay time signal), that is, the delay time T, for each input (period) of the line synchronization signal.

[0103] The delay time T can be determined by selecting these two types of signals with the delay time selection s, which is a signal from the register unit 802. Specifically, when the delay time selection s is 0, the random number generated by the random number generation unit 1501 is selected as the delay time T, and when the delay time selection s is 1, the previous stage delay time signal stored in the previous stage delay time storage unit 1502 is selected as the delay time T. In this embodiment, the set value of the delay time selection s and the set value of the pulse width b are shown in FIG. 17(b). That is, in this embodiment, the delay time selection s and the pulse width b set in the pulse signal generation units 1405-0 to 1405-5 corresponding to each light emitting element row are set according to the table shown in FIG. 17(b). Note that the set values ​​shown in FIG. 17(b) are merely examples and are not limited thereto, and should be set appropriately as necessary.

[0104] In Fig. 17(b), the target circuits are pulse signal generating units (pulse signal generating circuits) 1405-0 to 1405-5 corresponding to each light-emitting element column shown in Fig. 16. Also, the setting value of delay time selection s and the setting value of pulse width b are signals from a register unit, and are set in the pulse signal generating units 1405-0 to 1405-5 corresponding to each light-emitting element column, respectively.

[0105] The operation of the pulse signal generating unit will be described with reference to Fig. 19(a) and Fig. 19(b). Fig. 19(a) is a timing chart of the pulse signal generating unit 1405-0 shown in Fig. 16 in this embodiment. The pulse signal generating unit 1405-0 has the output determining unit 903, the counter unit 904, the random number generating unit 1501, and the front-stage delay time storage unit 1502 as described above.

[0106] The counter unit 904 counts the clock and resets the count at each line synchronization signal period c (timing C1 and timing C2 in FIG. 19(a)).

[0107] An output determination unit 903 generates a pulse signal according to the count, pulse width b, and delay time T. A pulse signal is generated by setting the output to High when the count generated by the counter unit 904 becomes R1 (timing A in FIG. 19(a)), and setting the output to Low when the count becomes R1+b after the time of pulse width b has elapsed (timing B in FIG. 19(a)).

[0108] The pulse width b is transmitted from a register unit 802, and the value can be changed in units of a clock cycle by rewriting the register unit 802. The delay time T is updated as a random number every time the line synchronization signal is asserted.

[0109] Next, the delay time T of each of the pulse signal generating units 1405-0 to 1405-5 corresponding to each light emitting element column will be described. Fig. 19(b) is a timing chart showing the operation of the delay time T of each circuit of the pulse signal generating units 1405-0 to 1405-5. For the delay time T of the pulse signal generating unit 1405-0, which has no previous stage, a random number is generated every time the line synchronization signal is asserted. In Fig. 19(b), random numbers are generated in sequence R0, R1, R2, and used as the delay time T. On the other hand, for the pulse signal generating units 1405-1 and onwards, which have a previous stage, the delay time T of the previous stage is used, and therefore the shift register operates every time the line synchronization signal is asserted.

[0110] That is, for each period of the line synchronization signal, the delay time T of the previous stage pulse signal generating unit 1405-0 is stored in the previous stage delay time storage unit 1502 of the next stage pulse signal generating unit 1405-1. Then, upon input of the next line synchronization signal, a pulse signal for causing the second light emitting element row to emit light is generated in the pulse signal generating unit 1405-1 based on the delay time T stored in the previous stage delay time storage unit 1502. Similarly, for other pulse signal generating units having a previous stage, the delay time T of the previous stage is stored in the period of the immediately preceding synchronization signal, and a pulse signal is generated based on the delay time T of the previous stage stored in the previous stage delay time storage unit 1502 upon input of the next line synchronization signal.

[0111] The transition of the sections in which the light emitting elements of the light emitting element columns 604-1 to 604-6 are lit up in this embodiment is shown in FIG. 20(a), FIG. 20(b), and FIG. 20(c).

[0112] FIG. 20(a) shows the light emission sections of each of the light emitting element columns 604-1 to 604-6 when the Nth line synchronization signal is input. When the line synchronization signal is input, a random number is generated by the random number generation unit 1501 of the pulse signal generation unit 1405-0 corresponding to the light emitting element column 604-1 (random number 1 in the figure), and the delay time T (light emission start timing) of the light emitting element column 604-1 is determined. In addition, the delay time T (random number 1) of the light emitting element column 604-1 is sent to the pulse signal generation unit 1405-1 corresponding to the next stage light emitting element column 604-2, and is stored in the previous stage delay time storage unit 1502 of the pulse signal generation unit 1405-1. Then, each pulse signal generation unit generates a pulse signal for causing each light emitting element column shown in FIG. 20(a) to emit light based on the delay time of the start timing that differs for each light emitting element column.

[0113] Next, FIG. 20(b) shows the light emission sections of each of the light emitting element columns 604-1 to 604-6 when the N+1th line synchronization signal is input. When the line synchronization signal is input, a random number is generated by the random number generation unit 1501 of the pulse signal generation unit 1405-0 corresponding to the light emitting element column 604-1 (random number 2 in the figure), and the delay time T (light emission start timing) of the light emitting element column 604-1 is determined. At this time, the random number is changed to random number 2, which is different from random number 1 at the time of the Nth line synchronization signal. In other words, the random number generation unit 1501 generates a delay time (random number 2) different from the delay time T (random number 1) set for the light emitting element column 604-1 in the period of the Nth line synchronization signal, which is the immediately preceding line synchronization signal. Also, for the light emitting element column 604-2, the delay time T stored in the previous stage delay time storage unit 1502 is selected by the setting value 1, which is a signal of the delay time selection s. Here, the delay time T stored in the previous stage delay time storage unit 1502 is the delay time T (random number 1) set for the light emitting element column 604-1 in the period of the Nth line synchronization signal, which is the immediately preceding line synchronization signal. Therefore, the light emitting element column 604-2 corresponding to the pulse signal generation unit 1405-1 is determined to have a lighting period at the same timing as the light emitting element column 604-1 at the time of the Nth line synchronization signal. The delay time T (random number 2) of the light emitting element column 604-1 is sent to the pulse signal generation unit 1405-1 corresponding to the next stage light emitting element column 604-2, and is stored in the previous stage delay time storage unit 1502 of the pulse signal generation unit 1405-1. The delay time T (random number 1) of the light emitting element column 604-2 is sent to the pulse signal generation unit 1405-2 corresponding to the next stage light emitting element column 604-3, and is stored in the previous stage delay time storage unit 1502 of the pulse signal generation unit 1405-2. Then, each pulse signal generating section generates a pulse signal for causing each light emitting element column shown in FIG. 20(b) to emit light, based on a delay time of the start timing that differs for each light emitting element column.

[0114] Next, FIG. 20(c) shows the light emission sections of each of the light emitting element columns 604-1 to 604-6 when the N+2th line synchronization signal is input. When the line synchronization signal is input, a random number is generated by the random number generation unit 1501 of the pulse signal generation unit 1405-0 corresponding to the light emitting element column 604-1 (random number 3 in the figure), and the delay time T (light emission start timing) of the light emitting element column 604-1 is determined. At this time, the random number is changed to random number 3, which is different from random number 1 at the time of the Nth line synchronization signal and different from random number 2 at the time of the N+1th line synchronization signal. The random number generation unit 1501 generates different random numbers at least for the number of light emitting element columns that one light emitting element array chip has. Also, for the light emitting element column 604-2, the delay time T stored in the previous stage delay time storage unit 1502 is selected by the set value 1, which is a signal of the delay time selection s. Here, the delay time T stored in the previous delay time storage unit 1502 is the delay time T (random number 2) set in the light emitting element column 604-1 in the period of the N+1th line synchronization signal, which is the immediately preceding line synchronization signal. Therefore, the light emitting element column 604-2 has a lighting period determined at the same timing as the light emitting element column 604-1 at the N+1th line synchronization signal. Similarly, the light emitting element column 604-3 has a delay time T stored in the previous delay time storage unit 1502 selected by the setting value 1, which is the delay time selection s signal. Here, the delay time T stored in the previous delay time storage unit 1502 is the delay time T (random number 1) set in the light emitting element column 604-2 in the period of the N+1th line synchronization signal, which is the immediately preceding line synchronization signal. Therefore, the light emitting element column 604-3 has a lighting period determined at the same timing as the light emitting element column 604-2 at the N+1th line synchronization signal. The delay time T (random number 3) of the light-emitting element column 604-1 is sent to the pulse signal generating unit 1405-1 corresponding to the next-stage light-emitting element column 604-2, and is stored in the previous-stage delay time storage unit 1502 of the pulse signal generating unit 1405-1. The delay time T (random number 2) of the light-emitting element column 604-2 is sent to the pulse signal generating unit 1405-2 corresponding to the next-stage light-emitting element column 604-3, and is stored in the previous-stage delay time storage unit 1502 of the pulse signal generating unit 1405-2.Further, the delay time T (random number 1) of the light-emitting element column 604-3 is sent to the pulse signal generating unit 1405-3 corresponding to the next-stage light-emitting element column 604-4, and is stored in the previous-stage delay time storage unit 1502 of the pulse signal generating unit 1405-3. Then, each pulse signal generating unit generates a pulse signal for causing each light-emitting element column shown in FIG. 20(c) to emit light, based on the delay time of the start timing that differs for each light-emitting element column.

[0115] In this way, even though the light emission timing and the light-off timing are changed for each light-emitting element row, the pixels of each line (light-emitting element row) form latent images at the same positions in the rotation direction of the photosensitive drum 102. Specifically, as shown in Fig. 18(b), the latent images formed by the light-emitting elements of the first light-emitting element row 604-1 and the latent images formed by the light-emitting elements of the second light-emitting element row 604-2 have the same delay time, and therefore the exposure positions in the drum rotation direction are the same. This makes it possible to suppress blurring of the latent image due to multiple exposures, and to form a latent image with sharper edges. [Explanation of symbols]

[0116] 102 ... Photosensitive drum 106 ... exposure head 201 ... light emitting element group 202 ... Printed circuit board 400 ... Light emitting element array chip 604 ... Light emitting element row 700 …Image controller section 703...CPU 710 ... Head information storage unit 800 ... Digital section 801 ... Communication IF section 802 ... Register section 803 ... Chip select signal generator 804 ... Image data storage unit 805 ... Pulse signal generating unit 806 ... Analog section 807 ... Lighting control unit 903 ... Output determination unit 904 …Counter section 1501 ...Random number generator 1502 ... Front-stage delay time memory unit

Claims

1. A photoconductor; an exposure device having a chip in which a first light-emitting element row formed of a plurality of light-emitting elements arranged along a first direction which is a rotation axis direction of the photosensitive member, and a second light-emitting element row formed of a plurality of light-emitting elements arranged along the first direction are sequentially arranged in a second direction perpendicular to the first direction, and which performs multiple exposure with the second light-emitting element row at exposure positions exposed by the first light-emitting element row on the photosensitive member; a controller that transmits a signal to the exposure apparatus for controlling the exposure apparatus; Equipped with The exposure apparatus includes: setting a first pulse signal for causing the first light-emitting element row to emit light based on a first delay time from an input timing of a line synchronization signal to a first start timing at which light emission is started and a first pulse width from the first start timing to a first end timing at which the light emission is ended by the input timing of a line synchronization signal next to the line synchronization signal; a second pulse signal for causing the second light emitting element row to emit light based on a second delay time different from the first delay time from an input timing of a line synchronization signal to a second start timing at which light emission is started, and a second pulse width equal to the first pulse width from the second start timing to a second end timing at which the light emission is ended by an input timing of a line synchronization signal next to the line synchronization signal; Starting and stopping the emission of each light emitting element row according to the settings; 1. An image forming apparatus comprising:

2. The set values ​​for each light emitting element column satisfy a0≠a1, b0=b1, and a0+b0≠a1+b1, where a first delay time is a0, a first pulse width is b0, a second delay time is a1, and a second pulse width is b1.

2. The image forming apparatus according to claim 1,

3. the exposure device has a pulse signal generating unit that generates a pulse signal for causing the light emitting element row to emit light based on a delay time from an input timing of a line synchronization signal to a start timing for starting light emission and a pulse width from the start timing to an end timing for ending the light emission, the pulse signal generating unit generates a first pulse signal for causing the first light-emitting element row to emit light based on a first delay time from the input timing of a line synchronization signal to a first start timing at which light emission starts and a first pulse width from the first start timing to a first end timing at which the light emission ends by the input timing of a line synchronization signal next to the line synchronization signal, and generates a second pulse signal for causing the second light-emitting element row to emit light based on a second delay time different from the first delay time from the input timing of the line synchronization signal to a second start timing at which light emission starts and a second pulse width equal to the first pulse width from the second start timing to a second end timing at which the light emission ends by the input timing of a line synchronization signal next to the line synchronization signal.

3. The image forming apparatus according to claim 1, wherein the first and second electrodes are arranged in a first direction.

4. The exposure apparatus includes: In a period of a line synchronization signal for multiple exposure of an exposure position exposed by the first light emitting element row by the second light emitting element row, a pulse signal for causing the second light emitting element row to emit light based on a first delay time set for the first light emitting element row in a period of the line synchronization signal immediately before the first delay time; setting a pulse signal for causing the first light emitting element row to emit light based on a delay time different from a first delay time set for the first light emitting element row in the period of the immediately preceding line synchronization signal; 4. The image forming apparatus according to claim 1, wherein the first and second electrodes are arranged in a first direction.

5. The exposure apparatus includes: a delay time generating unit that generates a different delay time for each period of the line synchronization signal; a delay time storage unit that stores a delay time set for the light emitting element row; setting a pulse signal for causing the second light emitting element row to emit light based on a first delay time set for the first light emitting element row in the period of the immediately preceding line synchronization signal, the first delay time being stored in the delay time storage unit; A pulse signal for causing the first light emitting element row to emit light is set based on a delay time different from a first delay time set for the first light emitting element row in the period of the immediately preceding line synchronization signal, the delay time being generated by the delay time generating unit.

5. The image forming apparatus according to claim 4.

6. The delay time generating unit generates a different delay time for each period of the line synchronization signal using a pseudorandom number.

6. The image forming apparatus according to claim 5,

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