Display device

Abstract

To provide a display device including horizontal line areas separated from each other.SOLUTION: A display device according to an exemplary embodiment comprises: a display panel having a display area including a plurality of pixels and a scan driver connected to the pixels and a non-display area disposed around the display area; and a first chip-on film attached to an end of the display panel. The non-display area includes a horizontal line area disposed between the first chip-on film and the display area in plan view, and the horizontal line area includes a first horizontal line area and a second horizontal line area spaced apart from each other in a first direction.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present specification relates to a display device.

[0002] The display panel of the display device may include display elements for displaying images, driving elements for driving the display elements, and lines for transmitting various signals to the display elements and the driving elements, etc. The display elements may be defined differently depending on the type of the display panel. For example, when the display panel is an organic light emitting display panel, the display elements may be organic light emitting elements including an anode, an emission layer, and a cathode. Summary of the Invention [Problem to be solved by the invention]

[0003] The present disclosure provides a display device including horizontal line regions separated from one another.

[0004] A display device according to one embodiment for solving the above problem includes a display panel including a display area including pixels and a scan driver connected to the pixels, and a non-display area arranged around the display area, and a first chip-on-film attached to an end of the display panel, wherein the non-display area includes a horizontal line area arranged between the first chip-on-film and the display area on a plane, and the horizontal line area includes a first horizontal line area and a second horizontal line area spaced apart from each other in a first direction.

[0005] The problems are not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description. Effect of the Invention

[0006] According to an embodiment of the present invention, a display device includes horizontal line regions separated from each other, thereby reducing a bezel area.

[0007] The effects of the present specification are not limited to those exemplified above, and other effects not mentioned will be clearly understood by a person having ordinary skill in the art to which the present specification pertains from the following description. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram illustrating a display device according to an embodiment. [Diagram 2] FIG. 2 is a cross-sectional view showing a stacked configuration of a display device according to an embodiment. [Diagram 3] FIG. 3 is a diagram showing a configuration of a scan driver in a display device according to an embodiment. [Figure 4] FIG. 4 is a diagram of a pixel circuit in a display device according to an embodiment. [Figure 5A] FIG. 5A is a diagram illustrating the operations of a scan signal and a light emission control signal during a refresh period and a hold period in the pixel circuit shown in FIG. [Figure 5B] FIG. 5B is a diagram illustrating the operations of the scan signal and the light emission control signal during the refresh period and the hold period in the pixel circuit shown in FIG. [Figure 5C] FIG. 5C is a diagram illustrating the operations of the scan signal and the light emission control signal during the refresh period and the hold period in the pixel circuit shown in FIG. [Figure 6] FIG. 6 is a plan view of a display device according to an embodiment. [Figure 7] FIG. 7 is a detailed view of the plan layout of the display device according to FIG. [Figure 8] FIG. 8 is a detailed plan view of the first display area according to FIG. [Figure 9] FIG. 9 is an enlarged plan view of region A in FIG. [Figure 10] FIG. 10 is a diagram showing a first horizontal line region and a second horizontal line region according to an embodiment. [Figure 11] FIG. 11 is a plan layout diagram of a display device according to another embodiment. [Figure 12] FIG. 12 is a plan layout diagram of a display device according to still another embodiment. [Figure 13] FIG. 13 is a plan view showing a display device according to still another embodiment. [Figure 14] FIG. 14 is a plan layout diagram of a display device according to still another embodiment. [Figure 15] FIG. 15 is a plan layout diagram of a display device according to still another embodiment. [Figure 16] FIG. 16 is a detailed plan view of a first display area according to another embodiment. Specific details for carrying out the invention

[0009] The advantages and features, as well as the methods for achieving them, will become apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the present specification is not limited to the following embodiments, and may be embodied in various different forms. The embodiments are provided merely to make the disclosure complete and to fully indicate the scope of the disclosure to those skilled in the art to which the present specification pertains, and the present specification is defined only by the scope of the claims. The same reference numerals refer to the same elements throughout the specification.

[0010] When an element is referred to as being "connected to" or "coupled to" another element, this includes being directly connected to or coupled to the other element, or having other elements between them. In contrast, when an element is referred to as being "directly connected to" or "directly coupled to" another element, this includes being connected to or coupled to the other element, or having other elements between them. "And / or" includes each and every combination of one or more of the listed items.

[0011] The terms used in the present specification are for the purpose of describing the embodiments and are not intended to limit the present specification. In the present specification, the singular form includes the plural form unless otherwise specified. As used in the present specification, the terms "comprises" and / or "comprising" refer to a referenced component, step, operation and / or element and do not exclude the presence or addition of one or more other components, steps, operations and / or elements.

[0012] Although terms such as first, second, etc. are used to describe various components, it is understood that these components are not limited by these terms, and these terms are merely used to distinguish one component from another.

[0013] Therefore, it is obvious that the first component mentioned below may be the second component within the technical concept. Unless otherwise defined, all terms (including technical and scientific terms) used in this specification may be used as commonly understood by those having ordinary knowledge in the technical field to which this specification belongs. Furthermore, terms defined in commonly used dictionaries are not interpreted ideally or excessively unless clearly defined otherwise.

[0014] FIG. 1 is a block diagram illustrating a display device according to an embodiment.

[0015] Referring to FIG. 1, the display device (10) includes a display panel (100) including a plurality of pixels (P), a controller (200), a scan driver (150) that supplies gate signals to each of the plurality of pixels (P), a data driver (400) that supplies data signals to each of the plurality of pixels (P), and a power supply unit (500) that supplies power required for driving each of the plurality of pixels (P).

[0016] The display panel (100) includes a display area (AA) in which the pixels (P) are located, and a non-display area (NA) surrounding the display area (AA) in which a scan driver (150) and a data driver (400) are located.

[0017] In the display panel 100, a plurality of scan lines (SCL) and a plurality of data lines (DL) cross each other, and each of a plurality of pixels (P) is connected to the scan lines (SCL) and the data lines (DL). Specifically, one pixel (P) is supplied with a gate signal from the scan driver 150 via the scan line (SCL), a data signal from the data driver 400 via the data line (DL), and a high potential driving voltage (EVDD) and a low potential driving voltage (EVSS) from the power supply 500.

[0018] Here, the scan line (SCL) supplies a scan signal (SC) and an emission control signal (EM), and the data line (DL) supplies a data voltage (Vdata). In addition, according to various embodiments, the scan line (SCL) may include a plurality of scan lines (SCL) that supply the scan signal (SC) and an emission control signal line (EML) that supplies the emission control signal (EM). In addition, the plurality of pixels (P) may further include a power supply line (VL) and may be supplied with a bias voltage (Vobs) and initialization voltages (Var, Vini).

[0019] Each pixel (P) includes a light-emitting element (OLED) and a pixel circuit that controls the driving of the light-emitting element (OLED), as shown in Fig. 2. Here, the light-emitting element (OLED) is composed of an anode electrode (ANO), a cathode electrode (CAT), and a light-emitting layer (EL) between the anode electrode (ANO) and the cathode electrode (CAT).

[0020] The pixel circuit includes a plurality of switching elements, a driving element, and a capacitor. Here, the switching elements and the driving element may be thin film transistors. In the pixel circuit, the driving element controls the amount of current supplied to the light emitting element (OLED) according to a data voltage to adjust the amount of light emitted by the light emitting element (OLED). In addition, the plurality of switching elements receive scan signals (SC) supplied via a plurality of scan lines (SCL) and light emission control signals (EM) supplied via a light emission control line (EML) to operate the pixel circuit.

[0021] The display panel 100 may be implemented as a non-transmissive display panel or a transmissive display panel. The transmissive display panel may be applied to a transparent display device in which an image is displayed on a screen and the actual object in the background can be seen. The display panel 100 may be manufactured as a flexible display panel. The flexible display panel may be implemented as an OLED panel using a plastic substrate.

[0022] Each of the pixels (P) is divided into a red pixel, a green pixel, and a blue pixel to realize a color. Each of the pixels (P) may further include a white pixel. Each of the pixels (P) includes a pixel circuit.

[0023] A touch sensor may be disposed on the display panel 100. Touch input may be sensed using a separate touch sensor or may be sensed through the pixel P. The touch sensor may be an on-cell type or add-on type that is disposed on the screen of the display panel, or may be an in-cell type touch sensor that is built into the display panel 100.

[0024] The controller 200 processes externally input image data (RGB) to match the size and resolution of the display panel 100 and supplies the processed data to the data driver 400. The controller 200 generates gate control signals (GCS) and data control signals (DCS) using externally input synchronous signals, for example, a dot clock signal (CLK), a data enable signal (DE), a horizontal synchronous signal (Hsync), and a vertical synchronous signal (Vsync). The controller 200 supplies the generated gate control signals (GCS) and data control signals (DCS) to the scan driver 150 and the data driver 400, respectively, to control the scan driver 150 and the data driver 400.

[0025] The controller (200) may be configured in combination with various processors, such as a microprocessor, a mobile processor, an application processor, etc., depending on the device in which it is implemented.

[0026] The host system may be any one of a television system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, a wearable device, and a vehicle system.

[0027] The controller (200) can multiply the input frame frequency by i to control the operation timing of the display panel driver at a frame frequency of input frame frequency Xi (i is a positive integer greater than 0) Hz. The input frame frequency is 60 Hz for the NTSC (National Television Standards Committee) system and 50 Hz for the PAL (Phase-Alternating Line) system.

[0028] The controller 200 generates signals so that the pixels P are driven at various refresh rates. That is, the controller 200 generates signals related to driving so that the pixels P are driven in a variable refresh rate (VRR) mode or switchably between a first refresh rate and a second refresh rate. For example, the controller 200 can drive the pixels P at various refresh rates by simply changing the speed of a clock signal, generating a synchronization signal so that a horizontal blank or a vertical blank occurs, or driving the scan driver 150 in a mask mode.

[0029] The controller 200 generates gate control signals (GCS) for controlling the operation timing of the scan driver 150 and data control signals (DCS) for controlling the operation timing of the data driver 400 based on timing signals (Vsync, Hsync, DE) received from the host system. The controller 200 controls the operation timing of the display panel drivers to synchronize the scan driver 150 and the data driver 400.

[0030] The voltage level of the gate control signal (GCS) output from the controller 200 may be converted into gate-on voltages (VGL, VEL) and gate-off voltages (VGH, VEH) by a level shifter (not shown) and supplied to the scan driver 150. The level shifter converts the low level voltage of the gate control signal (GCS) into a gate low voltage (VGL) and converts the high level voltage of the gate control signal (GCS) into a gate high voltage (VGH). The gate control signal (GCS) includes a start pulse and a shift clock.

[0031] The scan driver 150 supplies a scan signal SC to the scan line SCL in response to a gate control signal GCS supplied from the controller 200. The scan driver 150 may be disposed on one or both sides of the display panel 100 in a GIP (Gate In Panel) manner.

[0032] The scan driver 150 sequentially outputs gate signals to a plurality of scan lines (SCL) under the control of the controller 200. The scan driver 150 can sequentially supply the gate signals to the scan lines (SCL) by shifting the gate signals using a shift register.

[0033] In the organic light emitting display device, the gate signal may include a scan signal (SC) and a light emission control signal (EM). The scan signal (SC) may include a scan pulse that swings between a gate-on voltage (VGL) and a gate-off voltage (VGH). The light emission control signal (EM) may include a light emission control signal pulse that swings between a gate-on voltage (VEL) and a gate-off voltage (VEH).

[0034] The scan pulse is synchronized with the data voltage (Vdata) to select the pixels (P) of the line on which data is written. The light emission control signal (EM) defines the light emission time of the pixels (P).

[0035] The scan driver 150 may include an emission control signal driver (ECP) and at least one scan driver (SCP).

[0036] The light emission control signal driver (ECP) outputs a light emission control signal pulse in response to a start pulse and a shift clock from the controller (200), and shifts the light emission control signal pulse in sequence according to the shift clock.

[0037] At least one scan driver (SCP) outputs a scan pulse in response to a start pulse and a shift clock from the controller (200) and shifts the scan pulse in accordance with the shift clock timing.

[0038] The data driver 400 converts the image data (RGB) into a data voltage (Vdata) in response to a data control signal (DCS) provided from the controller 200, and provides the converted data voltage (Vdata) to the pixel (P) through the data line (DL).

[0039] Although the data driver 400 is shown arranged in one form on one side of the display panel 100 in FIG. 1, the number and arrangement of the data driver 400 are not limited thereto.

[0040] That is, the data driver 400 may be composed of a plurality of integrated circuits (ICs) and may be arranged on one side of the display panel 100 in a divided manner.

[0041] The power supply unit 500 generates a DC power supply required for driving the pixel array of the display panel 100 and the display panel driver using a DC-DC converter. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply unit 500 receives a DC input voltage applied from a host system (not shown) and generates DC voltages such as gate-on voltages (VGL, VEL), gate-off voltages (VGH, VEH), a high potential driving voltage (EVDD), and a low potential driving voltage (EVSS). The gate-on voltages (VGL, VEL) and gate-off voltages (VGH, VEH) are supplied to a level shifter (not shown) and the scan driver 150. The high potential driving voltage (EVDD) and the low potential driving voltage (EVSS) are commonly supplied to the pixels P.

[0042] FIG. 2 is a cross-sectional view showing a stacked configuration of a display device according to an embodiment.

[0043] 2 is a cross-sectional view including two switching thin film transistors (TFT1, TFT2) and one capacitor (CST). The two thin film transistors (TFT1, TFT2) include one of a switching thin film transistor or a driving transistor including a polycrystalline semiconductor material, and an oxide thin film transistor (TFT2) including an oxide semiconductor material. In this case, the thin film transistor including the polycrystalline semiconductor material is referred to as the polycrystalline thin film transistor (TFT1), and the thin film transistor including the oxide semiconductor material is referred to as the oxide thin film transistor (TFT2).

[0044] The polycrystalline thin film transistor (TFT1) shown in FIG. 2 is an emission switching thin film transistor connected to the light emitting element (OLED), and the oxide thin film transistor (TFT2) is one of the switching thin film transistors connected to the capacitor (CST).

[0045] A pixel (P) includes a light-emitting element (OLED) and a pixel driving circuit that applies a driving current to the light-emitting element (OLED). The pixel driving circuit is disposed on a substrate (111), and the light-emitting element (OLED) is disposed on the pixel driving circuit. In addition, an encapsulation layer (120) is disposed on the light-emitting element (OLED). The encapsulation layer (120) protects the light-emitting element (OLED).

[0046] The pixel driving circuit may refer to one pixel (P) array part including a driving thin film transistor, a switching thin film transistor, and a capacitor, and the light emitting element (OLED) may refer to an array part for emitting light including an anode electrode, a cathode electrode, and a light emitting layer disposed therebetween.

[0047] In one embodiment, the driving thin film transistor and at least one switching thin film transistor use an oxide semiconductor material as an active layer. A thin film transistor using an oxide semiconductor material as an active layer has a good effect of blocking leakage current and has a relatively low manufacturing cost compared to a thin film transistor using a polycrystalline semiconductor material as an active layer. Therefore, in order to reduce power consumption and manufacturing costs, a pixel driving circuit according to one embodiment includes a driving thin film transistor and at least one switching thin film transistor using an oxide semiconductor material.

[0048] All thin film transistors constituting the pixel driving circuit may be implemented using an oxide semiconductor material, or only some switching thin film transistors may be implemented using an oxide semiconductor material.

[0049] However, since it is difficult to ensure the reliability of thin film transistors using oxide semiconductor materials, and thin film transistors using polycrystalline semiconductor materials have a high operating speed and excellent reliability, one embodiment includes both switching thin film transistors using oxide semiconductor materials and switching thin film transistors using polycrystalline semiconductor materials.

[0050] The substrate 111 may be implemented as a multi-layer in which organic and inorganic layers are alternately stacked, for example, the substrate 111 may be implemented as a multi-layer in which organic layers such as polyimide and inorganic layers such as silicon oxide (SiO2) are alternately stacked.

[0051] A lower buffer layer (112a) is formed on the substrate (111). The lower buffer layer (112a) is intended to block moisture from penetrating from the outside, and can be made by laminating multiple layers of silicon oxide (SiO2) films. An auxiliary buffer layer (112b) can also be disposed on the lower buffer layer (112a) to protect the element from moisture.

[0052] A polycrystalline thin film transistor (TFT1) is formed on the substrate (111). The polycrystalline thin film transistor (TFT1) can use a polycrystalline semiconductor as an active layer. The polycrystalline thin film transistor (TFT1) includes a first active layer (ACT1) including a channel through which electrons or holes move, a first gate electrode (GE1), a first source electrode (SD1), and a first drain electrode (SD2).

[0053] The first active layer (ACT1) includes a first channel region, a first source region disposed on one side of the first channel region, and a first drain region disposed on the other side.

[0054] The first source region and the first drain region are regions in which an intrinsic polycrystalline semiconductor material is doped with a predetermined concentration of Group V or Group III impurity ions, such as phosphorus (P) or boron (B), to make it conductive. The first channel region is a region in which the polycrystalline semiconductor material maintains its intrinsic state and provides a path for the movement of electrons and holes.

[0055] Meanwhile, the polycrystalline thin film transistor (TFT1) includes a first gate electrode (GE1) overlapping a first channel region of the first active layer (ACT1). A first gate insulating layer (113) is disposed between the first gate electrode (GE1) and the first active layer (ACT1). The first gate insulating layer (113) may be a single layer or multiple layers of inorganic layers such as silicon oxide (SiO2) and silicon nitride (SiNx).

[0056] In one embodiment, the polycrystalline thin film transistor (TFT1) has a top gate structure in which the first gate electrode (GE1) is located on the top of the first active layer (ACT1). As a result, the first electrode (CST1) included in the capacitor (CST) and the light-shielding layer (LS) included in the oxide thin film transistor (TFT2) can be formed of the same material as the first gate electrode (GE1). The first gate electrode (GE1), the first electrode (CST1), and the light-shielding layer (LS) can be formed using a single mask process, thereby reducing the number of mask processes.

[0057] The first gate electrode (GE1) is made of a metal material, for example, the first gate electrode (GE1) may be a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, but is not limited thereto.

[0058] A first interlayer insulating layer 114 is disposed on the first gate electrode GE1. The first interlayer insulating layer 114 may be implemented by silicon oxide (SiO2), silicon nitride (SiNx), or the like.

[0059] The display panel (100) may further include an upper buffer layer (115), a second gate insulating layer (116), and a second interlayer insulating layer (117) arranged in sequence on the first interlayer insulating layer (114), and the polycrystalline thin film transistor (TFT1) is formed on the second interlayer insulating layer (117) and includes a first source electrode (SD1) and a first drain electrode (SD2) connected to the first source region and the first drain region, respectively.

[0060] The first source electrode (SD1) and the first drain electrode (SD2) may be a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, but is not limited thereto.

[0061] The upper buffer layer (115) separates the second active layer (ACT2) of the oxide thin film transistor (TFT2) made of an oxide semiconductor material from the first active layer (ACT1) made of a polycrystalline semiconductor material, and provides a base on which the second active layer (ACT2) can be formed.

[0062] The second gate insulating layer 116 covers the second active layer ACT2 of the oxide thin film transistor TFT2. The second gate insulating layer 116 is formed on the second active layer ACT2 made of an oxide semiconductor material, and is therefore made of an inorganic film. For example, the second gate insulating layer 116 may be silicon oxide (SiO2), silicon nitride (SiNx), etc.

[0063] The second gate electrode (GE2) is made of a metal material, for example, the second gate electrode (GE2) may be a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, but is not limited thereto.

[0064] Meanwhile, the oxide thin film transistor (TFT2) includes a second active layer (ACT2) formed on the upper buffer layer (115) and implemented with an oxide semiconductor material, a second gate electrode (GE2) disposed on the second gate insulating layer (116), a second source electrode (SD3) disposed on the second interlayer insulating layer (117), and a second drain electrode (SD4).

[0065] The second active layer (ACT2) is implemented with an oxide semiconductor material and includes an intrinsic second channel region that is not doped with impurities, and second source and drain regions that are doped with impurities to make them conductive.

[0066] The oxide thin film transistor (TFT2) further includes a light-shielding layer (LS) located under the upper buffer layer (115) and overlapping the second active layer (ACT2). The light-shielding layer (LS) can block light incident on the active layer (401) to ensure the reliability of the oxide thin film transistor (TFT2). The light-shielding layer (LS) may be formed of the same material as the first gate electrode (GE1) and formed on the upper surface of the first gate insulating layer (113). The light-shielding layer (LS) may be electrically connected to the second gate electrode (GE2) to form a dual gate.

[0067] The second source electrode (SD3) and the second drain electrode (SD4) are simultaneously formed of the same material on the second interlayer insulating layer (117) together with the first source electrode (SD1) and the first drain electrode (SD2), thereby reducing the number of mask processes.

[0068] Meanwhile, a capacitor (CST) may be implemented by disposing a second electrode (CST2) to overlap the first electrode (CST1) on the first interlayer insulating layer 114. The second electrode (CST2) may be a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0069] The capacitor (CST) stores the data voltage applied through the data line (DL) for a certain period of time and provides it to the light emitting element (OLED). The capacitor (CST) includes two electrodes corresponding to each other and a dielectric disposed between them. A first interlayer insulating layer (114) is disposed between the first electrode (CST1) and the second electrode (CST2).

[0070] The first electrode (CST1) or the second electrode (CST2) of the capacitor (CST) may be electrically connected to the second source electrode (SD3) or the second drain electrode (SD4) of the oxide thin film transistor (TFT2). However, the present invention is not limited thereto, and the connection relationship of the capacitor (CST) may be changed according to the pixel driving circuit.

[0071] Meanwhile, a first planarization layer 118 and a second planarization layer 119 are sequentially disposed on the pixel driving circuit to planarize the upper end of the pixel driving circuit. The first planarization layer 118 and the second planarization layer 119 may be an organic film such as polyimide or acrylic resin.

[0072] In addition, a light emitting device (OLED) is formed on the second planarization layer (119).

[0073] The light emitting element (OLED) includes an anode electrode (ANO), a cathode electrode (CAT), and an emitting layer (EL) disposed between the anode electrode (ANO) and the cathode electrode (CAT). When implemented as a pixel driving circuit that uses a common low potential voltage connected to the cathode electrode (CAT), the anode electrode (ANO) is disposed as a separate electrode for each sub-pixel. When implemented as a pixel driving circuit that uses a common high potential voltage, the cathode electrode (CAT) may be disposed as a separate electrode for each sub-pixel.

[0074] The light emitting element (OLED) is electrically connected to the driving element through the intermediate electrode (CNE) disposed on the first planarization layer 118. Specifically, the anode electrode (ANO) of the light emitting element (OLED) and the first source electrode (SD1) of the polycrystalline thin film transistor (TFT1) constituting the pixel driving circuit are connected to each other by the intermediate electrode (CNE).

[0075] The anode electrode (ANO) is connected to the intermediate electrode (CNE) exposed through a contact hole penetrating the second planarization layer (119), and the intermediate electrode (CNE) is connected to the first source electrode (SD1) exposed through a contact hole penetrating the first planarization layer (118).

[0076] The intermediate electrode (CNE) serves as a medium connecting the first source electrode (SD1) and the anode electrode (ANO) and may be made of a conductive material such as copper (Cu), silver (Ag), molybdenum (Mo), or titanium (Ti).

[0077] The anode electrode (ANO) may be formed in a multi-layer structure including a transparent conductive film and an opaque conductive film with high reflectivity. The transparent conductive film may be made of a material with a relatively large work function value such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO), and the opaque conductive film may be formed in a single layer or multi-layer structure including aluminum (Al), silver (Ag), copper (Cu), lead (Pb), molybdenum (Mo), titanium (Ti), or an alloy thereof. For example, the anode electrode (ANO) may be formed in a structure in which a transparent conductive film, an opaque conductive film, and a transparent conductive film are laminated in order, or a transparent conductive film and an opaque conductive film are laminated in order.

[0078] The light-emitting layer (EL) is formed by laminating a hole-related layer, an organic light-emitting layer, and an electron-related layer on an anode electrode (ANO) in this order or in the reverse order.

[0079] The bank layer (BNK) may be a pixel definition film that exposes the anode electrode (ANO) of each pixel (P). The bank layer (BNK) may be made of an opaque material (e.g., black) to prevent optical interference between adjacent pixels (P). In this case, the bank layer (BNK) includes a light-shielding material made of at least one of a color pigment, organic black, and carbon. A spacer (700) may be further disposed on the bank layer (BNK).

[0080] The cathode electrode (CAT) faces the anode electrode (ANO) across the light emitting layer (EL) and is formed on the top and side surfaces of the light emitting layer (EL). The cathode electrode (CAT) may be integrally formed over the entire display area (AA). When the cathode electrode (CAT) is applied to a full-surface emitting organic light emitting display device, it may be made of a transparent conductive film such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0081] A sealing layer (120) that inhibits moisture penetration may further be disposed on the cathode electrode (CAT).

[0082] The encapsulation layer (120) can prevent external moisture and oxygen from penetrating into the light emitting element (EL), which is vulnerable to external moisture and oxygen. To this end, the encapsulation layer (120) can include at least one inorganic encapsulation layer and at least one organic encapsulation layer, but is not limited thereto. In the present invention, a structure of the encapsulation layer (120) in which a first encapsulation layer (121), a second encapsulation layer (122), and a third encapsulation layer (123) are stacked in this order will be described as an example.

[0083] The first encapsulation layer (121) is formed on the substrate (111) on which the cathode electrode (CAT) is formed. The third encapsulation layer (123) may be formed on the substrate (111) on which the second encapsulation layer (122) is formed, and may be formed to surround the upper surface, lower surface and side surface of the second encapsulation layer (122) together with the first encapsulation layer (121). The first encapsulation layer (121) and the third encapsulation layer (123) may minimize or prevent external moisture and oxygen from penetrating into the light emitting element (EL). The first encapsulation layer (121) and the third encapsulation layer (123) may be formed of an inorganic insulating material that can be deposited at a low temperature, such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). Since the first encapsulating layer (121) and the third encapsulating layer (123) are deposited in a low temperature atmosphere, damage to the light emitting element (EL), which is vulnerable to a high temperature atmosphere, can be prevented during the deposition process of the first encapsulating layer (121) and the third encapsulating layer (123).

[0084] The second encapsulation layer 122 acts as a buffer to relieve stress between layers due to warping of the display device 10, and can flatten steps between layers. The second encapsulation layer 122 may be formed on the substrate 111 on which the first encapsulation layer 121 is formed, from a non-photosensitive organic insulating material such as acryl resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, polyethylene, or silicon oxycarbon (SiOC), or a photosensitive organic insulating material such as photoacrylic, but is not limited thereto. When the second encapsulation layer 122 is formed by the inkjet method, a dam (DAM) may be disposed to prevent the second encapsulation layer 122 in a liquid form from diffusing to the edge of the substrate 111. The dam (DAM) is disposed closer to the edge of the substrate 111 than the second encapsulation layer 122. Such a dam (DAM) can prevent the second sealing layer (122) from diffusing into a pad region where the conductive pads arranged at the outermost periphery of the substrate (111) are arranged.

[0085] The dam (DAM) is designed to prevent the diffusion of the second encapsulation layer (122), but if the second encapsulation layer (122) is formed to exceed the height of the dam (DAM) during the process, the second encapsulation layer (122), which is an organic layer, may be exposed to the outside, and moisture may easily penetrate into the light emitting device. Therefore, in order to prevent this, at least 10 or more dams (DAM) may be formed in overlapping fashion.

[0086] A dam (DAM) may be disposed on the second interlayer insulating layer (117) in the non-display area (NA).

[0087] Also, the dam (DAM) may be formed simultaneously with the first planarization layer 118 and the second planarization layer 119. The dam (DAM) may be formed by stacking a double structure in which a lower layer of the dam (DAM) is formed when the first planarization layer 118 is formed, and an upper layer of the dam (DAM) is formed when the second planarization layer 119 is formed.

[0088] Therefore, the dam (DAM) may be made of the same material as the first planarization layer (118) and the second planarization layer (119), but is not limited to this.

[0089] The dam (DAM) may be formed to overlap with the low potential driving power line (VSS). For example, the low potential driving power line (VSS) may be formed in a lower layer of the area where the dam (DAM) is located in the non-display area (NA).

[0090] The low potential driving power line (VSS) may be located outside the scan driver 150. Also, the low potential driving power line (VSS) may be connected to the cathode electrode (CAT) to apply a common voltage.

[0091] On the other hand, the scan driver 150 may be disposed above the display area AA as shown in FIG.

[0092] The low potential driving power line (VSS) is disposed outside the scan driver 150. The low potential driving power line (VSS) is disposed outside the scan driver 150 and surrounds the display area (AA). For example, the low potential driving power line (VSS) may be made of the same material as the first gate electrode (GE1), but is not limited thereto, and may be made of the same material as the second electrode (CST2) or the first source and drain electrodes (SD1, SD2), but is not limited thereto.

[0093] In addition, a low potential driving power line (VSS) may be electrically connected to the cathode electrode (CAT). The low potential driving power line (VSS) may supply a low potential driving voltage (EVSS) to a plurality of pixels (P) of the display area (AA).

[0094] A touch layer may be disposed on the encapsulation layer 120. In the touch layer, a touch buffer film 151 may be disposed between a touch sensor metal including touch electrode connection lines 152, 154 and touch electrodes 155, 156, and a cathode electrode CAT of the light emitting element EL.

[0095] The touch buffer film (151) can prevent chemicals (such as a developing solution or an etching solution) used in the manufacturing process of the touch sensor metal disposed on the touch buffer film (151) or moisture from the outside from penetrating into the light emitting layer (EL) containing organic matter. As a result, the touch buffer film (151) can prevent damage to the light emitting layer (EL), which is vulnerable to chemicals or moisture.

[0096] The touch buffer film (151) can be formed at a certain temperature (e.g., 100° C. or less) in order to prevent damage to the light emitting layer (EL) including organic material vulnerable to high temperatures, and is formed of an organic insulating material having a low dielectric constant of 1 to 3. For example, the touch buffer film (151) may be formed of an acrylic-based, epoxy-based, or siloxane-based material. The touch buffer film (151) made of an organic insulating material and having planarization performance can prevent damage to the encapsulation layer (120) due to warping of the OLED display device and tearing of the touch sensor metal formed on the touch buffer film (151).

[0097] According to a touch sensor structure based on mutual capacitance, touch electrodes (155, 156) are disposed on a touch buffer film (151), and the touch electrodes (155, 156) may be disposed to cross each other.

[0098] The touch electrode connecting lines 152 and 154 may electrically connect the touch electrodes 155 and 156. The touch electrode connecting lines 152 and 154 and the touch electrodes 155 and 156 may be located in different layers with a touch insulating film 153 interposed therebetween.

[0099] The touch electrode connecting lines 152 and 154 are arranged to overlap the bank layer 165, thereby preventing a decrease in the aperture ratio.

[0100] Meanwhile, the touch electrodes 155 and 156 may be electrically connected to a touch driving circuit (not shown) through a touch pad (PAD) such that a portion of the touch electrode connection line 152 passes through the upper and side surfaces of the encapsulation layer 120 and the upper and side surfaces of the dam (DAM).

[0101] A part of the touch electrode connecting line 152 may receive a touch driving signal from the touch driving circuit and transmit it to the touch electrodes 155 and 156, and may also transmit a touch sensing signal at the touch electrodes 155 and 156 to the touch driving circuit.

[0102] A touch protection film 157 may be disposed on the touch electrodes 155 and 156. In the drawings, the touch protection film 157 is illustrated as being disposed only on the touch electrodes 155 and 156, but is not limited thereto, and the touch protection film 157 may extend to the front or rear of the dam and be disposed on the touch electrode connecting line 152.

[0103] In addition, a color filter (not shown) may be further disposed on the encapsulation layer (120), and the color filter may be located on the touch layer or between the encapsulation layer (120) and the touch layer.

[0104] FIG. 3 is a diagram showing a configuration of a scan driver in a display device according to an embodiment.

[0105] The gate driving circuit 150 according to an embodiment may be implemented (or built-in) in the display area AA of the substrate 111. The gate driving circuit 150 may generate a scan signal based on a gate control signal or an emission control signal provided via a pad unit and a scan control line GCL, and sequentially provide the scan signal to a plurality of scan lines SCL or emission control lines EML.

[0106] The scan control lines (GCL) may include a start signal line, a plurality of shift clock lines, at least one gate driving voltage line, and at least one gate common voltage line. The scan control lines (GCL) may be arranged on the display area (AA) of the substrate (111) so as to extend long along the second direction (DR2) and have a predetermined interval along the first direction (DR1). For example, the scan control lines (GCL) may be arranged between at least one pixel (P) along the first direction (DR1).

[0107] As shown in FIG. 3, the gate driving circuit 150 according to an embodiment may be realized as a shift register including a first stage circuit portion 150a and a second stage circuit portion 150b. The first stage circuit portion 150a and the second stage circuit portion 150b may be arranged to be spaced apart from each other in a first direction DR1. The first stage circuit portion 150a and the second stage circuit portion 150b may be separately arranged in each horizontal line on a first surface of the substrate 111 along the first direction DR1, and may be connected to each other in a subordinate manner along a second direction DR2. Each of the first stage circuit portion 150a and the second stage circuit portion 150b may generate a scan signal according to a predetermined procedure in response to a gate control signal provided through the first pad portion 110 and the scan control line GCL, and provide the scan signal to a corresponding scan line SCL. The first stage circuitry 150a and the second stage circuitry 150b will be described in detail later.

[0108] FIG. 4 is a diagram of a pixel circuit in a display device according to an embodiment.

[0109] 4 shows a pixel circuit as an example for the purpose of explanation, and is not limited to a specific structure as long as the light emission signal (EM(n)) is applied to control the emission of the light emitting element (EL). For example, the pixel circuit may include an additional scan signal and a switching thin film transistor connected thereto, and a switching thin film transistor to which an additional initialization voltage is applied, and the connection relationship of the switching elements and the connection position of the capacitors may be variously arranged. For the convenience of explanation, a display device having the pixel circuit structure of FIG. 4 will be described below.

[0110] Referring to FIG. 4, each of the plurality of pixels (P) may include a pixel circuit having a driving transistor (DT) and a light emitting element (EL) coupled to the pixel circuit.

[0111] The pixel circuit can drive the light-emitting element (EL) by controlling a drive current flowing through the light-emitting element (EL). The pixel circuit may include a drive transistor (DT), first to seventh transistors (T1 to T7), and a capacitor (Cst). Each of the transistors (DT, T1 to T7) may include a first electrode, a second electrode, and a gate electrode. One of the first electrode and the second electrode may be a source electrode, and the other of the first electrode and the second electrode may be a drain electrode.

[0112] Each of the transistors (DT, T1 to T7) may be a P-type thin film transistor or an N-type thin film transistor. In the embodiment of FIG. 3, the first transistor (T1) and the seventh transistor (T7) are N-type thin film transistors, and the remaining transistors (DT, T2 to T6) are P-type thin film transistors. However, this is not limited thereto, and depending on the embodiment, all or some of the transistors (DT, T1 to T7) may be P-type thin film transistors or N-type thin film transistors. In addition, the N-type thin film transistors may be oxide thin film transistors, and the P-type thin film transistors may be polycrystalline silicon thin film transistors.

[0113] In the following description, the first transistor T1 and the seventh transistor T7 are N-type thin film transistors, and the remaining transistors DT, T2 to T6 are P-type thin film transistors. Therefore, the first transistor T1 and the seventh transistor T7 are turned on when a high voltage is applied, and the remaining transistors DT, T2 to T6 are turned on when a low voltage is applied.

[0114] According to one example, the first transistor (T1) constituting the pixel circuit can function as a compensation transistor, the second transistor (T2) as a data supply transistor, the third and fourth transistors (T3, T4) as light emission control transistors, the fifth transistor (T5) as a bias transistor, and the sixth and seventh transistors (T6, T7) as initialization transistors.

[0115] The light emitting element (EL) may include an anode electrode and a cathode electrode, the anode electrode of the light emitting element (EL) may be connected to the fifth node (N5), and the cathode electrode of the light emitting element (EL) may be connected to the low potential driving voltage (EVSS).

[0116] The driving transistor (DT) may include a first electrode connected to the second node (N2), a second electrode connected to the third node (N3), and a gate electrode connected to the first node (N1). The driving transistor (DT) may provide a driving current (Id) to the light emitting element (EL) based on a voltage of the first node (N1) (or a data voltage stored in a capacitor (Cst) described below).

[0117] The first transistor (T1) may include a first electrode connected to the first node (N1), a second electrode connected to the third node (N3), and a gate electrode receiving a first scan signal (SC1(n)). The first transistor (T1) is turned on in response to the first scan signal (SC1(n)) and is diode-coupled between the data voltage first node (N1) and the third node (N3) to sample the threshold voltage (Vth) of the driving transistor (DT). Such a first transistor (T1) may be a compensation transistor.

[0118] The capacitor Cst may be connected or formed between the first node N1 and the fourth node N4. The capacitor Cst may store or hold the high potential driving voltage EVDD provided.

[0119] The second transistor (T2) may include a first electrode connected to the data line (DL) (or receiving a data voltage (Vdata)), a second electrode connected to the second node (N2), and a gate electrode receiving a second scan signal (SC2(n)). The second transistor (T2) may be turned on in response to the second scan signal (SC2(n)) and transfer the data voltage (Vdata) to the second node (N2). Such a second transistor (T2) may be a data supply transistor.

[0120] The third transistor (T3) and the fourth transistor (T4) (or the first and second light emitting control transistors) are connected between the high potential driving voltage (EVDD) and the light emitting element (EL) and can form a current transfer path through which the driving current (Id) generated by the driving transistor (DT) transfers.

[0121] The third transistor (T3) may include a first electrode coupled to the fourth node (N4) to receive the high potential driving voltage (EVDD), a second electrode coupled to the second node (N2), and a gate electrode receiving the light emission control signal (EM(n)).

[0122] The fourth transistor (T4) may include a first electrode coupled to the third node (N3), a second electrode coupled to the fifth node (N5) (or an anode electrode of the light emitting element (EL)), and a gate electrode receiving the light emission control signal (EM(n)).

[0123] The third and fourth transistors (T3, T4) are turned on in response to the light emitting control signal (EM(n)), in which case the driving current (Id) is provided to the light emitting element (EL), and the light emitting element (EL) can emit light having a brightness corresponding to the driving current (Id).

[0124] The fifth transistor T5 may include a first electrode for receiving a bias voltage Vobs, a second electrode connected to the second node N2, and a gate electrode for receiving a third scan signal SC3(n). Such a fifth transistor T5 may be a bias transistor.

[0125] The sixth transistor T6 may include a first electrode receiving the first initialization voltage Var, a second electrode coupled to the fifth node N5, and a gate electrode receiving the third scan signal SC3(n).

[0126] The sixth transistor (T6) is turned on in response to the third scan signal (SC3(n)) before the light emitting element (EL) emits light (or after the light emitting element (EL) emits light), and can initialize the anode electrode (or pixel electrode) of the light emitting element (EL) using the first initialization voltage (Var). The light emitting element (EL) may have a parasitic capacitor formed between the anode electrode and the cathode electrode. In addition, the parasitic capacitor is charged while the light emitting element (EL) emits light, and the anode electrode of the light emitting element (EL) can have a specific voltage. Therefore, the amount of charge stored in the light emitting element (EL) can be initialized by applying the first initialization voltage (Var) to the anode electrode of the light emitting element (EL) via the sixth transistor (T6).

[0127] In this specification, the gate electrodes of the fifth and sixth transistors (T5, T6) are configured to commonly receive the third scan signal (SC3(n)). However, this is not necessarily limited thereto, and the gate electrodes of the fifth and sixth transistors (T5, T6) may be configured to receive separate scan signals and be controlled independently.

[0128] The seventh transistor T7 may include a first electrode receiving the second initialization voltage Vini, a second electrode coupled to the first node N1, and a gate electrode receiving a fourth scan signal SC4(n)

[0129] The seventh transistor (T7) is turned on in response to the fourth scan signal (SC4(n)) and can initialize the gate electrode of the driving transistor (DT) using the second initialization voltage (Vini). Unnecessary charges may remain on the gate electrode of the driving transistor (DT) due to the high potential driving voltage (EVDD) stored in the capacitor (Cst). Therefore, the amount of remaining charges can be initialized by applying the second initialization voltage (Vini) to the gate electrode of the driving transistor (DT) via the seventh transistor (T7).

[0130] 5A to 5C are diagrams illustrating the operations of the scan signal and the emission control signal during the refresh period and the hold period in the pixel circuit shown in FIG.

[0131] The display device according to the embodiment can be operated as a VRR (variable refresh rate) mode display device. The VRR mode operates pixels by increasing the refresh rate at which the data voltage (Vdata) is updated when high-speed driving is required, and by decreasing the refresh rate when power consumption is reduced or low-speed driving is required.

[0132] Each of the plurality of pixels (P) may be driven by a combination of a refresh frame and a hold frame within one second. In this specification, one set is defined as a combination of a refresh period in which the data voltage (Vdata) is updated and a hold period in which the data voltage (Vdata) is not updated, repeated within one second. Also, one set period is a period in which a combination of a refresh period and a hold period is repeated.

[0133] If the refresh rate is 120Hz, the display can be driven only during the refresh period. In other words, the refresh period can be driven 120 times within one second. One refresh period is 1 / 120=8.33ms, and one set period is also 8.33ms.

[0134] When the refresh rate is 60 Hz, the refresh period and the hold period may be alternated. That is, the refresh period and the hold period may be alternated 60 times each within one second. The duration of each of one refresh period and one hold period is 0.5 / 60=8.33 ms, and one set period is 16.66 ms.

[0135] When the refresh rate is 1 Hz, one frame may be driven with one refresh period and 119 hold periods after the refresh period. When the refresh rate is 1 Hz, one frame may be driven with multiple refresh periods and multiple hold periods. In this case, the duration of each of one refresh period and one hold period is 1 / 120=8.33 ms, and one set is 1 s.

[0136] During the refresh period, a new data voltage (Vdata) is charged and applied to the driving transistor (DT), while during the hold period, the data voltage (Vdata) of the previous frame is maintained and used as is. Meanwhile, the hold period is also called a skip period because the process of applying a new data voltage (Vdata) to the driving transistor (DT) is omitted.

[0137] Each of the pixels (P) can initialize the voltage that is charged or remains in the pixel circuit during the refresh period. Specifically, each of the pixels (P) can remove the influence of the data voltage (Vdata) and the high potential driving voltage (EVDD) stored in the previous frame during the refresh period. Therefore, each of the pixels (P) can display an image corresponding to the new data voltage (Vdata) during the hold period.

[0138] Each of the plurality of pixels (P) may provide a driving current corresponding to a data voltage (Vdata) to a light emitting element (EL) during a hold period to display an image and maintain a turn-on state of the light emitting element (EL).

[0139] First, the driving of the pixel circuit and the light emitting element during the refresh period of Fig. 5A will be described. The refresh period can include at least one bias section (Tobs1, Tobs2), an initialization section (Ti), a sampling section (Ts), and a light emitting section (Te), but this is merely an example and is not necessarily limited to such a procedure.

[0140] Referring to FIG. 5A, the pixel circuit may operate including at least one bias period (Tobs1, Tobs2) during a refresh period.

[0141] At least one bias section (Tobs1, Tobs2) is a section in which an on-bias stress operation (OBS) is performed in which a bias voltage (Vobs) is applied, the emission control signal (EM(n)) is a high voltage, and the third and fourth transistors (T3, T4) are turned off. The first scan signal (SC1(n)) and the fourth scan signal (SC4(n)) are a low voltage, and the first transistor (T1) and the seventh transistor (T7) are turned off. The second scan signal (SC2) is a high voltage, and the second transistor (T2) is turned off.

[0142] The third scan signal SC3(n) is input at a low voltage, and the fifth and sixth transistors T5 and T6 are turned on. As the fifth transistor T5 is turned on, the bias voltage Vobs is applied to the first electrode of the driving transistor DT connected to the second node N2.

[0143] Here, the bias voltage (Vobs) is supplied to the third node (N3) which is the drain electrode of the driving transistor (DT), thereby reducing the charging time or charging delay of the voltage of the fifth node (N5) which is the anode electrode of the light emitting element (EL) during the light emitting period, and the driving transistor (DT) maintains a stronger saturation state.

[0144] For example, as the bias voltage (Vobs) increases, the voltage of the third node (N3), which is the drain electrode of the driving transistor (DT), increases, and the gate-source voltage or drain-source voltage of the driving transistor (DT) may decrease. Therefore, it is preferable that the bias voltage (Vobs) is at least greater than the data voltage (Vdata).

[0145] At this time, the magnitude of the drain-source current (Id) passing through the drive transistor (DT) is reduced, and the stress of the drive transistor (DT) is reduced under positive bias stress conditions, thereby eliminating the charging delay of the third node (N3) voltage. In other words, by performing an on-bias stress operation (OBS) before sampling the threshold voltage (Vth) of the drive transistor (DT), the hysteresis of the drive transistor (DT) can be alleviated.

[0146] Therefore, an on-bias stress operation (OBS) in at least one bias section (Tobs1, Tobs2) can be defined as an operation in which a bias voltage suitable for a non-light emitting period is applied to the direct drive transistor (DT).

[0147] In addition, in at least one bias section (Tobs1, Tobs2), the sixth transistor (T6) is turned on, so that the anode electrode (or pixel electrode) of the light emitting element (EL) connected to the fifth node (N5) is initialized to the first initialization voltage (Var).

[0148] However, the gate electrodes of the fifth and sixth transistors (T5, T6) may be configured to receive separate scan signals and be controlled independently of each other, i.e., it is not required to simultaneously apply a bias voltage to the first electrode of the driving transistor (DT) and the anode electrode of the light emitting element (EL) during the bias period.

[0149] 5A, the pixel circuit may operate during a refresh period including an initialization period (Ti), in which the voltage of the gate electrode of the driving transistor (DT) is initialized.

[0150] The first scan signal (SC1(n)) through the fourth scan signal (SC4(n)) and the emission control signal (EM(n)) are at high voltages, and the first transistor (T1) and the seventh transistor (T7) are turned on. The second through sixth transistors (T2, T3, T4, T5, T6) are turned off. As the first and seventh transistors (T1, T7) are turned on, the gate electrode and the second electrode of the driving transistor (DT) connected to the first node (N1) are initialized to the second initialization voltage (Vini).

[0151] 5A, the pixel circuit may operate during a refresh period including a sampling period (Ts), in which the threshold voltage (Vth) of the drive transistor (DT) is sampled.

[0152] The first scan signal (SC1(n)), the third scan signal (SC3(n)), and the emission control signal (EM(n)) are high voltages, and the second scan signal (SC2(n)) and the fourth scan signal (SC4(n)) are low voltages. As a result, the third to seventh transistors (T3, T4, T5, T6, T7) are turned off, the first transistor (T1) maintains an on state, and the second transistor (T2) is turned on. That is, the second transistor (T2) is turned on, the data voltage (Vatat) is applied to the driving transistor (DT), and the first transistor (T1) is diode-coupled between the first node (N1) and the third node (N3), thereby sampling the threshold voltage (Vth) of the driving transistor (DT).

[0153] 5A, the pixel circuit may operate during a refresh period including an emission period (Te), which is a period in which the sampled threshold voltage (Vth) is offset and the light emitting element (EL) is caused to emit light with a driving current corresponding to the sampled data voltage.

[0154] The light emission control signal (EM(n)) is at a low voltage, and the third and fourth transistors (T3, T4) are turned on.

[0155] As the third transistor T3 is turned on, the high potential driving voltage EVDD connected to the fourth node N4 is applied to the first electrode of the driving transistor DT connected to the second node N2 via the third transistor T3. The driving current Id supplied to the light emitting element EL from the driving transistor DT via the fourth transistor T4 is independent of the threshold voltage Vth of the driving transistor DT and operates with the threshold voltage Vth of the driving transistor DT compensated.

[0156] Next, driving of the pixel circuit and the light emitting element during the hold period will be described with reference to FIG. 5B.

[0157] The hold period may include at least one bias period (Tobs3, Tobs4) and a light emission period (Te'). The operation of the pixel circuit, which is the same as the operation of the refresh period, will not be described.

[0158] As described above, the refresh period is different in that the new data voltage (Vdata) is charged and applied to the gate electrode of the driving transistor (DT), while the hold period maintains and uses the data voltage (Vdata) of the refresh period as it is. Therefore, unlike the refresh period, the hold period does not require the initialization period (Ti) and the sampling period (Ts).

[0159] In the operation of the hold period, the on-bias stress operation (OBS) may be sufficient only once. However, in this embodiment, for convenience of the driving circuit, the third scan signal (SC3(n)) in the hold period is driven in the same manner as the third scan signal (SC3(n)) in the refresh period, so that the on-bias stress operation (OBS) can be performed twice as in the refresh period.

[0160] The difference between the driving during the refresh period described with reference to FIG. 5A and the driving signals during the hold period in FIG. 5B is in the second and fourth scan signals (SC2(n), SC4(n)). Since the initialization period (Ti) and sampling period (Ts) are not required during the hold period, unlike the refresh period, the second scan signal (SC2(n)) is always at a high voltage and the fourth scan signal (SC4(n)) is always at a low voltage. In other words, the second and seventh transistors (T2, T7) are always turned off.

[0161] FIG. 6 is a plan view of a display device according to an embodiment.

[0162] 6, a display device (1) according to an embodiment may include a display area (AA) and a non-display area (NA) surrounding the display area (AA). The non-display area (NA) may completely surround the display area (AA) on a plane, but is not limited thereto.

[0163] A chip-on-film (COF) may be attached to an end of the non-display area (NA) (e.g., one end in the second direction (DR2)). Multiple chip-on-films (COF) may be provided. The multiple chip-on-films (COF) may be spaced apart in the first direction (DR1). Although only two chip-on-films (COF) are illustrated in FIG. 6, there may be three or more chip-on-films (COF), or there may be only one. A printed circuit board (PCB) may be connected to the other end of the chip-on-film (COF). The above-mentioned controller (200) and power supply unit (500) may be arranged on the printed circuit board (PCB).

[0164] The non-display area (NA) may include a horizontal line area (HA). The horizontal line area (HA) may be disposed between the display area (AA) and the chip on film (COF) and may extend along a first direction (DR1). The horizontal line area (HA) may be an area in which scan control lines (GCL) connected to each of the first stage circuit unit (150a) and the second stage circuit unit (150b) are disposed. That is, the scan control lines (GCL) arranged to extend along the first direction (DR1) in the horizontal line area (HA) may be branched and extended along the second direction (DR2) as shown in FIG. 3 to be connected to each of the first stage circuit unit (150a) and the second stage circuit unit (150b).

[0165] Meanwhile, in this specification, for convenience of explanation, the display area (AA) corresponding to each chip-on-film (COF) may be divided. For example, the display area (AA) may include a first display area (AA1) corresponding to a chip-on-film (COF) (hereinafter, first chip-on-film) located on the other side of the first direction (DR1), and a second display area (AA2) corresponding to a chip-on-film (COF) (hereinafter, second chip-on-film) located on one side of the first direction (DR1). The first display area (AA1) may correspond to the first chip-on-film (COF) in the second direction (DR2), and the second display area (AA2) may correspond to the second chip-on-film (COF) in the second direction (DR2).

[0166] FIG. 7 is a detailed view of the plan layout of the display device according to FIG.

[0167] 7, the horizontal line region (HA) may include a first horizontal line region (HA1) and a second horizontal line region (HA2). Also, each display region (AA1, AA2) may include a first stage region (P1) in which the first stage circuit unit (150a) is arranged, and a second stage region (P2) in which the second stage circuit unit (150b) is arranged. That is, the first display region (AA1) may include a first stage region (P1) in which the first stage circuit unit (150a) is arranged, and a second stage region (P2) in which the second stage circuit unit (150b) is arranged, and the second display region (AA2) may include a first stage region (P1) in which the first stage circuit unit (150a) is arranged, and a second stage region (P2) in which the second stage circuit unit (150b) is arranged.

[0168] A plurality of first horizontal line regions (HA1) and a plurality of second horizontal line regions (HA2) may be provided. For example, two each of the first horizontal line regions (HA1) and the second horizontal line regions (HA2) may be provided. The first and second horizontal line regions (HA1, HA2) may be arranged in the horizontal line regions (HA) corresponding to the first display region (AA1) in the second direction (DR2), and the first and second horizontal line regions (HA1, HA2) may be arranged in the horizontal line regions (HA) corresponding to the second display region (AA2) in the second direction (DR2). In the second direction (DR2), the first stage region (P1) of the first display area (AA1) may correspond to the first horizontal line region (HA1), the second stage region (P2) of the first display area (AA1) may correspond to the second horizontal line region (HA2), the first stage region (P1) of the second display area (AA2) may correspond to the first horizontal line region (HA1), and the second stage region (P2) of the second display area (AA2) may correspond to the second horizontal line region (HA2).

[0169] In the horizontal line region (HA), the second horizontal line region (HA2) may be disposed between adjacent first horizontal line regions (HA1), and the first horizontal line region (HA1) may be disposed between adjacent second horizontal line regions (HA2). That is, the first horizontal line regions (HA1) and the second horizontal line regions (HA2) may be disposed alternately with each other.

[0170] Furthermore, on the display area (AA), a second stage area (P2) may be arranged between adjacent first stage areas (P1), and a first stage area (P1) may be arranged between adjacent second stage areas (P2).

[0171] FIG. 8 is a detailed plan view of the first display area according to FIG.

[0172] Referring to FIG. 8, the first stage circuit section (150a) includes a plurality of stage circuit sections (1501a to 150ma), and each of the plurality of stage circuit sections (1501a to 150ma) may include a plurality of branch circuits (1511, 1513, 1514) and a first branch network (153).

[0173] Each of the plurality of branch circuits (1511, 1513, 1514) may be selectively connected to a scan control line (GCL) on the first stage region (P1) through the first branch network 153, and may be electrically connected to each other through the first branch network 153. Each of the plurality of branch circuits (1511, 1513, 1514) may generate a scan signal or an emission control signal according to a gate control signal supplied through the scan control line (GCL) and a voltage of the first branch network 153, and supply the generated signal to a corresponding scan line (SCL) or emission control signal line (EML).

[0174] The plurality of branch circuits (1511, 1513, 1514) may include a first branch circuit (1511) connected to a first scan line connected to a pixel (P), a third branch circuit (1513) connected to a third scan line, and a fourth branch circuit (1514) connected to a fourth scan line.

[0175] Each of the plurality of branch circuits (1511, 1513, 1514) may include at least one TFT (or a branch TFT) among the plurality of TFTs that configure one stage circuit portion (1501a to 150ma).

[0176] Each of the plurality of branch circuits (1511, 1513, 1514) may include sub-branch circuits spaced apart in a first direction (DR1) as shown in Fig. 8. Although Fig. 8 illustrates an example in which each of the plurality of branch circuits (1511, 1513, 1514) includes two sub-branch circuits, the present invention is not limited thereto, and the number of sub-branch circuits may be one or three or more. In the following description, for convenience of explanation, each of the plurality of branch circuits (1511, 1513, 1514) will be described as including two sub-branch circuits.

[0177] Any one of the sub-branch circuits of each of the plurality of branch circuits (1511, 1513, 1514) may include a pull-up TFT connected to each scan line, and another one of the sub-branch circuits of each of the plurality of branch circuits (1511, 1513, 1514) may include a pull-down TFT connected to a scan line (SCL).

[0178] The first branch network 153 may be disposed on each horizontal line of the substrate 111 and electrically connect the plurality of branch circuits 1511, 1513, 1514 to each other. The first branch network 153 according to an embodiment may include a plurality of control node lines and a plurality of network lines.

[0179] A plurality of control node lines may be disposed on each horizontal line of the substrate (111) and selectively coupled to a plurality of branch circuits (1511, 1513, 1514) on one horizontal line.

[0180] The plurality of network lines may be selectively coupled to a scan control line (GCL) disposed on the substrate (111) and selectively coupled to a plurality of branch circuits (1511, 1513, 1514).

[0181] The second stage circuit section (150b) includes a plurality of stage circuit sections (1501b to 150mb), and each of the plurality of stage circuit sections (1501b to 150mb) may include a plurality of branch circuits (1512, 1515) and a second branch network (155).

[0182] Each of the plurality of branch circuits 1512, 1515 may be selectively connected to a scan control line (GCL) on the second stage region (P2) through a second branch network 155, and may be electrically connected to each other through the second branch network 155. Each of the plurality of branch circuits 1512, 1515 may generate a scan signal or an emission control signal according to a scan control signal supplied through the scan control line (GCL) and a voltage of the second branch network 155, and supply the generated signal to a corresponding scan line (SCL) or emission control signal line (EML).

[0183] The plurality of branch circuits (1512, 1515) may include a second branch circuit (1512) connected to a second scan line connected to the pixel (P) and a fifth branch circuit (1515) connected to a light emission control signal line.

[0184] Each of the plurality of branch circuits (1512, 1515) may include at least one TFT (or a branch TFT) among the plurality of TFTs that configure one stage circuit portion (1501b to 150mb).

[0185] Each of the plurality of branch circuits (1512, 1515) may include sub-branch circuits spaced apart in a first direction (DR1) as shown in Fig. 8. Although Fig. 8 illustrates an example in which each of the plurality of branch circuits (1512, 1515) includes two sub-branch circuits, the present invention is not limited thereto, and the number of sub-branch circuits may be one or three or more. In the following description, for convenience of explanation, each of the plurality of branch circuits (1512, 1515) will be described as including two sub-branch circuits.

[0186] Any one of the sub-branch circuits of each of the plurality of branch circuits (1512, 1515) may include a pull-up TFT coupled to each scan line, and the other one of the sub-branch circuits of each of the plurality of branch circuits (1512, 1515) may include a pull-down TFT coupled to a scan line (SCL).

[0187] The second branch network 155 may be disposed on each horizontal line of the substrate 111 and electrically connect the branch circuits 1512, 1515 to each other. The second branch network 155 according to an embodiment may include a plurality of control node lines and a plurality of network lines.

[0188] A plurality of control node lines may be disposed on each horizontal line of the substrate (111) and selectively coupled to a plurality of branch circuits (1512, 1515) on one horizontal line.

[0189] The plurality of network lines may be selectively coupled to a scan control line (GCL) disposed on the substrate (111) and selectively coupled to a plurality of branch circuits (1512, 1515).

[0190] 8, the first display area (AA1) may include a driving voltage line area (PWA) and a pixel area (PXA). The second display area (AA2) includes substantially the same components as the first display area (AA1), and therefore a detailed description thereof will be omitted.

[0191] In the driving voltage line area (PWA), a first driving voltage line for supplying a high potential driving voltage (EVDD) supplied from a power supply unit (500) to each pixel (P) and a second driving voltage line for supplying a low potential driving voltage (EVSS) supplied from the power supply unit (500) to each pixel (P) may be arranged. In the pixel area (PXA), a plurality of pixels (P) may be arranged. The plurality of pixels (P) may be arranged in a line along the second direction (DR2), and one pixel area (PXA) may have one row of pixels (P), but is not limited thereto, and the plurality of pixels (P) may be arranged in a staggered arrangement or random arrangement in the pixel area (PXA), and one pixel area (PXA) may have multiple rows of pixels (P).

[0192] As shown in FIG. 8, in the first stage region (P1), the driving voltage line region (PWA), the pixel region (PXA), and each sub-branch circuit of the branch circuits (1511, 1513, 1514) may be alternately arranged along the first direction (DR1). For example, the driving voltage line region (PWA) may be arranged between adjacent pixel regions (PXA), and each sub-branch circuit of the branch circuits (1511, 1513, 1514) may be arranged between adjacent pixel regions (PXA). In the first stage region (P1) shown in FIG. 8, the arrangement of the driving voltage line region (PWA), the pixel region (PXA), and each sub-branch circuit of the branch circuits (1511, 1513, 1514) may be variously changed without being limited thereto. In the second stage region (P2), the driving voltage line region (PWA), the pixel region (PXA), and each sub-branch circuit of the branch circuit (1512, 1515) may be alternately arranged along the first direction (DR1). For example, the driving voltage line region (PWA) may be arranged between adjacent pixel regions (PXA), and each sub-branch circuit of the branch circuit (1512, 1515) may be arranged between adjacent pixel regions (PXA). In the first stage region (P1) shown in FIG. 8, the arrangement of the driving voltage line region (PWA), the pixel region (PXA), and each sub-branch circuit of the branch circuit (1512, 1515) may be variously changed without being limited thereto.

[0193] FIG. 9 is an enlarged plan view of region A in FIG.

[0194] 9, a first driving voltage line (VDDL) and a second driving voltage line (VSSL) may be arranged in the driving voltage line area (PWA). The first driving voltage line (VDDL) and the second driving voltage line (VSSL) may supply a high potential driving voltage (EVDD) and a low potential driving voltage (EVSS) from a power supply unit (500) to each pixel (P). The first driving voltage line (VDDL) and the second driving voltage line (VSSL) may extend from the power supply unit (500) and extend along a first direction (DR1) in the horizontal line area (HA). As described later in FIG. 10, the horizontal line area (HA) between the chip on film (COF) and the display area (AA) is divided into horizontal line areas (HA1, HA2) spaced apart from each other, and the horizontal lines (HL_SC1, HL_SC2, HL_SC3, HL_SC4, HL_EM) are arranged in each horizontal line area (HA1, HA2) according to the number of shift clock lines included in each horizontal line (HL_SC1, HL_SC2, HL_SC3, HL_SC4, HL_EM), and the horizontal lines (HL_SC1, HL_SC2, HL_SC3, HL_SC4, HL_EM) arranged in each other line area (HA1, HA2) may be separated from each other in the first direction (DR1). Meanwhile, the first driving voltage line (VDDL) and the second driving voltage line (VSSL) arranged in the horizontal line area (HA) may extend integrally along the first direction (DR1) without being divided into the horizontal line areas (HA1, HA2). The first driving voltage line (VDDL) and the second driving voltage line (VSSL) arranged in the horizontal line region (HA) may be branched and connected to each pixel (P). The connection between the first driving voltage line (VDDL) and the second driving voltage line (VSSL) and the pixel (P) is well known in the art, so a detailed description will be omitted.

[0195] FIG. 10 is a diagram showing a first horizontal line region and a second horizontal line region according to an embodiment.

[0196] 10, the first horizontal line region (HA1) and the second horizontal line region (HA2) may each be provided with a scan control line (see GCL in FIG. 3). As described above in FIG. 3, the scan control line (see GCL in FIG. 3) may include a start signal line and a plurality of shift clock lines.

[0197] For example, a first horizontal line (HL_SC1) connected to a first branch circuit (1511), a third horizontal line (HL_SC3) connected to a third branch circuit (1513), and a fourth horizontal line (HL_SC4) connected to a fourth branch circuit (1514) may be arranged in the first horizontal line region (HA1), and a second horizontal line (HL_SC2) connected to a second branch circuit (1512), and a fifth horizontal line (HL_EM) connected to a fifth branch circuit (1515) may be arranged in the second horizontal line region (HA2). A first horizontal line (HL_SC1) connected to the first branch circuit (1511), a third horizontal line (HL_SC3) connected to the third branch circuit (1513), and a fourth horizontal line (HL_SC4) connected to the fourth branch circuit (1514) may be arranged along the second direction (DR2), and a second horizontal line (HL_SC2) connected to the second branch circuit (1512) and a fifth horizontal line (HL_EM) connected to the fifth branch circuit (1515) may be arranged along the second direction (DR2).

[0198] For example, the first horizontal line (HL_SC1) may include one first start signal line (VST1) and four shift clock lines (CLK1-1 to CLK1-4), the third horizontal line (HL_SC3) may include one third start signal line (VST3) and two shift clock lines (CLK3-1 to CLK3-2), the fourth horizontal line (HL_SC4) may include one fourth start signal line (VST4) and two shift clock lines (CLK4-1 to CLK4-2), the second horizontal line (HL_SC2) may include one second start signal line (VST2) and five shift clock lines (CLK2-1 to CLK2-5), and the fifth horizontal line (HL_EM) may include one fifth start signal line (EVST) and two shift clock lines (CLKE-1 to CLKE-2).

[0199] That is, horizontal lines (HL_SC1, HL_SC3, HL_SC4) are arranged in a first horizontal line region (HA1), and horizontal lines (HL_SC2, HL_EM) are arranged in a second horizontal line region (HA2), which may be designed according to the number of shift clock lines each horizontal line includes.

[0200] In one embodiment, the second horizontal line (HL_SC2) has the largest number of shift clock lines (CLK2-1 to CLK2-5), followed by the first horizontal line (HL_SC1) with the next largest number of shift clock lines (CLK1-1 to CLK1-4), so that the second horizontal line (HL_SC2) and the first horizontal line (HL_SC1) can be arranged separately in the first horizontal line area (HA1) and the second horizontal line area (HA2), respectively. Furthermore, the second horizontal line (HL_SC2) has the largest number of shift clock lines (CLK2-1 to CLK2-5), so that two of the remaining three horizontal lines (HL_SC3, HL_SC4, HL_EM) may be arranged in the same horizontal line area (HA1, HA2) as the first horizontal line (HL_SC1), and the remaining one horizontal line may be arranged in the same horizontal line area (HA1, HA2) as the second horizontal line (HL_SC2).

[0201] According to an embodiment, the horizontal line area (HA) between the chip on film (COF) and the display area (AA) may be divided into horizontal line areas (HA1, HA2) spaced apart from each other, and the horizontal lines (HL_SC1, HL_SC2, HL_SC3, HL_SC4, HL_EM) may be arranged in each horizontal line area (HA1, HA2) according to the number of shift clock lines included in each horizontal line (HL_SC1, HL_SC2, HL_SC3, HL_SC4, HL_EM). This has the advantage that the widths of the horizontal line areas (HA1, HA2) in the second direction (DR2) can be designed to be similar, and the bezel area occupied by the horizontal line area (HA) can be significantly reduced.

[0202] In some embodiments, instead of the fifth horizontal line (HL_EM), a third horizontal line (HL_SC3) or a fourth horizontal line (HL_SC4) having the same shift clock line may be arranged in the second horizontal line area (HA2), in which case the fifth horizontal line (HL_EM) may be arranged in the first horizontal line area (HA1).

[0203] Hereinafter, a display device according to another embodiment will be described.

[0204] FIG. 11 is a plan layout diagram of a display device according to another embodiment.

[0205] Referring to Figure 11, the second horizontal line region (HA2) corresponding to the second display region (AA2) of the display device (10_1) of this embodiment (hereinafter, corresponding in the second direction (DR2)) differs from the display device (10) of Figure 7 in that it is arranged between the first horizontal line region (HA1) corresponding to the second display region (AA2) and the second horizontal line region (HA2) corresponding to the first display region (AA1).

[0206] More specifically, the second horizontal line region (HA2) corresponding to the second display region (AA2) of the display device (10_1) according to this embodiment may be disposed between the first horizontal line region (HA1) corresponding to the second display region (AA2) and the second horizontal line region (HA2) corresponding to the first display region (AA1). The second stage region (P2) of the second display region (AA2) may be disposed between the first stage region (P1) of the second display region (AA2) and the second stage region (P2) of the first display region (AA1).

[0207] According to this embodiment, the horizontal line area (HA) between the chip on film (COF) and the display area (AA) may be divided into horizontal line areas (HA1, HA2) spaced apart (or separated) from each other, and the horizontal lines (HL_SC1, HL_SC2, HL_SC3, HL_SC4, HL_EM) may be arranged in each horizontal line area (HA1, HA2) according to the number of shift clock lines included in each horizontal line (HL_SC1, HL_SC2, HL_SC3, HL_SC4, HL_EM). This has the advantage that the widths of the horizontal line areas (HA1, HA2) in the second direction (DR2) can be designed to be similar, and the bezel area occupied by the horizontal line area (HA) can be significantly reduced.

[0208] The rest of the description has been given above with reference to FIG. 7 to FIG. 10, so detailed description will be omitted below.

[0209] FIG. 12 is a plan view showing the layout of a display device according to still another embodiment.

[0210] Referring to FIG. 12, the second horizontal line region (HA2_1) of the display device (10_2) according to this embodiment is disposed between adjacent first horizontal line regions (HA1), but differs from the display device (10_1) according to FIG. 11 in that it is integrally formed.

[0211] More specifically, the second horizontal line region (HA2_1) corresponding to the first display region (AA1) (hereinafter, corresponding in the second direction (DR2)) and the second horizontal line region (HA2_1) corresponding to the second display region (AA2) may be formed integrally. That is, the second horizontal line (HL_SC2) and the fifth horizontal line (HL_EM) described above in FIG. 10 may extend integrally in the first direction (DR1) in the second horizontal line region (HA2_1) of the horizontal line region corresponding to the first display region (AA1) and the second display region (AA2).

[0212] The second stage area (P2) of the first display area (AA1) and the second stage area (P2) of the second display area (AA2) may also be formed integrally.

[0213] According to this embodiment, the horizontal line area (HA) between the chip on film (COF) and the display area (AA) may be divided into horizontal line areas (HA1, HA2_1) spaced apart (or separated) from each other, and each horizontal line (HL_SC1, HL_SC2, HL_SC3, HL_SC4, HL_EM) may be arranged in each horizontal line area (HA1, HA2_1) according to the number of shift clock lines included in each horizontal line (HL_SC1, HL_SC2, HL_SC3, HL_SC4, HL_EM). This has the advantage that the widths of each horizontal line area (HA1, HA2_1) in the second direction (DR2) can be designed to be similar, and the bezel area occupied by the horizontal line area (HA) can be significantly reduced.

[0214] The rest of the description has been given above with reference to FIG. 7 to FIG. 11, so detailed description will be omitted below.

[0215] FIG. 13 is a plan view showing a display device according to still another embodiment.

[0216] Referring to Figure 13, the display device (10_3) of this embodiment differs from the display device (10) of Figure 7 in that a second horizontal line area (HA2) and a first horizontal line area (HA1) corresponding to the first display area (AA1) (hereinafter, corresponding to the second direction (DR2)) and a second horizontal line area (HA2) and a first horizontal line area (HA1) corresponding to the second display area (AA2) are arranged from the other side of the first direction (DR1) to one side of the first direction (DR1).

[0217] Similarly, the second stage area (P2) of the first display area (AA1), the first stage area (P1), the second stage area (P2) of the second display area (AA2), and the first stage area (P1) may be arranged from the other side of the first direction (DR1) to one side of the first direction (DR1).

[0218] According to this embodiment, the horizontal line area (HA) between the chip on film (COF) and the display area (AA) may be divided into horizontal line areas (HA1, HA2) spaced apart (or separated) from each other, and the horizontal lines (HL_SC1, HL_SC2, HL_SC3, HL_SC4, HL_EM) may be arranged in each horizontal line area (HA1, HA2) according to the number of shift clock lines included in each horizontal line (HL_SC1, HL_SC2, HL_SC3, HL_SC4, HL_EM). This has the advantage that the widths of the horizontal line areas (HA1, HA2) in the second direction (DR2) can be designed to be similar, and the bezel area occupied by the horizontal line area (HA) can be significantly reduced.

[0219] FIG. 14 is a plan layout diagram of a display device according to still another embodiment.

[0220] Referring to Figure 14, the first horizontal line region (HA1) corresponding to the second display region (AA2) of the display device (10_4) of this embodiment (hereinafter, corresponding in the second direction (DR2)) differs from the display device (10_3) of Figure 13 in that it is arranged between the second horizontal line region (HA2) corresponding to the second display region (AA2) and the first horizontal line region (HA1) corresponding to the first display region (AA1).

[0221] The first stage area (P1) of the second display area (AA2) may be disposed between the second stage area (P2) of the second display area (AA2) and the first stage area (P1) of the first display area (AA1).

[0222] According to this embodiment, the horizontal line area (HA) between the chip on film (COF) and the display area (AA) may be divided into horizontal line areas (HA1, HA2) spaced apart (or separated) from each other, and the horizontal lines (HL_SC1, HL_SC2, HL_SC3, HL_SC4, HL_EM) may be arranged in each horizontal line area (HA1, HA2) according to the number of shift clock lines included in each horizontal line (HL_SC1, HL_SC2, HL_SC3, HL_SC4, HL_EM). This has the advantage that the widths of the horizontal line areas (HA1, HA2) in the second direction (DR2) can be designed to be similar, and the bezel area occupied by the horizontal line area (HA) can be significantly reduced.

[0223] FIG. 15 is a plan layout diagram of a display device according to still another embodiment.

[0224] Referring to FIG. 15, the first horizontal line region (HA1_2) of the display device (10_5) according to this embodiment is disposed between the adjacent second horizontal line regions (HA2), but differs from the display device (10_4) according to FIG. 14 in that it is integrally formed.

[0225] More specifically, the first horizontal line region (HA1_1) corresponding to the first display region (AA1) (hereinafter, corresponding in the second direction (DR2)) and the first horizontal line region (HA1_1) corresponding to the second display region (AA2) may be formed integrally. That is, the first, third and fourth horizontal lines (HL_SC1, HL_SC3, HL_SC4) described above in FIG. 10 may extend integrally in the first direction (DR1) in the first horizontal line region (HA1_1) of the horizontal line region corresponding to the first display region (AA1) and the second display region (AA2).

[0226] The first stage region (P1) of the first display region (AA1) and the first stage region (P1) of the second display region (AA2) may also be formed integrally.

[0227] According to this embodiment, the horizontal line area (HA) between the chip on film (COF) and the display area (AA) may be divided into horizontal line areas (HA1_1, HA2) spaced apart (or separated) from each other, and the horizontal lines (HL_SC1, HL_SC2, HL_SC3, HL_SC4, HL_EM) may be arranged in each horizontal line area (HA1_1, HA2) according to the number of shift clock lines included in each horizontal line (HL_SC1, HL_SC2, HL_SC3, HL_SC4, HL_EM). This has the advantage that the widths of the horizontal line areas (HA1_1, HA2) in the second direction (DR2) can be designed to be similar, and the bezel area occupied by the horizontal line area (HA) can be significantly reduced.

[0228] FIG. 16 is a detailed plan view of a first display area according to another embodiment.

[0229] 16, the embodiment differs from that of FIG. 8 in that the first branch network 153_1 and the second branch network 155_1 each extend in a step-like manner in a downward direction (eg, in a second direction DR2).

[0230] More specifically, the first branch network (153_1) may extend along the first direction (DR1) to a sub-branch circuit of the first branch circuit (1511), then bend downward, and extend from the right sub-branch circuit of the first branch circuit (1511) to the left sub-branch circuit of the third branch circuit (1513). In this manner, the first branch network (153_1) may extend from the first branch circuit (1511) to the fourth branch circuit (1514). Similarly, the second branch network (155_1) may extend along the first direction (DR1) to a sub-branch circuit of the second branch circuit (1512), then bend downward, and extend from the right sub-branch circuit of the second branch circuit (1512) to the left sub-branch circuit of the fifth branch circuit (1515). In this manner, the second branch network (155_1) may extend from the second branch circuit (1512) to the fifth branch circuit (1515).

[0231] However, the step shapes of the first and second branch networks (153_1, 155_1) illustrated in FIG. 16 are not limited to these.

[0232] According to some embodiments, a display device includes a display panel including a display area including pixels and a scan driver connected to the pixels, and a non-display area arranged around the display area; and a first chip-on-film attached to an edge of the display panel, the non-display area including a horizontal line area arranged between the first chip-on-film and the display area on a plane, the horizontal line area including a first horizontal line area and the second horizontal line area spaced apart from each other in a first direction.

[0233] The display area may include a first stage area corresponding to the first horizontal line area in a second direction intersecting the first direction, and a second stage area corresponding to the second horizontal line area in the second direction, a first stage circuit section being arranged in the first stage area, and a second stage circuit section different from the first stage circuit section being arranged in the second stage area.

[0234] The first stage circuitry may include a first branch circuit, a third branch circuit, and a fourth branch circuit, and the second stage circuitry may include a second branch circuit, and a fifth branch circuit.

[0235] The first branch circuit may be connected to a first scan line connected to the pixel, the second branch circuit may be connected to a second scan line connected to the pixel, the third branch circuit may be connected to a third scan line connected to the pixel, the fourth branch circuit may be connected to a fourth scan line connected to the pixel, and the fifth branch circuit may be connected to a light emission control signal line connected to the pixel.

[0236] The first horizontal line region may include a first horizontal line connected to the first branch circuit, a third horizontal line connected to the third branch circuit, and a fourth horizontal line connected to the fourth branch circuit, and the second horizontal line region may include a second horizontal line connected to the second branch circuit, and a fifth horizontal line connected to a fifth branch circuit.

[0237] Each of the first to fifth horizontal lines may include a plurality of shift clock lines, and the second horizontal line may have the largest number of shift clock lines.

[0238] The semiconductor device may further include a second chip-on-film spaced apart from the first chip-on-film in the first direction.

[0239] The display area may include a first display area corresponding to the first chip-on-film in the second direction, and a second display area corresponding to the second chip-on-film in the second direction, and two of the first and second horizontal line areas may be provided.

[0240] The second horizontal line region that corresponds to the first display region in the second direction may be arranged between the first horizontal line region that corresponds to the first display region in the second direction and the first horizontal line region that corresponds to the second display region in the second direction.

[0241] The second horizontal line region that corresponds to the first display region in the second direction may be arranged between the first horizontal line region that corresponds to the first display region in the second direction and the second horizontal line region that corresponds to the second display region in the second direction.

[0242] The second horizontal line region corresponding to the first display region in the second direction and the second horizontal line region corresponding to the second display region in the second direction may be formed integrally with each other, and the second horizontal line and the fifth horizontal line arranged in the second horizontal line region corresponding to the first display region in the second direction and the second horizontal line region corresponding to the second display region in the second direction may each extend integrally.

[0243] The first horizontal line region that corresponds to the first display region in the second direction may be arranged between the second horizontal line region that corresponds to the first display region in the second direction and the second horizontal line region that corresponds to the second display region in the second direction.

[0244] The first horizontal line region that corresponds to the first display region in the second direction may be arranged between the second horizontal line region that corresponds to the first display region in the second direction and the first horizontal line region that corresponds to the second display region in the second direction.

[0245] The first horizontal line region corresponding to the first display region in the second direction and the first horizontal line region corresponding to the second display region in the second direction may be formed integrally with each other, and the first horizontal line, the third horizontal line, and the fourth horizontal line arranged in the first horizontal line region corresponding to the first display region in the second direction and the first horizontal line region corresponding to the second display region in the second direction may each extend integrally.

[0246] The above description and the accompanying drawings are merely illustrative of the technical idea, and a person having ordinary skill in the art to which this specification pertains may make various modifications and variations, such as combination, separation, substitution, and alteration of the configuration, within the scope of the essential characteristics. Therefore, the embodiments disclosed in this specification are for illustrative purposes only and are not intended to limit the technical idea, and the scope of the technical idea is not limited by such embodiments. The scope of protection should be interpreted according to the following claims, and any technical idea within the scope equivalent thereto should be interpreted as being included in the scope of rights. [Explanation of symbols]

[0247] 100: Display panel 200: Controller 300: Scan drive unit 400: Data Drive Unit 500: Power supply section

Claims

1. A display panel including a display area including pixels and a scan driver connected to the pixels, and a non-display area disposed around the display area; and a first chip-on-film connected to an edge of the display panel; the non-display area includes a first horizontal line area and a second horizontal line area disposed between the first chip-on-film and the display area on a plane; Each of the first horizontal line region and the second horizontal line region includes a plurality of control lines that supply gate control signals, and the plurality of control lines extend in a horizontal direction that is a first direction intersecting a direction in which the first chip-on-film and the display region are aligned, A display device, wherein the first horizontal line region and the second horizontal line region are arranged with a gap therebetween in the first direction.

2. 2. The display device of claim 1, wherein the display area includes a first stage area corresponding to the first horizontal line area in a second direction intersecting the first direction, and a second stage area corresponding to the second horizontal line area in the second direction, a first stage circuit section is arranged in the first stage area, and a second stage circuit section different from the first stage circuit section is arranged in the second stage area.

3. The display device of claim 2 , wherein the first stage circuitry includes a first branch circuit, a third branch circuit, and a fourth branch circuit, and the second stage circuitry includes a second branch circuit, and a fifth branch circuit.

4. 4. The display device of claim 3, wherein the first branch circuit is connected to a first scan line connected to the pixel, the second branch circuit is connected to a second scan line connected to the pixel, the third branch circuit is connected to a third scan line connected to the pixel, the fourth branch circuit is connected to a fourth scan line connected to the pixel, and the fifth branch circuit is connected to a light emission control signal line connected to the pixel.

5. 5. The display device of claim 4, wherein the first horizontal line region includes a first horizontal line connected to the first branch circuit, a third horizontal line connected to the third branch circuit, and a fourth horizontal line connected to the fourth branch circuit, and the second horizontal line region includes a second horizontal line connected to the second branch circuit, and a fifth horizontal line connected to a fifth branch circuit.

6. The display device according to claim 5 , wherein each of the first to fifth horizontal lines includes a plurality of shift clock lines, and the second horizontal line has the largest number of the shift clock lines.

7. The display device of claim 5 , further comprising a second chip-on-film spaced apart from the first chip-on-film in the first direction.

8. The display device of claim 7, wherein the display area includes a first display area corresponding to the first chip-on-film in the second direction, and a second display area corresponding to the second chip-on-film in the second direction, and two of the first horizontal line areas and two of the second horizontal line areas are provided, respectively.

9. The display device of claim 8, wherein the second horizontal line region corresponding to the first display region in the second direction is arranged between the first horizontal line region corresponding to the first display region in the second direction and the first horizontal line region corresponding to the second display region in the second direction.

10. The display device of claim 8, wherein the second horizontal line region corresponding to the first display region in the second direction is arranged between the first horizontal line region corresponding to the first display region in the second direction and the second horizontal line region corresponding to the second display region in the second direction.

11. The display device of claim 8, wherein the second horizontal line region corresponding to the first display area in the second direction and the second horizontal line region corresponding to the second display area in the second direction are formed integrally with each other, and the second horizontal line and the fifth horizontal line arranged in the second horizontal line region corresponding to the first display area in the second direction and the second horizontal line region corresponding to the second display area in the second direction, respectively, extend integrally.

12. The display device of claim 8, wherein the first horizontal line region corresponding to the first display region in the second direction is arranged between the second horizontal line region corresponding to the first display region in the second direction and the second horizontal line region corresponding to the second display region in the second direction.

13. The display device of claim 8, wherein the first horizontal line region corresponding to the first display region in the second direction is arranged between the second horizontal line region corresponding to the first display region in the second direction and the first horizontal line region corresponding to the second display region in the second direction.

14. The display device of claim 8, wherein the first horizontal line region corresponding to the first display area in the second direction and the first horizontal line region corresponding to the second display area in the second direction are formed integrally with each other, and the first horizontal line, the third horizontal line, and the fourth horizontal line arranged in the first horizontal line region corresponding to the first display area in the second direction and the first horizontal line region corresponding to the second display area in the second direction, respectively, each extend integrally.

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