Signal processing circuit and electronic device

Abstract

To provide a signal processing circuit that allows a receiving side to appropriately amplify a received signal.SOLUTION: A signal processing circuit includes an analog signal processing unit in which a plurality of analog signal processing circuits are connected in series, each analog signal processing circuit including a lowpass filter that passes an analog signal of a first frequency or lower, a high-pass filter that passes the analog signal of a second frequency or higher, a clamp circuit that limits voltage of the analog signal to a predetermined range, and a low-noise amplifier that amplifies the analog signal.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a signal processing circuit and an electronic device.

Background Art

[0002] Generally, wireless communication is configured such that, for example, in a wireless communication system such as an automatic ticket gate system at a station or a keyless entry system, an IC ticket or a remote control cannot perform wireless communication unless it approaches an automatic ticket gate or a vehicle, etc. And as another example, like CDMA (Code Division Multiple Access) communication (see Patent Document 1 and Patent Document 2), there are cases where it is configured to be able to perform wireless communication even when separated, and the system was configured in advance as being limited to one of them.

[0003] Therefore, a wireless communication system has been proposed that can control the range in which wireless communication is possible, maintain good communication quality even when the communication distance fluctuates, and enable high-quality communication even with weak power (see Patent Document 3). Patent Document 3 discloses a communication device that enables high-quality communication even with weak power by adding (integrating) a plurality of the same data.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0005] In order to enable high-quality communication even with weak power, it is necessary to amplify the received signal on the receiving side in order to recognize the content of the signal.

[0006] The present invention has been made in view of the above points, and an object thereof is to provide a signal processing circuit and an electronic device that appropriately amplify a received signal on the receiving side.

Means for Solving the Problems

[0007] In order to achieve the above object, a signal processing circuit according to an aspect of the present invention includes a low-pass filter that passes an analog signal having a frequency equal to or lower than a first frequency, a high-pass filter that passes the analog signal having a frequency equal to or higher than a second frequency, a clamp circuit that limits the voltage of the analog signal to a predetermined range, and a low-noise amplifier that amplifies the analog signal, and includes an analog signal processing unit in which a plurality of analog signal processing circuits are connected in series.

[0008] The signal processing circuit may further include a comparator that compares the voltage of the analog signal output from the analog signal processing unit with a predetermined voltage.

[0009] The predetermined voltage may be 0 volts.

[0010] Also, in order to achieve the above object, a wireless communication device according to another aspect of the present invention includes the above signal processing circuit.

Effects of the Invention

[0011] According to the present invention, by connecting a plurality of analog signal processing circuits in series, it is possible to provide a signal processing circuit and a wireless communication device that can appropriately amplify a received signal on the receiving side.

Brief Description of the Drawings

[0012]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Embodiments for Carrying Out the Invention

[0013] Hereinafter, an example of an embodiment of the present disclosure will be described with reference to the drawings. In each drawing, the same or equivalent components and parts are given the same reference numerals. Also, the dimensional ratios in the drawings are exaggerated for convenience of explanation and may be different from the actual ratios.

[0014] FIG. 1 is a diagram showing a schematic configuration of a signal processing circuit according to the present embodiment.

[0015] The signal processing circuit shown in FIG. 1 is composed of an analog signal processing circuit 100 and a comparator 110.

[0016] The analog signal processing circuit 100 is composed of a high-pass filter (HPF) 101, a low-pass filter (LPF) 102, a clamp circuit 103, and a low-noise amplifier (LNA) 104. In FIG. 1, the high-pass filter 101, the low-pass filter 102, the clamp circuit 103, and the low-noise amplifier 104 are connected in this order, but the connection order is not limited to such an example.

[0017] The high-pass filter 101 is a filter that passes an analog signal below a predetermined first frequency and attenuates an analog signal exceeding the first frequency. As shown in FIG. 1, the high-pass filter 101 is composed of a resistor in parallel with the input signal and a capacitor in series with the input signal.

[0018] The low-pass filter 102 is a filter that passes an analog signal having a predetermined second frequency or higher and attenuates an analog signal having a frequency lower than the second frequency. As shown in FIG. 1, the low-pass filter 102 is composed of a capacitor in parallel with the input signal and a resistor in series with the input signal.

[0019] The clamp circuit 103 is a circuit that limits the voltage of an analog signal to a predetermined range. As shown in FIG. 1, the clamp circuit 103 is composed of a resistor in series with the input signal and a Zener diode in parallel with the input signal.

[0020] The low-noise amplifier 104 is a circuit that amplifies an analog signal by a predetermined amount, and mainly amplifies a weak analog signal.

[0021] The comparator 110 is a circuit that compares the voltage of the analog signal output from the analog signal processing circuit 100 with a predetermined reference voltage. The predetermined reference voltage is, for example, 0 volts.

[0022] In order to accurately detect the state of a weak analog signal, the low-noise amplifier 104 requires sufficient gain. When the S / N is -100 dB to -160 dB noise, if the analog signal is too small, the dynamic range required for the low-noise amplifier 104 is very large, and at least 100 dB to 160 dB or more is required.

[0023] If the minimum voltage required for the comparator 110 is 1 μV, the maximum noise is 100 V. For a normal low-noise amplifier 104, an amplifier with a power supply voltage of 100 V or more and a dynamic range of 160 dB is required. It is very difficult to realize such a low-noise amplifier 104 that satisfies such predetermined conditions.

[0024] Therefore, in the present embodiment, a signal processing circuit in which a plurality of the analog signal processing circuits shown in FIG. 1 are connected in series is shown. By connecting a plurality of the analog signal processing circuits shown in FIG. 1 in series, it is possible to secure a gain for detecting a minute signal.

[0025] Figure 2 is a diagram showing a schematic configuration of a signal processing circuit according to an embodiment of the present invention.

[0026] The signal processing circuit shown in Figure 2 is composed of an analog signal processing unit 10 and a comparator 110.

[0027] The analog signal processing unit 10 has a configuration in which a plurality of analog signal processing circuits 100 are connected in series. For example, if a gain of 160 dB is required to output to the comparator 110 and a gain of 20 dB can be obtained with one analog signal processing circuit 100, the analog signal processing unit 10 can obtain a desired gain by connecting eight analog signal processing circuits 100 in series.

[0028] Subsequently, a communication device using the signal processing circuit shown in Figure 2 will be described.

[0029] Figure 3 is a diagram showing communication devices 200A and 200B. The communication devices 200A and 200B shown in Figure 3 perform wireless communication with each other. The communication devices 200A and 200B according to the present embodiment transmit data packets to the other party, and the communication devices 200A and 200B that receive data packets from the other party transmit one response packet to the other party.

[0030] In the following description, the communication devices 200A and 200B may be collectively referred to simply as the communication device 200. Also, in the following description, in the wireless communication system using the communication devices 200A and 200B, it is assumed that data packets and response packets are encoded and decoded based on the Manchester coding method. Of course, the coding method is not limited to such an example.

[0031] Figure 4 is a diagram showing a functional configuration example of the communication device 200.

[0032] The communication device 200 is composed of a receiving antenna 201, a receiving circuit 202, an AD converter 203, a periodic integration circuit 210, a decoding / synchronization detection circuit 204, an error detection circuit 205, a receiving buffer 206, a periodic integration circuit 210, a clock recovery circuit 220, a transmitting buffer 221, an error detection code addition circuit 222, an encoding circuit 223, a DA converter 224, a transmitting circuit 225, and a transmitting antenna 226.

[0033] The receiving antenna 201 receives the transmission packet transmitted from the wireless communication partner. The transmission packet received by the receiving antenna 201 is sent to the receiving circuit 202.

[0034] The receiving circuit 202 performs receiving processing on the transmission packet received by the receiving antenna 201, for example, amplification processing and noise filtering processing for removing noise generated on the transmission path. The receiving circuit 202 sends the signal after performing the receiving processing on the transmission packet to the AD converter 203.

[0035] The AD converter 203 converts the signal sent from the receiving circuit 202 into a digital signal. Specifically, the AD converter 203 outputs 1 when exceeding the reference value and outputs 0 when less than the reference value.

[0036] The periodic integration circuit 210 executes periodic integration processing on the digital signal sent from the AD converter 203 and the digital signal sent from the encoding circuit 223. The periodic integration circuit 210 includes a plurality of registers 211, 213, an adder 212, and a selector 214.

[0037] The registers 211, 213 are provided corresponding to the number required for sampling the bits forming the data packet. Specifically, the digital signal sent from the AD converter 203 is sampled according to the number of the registers 211, and the values at each sampling point are respectively integrated in the plurality of registers 211. Also, the data sent from the encoding circuit 223 is sampled according to the number of the registers 213, and the values at each sampling point are respectively integrated in the plurality of registers 213.

[0038] The adder 212 adds and outputs the digital signal sent from the AD converter 203 and the signal output from the last-stage register 211 among the plurality of registers 211.

[0039] The decoding / synchronization detection circuit 204 decodes the signal output from the periodic integration circuit 210, detects a predetermined pattern, and synchronizes.

[0040] The error detection circuit 205 performs an error detection process on the decoded signal. Specifically, when the data output from the decoding / synchronization detection circuit 204 satisfies CRC (Cyclic Redundancy Check), the error detection circuit 205 determines that a correct data packet has been received, and when it does not satisfy, it determines that a correct data packet has not been received.

[0041] The receive buffer 206 buffers the data output from the error detection circuit 205 and outputs it to a control circuit (not shown) at a predetermined timing.

[0042] The clock recovery circuit 220 includes a PLL (Phase Locked Loop) inside and supplies clocks to the decoding / synchronization detection circuit 204, the error detection circuit 205, the receive buffer 206, the periodic integration circuit 210, the transmit buffer 221, the error detection code addition circuit 222, and the encoding circuit 223.

[0043] The transmit buffer 221 buffers the data from a control circuit (not shown).

[0044] The error detection code addition circuit 222 adds an error detection code for performing error detection in the communication device 200 of the communication partner.

[0045] The encoding circuit 223 Manchester-encodes the data sent from the error detection code addition circuit 222 and sends it to the periodic integration circuit 210.

[0046] The DA converter 224 converts the data sent from the periodic integration circuit 210 into an analog signal.

[0047] The transmission circuit 225 executes signal processing on the analog signal sent from the DA converter 224.

[0048] The transmission antenna 26 transmits the signal sent from the transmission circuit 225.

[0049] FIG. 5 is a diagram showing the structure of a packet communicated by the communication device 200.

[0050] The packet 300 shown in FIG. 5 consists of a preamble part 301, a synchronization code part 302, a payload length part 303, a payload part 304, a CRC part 305, and a postamble part 306. The length of each block can be set to an arbitrary length.

[0051] The preamble part 301 is a block in which a code indicating the start of the packet 300 is stored.

[0052] The synchronization code part 302 is a block in which a synchronization code for synchronizing a plurality of packets 300 on the receiving side is stored. Note that, as the synchronization code, a violation code that does not exist in the normal data stored in the payload part 304 can be used. As the violation code, for example, data not used in a data conversion method such as the 8b / 10b method can be used.

[0053] The payload length part 303 is a block in which information on the length of the subsequent payload part 304 is stored.

[0054] The payload part 304 is a block in which data transmitted from the transmitting side to the receiving side is stored.

[0055] The CRC part 305 is a block in which data for CRC on the receiving side is stored.

[0056] The postamble section 306 is a block in which a code indicating the end of the packet 300 is stored.

[0057] The communication device 200 on the transmitting side and the receiving side according to the present embodiment can receive data with high quality even when the communication distance varies by receiving a packet 300 in which the same data is stored in the payload section 304. Further, when transmitting the same data, the communication device 200 according to the present embodiment enables high-quality communication even with weak power.

[0058] Also, the signal processing circuit according to the present embodiment is used in the communication device 200 shown in FIG. 4, so that a gain for detecting a minute signal can be secured.

[0059] The present invention can be applied to all communication systems such as space communication, military communication, card payment, and civilian digital communication such as keyless entry systems.

Explanation of Signs

[0060] 10 Analog signal processing unit 100 Analog signal processing circuit 101 High-pass filter 102 Low-pass filter 103 Clamp circuit 104 Low-noise amplifier 110 Comparator 200 Communication device 201 Receiving antenna 202 Receiving circuit 203 AD converter 204 Decoding / synchronous detection circuit 205 Error detection circuit 206 Receiving buffer 210 Periodic integration circuit 220 Clock recovery circuit 221 Transmitting buffer 222 Error detection code addition circuit 223 Encoding circuit 224 DA converter 225 Transmitting circuit 226 Transmission Antenna

Claims

1. a low pass filter that passes analog signals having a frequency equal to or lower than a first frequency; a high-pass filter that passes the analog signal having a second frequency or higher; a clamp circuit for limiting the voltage of the analog signal to a predetermined range; a low noise amplifier for amplifying the analog signal; A signal processing circuit comprising an analog signal processing section in which a plurality of analog signal processing circuits each comprising:

2. 2. The signal processing circuit according to claim 1, further comprising a comparator that compares a voltage of the analog signal output by the analog signal processing unit with a predetermined voltage.

3. 3. The signal processing circuit according to claim 2, wherein the predetermined voltage is 0 volts.

4. An electronic device comprising the signal processing circuit according to any one of claims 1 to 3.

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