Waveform generation circuit

Abstract

To provide a faster and cheaper waveform generation circuit that has a low jitter effect on arbitrary waveform generation.SOLUTION: A waveform generation circuit 10 includes: an accumulator 11 that adds and outputs a phase addition value for each clock; a waveform memory 12 that stores waveform data on the digitized waveform output; a data processing unit 13 that reads the waveform data from the waveform memory 12 for each clock, and outputs waveform processing data interpolated at sudden change positions in the waveform data on the basis of the read waveform data; a DA converter 14 that converts the waveform processing data to an analog signal; and a low-pass filter 15 that smooths an analog signal from the DA converter 14 and outputs the smoothed signal. The interpolation of the waveform data is performed according to the data at two consecutive points of the sudden change position of the waveform data, the fraction of the accumulator 11, and the phase addition value.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a waveform generation circuit, and more particularly to a waveform generation circuit that outputs an arbitrary waveform.

Background Art

[0002] As a waveform generation circuit capable of generating an arbitrary waveform, a waveform generation circuit based on the digital direct synthesis (hereinafter abbreviated as DDS) method is known. Such a waveform generation circuit holds, for example, waveform data for one period in a waveform memory, sequentially reads out the waveform data every certain clock period, and outputs it as an analog signal by a DA converter based on the read data, thereby outputting a periodic signal having a desired waveform.

[0003] Regarding such a signal generator, for example, in the synthesizer disclosed in Patent Document 1, a synthesizer that can perform accurate and high-resolution edge placement without requiring a system clock having a frequency much higher than the frequency of the synthesized clock signal is realized.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In a conventional DDS waveform generation circuit, the output frequency is changed by setting an increment for each clock by an adder. However, in the case of a waveform having a portion where the magnitude of a signal such as a rectangular wave changes abruptly, it is inevitable that jitter occurs at the abrupt change point of the waveform depending on the output frequency. In response to such a problem of the conventional waveform generation circuit, in the invention according to Patent Document 1, when generating a signal such as a rectangular wave represented by a clock, for example, a comparator is used for a sine wave passed through a band-pass filter to reduce jitter. However, there is a problem that the low-jitter output waveform obtained by such a method is limited to a specific waveform such as a rectangular wave, and an effect cannot be obtained for waveforms of arbitrary shapes.

[0006] An object of the present invention is to provide a waveform generation circuit that has an effect of low jitter for generating arbitrary waveforms and is faster and less expensive.

Means for Solving the Problems

[0007] To achieve the above object, the waveform generation circuit of the present invention includes A waveform generation circuit using the DDS method, an accumulator that adds and outputs a phase addition value for each clock, and stores waveform data of a digitized waveform output wherein the upper bits of the output of the accumulator are used as address inputs, a waveform memory, taking the output of the accumulator and the data output of the waveform memory as inputs, reads waveform data from the waveform memory for each clock the and, based on the read the waveform data and the lower bits of the output of the accumulator other than the upper bits outputs waveform processing data that has been the processed at abrupt change points of the waveform data correction a data processing unit, a DA converter that converts the waveform processing data into an analog signal, and an analog signal from the DA converter generating smoothes and outputs using the data input as the data input and a low-pass filter, and is characterized by including output waveform this. signal and reducing jitter

[0008] In the above configuration, Let the period of the output signal be T O and the period of the clock be T ACLK ​​When this is the case, a positive integer N is selected such that N ≤ T O / T ACLK is satisfied, the number of data points of the waveform data is set to N, and the N pieces of the waveform data are Write to the waveform memory seen, The phase addition value When this is taken as Δθ, Δθ is expressed as Δθ = N·T ACLK / T o and its value is Be 1 or less such that when the value of the upper bits of the output of the accumulator exceeds N, it returns to 0, and the operation is based on the continuous adjacent waveform data This is preferable.

[0009] Further, the waveform generation circuit of the present invention is a waveform generation circuit of a DDS system, and includes an accumulator that adds and outputs a phase addition value for each clock, and stores waveform data of a digitized waveform output existing And a waveform memory, and supplies to the waveform memory each time the value of the upper bits of the output of the accumulator increases wave A configuration for generating a clock for the waveform memory and supplying it to the waveform memory, a configuration for supplying a reset signal to the waveform memory when the value of the upper bits of the output of the accumulator exceeds the number of data points of the waveform data, and And a data processing unit having a configuration for inputting the output of the accumulator and the data output of the waveform memory, reading the waveform data from the waveform memory for each clock for the waveform memory, and based on the lower bits other than the upper bits of the read waveform data and the output of the accumulator, generating and outputting waveform processing data corrected at a rapid change point of the waveform data, a DA converter that converts the waveform processing data into an analog signal with the waveform processing data as a data input, and a low-pass filter that smooths the analog signal output waveform from the DA converter to obtain an output signal, characterized in that jitter is reduced.

[0010] In the above configuration, the the Waveform data inside Add correction necessity information to, and based on the correction necessity information the Of the waveform data correction It is preferable to configure the data processing unit to determine whether or not to perform.

[0011] In the above configuration correctionthat do not need to be performed the It is preferable that the waveform data has the digitized information of the waveform output written also in the data part of the correction necessity information.

[0012] Furthermore, Let the bit addition value be Δθ and the value obtained by replacing the data of the lower bits with the decimal part be D U When this is the case, the correction coefficient k is set to k = (1 - D U ) / Δθ, and the period of the clock is T ACLK , the time is T X At this time, the waveform data is Da(T X ), and the waveform data at the sampling time immediately before that is Da(T X -T ACLK ). When this is the case, based on the correction coefficient k, the data generation unit included in the data processing unit outputs data of k·Da(T X )+(1 - k)·Da(T X -T ACLK ) is preferable.

Advantages of the Invention

[0013] According to the present invention, it is possible to reduce jitter and to provide a waveform generation circuit that is faster and less expensive than conventional waveform generation circuits.

Brief Description of the Drawings

[0014]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Mode for Carrying Out the Invention

[0015] Hereinafter, embodiments of the present invention will be described. However, the present invention is not limited to the following description, and various modifications and changes can be made by those skilled in the art based on the gist of the invention described in the claims or disclosed in the mode for carrying out the invention. Such modifications and changes are also included in the scope of the present invention.

[0016] 〔First Embodiment〕 The first embodiment is an example of a waveform generation circuit based on a basic configuration. Examples according to the first embodiment are shown in FIGS. 1 to 6. FIG. 1 is a diagram showing a configuration example of a waveform generation circuit according to the first embodiment. FIG. 2 is a diagram showing an example of an accumulator output. FIG. 3 is a diagram showing an example of input / output signals of a low-pass filter. FIG. 4 is a diagram showing a configuration example of a data processing unit. FIG. 5 is a diagram showing a configuration example of a data generation unit. FIG. 6 is a diagram showing an example of a rectangular wave output.

[0017] FIG. 1 is an example of the configuration of a waveform generation circuit 10 according to the first embodiment. The waveform generation circuit 10 includes an accumulator 11, a waveform memory 12, a data processing unit 13, a DA converter 14, and a low-pass filter 15.

[0018] The accumulator 11 adds and outputs a phase addition value Δθ corresponding to the period T of the output signal O (= the reciprocal of the frequency f O ) for each clock according to the period setting based on the reciprocal). O It is a part that adds and outputs the phase addition value Δθ corresponding to the period T of the output signal.

[0019] The phase addition value Δθ is based on the period T of the output signal O , the register of the accumulator 11 is D bits, and the period of the clock of the accumulator 11 is T ACLK (the reciprocal of which is the frequency fACLK Let it be so. Then, it is given by the following (Equation 1-1).

[0020]

Number

[0021] The accumulator 11 of D bits adds Δθ each clock cycle T of the accumulator 11 ACLK and repeats the operation sequentially in a form that ignores the carry to the 2 D bit when it exceeds 2 D -1.

[0022] The waveform memory 12 is a storage medium for storing, as digitized waveform data, one period of a waveform having not only typical shapes such as a sine wave, a rectangular wave, or a triangular wave but also any other arbitrary shape. The waveform memory 12 is a digital memory such as a ROM (Read Only Memory), a RAM (Random Access Memory), or a sequential memory. The waveform memory 12 sequentially outputs waveform data for each clock. The output data becomes the data at the address specified by the output of the accumulator 11 from among the waveform data written in the waveform memory 12 if the waveform memory 12 is a randomly accessible memory. If the waveform memory 12 is a sequential memory, the output data is sequentially output while repeating the operation of sequentially outputting the waveform data previously written in the waveform memory 12 from the head data in order, and returning to the head data after the last data.

[0023] The data processing unit 13 performs various processes according to the input from the waveform memory 12 and the input from the accumulator 11, generates waveform processing data, and outputs it. The details of the processing in this data processing unit 13 will be described later.

[0024] The DA converter 14 uses the output of the data processing unit 13 as the waveform processing data input, and outputs a signal obtained by converting the waveform processing data, which is numerical data, into an analog signal for each clock of the DA converter 14.

[0025] By each part repeating such an operation for each clock input, an analog periodic signal having a waveform written in the waveform memory 12 with a frequency of f O is obtained as the output signal. The analog signal, which is the output signal of this DA converter 14, becomes a stepped waveform having a flat portion for each clock period T ACLK .

[0026] The low-pass filter 15 is arranged to smooth the stepped waveform that is the output signal from the DA converter 14. The characteristics of the low-pass filter 15 may be a low-pass filter with a cut-off frequency having an attenuation amount with respect to the clock frequency f ACLK .

[0027] FIG. 2 is a diagram showing the output value of the accumulator 11 with the horizontal axis being time and the vertical axis being the output value of the accumulator 11. As time passes, the output value of the accumulator 11 behaves like a sawtooth wave that repeats values between 0 and 2 D -1 at a frequency of f O (T O = 1 / f O ).

[0028] The two D possible values that can be taken as the output value of this accumulator 11 are values corresponding to the phase of one period of the waveform. For example, when the horizontal axis of one period of the periodic signal is represented by a phase of 360 deg, the phase 0 deg is 0, the phase 180 deg is 2 D-1 , and immediately before the phase 360 deg is 2 D -1. Then, the upper D1 bits (D1 is a positive integer less than D) of the output of the accumulator 11 are input to the address bus of the waveform memory 12.

[0029] FIG. 3(A) shows an example of the input signal and output signal of the low-pass filter 15. The horizontal axis represents time, and the vertical axis represents the magnitude of the signal. The stepped waveform output from the DA converter 14 is shown by a solid line, and the waveform smoothed by the low-pass filter 15 is shown by a dotted line. The output of the low-pass filter 15 with the stepped waveform input shows a transient response as shown by the dotted line according to the time constant of the low-pass filter 15 and the like. This transient response becomes a waveform that monotonically increases or decreases to the output value of the next step as time passes. Hereinafter, for the sake of simplicity, unless otherwise specified, as shown in FIG. 3(B), it will be described in a form where the sampling points are connected by straight lines.

[0030] FIG. 4 shows an example of the configuration of the data processing unit 13. The data processing unit 13 includes a data generation unit 21 and a correction determination unit 22. The waveform data that is the output of the waveform memory 12 is input to the data generation unit 21 and the correction determination unit 22 of the data processing unit 13, respectively.

[0031] Based on the input waveform data, the correction determination unit 22 determines whether to perform correction processing on the waveform processing data output to the DA converter 14, and when it is determined that correction is necessary, outputs a correction command signal to the data generation unit 21. This determination can be made, for example, by comparing a certain threshold value with the absolute value of the difference between adjacent waveform data when there is a change of 10% or more with respect to the full range of the waveform data. When the conditions in this example are specifically expressed by an equation, taking a certain threshold value as A th , the waveform data at time T X as Da(T X ), and the waveform data at the sampling time immediately before that as Da(T X - T ACLK ), the following (Equation 1-2) becomes the condition for outputting the correction command signal.

[0032]

Equation

[0033] Note that the threshold value A th can be arbitrarily set with respect to the full range of the waveform data, such as 30% or 50% of the full range, or it can be an operation corresponding to 0% where constant correction works.

[0034] The data generation unit 21 performs the following processing according to the presence or absence of a correction command signal from the correction determination unit 22. (1) When there is no correction command signal Output the input waveform data as waveform processing data in the input order. (2) When there is a correction command signal For the part of the waveform data where there is a change of more than the threshold value A due to the input direct waveform data A and the past waveform data via the delay unit 31 described later, output the corrected waveform processing data instead of the data output in (1). th

[0035] FIG. 5 is an example of the configuration of the data generation unit 21. The data generation unit 21 includes a delay unit 31, a subtraction unit 32, a multiplication unit 33, and an addition unit 34. In the data generation unit 21, at a certain time T X the difference between the waveform data Da(T X ) input at that time and the waveform data Da(T X -T ACLK ) input at the previous clock via the delay unit 31 is obtained by the subtraction unit 32, and the result is multiplied by the correction coefficient k from the correction determination unit 22 by the multiplication unit 33. The sum of the multiplied value and the waveform data Da(T X -T ACLK ), which is the output of the delay unit 31, is obtained by the addition unit 34, and the result is output. By such internal calculations, the data output from the data generation unit 21 is as shown in the following (Equations 1-3).

[0036]

Equation

[0037] The correction coefficient k is in the range of 0 ≦ k ≦ 1. From (Equations 1-3), the output of the data generation unit 21 is, when k = 0, Da(TX -T ACLK ) is obtained. When k = 1, Da(T X ) is obtained. When 0 < k < 1, the input signal Da(T X ) and the input signal Da(T X -T ACLK ) at the previous sampling time T X -T ACLK ) are weighted-averaged by the correction coefficient k.

[0038] The value of the correction coefficient k is determined as follows, for example. (1) When there is no correction command signal, k = 0. At this time, the output of the data generation unit 21 is Da(T X -T ACLK ). (2) When there is a correction command signal, k is the fractional part D obtained by replacing the data of the lower D2 bits of the accumulator 11 with a numerical value below the decimal point. U Based on the value of the carry addition value Δθ, the value calculated by the following (Equation 1-4) is used.

[0039]

Equation

[0040] The calculation of the value of this correction coefficient k may be performed by the correction determination unit 22. Also, there is no need to prepare a separate signal as the correction command signal. If the correction coefficient k is 0, the operation is the same as in the case without the correction command signal described above. By setting the correction coefficient k to k > 0, the operation is the same as in the case with the correction command signal. The correction determination unit 22 may have such a configuration.

[0041] Figure 6 is a diagram showing an example of a rectangular wave output. An example of a specific operation according to the example of the first embodiment will be described with a model in which the address length of the waveform memory 12 is simplified to 8 bits and the waveform is a rectangular wave. Also, for the sake of simplicity of explanation, the output of the accumulator 11 corresponds to the upper D1 bit portion corresponding to the address length of the waveform memory 12 as the integer part, and the fractional part D of the lower D2 bit portion of the accumulator 11. UThe numerical value corresponding to it is used as the decimal part, and the description is given in the form expressed in decimal. Corresponding to the example of the phase shown, address 0 is phase 0 deg, address 128 (= 2 7 ) is phase 180 deg, and address 255 (= 2 8 - 1) corresponds to just before phase 360 deg. And the waveform data in the waveform memory 12 has the maximum value of the rectangular wave as A MAX , the minimum value as A MIN , and from address 0 to 127 (= 2 7 - 1) of the waveform memory 12 has A MAX , and from address 128 (= 2 7 ) to 255 (= 2 8 - 1) has A MIN written. However, the address length of the waveform memory 12 is not limited to 8 bits, and further, the number of addresses of the waveform memory 12 is not limited to 2 n (n is a positive integer).

[0042] Here, the period T ACLK of the clock is 1 ns (frequency f ACLK = 1 GHz), and the period setting of the accumulator 11 is performed so that the frequency f O of the output signal of the waveform generation circuit 10 becomes 3 MHz. This period setting, in other words, is the period in which exactly 3 waves of rectangular waves are output in 1 μs (= 1000 ns, 1000 waves of clock).

[0043] At this time, the phase addition value Δθ is

[0044]

Equation

[0045] The initial value of the accumulator 11 is set to 0, and this time is set as time 0. Since the value of the accumulator 11 is incremented by the phase addition value Δθ for each input of the clock,

[0046]

Equation

[0047]

Number

[0048]

Number

[0049] The length of one cycle of the rectangular wave is that the time from time 0 to the first return to phase 0 is 334 ns, the time from here to the second return to phase 0 is 333 ns, and further the time from here to the return to phase 0 is 333 ns, and this cycle is repeated. That is, the frequency f of the output signal O Even with the cycle setting to the accumulator 11 such that it becomes 3 MHz, as shown in FIG. 6(B), the output signal is output separately in the cases of 333 ns and 334 ns for one cycle. In this way, jitter occurs in the conventional DDS method. The same applies to the falling edge part.

[0050] FIG. 6(C) is an example showing the rising edge part of the output signal when correction is performed by the correction determination unit 22 under the same setting conditions.

[0051] When returning from just before the phase of 360 deg (address 255) to phase 0, since the value of the waveform data suddenly changes from A MIN to A MAX Therefore,

[0052]

Number

[0053] Normally, the waveform processing data output from the data generation unit 21 to the DA converter 14 is sent after a delay of one clock. When the correction determination unit 22 determines that correction is required, corrected waveform processing data is generated based on the calculated k between the waveform data delayed by one clock and the waveform data without delay.

[0054] For example, between the 333rd clock and the 334th clock from time 0, the value of the waveform data changes abruptly from A MIN to A MAX and becomes equal to or greater than the threshold value A th At this time, when k is applied to (Equation 1-4), the fractional part D U which is the numerical value after the decimal point of the accumulator 11 at the input time of the 333rd clock, is 0.744 as shown in (Equation 1-6), and since Δθ = 0.768,

[0055]

Number

[0056] Similarly, between the 666th clock and the 667th clock from time 0, the value of the waveform data changes abruptly from A MIN to A MAX At this time, when k is obtained based on (Equation 1-4), the fractional part D

[0057] of the accumulator 11 at the input time of the 666th clock is 0.488 as shown in (Equation 1-7), so U is, as shown in (Equation 1-7), 0.488, so

[0058]

Number

[0059] From this, it can be seen that due to this correction, the end part of one cycle section of the rectangular wave is shifted in the direction of being delayed by 2 / 3 of one clock. Since the start part of the one-cycle section is shifted in the direction of being delayed by about 1 / 3, the one cycle of the rectangular wave in this section has also become 1 / 3 longer than one clock in total.

[0060] And, since the start part of the third rectangular wave is shifted in the direction of being delayed by 2 / 3 clock, the section with a period of 334 ns also becomes about 333.3 ns.

[0061] Thus, it can be seen that by the operation of the correction determination unit 22, the generation of jitter for one clock is suppressed, and each section of one cycle becomes substantially the same period.

[0062] (Summary of Effects) In the example according to the first embodiment, an accumulator 11 that adds and outputs a phase addition value Δθ for each clock according to the input period setting, a waveform memory 12 that stores waveform data of the digitized waveform output, and reads waveform data from the waveform memory 12 for each clock. Based on the read waveform data, at the steep change points of the waveform data correction A data processing unit 13 that outputs the processed waveform data, a DA converter 14 that converts the processed waveform data into an analog signal, and a low-pass filter 15 that smoothes and outputs the analog signal from the DA converter 14 are provided. By using the waveform generation circuit 10, the data of two consecutive points at the steep change points of the waveform data and the fractional part D of the accumulator 11 U And the waveform data according to the phase addition value Δθ correction Are configured to be processed. As a result, an excellent effect of suppressing jitter is exhibited even at the steep change points of the waveform where jitter is likely to appear significantly in the conventional DDS method.

[0063] 〔Second Embodiment〕 The second embodiment is an example in the case where the number of waveform data points stored in the waveform memory 12 is limited to a number that satisfies the conditions according to the setting of the output period.

[0064] The bit addition calculation value Δθ can be obtained by (Equation 1-1). Here, in the case of the example according to the first embodiment, the period setting T O The smaller it becomes, in other words, the higher the frequency of the output waveform, the larger the value of the bit addition calculation value Δθ, and it may exceed 1.

[0065] In such a case, the waveform data stored in the waveform memory 12 may have an address specified as the output of the waveform memory 12 exceeding 1. Therefore, adjacent waveform data is not used sequentially, and the output waveform is generated by the waveform data at non - consecutive addresses. Even in such a case, correction is performed using the waveform data used, and waveform output is performed. However, in the example of the waveform generation circuit 10 according to the present embodiment, it is to ensure that correction is reliably performed between adjacent waveform data.

[0066] To achieve this, first, as the number of waveform data points, a positive integer N that satisfies the following (Equation 2-1) is determined in advance.

[0067]

Equation

[0068] And the bit addition calculation value Δθ is calculated by the following (Equation 2-2).

[0069]

Equation

[0070] These operations can be easily obtained from known values. As the data written into the waveform memory 12, it is generated by spline approximation, linear approximation, moving average of data in the included interval, or other function approximations based on the data prepared in advance as arbitrary waveform data.

[0071] In this way, the waveform data corresponding to N points obtained by equally dividing one period into N parts can be generated, and the generated waveform data can be written into the waveform memory 12. The number of data points of the waveform data to be written into the waveform memory 12 is limited so that the phase addition value Δθ becomes 1 or less. Then, the accumulator 11 performs phase addition so as to return to 0 when it exceeds N. By such processing, it is possible to perform an operation using continuous adjacent waveform data, and it becomes possible to obtain a stable waveform for each period.

[0072] Incidentally, if N is selected so that Δθ approaches 1, the number of data points for generating the output waveform of one period increases, the quality of the waveform improves, and it can be said that the data point number N is more suitably selected. Further, a waveform data generation unit (not shown) that generates waveform data with the number of data points limited so that the phase addition value Δθ becomes 1 or less and writes the waveform data into the waveform memory 12 is provided inside or outside the waveform generation circuit 10.

[0073] (Summary of effects) In the example according to the second embodiment, as data to be written into the waveform memory 12, an example of generation by spline approximation, linear approximation, moving average of data in an included section, or other function approximation based on data prepared in advance as arbitrary waveform data according to the period setting was described. By such processing, as the waveform data to be written into the waveform memory 12, by adopting a configuration including waveform data with the number of data points limited so that the phase addition value Δθ becomes 1 or less, in addition to the excellent effect of suppressing jitter, it is possible to perform an operation using continuous adjacent waveform data, and it is possible to obtain a stable waveform for each period, thus demonstrating an excellent effect.

[0074] [Third Embodiment] The third embodiment is an example of the waveform generation circuit 10 configured in such a manner that a clock signal for reading waveform data from the waveform memory 12 is supplied from the data processing unit 13 and the address is not specified from the accumulator 11.

[0075] FIG. 7 shows an example of the waveform generation circuit 10 according to the third embodiment. The waveform generation circuit 10 includes an accumulator 11, a waveform memory 12, a data processing unit 13, a DA converter 14, and a low-pass filter 15. In the case of the example of the second embodiment in which waveform data is sequentially read from adjacent data, the waveform memory 12 does not necessarily need to be a memory capable of random access that outputs data at a specified address, and a sequential memory may be used.

[0076] This embodiment is a configuration example in such a case, and the data processing unit 13 performs a process of generating a clock for the waveform memory that sequentially outputs waveform data each time the integer part of the output value from the accumulator 11 increases. Based on this clock for the waveform memory, waveform data is output from the waveform memory 12. If the number of data points of the waveform data is N points, a signal for resetting to perform sequential memory reading from the beginning at a timing exceeding N may be added. By doing so, the sequential memory does not necessarily need to use all the memories.

[0077] With the recent increase in processing speed, a configuration in which a sequential memory capable of high-speed processing at low cost can be used can also achieve the effects of increasing processing speed and reducing costs. In addition, there are some sequential memories that achieve high-speed operation by collectively reading data of multiple words by burst access. In the case of such an operation, since a plurality of adjacent waveform data is read in advance, it is convenient for generating waveform processing data based on the waveform data, and it can be said to be a suitable configuration example.

[0078] (Summary of effects) In the example according to the third embodiment, the waveform memory 12 does not necessarily have to be a memory capable of random access that outputs data at a specified address. As a configuration example that can also be implemented with a sequential memory, a waveform generation circuit 10 configured with a data processing unit 13 is described such that the reading of waveform data from the waveform memory 12 is performed using a clock for the waveform memory generated according to the addition of the output integer part from the accumulator 11. By such processing, in addition to the excellent effect of suppressing jitter, the effects of speeding up the processing and reducing costs, such as being able to use a sequential memory that enables high-speed processing at low cost, can also be obtained.

[0079] 〔Fourth Embodiment〕 The fourth embodiment is an example of an embodiment in which specific information that prescribes in advance whether output correction is necessary is incorporated into the waveform data stored in the waveform memory 12.

[0080] FIG. 8 is a configuration example of a correction determination unit 22 according to the fourth embodiment. The correction determination unit 22 determines whether to correct the waveform processing data output to the DA converter 14 based on the information of the bits for the signal to be corrected that are not used as amplitude data for waveform output among the waveform data output from the waveform memory 12. When it is determined that correction is necessary, a correction coefficient processing unit 41 that calculates a correction coefficient k that becomes a correction command signal and outputs this correction coefficient k to the data generation unit 21 is provided.

[0081] In this embodiment, as waveform data, an arbitrary bit, for example, the least significant bit, is used as the bit for the signal to be corrected. This information is not used as the amplitude data of the waveform output. If this bit is 1, based on the correction coefficient k calculated by the correction coefficient processing unit 41, the data generation unit 21 corrects the amplitude data of the waveform output. If it is 0, the data generation unit 21 outputs the amplitude data of the waveform output as it is. In the data processing unit 13, according to the presence or absence of this information, by specifying the part of the waveform where correction is to be performed, it is possible to obtain the difference between the data and perform correction on an arbitrary waveform part without performing a magnitude determination with respect to the threshold value. The data other than the bit for the signal to be corrected is used as the amplitude data of the waveform output, and data processing according to the presence or absence of correction is performed, and the processed amplitude data is output to the DA converter 14.

[0082] (Summary of effects) In the example according to the fourth embodiment, as an example of the embodiment in which specific information specifying the necessity of output correction is incorporated into the waveform data, information on the bit for the signal to be corrected, which is the information on the necessity of correction, is added to the waveform data read from the waveform memory 12. Based on this information on the bit for the signal to be corrected, the waveform generation circuit 10 constituting the data processing unit 13 is described so as to determine whether or not to perform correction With such a configuration of the waveform data, an excellent effect of suppressing jitter can be surely obtained at the intended waveform part.

[0083] 〔Fifth embodiment〕 The fifth embodiment is another example of the embodiment in which specific information specifying the necessity of output correction is incorporated into the waveform data stored in the waveform memory 12.

[0084] FIG. 9 is a configuration example of the correction determination unit 22 according to the fifth embodiment. The correction determination unit 22 determines whether to perform correction processing on the waveform processing data output to the DA converter 14 based on information on the bit string for the signal to be corrected that can also be used as amplitude data for waveform output among the waveform data output from the waveform memory 12. When it is determined that correction is necessary, the correction coefficient processing unit 41 calculates a correction coefficient k that becomes a correction command signal and outputs this correction coefficient k to the data generation unit 21.

[0085] In this embodiment, instead of securing specific bits of the waveform data as bits for the signal to be corrected, for example, when the number of bits of the waveform data is 16 bits, a specific value of the lower 6 bits is defined as the bit pattern for the signal to be corrected. Specifically, if the lower 6 bits are all in the pattern of "111111", the correction coefficient processing unit 41 determines that this data part is a part to be corrected, and based on the correction coefficient k calculated by the correction coefficient processing unit 41, the data generation unit 21 corrects the amplitude data of the waveform output. For other patterns, the data generation unit 21 outputs the amplitude data of the waveform output as it is. Here, the upper 10 bits are used as the amplitude data of the output waveform, but the number of these upper and lower bits is arbitrary and is not limited to these values.

[0086] In an example like this embodiment, it is necessary to ensure that the values defined for the bit string for the signal to be corrected by a plurality of lower bits are not used in the waveform data of parts that do not require correction. Therefore, when generating the waveform data to be written into the waveform memory 12, the amplitude data that happens to correspond to this pattern in parts that do not require correction may be processed to be set as a value of +1 or -1 with respect to the defined value.

[0087] By adopting such a form, it becomes possible to configure the waveform generation circuit 10 that uses waveform data including information on whether correction is required without substantially reducing the resolution in the amplitude direction.

[0088] (Summary of Effects) In the example according to the fifth embodiment, as an example of another embodiment in which specific information that prescribes in advance the necessity of output correction is inserted into the waveform data, correction The waveform generation circuit 10 in which amplitude data serving as digitized information of waveform output is also written in the data portion of the bits for the signal to be corrected, which is information on whether correction is necessary, in the waveform data that does not need to be performed correction was described. With such a configuration of waveform data, an excellent effect of suppressing jitter can be surely obtained at the intended waveform part with almost no sacrifice of waveform resolution.

[0089] 〔Sixth Embodiment〕 The sixth embodiment is yet another example of an embodiment in which specific information that prescribes in advance the necessity of output correction is inserted into the waveform data stored in the waveform memory 12.

[0090] This is an embodiment in which data in the time axis direction instead of the amplitude direction is added to the remaining data portion to be embedded in the waveform data having the bit pattern for the signal to be corrected in the fifth embodiment.

[0091] For example, assuming that the number of bits of the waveform data is 16 bits, a specific value of the lower 6 bits is defined as the bit pattern for the signal to be corrected. Specifically, for example, when the lower 6 bits are all in the pattern of "111111", the data used for the remaining 10 bits is, for example, data that designates the position on the time axis between two pieces of data such that the midpoint of the amplitude data of the waveform outputs before and after having the signal to be corrected passes through. Note that using the midpoint is a preferred example, but it is an arbitrary design matter which position, such as the 1:2 or 3:1 position between two amplitude data, is set to pass through.

[0092] Correction of waveform data can be achieved by function approximation such as linear approximation, spline approximation, or sinusoidal waveforms as in the example of the first embodiment. Further, in the configuration example of the data generation unit 21 shown in FIG. 5, the value of the correction coefficient k may be obtained by performing an inverse function operation so that values based on these interpolations or approximations can be obtained. By determining the function used for correction, the two end points within the correction interval, and the time positions of the points passing therebetween, the corrected waveform data at the clock output time when the output waveform is updated can be generated by the inverse function operation.

[0093] Linear approximation is a type of linear approximation and can be realized with relatively simple arithmetic processing. However, for arithmetic operations of function approximation such as spline approximation and sinusoidal waveforms including such interpolation, a function table may be prepared, and the value of the function may be output in a form based on the value according to the phase addition value Δθ. It is also possible to avoid directly performing heavy arithmetic operations such as power operations and trigonometric function operations (time-consuming operations), which can be said to be a preferable configuration example.

[0094] (Summary of effects) In the example according to the sixth embodiment, as another example of an embodiment in which specific information specifying the necessity of output correction is incorporated into the waveform data, correction The waveform generation circuit 10 has been described, in which for the waveform data that needs to be processed, information specifying the time position between amplitude data, which is the digitized information of the waveform output in the waveform data before and after including that waveform data, is written in the remaining data part other than the information of the bits for the signal to be corrected. With such a configuration of the waveform data, an excellent effect of suppressing jitter can be surely obtained at the intended waveform part without accompanying a decrease in waveform resolution.

[0095] (Overall summary) In the example according to the first embodiment, an accumulator 11 that adds and outputs the phase addition value Δθ for each clock according to the input period setting, a waveform memory 12 that stores the waveform data of the digitized waveform output, and the waveform data is read from the waveform memory 12 for each clock. Based on the read waveform data, at the abrupt change points of the waveform datacorrection A waveform generation circuit 10 including a data processing unit 13 that outputs the generated waveform data, is configured such that, for two consecutive points of data at a rapid change point of the waveform data and the fractional part D of the accumulator 11 U and the phase addition value Δθ, the waveform data is correction processed. By doing so, even at a rapid change point of a waveform where jitter is likely to appear significantly in the conventional DDS method, an excellent effect of suppressing jitter is exhibited.

[0096] In the example according to the second embodiment, as the data written to the waveform memory 12, an example of generation by spline approximation, linear approximation, moving average of data in an included section, or other function approximation based on data prepared in advance as arbitrary waveform data according to the period setting was described. By such processing, as the waveform data written to the waveform memory 12, by adopting a configuration including waveform data limited to a number of data points such that the phase addition value Δθ is 1 or less, in addition to the excellent effect of suppressing jitter, it is possible to perform an operation using consecutive adjacent waveform data, and an excellent effect of being able to obtain a stable waveform for each period is exhibited.

[0097] In the example according to the third embodiment, as the waveform memory 12, it is not necessary to be a memory capable of random access that outputs data at a specified address. As a configuration example that can also be implemented with a sequential memory, a waveform generation circuit 10 configured such that the data processing unit 13 reads waveform data from the waveform memory 12 using a waveform memory clock generated according to the addition of the integer part of the output from the accumulator 11 was described. By such processing, in addition to the excellent effect of suppressing jitter, an effect of speeding up the processing and reducing costs, such that an inexpensive and high-speed processing-capable sequential memory can be used, is also obtained.

[0098] In the example according to the fourth embodiment, as an example of the embodiment in which specific information that defines in advance the necessity of output correction is incorporated into the waveform data, information of bits for a signal to be corrected, which is correction necessity information, is added to the waveform data read from the waveform memory 12, and based on the information of the bits for the signal to be corrected, the waveform generation circuit 10 that constitutes the data processing unit 13 is configured to determine whether to correction perform the operation. With such a configuration of the waveform data, an excellent effect of suppressing jitter can be surely obtained at the intended waveform part.

[0099] In the example according to the fifth embodiment, as another example of the embodiment in which specific information that defines in advance the necessity of output correction is incorporated into the waveform data, correction in the waveform data that does not need to perform the operation, amplitude data that is quantization information of the waveform output is also written in the data part of the information of the bits for the signal to be corrected, which is correction necessity information, of the waveform generation circuit 10. With such a configuration of the waveform data, an excellent effect of suppressing jitter can be surely obtained at the intended waveform part, and the waveform resolution can be obtained with almost no sacrifice.

[0100] In the example according to the sixth embodiment, as yet another example of the embodiment in which specific information that defines in advance the necessity of output correction is incorporated into the waveform data, correction in the waveform data that needs to perform the operation, information that designates the time position between the amplitude data, which is quantization information of the waveform output, in the waveform data before and after including the waveform data, is written in the remaining data part other than the information of the bits for the signal to be corrected, of the waveform generation circuit 10. With such a configuration of the waveform data, an excellent effect of suppressing jitter can be surely obtained at the intended waveform part, and the effect can be obtained without accompanying a decrease in waveform resolution.

[0101] These can be said to show the superiority such as jitter reduction over the conventional technology of the present invention.

[0102] The above describes the most preferred embodiments of the present invention and the like, but the present invention is not limited to the above description. Based on the gist of the invention described in the claims or disclosed in the embodiments for carrying out the invention, various modifications and changes are possible for those skilled in the art. Such modifications and changes are included in the scope of the present invention.

Industrial Applicability

[0103] The waveform generation circuit of the present invention can be used for, for example, the following applications and is beneficial. (1) Generation of test signals for operation tests of electronic circuits (2) Simulation signal source for standard signals conforming to various standards (3) Signal source for modulation in the communication field and the like

Explanation of Signs

[0104] 11 Accumulator 12 Waveform Memory 13 Data Processing Unit 14 DA Converter 15 LPF (Low Pass Filter) 21 Data Generation Unit 22 Correction Judgment Unit 31 Delay Unit 32 Subtraction Unit 33 Multiplication Unit 34 Addition Unit 41 Correction Coefficient Processing Unit

Claims

1. A waveform generation circuit using the DDS method, comprising: an accumulator that adds and outputs a phase addition value for each clock; a waveform memory that stores waveform data of a digitized waveform output and uses the upper bits of the output of the accumulator as an address input; a data processing unit that takes as inputs the output of the accumulator and the data output of the waveform memory, reads out the waveform data from the waveform memory for each clock, and generates and outputs waveform processing data corrected at a rapid change point of the waveform data based on the lower bits other than the upper bits of the read waveform data and the output of the accumulator; a DA converter that takes the waveform processing data as a data input and converts the data input into an analog signal; a low-pass filter that smooths the analog signal output waveform from the DA converter and outputs it as an output signal; and is characterized by reducing jitter.

2. Let the sum-of-bits addition value be Δθ, and let the value obtained by replacing the data of the lower bits with values below the decimal point be D Ｕ When this is the case, the correction coefficient k is k = (1 - D Ｕ ) / Δθ, Let the period of the clock be T ＡＣＬＫ , and the waveform data at time T Ｘ be Da(T Ｘ ), and the waveform data at the sampling time immediately before that be Da(T Ｘ - T ＡＣＬＫ ). When this is the case, based on the correction coefficient k, the data generation unit included in the data processing unit outputs data of k·Da(T Ｘ ) + (1 - k)·Da(T Ｘ - T ＡＣＬＫ ). The waveform generation circuit according to claim 1, characterized in that.

3. Let the period of the output signal be T Ｏ and the period of the clock be T ＡＣＬＫ When this is the case, a positive integer N is selected such that N ≤ T Ｏ / T ＡＣＬＫ is satisfied, wherein the number of data points of the waveform data is N, the N pieces of waveform data are written into the waveform memory, When the bit addition value is Δθ, Δθ is expressed as Δθ = N · T ＡＣＬＫ / T ｏ and its value is 1 or less, the value of the upper bits of the output of the accumulator returns to 0 when it exceeds N, and the operation is based on the continuous adjacent waveform data. The waveform generation circuit according to claim 1 or 2.

4. A waveform generation circuit using the DDS method, comprising: an accumulator that adds and outputs a phase addition value for each clock; a waveform memory formed by a sequential memory that stores waveform data of a digitized waveform output; a configuration that generates a waveform memory clock supplied to the waveform memory each time the value of the upper bits of the output of the accumulator increases, and supplies the waveform memory clock to the waveform memory, a configuration that supplies a reset signal to the waveform memory when the value of the upper bits of the output of the accumulator exceeds the number of data points of the waveform data, and a configuration of a data processing unit that takes as inputs the output of the accumulator and the data output of the waveform memory, reads out the waveform data from the waveform memory for each waveform memory clock, and generates and outputs waveform processing data corrected at a rapid change point of the waveform data based on the lower bits other than the upper bits of the read waveform data and the output of the accumulator; a DA converter that takes the waveform processing data as a data input and converts the data input into an analog signal; A low-pass filter that smoothes the analog signal output waveform from the DA converter and outputs the signal, is provided, and a waveform generation circuit characterized by reducing jitter. **Claim 5** Add correction necessity information to the waveform data read from the waveform memory, The data processing unit is configured to determine whether to correct the waveform data based on the correction necessity information, and the waveform generation circuit according to any one of claims 1 to 4, characterized in that. **Claim 6** In the waveform data that does not need to be corrected, quantization information of the waveform output is also written in the data part of the correction necessity information, and the waveform generation circuit according to claim 5, characterized in that.

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